CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238 Data sheet acquired from Harris Semiconductor SCHS147I High-Speed CMOS Logic 3- to 8-Line Decoder/ Demultiplexer Inverting and Noninverting October 1997 - Revised August 2004 Features Ordering Information • Select One Of Eight Data Outputs TEMP. RANGE Active Low for 138, Active High for 238 [ /Title PART NUMBER (oC) PACKAGE • l/O Port or Memory Selector (CD74 CD54HC138F3A -55 to 125 16 Ld CERDIP HC138 • Three Enable Inputs to Simplify Cascading CD54HC238F3A -55 to 125 16 Ld CERDIP , • Typical Propagation Delay of 13 ns at VCC = 5 V, CD74 CL = 15 pF, TA = 25oC CD54HCT138F3A -55 to 125 16 Ld CERDIP HCT13 • Fanout (Over Temperature Range) CD54HCT238F3A -55 to 125 16 Ld CERDIP 8, - Standard Outputs. . . . . . . . . . . . . . .10 LSTTL Loads CD74HC138E -55 to 125 16 Ld PDIP CD74 - Bus Driver Outputs . . . . . . . . . . . . .15 LSTTL Loads CD74HC138M -55 to 125 16 Ld SOIC HC238 • Wide Operating Temperature Range . . .-55oC to 125oC , CD74HC138MT -55 to 125 16 Ld SOIC • Balanced Propagation Delay and Transition Times CD74 CD74HC138M96 -55 to 125 16 Ld SOIC • Significant Power Reduction Compared to LSTTL HCT23 Logic ICs CD74HC238E -55 to 125 16 Ld PDIP 8) • HC Types CD74HC238M -55 to 125 16 Ld SOIC /Sub- - 2 V to 6 V Operation ject CD74HC238MT -55 to 125 16 Ld SOIC - High Noise Immunity: NIL = 30%, NIH = 30% of VCC (High at VCC = 5 V CD74HC238M96 -55 to 125 16 Ld SOIC Speed • HCT Types CD74HC238NSR -55 to 125 16 Ld SOP - 4.5-V to 5.5-V Operation CD74HC238PW -55 to 125 16 Ld TSSOP - Direct LSTTL Input Logic Compatibility, VIL= 0.8 V (Max), VIH = 2 V (Min) CD74HC238PWR -55 to 125 16 Ld TSSOP - CMOS Input Compatibility, Il≤ 1µA at VOL, VOH CD74HC238PWT -55 to 125 16 Ld TSSOP Description CD74HCT138E -55 to 125 16 Ld PDIP The’HC138,’HC238,’HCT138,and’HCT238arehigh-speed CD74HCT138M -55 to 125 16 Ld SOIC silicon-gate CMOS decoders well suited to memory address CD74HCT138MT -55 to 125 16 Ld SOIC decoding or data-routing applications. Both circuits feature low power consumption usually associated with CMOS CD74HCT138M96 -55 to 125 16 Ld SOIC circuitry, yet have speeds comparable to low-power Schottky TTL logic. Both circuits have three binary select inputs (A0, CD74HCT238E -55 to 125 16 Ld PDIP A1,andA2).Ifthedeviceisenabled,theseinputsdetermine CD74HCT238M -55 to 125 16 Ld SOIC which one of the eight normally high outputs of the HC/HCT138 series go low or which of the normally low CD74HCT238M96 -55 to 125 16 Ld SOIC outputs of the HC/HCT238 series go high. NOTE: Whenordering,usetheentirepartnumber.Thesuffixes96 Twoactivelowandoneactivehighenables(E1,E2,andE3) andRdenotetapeandreel.ThesuffixTdenotesasmall-quantity are provided to ease the cascading of decoders. The reel of 250. decoder’s eight outputs can drive ten low-power Schottky TTL equivalent loads. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2004, Texas Instruments Incorporated 1

CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238 Pinout Functional Diagram HC/HCTHC/HCT CD54HC138, CD54HCT138, CD54HC238, CD54HCT238 238 138 (CERDIP) 1 15 CD74HC138, CD74HCT138, CD74HCT238 A0 Y0 Y0 (PDIP, SOIC) 2 14 CD74HC238 A1 Y1 Y1 (PDIP, SOIC, SOP, TSSOP) 3 13 TOP VIEW A2 Y2 Y2 12 Y3 Y3 A0 1 16 VCC 4 11 A1 2 15 Y0 (Y0) E1 Y4 Y4 5 10 A2 3 14 Y1 (Y1) E2 Y5 Y5 E1 4 13 Y2 (Y2) 6 9 E3 Y6 Y6 E2 5 12 Y3 (Y3) 7 E3 6 11 Y4 (Y4) Y7 Y7 (Y7) Y7 7 10 Y5 (Y5) GND 8 9 Y6 (Y6) Signal names in parentheses are for ’HC138 and ’HCT138. TRUTH TABLE ’HC138, ’HCT138 INPUTS ENABLE ADDRESS OUTPUTS E3 E2 E1 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 X X H X X X H H H H H H H H L X X X X X H H H H H H H H X H X X X X H H H H H H H H H L L L L L L H H H H H H H H L L L L H H L H H H H H H H L L L H L H H L H H H H H H L L L H H H H H L H H H H H L L H L L H H H H L H H H H L L H L H H H H H H L H H H L L H H L H H H H H H L H H L L H H H H H H H H H H L H = High Voltage Level, L = Low Voltage Level, X = Don’t Care TRUTH TABLE ’HC238, ’HCT238 INPUTS ENABLE ADDRESS OUTPUTS E3 E2 E1 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 X X H X X X L L L L L L L L L X X X X X L L L L L L L L X H X X X X L L L L L L L L H L L L L L H L L L L L L L H L L L L H L H L L L L L L H L L L H L L L H L L L L L H L L L H H L L L H L L L L H L L H L L L L L L H L L L H L L H L H L L L L L H L L H L L H H L L L L L L L H L H L L H H H L L L L L L L H H = High Voltage Level, L = Low Voltage Level, X = Don’t Care 2

CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Package Thermal Impedance,θJA(see Note 1): DC Input Diode Current, IIK E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67oC/W For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73oC/W DC Output Diode Current, IOK NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64oC/W For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 108oC/W DC Output Source or Sink Current per Output Pin, IO Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC DC VCC or Ground Current, ICC orIGND. . . . . . . . . . . . . . . . . .±50mA Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . .-55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION:Stressesabovethoselistedin“AbsoluteMaximumRatings”maycausepermanentdamagetothedevice.Thisisastressonlyrating,andoperation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS 25oC -40oC TO 85oC -55oCTO125oC VCC PARAMETER SYMBOL VI(V) IO(mA) (V) MIN TYP MAX MIN MAX MIN MAX UNITS HC TYPES High Level Input VIH - - 2 1.5 - - 1.5 - 1.5 - V Voltage 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V Low Level Input VIL - - 2 - - 0.5 - 0.5 - 0.5 V Voltage 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V High Level Output VOH VIHorVIL -0.02 2 1.9 - - 1.9 - 1.9 - V Voltage -0.02 4.5 4.4 - - 4.4 - 4.4 - V CMOS Loads -0.02 6 5.9 - - 5.9 - 5.9 - V High Level Output - - - - - - - - - V Voltage -4 4.5 3.98 - - 3.84 - 3.7 - V TTL Loads -5.2 6 5.48 - - 5.34 - 5.2 - V Low Level Output VOL VIHorVIL 0.02 2 - - 0.1 - 0.1 - 0.1 V Voltage 0.02 4.5 - - 0.1 - 0.1 - 0.1 V CMOS Loads 0.02 6 - - 0.1 - 0.1 - 0.1 V Low Level Output - - - - - - - - - V Voltage 4 4.5 - - 0.26 - 0.33 - 0.4 V TTL Loads 5.2 6 - - 0.26 - 0.33 - 0.4 V Input Leakage II VCC or - 6 - - ±0.1 - ±1 - ±1 µA Current GND Quiescent Device ICC VCC or 0 6 - - 8 - 80 - 160 µA Current GND 3

CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238 DC Electrical Specifications (Continued) TEST CONDITIONS 25oC -40oC TO 85oC -55oCTO125oC VCC PARAMETER SYMBOL VI(V) IO(mA) (V) MIN TYP MAX MIN MAX MIN MAX UNITS HCT TYPES High Level Input VIH - - 4.5 to 2 - - 2 - 2 - V Voltage 5.5 Low Level Input VIL - - 4.5 to - - 0.8 - 0.8 - 0.8 V Voltage 5.5 High Level Output VOH VIHorVIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V Voltage CMOS Loads High Level Output -4 4.5 3.98 - - 3.84 - 3.7 - V Voltage TTL Loads Low Level Output VOL VIHorVIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V Voltage CMOS Loads Low Level Output 4 4.5 - - 0.26 - 0.33 - 0.4 V Voltage TTL Loads Input Leakage II VCCand 0 5.5 - ±0.1 - ±1 - ±1 µA Current GND Quiescent Device ICC VCC or 0 5.5 - - 8 - 80 - 160 µA Current GND Additional Quiescent ∆ICC VCC - 4.5 to - 100 360 - 450 - 490 µA Device Current Per (Note 2) -2.1 5.5 Input Pin: 1 Unit Load NOTE: 2. For dual-supply systems, theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS A0-A2 1.5 E1,E2 1.25 E3 1 NOTE: UnitLoadis∆ICClimitspecifiedinDCElectricalTable,e.g., 360µA max at 25oC. Switching SpecificationsInput tr, tf = 6ns -40oC TO 25oC 85oC -55oC TO 125oC TEST PARAMETER SYMBOL CONDITIONS VCC(V) MIN TYP MAX MIN MAX MIN MAX UNITS HC TYPES Propagation Delay tPLH,tPHL CL= 50pF 2 - - 150 - 190 - 225 ns Address to Output 4.5 - - 30 - 38 - 45 ns CL= 15pF 5 - 13 - - - - - ns CL= 50pF 6 - - 26 - 33 - 38 ns 4

CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238 Switching SpecificationsInput tr, tf = 6ns (Continued) -40oC TO 25oC 85oC -55oC TO 125oC TEST PARAMETER SYMBOL CONDITIONS VCC(V) MIN TYP MAX MIN MAX MIN MAX UNITS Enable to Output tPLH,tPHL CL= 50pF 2 - - 150 - 190 - 265 ns HC/HCT138 4.5 - - 30 - 38 - 53 ns 6 - - 26 - 33 - 45 ns Output Transition Time tTLH, tTHL CL= 50pF 2 - - 75 - 95 - 110 ns (Figure 1) 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns Power Dissipation CPD CL= 15pF 5 - 67 - - - - - pF Capacitance (Notes 3, 4) Input Capacitance CIN - - - - 10 - 10 - 10 pF HCT TYPES Propagation Delay Address to Output tPLH, tPHL CL= 50pF 4.5 - - 35 - 44 - 53 ns CL= 15pF 5 - 14 - - - - - ns Enable to Output tPLH, tPHL CL= 50pF 4.5 - - 35 - 44 - 53 ns HC/HCT138 Enable to Output tPLH,tPHL CL= 15pF 4.5 - - 40 - 50 - 60 ns HC/HCT238 Output Transition Time tTLH, tTHL CL= 50pF 4.5 - - 15 - 19 - 22 ns (Figure 2) Power Dissipation CPD CL= 15pF 5 - 67 - - - - - pF Capacitance (Notes 3, 4) Input Capacitance CIN - - - - 10 - 10 - 10 pF NOTES: 3. CPD is used to determine the dynamic power consumption, per gate. 4. PD = VCC2 fi(CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. Test Circuits and Waveforms tr = 6ns tf = 6ns tr = 6ns tf = 6ns 90% VCC 2.7V 3V INPUT 50% INPUT 1.3V 10% GND 0.3V GND tTHL tTLH tTHL tTLH 90% 90% 50% INVERTING 10% INVERTING 1.3V OUTPUT OUTPUT 10% tPHL tPLH tPHL tPLH FIGURE7. HCANDHCUTRANSITIONTIMESANDPROPAGA- FIGURE8. HCTTRANSITIONTIMESANDPROPAGATION TION DELAY TIMES, COMBINATION LOGIC DELAY TIMES, COMBINATION LOGIC 5

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 5962-8688401EA ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8688401EA CD54HC238F3A CD54HC138F ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type -55 to 125 CD54HC138F CD54HC138F3A ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type -55 to 125 8406201EA CD54HC138F3A CD54HC238F3A ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8688401EA CD54HC238F3A CD54HCT138F ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type -55 to 125 CD54HCT138F CD54HCT138F3A ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type -55 to 125 8550401EA CD54HCT138F3A CD54HCT238F3A ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8974501EA CD54HCT238F3A CD74HC138E ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -55 to 125 CD74HC138E & no Sb/Br) CD74HC138EE4 ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -55 to 125 CD74HC138E & no Sb/Br) CD74HC138M ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC138M & no Sb/Br) CD74HC138M96 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC138M & no Sb/Br) CD74HC138M96E4 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC138M & no Sb/Br) CD74HC138ME4 ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC138M & no Sb/Br) CD74HC138MT ACTIVE SOIC D 16 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC138M & no Sb/Br) CD74HC138MTG4 ACTIVE SOIC D 16 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC138M & no Sb/Br) CD74HC238E ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -55 to 125 CD74HC238E & no Sb/Br) CD74HC238EE4 ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -55 to 125 CD74HC238E & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) CD74HC238M ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC238M & no Sb/Br) CD74HC238M96 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC238M & no Sb/Br) CD74HC238M96E4 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC238M & no Sb/Br) CD74HC238MT ACTIVE SOIC D 16 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC238M & no Sb/Br) CD74HC238NSR ACTIVE SO NS 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC238M & no Sb/Br) CD74HC238PW ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HJ238 & no Sb/Br) CD74HC238PWR ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HJ238 & no Sb/Br) CD74HC238PWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HJ238 & no Sb/Br) CD74HC238PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HJ238 & no Sb/Br) CD74HC238PWT ACTIVE TSSOP PW 16 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HJ238 & no Sb/Br) CD74HCT138E ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -55 to 125 CD74HCT138E & no Sb/Br) CD74HCT138M ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT138M & no Sb/Br) CD74HCT138M96 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT138M & no Sb/Br) CD74HCT138M96G4 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT138M & no Sb/Br) CD74HCT238E ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -55 to 125 CD74HCT238E & no Sb/Br) CD74HCT238M ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT238M & no Sb/Br) CD74HCT238M96 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT238M & no Sb/Br) CD74HCT238M96G4 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT238M & no Sb/Br) Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) CD74HCT238PW ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HK238 & no Sb/Br) CD74HCT238PWR ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HK238 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF CD54HC138, CD54HC238, CD54HCT138, CD54HCT238, CD74HC138, CD74HC238, CD74HCT138, CD74HCT238 : Addendum-Page 3

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 •Catalog: CD74HC138, CD74HC238, CD74HCT138, CD74HCT238 •Automotive: CD74HC138-Q1, CD74HC138-Q1 •Military: CD54HC138, CD54HC238, CD54HCT138, CD54HCT238 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects •Military - QML certified for Military and Defense Applications Addendum-Page 4

PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) CD74HC138M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD74HC238M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD74HC238NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 CD74HC238PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 CD74HC238PWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 CD74HCT138M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD74HCT238M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD74HCT238PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) CD74HC138M96 SOIC D 16 2500 333.2 345.9 28.6 CD74HC238M96 SOIC D 16 2500 333.2 345.9 28.6 CD74HC238NSR SO NS 16 2000 367.0 367.0 38.0 CD74HC238PWR TSSOP PW 16 2000 367.0 367.0 35.0 CD74HC238PWT TSSOP PW 16 250 367.0 367.0 35.0 CD74HCT138M96 SOIC D 16 2500 333.2 345.9 28.6 CD74HCT238M96 SOIC D 16 2500 333.2 345.9 28.6 CD74HCT238PWR TSSOP PW 16 2000 367.0 367.0 35.0 PackMaterials-Page2

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PACKAGE OUTLINE PW0016A TSSOP - 1.2 mm max height SCALE 2.500 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 14X 0.65 16 1 2X 5.1 4.55 4.9 NOTE 3 8 9 0.30 B 4.5 16X 0.19 1.2 MAX 4.3 0.1 C A B NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.05 0.75 0.50 0 -8 DETA 20AIL A TYPICAL 4220204/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL UNDER SOLDER MASK OPENING METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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