CD54HC175, CD74HC175, CD54HCT175, CD74HCT175 Data sheet acquired from Harris Semiconductor SCHS160C High-Speed CMOS Logic Quad D-Type Flip-Flop with Reset August 1997 - Revised October 2003 Features advantageofstandardCMOSICsandtheabilitytodrive10 LSTTL devices. • Common Clock and Asynchronous Reset on Four D-Type Flip-Flops InformationattheDinputistransferredtotheQ,Qoutputson [ /Title the positive going edge of the clock pulse. All four Flip-Flops (CD74 • Positive Edge Pulse Triggering arecontrolledbyacommonclock(CP)andacommonreset (MR). Resetting is accomplished by a low voltage level HC175 • Complementary Outputs independent of the clock. All four Q outputs are reset to a , • Buffered Inputs logic 0 and all fourQ outputs to a logic 1. CD74 • Fanout (Over Temperature Range) Ordering Information HCT17 - Standard Outputs. . . . . . . . . . . . . . .10 LSTTL Loads 5) - Bus Driver Outputs . . . . . . . . . . . . .15 LSTTL Loads TEMP. RANGE /Sub- • Wide Operating Temperature Range . . .-55oC to 125oC PART NUMBER (oC) PACKAGE ject • Balanced Propagation Delay and Transition Times CD54HC175F3A -55 to 125 16 Ld CERDIP (High • Significant Power Reduction Compared to LSTTL Speed CD54HCT175F3A -55 to 125 16 Ld CERDIP Logic ICs CMOS CD74HC175E -55 to 125 16 Ld PDIP • HC Types Logic - 2V to 6V Operation CD74HC175M -55 to 125 16 Ld SOIC Quad - High Noise Immunity: NIL = 30%, NIH = 30% of VCC D- at VCC = 5V CD74HC175MT -55 to 125 16 Ld SOIC Type • HCT Types CD74HC175M96 -55 to 125 16 Ld SOIC Flip- - 4.5V to 5.5V Operation CD74HCT175E -55 to 125 16 Ld PDIP - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) CD74HCT175M -55 to 125 16 Ld SOIC - CMOS Input Compatibility, Il≤1µA at VOL, VOH CD74HCT175MT -55 to 125 16 Ld SOIC Description CD74HCT175M96 -55 to 125 16 Ld SOIC The’HC175and’HCT175arehighspeedQuadD-typeFlip- NOTE: Whenordering,usetheentirepartnumber.Thesuffix96 Flops with individual D-inputs and Q, Q complementary denotestapeandreel.ThesuffixTdenotesasmall-quantityreelof outputs.ThedevicesarefabricatedusingsilicongateCMOS 250. technology. They have the low power consumption Pinout CD54HC175, CD54HCT175 (CERDIP) CD74HC175, CD74HCT175 (PDIP, SOIC) TOP VIEW MR 1 16 VCC Q0 2 15 Q3 Q0 3 14 Q3 D0 4 13 D3 D1 5 12 D2 Q1 6 11 Q2 Q1 7 10 Q2 GND 8 9 CP CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated 1

CD54HC175, CD74HC175, CD54HCT175, CD74HCT175 Functional Diagram 4 D0 9 D Q 2 Q0 CP CP 3 MR 1 R Q Q0 5 D1 D Q 7 Q1 CP 6 R Q Q1 12 D2 D Q 10Q2 CP 11 R Q Q2 13 D3 D Q 15Q3 CP 14 R Q Q3 TRUTH TABLE INPUTS OUTPUTS RESET (MR) CLOCK CP DATA Dn Qn Qn L X X L H H ↑ H H L H ↑ L L H H L X Q0 Q0 H = High Voltage Level, L = Low Voltage Level, X = Don’t Care,↑ = Transition from Low to High Level, Q0=Level Before the Indicated Steady-State Input Conditions Were Established. Logic Diagram CL CL ONE OF FOUR F/F 4 (5, 12, 13) D p p 3( 6, 11, 14) Dn n n Qn CL CL CL CL p p n n CL CL CL CL 2( 7, 10, 15) Qn R CP 1 MR TO OTHER THREE F/F 8 16 9 CP TO OTHER THREE F/F GND VCC 2

CD54HC175, CD74HC175, CD54HCT175, CD74HCT175 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Thermal Resistance (Typical, Note 1) θJA (oC/W) DC Input Diode Current, IIK E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 67 For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 73 DC Output Diode Current, IOK Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC DC Output Source or Sink Current per Output Pin, IO Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA (SOIC - Lead Tips Only) DC VCC or Ground Current, ICC orIGND. . . . . . . . . . . . . . . . . .±50mA Operating Conditions Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . .-55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION:Stressesabovethoselistedin“AbsoluteMaximumRatings”maycausepermanentdamagetothedevice.Thisisastressonlyratingandoperation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS 25oC -40oC TO +85oC -55oC TO 125oC PARAMETER SYMBOL VI(V) IO(mA) VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS HC TYPES High Level Input VIH - - 2 1.5 - - 1.5 - 1.5 - V Voltage 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V Low Level Input VIL - - 2 - - 0.5 - 0.5 - 0.5 V Voltage 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V High Level Output VOH VIH or -0.02 2 1.9 - - 1.9 - 1.9 - V Voltage VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V CMOS Loads -0.02 6 5.9 - - 5.9 - 5.9 - V High Level Output -4 4.5 3.98 - - 3.84 - 3.7 - V Voltage -5.2 6 5.48 - - 5.34 - 5.2 - V TTL Loads Low Level Output VOL VIH or 0.02 2 - - 0.1 - 0.1 - 0.1 V Voltage VIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V CMOS Loads 0.02 6 - - 0.1 - 0.1 - 0.1 V Low Level Output 4 4.5 - - 0.26 - 0.33 - 0.4 V Voltage 5.2 6 - - 0.26 - 0.33 - 0.4 V TTL Loads Input Leakage II VCC or - 6 - - ±0.1 - ±1 - ±1 µA Current GND Quiescent Device ICC VCC or 0 6 - - 8 - 80 - 160 µA Current GND 3

CD54HC175, CD74HC175, CD54HCT175, CD74HCT175 DC Electrical Specifications (Continued) TEST CONDITIONS 25oC -40oC TO +85oC -55oC TO 125oC PARAMETER SYMBOL VI(V) IO(mA) VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS HCT TYPES High Level Input VIH - - 4.5 to 2 - - 2 - 2 - V Voltage 5.5 Low Level Input VIL - - 4.5 to - - 0.8 - 0.8 - 0.8 V Voltage 5.5 High Level Output VOH VIH or -0.02 4.5 4.4 - - 4.4 - 4.4 - V Voltage VIL CMOS Loads High Level Output -4 4.5 3.98 - - 3.84 - 3.7 - V Voltage TTL Loads Low Level Output VOL VIH or 0.02 4.5 - - 0.1 - 0.1 - 0.1 V Voltage VIL CMOS Loads Low Level Output 4 4.5 - - 0.26 - 0.33 - 0.4 V Voltage TTL Loads Input Leakage II VCC to 0 5.5 - - ±0.1 - ±1 - ±1 µA Current GND Quiescent Device ICC VCC or 0 5.5 - - 8 - 80 - 160 µA Current GND Additional Quiescent ∆ICC VCC - 4.5 to - 100 360 - 450 - 490 µA Device Current Per (Note 2) -2.1 5.5 Input Pin: 1 Unit Load NOTES: 2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS MR 1 CP 0.60 D 0.15 NOTE: Unit Load is∆ICClimit specified in DC Electrical Specifications table, e.g. 360µA max at 25oC. Prerequisite For Switching Specifications 25oC -40oC TO 85oC -55oCTO125oC TEST VCC PARAMETER SYMBOL CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX UNITS HC TYPES Clock Pulse Width tw - 2 80 - - 100 - 120 - ns 4.5 16 - - 20 - 24 - ns 6 14 - - 17 - 20 - ns MR Pulse Width tw - 2 80 - - 100 - 120 - ns 4.5 16 - - 20 - 24 - ns 6 14 - - 17 - 20 - ns 4

CD54HC175, CD74HC175, CD54HCT175, CD74HCT175 Prerequisite For Switching Specifications (Continued) 25oC -40oC TO 85oC -55oCTO125oC TEST VCC PARAMETER SYMBOL CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX UNITS Setup Time, Data to Clock tSU - 2 80 - - 100 - 120 - ns 4.5 16 - - 20 - 24 - ns 6 14 - - 17 - 20 - ns Hold Time, Data to Clock tH - 2 5 - - 5 - 5 - ns 4.5 5 - - 5 - 5 - ns 6 5 - - 5 - 5 - ns Removal Time,MR to Clock tREM - 2 5 - - 5 - 5 - ns 4.5 5 - - 5 - 5 - ns 6 5 - - 5 - 5 - ns Clock Frequency fMAX - 2 6 - - 5 - 4 - MHz 4.5 30 - - 25 - 20 - MHz 6 35 - - 29 - 23 - MHz HCT TYPES Clock Pulse Width tw - 4.5 20 - - 25 - 30 - ns MR Pulse Width tw - 4.5 20 - - 25 - 30 - ns Setup Time Data to Clock tSU - 4.5 20 - - 25 - 30 - ns Hold Time Data to Clock tH - 4.5 5 - - 5 - 5 - ns Removal TimeMR to Clock tREM - 4.5 5 - - 5 - 5 - ns Clock Frequency fMAX - 4.5 25 - - 20 - 16 - MHz Switching Specifications Input tr, tf = 6ns -55oC TO 25oC -40oC TO 85oC 125oC TEST PARAMETER SYMBOL CONDITIONS VCC (V) TYP MAX MAX MAX UNITS HC TYPES PropagationDelay,Clockto tPLH, tPHL CL= 50pF 2 - 175 220 265 ns Q orQ 4.5 - 35 44 53 ns 6 - 30 37 45 ns CL= 15pF 5 14 - - - ns Propagation Delay, tPLH, tPHL CL= 50pF 2 - 175 220 265 ns MR to Q orQ 4.5 - 35 44 53 ns 6 - 30 37 45 ns CL= 15pF 5 14 - - - ns Output Transition Times tTLH, tTHL CL= 50pF 2 - 75 95 110 ns 4.5 - 15 19 22 ns 6 - 13 16 19 ns Input Capacitance CIN - - - 10 10 10 pF Power Dissipation CPD - 5 65 - - - pF Capacitance (Notes 3, 4) 5

CD54HC175, CD74HC175, CD54HCT175, CD74HCT175 Switching Specifications Input tr, tf = 6ns (Continued) -55oC TO 25oC -40oC TO 85oC 125oC TEST PARAMETER SYMBOL CONDITIONS VCC (V) TYP MAX MAX MAX UNITS HCT TYPES Propagation Delay, tPLH, tPHL CL= 50pF 4.5 - 33 41 50 ns Clock to Q orQ CL= 15pF 5 13 - - - ns Propagation Delay, tPLH, tPHL CL= 50pF 4.5 - 35 44 53 ns MR to Q orQ CL= 15pF 5 17 - - - ns Output Transition Times tTLH, tTHL CL= 50pF 4.5 - 15 19 22 ns Input Capacitance CIN - - - 10 10 10 pF Power Dissipation CPD - 5 67 - - - pF Capacitance (Notes 3, 4) NOTES: 3. CPD is used to determine the dynamic power consumption, per flip-flop. 4. PD=VCC2fi+∑(CLVCC2+fO)wherefi=InputFrequency,fO=InputFrequency,CL=OutputLoadCapacitance,VCC=SupplyVoltage. Test Circuits and Waveforms trCL tfCL trCL tfCL 90% VCC CLOCK 2.7V 3V CLOCK 50% 1.3V INPUT 10% INPUT 0.3V GND GND tH(H) tH(L) tH(H) tH(L) VCC DATA 3V INDPAUTAT 50% INPUT 1.3V 1.3V 1.3V GND GND tSU(H) tSU(L) tSU(H) tSU(L) tTLH tTHL tTLH tTHL 90% 90% 90% 90% 50% OUTPUT OUTPUT 1.3V 1.3V 10% 10% tPLH tPHL tPLH tPHL tREM tREM VCC 3V SET, RESET 50% SET, RESET 1.3V OR PRESET GND OR PRESET GND IC IC CL CL 50pF 50pF FIGURE1. HCSETUPTIMES,HOLDTIMES,REMOVALTIME, FIGURE2. HCTSETUPTIMES,HOLDTIMES,REMOVALTIME, AND PROPAGATION DELAY TIMES FOR EDGE AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS TRIGGERED SEQUENTIAL LOGIC CIRCUITS 6

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 5962-8970101EA ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8970101EA CD54HCT175F3A CD54HC175F3A ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type -55 to 125 8408901EA CD54HC175F3A CD54HCT175F3A ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8970101EA CD54HCT175F3A CD74HC175E ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -55 to 125 CD74HC175E & no Sb/Br) CD74HC175EE4 ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -55 to 125 CD74HC175E & no Sb/Br) CD74HC175M ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC175M & no Sb/Br) CD74HC175M96 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC175M & no Sb/Br) CD74HCT175E ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -55 to 125 CD74HCT175E & no Sb/Br) CD74HCT175EE4 ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -55 to 125 CD74HCT175E & no Sb/Br) CD74HCT175M ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT175M & no Sb/Br) CD74HCT175M96 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT175M & no Sb/Br) CD74HCT175M96G4 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT175M & no Sb/Br) CD74HCT175MG4 ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT175M & no Sb/Br) CD74HCT175MT ACTIVE SOIC D 16 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT175M & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF CD54HC175, CD54HCT175, CD74HC175, CD74HCT175 : •Catalog: CD74HC175, CD74HCT175 •Military: CD54HC175, CD54HCT175 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0(mm) B0(mm) K0(mm) P1 W Pin1 Type Drawing Diameter Width (mm) (mm) Quadrant (mm) W1(mm) CD74HC175M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD74HCT175M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) CD74HC175M96 SOIC D 16 2500 333.2 345.9 28.6 CD74HCT175M96 SOIC D 16 2500 333.2 345.9 28.6 PackMaterials-Page2

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