CD54HC164, CD74HC164, CD54HCT164, CD74HCT164 Data sheet acquired from Harris Semiconductor SCHS155C High-Speed CMOS Logic October 1997 - Revised August 2003 8-Bit Serial-In/Parallel-Out Shift Register Features Description • Buffered Inputs The’HC164and’HCT164are8-bitserial-inparallel-outshift registers with asynchronous reset. Data is shifted on the [ /Title • Asynchronous Master Reset positive edge of Clock (CP). A LOW on the Master Reset (CD74 • Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, (MR) pin resets the shift register and all outputs go to the HC164 TA = 25oC LOW state regardless of the input conditions. Two Serial Datainputs(DS1andDS2)areprovided,eitheronecanbe , • Fanout (Over Temperature Range) used as a Data Enable control. CD74 - Standard Outputs. . . . . . . . . . . . . . .10 LSTTL Loads HCT16 - Bus Driver Outputs . . . . . . . . . . . . .15 LSTTL Loads Ordering Information 4) • Wide Operating Temperature Range . . .-55oC to 125oC TEMP. RANGE /Sub- • Balanced Propagation Delay and Transition Times PART NUMBER (oC) PACKAGE ject • Significant Power Reduction Compared to LSTTL CD54HC164F3A -55 to 125 14 Ld CERDIP (High Logic ICs Speed • HC Types CD54HCT164F3A -55 to 125 14 Ld CERDIP CMOS - 2V to 6V Operation CD74HC164E -55 to 125 14 Ld PDIP Logic - High Noise Immunity: NIL = 30%, NIH = 30% of VCC 8-Bit at VCC = 5V CD74HC164M -55 to 125 14 Ld SOIC Serial- • HCT Types CD74HC164MT -55 to 125 14 Ld SOIC - 4.5V to 5.5V Operation In/Par- CD74HC164M96 -55 to 125 14 Ld SOIC - Direct LSTTL Input Logic Compatibility, allel- VIL= 0.8V (Max), VIH = 2V (Min) CD74HCT164E -55 to 125 14 Ld PDIP - CMOS Input Compatibility, Il≤1µA at VOL, VOH CD74HCT164M -55 to 125 14 Ld SOIC CD74HCT164MT -55 to 125 14 Ld SOIC CD74HCT164M96 -55 to 125 14 Ld SOIC NOTE: When ordering, use the entire part number. The suffix 96 denotestapeandreel.ThesuffixTdenotesasmall-quantityreelof 250. Pinout CD54HC164, CD54HCT164 (CERDIP) CD74HC164, CD74HCT164 (PDIP, SOIC) TOP VIEW DS1 1 14 VCC DS2 2 13 Q7 Q0 3 12 Q6 Q1 4 11 Q5 Q2 5 10 Q4 Q3 6 9 MR GND 7 8 CP CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated 1

CD54HC164, CD74HC164, CD54HCT164, CD74HCT164 Functional Diagram 3 1 Q0 DS1 4 Q1 2 5 DS2 Q2 6 Q3 10 Q4 11 Q5 12 Q6 13 Q7 9 8 MR GND = 7 CP VCC= 14 TRUTH TABLE INPUTS OUTPUTS OPERATING MODE MR CP DS1 DS2 Q0 Q1 - Q7 RESET (CLEAR) L X X X L L - L Shift H ↑ l l L q0 -q6 H ↑ l h L q0 -q6 H ↑ h l L q0 -q6 H ↑ h h H q0 -q6 H= High Voltage Level. h= High Voltage Level One Set-up Time Prior To The Low-to-high Clock Transition. l= Low Voltage Level One Set-up Time Prior To The Low-to-high Clock Transition. L= Low Voltage Level. X= Don’t Care. ↑= Transition from Low to High Level. qn=Lower Case Letters Indicate The State Of the Reference Input Clock Transition. 2

CD54HC164, CD74HC164, CD54HCT164, CD74HCT164 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Thermal Resistance (Typical, Note 1) θJA (oC/W) DC Input Diode Current, IIK E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 80 For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 86 DC Output Diode Current, IOK Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC DC Output Source or Sink Current per Output Pin, IO Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA (SOIC - Lead Tips Only) DC VCC or Ground Current, ICC orIGND. . . . . . . . . . . . . . . . . .±50mA Operating Conditions Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . .-55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION:Stressesabovethoselistedin“AbsoluteMaximumRatings”maycausepermanentdamagetothedevice.Thisisastressonlyratingandoperation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC PARAMETER SYMBOL VI(V) IO(mA) VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS HC TYPES High Level Input VIH - - 2 1.5 - - 1.5 - 1.5 - V Voltage 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V Low Level Input VIL - - 2 - - 0.5 - 0.5 - 0.5 V Voltage 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V High Level Output VOH VIH or -0.02 2 1.9 - - 1.9 - 1.9 - V Voltage VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V CMOS Loads -0.02 6 5.9 - - 5.9 - 5.9 - V High Level Output -4 4.5 3.98 - - 3.84 - 3.7 - V Voltage -5.2 6 5.48 - - 5.34 - 5.2 - V TTL Loads Low Level Output VOL VIH or 0.02 2 - - 0.1 - 0.1 - 0.1 V Voltage VIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V CMOS Loads 0.02 6 - - 0.1 - 0.1 - 0.1 V Low Level Output 4 4.5 - - 0.26 - 0.33 - 0.4 V Voltage 5.2 6 - - 0.26 - 0.33 - 0.4 V TTL Loads Input Leakage II VCC or - 6 - - ±0.1 - ±1 - ±1 µA Current GND Quiescent Device ICC VCC or 0 6 - - 8 - 80 - 160 µA Current GND 3

CD54HC164, CD74HC164, CD54HCT164, CD74HCT164 DC Electrical Specifications (Continued) TEST CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC PARAMETER SYMBOL VI(V) IO(mA) VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS HCT TYPES High Level Input VIH - - 4.5 to 2 - - 2 - 2 - V Voltage 5.5 Low Level Input VIL - - 4.5 to - - 0.8 - 0.8 - 0.8 V Voltage 5.5 High Level Output VOH VIH or -0.02 4.5 4.4 - - 4.4 - 4.4 - V Voltage VIL CMOS Loads High Level Output -4 4.5 3.98 - - 3.84 - 3.7 - V Voltage TTL Loads Low Level Output VOL VIH or 0.02 4.5 - - 0.1 - 0.1 - 0.1 V Voltage VIL CMOS Loads Low Level Output 4 4.5 - - 0.26 - 0.33 - 0.4 V Voltage TTL Loads Input Leakage II VCC to 0 5.5 - - ±0.1 - ±1 - ±1 µA Current GND Quiescent Device ICC VCC or 0 5.5 - - 8 - 80 - 160 µA Current GND Additional Quiescent ∆ICC VCC - 4.5 to - 100 360 - 450 - 490 µA Device Current Per (Note 2) -2.1 5.5 Input Pin: 1 Unit Load NOTE: 2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS Date Shift-In (1, 2) 0.3 MR 0.9 Clock 0.7 NOTE: Unit Load is∆ICClimit specified in DC Electrical Specifications table, e.g. 360µA max at 25oC. Prerequisite For Switching Function 25oC -40oC TO 85oC -55oC TO 125oC PARAMETER SYMBOL VCC (V) MIN MAX MIN MAX MIN MAX UNITS HC TYPES Maximum Clock Frequency fMAX 2 6 - 5 - 4 - MHz 4.5 30 - 24 - 20 - MHz 6 35 - 28 - 24 - MHz MR Pulse Width tw 2 60 - 75 - 90 - ns 4.5 12 - 15 - 18 - ns 6 10 - 13 - 15 - ns 4

CD54HC164, CD74HC164, CD54HCT164, CD74HCT164 Prerequisite For Switching Function (Continued) 25oC -40oC TO 85oC -55oC TO 125oC PARAMETER SYMBOL VCC (V) MIN MAX MIN MAX MIN MAX UNITS CP Pulse Width tW 2 80 - 100 - 120 - ns 4.5 16 - 20 - 24 - ns 6 14 - 17 - 20 - ns Set-up Time tSU 2 60 - 75 - 90 - ns 4.5 12 - 15 - 18 - ns 6 10 - 13 - 15 - ns Hold Time tH 2 4 - 4 - 4 - ns 4.5 4 - 4 - 4 - ns 6 4 - 4 - 4 - ns MR to Clock, tREM 2 80 - 100 - 120 - ns Removal Time 4.5 16 - 20 - 24 - ns 6 14 - 17 - 20 - ns HCT TYPES Maximum Clock Frequency fMAX 4.5 27 - 22 - 18 - MHz MR Pulse Width tw 6 18 - 23 - 27 - ns CP Pulse Width tw 4.5 18 - 23 - 27 - ns Set-up Time tSU 6 12 - 15 - 18 - ns Hold Time tH 4.5 4 - 4 - 4 - ns MR to Clock, tREM 6 16 - 20 - 24 - ns Removal Time Switching Specifications Input tr, tf = 6ns 25oC -40oC TO 85oC -55oCTO125oC TEST PARAMETER SYMBOL CONDITIONS VCC (V) TYP MAX MAX MAX UNITS HC TYPES Propagation Delay, tPLH, tPHL CL= 50pF 2 - 170 212 255 ns CP to Qn 4.5 - 34 43 51 ns CL= 15pF 5 14 - - - ns CL= 50pF 6 - 29 36 43 ns MR to Qn tPLH, tPHL CL= 50pF 2 - 140 175 210 ns 4.5 - 28 35 42 ns CL= 15pF 5 11 - - - ns CL= 50pF 6 - 24 30 36 ns Output Transition Times tTLH, tTHL CL= 50pF 2 - 75 - 110 ns 4.5 - 15 - 22 ns 6 - 13 - 19 ns Maximum Clock Frequency fMAX CL= 15pF 5 60 - - - MHz Input Capacitance CIN - - - 10 10 10 pF 5

CD54HC164, CD74HC164, CD54HCT164, CD74HCT164 Switching Specifications Input tr, tf = 6ns (Continued) 25oC -40oC TO 85oC -55oCTO125oC TEST PARAMETER SYMBOL CONDITIONS VCC (V) TYP MAX MAX MAX UNITS Power Dissipation CPD - 5 47 - - - pF Capacitance (Notes 3, 4) HCT TYPES Propagation Delay, tPLH, tPHL CL= 50pF 4.5 - 36 45 54 ns CP to Qn CL= 15pF 5 15 - - - ns MR to Qn tPLH, tPHL CL= 50pF 4.5 - 38 46 57 ns CL= 15pF 5 16 - - - ns Output Transition Times tTLH, tTHL CL= 50pF 4.5 - 15 19 22 ns Input Capacitance CIN - - - - - - pF Maximum Clock Frequency fMAX CL= 15pF - 54 - - - MHz Power Dissipation CPD - 5 49 10 10 10 pF Capacitance (Notes 3, 4) NOTES: 3. CPD is used to determine the dynamic power consumption, per device. 4. PD=VCC2fi+∑(CLVCC2+fO)wherefi=InputFrequency,fO=OutputFrequency,CL=OutputLoadCapacitance,VCC=Supply Voltage. Test Circuits and Waveforms trCL tfCL trCL tfCL 90% VCC CLOCK 2.7V 3V CLOCK 50% 1.3V INPUT 10% INPUT 0.3V GND GND tH(H) tH(L) tH(H) tH(L) VCC DATA 3V INDPAUTAT 50% INPUT 1.3V 1.3V 1.3V GND GND tSU(H) tSU(L) tSU(H) tSU(L) tTLH tTHL tTLH tTHL 90% 90% 90% 90% 50% OUTPUT OUTPUT 1.3V 1.3V 10% 10% tPLH tPHL tPLH tPHL tREM tREM VCC 3V SET, RESET 50% SET, RESET 1.3V OR PRESET GND OR PRESET GND IC IC CL CL 50pF 50pF FIGURE1. HCSETUPTIMES,HOLDTIMES,REMOVALTIME, FIGURE2. HCTSETUPTIMES,HOLDTIMES,REMOVALTIME, AND PROPAGATION DELAY TIMES FOR EDGE AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS TRIGGERED SEQUENTIAL LOGIC CIRCUITS 6

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 5962-8970401CA ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8970401CA CD54HCT164F3A CD54HC164F ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type -55 to 125 CD54HC164F CD54HC164F3A ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type -55 to 125 8416201CA CD54HC164F3A CD54HCT164F3A ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8970401CA CD54HCT164F3A CD74HC164E ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type -55 to 125 CD74HC164E & no Sb/Br) CD74HC164M ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC164M & no Sb/Br) CD74HC164M96 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC164M & no Sb/Br) CD74HC164M96G4 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC164M & no Sb/Br) CD74HC164ME4 ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC164M & no Sb/Br) CD74HC164MG4 ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC164M & no Sb/Br) CD74HC164MT ACTIVE SOIC D 14 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC164M & no Sb/Br) CD74HCT164E ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type -55 to 125 CD74HCT164E & no Sb/Br) CD74HCT164M ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT164M & no Sb/Br) CD74HCT164M96 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT164M & no Sb/Br) CD74HCT164M96E4 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT164M & no Sb/Br) CD74HCT164MT ACTIVE SOIC D 14 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT164M & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF CD54HC164, CD54HCT164, CD74HC164, CD74HCT164 : •Catalog: CD74HC164, CD74HCT164 •Military: CD54HC164, CD54HCT164 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 •Military - QML certified for Military and Defense Applications Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 8-Nov-2018 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) CD74HC164M96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 CD74HC164MT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 CD74HCT164M96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 CD74HCT164MT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 8-Nov-2018 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) CD74HC164M96 SOIC D 14 2500 367.0 367.0 38.0 CD74HC164MT SOIC D 14 250 210.0 185.0 35.0 CD74HCT164M96 SOIC D 14 2500 367.0 367.0 38.0 CD74HCT164MT SOIC D 14 250 210.0 185.0 35.0 PackMaterials-Page2

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PACKAGE OUTLINE J0014A CDIP - 5.08 mm max height SCALE 0.900 CERAMIC DUAL IN LINE PACKAGE PIN 1 ID A 4X .005 MIN (OPTIONAL) [0.13] .015-.060 TYP [0.38-1.52] 1 14 12X .100 [2.54] 14X .014-.026 14X .045-.065 [0.36-0.66] [1.15-1.65] .010 [0.25] C A B .754-.785 [19.15-19.94] 7 8 B .245-.283 .2 MAX TYP .13 MIN TYP [6.22-7.19] [5.08] [3.3] SEATING PLANE C .308-.314 [7.83-7.97] AT GAGE PLANE .015 GAGE PLANE [0.38] 0 -15 14X .008-.014 TYP [0.2-0.36] 4214771/A 05/2017 NOTES: 1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package is hermitically sealed with a ceramic lid using glass frit. 4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only. 5. Falls within MIL-STD-1835 and GDIP1-T14. www.ti.com

EXAMPLE BOARD LAYOUT J0014A CDIP - 5.08 mm max height CERAMIC DUAL IN LINE PACKAGE (.300 ) TYP [7.62] SEE DETAIL B SEE DETAIL A 1 14 12X (.100 ) [2.54] SYMM 14X ( .039) [1] 7 8 SYMM LAND PATTERN EXAMPLE NON-SOLDER MASK DEFINED SCALE: 5X .002 MAX (.063) [0.05] [1.6] METAL ALL AROUND ( .063) SOLDER MASK [1.6] OPENING METAL .002 MAX SOLDER MASK (R.002 ) TYP [0.05] OPENING [0.05] ALL AROUND DETAIL A DETAIL B SCALE: 15X 13X, SCALE: 15X 4214771/A 05/2017 www.ti.com

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