CD74HC93, CD74HCT93 Data sheet acquired from Harris Semiconductor SCHS138C High-Speed CMOS Logic 4-Bit Binary Ripple Counter August 1997 - Revised September 2003 Features Description • Can Be Configured to Divide By 2, 8, and 16 TheCD74HC93andCD74HCT93arehigh-speedsilicon-gate CMOS devices and are pin-compatible with low power [ /Title • Asynchronous Master Reset Schottky TTL (LSTTL). These 4-bit binary ripple counters (CD74 • Fanout (Over Temperature Range) consist of four master-slave flip-flops internally connected to HC93, - Standard Outputs. . . . . . . . . . . . . . .10 LSTTL Loads provideadivide-by-twosectionandadivide-by-eightsection. CD74 - Bus Driver Outputs . . . . . . . . . . . . .15 LSTTL Loads Each section has a separate clock input (CP0 and CP1) to initiate state changes of the counter on the HIGH to LOW HCT93 • Wide Operating Temperature Range . . .-55oC to 125oC clocktransition.StatechangesoftheQnoutputsdonotoccur ) • Balanced Propagation Delay and Transition Times simultaneously because of internal ripple delays. Therefore, /Sub- decoded output signals are subject to decoding spikes and • Significant Power Reduction Compared to LSTTL should not be used for clocks or strobes. ject Logic ICs (High AgatedANDasynchronousmasterreset(MR1andMR2is • HC Types provided which overrides both clocks and resets (clears) all Speed - 2V to 6V Operation flip-flops. CMOS - High Noise Immunity: NIL = 30%, NIH = 30% of VCC Logic at VCC = 5V Because the output from the divide by two section is not internally connected to the succeeding stages, the device 4-Bit • HCT Types may be operated in various counting modes. - 4.5V to 5.5V Operation Binary - Direct LSTTL Input Logic Compatibility, In a 4-bit ripple counter the output Q0 must be connected Ripple VIL= 0.8V (Max), VIH = 2V (Min) externally to input CP1. The input count pulses are applied Counte - CMOS Input Compatibility, Il≤1µA at VOL, VOH toclockinputCP0.Simultaneousfrequencydivisionsof2,4, r) 8,and16areperformedattheQ0,Q1,Q2,andQ3outputs as shown in the function table. As a 3-bit ripple counter the Pinout input count pulses are applied to inputCP1. Simultaneousfrequencydivisionsof2,4,and8areavailable CD74HC93 (PDIP, SOIC) at the Q1, Q2, Q3 outputs. Independent use of the first flip- flopisavailableiftheresetfunctioncoincideswiththereset CD74HCT93 (PDIP) of the 3-bit ripple-through counter. TOP VIEW Ordering Information CP1 1 14 CPO TEMP. RANGE MR1 2 13 NC PART NUMBER (oC) PACKAGE MR2 3 12 Q0 CD74HC93E -55 to 125 14 Ld PDIP NC 4 11 Q3 CD74HC93M -55 to 125 14 Ld SOIC VCC 5 10 GND CD74HC93MT -55 to 125 14 Ld SOIC NC 6 9 Q1 NC 7 8 Q2 CD74HC93M96 -55 to 125 14 Ld SOIC CD74HCT93E -55 to 125 14 Ld PDIP NOTE: Whenordering,usetheentirepartnumber.Thesuffix96 denotestapeandreel.ThesuffixTdenotesasmall-quantityreel of 250. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated 1

CD74HC93, CD74HCT93 TRUTH TABLE OUTPUTS COUNT Q0 Q1 Q2 Q3 0 L L L L 1 H L L L 2 L H L L 3 H H L L 4 L L H L 5 H L H L 6 L H H L 7 H H H L 8 L L L H 9 H L L H 10 L H L H 11 H H L H 12 L L H H 13 H L H H 14 L H H H 15 H H H H H = High Voltage Level, L = Low Voltage Level MODE SELECTION RESET OUTPUTS OUTPUTS MR1 MR2 Q0 Q1 Q2 Q3 H H L L L L L H Count Count Count Count H L L L H = High Voltage Level, L = Low Voltage Level 2

CD74HC93, CD74HCT93 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Thermal Resistance (Typical, Note 1) θJA (oC/W) DC Input Diode Current, IIK E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 80 For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 86 DC Output Diode Current, IOK Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC DC Output Source or Sink Current per Output Pin, IO Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA (SOIC - Lead Tips Only) DC VCC or Ground Current, ICC orIGND. . . . . . . . . . . . . . . . . .±50mA Operating Conditions Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . .-55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION:Stressesabovethoselistedin“AbsoluteMaximumRatings”maycausepermanentdamagetothedevice.Thisisastressonlyratingandoperation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC PARAMETER SYMBOL VI(V) IO(mA) VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS HC TYPES High Level Input VIH - - 2 1.5 - - 1.5 - 1.5 - V Voltage 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V Low Level Input VIL - - 2 - - 0.5 - 0.5 - 0.5 V Voltage 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V High Level Output VOH VIH or -0.02 2 1.9 - - 1.9 - 1.9 - V Voltage VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V CMOS Loads -0.02 6 5.9 - - 5.9 - 5.9 - V High Level Output -4 4.5 3.98 - - 3.84 - 3.7 - V Voltage -5.2 6 5.48 - - 5.34 - 5.2 - V TTL Loads Low Level Output VOL VIH or 0.02 2 - - 0.1 - 0.1 - 0.1 V Voltage VIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V CMOS Loads 0.02 6 - - 0.1 - 0.1 - 0.1 V Low Level Output 4 4.5 - - 0.26 - 0.33 - 0.4 V Voltage 5.2 6 - - 0.26 - 0.33 - 0.4 V TTL Loads Input Leakage II VCC or - 6 - - ±0.1 - ±1 - ±1 µA Current GND Quiescent Device ICC VCC or 0 6 - - 8 - 80 - 160 µA Current GND 3

CD74HC93, CD74HCT93 DC Electrical Specifications (Continued) TEST CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC PARAMETER SYMBOL VI(V) IO(mA) VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS HCT TYPES High Level Input VIH - - 4.5 to 2 - - 2 - 2 - V Voltage 5.5 Low Level Input VIL - - 4.5 to - - 0.8 - 0.8 - 0.8 V Voltage 5.5 High Level Output VOH VIH or -0.02 4.5 4.4 - - 4.4 - 4.4 - V Voltage VIL CMOS Loads High Level Output -4 4.5 3.98 - - 3.84 - 3.7 - V Voltage TTL Loads Low Level Output VOL VIH or 0.02 4.5 - - 0.1 - 0.1 - 0.1 V Voltage VIL CMOS Loads Low Level Output 4 4.5 - - 0.26 - 0.33 - 0.4 V Voltage TTL Loads Input Leakage II VCC to 0 5.5 - - ±0.1 - ±1 - ±1 µA Current GND Quiescent Device ICC VCC or 0 5.5 - - 8 - 80 - 160 µA Current GND Additional Quiescent ∆ICC VCC - 4.5 to - 100 360 - 450 - 490 µA Device Current Per (Note 2) -2.1 5.5 Input Pin: 1 Unit Load NOTE: 2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS CP0,CP1 0.6 MR1, MR2 0.4 NOTE: Unit Load is∆ICClimit specified in DC Electrical Specifications table, e.g. 360µA max at 25oC. Prerequisite For Switching Specifications 25oC -40oC TO 85oC -55oC TO 125oC TEST CONDITIONS PARAMETER SYMBOL VCC (V) MIN MAX MIN MAX MIN MAX UNITS HC TYPES Maximum Clock Frequency fMAX 2 6 - 5 - 4 - MHz 4.5 30 - 24 - 20 - MHz 6 35 - 28 - 24 - MHz Clock Pulse Width tw 2 80 - 100 - 120 - ns CP0,CP1 4.5 16 - 20 - 24 - ns 6 14 - 17 - 20 - ns 4

CD74HC93, CD74HCT93 Prerequisite For Switching Specifications (Continued) 25oC -40oC TO 85oC -55oC TO 125oC TEST CONDITIONS PARAMETER SYMBOL VCC (V) MIN MAX MIN MAX MIN MAX UNITS Reset Pulse Width tW 2 80 - 100 - 120 - ns 4.5 16 - 20 - 24 - ns 6 14 - 17 - 20 - ns Reset Removal Time tREM 2 50 - 65 - 75 - ns 4.5 10 - 13 - 15 - ns 6 9 - 11 - 13 - ns HCT TYPES Maximum Clock Frequency fMAX 4.5 30 - 24 - 20 - mHz Clock Pulse Width tW 4.5 16 - 20 - 24 - ns CP0,CP1 Reset Pulse Width tW 4.5 16 - 20 - 24 - ns Reset Removal Time tREM 4.5 10 - 13 - 15 - ns Switching Specifications Input tr, tf = 6ns -55oC TO 25oC -40oC TO 85oC 125oC TEST VCC PARAMETER SYMBOL CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX UNITS HC TYPES Propagation Delay Time tPLH, tPHL CL= 50pF 2 - - 125 - 155 - 190 ns CP0 to Q0 CL= 50pF 4.5 - - 25 - 31 - 38 ns CL= 15pF 5 - 10 - - - - ns CL= 50pF 6 - - 21 - 26 - 32 ns CP1 to Q1 tPLH, tPHL CL= 50pF 2 - 135 - 170 - 205 ns CL= 50pF 4.5 - 27 - 34 - 41 ns CL= 50pF 6 - 23 - 29 - 35 ns CP1 to Q2 tPLH, tPHL CL= 50pF 2 - 185 - 230 - 280 ns CL= 50pF 4.5 - 37 - 46 - 56 ns CL= 50pF 6 - 31 - 39 - 48 ns CP1 to Q3 tPLH, tPHL CL= 50pF 2 - 245 - 305 - 370 ns CL= 50pF 4.5 - 49 - 61 - 74 ns CL= 15pF 5 - 21 - - - - - ns CL= 50pF 6 - - 42 - 52 - 63 ns MR1, MR2 to Qn tPLH, tPHL CL= 50pF 2 - 155 - 195 - 235 ns CL= 50pF 4.5 - 31 - 39 - 47 ns CL= 15pF 5 - 13 - - - ns CL= 50pF 6 - 26 - 33 - 40 ns Output Transition Time tTLH, tTHL CL= 50pF 2 - - 75 - 95 - 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns Input Capacitance CIN CL= 50pF - - - 10 - 10 - 10 pF Power Dissipation Capacitance CPD - - - 25 - - 10 - 19 pF 5

CD74HC93, CD74HCT93 Switching Specifications Input tr, tf = 6ns (Continued) -55oC TO 25oC -40oC TO 85oC 125oC TEST VCC PARAMETER SYMBOL CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX UNITS HCT TYPES Propagation Delay Time tPLH, tPHL CL= 50pF 4.5 - - 34 - 43 - 51 ns CP0 to Q0 CL= 15pF 5 - 14 - - - - - ns CP1 to Q1 tPLH, tPHL CL= 50pF 4.5 - - 34 - 43 - 51 ns CL= 15pF 5 - - - - - - - ns CP1 to Q2 tPLH, tPHL CL= 50pF 4.5 - - 46 - 58 - 69 ns CL= 15pF 5 - - - - - - - ns CP1 to Q3 tPLH, tPHL CL= 50pF 4.5 - - 58 - 73 - 87 ns CL= 15pF 5 - 24 - - - - - ns MR1, MR2 to Qn tPLH, tPHL CL= 50pF 4.5 - - 33 - 41 - 50 ns CL= 15pF 5 - 13 - - - - - ns Output Transition Time tTLH, tTHL CL= 50pF 4.5 - - 15 - 19 - 22 ns Input Capacitance CIN CL= 50pF - - - 10 - 10 - 10 pF Power Dissipation Capacitance CPD - - - 25 - - - - - pF Test Circuits and Waveforms trCL tfCL trCL tfCL 90% VCC CLOCK 2.7V 3V CLOCK 50% 1.3V INPUT 10% INPUT 0.3V GND GND tH(H) tH(L) tH(H) tH(L) VCC DATA 3V INDPAUTAT 50% INPUT 1.3V 1.3V 1.3V GND GND tSU(H) tSU(L) tSU(H) tSU(L) tTLH tTHL tTLH tTHL 90% 90% 90% 90% 50% OUTPUT OUTPUT 1.3V 1.3V 10% 10% tPLH tPHL tPLH tPHL tREM tREM VCC 3V SET, RESET 50% SET, RESET 1.3V OR PRESET GND OR PRESET GND IC IC CL CL 50pF 50pF FIGURE1. HCSETUPTIMES,HOLDTIMES,REMOVALTIME, FIGURE2. HCTSETUPTIMES,HOLDTIMES,REMOVALTIME, AND PROPAGATION DELAY TIMES FOR EDGE AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS TRIGGERED SEQUENTIAL LOGIC CIRCUITS 6

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) CD74HC93E ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type -55 to 125 CD74HC93E & no Sb/Br) CD74HC93EE4 ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type -55 to 125 CD74HC93E & no Sb/Br) CD74HC93M ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC93M & no Sb/Br) CD74HC93M96 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC93M & no Sb/Br) CD74HC93MT ACTIVE SOIC D 14 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC93M & no Sb/Br) CD74HCT93E ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type -55 to 125 CD74HCT93E & no Sb/Br) CD74HCT93EE4 ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type -55 to 125 CD74HCT93E & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 8-Nov-2018 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) CD74HC93M96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 CD74HC93MT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 8-Nov-2018 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) CD74HC93M96 SOIC D 14 2500 367.0 367.0 38.0 CD74HC93MT SOIC D 14 250 210.0 185.0 35.0 PackMaterials-Page2

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