CD54HC670, CD74HC670, CD74HCT670 Data sheet acquired from Harris Semiconductor SCHS195C High-Speed CMOS Logic 4x4 Register File January 1998 - Revised October 2003 Features Description • Simultaneous and Independent Read and Write The ’HC670 and CD74HCT670 are 16-bit register files Operations organizedas4wordsx4bitseach.Readandwriteaddress [ /Title andenableinputsallowsimultaneouswritingintoonelocation (CD74H • Expandable to 512 Words of n-Bits whilereadinganother.Fourdatainputsareprovidedtostore C670, • Three-State Outputs the 4-bit word. The write address inputs (WA0 and WA1) determine the location of the stored word in the register. CD74H • Organized as 4 Words x 4 Bits Wide When write enable (WE) is low the word is entered into the CT670) • Buffered Inputs address location and it remains transparent to the data. The /Subject outputswillreflectthetrueformoftheinputdata.When(WE) (High- • Typical Read Time = 16ns for ’HC670 VCC = 5V, CL = ishighdataandaddressinputsareinhibited.Dataacquisition 15pF, TA = 25oC fromthefourregistersismadepossiblebythereadaddress Speed inputs (RA1 and RA0). The addressed word appears at the • Fanout (Over Temperature Range) CMOS outputwhenthereadenable(RE)islow.Theoutputisinthe - Standard Outputs. . . . . . . . . . . . . . .10 LSTTL Loads Logic highimpedancestatewhenthe(RE)ishigh.Outputscanbe - Bus Driver Outputs . . . . . . . . . . . . .15 LSTTL Loads 4x4Reg- tied together to increase the word capacity to 512 x 4 bits. • Wide Operating Temperature Range . . .-55oC to 125oC Ordering Information ister • Balanced Propagation Delay and Transition Times TEMP. RANGE PART NUMBER (oC) PACKAGE • Significant Power Reduction Compared to LSTTL Logic ICs CD54HC670F3A -55 to 125 16 Ld CERDIP CD74HC670E -55 to 125 16 Ld PDIP • HC Types CD74HC670M -55 to 125 16 Ld SOIC - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC CD74HC670MT -55 to 125 16 Ld SOIC at VCC = 5V CD74HC670M96 -55 to 125 16 Ld SOIC • HCT Types CD74HCT670E -55 to 125 16 Ld PDIP - 4.5V to 5.5V Operation CD74HCT670M -55 to 125 16 Ld SOIC - Direct LSTTL Input Logic Compatibility, CD74HCT670MT -55 to 125 16 Ld SOIC VIL= 0.8V (Max), VIH = 2V (Min) CD74HCT670M96 -55 to 125 16 Ld SOIC - CMOS Input Compatibility, Il≤1µA at VOL, VOH NOTE: When ordering, use the entire part number. The suffix 96 denotestapeandreel.ThesuffixTdenotesasmall-quantityreelof 250. Pinout CD54HC670 (CERDIP) CD74HC670, CD74HCT670 (PDIP, SOIC) TOP VIEW D1 1 16 VCC D2 2 15 D0 D3 3 14 WA0 RA1 4 13 WA1 RA0 5 12 WE Q3 6 11 RE Q2 7 10 Q0 GND 8 9 Q1 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated 1

CCDD5544HHCC667700,, CCDD7744HHCC667700,, CCDD7744HHCCTT667700 Functional Diagram 15 10 Q0 D0 1 9 D1 Q1 2 D2 7 3 Q2 D3 12 6 Q3 WE 11 RE 4 5 14 13 RA1 RA0 WA0 WA1 WRITE MODE SELECT TABLE READ MODE SELECT TABLE INPUTS INTERNAL INPUTS OPERATING LATCHES INTERNAL MODE WE DN (NOTE 1) OPERATING LATCHES OUTPUT Write Data L L L MODE RE (NOTE 2) QN L H H Read L L L Data Latched H X No Change L H H NOTE: Disabled H X (Z) 1. TheWriteAddress(WA0andWA1)tothe“internallatches”must NOTE: be stable whileWE is LOW for conventional operation. 2. Theselectionofthe“internallatches”byReadAddress(RA0and RA1) are not constrained byWE orRE operation. H = High Voltage Level L = Low Voltage Level X= Don’t Care Z = High Impedance “Off” State 2

CCDD5544HHCC667700,, CCDD7744HHCC667700,, CCDD7744HHCCTT667700 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Thermal Resistance (Typical, Note 3) θJA (oC/W) DC Input Diode Current, IIK E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 67 For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 73 DC Output Diode Current, IOK Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC DC Drain Current, per Output, IO Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA (SOIC - Lead Tips Only) DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . .-55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION:Stressesabovethoselistedin“AbsoluteMaximumRatings”maycausepermanentdamagetothedevice.Thisisastressonlyratingandoperation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 3. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS 25oC -40oC TO 85oC -55oCTO125oC VCC PARAMETER SYMBOL VI(V) IO(mA) (V) MIN TYP MAX MIN MAX MIN MAX UNITS HC TYPES High Level Input VIH - - 2 1.5 - - 1.5 - 1.5 - V Voltage 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V Low Level Input VIL - - 2 - - 0.5 - 0.5 - 0.5 V Voltage 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V High Level Output VOH VIHorVIL -0.02 2 1.9 - - 1.9 - 1.9 - V Voltage -0.02 4.5 4.4 - - 4.4 - 4.4 - V CMOS Loads -0.02 6 5.9 - - 5.9 - 5.9 - V High Level Output - - - - - - - - - V Voltage -6 4.5 3.98 - - 3.84 - 3.7 - V TTL Loads -7.8 6 5.48 - - 5.34 - 5.2 - V Low Level Output VOL VIHorVIL 0.02 2 - - 0.1 - 0.1 - 0.1 V Voltage 0.02 4.5 - - 0.1 - 0.1 - 0.1 V CMOS Loads 0.02 6 - - 0.1 - 0.1 - 0.1 V Low Level Output - - - - - - - - - V Voltage 6 4.5 - - 0.26 - 0.33 - 0.4 V TTL Loads 7.8 6 - - 0.26 - 0.33 - 0.4 V Input Leakage II VCC or - 6 - - ±0.1 - ±1 - ±1 µA Current GND 3

CCDD5544HHCC667700,, CCDD7744HHCC667700,, CCDD7744HHCCTT667700 DC Electrical Specifications (Continued) TEST CONDITIONS 25oC -40oC TO 85oC -55oCTO125oC VCC PARAMETER SYMBOL VI(V) IO(mA) (V) MIN TYP MAX MIN MAX MIN MAX UNITS Quiescent Device ICC VCC or 0 6 - - 8 - 80 - 160 µA Current GND Three-StateLeakage VILorVIH VO = 6 - - ±0.5 - ±5.0 - ±10 µA Current VCC or GND HCT TYPES High Level Input VIH - - 4.5 to 2 - - 2 - 2 - V Voltage 5.5 Low Level Input VIL - - 4.5 to - - 0.8 - 0.8 - 0.8 V Voltage 5.5 High Level Output VOH VIHorVIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V Voltage CMOS Loads High Level Output -6 4.5 3.98 - - 3.84 - 3.7 - V Voltage TTL Loads Low Level Output VOL VIHorVIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V Voltage CMOS Loads Low Level Output 6 4.5 - - 0.26 - 0.33 - 0.4 V Voltage TTL Loads Input Leakage II VCCand 0 5.5 - ±0.1 - ±1 - ±1 µA Current GND Quiescent Device ICC VCC or 0 5.5 - - 8 - 80 - 160 µA Current GND Three-StateLeakage VILorVIH VO = 5.5 - - ±0.5 - ±5.0 - ±10 µA Current VCC or GND Additional Quiescent ∆ICC VCC - 4.5 to - 100 360 - 450 - 490 µA Device Current Per (Note 4) -2.1 5.5 Input Pin: 1 Unit Load NOTE: 4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS WE 0.3 WA0 0.2 WA1 0.4 RE 1.5 DATA 0.15 RA0 0.4 RA1 0.7 NOTE: UnitLoadis∆ICClimitspecificinDCElectricalSpecifications Table, e.g., 360µA max. at 25oC. 4

CCDD5544HHCC667700,, CCDD7744HHCC667700,, CCDD7744HHCCTT667700 Prerequisite for Switching Specifications 25oC -40oC TO 85oC -55oC TO 125oC PARAMETER SYMBOL VCC(V) MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS HC TYPES Setup Time tSU, th 2 60 - - 75 - - 90 - - ns Data toWE Write toWE 4.5 12 - - 15 - - 18 - - ns 6 10 - - 13 - - 15 - - ns Hold Time tH, tW 2 5 - - 5 - - 5 - - ns Data toWE Write toWE 4.5 5 - - 5 - - 5 - - ns 6 5 - - 5 - - 5 - - ns Pulse WidthWE tW 2 80 - - 100 - - 120 - - ns 4.5 16 - - 20 - - 24 - - ns 6 14 - - 17 - - 20 - - ns Latch TimeWE to RA0, tLATCH 2 100 - - 125 - - 150 - - ns RA1 4.5 20 - - 25 - - 30 - - ns 6 17 - - 21 - - 26 - - ns HCT TYPES Setup Time tSU, th 4.5 12 - - 15 - - 18 - - ns Data toWE Hold Time tH, tW 4.5 5 - - 5 - - 5 - - ns Data toWE Write toWE Setup Time tSU 4.5 18 - - 23 - - 27 - - ns Write toWE Pulse WidthWE tW 4.5 20 - - 25 - - 30 - - ns Latch TimeWE to RA0, tLATCH 4.5 25 - - 31 - - 38 - - ns RA1 Switching Specifications CL = 50pF, Input tr, tf= 6ns -40oC TO -55oC TO 25oC 85oC 125oC TEST PARAMETER SYMBOL CONDITIONS VCC(V) MIN TYP MAX MIN MAX MIN MAX UNITS HC TYPES Propagation Delay tPLH, tPHL CL = 50pF Reading Any Word 2 - - 195 - 245 - 295 ns 4.5 - - 39 - 49 - 59 ns CL = 15pF 5 - 16 - - - - - ns CL = 50pF 6 - - 33 - 42 - 50 ns Write Enable to Output tPLH,tPHL CL = 50pF 2 - - 250 - 315 - 375 ns 4.5 - - 50 - 63 - 75 ns CL = 15pF 5 - 21 - - - - - ns CL = 50pF 6 - - 43 - 54 - 64 ns 5

CD54HC670, CD74HC670, CD74HCT670 Switching Specifications CL = 50pF, Input tr, tf= 6ns (Continued) -40oC TO -55oC TO 25oC 85oC 125oC TEST PARAMETER SYMBOL CONDITIONS VCC(V) MIN TYP MAX MIN MAX MIN MAX UNITS Data to Output tPLH,tPHL CL = 50pF 2 - - 256 - 315 - 375 ns 4.5 - - 50 - 63 - 75 ns CL = 15pF 5 - 21 - - - - - ns CL = 50pF 6 - - 43 - 54 - 64 ns Output Disable Time tPLZ,tPHZ CL = 50pF 2 - - 150 - 190 - 225 ns 4.5 - - 30 - 38 - 45 ns CL = 15pF 5 - 12 - - - - - ns CL = 50pF 6 - - 26 - 33 - 38 ns Output Enable Time tPZL,tPZH CL = 50pF 2 - - 150 - 190 - 225 ns 4.5 - - 30 - 38 - 45 ns CL = 15pF 5 - 12 - - - - - ns CL = 50pF 6 - - 26 - 33 - 38 ns Output Transition Time tTHL, tTLH CL = 50pF 2 - - 75 - 95 - 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 10 - 19 ns Input Capacitance CI CL = 50pF - 10 - 10 - 10 - 10 pF Three-State Output CO - - 20 - 20 - 20 - 20 pF Capacitance Power Dissipation Capacitance CPD CL = 15pF 5 - 59 - - - - - pF (Notes 5, 6) HCT TYPES Propagation Delay tPHL,tPLH Reading Any Word CL = 50pF 4.5 - - 40 - 50 - 53 ns CL = 15pF 5 - 17 - - - - - ns Write Enable to Output tPHL,tPLH CL = 50pF 4.5 - - 50 - 63 - 75 ns CL = 15pF 5 - 21 - - - - - ns Data to Output tPHL,tPLH CL = 50pF 4.5 - - 50 - 63 - 75 ns CL = 15pF 5 - 21 - - - - - ns Output Disable Time tPLZ,tPHZ CL = 50pF 4.5 - - 35 - 44 - 53 ns CL = 15pF 5 - 14 - - - - - ns Output Enable Time tPZL,tPZH CL = 50pF 4.5 - - 38 - 48 - 57 ns CL = 15pF 5 - 16 - - - - - ns Output Transition Time tTLH, tTHL CL = 50pF 4.5 - - 15 - 19 - 22 ns Input Capacitance CI CL = 50pF - 10 - 10 - 10 - 10 pF Three-State Output CO - - 20 - 20 - 20 - 20 pF Capacitance Power Dissipation Capacitance CPD CL = 15pF 5 - 66 - - - - - pF (Notes 5, 6) NOTES: 5. CPD is used to determine the dynamic power consumption, per output. 6. PD=CPDVCC2fi+∑CLVCC2fOwherefi=InputFrequency,fO=OutputFrequency,CL=OutputLoadCapacitance,VCC=Supply Voltage. 6

CCDD5544HHCC667700,, CCDD7744HHCC667700,, CCDD7744HHCCTT667700 Test Circuits and Waveforms I trCL tfCL tWL+ tWH=fCIL trCL= 6ns tfCL= 6ns tWL+ tWH=fCL VCC 3V 90% 2.7V CLOCK 50% 50% 50% CLOCK 1.3V 1.3V 1.3V 10% 10% GND 0.3V 0.3V GND tWL tWH tWL tWH NOTE: Outputs should be switching from 10% VCC to 90% VCC in NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordancewithdevicetruthtable.ForfMAX,inputdutycycle=50%. accordancewithdevicetruthtable.ForfMAX,inputdutycycle=50%. FIGURE1. HCCLOCKPULSERISEANDFALLTIMESAND FIGURE2. HCTCLOCKPULSERISEANDFALLTIMESAND PULSE WIDTH PULSE WIDTH tr = 6ns tf = 6ns tr = 6ns tf = 6ns 90% VCC 2.7V 3V INPUT 50% INPUT 1.3V 10% GND 0.3V GND tTHL tTLH tTHL tTLH 90% 90% 50% 1.3V INVERTING INVERTING 10% 10% OUTPUT OUTPUT tPHL tPLH tPHL tPLH FIGURE3. HCTRANSITIONTIMESANDPROPAGATION FIGURE4. HCTTRANSITIONTIMESANDPROPAGATION DELAY TIMES, COMBINATION LOGIC DELAY TIMES, COMBINATION LOGIC trCL tfCL trCL tfCL 90% VCC CLOCK 2.7V 3V CLOCK 50% 1.3V INPUT 10% INPUT 0.3V GND GND tH(H) tH(L) tH(H) tH(L) VCC DATA 3V INDPAUTAT 50% INPUT 1.3V 1.3V 1.3V GND GND tSU(H) tSU(L) tSU(H) tSU(L) tTLH tTHL tTLH tTHL 90% 90% 90% 90% 50% OUTPUT OUTPUT 1.3V 1.3V 10% 10% tPLH tPHL tPLH tPHL tREM tREM VCC 3V SET, RESET 50% SET, RESET 1.3V OR PRESET GND OR PRESET GND IC IC CL CL 50pF 50pF FIGURE5. HCSETUPTIMES,HOLDTIMES,REMOVALTIME, FIGURE6. HCTSETUPTIMES,HOLDTIMES,REMOVALTIME, AND PROPAGATION DELAY TIMES FOR EDGE AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS TRIGGERED SEQUENTIAL LOGIC CIRCUITS 7

CCDD5544HHCC667700,, CCDD7744HHCC667700,, CCDD7744HHCCTT667700 Test Circuits and Waveforms (Continued) 6ns 6ns tr 6ns tf 6ns OUTPUT 90% VCC OUTPUT 2.7 3V DISABLE 50% DISABLE 1.3 10% 0.3 GND GND tPLZ tPZL tPLZ tPZL OUTPUT LOW OUTPUT LOW TO OFF 50% TO OFF 1.3V 10% 10% tPHZ 90% tPZH tPHZ 90% tPZH OUTPUT HIGH OUTPUT HIGH 50% TO OFF TO OFF 1.3V OUTPUTS OUTPUTS OUTPUTS OUTPUTS OUTPUTS OUTPUTS ENABLED DISABLED ENABLED ENABLED DISABLED ENABLED FIGURE7. HCTHREE-STATEPROPAGATIONDELAY FIGURE8. HCTTHREE-STATEPROPAGATIONDELAY WAVEFORM WAVEFORM OTHER OUTPUT INPUTS IC WITH RL = 1kΩ TIED HIGH THREE- VCC FOR tPLZ AND tPZL OR LOW STATE CL GND FOR tPHZ AND tPZH OUTPUT 50pF OUTPUT DISABLE NOTE: OpendrainwaveformstPLZandtPZLarethesameasthoseforthree-stateshownontheleft.ThetestcircuitisOutputRL=1kΩto VCC, CL = 50pF. FIGURE 9. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT 8

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) CD74HC670E ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -55 to 125 CD74HC670E & no Sb/Br) CD74HC670M ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC670M & no Sb/Br) CD74HC670M96 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC670M & no Sb/Br) CD74HCT670E ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -55 to 125 CD74HCT670E & no Sb/Br) CD74HCT670M ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT670M & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2009 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) CD74HC670M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2009 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) CD74HC670M96 SOIC D 16 2500 333.2 345.9 28.6 PackMaterials-Page2

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