CD54HC4514, CD74HC4514, CD74HC4515 Data sheet acquired from Harris Semiconductor SCHS280C High-Speed CMOS Logic 4- to 16-Line Decoder/Demultiplexer with Input Latches November 1997 - Revised July 2003 Features Description • Multifunction Capability The CD54HC4514, CD74HC4514, and CD74HC4515 are - Binary to 1-of-16 Decoder high-speedsilicongatedevicesconsistingofa4-bitstrobed [ /Title latch and a 4- to 16-line decoder. The selected output is - 1-to-16 Line Demultiplexer (CD74 enabledbyalowontheenableinput(E).AhighonEinhibits • Fanout (Over Temperature Range) HC451 selection of any output. Demultiplexing is accomplished by 4, - Standard Outputs. . . . . . . . . . . . . . .10 LSTTL Loads usingtheEinputasthedatainputandtheselectinputs(A0- - Bus Driver Outputs . . . . . . . . . . . . .15 LSTTL Loads A3)asaddresses.ThisEinputalsoservesasachipselect CD74 when these devices are cascaded. HC451 • Wide Operating Temperature Range . . .-55oC to 125oC When Latch Enable (LE) is high the output follows changes 5) • Balanced Propagation Delay and Transition Times in the inputs (see truth table). When LE is low the output is /Sub- isolated from changes in the input and remains at the level • Significant Power Reduction Compared to LSTTL ject Logic ICs (highforthe4514,lowforthe4515)ithadbeforethelatches were enabled. These devices, enhanced versions of the (High • HC Types equivalent CMOS types, can drive 10 LSTTL loads. Speed - 2V to 6V Operation CMOS Ordering Information - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V PART NUMBER TEMP. RANGE (oC) PACKAGE Pinout CD54HC4514F3A -55 to 125 24 Ld CERDIP CD74HC4514E -55 to 125 24 Ld PDIP CD54HC4514 (CERDIP) CD74HC4514EN -55 to 125 24 Ld PDIP CD74HC4514, CD74HC4515 (PDIP, SOIC) CD74HC4514M -55 to 125 24 Ld SOIC TOP VIEW CD74HC4514M96 -55 to 125 24 Ld SOIC LE 1 24 VCC CD74HC4515E -55 to 125 24 Ld PDIP A0 2 23 E CD74HC4515EN -55 to 125 24 Ld PDIP A1 3 22 A3 CD74HC4515M -55 to 125 24 Ld SOIC Y7 4 21 A2 Y6 5 20 Y10 CD74HC4515M96 -55 to 125 24 Ld SOIC Y5 6 19 Y11 NOTE: When ordering, use the entire part number. The suffix 96 Y4 7 18 Y8 denotes tape and reel. Y3 8 17 Y9 Y1 9 16 Y14 Y2 10 15 Y15 Y0 11 14 Y12 GND 12 13 Y13 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated 1

CD54HC4514, CD74HC4514, CD74HC4515 Functional Diagram HC HC 4514 4515 11 Y0 Y0 9 Y1 Y1 10 Y2 Y2 8 Y3 Y3 7 2 Y4 Y4 A0 6 Y5 Y5 3 5 A1 Y6 Y6 4 A2 21 LATCH D4E-CTOOD-1E6R 18 YY87 YY87 17 22 Y9 Y9 A3 20 Y10 Y10 19 1 Y11 Y11 LE 14 Y12 Y12 13 Y13 Y13 16 Y14 Y14 15 Y15 Y15 23 GND = 12 E VCC = 24 DECODE TRUTH TABLE (LE = 1) DECODER INPUTS ADDRESSED OUTPUT 4514 = LOGIC 1 (HIGH) ENABLE A3 A2 A1 A0 4515 = LOGIC 0 (HIGH) 0 0 0 0 0 Y0 0 0 0 0 1 Y1 0 0 0 1 0 Y2 0 0 0 1 1 Y3 0 0 1 0 0 Y4 0 0 1 0 1 Y5 0 0 1 1 0 Y6 0 0 1 1 1 Y7 0 1 0 0 0 Y8 0 1 0 0 1 Y9 0 1 0 1 0 Y10 0 1 0 1 1 Y11 0 1 1 0 0 Y12 0 1 1 0 1 Y13 0 1 1 1 0 Y14 0 1 1 1 1 Y15 1 X X X X All Outputs = 0, 4514 All Outputs = 1, 4515 X = Don’t Care; Logic 1 = High; Logic 0 = Low 2

CD54HC4514, CD74HC4514, CD74HC4515 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Thermal Resistance (Typical) θJA (oC/W) DC Input Diode Current, IIK E (PDIP) Package (Note 1) . . . . . . . . . . . . . . . . . . . 67 For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA EN (PDIP) Package (Note 1). . . . . . . . . . . . . . . . . . 67 DC Output Diode Current, IOK M (SOIC) Package (Note 2). . . . . . . . . . . . . . . . . . . 46 For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC DC Drain Current, per Output, IO Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC DC Output Source or Sink Current per Output Pin, IO (SOIC - Lead Tips Only) For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA Operating Conditions Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . .-55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION:Stressesabovethoselistedin“AbsoluteMaximumRatings”maycausepermanentdamagetothedevice.Thisisastressonlyratingandoperation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. The package thermal impedance is calculated in accordance with JESD 51-3. 2. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS 25oC -40oC TO 85oC -55oCTO125oC VCC PARAMETER SYMBOL VI(V) IO(mA) (V) MIN TYP MAX MIN MAX MIN MAX UNITS HC TYPES High Level Input VIH - - 2 1.5 - - 1.5 - 1.5 - V Voltage 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V Low Level Input VIL - - 2 - - 0.5 - 0.5 - 0.5 V Voltage 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V High Level Output VOH VIHorVIL -0.02 2 1.9 - - 1.9 - 1.9 - V Voltage CMOS Loads -0.02 4.5 4.4 - - 4.4 - 4.4 - V -0.02 6 5.9 - - 5.9 - 5.9 - V High Level Output - - - - - - - - - V Voltage TTL Loads -4 4.5 3.98 - - 3.84 - 3.7 - V -5.2 6 5.48 - - 5.34 - 5.2 - V 3

CD54HC4514, CD74HC4514, CD74HC4515 DC Electrical Specifications (Continued) TEST CONDITIONS 25oC -40oC TO 85oC -55oCTO125oC VCC PARAMETER SYMBOL VI(V) IO(mA) (V) MIN TYP MAX MIN MAX MIN MAX UNITS Low Level Output VOL VIHorVIL 0.02 2 - - 0.1 - 0.1 - 0.1 V Voltage CMOS Loads 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 0.02 6 - - 0.1 - 0.1 - 0.1 V Low Level Output - - - - - - - - - V Voltage TTL Loads 4 4.5 - - 0.26 - 0.33 - 0.4 V 5.2 6 - - 0.26 - 0.33 - 0.4 V Input Leakage II VCC or - 6 - - ±0.1 - ±1 - ±1 µA Current GND Quiescent Device ICC VCC or 0 6 - - 8 - 80 - 160 µA Current GND Prerequisite For Switching Specifications 25oC -40oC TO 85oC -55oCTO125oC TEST VCC PARAMETER SYMBOL CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX UNITS HC TYPES LE Pulse Width tW - 2 75 - - 95 - 110 - ns 4.5 30 - - 19 - 22 - ns 6 35 - - 16 - 19 - ns Select toLE Set-Up Time tSU - 2 100 - - 125 - 150 - ns 4.5 20 - - 25 - 30 - ns 6 17 - - 21 - 26 - ns Select toLE Hold Time tH - 2 0 - - 0 - 0 - ns 4.5 0 - - 0 - 0 - ns 6 0 - - 0 - 0 - ns Switching Specifications CL = 50pF, Input tr, tf= 6ns -40oC TO -55oC TO 25oC 85oC 125oC TEST PARAMETER SYMBOL CONDITIONS VCC(V) MIN TYP MAX MIN MAX MIN MAX UNITS HC TYPES Propagation Delay tPHL, tPLH CL = 50pF Select to Outputs 2 - - 275 - 345 - 415 ns 4.5 - - 55 - 69 - 83 ns CL = 15pF 5 - 23 - - - - - ns CL = 50pF 6 - - 47 - 59 - 71 ns LE to Outputs tPHL, tPLH CL = 50pF 2 - - 225 - 280 - 340 ns 4.5 - - 45 - 56 - 68 ns CL = 15pF 5 - 19 - - - - - ns CL = 50pF 6 - - 38 - 48 - 58 ns 4

CD54HC4514, CD74HC4514, CD74HC4515 Switching Specifications CL = 50pF, Input tr, tf= 6ns (Continued) -40oC TO -55oC TO 25oC 85oC 125oC TEST PARAMETER SYMBOL CONDITIONS VCC(V) MIN TYP MAX MIN MAX MIN MAX UNITS E to Outputs tPHL, tPLH CL = 50pF 2 - - 175 - 220 - 265 ns 4.5 - - 35 - 44 - 53 ns CL = 15pF 5 - 14 - - - - - ns CL = 50pF 6 - - 30 - 37 - 45 ns Output Transition Time tTHL, tTLH CL = 50pF 2 - - 75 - 95 - 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns Input Capacitance CIN CL = 50pF - 10 - 10 - 10 - 10 pF Power Dissipation Capacitance CPD - 5 - 70 - - - - - pF (Notes 3, 4) NOTES: 3. CPD is used to determine the dynamic power consumption, per package. 4. PD = VCC2 fi (CPD + CL) where fi =Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. Test Circuits and Waveforms tr = 6ns tf = 6ns trCL tfCL tWL+ tWH=fCIL INPUT 9500%% VCC 90% VCC 10% GND CLOCK 50% 50% 50% 10% 10% GND tTHL tTLH tWL tWH 90% 50% INVERTING 10% OUTPUT NOTE: Outputs should be switching from 10% VCC to 90% VCC in tPHL tPLH accordancewithdevicetruthtable.ForfMAX,inputdutycycle=50%. FIGURE1. HCCLOCKPULSERISEANDFALLTIMESAND FIGURE2. HCTRANSITIONTIMESANDPROPAGATION PULSE WIDTH DELAY TIMES, COMBINATION LOGIC tr = 6ns tf = 6ns 90% VCC INPUT 50% 10% GND tTHL tTLH 90% 50% INVERTING 10% OUTPUT tPHL tPLH FIGURE 3. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC 5

CD54HC4514, CD74HC4514, CD74HC4515 Test Circuits and Waveforms (Continued) trCL tfCL trCL tfCL 90% VCC 90% VCC CLOCK 50% CLOCK 50% INPUT 10% INPUT 10% GND GND tH(H) tH(L) tH(H) tH(L) VCC VCC DATA 50% DATA 50% INPUT INPUT GND GND tSU(H) tSU(L) tSU(H) tSU(L) tTLH tTHL tTLH tTHL 90% 90% 90% 90% 50% 50% OUTPUT OUTPUT 10% 10% tPLH tPHL tPLH tPHL tREM tREM VCC VCC SET, RESET 50% SET, RESET 50% OR PRESET OR PRESET GND GND IC IC CL CL 50pF 50pF FIGURE4. HCSETUPTIMES,HOLDTIMES,REMOVALTIME, FIGURE5. HCSETUPTIMES,HOLDTIMES,REMOVALTIME, AND PROPAGATION DELAY TIMES FOR EDGE AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS TRIGGERED SEQUENTIAL LOGIC CIRCUITS 6

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 5962-9865501QJA ACTIVE CDIP J 24 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9865501QJ A CD54HC4514F3A CD54HC4514F3A ACTIVE CDIP J 24 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-9865501QJ A CD54HC4514F3A CD74HC4514M ACTIVE SOIC DW 24 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC4514M & no Sb/Br) CD74HC4514M96 ACTIVE SOIC DW 24 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC4514M & no Sb/Br) CD74HC4515M ACTIVE SOIC DW 24 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC4515M & no Sb/Br) CD74HC4515M96 ACTIVE SOIC DW 24 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC4515M & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF CD54HC4514, CD74HC4514 : •Catalog: CD74HC4514 •Military: CD54HC4514 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 14-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) CD74HC4514M96 SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1 CD74HC4515M96 SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 14-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) CD74HC4514M96 SOIC DW 24 2000 350.0 350.0 43.0 CD74HC4515M96 SOIC DW 24 2000 350.0 350.0 43.0 PackMaterials-Page2

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MECHANICAL DATA MCDI004A – JANUARY 1995 – REVISED NOVEMBER 1997 J (R-GDIP-T**) CERAMIC DUAL-IN-LINE PACKAGE 24 PINS SHOWN B 24 13 C 1 12 0.065 (1,65) Lens Protrusion (Lens Optional) 0.045 (1,14) 0.010 (0.25) MAX 0.090 (2,29) 0.175 (4,45) A 0.060 (1,53) 0.140 (3,56) Seating Plane 0.018 (0,46) MIN 0.022 (0,56) 0.125 (3,18) MIN 0.100 (2,54) 0.014 (0,36) 0.012 (0,30) 0.008 (0,20) PINS ** 24 28 32 40 DIM NARR WIDE NARR WIDE NARR WIDE NARR WIDE MAX 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) ”A” MIN 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) MAX 1.265(32,13) 1.265(32,13) 1.465(37,21) 1.465(37,21) 1.668(42,37) 1.668(42,37) 2.068(52,53) 2.068(52,53) ”B” MIN 1.235(31,37) 1.235(31,37) 1.435(36,45) 1.435(36,45) 1.632(41,45) 1.632(41,45) 2.032(51,61) 2.032(51,61) MAX 0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19) ”C” MIN 0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50) 4040084/C 10/97 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Window (lens) added to this group of packages (24-, 28-, 32-, 40-pin). D. This package can be hermetically sealed with a ceramic lid using glass frit. E. Index point is provided on cap for terminal identification. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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