CD54HC4017, CD74HC4017 Data sheet acquired from Harris Semiconductor SCHS200D High-Speed CMOS Logic Decade Counter/Divider with 10 Decoded Outputs November 1997 - Revised October 2003 Features Description • Fully Static Operation The ’HC4017 is a high speed silicon gate CMOS 5-stage Johnson counter with 10 decoded outputs. Each of the [ /Title • Buffered Inputs decodedoutputsisnormallylowandsequentiallygoeshigh (CD74 • Common Reset on the low to high transition clock period of the 10 clock HC401 periodcycle.TheCARRY(TC)outputtransitionslowtohigh • Positive Edge Clocking afterOUTPUT10goesfromhightolow,andcanbeusedin 7) /Sub- • TypicalfMAX=50MHzatVCC=5V,CL=15pF,TA=25oC conjunction with the CLOCK ENABLE (CE) to cascade several stages. The CLOCK ENABLE input disables ject • Fanout (Over Temperature Range) countingwheninthehighstate.ARESET(MR)inputisalso (High - Standard Outputs. . . . . . . . . . . . . . .10 LSTTL Loads provided which when taken high sets all the decoded - Bus Driver Outputs . . . . . . . . . . . . .15 LSTTL Loads outputs, except “0”, low. Speed CMOS • Wide Operating Temperature Range . . .-55oC to 125oC Thedevicecandriveupto10lowpowerSchottkyequivalent loads. Logic • Balanced Propagation Delay and Transition Times Decade Ordering Information • Significant Power Reduction Compared to LSTTL Counte Logic ICs TEMP. RANGE • HC Types PART NUMBER (oC) PACKAGE - 2V to 6V Operation CD54HC4017F3A -55 to 125 16 Ld CERDIP - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V CD74HC4017E -55 to 125 16 Ld PDIP CD74HC4017M -55 to 125 16 Ld SOIC CD74HC4017MT -55 to 125 16 Ld SOIC CD74HC4017M96 -55 to 125 16 Ld SOIC CD74HC4017NSR -55 to 125 16 Ld SOP CD74HC4017PW -55 to 125 16 Ld TSSOP CD74HC4017PWR -55 to 125 16 Ld TSSOP NOTE: Whenordering,usetheentirepartnumber.Thesuffixes96 andRdenotetapeandreel.ThesuffixTdenotesasmall-quantity reel of 250. Pinout CD54HC4017 (CERDIP) CD74HC4017 (PDIP, SOIC, SOP, TSSOP) TOP VIEW 5 1 16 VCC 1 2 15 MR 0 3 14 CP 2 4 13 CE 6 5 12 TC 7 6 11 9 3 7 10 4 GND 8 9 8 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated 1

CD54HC4017, CD74HC4017 Functional Diagram 3 0 14 2 1 CLOCK 4 CLOCK 13 2 UT ENABLE 7 O 3 L A 10 M 4 CI MASTER 15 1 DE RESET 5 D 5 E 6 OD 6 C 7 DE 9 8 11 9 12 TERMINAL COUNT TRUTH TABLE CP CE MR OUTPUT STATE† L X L No Change X H L No Change X X H “0” = H, “1”-”9” = L ↑ L L Increments Counter ↓ X L No Change X ↑ L No Change H ↓ L Increments Counter H = High Level L = Low Level ↑ = High to Low Transition ↓ = Low to High Transition X = Don’t Care. † If n < 5 TC = H, Otherwise = L 2

CD54HC4017, CD74HC4017 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Package Thermal Impedance,θJA(see Note 1): DC Input Diode Current, IIK E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67oC/W For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73oC/W DC Output Diode Current, IOK NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64oC/W For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA PW (TSSOP) Package. . . . . . . . . . . . . . . . . . . . . . . . . .108oC/W DC Output Source or Sink Current per Output Pin, IO Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC DC VCC or Ground Current, ICC orIGND. . . . . . . . . . . . . . . . . .±50mA Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . .-55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION:Stressesabovethoselistedin“AbsoluteMaximumRatings”maycausepermanentdamagetothedevice.Thisisastressonlyratingandoperation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS 25oC -40oC TO 85oC -55oCTO125oC VCC PARAMETER SYMBOL VI(V) IO(mA) (V) MIN TYP MAX MIN MAX MIN MAX UNITS High Level Input VIH - - 2 1.5 - - 1.5 - 1.5 - V Voltage 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V Low Level Input VIL - - 2 - - 0.5 - 0.5 - 0.5 V Voltage 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V High Level Output VOH VIHorVIL -0.02 2 1.9 - - 1.9 - 1.9 - V Voltage -0.02 4.5 4.4 - - 4.4 - 4.4 - V CMOS Loads -0.02 6 5.9 - - 5.9 - 5.9 - V High Level Output - - - - - - - - - V Voltage -4 4.5 3.98 - - 3.84 - 3.7 - V TTL Loads -5.2 6 5.48 - - 5.34 - 5.2 - V Low Level Output VOL VIHorVIL 0.02 2 - - 0.1 - 0.1 - 0.1 V Voltage 0.02 4.5 - - 0.1 - 0.1 - 0.1 V CMOS Loads 0.02 6 - - 0.1 - 0.1 - 0.1 V Low Level Output - - - - - - - - - V Voltage 4 4.5 - - 0.26 - 0.33 - 0.4 V TTL Loads 5.2 6 - - 0.26 - 0.33 - 0.4 V Input Leakage II VCC or - 6 - - ±0.1 - ±1 - ±1 µA Current GND Quiescent Device ICC VCC or 0 6 - - 8 - 80 - 160 µA Current GND 3

CD54HC4017, CD74HC4017 Prerequisite for Switching Specifications 25oC -40oC TO 85oC -55oCTO125oC TEST VCC PARAMETER SYMBOL CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX UNITS Maximum Clock fMAX - 2 6 - - 5 - 4 - MHz Frequency 4.5 30 - - 35 - 20 - MHz 6 35 - - 49 - 23 - MHz CP Pulse Width tW - 2 80 - - 100 - 120 - ns 4.5 16 - - 20 - 24 - ns 6 14 - - 17 - 20 - ns MR Pulse Width tW - 2 80 - - 100 - 120 - ns 4.5 16 - - 20 - 24 - ns 6 14 - - 17 - 20 - ns Set-up Time, tSU - 2 75 - - 95 - 110 - ns CE to CP 4.5 15 - - 19 - 22 - ns 6 13 - - 16 - 19 - ns Hold Time, tH - 2 0 - - 0 - 0 - ns CE to CP 4.5 0 - - 0 - 0 - ns 6 0 - - 0 - 0 - ns MR Removal Time tREM - 2 5 - - 5 - 5 - ns 4.5 5 - - 5 - 5 - ns 6 5 - - 5 - 5 - ns Switching SpecificationsInput tr, tf = 6ns -40oC TO 25oC 85oC -55oCTO125oC TEST VCC PARAMETER SYMBOL CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX UNITS Propagation Delay tPLH, CL = 50pF 2 - - 230 - 290 - 345 ns CP to any Dec. Out tPHL CL = 50pF 4.5 - - 46 - 58 - 69 ns CL = 15pF 5 - 19 - - - - - ns CL = 50pF 6 - - 39 - 49 - 59 ns CP to TC tPLH, CL = 50pF 2 - - 230 - 290 - 345 ns tPHL CL = 50pF 4.5 - - 46 - 58 - 69 ns CL = 15pF 5 - 19 - - - - - ns CL = 50pF 6 - - 39 - 49 - 59 ns CE to any Dec. Out tPLH, CL = 50pF - - 250 - 315 - 375 ns tPHL 2 CL = 50pF 4.5 - - 50 - 63 - 75 ns CL = 15pF 5 - 21 - - - - - ns CL = 50pF 6 - - 43 - 54 - 64 ns CE to TC tPLH, CL = 50pF 2 - - 250 - 315 - 375 ns tPHL CL = 50pF 4.5 - - 50 - 63 - 75 ns CL = 15pF 5 - 21 - - - - - ns CL = 50pF 6 - - 43 - 54 - 64 ns 4

CD54HC4017, CD74HC4017 Switching SpecificationsInput tr, tf = 6ns (Continued) -40oC TO 25oC 85oC -55oCTO125oC TEST VCC PARAMETER SYMBOL CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX UNITS MR to any Dec. Out tPLH, CL = 50pF 2 - - 230 - 290 - 345 ns tPHL CL = 50pF 4.5 - - 46 - 58 - 69 ns CL = 15pF 5 - 19 - - - - - ns CL = 50pF 6 - - 39 - 49 - 59 ns MR to TC tPLH, CL = 50pF 2 - - 230 - 290 - 345 ns tPHL CL = 50pF 4.5 - - 46 - 58 - 69 ns CL = 15pF 5 - 19 - - - - - ns CL = 50pF 6 - - 39 - 49 - 59 ns Transition Time TC, Dec. Out tTLH,tTHL CL = 50pF 2 - - 75 - 95 - 110 ns CL = 50pF 4.5 - - 15 - 19 - 22 ns CL = 50pF 6 - - 13 - 16 - 19 ns Input Capacitance CIN CL = 50pF - - - 10 - 10 - 10 pF Maximum CP Frequency fMAX CL = 15pF 5 - 60 - - - - - MHz Power Dissipation Capacitance CPD CL = 15pF 5 - 39 - - - - - pF (Notes 2, 3) NOTES: 2. CPD is used to determine the dynamic power consumption, per package. 3. PD = VCC2 fiΣ€CL VCC2 fo where fi = input frequency, fo = output frequency, CL = output load capacitance, VCC = supply voltage. Test Circuits and Waveforms I tr = 6ns tf = 6ns trCL tfCL tWL+ tWH=fCL 90% VCC VCC INPUT 50% CLOCK 90% 50% 50% 50% 10% GND 10% 10% GND tTHL tTLH tWL tWH 90% 50% INVERTING 10% OUTPUT NOTE: Outputs should be switching from 10% VCC to 90% VCC in tPHL tPLH accordancewithdevicetruthtable.ForfMAX,inputdutycycle=50%. FIGURE1. HCCLOCKPULSERISEANDFALLTIMESAND FIGURE2. HCTRANSITIONTIMESANDPROPAGATION PULSE WIDTH DELAY TIMES, COMBINATION LOGIC 5

CD54HC4017, CD74HC4017 Test Circuits and Waveforms (Continued) trCL tfCL 90% VCC CLOCK 50% INPUT 10% GND tH(H) tH(L) VCC DATA 50% INPUT GND tSU(H) tSU(L) tTLH tTHL 90% 90% 50% OUTPUT 10% tPLH tPHL tREM VCC SET, RESET 50% OR PRESET GND IC CL 50pF FIGURE3. HCSETUPTIMES,HOLDTIMES,REMOVALTIME,ANDPROPAGATIONDELAYTIMESFOREDGETRIGGERED SEQUENTIAL LOGIC CIRCUITS Timing Diagrams CLOCK MASTER RESET CLOCK ENABLE CL CL “0” 0 0 “1” D P P 1 1 N N Q “2” 2 2 CL CL CL CL ““34”” 3 4 C CL PN CL P “5” Q 5 N “6” 6 CL “7” 7 R “8” 8 “9” 9 FF DETAIL TERMINAL COUNT FIGURE 4. FIGURE 5. 6

PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 8601101EA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 8601101EA CD54HC4017F3A CD54HC4017F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 8601101EA CD54HC4017F3A CD74HC4017E ACTIVE PDIP N 16 25 Green (RoHS CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC4017E & no Sb/Br) CD74HC4017EE4 ACTIVE PDIP N 16 25 Green (RoHS CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC4017E & no Sb/Br) CD74HC4017M ACTIVE SOIC D 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4017M & no Sb/Br) CD74HC4017M96 ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4017M & no Sb/Br) CD74HC4017MT ACTIVE SOIC D 16 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4017M & no Sb/Br) CD74HC4017MTE4 ACTIVE SOIC D 16 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4017M & no Sb/Br) CD74HC4017NSR ACTIVE SO NS 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4017M & no Sb/Br) CD74HC4017NSRE4 ACTIVE SO NS 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC4017M & no Sb/Br) CD74HC4017PW ACTIVE TSSOP PW 16 90 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4017 & no Sb/Br) CD74HC4017PWR ACTIVE TSSOP PW 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4017 & no Sb/Br) CD74HC4017PWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4017 & no Sb/Br) CD74HC4017PWT ACTIVE TSSOP PW 16 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ4017 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF CD54HC4017, CD74HC4017 : •Catalog: CD74HC4017 •Automotive: CD74HC4017-Q1, CD74HC4017-Q1 •Enhanced Product: CD74HC4017-EP, CD74HC4017-EP •Military: CD54HC4017 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 •Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects •Enhanced Product - Supports Defense, Aerospace and Medical Applications •Military - QML certified for Military and Defense Applications Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) CD74HC4017M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD74HC4017NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 CD74HC4017PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 CD74HC4017PWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) CD74HC4017M96 SOIC D 16 2500 333.2 345.9 28.6 CD74HC4017NSR SO NS 16 2000 367.0 367.0 38.0 CD74HC4017PWR TSSOP PW 16 2000 367.0 367.0 35.0 CD74HC4017PWT TSSOP PW 16 250 367.0 367.0 35.0 PackMaterials-Page2

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PACKAGE OUTLINE PW0016A TSSOP - 1.2 mm max height SCALE 2.500 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 14X 0.65 16 1 2X 5.1 4.55 4.9 NOTE 3 8 9 0.30 B 4.5 16X 0.19 1.2 MAX 4.3 0.1 C A B NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.05 0.75 0.50 0 -8 DETA 20AIL A TYPICAL 4220204/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL UNDER SOLDER MASK OPENING METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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