CD54HC373, CD74HC373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS452A – FEBRUARY 2001 – REVISED APRIL 2003 (cid:0) 2-V to 6-V VCC Operation CD54HC373...F PACKAGE (cid:0) CD74HC373...E OR M PACKAGE Wide Operating Temperature Range of (TOP VIEW) –55°C to 125°C (cid:0) Balanced Propagation Delays and OE 1 20 V CC Transition Times 1Q 2 19 8Q (cid:0) Standard Outputs Drive up to 15 LS-TTL 1D 3 18 8D Loads 2D 4 17 7D (cid:0) 2Q 5 16 7Q Significant Power Reduction Compared to LS-TTL Logic ICs 3Q 6 15 6Q 3D 7 14 6D description/ordering information 4D 8 13 5D 4Q 9 12 5Q The ’HC373 devices are octal transparent D-type GND 10 11 LE latches designed for 2-V to 6-V VCC operation. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING PDIP – E Tube CD74HC373E CD74HC373E Tube CD74HC373M –5555°°CC ttoo 112255°°CC SSOOIICC – MM HHCC337733MM Tape and reel CD74HC373M96 CDIP – F Tube CD54HC373F3A CD54HC373F3A †Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright  2003, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments On products compliant to MIL-PRF-38535, all parameters are tested standard warranty. Production processing does not necessarily include unless otherwise noted. On all other products, production testing of all parameters. processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

CD54HC373, CD74HC373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS452A – FEBRUARY 2001 – REVISED APRIL 2003 FUNCTION TABLE (each latch) INPUTS OUTPUT OE LE D Q L H H H L H L L L L X Q0 H X X Z logic diagram (positive logic) 1 OE 11 LE C1 2 3 1Q 1D 1D To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V CC Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA IK I I CC Output clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA OK O O CC Continuous output drain current per output, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA O O CC Continuous output source or sink current per output, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . ±25 mA O O CC Continuous current through V or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA CC Package thermal impedance, θJA (see Note 2): E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CD54HC373, CD74HC373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS452A – FEBRUARY 2001 – REVISED APRIL 2003 recommended operating conditions (see Note 3) MIN MAX UNIT VCC Supply voltage 2 6 V VCC = 2 V 1.5 VIH High-level input voltage VCC = 4.5 V 3.15 V VCC = 6 V 4.2 VCC = 2 V 0.5 VIL Low-level input voltage VCC = 4.5 V 1.35 V VCC = 6 V 1.8 VI Input voltage 0 VCC V VO Output voltage 0 VCC V VCC = 2 V 1000 tt Input transition (rise and fall) time VCC = 4.5 V 500 ns VCC = 6 V 400 TA Operating free-air temperature –55 125 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCCCC TA = 25°C TTAO = 1 –2555°°CC TATO = 8–54°0C°C UNIT MIN MAX MIN MAX MIN MAX 2 V 1.9 1.9 1.9 IOH = –20 µA 4.5 V 4.4 4.4 4.4 VOH VI = VIH or VIL 6 V 5.9 5.9 5.9 V IOH = –6 mA 4.5 V 3.98 3.7 3.84 IOH = –7.8 mA 6 V 5.48 5.2 5.34 2 V 0.1 0.1 0.1 IOL = 20 µA 4.5 V 0.1 0.1 0.1 VOL VI = VIH or VIL 6 V 0.1 0.1 0.1 V IOL = 6 mA 4.5 V 0.26 0.4 0.33 IOL = 7.8 mA 6 V 0.26 0.4 0.33 II VI = VCC or 0 6 V ±0.1 ±1 ±1 µA IOZ VO = VCC or 0 6 V ±0.5 ±10 ±5 µA ICC VI = VCC or 0, IO = 0 6 V 8 160 80 µA Ci 10 10 10 pF Co 20 20 20 pF POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

CD54HC373, CD74HC373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS452A – FEBRUARY 2001 – REVISED APRIL 2003 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCCCC TA = 25°C TTAO = 1 –2555°°CC TATO = 8–54°0C°C UNIT MIN MAX MIN MAX MIN MAX 2 V 80 120 100 tw Pulse duration, LE high 4.5 V 16 24 20 ns 6 V 14 20 17 2 V 50 75 65 tsu Setup time, data before LE↓↓ 4.5 V 10 15 13 ns 6 V 9 13 11 2 V 5 5 5 th Hold time, data after LE↓↓ 4.5 V 5 5 5 ns 6 V 5 5 5 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER ((IIFNNRPPOUUMTT)) ((OOUUTTTOPPUUTT)) CCAAPPAALOCCIIATTDAANNCCEE VCCCC TA = 25°C TTAO = 1 –2555°°CC TATO = 8–54°0C°C UNIT MIN MAX MIN MAX MIN MAX 2 V 150 225 190 D Q CL = 50 pF 4.5 V 30 45 38 6 V 26 38 33 ttpdd nnss 2 V 175 265 220 LE Q CL = 50 pF 4.5 V 35 53 44 6 V 30 45 37 2 V 150 225 190 ten OE Q CL = 50 pF 4.5 V 30 45 38 ns 6 V 26 38 33 2 V 150 225 190 tdis OE Q CL = 50 pF 4.5 V 30 45 38 ns 6 V 26 38 33 2 V 60 90 75 tt Q CL = 50 pF 4.5 V 12 18 15 ns 6 V 10 15 13 operating characteristics, VCC = 5 V, TA = 25°C PARAMETER TYP UNIT Cpd Power dissipation capacitance 51 pF 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CD54HC373, CD74HC373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS452A – FEBRUARY 2001 – REVISED APRIL 2003 PARAMETER MEASUREMENT INFORMATION VCC PARAMETER S1 S2 tPZH Open Closed Test S1 ten tPZL Closed Open From Output Point RL = 1 kΩ Under Test tPHZ Open Closed tdis CL tPLZ Closed Open S2 (see Note A) tpd or tt Open Open tw LOAD CIRCUIT VCC Input 50% VCC 50% VCC 0 V VOLTAGE WAVEFORMS PULSE DURATION VCC VCC Reference 50% VCC CLR 50% VCC Input 0 V Input 0 V tsu th trec VCC Data 90% 90% VCC Input 50% 50% VCC CLK 50% VCC 10% 10% 0 V 0 V tr tf VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS RECOVERY TIME SETUP AND HOLD AND INPUT RISE AND FALL TIMES VCC Input 50% VCC 50% VCC Output VCC 0 V Control 50% VCC 50% VCC 0 V tPLH tPHL tPZL tPLZ InO-Puhtapsuet 50% 90% 90% 50% VCVCOH Output ≈VCC 10% tr 10%tf VOL (Wseaev eNfootrem B 1) 50% VCC 10% VOL tPHL tPLH tPZH tPHZ VOH Out-of-Phase 90% 90% 50% VCC 50% Output VOH Output 10% 10% 90% VOL Waveform 2 50% VCC tf tr (see Note B) ≈0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES OUTPUT ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. D. For clock inputs, fmax is measured with the input duty cycle at 50%. E. The outputs are measured one at a time with one input transition per measurement. F. tPLZ and tPHZ are the same as tdis. G. tPZL and tPZH are the same as ten. H. tPLH and tPHL are the same as tpd. I. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) CD54HC373F ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 CD54HC373F CD54HC373F3A ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 8407201RA CD54HC373F3A CD74HC373E ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type -55 to 125 CD74HC373E (RoHS) CD74HC373EE4 ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type -55 to 125 CD74HC373E (RoHS) CD74HC373M ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC373M & no Sb/Br) CD74HC373M96 ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC373M & no Sb/Br) CD74HC373ME4 ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC373M & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF CD54HC373, CD74HC373 : •Catalog: CD74HC373 •Military: CD54HC373 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) CD74HC373M96 SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) CD74HC373M96 SOIC DW 20 2000 367.0 367.0 45.0 PackMaterials-Page2

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PACKAGE OUTLINE DW0020A SOIC - 2.65 mm max height SCALE 1.200 SOIC C 10.63 SEATING PLANE TYP 9.97 A PIN 1 ID 0.1 C AREA 18X 1.27 20 1 13.0 2X 12.6 11.43 NOTE 3 10 11 0.51 20X 7.6 0.31 2.65 MAX B 7.4 0.25 C A B NOTE 4 0.33 TYP 0.10 0.25 SEE DETAIL A GAGE PLANE 0.3 1.27 0 - 8 0.1 0.40 DETAIL A TYPICAL 4220724/A 05/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS-013. www.ti.com

EXAMPLE BOARD LAYOUT DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM (R0.05) TYP 10 11 (9.3) LAND PATTERN EXAMPLE SCALE:6X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220724/A 05/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM 10 11 (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4220724/A 05/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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