CD54HC273, CD74HC273, CD54HCT273, CD74HCT273 Data sheet acquired from Harris Semiconductor SCHS174B High-Speed CMOS Logic February 1998 - Revised May 2003 Octal D-Type Flip-Flop with Reset Features Description • Common Clock and Asynchronous Master Reset The ’HC273 and ’HCT273 high speed octal D-Type flip-flops with a direct clear input are manufactured with silicon-gate [ /Title • Positive Edge Triggering CMOStechnology.Theypossessthelowpowerconsumption (CD74 • Buffered Inputs of standard CMOS integrated circuits. HC273 • Fanout (Over Temperature Range) Information at the D inputis transferred to the Q outputs on , - Standard Outputs. . . . . . . . . . . . . . .10 LSTTL Loads thepositive-goingedgeoftheclockpulse.Alleightflip-flops CD74 - Bus Driver Outputs . . . . . . . . . . . . .15 LSTTL Loads arecontrolledbyacommonclock(CP)andacommonreset (MR). Resetting is accomplished by a low voltage level HCT27 • Wide Operating Temperature Range . . .-55oC to 125oC independent of the clock. All eight Q outputs are reset to a 3) • Balanced Propagation Delay and Transition Times logic 0. /Sub- Ordering Information • Significant Power Reduction Compared to LSTTL ject Logic ICs (High PART NUMBER TEMP. RANGE (oC) PACKAGE • HC Types Speed - 2V to 6V Operation CD54HC273F3A -55 to 125 20 Ld CERDIP CMOS - High Noise Immunity: NIL = 30%, NIH = 30% of VCC CD74HC273E -55 to 125 20 Ld PDIP Logic at VCC = 5V CD74HC273M -55 to 125 20 Ld SOIC Octal • HCT Types CD74HC273M96 -55 to 125 20 Ld SOIC D- - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, CD54HCT273F3A -55 to 125 20 Ld CERDIP Type Flip- - VCIML=O 0S. 8InVp (uMt aCxo),m VpIHat =ib 2ilVit y(,M Ilin≤)1µA at VOL, VOH CD74HCT273E -55 to 125 20 Ld PDIP CD74HCT273M -55 to 125 20 Ld SOIC CD74HCT273M96 -55 to 125 20 Ld SOIC NOTE: Whenordering,usetheentirepartnumber.Thesuffix96 denotes tape and reel. Pinout CD54HC273, CD54HCT273 (CERDIP) CD74HC273, CD74HCT273 (PDIP, SOIC) TOP VIEW MR 1 20 VCC Q0 2 19 Q7 D0 3 18 D7 D1 4 17 D6 Q1 5 16 Q6 Q2 6 15 Q5 D2 7 14 D5 D3 8 13 D4 Q3 9 12 Q4 GND 10 11 CP CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated 1

CD54/74HC273, CD54/74HCT273 Functional Diagram CLOCK CP D0 Q0 D1 Q1 D2 Q2 D3 Q3 DATA DATA INPUTS OUTPUTS D4 Q4 D5 Q5 D6 Q6 D7 Q7 RESETMR TRUTH TABLE INPUTS OUTPUT RESET (MR) CLOCK CP DATA Dn Q L X X L H ↑ H H H ↑ L L H L X Q0 H=HighVoltageLevel,L=LowVoltageLevel,X=Don’tCare,↑=TransitionfromLowto High Level, Q0=Level Before the Indicated Steady-State Input Conditions Were Established. 2

CD54/74HC273, CD54/74HCT273 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Thermal Resistance (Typical, Note 1) θJC(oC/W) DC Input Diode Current, IIK E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 DC Output Diode Current, IOK Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC DC Drain Current, per Output, IO Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA (SOIC - Lead Tips Only) DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . .-55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION:Stressesabovethoselistedin“AbsoluteMaximumRatings”maycausepermanentdamagetothedevice.Thisisastressonlyratingandoperation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC PARAMETER SYMBOL VI(V) IO(mA) VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS HC TYPES High Level Input VIH - - 2 1.5 - - 1.5 - 1.5 - V Voltage 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V Low Level Input VIL - - 2 - - 0.5 - 0.5 - 0.5 V Voltage 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V High Level Output VOH VIH or -0.02 2 1.9 - - 1.9 - 1.9 - V Voltage VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V CMOS Loads -0.02 6 5.9 - - 5.9 - 5.9 - V High Level Output -4 4.5 3.98 - - 3.84 - 3.7 - V Voltage -5.2 6 5.48 - - 5.34 - 5.2 - V TTL Loads Low Level Output VOL VIH or 0.02 2 - - 0.1 - 0.1 - 0.1 V Voltage VIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V CMOS Loads 0.02 6 - - 0.1 - 0.1 - 0.1 V Low Level Output 4 4.5 - - 0.26 - 0.33 - 0.4 V Voltage 5.2 6 - - 0.26 - 0.33 - 0.4 V TTL Loads Input Leakage II VCC or - 6 - - ±0.1 - ±1 - ±1 µA Current GND Quiescent Device ICC VCC or 0 6 - - 8 - 80 - 160 µA Current GND 3

CD54/74HC273, CD54/74HCT273 DC Electrical Specifications (Continued) TEST CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC PARAMETER SYMBOL VI(V) IO(mA) VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS HCT TYPES High Level Input VIH - - 4.5 to 2 - - 2 - 2 - V Voltage 5.5 Low Level Input VIL - - 4.5 to - - 0.8 - 0.8 - 0.8 V Voltage 5.5 High Level Output VOH VIH or -0.02 4.5 4.4 - - 4.4 - 4.4 - V Voltage VIL CMOS Loads High Level Output -4 4.5 3.98 - - 3.84 - 3.7 - V Voltage TTL Loads Low Level Output VOL VIH or 0.02 4.5 - - 0.1 - 0.1 - 0.1 V Voltage VIL CMOS Loads Low Level Output 4 4.5 - - 0.26 - 0.33 - 0.4 V Voltage TTL Loads Input Leakage II VCC to 0 5.5 - - ±0.1 - ±1 - ±1 µA Current GND Quiescent Device ICC VCC or 0 5.5 - - 8 - 80 - 160 µA Current GND Additional Quiescent ∆ICC VCC - 4.5 to - 100 360 - 450 - 490 µA Device Current Per (Note 2) -2.1 5.5 Input Pin: 1 Unit Load NOTE: 2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS MR 1.5 Data 0.4 CP 1.5 NOTE: Unit Load is∆ICClimit specified in DC Electrical Specifications table, e.g., 360µA max at 25oC. Prerequisite For Switching Specifications 25oC -40oC TO 85oC -55oCTO125oC TEST VCC PARAMETER SYMBOL CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX UNITS HC TYPES Maximum Clock Frequency fMAX - 2 6 - - 5 - 4 - MHz (Figure 1) 4.5 30 - - 25 - 20 - MHz 6 35 - - 29 - 23 - MHz MR Pulse Width tW - 2 60 - - 75 - 90 - ns (Figure 1) 4.5 12 - - 15 - 18 - ns 6 10 - - 13 - 15 - ns 4

CD54/74HC273, CD54/74HCT273 Prerequisite For Switching Specifications (Continued) 25oC -40oC TO 85oC -55oCTO125oC TEST VCC PARAMETER SYMBOL CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX UNITS Clock Pulse Width (Figure 1) tW - 2 80 - - 100 - 120 - ns 4.5 16 - - 20 - 24 - ns 6 14 - - 17 - 20 - ns Set-up Time Data to Clock tSU - 2 60 - - 75 - 70 - ns (Figure 5) 4.5 12 - - 15 - 18 - ns 6 10 - - 13 - 15 - ns Hold Time, Data to Clock tH - 2 3 - - 3 - 3 - ns (Figure 5) 4.5 3 - - 3 - 3 - ns 6 3 - - 3 - 3 - ns Removal Time,MR to Clock tREM - 2 50 - - 65 - 75 - ns 4.5 10 - - 13 - 15 - ns 6 9 - - 11 - 13 - ns HCT TYPES Maximum Clock Frequency fMAX - 4.5 25 - - 20 - 16 - MHz (Figure 2) MR Pulse Width tw - 4.5 12 - - 15 - 18 - ns (Figure 2) Clock Pulse Width (Figure 2) tw - 4.5 20 - - 25 - 30 - ns Set-up Time Data to Clock tSU - 4.5 12 - - 15 - 18 - ns (Figure 6) Hold Time, Data to Clock tH - 4.5 3 - - 3 - 3 - ns (Figure 6) Removal Time,MR to Clock tREM - 4.5 10 - - 13 - 15 - ns Switching Specifications Input tr, tf = 6ns -55oC TO 25oC -40oC TO 85oC 125oC TEST PARAMETER SYMBOL CONDITIONS VCC (V) TYP MAX MAX MAX UNITS HC TYPES Propagation Delay, tPLH, tPHL CL= 50pF 2 - 150 190 225 ns Clock to Output (Figure 3) 4.5 - 30 38 45 ns 6 - 26 30 38 ns CL= 15pF 5 12 - - - ns Propagation Delay, tPHL CL= 50pF 2 - 150 190 225 ns MR to Output (Figure 3) 4.5 - 30 38 45 ns 6 - 26 30 38 ns Output Transition Time tTLH, tTHL CL= 50pF 2 - 75 95 110 ns (Figure 3) 4.5 - 15 19 22 ns 6 - 13 16 19 ns Input Capacitance CI - - - 10 10 10 pF Maximum Clock Frequency fMAX CL= 15pF 5 60 - - - MHz 5

CD54/74HC273, CD54/74HCT273 Switching Specifications Input tr, tf = 6ns (Continued) -55oC TO 25oC -40oC TO 85oC 125oC TEST PARAMETER SYMBOL CONDITIONS VCC (V) TYP MAX MAX MAX UNITS Power Dissipation CPD - 5 25 - - - pF Capacitance (Notes 3, 4) HCT TYPES Propagation Delay, tPLH, tPHL CL= 50pF 4.5 - 30 38 45 ns Clock to Output (Figure 4) CL= 15pF 5 12 - - - ns Propagation Delay, tPHL CL= 50pF 4.5 - 32 40 48 ns MR to Output (Figure 4) Output Transition Time tTLH, tTHL CL= 50pF 4.5 - 15 19 22 ns Input Capacitance CIN - - - 10 10 10 pF Maximum Clock Frequency fMAX CL= 15pF 5 50 - - - MHz Power Dissipation CPD - 5 25 - - - pF Capacitance (Notes 3, 4) NOTES: 3. CPD is used to determine the dynamic power consumption, per flip-flop. 4. PD=CPDVCC2fi+∑(CLVCC2+fO)wherefi=InputFrequency,fO=OutputFrequency,CL=OutputLoadCapacitance,VCC=Supply Voltage. Test Circuits and Waveforms I trCL tfCL tWL+ tWH=fCIL trCL= 6ns tfCL= 6ns tWL+ tWH=fCL VCC 3V 90% 2.7V CLOCK 50% 50% 50% CLOCK 1.3V 1.3V 1.3V 10% 10% GND 0.3V 0.3V GND tWL tWH tWL tWH NOTE: Outputs should be switching from 10% VCC to 90% VCC in NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordancewithdevicetruthtable.ForfMAX,inputdutycycle=50%. accordancewithdevicetruthtable.ForfMAX,inputdutycycle=50%. FIGURE1. HCCLOCKPULSERISEANDFALLTIMESAND FIGURE2. HCTCLOCKPULSERISEANDFALLTIMESAND PULSE WIDTH PULSE WIDTH tr = 6ns tf = 6ns tr = 6ns tf = 6ns 90% VCC 2.7V 3V INPUT 50% INPUT 1.3V 10% GND 0.3V GND tTHL tTLH tTHL tTLH 90% 90% 50% 1.3V INVERTING INVERTING 10% 10% OUTPUT OUTPUT tPHL tPLH tPHL tPLH FIGURE3. HCANDHCUTRANSITIONTIMESANDPROPAGA- FIGURE4. HCTTRANSITIONTIMESANDPROPAGATION TION DELAY TIMES, COMBINATION LOGIC DELAY TIMES, COMBINATION LOGIC 6

CD54/74HC273, CD54/74HCT273 Test Circuits and Waveforms (Continued) trCL tfCL trCL tfCL 90% VCC CLOCK 2.7V 3V CLOCK 50% 1.3V INPUT 10% INPUT 0.3V GND GND tH(H) tH(L) tH(H) tH(L) VCC DATA 3V INDPAUTAT 50% INPUT 1.3V 1.3V 1.3V GND GND tSU(H) tSU(L) tSU(H) tSU(L) tTLH tTHL tTLH tTHL 90% 90% 90% 90% 50% OUTPUT OUTPUT 1.3V 1.3V 10% 10% tPLH tPHL tPLH tPHL tREM tREM VCC 3V SET, RESET 50% SET, RESET 1.3V OR PRESET GND OR PRESET GND IC IC CL CL 50pF 50pF FIGURE5. HCSETUPTIMES,HOLDTIMES,REMOVALTIME, FIGURE6. HCTSETUPTIMES,HOLDTIMES,REMOVALTIME, AND PROPAGATION DELAY TIMES FOR EDGE AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS TRIGGERED SEQUENTIAL LOGIC CIRCUITS 7

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 5962-8772501RA ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8772501RA CD54HCT273F3A CD54HC273F ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 CD54HC273F CD54HC273F3A ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 8409901RA CD54HC273F3A CD54HCT273F ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 CD54HCT273F CD54HCT273F3A ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8772501RA CD54HCT273F3A CD74HC273E ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type -55 to 125 CD74HC273E (RoHS) CD74HC273M ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC273M & no Sb/Br) CD74HC273M96 ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC273M & no Sb/Br) CD74HC273M96E4 ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC273M & no Sb/Br) CD74HC273ME4 ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC273M & no Sb/Br) CD74HC273MG4 ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC273M & no Sb/Br) CD74HCT273E ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type -55 to 125 CD74HCT273E (RoHS) CD74HCT273EE4 ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type -55 to 125 CD74HCT273E (RoHS) CD74HCT273M ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT273M & no Sb/Br) CD74HCT273M96 ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT273M & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF CD54HC273, CD54HCT273, CD74HC273, CD74HCT273 : •Catalog: CD74HC273, CD74HCT273 •Military: CD54HC273, CD54HCT273 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) CD74HC273M96 SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 CD74HCT273M96 SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) CD74HC273M96 SOIC DW 20 2000 367.0 367.0 45.0 CD74HCT273M96 SOIC DW 20 2000 367.0 367.0 45.0 PackMaterials-Page2

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PACKAGE OUTLINE DW0020A SOIC - 2.65 mm max height SCALE 1.200 SOIC C 10.63 SEATING PLANE TYP 9.97 A PIN 1 ID 0.1 C AREA 18X 1.27 20 1 13.0 2X 12.6 11.43 NOTE 3 10 11 0.51 20X 7.6 0.31 2.65 MAX B 7.4 0.25 C A B NOTE 4 0.33 TYP 0.10 0.25 SEE DETAIL A GAGE PLANE 0.3 1.27 0 - 8 0.1 0.40 DETAIL A TYPICAL 4220724/A 05/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS-013. www.ti.com

EXAMPLE BOARD LAYOUT DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM (R0.05) TYP 10 11 (9.3) LAND PATTERN EXAMPLE SCALE:6X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220724/A 05/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM 10 11 (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4220724/A 05/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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