CD54HC245, CD74HC245, CD54HCT245, CD74HCT245 Data sheet acquired from Harris Semiconductor SCHS119A High-Speed CMOS Logic Octal-Bus Transceiver, Three-State, Non-Inverting November 1997 - Revised May 2003 Features Description • Buffered Inputs The CD54HC245, CD54HCT245, and CD74HC245, CD74HCT245 are high-speed octal three-state bidirectional [ /Title • Three-State Outputs transceivers intended for two-way asynchronous (CD54 • Bus Line Driving Capability communication between data buses. They have high drive HC245 current outputs which enable high-speed operation while • Typical Propagation Delay (A to B, B to A) 9ns at VCC driving large bus capacitances. They provide the low power , = 5V, CL = 15pF, TA = 25oC consumption of standard CMOS circuits with speeds and CD54 • Fanout (Over Temperature Range) drive capabilities comparable to that of LSTTL circuits. HCT24 - Standard Outputs. . . . . . . . . . . . . . .10 LSTTL Loads The CD54HC245, CD54HCT245, CD74HC245 and 5, - Bus Driver Outputs . . . . . . . . . . . . .15 LSTTL Loads CD74HCT245 allow data transmission of the B bus or from CD74 theBbustotheAbus.Thelogiclevelatthedirectioninput • Wide Operating Temperature Range . . .-55oC to 125oC HC245 (DIR) determines the direction. The output enable input • Balanced Propagation Delay and Transition Times (OE), when high, puts the I/O ports in the high-impedance , state. CD74 • Significant Power Reduction Compared to LSTTL Logic ICs The HC/HCT245 is similar in operation to the HC/HCT640 HCT24 and the HC/HCT643. 5) • HC Types /Sub- - 2V to 6V Operation Ordering Information ject - High Noise Immunity: NIL = 30%, NIH = 30% of VCC (High at VCC = 5V PART NUMBER RATNEGMEP (.oC) PACKAGE Speed • HCT Types - 4.5V to 5.5V Operation CD54HC245F3A -55 to 125 20 Ld CERDIP - Direct LSTTL Input Logic Compatibility, CD54HCT245F3A -55 to 125 20 Ld CERDIP VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il≤1µA at VOL, VOH CD74HC245E -55 to 125 20 Ld PDIP CD74HC245M -55 to 125 20 Ld SOIC CD74HC245M96 -55 to 125 20 Ld SOIC Pinout CD74HCT245E -55 to 125 20 Ld PDIP CD54HC245, CD54HCT245 (CERDIP) CD74HCT245M -55 to 125 20 Ld SOIC CD74HC245, CD74HCT245 (PDIP, SOIC) CD74HCT245M96 -55 to 125 20 Ld SOIC TOP VIEW NOTE: Whenordering,usetheentirepartnumber.Thesuffix96 denotes tape and reel. DIR 1 20 VCC A0 2 19 OE A1 3 18 B0 A2 4 17 B1 A3 5 16 B2 A4 6 15 B3 A5 7 14 B4 A6 8 13 B5 A7 9 12 B6 GND 10 11 B7 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated 1

CCDD5544HHCC224455,, CCDD7744HHCC224455,, CCDD5544HHCCTT224455,, CCDD7744HHCCTT224455 Functional Diagram 2 18 A0 B0 3 17 A1 B1 4 16 A2 B2 5 15 A3 B3 6 14 A4 B4 7 13 A5 B5 8 12 A6 B6 9 11 A7 B7 1 DIR 19 OE TRUTH TABLE CONTROL INPUTS OE DIR OPERATION L L B Data to A Bus L H A Data to B Bus H X Isolation H = High Level, L = Low Level, X = Irrelevant To prevent excess currents in the High-Z (Isolation) modes all I/O terminals should be terminated with 10kΩ to 1MΩ resistors. 2

CCDD5544HHCC224455,, CCDD7744HHCC224455,, CCDD5544HHCCTT224455,, CCDD7744HHCCTT224455 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Thermal Resistance (Typical, Note 1). . . . . . . . . . . . . . . . .θJA (oC/W) DC Input Diode Current, IIK E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 DC Output Diode Current, IOK Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC DC Drain Current, per Output, IO Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA (SOIC - Lead Tips Only) DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . .-55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION:Stressesabovethoselistedin“AbsoluteMaximumRatings”maycausepermanentdamagetothedevice.Thisisastressonlyratingandoperation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. 1. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS 25oC -40oC TO 85oC -55oCTO125oC VCC PARAMETER SYMBOL VI(V) IO(mA) (V) MIN TYP MAX MIN MAX MIN MAX UNITS HC TYPES High Level Input VIH - - 2 1.5 - - 1.5 - 1.5 - V Voltage 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V Low Level Input VIL - - 2 - - 0.5 - 0.5 - 0.5 V Voltage 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V High Level Output VOH VIHorVIL -0.02 2 1.9 - - 1.9 - 1.9 - V Voltage -0.02 4.5 4.4 - - 4.4 - 4.4 - V CMOS Loads -0.02 6 5.9 - - 5.9 - 5.9 - V High Level Output - - - - - - - - - V Voltage -4 4.5 3.98 - - 3.84 - 3.7 - V TTL Loads -5.2 6 5.48 - - 5.34 - 5.2 - V Low Level Output VOL VIHorVIL 0.02 2 - - 0.1 - 0.1 - 0.1 V Voltage 0.02 4.5 - - 0.1 - 0.1 - 0.1 V CMOS Loads 0.02 6 - - 0.1 - 0.1 - 0.1 V Low Level Output - - - - - - - - - V Voltage 4 4.5 - - 0.26 - 0.33 - 0.4 V TTL Loads 5.2 6 - - 0.26 - 0.33 - 0.4 V Input Leakage II VCC or - 6 - - ±0.1 - ±1 - ±1 µA Current GND Quiescent Device ICC VCC or 0 6 - - 8 - 80 - 160 µA Current GND 3

CCDD5544HHCC224455,, CCDD7744HHCC224455,, CCDD5544HHCCTT224455,, CCDD7744HHCCTT224455 DC Electrical Specifications (Continued) TEST CONDITIONS 25oC -40oC TO 85oC -55oCTO125oC VCC PARAMETER SYMBOL VI(V) IO(mA) (V) MIN TYP MAX MIN MAX MIN MAX UNITS Three-State Leakage IOZ VILorVIH VO = 6 - - ±0.5 - ±5 - ±10 µA Current VCC or GND HCT TYPES High Level Input VIH - - 4.5 to 2 - - 2 - 2 - V Voltage 5.5 Low Level Input VIL - - 4.5 to - - 0.8 - 0.8 - 0.8 V Voltage 5.5 High Level Output VOH VIHorVIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V Voltage CMOS Loads High Level Output -4 4.5 3.98 - - 3.84 - 3.7 - V Voltage TTL Loads Low Level Output VOL VIHorVIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V Voltage CMOS Loads Low Level Output 4 4.5 - - 0.26 - 0.33 - 0.4 V Voltage TTL Loads Input Leakage II VCCand 0 5.5 - - ±0.1 - ±1 - ±1 µA Current GND Quiescent Device ICC VCC or 0 5.5 - - 8 - 80 - 160 µA Current GND Three-State Leakage IOZ VILorVIH VO = 6 - - ±0.5 - ±5 - ±10 µA Current VCC or GND Additional Quiescent ∆ICC VCC - 4.5 to - 100 360 - 450 - 490 µA Device Current Per (Note 2) -2.1 5.5 Input Pin: 1 Unit Load NOTE: 2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS An or Bn 0.4 OE 1.5 DIR 0.9 NOTE: UnitLoadis∆ICClimitspecifiedinDCElectricalTable,e.g., 360µA max at 25oC. 4

CCDD5544HHCC224455,, CCDD7744HHCC224455,, CCDD5544HHCCTT224455,, CCDD7744HHCCTT224455 Switching Specifications CL = 50pF, Input tr, tf= 6ns -40oC TO -55oC TO 25oC 85oC 125oC TEST PARAMETER SYMBOL CONDITIONS VCC(V) MIN TYP MAX MIN MAX MIN MAX UNITS HC TYPES Propagation Delay tPHL, tPLH CL = 50pF Data to Output 2 - - 110 - 140 - 165 ns 4.5 - - 22 - 28 - 33 ns CL = 15pF 5 - 9 - - - - - ns CL = 50pF 6 - - 19 - 24 - 28 ns Output Disable to Output tPHL, tPLH CL = 50pF 2 - - 150 - 190 - 225 ns 4.5 - - 30 - 38 - 45 ns CL = 15pF 5 - 12 - - - - - ns CL = 50pF 6 - - 26 - 33 - 38 ns Output Enable to Output tPHL, tPLH CL = 50pF 2 - - 150 - 190 - 225 ns 4.5 - - 30 - 38 - 45 ns CL = 15pF 5 - 12 - - - - - ns CL = 50pF 6 - - 26 - 33 - 38 ns Output Transition Time tTHL, tTLH CL = 50pF 2 - - 60 - 75 - 90 ns 4.5 - - 12 - 15 - 18 ns 6 - - 10 - 13 - 15 ns Input Capacitance CIN CL = 50pF - 10 - 10 - 10 - 10 pF Three-State Output CO - - - - 20 - 20 - 20 pF Capacitance Power Dissipation Capacitance CPD - 5 - 53 - - - - - pF (Notes 3, 4) HCT TYPES Propagation Delay Data to Output tPHL, tPLH CL = 50pF 4.5 - - 26 - 33 - 39 ns CL = 15pF 5 - 10 - - - - - ns Output Disable to Output tPHL, tPLH CL = 50pF 4.5 - - 30 - 38 - 45 ns CL = 15pF 5 - 12 - - - - - ns Output Enable to Output tPHL, tPLH CL = 50pF 4.5 - - 32 - 40 - 48 ns CL = 15pF 5 - 13 - - - - - ns Output Transition Time tTHL, tTLH CL = 50pF 4.5 - - 12 - 15 - 18 ns Input Capacitance CIN CL = 50pF - 10 - 10 - 10 - 10 pF Three-State Output CO - - - - 20 - 20 - 20 pF Capacitance Power Dissipation Capacitance CPD - 5 - 55 - - - - - pF (Notes 3, 4) NOTES: 3. CPD is used to determine the dynamic power consumption, per channel. 4. PD = VCC2 fi (CPD + CL) where fi =Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. 5

CCDD5544HHCC224455,, CCDD7744HHCC224455,, CCDD5544HHCCTT224455,, CCDD7744HHCCTT224455 Test Circuits and Waveforms tr = 6ns tf = 6ns tr = 6ns tf = 6ns 90% VCC 2.7V 3V INPUT 50% INPUT 1.3V 10% GND 0.3V GND tTHL tTLH tTHL tTLH 90% 90% 50% 1.3V INVERTING INVERTING 10% 10% OUTPUT OUTPUT tPHL tPLH tPHL tPLH FIGURE1. HCTRANSITIONTIMESANDPROPAGATION FIGURE2. HCTTRANSITIONTIMESANDPROPAGATION DELAY TIMES, COMBINATION LOGIC DELAY TIMES, COMBINATION LOGIC 6ns 6ns tr 6ns tf 6ns OUTPUT 90% VCC OUTPUT 2.7 3V DISABLE 50% DISABLE 1.3 10% 0.3 GND GND tPLZ tPZL tPLZ tPZL OUTPUT LOW OUTPUT LOW TO OFF 10% 50% TO OFF 10% 1.3V tPHZ tPZH tPHZ 90% 90% tPZH OUTPUT HIGH 50% OUTPUT HIGH TO OFF TO OFF 1.3V OUTPUTS OUTPUTS OUTPUTS OUTPUTS OUTPUTS OUTPUTS ENABLED DISABLED ENABLED ENABLED DISABLED ENABLED FIGURE3. HCTHREE-STATEPROPAGATIONDELAY FIGURE4. HCTTHREE-STATEPROPAGATIONDELAY WAVEFORM WAVEFORM OTHER OUTPUT INPUTS IC WITH RL = 1kΩ TIED HIGH THREE- VCC FOR tPLZ AND tPZL OR LOW STATE CL GND FOR tPHZ AND tPZH OUTPUT 50pF OUTPUT DISABLE NOTE: OpendrainwaveformstPLZandtPZLarethesameasthoseforthree-stateshownontheleft.ThetestcircuitisOutputRL=1kΩto VCC, CL = 50pF. FIGURE 5. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT 6

PACKAGE OPTION ADDENDUM www.ti.com 22-Jul-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) CD54HC245F ACTIVE CDIP J 20 1 TBD SNPB N / A for Pkg Type -55 to 125 CD54HC245F CD54HC245F3A ACTIVE CDIP J 20 1 TBD SNPB N / A for Pkg Type -55 to 125 8408501RA CD54HC245F3A CD54HCT245F ACTIVE CDIP J 20 1 TBD SNPB N / A for Pkg Type -55 to 125 CD54HCT245F CD54HCT245F3A ACTIVE CDIP J 20 1 TBD SNPB N / A for Pkg Type -55 to 125 8550601RA CD54HCT245F3A CD74HC245E ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type -55 to 125 CD74HC245E (RoHS) CD74HC245M ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC245M & no Sb/Br) CD74HC245M96 ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC245M & no Sb/Br) CD74HCT245E ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type -55 to 125 CD74HCT245E (RoHS) CD74HCT245EE4 ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type -55 to 125 CD74HCT245E (RoHS) CD74HCT245M ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT245M & no Sb/Br) CD74HCT245M96 ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT245M & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 22-Jul-2020 (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF CD54HC245, CD54HCT245, CD74HC245, CD74HCT245 : •Catalog: CD74HC245, CD74HCT245 •Military: CD54HC245, CD54HCT245 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) CD74HC245M96 SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 CD74HCT245M96 SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) CD74HC245M96 SOIC DW 20 2000 367.0 367.0 45.0 CD74HCT245M96 SOIC DW 20 2000 367.0 367.0 45.0 PackMaterials-Page2

None

None

PACKAGE OUTLINE DW0020A SOIC - 2.65 mm max height SCALE 1.200 SOIC C 10.63 SEATING PLANE TYP 9.97 A PIN 1 ID 0.1 C AREA 18X 1.27 20 1 13.0 2X 12.6 11.43 NOTE 3 10 11 0.51 20X 7.6 0.31 2.65 MAX B 7.4 0.25 C A B NOTE 4 0.33 TYP 0.10 0.25 SEE DETAIL A GAGE PLANE 0.3 1.27 0 - 8 0.1 0.40 DETAIL A TYPICAL 4220724/A 05/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS-013. www.ti.com

EXAMPLE BOARD LAYOUT DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM (R0.05) TYP 10 11 (9.3) LAND PATTERN EXAMPLE SCALE:6X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220724/A 05/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM 10 11 (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4220724/A 05/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

IMPORTANTNOTICEANDDISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated