CD54HC173, CD74HC173, CD54HCT173, CD74HCT173 Data sheet acquired from Harris Semiconductor SCHS158E High-Speed CMOS Logic February 1998 - Revised October 2003 Quad D-Type Flip-Flop, Three-State Features Description • Three-State Buffered Outputs The ’HC173 and ’HCT173 high speed three-state quad D- typeflip-flopsarefabricatedwithsilicongateCMOStechnol- [ /Title • Gated Input and Output Enables ogy. They possess the low power consumption of standard (CD74H • Fanout (Over Temperature Range) CMOS Integrated circuits, and can operate at speeds com- - Standard Outputs. . . . . . . . . . . . . . .10 LSTTL Loads parable to the equivalent low power Schottky devices. The C173, - Bus Driver Outputs . . . . . . . . . . . . .15 LSTTL Loads bufferedoutputscandrive15LSTTLloads.Thelargeoutput CD74H • Wide Operating Temperature Range . . .-55oC to 125oC drivecapabilityandthree-statefeaturemakethesepartside- CT173) ally suited for interfacing with bus lines in bus oriented sys- • Balanced Propagation Delay and Transition Times /Subject tems. • Significant Power Reduction Compared to LSTTL (High ThefourD-typeflip-flopsoperatesynchronouslyfromacom- Logic ICs Speed mon clock. The outputs are in the three-state mode when • HC Types eitherofthetwooutputdisablepinsareatthelogic“1”level. CMOS - 2V to 6V Operation The input ENABLES allow the flip-flops to remain in their Logic - High Noise Immunity: NIL = 30%, NIH = 30% of VCC presentstateswithouthavingtodisrupttheclockIfeitherof Quad D- at VCC = 5V the 2 input ENABLES are taken to a logic “1” level, the Q Type • HCT Types outputs are fed back to the inputs, forcing the flip-flops to - 4.5V to 5.5V Operation remain in the same state. Reset is enabled by taking the - Direct LSTTL Input Logic Compatibility, MASTER RESET (MR) input to a logic “1” level. The data VIL= 0.8V (Max), VIH = 2V (Min) outputschangestateonthepositivegoingedgeoftheclock. - CMOS Input Compatibility, Il≤1µA at VOL, VOH The’HCT173logicfamilyisfunctionally,aswellaspincom- patible with the standard LS logic family. Pinout Ordering Information CD54HC173, CD54HCT173 TEMP. RANGE (CERDIP) PART NUMBER (oC) PACKAGE CD74HC173 (PDIP, SOIC, SOP, TSSOP) CD54HC173F3A -55 to 125 16 Ld CERDIP CD74HCT173 (PDIP, SOIC) CD54HCT173F3A -55 to 125 16 Ld CERDIP TOP VIEW CD74HC173E -55 to 125 16 Ld PDIP OE 1 16 VCC CD74HC173M -55 to 125 16 Ld SOIC OE2 2 15 MR CD74HC173MT -55 to 125 16 Ld SOIC Q0 3 14 D0 CD74HC173M96 -55 to 125 16 Ld SOIC Q1 4 13 D1 Q2 5 12 D2 CD74HC173NSR -55 to 125 16 Ld SOP Q3 6 11 D3 CD74HC173PW -55 to 125 16 Ld TSSOP CP 7 10 E2 CD74HC173PWR -55 to 125 16 Ld TSSOP GND 8 9 E1 CD74HC173PWT -55 to 125 16 Ld TSSOP CD74HCT173E -55 to 125 16 Ld PDIP CD74HCT173M -55 to 125 16 Ld SOIC CD74HCT173MT -55 to 125 16 Ld SOIC CD74HCT173M96 -55 to 125 16 Ld SOIC NOTE: Whenordering,usetheentirepartnumber.Thesuffixes96 andRdenotetapeandreel.ThesuffixTdenotesasmall-quantity reel of 250. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated 1

CD54HC173, CD74HC173, CD54HCT173, CD74HCT173 Functional Diagram E1 E2 10 9 14 D0 3 13 Q0 D1 4 12 Q1 D2 5 11 Q2 D3 6 7 Q3 CP 15 1 2 MR OE1 OE2 TRUTH TABLE INPUTS DATA ENABLE DATA OUTPUT MR CP E1 E2 D Qn H X X X X L L L X X X Q0 L ↑ H X X Q0 L ↑ X H X Q0 L ↑ L L L L L ↑ L L H H H= High Voltage Level L= Low Voltage Level X= Irrelevant ↑= Transition from Low to High Level Q0=Level Before the Indicated Steady-State Input Conditions Were Established NOTE: 1. WheneitherOE1orOE2(orboth)is(are)high,theoutputisdis- abledtothehigh-impedancestate,however,sequentialopera- tion of the flip-flops is not affected. 2

CD54HC173, CD74HC173, CD54HCT173, CD74HCT173 Logic Diagram 9 E1 10 E2 VCC D Q 14 P D0 3 Q0 7 CP CP Q N R 15 MR 1 OE1 2 OE2 13 4 D1 Q1 12 3 CIRCUITS IDENTICAL TO ABOVE CIRCUIT 5 D2 IN DASHED ENCLOSURE Q2 11 6 D3 Q3 3

CD54HC173, CD74HC173, CD54HCT173, CD74HCT173 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Package Thermal Impedance,θJA(see Note 2): DC Input Diode Current, IIK E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67oC/W For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73oC/W ο DC Output Diode Current, IOK NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 C/W For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 108oC/W DC Output Source or Sink Current per Output Pin, IO Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±70mA Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . .-55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION:Stressesabovethoselistedin“AbsoluteMaximumRatings”maycausepermanentdamagetothedevice.Thisisastressonlyratingandoperation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 2. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC PARAMETER SYMBOL VI(V) IO(mA) VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS HC TYPES High Level Input VIH - - 2 1.5 - - 1.5 - 1.5 - V Voltage 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V Low Level Input VIL - - 2 - - 0.5 - 0.5 - 0.5 V Voltage 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V High Level Output VOH VIH or -0.02 2 1.9 - - 1.9 - 1.9 - V Voltage VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V CMOS Loads -0.02 6 5.9 - - 5.9 - 5.9 - V High Level Output -6 4.5 3.98 - - 3.84 - 3.7 - V Voltage -7.8 6 5.48 - - 5.34 - 5.2 - V TTL Loads Low Level Output VOL VIH or 0.02 2 - - 0.1 - 0.1 - 0.1 V Voltage VIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V CMOS Loads 0.02 6 - - 0.1 - 0.1 - 0.1 V Low Level Output 6 4.5 - - 0.26 - 0.33 - 0.4 V Voltage 7.8 6 - - 0.26 - 0.33 - 0.4 V TTL Loads Input Leakage II VCC or - 6 - - ±0.1 - ±1 - ±1 µA Current GND Quiescent Device ICC VCC or 0 6 - - 8 - 80 - 160 µA Current GND 4

CD54HC173, CD74HC173, CD54HCT173, CD74HCT173 DC Electrical Specifications (Continued) TEST CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC PARAMETER SYMBOL VI(V) IO(mA) VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS Three-State Leakage IOZ VIL or - 6 - - ±0.5 - ±0.5 - ±10 µA Current VIH HCT TYPES High Level Input VIH - - 4.5 to 2 - - 2 - 2 - V Voltage 5.5 Low Level Input VIL - - 4.5 to - - 0.8 - 0.8 - 0.8 V Voltage 5.5 High Level Output VOH VIH or -0.02 4.5 4.4 - - 4.4 - 4.4 - V Voltage VIL CMOS Loads High Level Output -6 4.5 3.98 - - 3.84 - 3.7 - V Voltage TTL Loads Low Level Output VOL VIH or 0.02 4.5 - - 0.1 - 0.1 - 0.1 V Voltage VIL CMOS Loads Low Level Output 6 4.5 - - 0.26 - 0.33 - 0.4 V Voltage TTL Loads Input Leakage II VCC to 0 5.5 - - ±0.1 - ±1 - ±1 µA Current GND Quiescent Device ICC VCC or 0 5.5 - - 8 - 80 - 160 µA Current GND Additional Quiescent ∆ICC VCC - 4.5 to - 100 360 - 450 - 490 µA Device Current Per (Note 3) -2.1 5.5 Input Pin: 1 Unit Load Three-State Leakage IOZ VIL or - 5.5 - - ±0.5 - ±5.0 - ±10 µA Current VIH NOTE: 3. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS D0-D3 0.15 E1 andE2 0.15 CP 0.25 MR 0.2 OE1 andOE2 0.5 NOTE: Unit Load is∆ICClimit specified in DC Electrical Specifications table, e.g., 360µA max at 25oC. 5

CD54HC173, CD74HC173, CD54HCT173, CD74HCT173 Switching Specifications Input tr, tf = 6ns 25oC -40oC TO 85oC -55oCTO125oC TEST PARAMETER SYMBOL CONDITIONS VCC (V) TYP MAX MAX MAX UNITS HC TYPES Propagation Delay, Clock to tPLH, tPHL CL= 50pF 2 - 200 250 300 ns Output 4.5 - 40 50 60 ns CL= 15pF 5 17 - - - ns CL = 50pF 6 - 34 43 51 ns Propagation Delay, MR to tPHL CL= 50pF 2 - 175 220 265 ns Output 4.5 - 35 44 53 ns CL= 15pF 5 12 - - - ns CL = 50pF 6 - 30 37 45 ns Propagation Delay Output tPLZ, tPHZ CL = 50pF 2 150 190 225 ns Enable to Q (Figure 6) tPZL, tPZH CL= 50pF 4.5 30 38 45 ns CL= 15pF 5 12 - - - ns CL = 50pF 6 26 33 38 ns Output Transition Times tTLH, tTHL CL= 50pF 2 - 60 75 90 ns 4.5 - 12 15 18 ns 6 - 10 13 15 ns Maximum Clock Frequency fMAX CL= 15pF 5 60 - - - MHz Input Capacitance CIN - - - 10 10 10 pF Three-State Output CO - - - 10 10 10 pF Capacitance Power Dissipation CPD - 5 29 - - - pF Capacitance (Notes 4, 5) HCT TYPES Propagation Delay, Clock to tPLH, tPHL CL= 50pF 4.5 - 40 50 60 ns Output CL= 15pF 5 17 - - - ns Propagation Delay, MR to tPHL CL= 50pF 4.5 - 44 55 66 ns Output CL= 15pF 5 18 - - - ns Propagation Delay Output tPZL, tPZH CL = 50pF 2 150 190 225 ns Enable to Q (Figure 6) CL= 50pF 4.5 30 38 45 ns CL= 15pF 5 14 - - - ns CL = 50pF 6 26 33 38 ns Output Transition Times tTLH, tTHL CL= 50pF 4.5 - 15 19 22 ns Maximum Clock Frequency fMAX CL= 15pF 5 60 - - - MHz Input Capacitance CIN - - - 10 10 10 pF Power Dissipation CPD - 5 34 - - - pF Capacitance (Notes 4, 5) NOTES: 4. CPD is used to determine the dynamic power consumption, per package. 5. PD=VCC2fi+∑(CLVCC2+fO)wherefi=InputFrequency,fO=InputFrequency,CL=OutputLoadCapacitance,VCC=SupplyVoltage. 6

CD54HC173, CD74HC173, CD54HCT173, CD74HCT173 Prerequisite For Switching Specifications 25oC -40oC TO 85oC -55oC TO 125oC PARAMETER SYMBOL VCC (V) MIN MAX MIN MAX MIN MAX UNITS HC TYPES Maximum Clock Frequency fMAX 2 6 - 5 - 4 - MHz 4.5 30 - 24 - 20 - MHz 6 35 - 28 - 24 - MHz MR Pulse Width tw 2 80 - 100 - 120 - ns 4.5 16 - 20 - 24 - ns 6 14 - 17 - 20 - ns Clock Pulse Width tw 2 80 - 100 - 120 - ns 4.5 16 - 20 - 24 - ns 6 14 - 17 - 20 - ns Set-up Time, Data to Clock tSU 2 60 - 75 - 90 - ns andE to Clock 4.5 12 - 15 - 18 - ns 6 10 - 13 - 15 - ns Hold Time, Data to Clock tH 2 3 - 3 - 3 - ns 4.5 3 - 3 - 3 - ns 6 3 - 3 - 3 - ns Hold Time,E to Clock tH 2 0 - 0 - 0 - ns 4.5 0 - 0 - 0 - ns 6 0 - 0 - 0 - ns Removal Time, MR to Clock tREM 2 60 - 75 - 90 - ns 4.5 12 - 15 - 18 - ns 6 10 - 13 - 15 - ns HCT TYPES Maximum Clock Frequency fMAX 4.5 20 - 16 - 13 - MHz MR Pulse Width tw 4.5 15 - 19 - 22 - ns Clock Pulse Width tw 4.5 25 - 31 - 38 - ns Set-up Time,E to Clock tSU 4.5 12 - 15 - 18 - ns Set-up Time, Data to Clock tSU 4.5 18 - 23 - 27 - ns Hold Time, Data to Clock tH 4.5 0 - 0 - 0 - ns Hold Time,E to Clock tH 4.5 0 - 0 - 0 - ns Removal Time, MR to Clock tREM 4.5 12 - 15 - 18 - ns 7

CD54HC173, CD74HC173, CD54HCT173, CD74HCT173 Test Circuits and Waveforms I trCL tfCL tWL+ tWH=fCIL trCL= 6ns tfCL= 6ns tWL+ tWH=fCL VCC 3V 90% 2.7V CLOCK 50% 50% 50% CLOCK 1.3V 1.3V 1.3V 10% 10% GND 0.3V 0.3V GND tWL tWH tWL tWH NOTE: Outputs should be switching from 10% VCC to 90% VCC in NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordancewithdevicetruthtable.ForfMAX,inputdutycycle=50%. accordancewithdevicetruthtable.ForfMAX,inputdutycycle=50%. FIGURE1. HCCLOCKPULSERISEANDFALLTIMESAND FIGURE2. HCTCLOCKPULSERISEANDFALLTIMESAND PULSE WIDTH PULSE WIDTH tr = 6ns tf = 6ns tr = 6ns tf = 6ns 90% VCC 2.7V 3V INPUT 50% INPUT 1.3V 10% GND 0.3V GND tTHL tTLH tTHL tTLH 90% 90% 50% 1.3V INVERTING INVERTING 10% 10% OUTPUT OUTPUT tPHL tPLH tPHL tPLH FIGURE3. HCANDHCUTRANSITIONTIMESANDPROPAGA- FIGURE4. HCTTRANSITIONTIMESANDPROPAGATION TION DELAY TIMES, COMBINATION LOGIC DELAY TIMES, COMBINATION LOGIC trCL tfCL trCL tfCL 90% VCC CLOCK 2.7V 3V CLOCK 50% 1.3V INPUT 10% INPUT 0.3V GND GND tH(H) tH(L) tH(H) tH(L) VCC DATA 3V INDPAUTAT 50% INPUT 1.3V 1.3V 1.3V GND GND tSU(H) tSU(L) tSU(H) tSU(L) tTLH tTHL tTLH tTHL 90% 90% 90% 90% 50% OUTPUT OUTPUT 1.3V 1.3V 10% 10% tPLH tPHL tPLH tPHL tREM tREM VCC 3V SET, RESET 50% SET, RESET 1.3V OR PRESET GND OR PRESET GND IC IC CL CL 50pF 50pF FIGURE5. HCSETUPTIMES,HOLDTIMES,REMOVALTIME, FIGURE6. HCTSETUPTIMES,HOLDTIMES,REMOVALTIME, AND PROPAGATION DELAY TIMES FOR EDGE AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS TRIGGERED SEQUENTIAL LOGIC CIRCUITS 8

CD54HC173, CD74HC173, CD54HCT173, CD74HCT173 Test Circuits and Waveforms (Continued) 6ns 6ns tr 6ns tf 6ns OUTPUT 90% VCC OUTPUT 2.7 3V DISABLE 50% DISABLE 1.3 10% 0.3 GND GND tPLZ tPZL tPLZ tPZL OUTPUT LOW OUTPUT LOW TO OFF 50% TO OFF 1.3V 10% 10% tPHZ 90% tPZH tPHZ 90% tPZH OUTPUT HIGH OUTPUT HIGH 50% TO OFF TO OFF 1.3V OUTPUTS OUTPUTS OUTPUTS OUTPUTS OUTPUTS OUTPUTS ENABLED DISABLED ENABLED ENABLED DISABLED ENABLED FIGURE7. HCTHREE-STATEPROPAGATIONDELAY FIGURE8. HCTTHREE-STATEPROPAGATIONDELAY WAVEFORM WAVEFORM OTHER OUTPUT INPUTS IC WITH RL = 1kΩ TIED HIGH THREE- VCC FOR tPLZ AND tPZL OR LOW STATE CL GND FOR tPHZ AND tPZH OUTPUT 50pF OUTPUT DISABLE NOTE: OpendrainwaveformstPLZandtPZLarethesameasthoseforthree-stateshownontheleft.ThetestcircuitisOutputRL=1kΩto VCC, CL = 50pF. FIGURE 9. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT 9

PACKAGE OPTION ADDENDUM www.ti.com 28-Jul-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) 5962-8682501EA ACTIVE CDIP J 16 1 TBD SNPB N / A for Pkg Type -55 to 125 5962-8682501EA CD54HC173F3A 5962-8875901EA ACTIVE CDIP J 16 1 TBD SNPB N / A for Pkg Type -55 to 125 5962-8875901EA CD54HCT173F3A CD54HC173F ACTIVE CDIP J 16 1 TBD SNPB N / A for Pkg Type -55 to 125 CD54HC173F CD54HC173F3A ACTIVE CDIP J 16 1 TBD SNPB N / A for Pkg Type -55 to 125 5962-8682501EA CD54HC173F3A CD54HCT173F3A ACTIVE CDIP J 16 1 TBD SNPB N / A for Pkg Type -55 to 125 5962-8875901EA CD54HCT173F3A CD74HC173E ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -55 to 125 CD74HC173E & no Sb/Br) CD74HC173M ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC173M & no Sb/Br) CD74HC173M96 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC173M & no Sb/Br) CD74HC173M96G4 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC173M & no Sb/Br) CD74HC173MG4 ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC173M & no Sb/Br) CD74HC173PW ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HJ173 & no Sb/Br) CD74HC173PWR ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HJ173 & no Sb/Br) CD74HCT173E ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -55 to 125 CD74HCT173E & no Sb/Br) CD74HCT173M ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT173M & no Sb/Br) CD74HCT173M96 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT173M & no Sb/Br) CD74HCT173MG4 ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT173M & no Sb/Br) (1) The marketing status values are defined as follows: Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 28-Jul-2020 ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF CD54HC173, CD54HCT173, CD74HC173, CD74HCT173 : •Catalog: CD74HC173, CD74HCT173 •Military: CD54HC173, CD54HCT173 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 28-Jul-2020 •Military - QML certified for Military and Defense Applications Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 18-Aug-2014 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) CD74HC173M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD74HC173PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 CD74HCT173M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 18-Aug-2014 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) CD74HC173M96 SOIC D 16 2500 333.2 345.9 28.6 CD74HC173PWR TSSOP PW 16 2000 367.0 367.0 35.0 CD74HCT173M96 SOIC D 16 2500 333.2 345.9 28.6 PackMaterials-Page2

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PACKAGE OUTLINE PW0016A TSSOP - 1.2 mm max height SCALE 2.500 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 14X 0.65 16 1 2X 5.1 4.55 4.9 NOTE 3 8 9 0.30 B 4.5 16X 0.19 1.2 MAX 4.3 0.1 C A B NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.05 0.75 0.50 0 -8 DETA 20AIL A TYPICAL 4220204/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL UNDER SOLDER MASK OPENING METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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