CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237 Data sheet acquired from Harris Semiconductor SCHS146F High-Speed CMOS Logic, 3- to 8-Line March 1998 - Revised October 2003 Decoder/Demultiplexer with Address Latches Features Bothcircuitshavethreebinaryselectinputs(A0,A1andA2) that can be latched by an active High Latch Enable (LE) • Select One of Eight Data Outputs signal to isolate the outputs from select-input changes. A - Active Low for CD74HC137 and CD74HCT137 “Low” LE makes the output transparent to the input and the [ /Title - Active High for ’HC237 and CD74HCT237 circuit functions as a one-of-eight decoder. Two Output (CD74 Enable inputs (OE1 and OE0) are provided to simplify HC137 • l/O Port or Memory Selector cascading and to facilitate demultiplexing. The , • Two Enable Inputs to Simplify Cascading demultiplexingfunctionisaccomplishedbyusingtheA0,A1, CD74 A2 inputs to select the desired output and using one of the • Typical Propagation Delay of 13ns at VCC = 5V, other Output Enable inputs as the data input while holding HCT13 15pF, TA = 25oC (CD74HC237) the other Output Enable input in its active state. In the 7, CD74HC137 and CD74HCT137 the selected output is a • Fanout (Over Temperature Range) CD74 “Low”;inthe’HC237andCD74HCT237theselectedoutputis - Standard Outputs. . . . . . . . . . . . . . .10 LSTTL Loads a “High”. HC237 - Bus Driver Outputs . . . . . . . . . . . . .15 LSTTL Loads , • Wide Operating Temperature Range . . .-55oC to 125oC Ordering Information CD74 • Balanced Propagation Delay and Transition Times HCT23 TEMP. RANGE PART NUMBER (oC) PACKAGE 7) • Significant Power Reduction Compared to LSTTL Logic ICs /Sub- CD54HC237F3A -55 to 125 16 Ld CERDIP ject • HC Types CD74HC137E -55 to 125 16 Ld PDIP - 2V to 6V Operation (High CD74HC137PW -55 to 125 16 Ld TSSOP Speed - High Noise Immunity: NIL = 30%, NIH = 30%, of VCC at VCC = 5V CD74HC137PWR -55 to 125 16 Ld TSSOP • HCT Types CD74HC137PWT -55 to 125 16 Ld TSSOP - 4.5V to 5.5V Operation CD74HC237E -55 to 125 16 Ld PDIP - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) CD74HC237M -55 to 125 16 Ld SOIC - CMOS Input Compatibility, Il≤1µA at VOL, VOH CD74HC237MT -55 to 125 16 Ld SOIC Description CD74HC237M96 -55 to 125 16 Ld SOIC The CD74HC137, CD74HCT137, ’HC237, and CD74HC237NSR -55 to 125 16 Ld SOP CD74HCT237 are high speed silicon gate CMOS decoders well suited to memory address decoding or data routing CD74HC237PW -55 to 125 16 Ld TSSOP applications. Both circuits feature low power consumption CD74HC237PWR -55 to 125 16 Ld TSSOP usually associated with CMOS circuitry, yet have speeds comparable to low power Schottky TTL logic. CD74HC237PWT -55 to 125 16 Ld TSSOP CD74HCT137E -55 to 125 16 Ld PDIP CD74HCT137MT -55 to 125 16 Ld SOIC CD74HCT137M96 -55 to 125 16 Ld SOIC CD74HCT237E -55 to 125 16 Ld PDIP NOTE: Whenordering,usetheentirepartnumber.Thesuffixes96 andRdenotetapeandreel.ThesuffixTdenotesasmall-quantity reel of 250. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated 1

CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237 Pinout Functional Diagram CD54HC237 (CERDIP) HC/HCTHC/HCT CD74HC137 (PDIP, TSSOP) 237 137 CD74HCT137 (PDIP, SOIC) A0 1 15 Y0 Y0 CD74HC237 (PDIP, SOIC, SOP, TSSOP) 2 3-BIT 14 CD74HCT237 (PDIP) A1 LATCH 1 OF 8 Y1 Y1 TOP VIEW 3 DECODER 13 A2 Y2 Y2 A0 1 16 VCC 4 12 Y3 Y3 A1 2 15 Y0 LE 11 A3 3 14 Y1 Y4 Y4 10 LE 4 13 Y2 Y5 Y5 OE1 5 12 Y3 5 9 OE1 Y6 Y6 OE0 6 11 Y4 6 7 Y7 7 10 Y5 OE0 Y7 Y7 GND 8 9 Y6 GND = 8 VCC= 16 ’HC137, ’HCT137 TRUTH TABLE INPUTS OUTPUTS LE OE0 OE1 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 X X H X X X H H H H H H H H X L X X X X H H H H H H H H L H L L L L L H H H H H H H L H L L L H H L H H H H H H L H L L H L H H L H H H H H L H L L H H H H H L H H H H L H L H L L H H H H L H H H L H L H L H H H H H H L H H L H L H H L H H H H H H L H L H L H H H H H H H H H H L H H L X X X Depends upon the address previously applied while LE was at a logic low. H = High Voltage Level, L = Low Voltage Level, X = Don’t Care ’HC237, ’HCT237 TRUTH TABLE INPUTS OUTPUTS LE OE0 OE1 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 X X H X X X L L L L L L L L X L X X X X L L L L L L L L L H L L L L H L L L L L L L L H L L L H L H L L L L L L L H L L H L L L H L L L L L L H L L H H L L L H L L L L L H L H L L L L L L H L L L L H L H L H L L L L L H L L L H L H H L L L L L L L H L L H L H H H L L L L L L L H H H L X X X Depends upon the address previously applied while LE was at a logic low. H = High Voltage Level, L = Low Voltage Level, X = Don’t Care 2

CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237 Functional Block Diagram A0 15 LE Y0 1 p A0 A0 14 n LE Y1 LE p 13 n Y2 LE 12 A1 Y3 2 A1 A1 LATCH A0 11 Y4 10 A2 Y5 3 A2 A2 LATCH A2 9 Y6 LE 4 7 LE LE Y7 5 OE1 6 OE0 3

CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Package Thermal Impedance,θJA(see Note 1): DC Input Diode Current, IIK E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67oC/W For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73oC/W DC Output Diode Current, IOK NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64oC/W For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 108oC/W DC Output Source or Sink Current per Output Pin, IO Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . .-55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION:Stressesabovethoselistedin“AbsoluteMaximumRatings”maycausepermanentdamagetothedevice.Thisisastressonlyratingandoperation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS 25oC -40oC TO 85oC -55oCTO125oC VCC PARAMETER SYMBOL VI(V) IO(mA) (V) MIN TYP MAX MIN MAX MIN MAX UNITS HC TYPES High Level Input VIH - - 2 1.5 - - 1.5 - 1.5 - V Voltage 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V Low Level Input VIL - - 2 - - 0.5 - 0.5 - 0.5 V Voltage 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V High Level Output VOH VIHorVIL -0.02 2 1.9 - - 1.9 - 1.9 - V Voltage -0.02 4.5 4.4 - - 4.4 - 4.4 - V CMOS Loads -0.02 6 5.9 - - 5.9 - 5.9 - V High Level Output - - - - - - - - - V Voltage -4 4.5 3.98 - - 3.84 - 3.7 - V TTL Loads -5.2 6 5.48 - - 5.34 - 5.2 - V Low Level Output VOL VIHorVIL 0.02 2 - - 0.1 - 0.1 - 0.1 V Voltage 0.02 4.5 - - 0.1 - 0.1 - 0.1 V CMOS Loads 0.02 6 - - 0.1 - 0.1 - 0.1 V Low Level Output - - - - - - - - - V Voltage 4 4.5 - - 0.26 - 0.33 - 0.4 V TTL Loads 5.2 6 - - 0.26 - 0.33 - 0.4 V Input Leakage II VCC or - 6 - - ±0.1 - ±1 - ±1 µA Current GND 4

CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237 DC Electrical Specifications (Continued) TEST CONDITIONS 25oC -40oC TO 85oC -55oCTO125oC VCC PARAMETER SYMBOL VI(V) IO(mA) (V) MIN TYP MAX MIN MAX MIN MAX UNITS Quiescent Device ICC VCC or 0 6 - - 8 - 80 - 160 µA Current GND HCT TYPES High Level Input VIH - - 4.5 to 2 - - 2 - 2 - V Voltage 5.5 Low Level Input VIL - - 4.5 to - - 0.8 - 0.8 - 0.8 V Voltage 5.5 High Level Output VOH VIHorVIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V Voltage CMOS Loads High Level Output -4 4.5 3.98 - - 3.84 - 3.7 - V Voltage TTL Loads Low Level Output VOL VIHorVIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V Voltage CMOS Loads Low Level Output 4 4.5 - - 0.26 - 0.33 - 0.4 V Voltage TTL Loads Input Leakage II VCCand 0 5.5 - - ±0.1 - ±1 - ±1 µA Current GND Quiescent Device ICC VCC or 0 5.5 - - 8 - 80 - 160 µA Current GND Additional Quiescent ∆ICC VCC - 4.5 to - 100 360 - 450 - 490 µA Device Current Per (Note 2) -2.1 5.5 Input Pin: 1 Unit Load NOTE: 2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS All 1.5 NOTE: UnitLoadis∆ICClimitspecifiedinDCElectricalTable,e.g., 360µA max at 25oC. Prerequisite For Switching Specifications 25oC -40oC TO 85oC -55oCTO125oC VCC PARAMETER SYMBOL (V) MIN TYP MAX MIN MAX MIN MAX UNITS HC TYPES Anto LE Setup Time tSU 2 50 - - 65 - 75 - ns 4.5 10 - - 13 - 15 - ns 6 9 - - 11 - 13 - ns An to LE Hold Time tH 2 30 - - 40 - 45 - ns 4.5 6 - - 8 - 9 - ns 6 5 - - 7 - 8 - ns 5

CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237 Prerequisite For Switching Specifications (Continued) 25oC -40oC TO 85oC -55oCTO125oC VCC PARAMETER SYMBOL (V) MIN TYP MAX MIN MAX MIN MAX UNITS LE Pulse Width tW 2 50 - - 65 - 75 - ns 4.5 10 - - 13 - 15 - ns 6 9 - - 1 - 13 - ns HCT TYPES An to LE Setup Time tSU 4.5 10 - - 13 - 15 - ns An to LE Hold Time CD74HCT137 tH 4.5 7 - - 9 - 11 - ns CD74HCT237 tH 4.5 5 - - 5 - 5 - ns LE Pulse Width tW 4.5 10 - - 13 - 15 - ns Switching SpecificationsInput tr, tf = 6ns -40oC TO 25oC 85oC -55oC TO 125oC TEST PARAMETER SYMBOL CONDITIONS VCC(V) MIN TYP MAX MIN MAX MIN MAX UNITS HC TYPES Propagation Delay tPLH,tPHL CL= 50pF 2 - - 180 - 225 - 270 ns CD74HC137, CD74HCT137 An to anyY 4.5 - - 36 - 45 - 54 ns 6 - - 31 - 38 - 46 ns Propagation Delay tPLH,tPHL CL= 50pF 2 - - 160 - 200 - 240 ns ’HC237, CD74HCT237 An to any Y 4.5 - - 32 - 40 - 48 ns 6 - - 27 - 34 - 41 ns Address to Output CD74HC137 tPLH, tPHL CL = 15pF 5 5 15 - - - - - ns ’HC237 tPLH, tPHL CL = 15pF 5 - 13 - - - - - ns OE0 to anyY or Y tPLH,tPHL CL= 50pF 2 - - 145 - 180 - 220 ns 4.5 - - 29 - 36 - 44 ns 6 - - 25 - 31 - 38 ns OE1 to anyY or Y tTLH, tTHL CL= 50pF 2 - - 145 - 180 - 220 ns 4.5 - - 29 - 36 - 44 ns 6 - - 25 - 31 - 38 ns LE to anyY or Y tTLH, tTHL CL = 50pF 2 - - 190 - 240 - 285 ns 4.5 - - 38 - 48 - 57 ns 6 - - 32 - 41 - 48 ns Power Dissipation Capacitance, (Notes 3, 4) CD74HC137 CPD CL = 15pF 5 - 19 - - - - - pF ’HC237 CPD CL = 15pF 5 - 23 - - - - - pF Output Transition Time tTLH, tTHL CL= 50pF 2 - - 75 - 95 - 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns Input Capacitance CI - - - - 10 - 10 - 10 pF 6

CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237 Switching SpecificationsInput tr, tf = 6ns (Continued) -40oC TO 25oC 85oC -55oC TO 125oC TEST PARAMETER SYMBOL CONDITIONS VCC(V) MIN TYP MAX MIN MAX MIN MAX UNITS HCT TYPES Propagation Delay An to anyY or Y tPLH, tPHL CL = 50pF 4.5 - - 38 - 48 - 57 ns Address to Output tPLH, tPHL CL = 15pF 5 - 16 - - - - - ns OE0to any Y (HC137) tPLH, tPHL CL = 50pF 4.5 - - 35 - 44 - 53 ns OE0to anyY (HC237) tPLH, tPHL CL = 50pF 4.5 - - 33 - 41 - 60 ns OE1to anyY (HC137) tTLH, tTHL CL= 50pF 4.5 - - 37 - 46 - 56 ns OE1to anyY (HC237) tTLH, tTHL CL= 50pF 4.5 - - 35 - 44 - 53 ns LE to any Y (HC137) tTLH, tTHL CL = 50pF 4.5 - - 44 - 55 - 66 ns LE to anyY (HC237) tTLH, tTHL CL= 50pF 4.5 - - 42 - 53 - 63 ns Power Dissipation Capacitance, (Notes 3, 4) CD74HC137 CPD CL = 15pF 5 - 19 - - - - - pF ’HC237 CPD CL= 15pF 5 - 23 - - - - - pF Output Transition Time tTLH, tTHL CL= 50pF 4.5 15 19 22 ns Input Capacitance CI - - - - 10 - 10 - 10 pF NOTES: 3. CPD is used to determine the dynamic power consumption, per gate. 4. PD = VCC2 fi(CPD + CL) where: fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. Test Circuits and Waveforms I trCL tfCL tWL+ tWH=fCIL trCL= 6ns tfCL= 6ns tWL+ tWH=fCL VCC 3V 90% 2.7V CLOCK 50% 50% 50% CLOCK 1.3V 1.3V 1.3V 10% 10% GND 0.3V 0.3V GND tWL tWH tWL tWH NOTE: Outputs should be switching from 10% VCC to 90% VCC in NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordancewithdevicetruthtable.ForfMAX,inputdutycycle=50%. accordancewithdevicetruthtable.ForfMAX,inputdutycycle=50%. FIGURE1. HCCLOCKPULSERISEANDFALLTIMESAND FIGURE2. HCTCLOCKPULSERISEANDFALLTIMESAND PULSE WIDTH PULSE WIDTH tr = 6ns tf = 6ns tr = 6ns tf = 6ns 90% VCC 2.7V 3V INPUT 50% INPUT 1.3V 10% GND 0.3V GND tTHL tTLH tTHL tTLH 90% 90% 50% 1.3V INVERTING INVERTING 10% 10% OUTPUT OUTPUT tPHL tPLH tPHL tPLH FIGURE3. HCANDHCUTRANSITIONTIMESANDPROPAGA- FIGURE4. HCTTRANSITIONTIMESANDPROPAGATION TION DELAY TIMES, COMBINATION LOGIC DELAY TIMES, COMBINATION LOGIC 7

CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237 Test Circuits and Waveforms (Continued) trCL tfCL trCL tfCL 90% VCC CLOCK 2.7V 3V CLOCK 50% 1.3V INPUT 10% INPUT 0.3V GND GND tH(H) tH(L) tH(H) tH(L) VCC DATA 3V INDPAUTAT 50% INPUT 1.3V 1.3V 1.3V GND GND tSU(H) tSU(L) tSU(H) tSU(L) tTLH tTHL tTLH tTHL 90% 90% 90% 90% 50% OUTPUT OUTPUT 1.3V 1.3V 10% 10% tPLH tPHL tPLH tPHL tREM tREM VCC 3V SET, RESET 50% SET, RESET 1.3V OR PRESET GND OR PRESET GND IC IC CL CL 50pF 50pF FIGURE5. HCSETUPTIMES,HOLDTIMES,REMOVALTIME, FIGURE6. HCTSETUPTIMES,HOLDTIMES,REMOVALTIME, AND PROPAGATION DELAY TIMES FOR EDGE AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS TRIGGERED SEQUENTIAL LOGIC CIRCUITS 8

PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 5962-8860601EA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8860601EA CD54HC237F3A CD54HC237F ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 CD54HC237F CD54HC237F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8860601EA CD54HC237F3A CD74HC137E ACTIVE PDIP N 16 25 Green (RoHS CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC137E & no Sb/Br) CD74HC137PW ACTIVE TSSOP PW 16 90 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ137 & no Sb/Br) CD74HC137PWR ACTIVE TSSOP PW 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ137 & no Sb/Br) CD74HC237E ACTIVE PDIP N 16 25 Green (RoHS CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC237E & no Sb/Br) CD74HC237EE4 ACTIVE PDIP N 16 25 Green (RoHS CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC237E & no Sb/Br) CD74HC237M ACTIVE SOIC D 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC237M & no Sb/Br) CD74HC237M96 ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC237M & no Sb/Br) CD74HC237M96G4 ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC237M & no Sb/Br) CD74HC237ME4 ACTIVE SOIC D 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC237M & no Sb/Br) CD74HC237NSR ACTIVE SO NS 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC237M & no Sb/Br) CD74HC237PWR ACTIVE TSSOP PW 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ237 & no Sb/Br) CD74HC237PWT ACTIVE TSSOP PW 16 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ237 & no Sb/Br) CD74HCT137E ACTIVE PDIP N 16 25 Green (RoHS CU NIPDAU N / A for Pkg Type -55 to 125 CD74HCT137E & no Sb/Br) CD74HCT137M96 ACTIVE SOIC D 16 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT137M & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) CD74HCT137MT ACTIVE SOIC D 16 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT137M & no Sb/Br) CD74HCT137MTE4 ACTIVE SOIC D 16 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT137M & no Sb/Br) CD74HCT237E ACTIVE PDIP N 16 25 Green (RoHS CU NIPDAU N / A for Pkg Type -55 to 125 CD74HCT237E & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 OTHER QUALIFIED VERSIONS OF CD54HC237, CD74HC237 : •Catalog: CD74HC237 •Military: CD54HC237 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 18-Aug-2014 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) CD74HC137PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 CD74HC237M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD74HC237NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 CD74HC237PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 CD74HC237PWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 CD74HCT137M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 18-Aug-2014 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) CD74HC137PWR TSSOP PW 16 2000 367.0 367.0 35.0 CD74HC237M96 SOIC D 16 2500 333.2 345.9 28.6 CD74HC237NSR SO NS 16 2000 367.0 367.0 38.0 CD74HC237PWR TSSOP PW 16 2000 367.0 367.0 35.0 CD74HC237PWT TSSOP PW 16 250 367.0 367.0 35.0 CD74HCT137M96 SOIC D 16 2500 333.2 345.9 28.6 PackMaterials-Page2

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PACKAGE OUTLINE PW0016A TSSOP - 1.2 mm max height SCALE 2.500 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 14X 0.65 16 1 2X 5.1 4.55 4.9 NOTE 3 8 9 0.30 B 4.5 16X 0.19 1.2 MAX 4.3 0.1 C A B NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.05 0.75 0.50 0 -8 DETA 20AIL A TYPICAL 4220204/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL UNDER SOLDER MASK OPENING METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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