CD54HC112, CD74HC112, CD54HCT112, CD74HCT112 Data sheet acquired from Harris Semiconductor Dual J-K Flip-Flop with Set and Reset SCHS141H Negative-Edge Trigger March 1998 - Revised October 2003 Features Description • Hysteresis on Clock Inputs for Improved Noise The ’HC112 and ’HCT112 utilize silicon-gate CMOS Immunity and Increased Input Rise and Fall Times technologytoachieveoperatingspeedsequivalenttoLSTTL [ /Title parts. They exhibit the low power consumption of standard (CD74 • Asynchronous Set and Reset CMOSintegratedcircuits,togetherwiththeabilitytodrive10 HC112 • Complementary Outputs LSTTL loads. , • Buffered Inputs These flip-flops have independent J, K, Set, Reset, and CD74 ClockinputsandQandQoutputs.Theychangestateonthe • Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, negative-going transition of the clock pulse. Set and Reset HCT11 TA = 25oC are accomplished asynchronously by low-level inputs. 2) • Fanout (Over Temperature Range) The HCT logic family is functionally as well as pin- /Sub- - Standard Outputs. . . . . . . . . . . . . . .10 LSTTL Loads compatible with the standard LS logic family. ject - Bus Driver Outputs . . . . . . . . . . . . .15 LSTTL Loads (Dual . • Wide Operating Temperature Range . . .-55oC to 125oC Ordering Information J-K • Balanced Propagation Delay and Transition Times Flip- TEMP. RANGE Flop • Significant Power Reduction Compared to LSTTL PART NUMBER (oC) PACKAGE Logic ICs with CD54HC112F3A -55 to 125 16 Ld CERDIP Setand • HC Types CD54HCT112F3A -55 to 125 16 Ld CERDIP Reset - 2V to 6V Operation CD74HC112E -55 to 125 16 Ld PDIP Nega- - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V CD74HC112MT -55 to 125 16 Ld SOIC • HCT Types CD74HC112M96 -55 to 125 16 Ld SOIC - 4.5V to 5.5V Operation CD74HC112NSR -55 to 125 16 Ld SOP - Direct LSTTL Input Logic Compatibility, CD74HC112PW -55 to 125 16 Ld TSSOP VIL= 0.8V (Max), VIH = 2V (Min) CD74HC112PWR -55 to 125 16 Ld TSSOP - CMOS Input Compatibility, Il≤1µA at VOL, VOH CD74HC112PWT -55 to 125 16 Ld TSSOP CD74HCT112E -55 to 125 16 Ld PDIP Pinout NOTE: Whenordering,usetheentirepartnumber.Thesuffixes96 CD54HC112, CD54HCT112 (CERDIP) andRdenotetapeandreel.ThesuffixTdenotesasmall-quantity CD74HC112 (PDIP, SOIC, SOP, TSSOP) reel of 250. CD74HCT112 (PDIP) TOP VIEW 1CP 1 16 VCC 1K 2 15 1R 1J 3 14 2R 1S 4 13 2CP 1Q 5 12 2K 1Q 6 11 2J 2Q 7 10 2S GND 8 9 2Q CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated 1

CD54HC112, CD74HC112, CD54HCT112, CD74HCT112 Functional Diagram 4 1S 3 5 1J 1Q 1K 2 F/F 1 6 1Q 1 1CP 15 1R 10 2S 11 2J 9 2Q 12 F/F 2 2K 7 2Q 13 2CP GND = 8 14 VCC = 16 2R TRUTH TABLE INPUTS OUTPUTS S R CP J K Q Q L H X X X H L H L X X X L H L L X X X H (Note 1) H (Note 1) H H ↓ L L No Change H H ↓ H L H L H H ↓ L H L H H H ↓ H H Toggle H H H X X No Change H= High Level (Steady State) L= Low Level (Steady State) X= Don’t Care ↓= High-to-Low Transition NOTE: 1. Output states unpredictable if bothS andR go High simultaneously after both being low at the same time. 2

CD54HC112, CD74HC112, CD54HCT112, CD74HCT112 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Package Thermal Impedance,θJA(see Note 2): DC Input Diode Current, IIK E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67oC/W For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64oC/W DC Drain Current, per Output, IO D (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73oC/W For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 108oC/W DC Output Diode Current, IOK Maximum Junction Temperature (Hermetic Package or Die) .175oC For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC DC Output Source or Sink Current per Output Pin, IO Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . .-55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time, tr, tf 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0ms (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0ms (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0ms (Max) CAUTION:Stressesabovethoselistedin“AbsoluteMaximumRatings”maycausepermanentdamagetothedevice.Thisisastressonlyratingandoperation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 2. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC PARAMETER SYMBOL VI(V) IO(mA) VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS HC TYPES High Level Input VIH - - 2 1.5 - - 1.5 - 1.5 - V Voltage 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V Low Level Input VIL - - 2 - - 0.5 - 0.5 - 0.5 V Voltage 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V High Level Output VOH VIH or -0.02 2 1.9 - - 1.9 - 1.9 - V Voltage VIL 4.5 4.4 - - 4.4 - 4.4 - V CMOS Loads 6 5.9 - - 5.9 - 5.9 - V High Level Output - - - - - - - - - V Voltage -4 4.5 3.98 - - 3.84 - 3.7 - V TTL Loads -5.2 6 5.48 - - 5.34 - 5.2 - V Low Level Output VOL VIH or 0.02 2 - - 0.1 - 0.1 - 0.1 V Voltage VIL 4.5 - - 0.1 - 0.1 - 0.1 V CMOS Loads 6 - - 0.1 - 0.1 - 0.1 V Low Level Output - - - - - - - - - V Voltage 4 4.5 - - 0.26 - 0.33 - 0.4 V TTL Loads 5.2 6 - - 0.26 - 0.33 - 0.4 V Input Leakage II VCC or - 6 - - ±0.1 - ±1 - ±1 µA Current GND 3

CD54HC112, CD74HC112, CD54HCT112, CD74HCT112 DC Electrical Specifications (Continued) TEST CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC PARAMETER SYMBOL VI(V) IO(mA) VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS Quiescent Device ICC VCC or 0 6 - - 4 - 40 - 80 µA Current GND HCT TYPES High Level Input VIH - - 4.5 to 2 - - 2 - 2 - V Voltage 5.5 Low Level Input VIL - - 4.5 to - - 0.8 - 0.8 - 0.8 V Voltage 5.5 High Level Output VOH VIH or -0.02 4.5 4.4 - - 4.4 - 4.4 - V Voltage VIL CMOS Loads High Level Output -4 4.5 3.98 - - 3.84 - 3.7 - V Voltage TTL Loads Low Level Output VOL VIH or 0.02 4.5 - - 0.1 - 0.1 - 0.1 V Voltage CMOS Loads VIL Low Level Output 4 4.5 - - 0.26 - 0.33 - 0.4 V Voltage TTL Loads Input Leakage II VCC - 5.5 - ±0.1 - ±1 - ±1 µA Current and GND Quiescent Device ICC VCC or 0 5.5 - - 4 - 40 - 80 µA Current GND Additional Quiescent ∆ICC VCC - 4.5 to - 100 360 - 450 - 490 µA Device Current Per (Note 3) - 2.1 5.5 Input Pin: 1 Unit Load NOTE: 3. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS 1S,2S 0.5 1K, 2K 0.6 1R,2R 0.65 1J, 2J,1CP,2CP 1 NOTE: Unit Load is∆ICClimit specified in DC Electrical Specifica- tions table, e.g., 360µA max at 25oC. Prerequisite For Switching Specifications 25oC -40oC TO 85oC -55oCTO125oC TEST VCC PARAMETER SYMBOL CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX UNITS HC TYPES Pulse WidthCP tW - 2 80 - - 100 - 120 - ns 4.5 16 - - 20 - 24 - ns 6 14 - - 17 - 20 - ns 4

CD54HC112, CD74HC112, CD54HCT112, CD74HCT112 Prerequisite For Switching Specifications (Continued) 25oC -40oC TO 85oC -55oCTO125oC TEST VCC PARAMETER SYMBOL CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX UNITS Pulse WidthR,S tW - 2 80 - - 100 - 120 - ns 4.5 16 - - 20 - 24 - ns 6 14 - - 17 - 20 - ns Setup Time J, K, toCP tSU - 2 80 - - 100 - 120 - ns 4.5 16 - - 20 - 24 - ns 6 14 - - 17 - 20 - ns Hold Time J, K, toCP tH - 2 0 - - 0 - 0 - ns 4.5 0 - - 0 - 0 - ns 6 0 - - 0 - 0 - ns Removal TimeR toCP,S toCP tREM - 2 80 - - 100 - 120 - ns 4.5 16 - - 20 - 24 - ns 6 14 - - 17 - 20 - ns CP Frequency fMAX - 2 6 - - 5 - 4 - MHz 4.5 30 - - 25 - 20 - MHz 6 35 - - 29 - 23 - MHz HCT TYPES Pulse WidthCP tSU - 4.5 16 - - 20 - 24 - ns Pulse WidthR,S tW - 4.5 18 - - 23 - 27 - ns Setup Time J, K, toCP tH - 4.5 16 - - 20 - 24 - ns Hold Time J, K, toCP tREM - 4.5 3 - - 3 - 3 - ns Removal TimeR toCP,S toCP tW - 4.5 20 - - 25 - 30 - ns CP Frequency fMAX - 4.5 30 - - 25 - 20 - MHz Switching SpecificationsInput tr, tf = 6ns 25oC -40oC TO 85oC -55oCTO125oC TEST VCC PARAMETER SYMBOL CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX UNITS HC TYPES Propagation Delay, tPLH, tPHL CL= 50pF 2 - - 175 - 220 - 265 ns CP to Q,Q CL= 50pF 4.5 - - 35 - 44 - 53 ns CL= 15pF 5 - 14 - - - - - ns CL= 50pF 6 - - 30 - 37 - 45 ns Propagation Delay, tPLH, tPHL CL= 50pF 2 - - 155 - 195 - 235 ns S to Q,Q CL= 50pF 4.5 - - 31 - 39 - 47 ns CL= 15pF 5 - 13 - - - - - ns CL= 50pF 6 - - 26 - 33 - 40 ns Propagation Delay, tPLH, tPHL CL= 50pF 2 - - 180 - 225 - 270 ns R to Q,Q CL= 50pF 4.5 - - 36 - 45 - 54 ns CL= 15pF 5 - 15 - - - - - ns CL= 50pF 6 - - 31 - 38 - 46 ns 5

CD54HC112, CD74HC112, CD54HCT112, CD74HCT112 Switching SpecificationsInput tr, tf = 6ns (Continued) 25oC -40oC TO 85oC -55oCTO125oC TEST VCC PARAMETER SYMBOL CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX UNITS Output Transition Time tTLH, tTHL CL= 50pF 2 - - 75 - 95 - 110 ns CL= 50pF 4.5 - - 15 - 19 - 22 ns CL= 50pF 6 - - 13 - 16 - 19 ns Input Capacitance CI - - - - 10 - 10 - 10 pF CP Frequency fMAX CL = 15pF 5 - 60 - - - - - MHz Power Dissipation Capacitance CPD - 5 - 12 - - - - - pF (Notes 4, 5) HCT TYPES Propagation Delay, tPLH, tPHL CL= 50pF 4.5 - - 35 - 44 - 53 ns CP to Q,Q CL = 15pF 5 - 14 - - - - - ns Propagation Delay, tPLH, tPHL CL= 50pF 4.5 - - 32 - 40 - 48 ns S to Q,Q CL = 15pF 5 - 13 - - - - - ns Propagation Delay, tPLH, tPHL CL= 50pF 4.5 - - 37 - 46 - 56 ns R to Q,Q CL = 15pF 5 - 14 - - - - - ns Output Transition Time tTLH, tTHL CL= 50pF 4.5 - - 15 - 19 - 22 ns Input Capacitance CI - - - - 10 - 10 - 10 pF CP Frequency fMAX CL = 15pF 5 - 60 - - - - - MHz Power Dissipation Capacitance CPD - 5 - 20 - - - - - pF (Notes 4, 5) NOTES: 4. CPD is used to determine the dynamic power consumption, per flip-flop. 5. PD = CPD VCC2 fi +Σ CLfowhere fi = input frequency, fo = output frequency, CL = output load capacitance, VCC = supply voltage. Test Circuits and Waveforms I trCL tfCL tWL+ tWH=fCIL trCL= 6ns tfCL= 6ns tWL+ tWH=fCL VCC 3V 90% 2.7V CLOCK 50% 50% 50% CLOCK 1.3V 1.3V 1.3V 10% 10% GND 0.3V 0.3V GND tWL tWH tWL tWH NOTE: Outputs should be switching from 10% VCC to 90% VCC in NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordancewithdevicetruthtable.ForfMAX,inputdutycycle=50%. accordancewithdevicetruthtable.ForfMAX,inputdutycycle=50%. FIGURE1. HCCLOCKPULSERISEANDFALLTIMESAND FIGURE2. HCTCLOCKPULSERISEANDFALLTIMESAND PULSE WIDTH PULSE WIDTH 6

CD54HC112, CD74HC112, CD54HCT112, CD74HCT112 Test Circuits and Waveforms (Continued) tr = 6ns tf = 6ns tr = 6ns tf = 6ns 90% VCC 2.7V 3V INPUT 50% INPUT 1.3V 10% GND 0.3V GND tTHL tTLH tTHL tTLH 90% 90% 50% 1.3V INVERTING INVERTING 10% 10% OUTPUT OUTPUT tPHL tPLH tPHL tPLH FIGURE3. HCANDHCUTRANSITIONTIMESANDPROPAGA- FIGURE4. HCTTRANSITIONTIMESANDPROPAGATION TION DELAY TIMES, COMBINATION LOGIC DELAY TIMES, COMBINATION LOGIC trCL tfCL trCL tfCL 90% VCC CLOCK 2.7V 3V CLOCK 50% 1.3V INPUT 10% INPUT 0.3V GND GND tH(H) tH(L) tH(H) tH(L) VCC DATA 3V INDPAUTAT 50% INPUT 1.3V 1.3V 1.3V GND GND tSU(H) tSU(L) tSU(H) tSU(L) tTLH tTHL tTLH tTHL 90% 90% 90% 90% 50% OUTPUT OUTPUT 1.3V 1.3V 10% 10% tPLH tPHL tPLH tPHL tREM tREM VCC 3V SET, RESET 50% SET, RESET 1.3V OR PRESET GND OR PRESET GND IC IC CL CL 50pF 50pF FIGURE5. HCSETUPTIMES,HOLDTIMES,REMOVALTIME, FIGURE6. HCTSETUPTIMES,HOLDTIMES,REMOVALTIME, AND PROPAGATION DELAY TIMES FOR EDGE AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS TRIGGERED SEQUENTIAL LOGIC CIRCUITS 7

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 5962-8970201EA ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8970201EA CD54HCT112F3A CD54HC112F3A ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type -55 to 125 8408801EA CD54HC112F3A CD54HCT112F3A ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8970201EA CD54HCT112F3A CD74HC112E ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -55 to 125 CD74HC112E & no Sb/Br) CD74HC112M96 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC112M & no Sb/Br) CD74HC112MT ACTIVE SOIC D 16 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC112M & no Sb/Br) CD74HC112NSR ACTIVE SO NS 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC112M & no Sb/Br) CD74HC112PW ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HJ112 & no Sb/Br) CD74HC112PWR ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HJ112 & no Sb/Br) CD74HC112PWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HJ112 & no Sb/Br) CD74HC112PWT ACTIVE TSSOP PW 16 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HJ112 & no Sb/Br) CD74HCT112E ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -55 to 125 CD74HCT112E & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF CD54HC112, CD54HCT112, CD74HC112, CD74HCT112 : •Catalog: CD74HC112, CD74HCT112 •Military: CD54HC112, CD54HCT112 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) CD74HC112M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD74HC112NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 CD74HC112PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 CD74HC112PWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) CD74HC112M96 SOIC D 16 2500 333.2 345.9 28.6 CD74HC112NSR SO NS 16 2000 367.0 367.0 38.0 CD74HC112PWR TSSOP PW 16 2000 367.0 367.0 35.0 CD74HC112PWT TSSOP PW 16 250 367.0 367.0 35.0 PackMaterials-Page2

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PACKAGE OUTLINE PW0016A TSSOP - 1.2 mm max height SCALE 2.500 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 14X 0.65 16 1 2X 5.1 4.55 4.9 NOTE 3 8 9 0.30 B 4.5 16X 0.19 1.2 MAX 4.3 0.1 C A B NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.05 0.75 0.50 0 -8 DETA 20AIL A TYPICAL 4220204/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL UNDER SOLDER MASK OPENING METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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