ICGOO在线商城 > 集成电路(IC) > 逻辑 - 栅极和逆变器 > CD74HC00M
数量阶梯 | 香港交货 | 国内含税 |
+xxxx | $xxxx | ¥xxxx |
查看当月历史价格
查看今年历史价格
CD74HC00M产品简介:
ICGOO电子元器件商城为您提供CD74HC00M由Texas Instruments设计生产,在icgoo商城现货销售,并且可以通过原厂、代理商等渠道进行代购。 CD74HC00M价格参考¥1.77-¥1.85。Texas InstrumentsCD74HC00M封装/规格:逻辑 - 栅极和逆变器, NAND Gate IC 4 Channel 14-SOIC。您可以下载CD74HC00M参考资料、Datasheet数据手册功能说明书,资料中有CD74HC00M 详细功能的应用电路图电压和使用方法及教程。
参数 | 数值 |
产品目录 | 集成电路 (IC)半导体 |
描述 | IC GATE NAND 4CH 2-INP 14-SOIC逻辑门 Quad 2-Input |
产品分类 | |
品牌 | Texas Instruments |
产品手册 | |
产品图片 | |
rohs | 符合RoHS无铅 / 符合限制有害物质指令(RoHS)规范要求 |
产品系列 | 逻辑集成电路,逻辑门,Texas Instruments CD74HC00M74HC |
数据手册 | |
产品型号 | CD74HC00M |
不同V、最大CL时的最大传播延迟 | 15ns @ 6V,50pF |
产品 | NAND |
产品目录页面 | |
产品种类 | 逻辑门 |
传播延迟时间 | 90 ns |
低电平输出电流 | 5.2 mA |
供应商器件封装 | 14-SOIC |
其它名称 | 296-9167-5 |
包装 | 管件 |
单位重量 | 129.400 mg |
商标 | Texas Instruments |
安装类型 | 表面贴装 |
安装风格 | SMD/SMT |
封装 | Tube |
封装/外壳 | 14-SOIC(0.154",3.90mm 宽) |
封装/箱体 | SOIC-14 |
工作温度 | -55°C ~ 125°C |
工作温度范围 | - 55 C to + 125 C |
工厂包装数量 | 50 |
最大工作温度 | + 125 C |
最小工作温度 | - 55 C |
栅极数量 | 4 |
标准包装 | 50 |
特性 | - |
电压-电源 | 2 V ~ 6 V |
电流-输出高,低 | 5.2mA,5.2mA |
电流-静态(最大值) | 2µA |
电源电压-最大 | 6 V |
电源电压-最小 | 2 V |
电路数 | 4 |
系列 | CD74HC00 |
输入/输出线数量 | 2 / 1 |
输入数 | 2 |
输入线路数量 | 2 |
输出线路数量 | 1 |
逻辑电平-低 | 0.5 V ~ 1.8 V |
逻辑电平-高 | 1.5 V ~ 4.2 V |
逻辑类型 | 与非门 |
逻辑系列 | 74HC |
高电平输出电流 | - 5.2 mA |
CD54HC00, CD74HC00, CD54HCT00, CD74HCT00 Data sheet acquired from Harris Semiconductor SCHS116C High-Speed CMOS Logic Quad 2-Input NAND Gate January 1998 - Revised September 2003 Features Description • Buffered Inputs The CD54HC00, CD74HC00, CD54HCT00, and CD74HCT00 logic gates utilize silicon gate CMOS [ /Title • Typical Propagation Delay: 7ns at VCC = 5V, technology to achieve operating speeds similar to LSTTL (CD54 CL = 15pF, TA = 25oC gates with the low power consumption of standard CMOS HC00, • Fanout (Over Temperature Range) integrated circuits. All devices have the ability to drive 10 LSTTL loads. The 74HCT logic family is functionally pin CD54 - Standard Outputs. . . . . . . . . . . . . . .10 LSTTL Loads compatible with the standard 74LS logic family. HCT00 - Bus Driver Outputs . . . . . . . . . . . . .15 LSTTL Loads , • Wide Operating Temperature Range . . .-55oC to 125oC Ordering Information CD74 • Balanced Propagation Delay and Transition Times TEMP. RANGE HC00, PART NUMBER (oC) PACKAGE • Significant Power Reduction Compared to LSTTL CD74 Logic ICs CD54HC00F3A -55 to 125 14 Ld CERDIP HCT00 • Alternate Source is Philips/Signetics CD54HCT00F3A -55 to 125 14 Ld CERDIP ) • HC Types CD74HC00E -55 to 125 14 Ld PDIP /Sub- - 2V to 6V Operation CD74HC00M -55 to 125 14 Ld SOIC - High Noise Immunity: NIL = 30%, NIH = 30% of VCC CD74HC00MT -55 to 125 14 Ld SOIC at VCC = 5V CD74HC00M96 -55 to 125 14 Ld SOIC • HCT Types CD74HCT00E -55 to 125 14 Ld PDIP - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, CD74HCT00M -55 to 125 14 Ld SOIC VIL= 0.8V (Max), VIH = 2V (Min) CD74HCT00MT -55 to 125 14 Ld SOIC - CMOS Input Compatibility, Il≤1µA at VOL, VOH CD74HCT00M96 -55 to 125 14 Ld SOIC NOTE: Whenordering,usetheentirepartnumber.Thesuffix96 denotestapeandreel.ThesuffixTdenotesasmall-quantityreel of 250. Pinout CD54HC00, CD54HCT00, (CERDIP) CD74HC00, CD74HCT00 (PDIP, SOIC) TOP VIEW 1A 1 14 VCC 1B 2 13 4B 1Y 3 12 4A 2A 4 11 4Y 2B 5 10 3B 2Y 6 9 3A GND 7 8 3Y CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated 1
CD54HC00, CD74HC00, CD54HCT00, CD74HCT00 Functional Diagram 1 14 1A VCC 2 13 1B 4B 3 12 1Y 4A 4 11 2A 4Y 5 10 2B 3B 6 9 2Y 3A 7 8 GND 3Y TRUTH TABLE INPUTS OUTPUT nA nB nY L L H L H H H L H H H L Logic Symbol nA nY nB 2
CD54HC00, CD74HC00, CD54HCT00, CD74HCT00 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Thermal Resistance (Typical, Note 1) θJA (oC/W) DC Input Diode Current, IIK E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 DC Output Diode Current, IOK Maximum Junction Temperature (Hermetic Package or Die) . . .175oC For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC DC Output Source or Sink Current per Output Pin, IO Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC DC VCC or Ground Current, ICC orIGND. . . . . . . . . . . . . . . . . .±50mA (SOIC - Lead Tips Only) Operating Conditions Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . .-55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION:Stressesabovethoselistedin“AbsoluteMaximumRatings”maycausepermanentdamagetothedevice.Thisisastressonlyratingandoperation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC PARAMETER SYMBOL VI(V) IO(mA) VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS HC TYPES High Level Input VIH - - 2 1.5 - - 1.5 - 1.5 - V Voltage 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V Low Level Input VIL - - 2 - - 0.5 - 0.5 - 0.5 V Voltage 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V High Level Output VOH VIH or -0.02 2 1.9 - - 1.9 - 1.9 - V Voltage VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V CMOS Loads -0.02 6 5.9 - - 5.9 - 5.9 - V High Level Output - - - - - - - - - V Voltage -4 4.5 3.98 - - 3.84 - 3.7 - V TTL Loads -5.2 6 5.48 - - 5.34 - 5.2 - V Low Level Output VOL VIH or 0.02 2 - - 0.1 - 0.1 - 0.1 V Voltage VIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V CMOS Loads 0.02 6 - - 0.1 - 0.1 - 0.1 V Low Level Output - - - - - - - - - V Voltage 4 4.5 - - 0.26 - 0.33 - 0.4 V TTL Loads 5.2 6 - - 0.26 - 0.33 - 0.4 V Input Leakage II VCC or - 6 - - ±0.1 - ±1 - ±1 µA Current GND 3
CD54HC00, CD74HC00, CD54HCT00, CD74HCT00 DC Electrical Specifications (Continued) TEST CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC PARAMETER SYMBOL VI(V) IO(mA) VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS Quiescent Device ICC VCC or 0 6 - - 2 - 20 - 40 µA Current GND HCT TYPES High Level Input VIH - - 4.5 to 2 - - 2 - 2 - V Voltage 5.5 Low Level Input VIL - - 4.5 to - - 0.8 - 0.8 - 0.8 V Voltage 5.5 High Level Output VOH VIH or - 0.02 4.5 4.4 - - 4.4 - 4.4 - V Voltage VIL CMOS Loads High Level Output - 4 4.5 3.98 - - 3.84 - 3.7 - V Voltage TTL Loads Low Level Output VOL VIH or 0.02 4.5 - - 0.1 - 0.1 - 0.1 V Voltage CMOS Loads VIL Low Level Output 4 4.5 - - 0.26 - 0.33 - 0.4 V Voltage TTL Loads Input Leakage II VCC - 5.5 - ±0.1 - ±1 - ±1 µA Current and GND Quiescent Device ICC VCC or 0 5.5 - - 2 - 20 - 40 µA Current GND Additional Quiescent ∆ICC VCC - 4.5 to - 100 360 - 450 - 490 µA Device Current Per (Note 2) - 2.1 5.5 Input Pin: 1 Unit Load NOTE: 2. For dual-supply systems theorectical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS nA 1.8 nB 1.1 NOTE: Unit Load is∆ICClimit specified in DC Electrical Specifica- tions table, e.g. 360µA max at 25oC. Switching SpecificationsInput tr, tf = 6ns 25oC -40oC TO 85oC -55oCTO125oC TEST VCC PARAMETER SYMBOL CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX UNITS HC TYPES Propagation Delay, tPLH, tPHL CL= 50pF 2 - - 90 - 115 - 135 ns Input to Output (Figure 1) 4.5 - - 18 - 23 - 27 ns 6 - - 15 - 20 - 23 ns PropagationDelay,DataInputto tPLH, tPHL CL= 15pF 5 - 7 - - - - - pF Output Y 4
CD54HC00, CD74HC00, CD54HCT00, CD74HCT00 Switching SpecificationsInput tr, tf = 6ns (Continued) 25oC -40oC TO 85oC -55oCTO125oC TEST VCC PARAMETER SYMBOL CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX UNITS Transition Times (Figure 1) tTLH, tTHL CL= 50pF 2 - - 75 - 95 18 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns Input Capacitance CI - - - - 10 - 10 - 10 pF Power Dissipation Capacitance CPD - 5 - 25 - - - - - pF (Notes 3, 4) HCT TYPES Propagation Delay, Input to tPLH, tPHL CL= 50pF 4.5 - - 20 - 25 - 30 ns Output (Figure 2) PropagationDelay,DataInputto tPLH, tPHL CL= 15pF 5 - 8 - - - - - pF Output Y Transition Times (Figure 2) tTLH, tTHL CL= 50pF 4.5 - - 15 - 19 - 22 ns Input Capacitance CI - - - - 10 - 10 - 10 pF Power Dissipation Capacitance CPD - 5 - 25 - - - - - pF (Notes 3, 4) NOTES: 3. CPD is used to determine the dynamic power consumption, per gate. 4. PD = VCC2 fi (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage. Test Circuits and Waveforms tr = 6ns tf = 6ns tr = 6ns tf = 6ns 90% VCC 2.7V 3V INPUT 50% INPUT 1.3V 10% GND 0.3V GND tTHL tTLH tTHL tTLH 90% 90% 50% 1.3V INVERTING INVERTING 10% 10% OUTPUT OUTPUT tPHL tPLH tPHL tPLH FIGURE1. HCANDHCUTRANSITIONTIMESANDPROPAGA- FIGURE2. HCTTRANSITIONTIMESANDPROPAGATION TION DELAY TIMES, COMBINATION LOGIC DELAY TIMES, COMBINATION LOGIC INPUT LEVEL HC TYPES HCT TYPES VCC 3V VS 50% VCC 1.3V NOTE: Transition times and propagation delay times. 5
PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) 5962-8683101CA ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8683101CA CD54HCT00F3A CD54HC00F ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type -55 to 125 CD54HC00F CD54HC00F3A ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type -55 to 125 8403701CA CD54HC00F3A CD54HCT00F ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type -55 to 125 CD54HCT00F CD54HCT00F3A ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type -55 to 125 5962-8683101CA CD54HCT00F3A CD74HC00E ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type -55 to 125 CD74HC00E & no Sb/Br) CD74HC00EE4 ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type -55 to 125 CD74HC00E & no Sb/Br) CD74HC00M ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC00M & no Sb/Br) CD74HC00M96 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC00M & no Sb/Br) CD74HC00M96E4 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC00M & no Sb/Br) CD74HC00ME4 ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC00M & no Sb/Br) CD74HC00MT ACTIVE SOIC D 14 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC00M & no Sb/Br) CD74HCT00E ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type -55 to 125 CD74HCT00E & no Sb/Br) CD74HCT00M ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT00M & no Sb/Br) CD74HCT00M96 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT00M & no Sb/Br) CD74HCT00M96G4 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT00M & no Sb/Br) CD74HCT00ME4 ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT00M & no Sb/Br) Addendum-Page 1
PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) CD74HCT00MG4 ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT00M & no Sb/Br) CD74HCT00MT ACTIVE SOIC D 14 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT00M & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF CD54HC00, CD54HCT00, CD74HC00, CD74HCT00 : Addendum-Page 2
PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 •Catalog: CD74HC00, CD74HCT00 •Military: CD54HC00, CD54HCT00 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 3
PACKAGE MATERIALS INFORMATION www.ti.com 8-Nov-2018 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) CD74HC00M96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 CD74HC00MT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 CD74HCT00M96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 CD74HCT00MT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 PackMaterials-Page1
PACKAGE MATERIALS INFORMATION www.ti.com 8-Nov-2018 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) CD74HC00M96 SOIC D 14 2500 367.0 367.0 38.0 CD74HC00MT SOIC D 14 250 210.0 185.0 35.0 CD74HCT00M96 SOIC D 14 2500 367.0 367.0 38.0 CD74HCT00MT SOIC D 14 250 210.0 185.0 35.0 PackMaterials-Page2
None
PACKAGE OUTLINE J0014A CDIP - 5.08 mm max height SCALE 0.900 CERAMIC DUAL IN LINE PACKAGE PIN 1 ID A 4X .005 MIN (OPTIONAL) [0.13] .015-.060 TYP [0.38-1.52] 1 14 12X .100 [2.54] 14X .014-.026 14X .045-.065 [0.36-0.66] [1.15-1.65] .010 [0.25] C A B .754-.785 [19.15-19.94] 7 8 B .245-.283 .2 MAX TYP .13 MIN TYP [6.22-7.19] [5.08] [3.3] SEATING PLANE C .308-.314 [7.83-7.97] AT GAGE PLANE .015 GAGE PLANE [0.38] 0 -15 14X .008-.014 TYP [0.2-0.36] 4214771/A 05/2017 NOTES: 1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package is hermitically sealed with a ceramic lid using glass frit. 4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only. 5. Falls within MIL-STD-1835 and GDIP1-T14. www.ti.com
EXAMPLE BOARD LAYOUT J0014A CDIP - 5.08 mm max height CERAMIC DUAL IN LINE PACKAGE (.300 ) TYP [7.62] SEE DETAIL B SEE DETAIL A 1 14 12X (.100 ) [2.54] SYMM 14X ( .039) [1] 7 8 SYMM LAND PATTERN EXAMPLE NON-SOLDER MASK DEFINED SCALE: 5X .002 MAX (.063) [0.05] [1.6] METAL ALL AROUND ( .063) SOLDER MASK [1.6] OPENING METAL .002 MAX SOLDER MASK (R.002 ) TYP [0.05] OPENING [0.05] ALL AROUND DETAIL A DETAIL B SCALE: 15X 13X, SCALE: 15X 4214771/A 05/2017 www.ti.com
None
None
None
IMPORTANTNOTICEANDDISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated