CD74FCT273 BiCMOS OCTAL D-TYPE FLIP-FLOP WITH RESET SCBS737A – JULY 2000 – REVISED JULY 2000 (cid:0) BiCMOS Technology With Low Quiescent E OR M PACKAGE Power (TOP VIEW) (cid:0) Buffered Inputs (cid:0) CLR 1 20 VCC Direct Clear Input 1Q 2 19 8Q (cid:0) 48-mA Output Sink Current 1D 3 18 8D (cid:0) Output Voltage Swing Limited to 3.7 V 2D 4 17 7D (cid:0) 2Q 5 16 7Q Controlled Output Edge Rates (cid:0) 3Q 6 15 6Q Input/Output Isolation From V CC 3D 7 14 6D (cid:0) SCR Latch-Up-Resistant BiCMOS Process 4D 8 13 5D and Circuit Design 4Q 9 12 5Q (cid:0) Applications Include: GND 10 11 CLK – Buffer/Storage Registers – Shift Registers – Pattern Generators (cid:0) Package Options Include Plastic Small-Outline (M) Package and Standard Plastic (E) DIP description The CD74FCT273 is a positive-edge-triggered, D-type flip-flop with a direct clear (CLR) input. This device uses a small-geometry BiCMOS technology. The output stage is a combination of bipolar and CMOS transistors that limits the output high level to two diode drops below V . This resultant lowering of output swing (0 V to 3.7 V) CC reduces power-bus ringing [a source of electromagnetic interference (EMI)] and minimizes V bounce and CC ground bounce and their effects during simultaneous output switching. The output configuration also enhances switching speed and is capable of sinking 48 mA. Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output. All eight flip-flops are controlled by a common clock (CLK) and a common reset (CLR). The outputs are placed in a low state when CLR is taken low, independent of the CLK. The CD74FCT273 is characterized for operation from 0°C to 70°C. FUNCTION TABLE (each flip-flop) INPUTS OOUUTTPPUUTT CLR CLK D Q L X X L H ↑ H H H ↑ L L H L X Q0 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright  2000, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

CD74FCT273 BiCMOS OCTAL D-TYPE FLIP-FLOP WITH RESET SCBS737A – JULY 2000 – REVISED JULY 2000 logic symbol† 1 CLR R 11 CLK C1 3 2 1D 1D 1Q 4 5 2D 2Q 7 6 3D 3Q 8 9 4D 4Q 13 12 5D 5Q 14 15 6D 6Q 17 16 7D 7Q 18 19 8D 8Q †This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) 1D 2D 3D 4D 5D 6D 7D 8D 3 4 7 8 13 14 17 18 11 CLK 1D 1D 1D 1D 1D 1D 1D 1D C1 C1 C1 C1 C1 C1 C1 C1 R R R R R R R R 1 CLR 2 5 6 9 12 15 16 19 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q logic diagram, each flip-flop (positive logic) C C D TG TG Q C C C C TG CLK(I) C TG C C C R 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CD74FCT273 BiCMOS OCTAL D-TYPE FLIP-FLOP WITH RESET SCBS737A – JULY 2000 – REVISED JULY 2000 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† DC supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V CC DC input diode current, IIK (VI < –0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA DC output diode current, IOK (VO < –0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA DC output sink current per output pin, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 mA OL DC output source current per output pin, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30 mA OH Continuous current through V , I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 mA CC CC Continuous current through GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 mA Package thermal impedance, q (see Note 1): E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W JA M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 2) MIN MAX UNIT VCC Supply voltage 4.75 5.25 V VIH High-level input voltage 2 V VIL Low-level input voltage 0.8 V VI Input voltage 0 VCC V VO Output voltage 0 VCC V IOH High-level output current –15 mA IOL Low-level output current 48 mA D t/D v Input transition rise or fall rate 0 10 ns/V TA Operating free-air temperature 0 70 °C NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating temperature range (unless otherwise noted) TA = 25°C PPAARRAAMMEETTEERR TTEESSTT CCOONNDDIITTIIOONNSS VVCCCC MMIINN MMAAXX UUNNIITT MIN MAX VIK II = –18 mA 4.75 V –1.2 –1.2 V VOH IOH = –15 mA 4.75 V 2.4 2.4 V VOL IOL = 48 mA 4.75 V 0.55 0.55 V II VI = VCC or GND 5.25 V ±0.1 ±1 (cid:0)A IOZ VO = VCC or GND 5.25 V ±0.5 ±10 (cid:0)A IOS‡ VI = VCC or GND, VO = 0 5.25 V –60 –60 mA ICC VI = VCC or GND, IO = 0 5.25 V 8 80 (cid:0)A One input at 3.4 V, D ICC§ Other inputs at VCC or GND 5.25 V 1.6 1.6 mA Ci VI = VCC or GND 10 pF ‡Not more than one output should be tested at a time, and the duration of the test should not exceed 100 ms. §This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

CD74FCT273 BiCMOS OCTAL D-TYPE FLIP-FLOP WITH RESET SCBS737A – JULY 2000 – REVISED JULY 2000 timing requirements over recommended operating conditions (unless otherwise noted) (see Figure 1) MIN MAX UNIT fclock Clock frequency 70 MHz CLR low 7 ttw PPuullssee dduurraattiioonn nnss CLK high or low 7 Data before CLK↑ 3 ttsu SSeettuupp ttiimmee nnss CLR before CLK↑ 4 th Hold time Data after CLK↑ 2 ns switching characteristics over recommended operating conditions, C = 50 pF (unless otherwise L noted) (see Figure 1) FROM TO TA = 25°C PPAARRAAMMEETTEERR MMIINN MMAAXX UUNNIITT (INPUT) (OUTPUT) TYP fmax 70 MHz CLK 7 2 13 ttpdd AAnny QQ nnss CLR 8 2 13 operating characteristics, T = 25°C A PARAMETER TEST CONDITIONS TYP UNIT Cpd Power dissipation capacitance No load, f = 1 MHz 36 pF 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CD74FCT273 BiCMOS OCTAL D-TYPE FLIP-FLOP WITH RESET SCBS737A – JULY 2000 – REVISED JULY 2000 PARAMETER MEASUREMENT INFORMATION 7 V 500 W S1 Open From Output Test From Output TEST S1 Under Test Point Under Test GND tPLH/tPHL Open CL = 50 pF 500 W CL = 50 pF 500 W tPLZ/tPZL 7 V (see Note A) (see Note A) tPHZ/tPZH Open Open Drain 7 V LOAD CIRCUIT FOR LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS 3-STATE AND OPEN-DRAIN OUTPUTS 3 V 90% 90% 1.5 V 1.5 V 10% 10% 0 V tr tf VOLTAGE WAVEFORM INPUT RISE AND FALL TIMES 3 V Timing Input 1.5 V tw 0 V th 3 V tsu 3 V Input 1.5 V 1.5 V Data Input 1.5 V 1.5 V 0 V 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PULSE DURATION SETUP AND HOLD TIMES 3 V 3 V Output Input 1.5 V 1.5 V Control 1.5 V 1.5 V 0 V 0 V tPLH tPHL tPZL tPLZ In-Phase VOH Output ≈3.5 V Output 1.5 V 1.5 V VOL (Wseaev eNfootrem B 1) 1.5 V VOL + 0.3 VVOL tPHL tPLH tPZH tPHZ Out-of-Phase VOH Output VOH – 0.3 VVOH 1.5 V 1.5 V Waveform 2 1.5 V Output VOL (see Note B) ≈0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 W , tr and tf = 2.5 ns. D. The outputs are measured one at a time with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) CD74FCT273E ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type 0 to 70 CD74FCT273E (RoHS) CD74FCT273M ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 74FCT273M & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Addendum-Page 2

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PACKAGE OUTLINE DW0020A SOIC - 2.65 mm max height SCALE 1.200 SOIC C 10.63 SEATING PLANE TYP 9.97 A PIN 1 ID 0.1 C AREA 18X 1.27 20 1 13.0 2X 12.6 11.43 NOTE 3 10 11 0.51 20X 7.6 0.31 2.65 MAX B 7.4 0.25 C A B NOTE 4 0.33 TYP 0.10 0.25 SEE DETAIL A GAGE PLANE 0.3 1.27 0 - 8 0.1 0.40 DETAIL A TYPICAL 4220724/A 05/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS-013. www.ti.com

EXAMPLE BOARD LAYOUT DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM (R0.05) TYP 10 11 (9.3) LAND PATTERN EXAMPLE SCALE:6X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220724/A 05/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM 10 11 (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4220724/A 05/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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