CD74ACT86-EP QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE www.ti.com SCHS357–MARCH2006 FEATURES • ControlledBaseline • SCR-Latchup-ResistantCMOSProcessand – OneAssembly/TestSite,OneFabrication CircuitDesign Site • Exceeds2-kVESDProtectionPer • ExtendedTemperaturePerformanceof MIL-STD-883,Method3015 –55(cid:176) Cto125(cid:176) C D PACKAGE • EnhancedDiminishingManufacturing (TOP VIEW) Sources(DMS)Support • EnhancedProduct-ChangeNotification 1A 1 14 VCC • QualificationPedigree (1) 1B 2 13 4B • InputsAreTTL-VoltageCompatible 1Y 3 12 4A 2A 4 11 4Y • SpeedofBipolarF,AS,andS,With 2B 5 10 3B SignificantlyReducedPowerConsumption 2Y 6 9 3A • BalancedPropagationDelays GND 7 8 3Y • – 24-mAOutputDriveCurrent – Fanoutto15FDevices (1) ComponentqualificationinaccordancewithJEDECand industrystandardstoensurereliableoperationoveran extendedtemperaturerange.Thisincludes,butisnotlimited to,HighlyAcceleratedStressTest(HAST)orbiased85/85, temperaturecycle,autoclaveorunbiasedHAST, electromigration,bondintermetalliclife,andmoldcompound life.Suchqualificationtestingshouldnotbeviewedas justifyinguseofthiscomponentbeyondspecified performanceandenvironmentallimits. DESCRIPTION/ORDERING INFORMATION The CD74ACT86-EP is a quadruple 2-input exclusive-OR gate. This device performs the Boolean function Y=A¯ BorY=AB+ABinpositivelogic. A common application is as a true/complement element. If one of the inputs is low, the other input is reproduced in true form at the output. If one of the inputs is high, the signal on the other input is reproduced inverted at the output. ORDERINGINFORMATION T PACKAGE(1) ORDERABLEPARTNUMBER TOP-SIDEMARKING A –55(cid:176) Cto125(cid:176) C SOIC–D TapeandReel CD74ACT86MDREP ACT86MEP (1) Packagedrawings,standardpackingquantities,thermaldata,symbolization,andPCBdesignguidelinesareavailableat www.ti.com/sc/package. FUNCTIONTABLE (EACHGATE) INPUTS OUTPUT A B Y L L L L H H H L H H H L Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2006,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

CD74ACT86-EP QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE www.ti.com SCHS357–MARCH2006 Exclusive-OR Logic An exclusive-OR gate has many applications, some of which can be represented better by alternative logic symbols. EXCLUSIVE OR = 1 These are five equivalent exclusive-OR symbols valid for an CD74ACT86-EP gate in positive logic; negation may be shown at any two ports. LOGIC-IDENTITY ELEMENT EVEN-PARITY ELEMENT ODD-PARITY ELEMENT = 2k 2k + 1 The output is active (low) if The output is active (low) if The output is active (high) if all inputs stand at the same an even number of inputs an odd number of inputs logic level (i.e., A = B). (i.e., 0 or 2) are active. (i.e., only 1 of the 2) are active. Absolute Maximum Ratings(1) overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT V Supplyvoltagerange –0.5 6 V CC I Inputclampcurrent(2) V <0orV >V – 20 mA IK I I CC I Outputclampcurrent(2) V <0orV >V – 50 mA OK O O CC I Continuousoutputcurrent V =0toV – 50 mA O O CC ContinuouscurrentthroughV orGND – 100 mA CC q Packagethermalimpedance(3) 86 (cid:176) C/W JA T Storagetemperaturerange –65 150 (cid:176) C stg (1) Stressesbeyondthoselistedunder"absolutemaximumratings"maycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunder"recommendedoperating conditions"isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Theinputandoutputvoltageratingsmaybeexceedediftheinputandoutputcurrentratingsareobserved. (3) ThepackagethermalimpedanceiscalculatedinaccordancewithJESD51-7. Recommended Operating Conditions(1) TA=25(cid:176) C –5152(cid:176)5C(cid:176) Cto UNIT MIN MAX MIN MAX V Supplyvoltage 4.5 5.5 4.5 5.5 V CC V High-levelinputvoltage 2 2 V IH V Low-levelinputvoltage 0.8 0.8 V IL V Inputvoltage 0 V 0 V V I CC CC V Outputvoltage 0 V 0 V V O CC CC I High-leveloutputcurrent –24 –24 mA OH I Low-leveloutputcurrent 24 24 mA OL D t/D v Inputtransitionriseorfallrate 10 10 ns/V (1) AllunusedinputsofthedevicemustbeheldatV orGNDtoensureproperdeviceoperation.RefertotheTIapplicationreport, CC ImplicationsofSloworFloatingCMOSInputs,literaturenumberSCBA004. 2 SubmitDocumentationFeedback

CD74ACT86-EP QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE www.ti.com SCHS357–MARCH2006 Electrical Characteristics overrecommendedoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS V TA=25(cid:176) C –5152(cid:176)5C(cid:176) Cto UNIT CC MIN MAX MIN MAX I =–50m A 4.4 4.4 OH 4.5V V V =V orV I =–24mA 3.94 3.7 V OH I IH IL OH I =–50mA(1) 5.5V 3.85 3.85 OH I =50m A 0.1 0.1 OL 4.5V V V =V orV I =24mA 0.36 0.5 V OL I IH IL OL I =50mA(1) 5.5V 1.65 1.65 OL I V =V orGND 5.5V – 0.1 – 1 m A I I CC I V =V orGND, I =0 5.5V 4 80 m A CC I CC O D I (2) V =V –2.1V 4.5Vto5.5V 2.4 3 mA CC I CC C 10 10 pF i (1) Testoneoutputatatime,notexceeding1-sduration.Measurementismadebyforcingindicatedcurrentandmeasuringvoltageto minimizepowerdissipation.Testverifiesaminimum50-W transmission-linedrivecapabilityat85(cid:176) Cand75-W transmission-linedrive capabilityat125(cid:176) C. (2) Additionalquiescentsupplycurrentperinputpin,TTLinputshigh,1unitload ACTINPUTLOADTABLE(1) INPUT UNITLOAD All 0.48 (1) UnitloadisD I limitspecifiedin CC electricalcharacteristicstable (e.g.,2.4mAat25(cid:176) C). Switching Characteristics overrecommendedoperatingfree-airtemperaturerange,V =5V– 0.5V(unlessotherwisenoted)(seeFigure1) CC –55(cid:176) Cto PARAMETER FROM TO 125(cid:176) C UNIT (INPUT) (OUTPUT) MIN MAX t 3.7 14.6 PLH AorB Y ns t 3.7 14.6 PHL Operating Characteristics V =5V,T =25(cid:176) C CC A PARAMETER TYP UNIT C Powerdissipationcapacitance 57 pF pd SubmitDocumentationFeedback 3

CD74ACT86-EP QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE www.ti.com SCHS357–MARCH2006 PARAMETER MEASUREMENT INFORMATION 2 × VCC TEST S1 S1 From Output R1 = 500 W Open tPLH/tPHL Open Under Test GND tPLZ/tPZL 2 × VCC CL = 50 pF tPHZ/tPZH GND (see Note A) R2 = 500 W tw 3 V Input 1.5 V 1.5 V LOAD CIRCUIT 0 V VOLTAGE WAVEFORMS PULSE DURATION 3 V 3 V Reference 1.5 V CLR Input Input 1.5 V 0 V 0 V tsu th trec 3 V 3 V IDnpautat 1.5 V 90% 90% 1.5 V CLK 1.5 V 10% 10% 0 V 0 V tr tf VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS RECOVERY TIME SETUP AND HOLD AND INPUT RISE AND FALL TIMES 3 V Input 1.5 V 1.5 V Output 3 V 1.5 V 1.5 V 0 V Control 0 V tPLH tPHL In-Phase VOH Output tPZL tPLZ Output 50% 90% 90% 50% VCC Waveform 1 ≈VCC 10% 10% tr tfVOL S(s1e aet N2 o×t eV CBC) 20% VCC 20% VCCVOL tPHL tPLH VOH tPZH tPHZ Out-ofO-Puhtapsuet 90% 501%0% VCC 105%0% 90% VOL WSa1v eaOfto uGrtmpNu D2t 80% VCC 80% VCCVOH tf tr (see Note B) ≈0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES OUTPUT ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 W , tr = 3 ns, tf = 3 ns. Phase relationships between waveforms are arbitrary. D. For clock inputs, fmax is measured with the input duty cycle at 50%. E. The outputs are measured one at a time, with one input transition per measurement. F. tPLH and tPHL are the same as tpd. G. tPZL and tPZH are the same as ten. H. tPLZ and tPHZ are the same as tdis. I. All parameters and waveforms are not applicable to all devices. Figure1.LoadCircuitandVoltageWaveforms 4 SubmitDocumentationFeedback

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) CD74ACT86MDREP ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 ACT86MEP & no Sb/Br) V62/06620-01XE ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 ACT86MEP & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 OTHER QUALIFIED VERSIONS OF CD74ACT86-EP : •Catalog: CD74ACT86 •Military: CD54ACT86 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) CD74ACT86MDREP SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) CD74ACT86MDREP SOIC D 14 2500 367.0 367.0 38.0 PackMaterials-Page2

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