CD54ACT163, CD74ACT163 4-BIT SYNCHRONOUS BINARY COUNTERS SCHS300B – APRIL 2000 – REVISED MARCH 2003 (cid:0) Inputs Are TTL-Voltage Compatible CD54ACT163...F PACKAGE (cid:0) CD74ACT163...E OR M PACKAGE Internal Look-Ahead for Fast Counting (TOP VIEW) (cid:0) Carry Output for n-Bit Cascading (cid:0) Synchronous Counting CLR 1 16 VCC (cid:0) Synchronously Programmable CLK 2 15 RCO A 3 14 QA description/ordering information B 4 13 QB C 5 12 QC The ’ACT163 devices are 4-bit binary counters. D 6 11 QD These synchronous, presettable counters feature ENP 7 10 ENT an internal carry look-ahead for application in GND 8 9 LOAD high-speed counting designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change, coincident with each other, when instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes normally associated with synchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform. The counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. Presetting is synchronous; therefore, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs. The clear function is synchronous. A low level at the clear (CLR) input sets all four of the flip-flop outputs low after the next low-to-high transition of CLK, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The active-low output of the gate used for decoding is connected to CLR to synchronously clear the counter to 0000 (LLLL). The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. ENP, ENT, and a ripple-carry output (RCO) are instrumental in accomplishing this function. Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a high-level pulse while the count is maximum (9 or 15, with Q high). This high-level overflow ripple-carry pulse A can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK. These devices feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times. ORDERING INFORMATION ORDERABLE TOP-SIDE TA PACKAGE† PART NUMBER MARKING PDIP – E Tube CD74ACT163E CD74ACT163E Tube CD74ACT163M –5555°°CC ttoo 112255°°CC SSOOIICC – MM AACCTT116633MM Tape and reel CD74ACT163M96 CDIP – F Tube CD54ACT163F3A CD54ACT163F3A Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright  2003, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments On products compliant to MIL-PRF-38535, all parameters are tested standard warranty. Production processing does not necessarily include unless otherwise noted. On all other products, production testing of all parameters. processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

CD54ACT163, CD74ACT163 4-BIT SYNCHRONOUS BINARY COUNTERS SCHS300B – APRIL 2000 – REVISED MARCH 2003 FUNCTION TABLE INPUTS OUTPUTS FFUUNNCCTTIIOONN CLR CLK ENP ENT LOAD A,B,C,D Qn RCO L ↑ X X X X L L Reset (clear) h ↑ X X l l L L PPaarraalllleell llooaadd h ↑ X X l h H Note 1 h ↑ h h h X Count Note 1 Count h X l X h X qn Note 1 IInnhhiibbiitt h X X l h X qn L H = high level, L = low level, X = don’t care, h = high level one setup time prior to the CLK low-to-high transition, l = low level one setup time prior to the CLK low-to-high transition, q = the state of the referenced output prior to the CLK low-to-high transition, and ↑ = CLK low-to-high transition. NOTE 1: The RCO output is high when ENT is high and the counter is at terminal count (HHHH). 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CD54ACT163, CD74ACT163 4-BIT SYNCHRONOUS BINARY COUNTERS SCHS300B – APRIL 2000 – REVISED MARCH 2003 logic diagram (positive logic) 9 LOAD 10 ENT 15 RCO LD† 7 ENP CK† 2 CLK 1 CK LD CLR R M1 G2 1, 2T/1C3 14 G4 QA 3 A 3D 4R M1 G2 1, 2T/1C3 13 G4 QB 4 B 3D 4R M1 G2 1, 2T/1C3 12 G4 QC 5 C 3D 4R M1 G2 1, 2T/1C3 11 G4 QD 6 D 3D 4R †For simplicity, routing of complementary signals LD and CK is not shown on this overall logic diagram. The uses of these signals are shown on the logic diagram of the D/T flip-flops. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

CD54ACT163, CD74ACT163 4-BIT SYNCHRONOUS BINARY COUNTERS SCHS300B – APRIL 2000 – REVISED MARCH 2003 logic symbol, each D/T flip-flop LD (Load) M1 TE (Toggle Enable) G2 CK (Clock) 1, 2T/1C3 Q (Output) G4 D (Inverted Data) 3D R (Inverted Reset) 4R logic diagram, each D/T flip-flop (positive logic) CK LD TE LD† TG TG TG Q LD† TG CK† D CK† TG TG CK† CK† R †The origins of LD and CK are shown in the logic diagram of the overall device. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CD54ACT163, CD74ACT163 4-BIT SYNCHRONOUS BINARY COUNTERS SCHS300B – APRIL 2000 – REVISED MARCH 2003 typical clear, preset, count, and inhibit sequence The following sequence is illustrated below: 1. Clear outputs to zero (synchronous) 2. Preset to binary 12 3. Count to 13, 14, 15, 0, 1, and 2 4. Inhibit CLR LOAD A B Data Inputs C D CLK ENP ENT QA QB Data Outputs QC QD RCO 12 13 14 15 0 1 2 Count Inhibit Sync Preset Clear POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

CD54ACT163, CD74ACT163 4-BIT SYNCHRONOUS BINARY COUNTERS SCHS300B – APRIL 2000 – REVISED MARCH 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V CC Input clamp current, I (V < 0 or V > V ) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA IK I I CC Output clamp current, I (V < 0 or V > V ) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA OK O O CC Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA O O CC Continuous current through V or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA CC Package thermal impedance, θJA (see Note 3): E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C stg †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 3. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 4) –55°C to –40°C to TA = 25°C 125°C 85°C UNIT MIN MAX MIN MAX MIN MAX VCC Supply voltage 4.5 5.5 4.5 5.5 4.5 5.5 V VIH High-level input voltage 2 2 2 V VIL Low-level input voltage 0.8 0.8 0.8 V VI Input voltage 0 VCC 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC 0 VCC V IOH High-level output current –24 –24 –24 mA IOL Low-level output current 24 24 24 mA ∆t/∆v Input transition rise or fall rate 10 10 10 ns NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CD54ACT163, CD74ACT163 4-BIT SYNCHRONOUS BINARY COUNTERS SCHS300B – APRIL 2000 – REVISED MARCH 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) –55°C to –40°C to PARAMETER TEST CONDITIONS VCCCC TA = 25°C 125°C 85°C UNIT MIN MAX MIN MAX MIN MAX IOH = –50 µA 4.5 V 4.4 4.4 4.4 IOH = –24 mA 4.5 V 3.94 3.7 3.8 VVOOHH VVII == VVIIHH oorr VVIILL IOH = –50 mA† 5.5 V – 3.85 – VV IOH = –75 mA† 5.5 V – – 3.85 IOL = 50 µA 4.5 V 0.1 0.1 0.1 IOL = 24 mA 4.5 V 0.36 0.5 0.44 VVOOLL VVII == VVIIHH oorr VVIILL IOL = 50 mA† 5.5 V – 1.65 – VV IOL = 75 mA† 5.5 V – – 1.65 II VI = VCC or GND 5.5 V ±0.1 ±1 ±1 µA ICC VI = VCC or GND, IO = 0 5.5 V 8 160 80 µA 4.5 V to (cid:0)ICC‡ VI = VCC –2.1 V 5.5 V 2.4 3 2.8 mA Ci 10 10 10 pF †Test one output at a time, not exceeding 1-second duration. Measurement is made by forcing indicated current and measuring voltage to minimize power dissipation. Test verifies a minimum 50-(cid:1) transmission-line drive capability at 85°C and 75-(cid:1) transmission-line drive capability at 125°C. ‡Additional quiescent supply current per input pin, TTL inputs high, 1 unit load ACT INPUT LOAD TABLE INPUT UNIT LOAD A, B, C, or D 0.13 CLK 1 CLR, ENT 0.83 LOAD 0.67 ENP 0.5 Unit Load is ∆ICC limit specified in electrical characteristics table (e.g., 2.4 mA at 25°C). timing requirements over recommended operating conditions (unless otherwise noted) –55°C to –40°C to 125°C 85°C UNIT MIN MAX MIN MAX fclock Clock frequency 80 91 MHz tw Pulse duration CLK high or low 6.2 5.4 ns A, B, C, or D 5 4.4 ENP or ENT 6 5.3 ttsu SSeettuupp ttiimmee, bbeeffoorree CCLLKK↑↑↑ nnss LOAD low 7.5 6.6 CLR inactive 7.5 6.6 A, B, C, or D 0 0 ENP or ENT 0 0 tthh HHoolldd ttiimmee, aafftteerr CCLLKK↑↑↑ nnss LOAD low 0 0 CLR inactive 0 0 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

CD54ACT163, CD74ACT163 4-BIT SYNCHRONOUS BINARY COUNTERS SCHS300B – APRIL 2000 – REVISED MARCH 2003 switching characteristics over recommended operating conditions, C = 50 pF (unless otherwise L noted) (see Figure 1) –55°C to –40°C to PARAMETER FROM TO 125°C 85°C UNIT ((IINNPPUUTT)) ((OOUUTTPPUUTT)) MIN MAX MIN MAX fmax 80 91 MHz RCO 4.2 16.7 4.3 15.2 CCLLKK tpd Any Q 4.1 16.5 4.2 15 ns ENT RCO 2.7 10.8 2.8 9.8 operating characteristics, T = 25°C A PARAMETER TEST CONDITIONS TYP UNIT Cpd Power dissipation capacitance No load 66 pF 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CD54ACT163, CD74ACT163 4-BIT SYNCHRONOUS BINARY COUNTERS SCHS300B – APRIL 2000 – REVISED MARCH 2003 PARAMETER MEASUREMENT INFORMATION 2 × VCC TEST S1 R1 = 500 Ω S1 Open tPLH/tPHL Open From Output Under Test GND tPLZ/tPZL 2 × VCC tPHZ/tPZH GND CL = 50 pF R2 = 500 Ω (see Note A) tw 3 V NOTE: When VCC = 1.5 V, R1 and R2 = 1 kΩ. Input 1.5 V 1.5 V LOAD CIRCUIT 0 V VOLTAGE WAVEFORMS PULSE DURATION 3 V 3 V CLR 1.5 V Reference 1.5 V Input Input 0 V 0 V trec tsu th 3 V 3 V Data 90% 90% CLK 1.5 V Input 1.5 V 1.5 V 10% 10% 0 V 0 V tr tf VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS RECOVERY TIME SETUP AND HOLD AND INPUT RISE AND FALL TIMES 3 V 3 V Input 1.5 V 1.5 V Output 1.5 V 1.5 V 0 V Control 0 V tPLH tPHL tPZL tPLZ InO-Puhtapsuet 105%0% 90%tr 90% 501%0% VtfCVVCOOHL S(1Ws eaaetv 2eNO f×oou tVretmpC Bu C1)t 50% VCC VOL + 0≈.V3VO CVLC tPHL tPLH tPZH tPHZ VOH Out-of-Phase 90% 50% VCC 50% 90% Output VOH Output 10% 10% VOL WSa1v aetf oOrpme n2 50% VCC VOH – 0.3 V tf tr (see Note B) ≈0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES OUTPUT ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. Phase relationships between waveforms are arbitrary. D. For clock inputs, fmax is measured with the input duty cycle at 50%. E. The outputs are measured one at a time with one input transition per measurement. F. tPLH and tPHL are the same as tpd. G. tPZL and tPZH are the same as ten. H. tPLZ and tPHZ are the same as tdis. I. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) CD54ACT163F3A ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type -55 to 125 CD54ACT163F3A CD74ACT163E ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -55 to 125 CD74ACT163E & no Sb/Br) CD74ACT163M ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 ACT163M & no Sb/Br) CD74ACT163M96 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 ACT163M & no Sb/Br) CD74ACT163M96E4 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 ACT163M & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF CD54ACT163, CD74ACT163 : •Catalog: CD74ACT163 •Military: CD54ACT163 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) CD74ACT163M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) CD74ACT163M96 SOIC D 16 2500 333.2 345.9 28.6 PackMaterials-Page2

None

None

None

None

IMPORTANTNOTICEANDDISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated