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CD74AC273M产品简介:
ICGOO电子元器件商城为您提供CD74AC273M由Texas Instruments设计生产,在icgoo商城现货销售,并且可以通过原厂、代理商等渠道进行代购。 CD74AC273M价格参考。Texas InstrumentsCD74AC273M封装/规格:逻辑 - 触发器, 。您可以下载CD74AC273M参考资料、Datasheet数据手册功能说明书,资料中有CD74AC273M 详细功能的应用电路图电压和使用方法及教程。
参数 | 数值 |
产品目录 | 集成电路 (IC)半导体 |
描述 | IC D-TYPE POS TRG SNGL 20SOIC触发器 Octal D-Type Flip-Flop with Reset |
产品分类 | |
品牌 | Texas Instruments |
产品手册 | |
产品图片 | |
rohs | 符合RoHS无铅 / 符合限制有害物质指令(RoHS)规范要求 |
产品系列 | 逻辑集成电路,触发器,Texas Instruments CD74AC273M74AC |
数据手册 | |
产品型号 | CD74AC273M |
不同V、最大CL时的最大传播延迟 | 13.5ns @ 5V,50pF |
产品目录页面 | |
产品种类 | 触发器 |
传播延迟时间 | 169 ns |
低电平输出电流 | 24 mA |
元件数 | 1 |
其它名称 | 296-25963-5 |
功能 | 主复位 |
包装 | 管件 |
单位重量 | 500.700 mg |
商标 | Texas Instruments |
安装类型 | 表面贴装 |
安装风格 | SMD/SMT |
封装 | Tube |
封装/外壳 | 20-SOIC(0.295",7.50mm 宽) |
封装/箱体 | SOIC-20 |
工作温度 | -55°C ~ 125°C (TA) |
工厂包装数量 | 25 |
最大工作温度 | + 125 C |
最小工作温度 | - 55 C |
极性 | Non-Inverting |
标准包装 | 25 |
每元件位数 | 8 |
电压-电源 | 1.5 V ~ 5.5 V |
电流-输出高,低 | 24mA,24mA |
电流-静态 | 8µA |
电源电压-最大 | 5.5 V |
电源电压-最小 | 1.5 V |
电路数量 | 8 |
类型 | D 型 |
系列 | CD74AC273 |
触发器类型 | 正边沿 |
输入电容 | 10pF |
输入类型 | CMOS |
输入线路数量 | 8 |
输出类型 | 非反相 |
输出线路数量 | 8 |
逻辑类型 | D-Type Flip-Flop |
逻辑系列 | AC |
频率-时钟 | 100MHz |
高电平输出电流 | - 24 mA |
CD54AC273, CD74AC273 CD54ACT273, CD74ACT273 Data sheet acquired from Harris Semiconductor SCHS249B Octal D Flip-Flop with Reset August 1998 - Revised July 2002 Features Description • Buffered Inputs The’AC273and’ACT273devicesareoctalD-typeflip-flops with reset that utilize advanced CMOS logic technology. • Typical Propagation Delay Information at the D input is transferred to the Q output on - 6.5ns at VCC = 5V, TA = 25oC, CL = 50pF thepositive-goingedgeoftheclockpulse.Alleightflip-flops arecontrolledbyacommonclock(CP)andacommonreset • Exceeds 2kV ESD Protection MIL-STD-883, Method 3015 (MR). Resetting is accomplished by a low voltage level independent of the clock. • SCR-Latchup-Resistant CMOS Process and Circuit Design Ordering Information • Speed of Bipolar FAST™/AS/S with Significantly Reduced Power Consumption PART TEMPERATURE NUMBER RANGE PACKAGE • Balanced Propagation Delays CD74AC273E 0oC to 70oC 20 Ld PDIP • AC Types Feature 1.5V to 5.5V Operation and -40oC to 85oC Balanced Noise Immunity at 30% of the Supply -55oC to 125oC • ±24mA Output Drive Current CD54AC273F3A -55oC to 125oC 20 Ld CDIP - Fanout to 15 FAST™ ICs CD74ACT273E 0oC to 70oC 20 Ld PDIP - Drives 50Ω Transmission Lines -40oC to 85oC -55oC to 125oC CD54ACT273F3A -55oC to 125oC 20 Ld CDIP Pinout CD74AC273M 0oC to 70oC 20 Ld SOIC -40oC to 85oC CD54AC273, CD54ACT273 -55oC to 125oC (CDIP) CD74AC273, CD74ACT273 CD74ACT273M 0oC to 70oC 20 Ld SOIC (PDIP, SOIC) -40oC to 85oC TOP VIEW -55oC to 125oC NOTES: MR 1 20 VCC 1. Whenordering,usetheentirepartnumber.Addthesuffix96to Q0 2 19 Q7 obtain the variant in the tape and reel. D0 3 18 D7 2. Waferanddieforthispartnumberisavailablewhichmeetsall D1 4 17 D6 electricalspecifications.Pleasecontactyourlocalsalesofficefor ordering information. Q1 5 16 Q6 Q2 6 15 Q5 D2 7 14 D5 D3 8 13 D4 Q3 9 12 Q4 GND 10 11 CP CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. FAST™ is a Trademark of Fairchild Semiconductor. 1 Copyright © 2002, Texas Instruments Incorporated
CD54AC273, CD74AC273, CD54ACT273, CD74ACT273 Functional Diagram CLOCK CP D0 Q0 D1 Q1 D2 Q2 D3 Q3 DATA DATA INPUTS OUTPUTS D4 Q4 D5 Q5 D6 Q6 D7 Q7 RESETMR TRUTH TABLE INPUTS OUTPUTS RESET CLOCK DATA (MR) CP Dn Qn L X X L H ↑ H H H ↑ L L H L X Q0 H=Highlevel(steadystate),L=Lowlevel(steadystate),X=Irrel- evant,↑=TransitionfromLowtoHighlevel,Q0=ThelevelofQ before the indicated steady-state input conditions were estab- lished. 2
CD54AC273, CD74AC273, CD54ACT273, CD74ACT273 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V Thermal Resistance,θJA(Typical, Note 5) DC Input Diode Current, IIK E Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69oC/W For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA M Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58oC/W DC Output Diode Current, IOK Maximum Junction Temperature (Plastic Package) . . . . . . . . . .150oC For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC DC Output Source or Sink Current per Output Pin, IO Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA DC VCC or Ground Current, ICC orIGND (Note 3) . . . . . . . . .±100mA Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . .-55oC to 125oC Supply Voltage Range, VCC (Note 4) AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Slew Rate, dt/dv AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max) AC Types, 3.6V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max) ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max) CAUTION:Stressesabovethoselistedin“AbsoluteMaximumRatings”maycausepermanentdamagetothedevice.Thisisastressonlyratingandoperation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 3. For up to 4 outputs per device, add±25mA for each additional output. 4. Unless otherwise specified, all voltages are referenced to ground. 5. The package thermal impedance is calculated in accordance with JESD 51. DC Electrical Specifications TEST -40oC TO -55oC TO CONDITIONS 25oC 85oC 125oC VCC PARAMETER SYMBOL VI(V) IO(mA) (V) MIN MAX MIN MAX MIN MAX UNITS AC TYPES High Level Input Voltage VIH - - 1.5 1.2 - 1.2 - 1.2 - V 3 2.1 - 2.1 - 2.1 - V 5.5 3.85 - 3.85 - 3.85 - V Low Level Input Voltage VIL - - 1.5 - 0.3 - 0.3 - 0.3 V 3 - 0.9 - 0.9 - 0.9 V 5.5 - 1.65 - 1.65 - 1.65 V High Level Output Voltage VOH VIH or VIL -0.05 1.5 1.4 - 1.4 - 1.4 - V -0.05 3 2.9 - 2.9 - 2.9 - V -0.05 4.5 4.4 - 4.4 - 4.4 - V -4 3 2.58 - 2.48 - 2.4 - V -24 4.5 3.94 - 3.8 - 3.7 - V -75 5.5 - - 3.85 - - - V (Note 6, 7) -50 5.5 - - - - 3.85 - V (Note 6, 7) 3
CD54AC273, CD74AC273, CD54ACT273, CD74ACT273 DC Electrical Specifications (Continued) TEST -40oC TO -55oC TO CONDITIONS 25oC 85oC 125oC VCC PARAMETER SYMBOL VI(V) IO(mA) (V) MIN MAX MIN MAX MIN MAX UNITS Low Level Output Voltage VOL VIH or VIL 0.05 1.5 - 0.1 - 0.1 - 0.1 V 0.05 3 - 0.1 - 0.1 - 0.1 V 0.05 4.5 - 0.1 - 0.1 - 0.1 V 12 3 - 0.36 - 0.44 - 0.5 V 24 4.5 - 0.36 - 0.44 - 0.5 V 75 5.5 - - - 1.65 - - V (Note 6, 7) 50 5.5 - - - - - 1.65 V (Note 6, 7) Input Leakage Current II VCC or - 5.5 - ±0.1 - ±1 - ±1 µA GND Quiescent Supply Current ICC VCC or 0 5.5 - 8 - 80 - 160 µA MSI GND ACT TYPES High Level Input Voltage VIH - - 4.5 to 2 - 2 - 2 - V 5.5 Low Level Input Voltage VIL - - 4.5 to - 0.8 - 0.8 - 0.8 V 5.5 High Level Output Voltage VOH VIH or VIL -0.05 4.5 4.4 - 4.4 - 4.4 - V -24 4.5 3.94 - 3.8 - 3.7 - V -75 5.5 - - 3.85 - - - V (Note 6, 7) -50 5.5 - - - - 3.85 - V (Note 6, 7) Low Level Output Voltage VOL VIH or VIL 0.05 4.5 - 0.1 - 0.1 - 0.1 V 24 4.5 - 0.36 - 0.44 - 0.5 V 75 5.5 - - - 1.65 - - V (Note 6, 7) 50 5.5 - - - - - 1.65 V (Note 6, 7) Input Leakage Current II VCC or - 5.5 - ±0.1 - ±1 - ±1 µA GND Quiescent Supply Current ICC VCC or 0 5.5 - 8 - 80 - 160 µA MSI GND AdditionalSupplyCurrentper ∆ICC VCC - 4.5 to - 2.4 - 2.8 - 3 mA Input Pin TTL Inputs High -2.1 5.5 1 Unit Load NOTES: 6. Testoneoutputatatimefora1-secondmaximumduration.Measurementismadebyforcingcurrentandmeasuringvoltagetominimize power dissipation. 7. Test verifies a minimum 50Ω transmission-line-drive capability at 85oC, 75Ω at 125oC. ACT Input Load Table INPUT UNIT LOAD Dn 0.5 MR 0.57 CP 1 NOTE: Unitloadis∆ICClimitspecifiedinDCElectricalSpecifications Table, e.g., 2.4mA max at 25oC. 4
CD54AC273, CD74AC273, CD54ACT273, CD74ACT273 Prerequisite For Switching Function -40oC TO 85oC -55oC TO 125oC PARAMETER SYMBOL VCC (V) MIN MAX MIN MAX UNITS AC TYPES Data to CP Set-Up Time tSU 1.5 2 - 2 - ns 3.3 2 - 2 - ns (Note 9) 5 2 - 2 - ns (Note 10) Hold Time tH 1.5 2 - 2 - ns 3.3 2 - 2 - ns 5 2 - 2 - ns Removal Time,MR to CP tREM 1.5 2 - 2 - ns 3.3 2 - 2 - ns 5 2 - 2 - ns MR Pulse Width tW 1.5 55 - 63 - ns 3.3 6.1 - 7 - ns 5 4.4 - 5 - ns CP Pulse Width tW 1.5 55 - 63 - ns 3.3 6.1 - 7 - ns 5 4.4 - 5 - ns CP Frequency fMAX 1.5 9 - 8 - MHz 3.3 81 - 71 - MHz 5 114 - 100 - MHz ACT TYPES Data to CP Set-Up Time tSU 5 2 - 2 - ns (Note 10) Hold Time tH 5 2 - 2 - ns Removal TimeMR to CP tREM 5 2 - 2 - ns MR Pulse Width tW 5 4.4 - 5 - ns CP Pulse Width tW 5 5.3 - 6 - ns CP Frequency fMAX 5 97 - 85 - MHz Switching SpecificationsInput tr, tf = 3ns, CL= 50pF (Worst Case) -40oC TO 85oC -55oC TO 125oC PARAMETER SYMBOL VCC (V) MIN TYP MAX MIN TYP MAX UNITS AC TYPES Propagation Delay, tPLH, tPHL 1.5 - - 154 - - 169 ns CP to Qn 3.3 4.9 - 17.2 4.7 - 18.9 ns (Note 9) 5 3.5 - 12.3 3.4 - 13.5 ns (Note 10) 5
CD54AC273, CD74AC273, CD54ACT273, CD74ACT273 Switching SpecificationsInput tr, tf = 3ns, CL= 50pF (Worst Case) (Continued) -40oC TO 85oC -55oC TO 125oC PARAMETER SYMBOL VCC (V) MIN TYP MAX MIN TYP MAX UNITS Propagation Delay, tPLH, tPHL 1.5 - - 154 - - 169 ns MR to Qn 3.3 4.9 - 17.2 4.7 - 18.9 ns 5 3.5 - 12.3 3.4 - 13.5 ns Input Capacitance CI - - - 10 - - 10 pF Power Dissipation Capacitance CPD - - 45 - - 45 - pF (Note 11) ACT TYPES Propagation Delay, tPLH, tPHL 5 3.5 - 12.3 3.4 - 13.5 ns CP to Qn (Note 10) Propagation Delay, tPLH, tPHL 5 3.5 - 12.3 3.4 - 13.5 ns MR to Qn Input Capacitance CI - - - 10 - - 10 pF Power Dissipation Capacitance CPD - - 45 - - 45 - pF (Note 11) NOTES: 8. Limits tested 100%. 9. 3.3V Min is at 3.6V, Max is at 3V. 10. 5V Min is at 5.5V, Max is at 4.5V. 11. CPD is used to determine the dynamic power consumption per flip-flop. AC: PD = CPD VCC2 fi=∑ (CL VCC2 fo) ACT:PD=CPDVCC2fi+∑(CLVCC2fo)+VCC∆ICCwherefi=inputfrequency,fo=outputfrequency,CL=outputloadcapacitance, VCC = supply voltage. INPUT LEVEL LINEPVUETL tr tf MR VS VS GND CP10% 9V0S% V10S% VS tW tREM INPUT tW tPLH CP VS tPHL (Q) tPLH Q VS VS Q VS FIGURE 1. PROPAGATION DELAY TIMES AND CLOCK FIGURE 2. PREREQUISITE AND PROPAGATION DELAY PULSE WIDTH TIMES FOR MASTER RESET 6
CD54AC273, CD74AC273, CD54ACT273, CD74ACT273 OUTPUT LEVEL D VS VS VS VS tH(L) tH(H) tSU(L) tSU(H) CP VS VS FIGURE 3. PREREQUISITE FOR CLOCK OUTPUT RL (NOTE) 500Ω DUT OUTPUT CL LOAD 50pF NOTE: For AC Series Only: When VCC = 1.5V, RL = 1kΩ. AC ACT Input Level VCC 3V Input Switching Voltage, VS 0.5 VCC 1.5V Output Switching Voltage, VS 0.5 VCC 0.5 VCC FIGURE 4. PROPAGATION DELAY TIMES 7
PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) CD54AC273F3A ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 CD54AC273F3A CD54ACT273F3A ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 CD54ACT273F3A CD74AC273E ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type -55 to 125 CD74AC273E (RoHS) CD74AC273EE4 ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type -55 to 125 CD74AC273E (RoHS) CD74AC273M ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 AC273M & no Sb/Br) CD74AC273M96 ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 AC273M & no Sb/Br) CD74ACT273E ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type -55 to 125 CD74ACT273E (RoHS) CD74ACT273EE4 ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type -55 to 125 CD74ACT273E (RoHS) CD74ACT273M ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 ACT273M & no Sb/Br) CD74ACT273M96 ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 ACT273M & no Sb/Br) CD74ACT273M96E4 ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 ACT273M & no Sb/Br) CD74ACT273PW ACTIVE TSSOP PW 20 70 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HM273 & no Sb/Br) CD74ACT273PWR ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HM273 & no Sb/Br) CD74ACT273PWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HM273 & no Sb/Br) CD74ACT273SM96 ACTIVE SSOP DB 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 ACT273SM & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. Addendum-Page 1
PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF CD54AC273, CD54ACT273, CD74AC273, CD74ACT273 : •Catalog: CD74AC273, CD74ACT273 •Military: CD54AC273, CD54ACT273 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 2-Oct-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) CD74AC273M96 SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 CD74ACT273M96 SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 CD74ACT273PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.0 1.4 8.0 16.0 Q1 CD74ACT273SM96 SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 PackMaterials-Page1
PACKAGE MATERIALS INFORMATION www.ti.com 2-Oct-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) CD74AC273M96 SOIC DW 20 2000 367.0 367.0 45.0 CD74ACT273M96 SOIC DW 20 2000 367.0 367.0 45.0 CD74ACT273PWR TSSOP PW 20 2000 367.0 367.0 38.0 CD74ACT273SM96 SSOP DB 20 2000 367.0 367.0 38.0 PackMaterials-Page2
PACKAGE OUTLINE DB0020A SSOP - 2 mm max height SCALE 2.000 SMALL OUTLINE PACKAGE C 8.2 TYP 7.4 A 0.1 C PIN 1 INDEX AREA SEATING PLANE 18X 0.65 20 1 2X 7.5 5.85 6.9 NOTE 3 10 11 0.38 20X 0.22 5.6 B 0.1 C A B 5.0 NOTE 4 2 MAX (0.15) TYP 0.25 SEE DETAIL A GAGE PLANE 0 -8 0.95 0.05 MIN 0.55 DETA 15AIL A TYPICAL 4214851/B 08/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-150. www.ti.com
EXAMPLE BOARD LAYOUT DB0020A SSOP - 2 mm max height SMALL OUTLINE PACKAGE 20X (1.85) SYMM (R0.05) TYP 1 20X (0.45) 20 SYMM 18X (0.65) 10 11 (7) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000 R MASK DETAILS 4214851/B 08/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com
EXAMPLE STENCIL DESIGN DB0020A SSOP - 2 mm max height SMALL OUTLINE PACKAGE 20X (1.85) SYMM (R0.05) TYP 1 20X (0.45) 20 SYMM 18X (0.65) 10 11 (7) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4214851/B 08/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com
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PACKAGE OUTLINE DW0020A SOIC - 2.65 mm max height SCALE 1.200 SOIC C 10.63 SEATING PLANE TYP 9.97 A PIN 1 ID 0.1 C AREA 18X 1.27 20 1 13.0 2X 12.6 11.43 NOTE 3 10 11 0.51 20X 7.6 0.31 2.65 MAX B 7.4 0.25 C A B NOTE 4 0.33 TYP 0.10 0.25 SEE DETAIL A GAGE PLANE 0.3 1.27 0 - 8 0.1 0.40 DETAIL A TYPICAL 4220724/A 05/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS-013. www.ti.com
EXAMPLE BOARD LAYOUT DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM (R0.05) TYP 10 11 (9.3) LAND PATTERN EXAMPLE SCALE:6X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220724/A 05/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com
EXAMPLE STENCIL DESIGN DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM 10 11 (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4220724/A 05/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com
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