CD54/74AC245, CD54/74ACT245 Data sheet acquired from Harris Semiconductor SCHS245B Octal-Bus Transceiver, September 1998 - Revised October 2000 Three-State, Non-Inverting Features Description • Buffered Inputs The ’AC245 and ’ACT245 are octal-bus transceivers that utilize Advanced CMOS Logic technology. They are non- • Typical Propagation Delay inverting three-state bidirectional transceiver-buffers - 4ns at VCC = 5V, TA = 25oC, CL = 50pF intendedfortwo-waytransmissionfrom“A”busto“B”busor “B” bus to “A”. The logic level present on the direction input • Exceeds 2kV ESD Protection per MIL-STD-883, (DIR)determinesthedatadirection.Whentheoutputenable Method 3015 input (OE) is HIGH, the outputs are in the high-impedance • SCR-Latchup-Resistant CMOS Process and Circuit state. [ /Title Design Ordering Information (CD74 • Speed of Bipolar FAST™/AS/S with Significantly AC245 Reduced Power Consumption PART TEMP. NUMBER RANGE (oC) PACKAGE , • Balanced Propagation Delays CD54AC245F3A -55 to 125 20 Ld CERDIP CD74 • AC Types Feature 1.5V to 5.5V Operation and CD74AC245E -55 to 125 20 Ld PDIP ACT24 Balanced Noise Immunity at 30% of the Supply 5) • – 24mA Output Drive Current CD74AC245M -55 to 125 20 Ld SOIC /Sub- - Fanout to 15 FAST™ ICs CD74AC245SM -55 to 125 20 Ld SSOP ject - Drives 50W Transmission Lines CD54ACT245F3A -55 to 125 20 Ld CERDIP (Octal- CD74ACT245E -55 to 125 20 Ld PDIP Bus CD74ACT245M -55 to 125 20 Ld SOIC Trans- CD74ACT245SM -55 to 125 20 Ld SSOP ceiver, NOTES: Three- 1. Whenordering,usetheentirepartnumber.Addthesuffix96to obtain the variant in the tape and reel. State, 2. Waferanddieforthispartnumberisavailablewhichmeetsall Non- electricalspecifications.PleasecontactyourlocalTIsalesofficeor Invert- customer service for ordering information. ing) /Autho Pinout r () /Key- CD54AC245, CD54ACT245 (CERDIP) words CD74AC245, CD74ACT245 (Har- (PDIP, SOIC, SSOP) TOP VIEW ris Semi- DIR 1 20 VCC con- A0 2 19 OE ductor, A1 3 18 B0 Advan A2 4 17 B1 ced A3 5 16 B2 CMOS A4 6 15 B3 ,Harris A5 7 14 B4 Semi- A6 8 13 B5 con- A7 9 12 B6 GND 10 11 B7 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. FAST™ is a Trademark of Fairchild Semiconductor. 1 Copyright © 2000, Texas Instruments Incorporated

CD54/74AC245, CD54/74ACT245 Functional Diagram 2 18 A0 B0 3 17 A1 B1 4 16 A2 B2 5 15 A3 B3 6 14 A4 B4 7 13 A5 B5 8 12 A6 B6 9 11 A7 B7 1 DIR 19 OE TRUTH TABLE CONTROL INPUTS OE DIR OPERATION L L B Data to A Bus L H A Data to B Bus H X Isolation H = High Level, L = Low Level, X = Irrelevant TopreventexcesscurrentsintheHigh-Z(isolation)modes,allI/O terminals should be terminated with 10kW to 1MW resistors. 2

CD54/74AC245, CD54/74ACT245 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V Thermal Resistance (Typical, Note 5) q JA (oC/W) DC Input Diode Current, IIK E Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .– 20mA M Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 DC Output Diode Current, IOK SM Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .– 50mA Maximum Junction Temperature (Plastic Package) . . . . . . . . . .150oC DC Output Source or Sink Current per Output Pin, IO Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .– 50mA Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC DC VCC or Ground Current, ICC orIGND (Note 3) . . . . . . . . .– 100mA Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . .-55oC to 125oC Supply Voltage Range, VCC (Note 4) AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Slew Rate, dt/dv AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max) AC Types, 3.6V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max) ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max) CAUTION:Stressesabovethoselistedin“AbsoluteMaximumRatings”maycausepermanentdamagetothedevice.Thisisastressonlyratingandoperation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 3. For up to 4 outputs per device, add– 25mA for each additional output. 4. Unless otherwise specified, all voltages are referenced to ground. 5. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications TEST -40oC TO -55oC TO CONDITIONS 25oC 85oC 125oC VCC PARAMETER SYMBOL VI(V) IO(mA) (V) MIN MAX MIN MAX MIN MAX UNITS AC TYPES High Level Input Voltage VIH - - 1.5 1.2 - 1.2 - 1.2 - V 3 2.1 - 2.1 - 2.1 - V 5.5 3.85 - 3.85 - 3.85 - V Low Level Input Voltage VIL - - 1.5 - 0.3 - 0.3 - 0.3 V 3 - 0.9 - 0.9 - 0.9 V 5.5 - 1.65 - 1.65 - 1.65 V High Level Output Voltage VOH VIH or VIL -0.05 1.5 1.4 - 1.4 - 1.4 - V -0.05 3 2.9 - 2.9 - 2.9 - V -0.05 4.5 4.4 - 4.4 - 4.4 - V -4 3 2.58 - 2.48 - 2.4 - V -24 4.5 3.94 - 3.8 - 3.7 - V -75 5.5 - - 3.85 - - - V (Note 6, 7) -50 5.5 - - - - 3.85 - V (Note 6, 7) 3

CD54/74AC245, CD54/74ACT245 DC Electrical Specifications (Continued) TEST -40oC TO -55oC TO CONDITIONS 25oC 85oC 125oC VCC PARAMETER SYMBOL VI(V) IO(mA) (V) MIN MAX MIN MAX MIN MAX UNITS Low Level Output Voltage VOL VIH or VIL 0.05 1.5 - 0.1 - 0.1 - 0.1 V 0.05 3 - 0.1 - 0.1 - 0.1 V 0.05 4.5 - 0.1 - 0.1 - 0.1 V 12 3 - 0.36 - 0.44 - 0.5 V 24 4.5 - 0.36 - 0.44 - 0.5 V 75 5.5 - - - 1.65 - - V (Note 6, 7) 50 5.5 - - - - - 1.65 V (Note 6, 7) Input Leakage Current II VCC or - 5.5 - – 0.1 - – 1 - – 1 m A GND Three-State Leakage IOZ VIH or VIL - 5.5 - – 0.5 - – 5 - – 10 m A Current VO=VCC or GND Quiescent Supply Current ICC VCC or 0 5.5 - 8 - 80 - 160 m A MSI GND ACT TYPES High Level Input Voltage VIH - - 4.5 to 2 - 2 - 2 - V 5.5 Low Level Input Voltage VIL - - 4.5 to - 0.8 - 0.8 - 0.8 V 5.5 High Level Output Voltage VOH VIH or VIL -0.05 4.5 4.4 - 4.4 - 4.4 - V -24 4.5 3.94 - 3.8 - 3.7 - V -75 5.5 - - 3.85 - - - V (Note 6, 7) -50 5.5 - - - - 3.85 - V (Note 6, 7) Low Level Output Voltage VOL VIH or VIL 0.05 4.5 - 0.1 - 0.1 - 0.1 V 24 4.5 - 0.36 - 0.44 - 0.5 V 75 5.5 - - - 1.65 - - V (Note 6, 7) 50 5.5 - - - - - 1.65 V (Note 6, 7) Input Leakage Current II VCC or - 5.5 - – 0.1 - – 1 - – 1 m A GND Three-State or Leakage IOZ VIH or VIL - 5.5 - – 0.5 - – 5 - – 10 m A Current VO=VCC or GND Quiescent Supply Current ICC VCC or 0 5.5 - 8 - 80 - 160 m A MSI GND AdditionalSupplyCurrentper D ICC VCC - 4.5 to - 2.4 - 2.8 - 3 mA Input Pin TTL Inputs High -2.1 5.5 1 Unit Load NOTES: 6. Testoneoutputatatimefora1-secondmaximumduration.Measurementismadebyforcingcurrentandmeasuringvoltagetominimize power dissipation. 7. Test verifies a minimum 50W transmission-line-drive capability at 85oC, 75W at 125oC. 4

CD54/74AC245, CD54/74ACT245 ACT Input Load Table INPUT UNIT LOAD An, Bn 0.83 OE 0.64 DIR 0.25 NOTE: UnitloadisD ICClimitspecifiedinDCElectricalSpecifications Table, e.g., 2.4mA max at 25oC. Switching SpecificationsInput tr, tf = 3ns, CL= 50pF (Worst Case) -40oC TO 85oC -55oC TO 125oC PARAMETER SYMBOL VCC (V) MIN TYP MAX MIN TYP MAX UNITS AC TYPES Propagation Delay, tPLH, tPHL 1.5 - - 96 - - 106 ns Data to Output 3.3 3.2 - 10.8 3 - 11.9 ns (Note 9) 5 2.2 - 7.7 2.1 - 8.5 ns (Note 10) Propagation Delay, tPLZ, tPHZ 1.5 - - 159 - - 175 ns Output Disable to Output 3.3 4.7 - 15.9 4.4 - 17.5 ns 5 3.7 - 12.7 3.5 - 14 ns Propagation Delay, tPZL, tPZH 1.5 - - 159 - - 175 ns Output Enable to Output 3.3 5.6 - 19 5.3 - 21 ns 5 3.7 - 12.7 3.5 - 14 ns Minimum (Valley) VOH During VOHV 5 - 4 at - - 4 at - V Switching of Other Outputs See Figure 1 25oC 25oC (OutputUnderTestNotSwitching) Maximum (Peak) VOL During VOLP 5 - 1 at - - 1 at - V Switching of Other Outputs See Figure 1 25oC 25oC (OutputUnderTestNotSwitching) Three-State Output Capacitance CO - - 15 - - 15 - pF Input Capacitance CI - - - 10 - - 10 pF Power Dissipation Capacitance CPD - - 57 - - 57 - pF (Note 11) ACT TYPES Propagation Delay, tPLH, tPHL 5 2.7 - 9.1 2.5 - 10 ns Data to Output (Note 10) Propagation Delay, tPLZ, tPHZ 5 3.7 12.7 3.5 14 ns Output Disable to Output Propagation Delay, tPZL, tPZH 5 3.8 13.1 3.6 14.4 ns Output Enable to Output Minimum (Valley) VOH During VOHV 5 - 4 at - - 4 at - V Switching of Other Outputs See Figure 1 25oC 25oC (OutputUnderTestNotSwitching) Maximum (Peak) VOL During VOLP 5 - 1 at - - 1 at - V Switching of Other Outputs See Figure 1 25oC 25oC (OutputUnderTestNotSwitching) 5

CD54/74AC245, CD54/74ACT245 Switching SpecificationsInput tr, tf = 3ns, CL= 50pF (Worst Case) (Continued) -40oC TO 85oC -55oC TO 125oC PARAMETER SYMBOL VCC (V) MIN TYP MAX MIN TYP MAX UNITS Three-State Output Capacitance CO - - 15 - - 15 - pF Input Capacitance CI - - - 10 - - 10 pF Power Dissipation Capacitance CPD - - 57 - - 57 - pF (Note 11) NOTES: 8. Limits tested 100% 9. 3.3V Min is at 3.6V, Max is at 3V. 10. 5V Min is at 5.5V, Max is at 4.5V. 11. CPD is used to determine the dynamic power consumption per channel. AC: PD = VCC2 fi(CPD + CL) ACT: PD = VCC2 fi(CPD + CL) + VCCD ICC where fi = input frequency, CL = output load capacitance, VCC = supply voltage. VOH OTHER OUTPUTS VOL VOH OUTPUT VOHV UNDER TEST VOLP VOL NOTES: 12. Input pulses have the following characteristics: PRR£ 1MHz, tr = 3ns, SKEW 1ns. 13. R.F.fixturewith700MHzdesignrulesrequired.ICshouldbesolderedintotestboardandbypassedwith0.1m Fcapacitor.Scopeand probes require 700MHz bandwidth. FIGURE 1. SIMULTANEOUS SWITCHING TRANSIENT WAVEFORMS 6

CD54/74AC245, CD54/74ACT245 tf = 3ns tr = 3ns INPUT LEVEL 90% OUTPUTS DISABLED VS 10% GND tPLZ tPZL OUTPUT: LOW TO OFF VS TO LOW 0.2 VCC VOL („ VCC) tPHZ tPZH OUTPUT: 0.8 VCC HIGH TO OFF VS TO HIGH OUTPUTS OUTPUTS OUTPUTS ENABLED DISABLED ENABLED GND (tPHZ, tPZH) OPEN (tPHL, tPLH) OTHER RL 2 VCC (tPLZ, tPZL) INPUTS DUT WITH 500W (OPEN DRAIN) TIED HIGH THREE- OUT OR LOW STATE CL RL OUTPUT OUTPUT 50pF 500W (NOTE 14) DISABLE NOTE: 14. For AC Series only: When VCC = 1.5V, RL = 1kW . FIGURE 2. THREE-STATE PROPAGATION DELAY TIMES AND TEST CIRCUIT tr = 3ns tf = 3ns INPUT LEVEL 90% An VS GND 10% tPLH tPHL Bn VS FIGURE 3. PROPAGATION DELAY TIMES OUTPUT RL (NOTE) 500W DUT OUTPUT CL LOAD 50pF NOTE: For AC Series Only: When VCC = 1.5V, RL = 1kW. AC ACT Input Level VCC 3V Input Switching Voltage, VS 0.5 VCC 1.5V Output Switching Voltage, VS 0.5 VCC 0.5 VCC FIGURE 4. PROPAGATION DELAY TIMES 7

PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) CD54AC245F3A ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 CD54AC245F3A CD54ACT245F3A ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 CD54ACT245F3A CD74AC245E ACTIVE PDIP N 20 20 Pb-Free CU NIPDAU N / A for Pkg Type -55 to 125 CD74AC245E (RoHS) CD74AC245EE4 ACTIVE PDIP N 20 20 Pb-Free CU NIPDAU N / A for Pkg Type -55 to 125 CD74AC245E (RoHS) CD74AC245M ACTIVE SOIC DW 20 25 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 AC245M & no Sb/Br) CD74AC245M96 ACTIVE SOIC DW 20 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 AC245M & no Sb/Br) CD74ACT245E ACTIVE PDIP N 20 20 Pb-Free CU NIPDAU N / A for Pkg Type -55 to 125 CD74ACT245E (RoHS) CD74ACT245EE4 ACTIVE PDIP N 20 20 Pb-Free CU NIPDAU N / A for Pkg Type -55 to 125 CD74ACT245E (RoHS) CD74ACT245M ACTIVE SOIC DW 20 25 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 ACT245M & no Sb/Br) CD74ACT245M96 ACTIVE SOIC DW 20 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 ACT245M & no Sb/Br) CD74ACT245M96G4 ACTIVE SOIC DW 20 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 ACT245M & no Sb/Br) CD74ACT245MG4 ACTIVE SOIC DW 20 25 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 ACT245M & no Sb/Br) CD74ACT245SM96 ACTIVE SSOP DB 20 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -55 to 125 ACT245SM & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF CD54AC245, CD54ACT245, CD74AC245, CD74ACT245 : •Catalog: CD74AC245, CD74ACT245 •Military: CD54AC245, CD54ACT245 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 17-Aug-2012 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) CD74AC245M96 SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 CD74ACT245M96 SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 CD74ACT245SM96 SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 17-Aug-2012 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) CD74AC245M96 SOIC DW 20 2000 367.0 367.0 45.0 CD74ACT245M96 SOIC DW 20 2000 367.0 367.0 45.0 CD74ACT245SM96 SSOP DB 20 2000 367.0 367.0 38.0 PackMaterials-Page2

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PACKAGE OUTLINE DB0020A TSSOP - 2 mm max height SCALE 2.000 SMALL OUTLINE PACKAGE C 8.2 TYP 7.4 A 0.1 C PIN 1 INDEX AREA SEATING PLANE 18X 0.65 20 1 2X 7.5 5.85 6.9 NOTE 3 10 11 0.38 20X 0.22 5.6 B 0.1 C A B 5.0 NOTE 4 2 MAX (0.15) TYP 0.25 SEE DETAIL A GAGE PLANE 0 -8 0.95 0.05 MIN 0.55 DETA 15AIL A TYPICAL 4214851/A 12/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-150. www.ti.com

EXAMPLE BOARD LAYOUT DB0020A TSSOP - 2 mm max height SMALL OUTLINE PACKAGE 20X (1.85) SYMM (R0.05) TYP 1 20X (0.45) 20 SYMM 18X (0.65) 10 11 (7) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL METAL UNDER SOLDER MASK OPENING SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000 R MASK DETAILS 4214851/A 12/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DB0020A TSSOP - 2 mm max height SMALL OUTLINE PACKAGE 20X (1.85) SYMM (R0.05) TYP 1 20X (0.45) 20 SYMM 18X (0.65) 10 11 (7) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4214851/A 12/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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PACKAGE OUTLINE DW0020A SOIC - 2.65 mm max height SCALE 1.200 SOIC C 10.63 SEATING PLANE TYP 9.97 A PIN 1 ID 0.1 C AREA 18X 1.27 20 1 13.0 2X 12.6 11.43 NOTE 3 10 11 0.51 20X 7.6 0.31 2.65 MAX B 7.4 0.25 C A B NOTE 4 0.33 TYP 0.10 0.25 SEE DETAIL A GAGE PLANE 0.3 1.27 0 - 8 0.1 0.40 DETAIL A TYPICAL 4220724/A 05/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side. 5. Reference JEDEC registration MS-013. www.ti.com

EXAMPLE BOARD LAYOUT DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM (R0.05) TYP 10 11 (9.3) LAND PATTERN EXAMPLE SCALE:6X SOOPLEDNEINRG MASK METAL MSOELTDAEL RU NMDAESRK SOOPLEDNEINRG MASK 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220724/A 05/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DW0020A SOIC - 2.65 mm max height SOIC 20X (2) SYMM 1 20 20X (0.6) 18X (1.27) SYMM 10 11 (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4220724/A 05/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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