CD4070B, CD4077B Data sheet acquired from Harris Semiconductor SCHS055E CMOS Quad Exclusive-OR and Exclusive-NOR Gate January 1998 - Revised September 2003 Features Ordering Information • High-Voltage Types (20V Rating) TEMP.RANGE [ /Title • CD4070B - Quad Exclusive-OR Gate PART NUMBER (oC) PACKAGE (CD40 • CD4077B - Quad Exclusive-NOR Gate CD4070BE -55 to 125 14 Ld PDIP 70B, • Medium Speed Operation CD4070BF3A -55 to 125 14 Ld CERDIP CD407 - tPHL, tPLH = 65ns (Typ) at VDD = 10V, CL = 50pF 7B) • 100% Tested for Quiescent Current at 20V CD4070BM -55 to 125 14 Ld SOIC /Sub- • Standardized Symmetrical Output Characteristics CD4070BMT -55 to 125 14 Ld SOIC ject • 5V, 10V and 15V Parametric Ratings CD4070BM96 -55 to 125 14 Ld SOIC (CMO • Maximum Input Current of 1µA at 18V Over Full SQuad Package Temperature Range CD4070BNSR -55 to 125 14 Ld SOP Exclu- - 100nA at 18V and 25oC CD4070BPW -55 to 125 14 Ld TSSOP sive- • Noise Margin (Over Full Package Temperature Range) CD4070BPWR -55 to 125 14 Ld TSSOP OR - 1V at VDD = 5V, 2V at VDD = 10V, 2.5V at VDD = 15V and CD4077BE -55 to 125 14 Ld PDIP • Meets All Requirements of JEDEC Standard No. 13B, Exclu- “Standard Specifications for Description of ‘B’ Series CD4077BF3A -55 to 125 14 Ld CERDIP sive- CMOS Devices CD4077BM -55 to 125 14 Ld SOIC NOR Applications Gate) CD4077BMT -55 to 125 14 Ld SOIC /Autho • Logical Comparators CD4077BM96 -55 to 125 14 Ld SOIC r () • Adders/Subtractors /Key- CD4077BNSR -55 to 125 14 Ld SOP • Parity Generators and Checkers words CD4077BPW -55 to 125 14 Ld TSSOP (Har- Description CD4077BPWR -55 to 125 14 Ld TSSOP ris The Harris CD4070B contains four independent Exclusive- NOTE: Whenordering,usetheentirepartnumber.Thesuffixes96 Semi- OR gates. The Harris CD4077B contains four independent andRdenotetapeandreel.ThesuffixTdenotesasmall-quantity con- Exclusive-NOR gates. reel of 250. ductor, The CD4070B and CD4077B provide the system designer CD400 with a means for direct implementation of the Exclusive-OR 0, and Exclusive-NOR functions, respectively. metal gate, CMOS , pdip, cerdip, mil, CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2003, Texas Instruments Incorporated 1

CD4070B, CD4077B Pinouts CD4070B CD4077B (PDIP, CERDIP, SOIC, SOP, TSSOP) (PDIP, CERDIP, SOIC, SOP, TSSOP) TOP VIEW TOP VIEW A 1 14 VDD A 1 14 VDD B 2 13 H B 2 13 H J = A⊕ B 3 12 G J = A⊕ B 3 12 G K = C⊕ D 4 11 M = G⊕ H K = C⊕ D 4 11 M = G⊕ H C 5 10 L = E⊕ F C 5 10 L = E⊕ F D 6 9 F D 6 9 F VSS 7 8 E VSS 7 8 E Functional Diagrams CD4070B CD4077B A 1 3 A 1 3 J = A⊕ B B 2 J B 2 J ⊕ K =C⊕ D C 56 4 K JK ==CA ⊕ DB C 56 4 K M = G⊕H D D L = E⊕ F E 8 10 M =G ⊕ H E 8 10 9 L ⊕ 9 L VSS = 7 F L =E F F VDD= 14 GH 1123 11M GH 1123 11 M 2

CD4070B, CD4077B VDD VDD VDD p VDD B† p B† p p 2(5,9,12) n n 2(5,9,12) n n n VSS p VSS p p VDD p J VDD pn 3(4J,10,11) A† p n 3(4,10,11) A† p n n 1(6,8,13) n 1(6,8,13) n VSS VDD VSS VSS VDD VSS † INPUTS PROTECTED † INPUTS PROTECTED BY CMOS PROTECTION BY CMOS PROTECTION NETWORK NETWORK VSS VSS FIGURE 1. SCHEMATIC DIAGRAM FOR CD4070B FIGURE 2. SCHEMATIC DIAGRAM FOR CD4077B (1 OF 4 IDENTICAL GATES) (1 OF 4 IDENTICAL GATES) CD4070B TRUTH TABLE (1 OF 4 GATES) CD4077B TRUTH TABLE (1 OF 4 GATES) A B J A B J 0 0 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 0 1 1 1 NOTE: NOTE: 1 = High Level 1 = High Level 0 = Low Level 0 = Low Level J = A⊕B J = A⊕B 3

CD4070B, CD4077B Absolute Maximum Ratings Thermal Information DC Supply Voltage Range (VDD). . . . . . . . . . . . . . . . . -0.5V to 20V Package Thermal Impedance,θJA(see Note 1): Input Voltage Range, All Inputs . . . . . . . . . . . . . .-0.5V to VDD 0.5V E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80oC/W DC Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±10mA M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86oC/W NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76oC/W Operating Conditions PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 113oC/W Maximum Junction Temperature (Hermetic Package or Die) .175oC Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . .-55oC to 125oC Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC Supply Voltage Range (Typical) . . . . . . . . . . . . . . . . . . . . 3V to 18V Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC CAUTION:Stressesabovethoselistedin“AbsoluteMaximumRatings”maycausepermanentdamagetothedevice.Thisisastressonlyratingandoperation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7. DC Electrical Specifications LIMITS AT INDICATED TEMPERATURES (oC) CONDITIONS 25 VO VIN VDD PARAMETER (V) (V) (V) -55 -40 85 125 MIN TYP MAX UNITS Quiescent Device Current - 0, 5 5 0.25 0.25 7.5 7.5 - 0.01 0.25 µA IDD Max - 0, 10 10 0.5 0.5 15 15 - 0.01 0.5 µA - 0, 15 15 1 1 30 30 - 0.01 1 µA - 0, 20 20 5 5 150 150 - 0.02 5 µA Output Low (Sink) Current 0.4 0, 5 5 0.64 0.61 0.42 0.36 0.51 1 - mA IOL Min 0.5 0, 10 10 1.6 1.5 1.1 0.9 1.3 2.6 - mA 1.5 0, 15 15 4.2 4 2.8 2.4 3.4 6.8 - mA Output High (Source) Current 4.6 0, 5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - mA IOH Min 2.5 0, 5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 - mA 9.5 0, 10 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 - mA 13.5 0, 15 15 -4.2 -4 -2.8 -2.4 -3.4 -6.8 - mA Output Voltage: Low Level, - 0, 5 5 0.05 0.05 0.05 0.05 - 0 0.05 V VOL Max - 0, 10 10 0.05 0.05 0.05 0.05 - 0 0.05 V - 0, 15 15 0.05 0.05 0.05 0.05 - 0 0.05 V Output Voltage: High Level, - 0, 5 5 4.95 4.95 4.95 4.95 4.95 5 - V VOH Min - 0, 10 10 9.95 9.95 9.95 9.95 9.95 10 - V - 0, 15 15 14.95 14.95 14.95 14.95 14.95 15 - V Input Low Voltage, 0.5, 4.5 - 5 1.5 1.5 1.5 1.5 - - 1.5 V VIL Max 1, 9 - 10 3 3 3 3 - - 3 V 1.5,13.5 - 15 4 4 4 4 - - 4 V Input High Voltage, 0.5, 4.5 - 5 3.5 3.5 3.5 3.5 3.5 - - V VIH Min 1, 9 - 10 7 7 7 7 7 - - V 1.5,13.5 - 15 11 11 11 11 11 - - V Input Current, IIN Max - 0, 18 18 ±0.1 ±0.1 ±1 ±1 - ±10-5 ±0.1 µA 4

CD4070B, CD4077B AC Electrical Specifications TA = 25oC, Input tr, tf = 20ns, CL = 50pF, RL = 200kΩ TEST CONDITIONS LIMITS ON ALL TYPES PARAMETER SYMBOL VDD (V) TYP MAX UNITS Propagation Delay Time tPHL, tPLH 5 140 280 ns 10 65 130 ns 15 50 100 ns Transition Time tTHL, tTLH 5 100 200 ns 10 50 100 ns 15 40 80 ns Input Capacitance CIN Any Input 5 7.5 pF Typical Performance Curves A) TA = 25oC A) TA = 25oC m m T ( T ( N N RE 30 GATE TO SOURCE VOLTAGE (VGS) = 15V RE 15 R R U U GATE TO SOURCE VOLTAGE (VGS) = 15V C 25 C 12.5 K) K) N N SI 20 SI 10 W ( 10V W ( 10V O 15 O 7.5 L L T T U 10 U 5 P P UT 5V UT 5V O 5 O 2.5 , L , L O O I 0 I 0 0 5 10 15 0 5 10 15 VDS, DRAIN TO SOURCE VOLTAGE (V) VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT FIGURE 4. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS CHARACTERISTICS VDS, DRAIN TO SOURCE VOLTAGE (V) VDS, DRAIN TO SOURCE VOLTAGE (V) -15 -10 -5 0 A) -15 -10 -5 0 TA =G 2A5ToEC TO SOURCE VOLTAGE (VGS) = -5V ---051105 CE) CURRENT (m TA =G 2A5ToEC TO SOURCE VOLTAGE (VGS) = -5V -05 CURRENT (mA) -10V -20 SOUR -10V -10 SINK) -25 H ( H ( G G -15V -30 T HI T HI U -15V -15 U P P T T U U O O , H , H O O I I FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS CHARACTERISTICS 5

Typical Performance Curves (Continued) s) TA = 25oC E (ns) TA = 25oC n M E ( TI N TIM 200 ELAY 300 O D TI SUPPLY VOLTAGE (VDD) = 5V N ANSI 150 ATIO 200 SUPPLY VOLTAGE (VDD) = 5V R G T A , H 100 10V OP , tHLTL 50 15V , PRLH 100 10V T P t , tL 15V 0 PH 0 0 20 40 60 80 100 110 t 0 20 40 60 80 100 CL, LOAD CAPACITANCE (pF) CL, LOAD CAPACITANCE (pF) FIGURE 7. TYPICAL TRANSITION TIME AS A FUNCTION OF FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A LOAD CAPACITANCE FUNCTION OF LOAD CAPACITANCE E (ns) TA = 25oC 105 TA = 25oC AGATION DELAY TIM 320000 LOAD CAPACITANCE CL = 50pF µR DISSIPATION (W) 111000324 S U P P LY V O L T A G E (V D D) = C11L50 V=V 15pF CL =1 500VpF P E O W 10 5V , PRPLH 100 P, POD 1 , tL PH 0 10-1 t 0 5 10 15 20 10-1 1 10 102 103 104 VDD, SUPPLY VOLTAGE (V) fI, INPUT FREQUENCY (kHz) FIGURE9. TYPICALPROPAGATIONDELAYTIMEASA FIGURE 10. TYPICAL DYNAMIC POWER DISSIPATION AS A FUNCTION OF SUPPLY VOLTAGE FUNCTION OF INPUT FREQUENCY 6

PACKAGE OPTION ADDENDUM www.ti.com 15-Oct-2009 PACKAGING INFORMATION OrderableDevice Status(1) Package Package Pins Package EcoPlan(2) Lead/BallFinish MSLPeakTemp(3) Type Drawing Qty CD4070BE ACTIVE PDIP N 14 25 Pb-Free CUNIPDAU N/AforPkgType (RoHS) CD4070BEE4 ACTIVE PDIP N 14 25 Pb-Free CUNIPDAU N/AforPkgType (RoHS) CD4070BF ACTIVE CDIP J 14 1 TBD A42 N/AforPkgType CD4070BF3A ACTIVE CDIP J 14 1 TBD A42 N/AforPkgType CD4070BF3AS2534 OBSOLETE CDIP J 14 TBD CallTI CallTI CD4070BM ACTIVE SOIC D 14 50 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) CD4070BM96 ACTIVE SOIC D 14 2500 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) CD4070BM96E4 ACTIVE SOIC D 14 2500 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) CD4070BM96G4 ACTIVE SOIC D 14 2500 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) CD4070BME4 ACTIVE SOIC D 14 50 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) CD4070BMG4 ACTIVE SOIC D 14 50 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) CD4070BMT ACTIVE SOIC D 14 250 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) CD4070BMTE4 ACTIVE SOIC D 14 250 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) CD4070BMTG4 ACTIVE SOIC D 14 250 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) CD4070BNSR ACTIVE SO NS 14 2000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) CD4070BNSRE4 ACTIVE SO NS 14 2000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) CD4070BNSRG4 ACTIVE SO NS 14 2000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) CD4070BPW ACTIVE TSSOP PW 14 90 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) CD4070BPWE4 ACTIVE TSSOP PW 14 90 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) CD4070BPWG4 ACTIVE TSSOP PW 14 90 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) CD4070BPWR ACTIVE TSSOP PW 14 2000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) CD4070BPWRE4 ACTIVE TSSOP PW 14 2000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) CD4070BPWRG4 ACTIVE TSSOP PW 14 2000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) CD4077BE ACTIVE PDIP N 14 25 Pb-Free CUNIPDAU N/AforPkgType (RoHS) CD4077BEE4 ACTIVE PDIP N 14 25 Pb-Free CUNIPDAU N/AforPkgType (RoHS) CD4077BF ACTIVE CDIP J 14 1 TBD A42 N/AforPkgType CD4077BF3A ACTIVE CDIP J 14 1 TBD A42 N/AforPkgType Addendum-Page1

PACKAGE OPTION ADDENDUM www.ti.com 15-Oct-2009 OrderableDevice Status(1) Package Package Pins Package EcoPlan(2) Lead/BallFinish MSLPeakTemp(3) Type Drawing Qty CD4077BM ACTIVE SOIC D 14 50 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) CD4077BM96 ACTIVE SOIC D 14 2500 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) CD4077BM96E4 ACTIVE SOIC D 14 2500 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) CD4077BM96G4 ACTIVE SOIC D 14 2500 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) CD4077BME4 ACTIVE SOIC D 14 50 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) CD4077BMG4 ACTIVE SOIC D 14 50 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) CD4077BMT ACTIVE SOIC D 14 250 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) CD4077BMTE4 ACTIVE SOIC D 14 250 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) CD4077BMTG4 ACTIVE SOIC D 14 250 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) CD4077BNSR ACTIVE SO NS 14 2000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) CD4077BNSRE4 ACTIVE SO NS 14 2000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) CD4077BNSRG4 ACTIVE SO NS 14 2000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) CD4077BPW ACTIVE TSSOP PW 14 90 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) CD4077BPWE4 ACTIVE TSSOP PW 14 90 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) CD4077BPWG4 ACTIVE TSSOP PW 14 90 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) CD4077BPWR ACTIVE TSSOP PW 14 2000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) CD4077BPWRE4 ACTIVE TSSOP PW 14 2000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) CD4077BPWRG4 ACTIVE TSSOP PW 14 2000 Green(RoHS& CUNIPDAU Level-1-260C-UNLIM noSb/Br) JM38510/17203BCA ACTIVE CDIP J 14 1 TBD A42 N/AforPkgType (1)Themarketingstatusvaluesaredefinedasfollows: ACTIVE:Productdevicerecommendedfornewdesigns. LIFEBUY:TIhasannouncedthatthedevicewillbediscontinued,andalifetime-buyperiodisineffect. NRND:Notrecommendedfornewdesigns.Deviceisinproductiontosupportexistingcustomers,butTIdoesnotrecommendusingthispartin anewdesign. PREVIEW:Devicehasbeenannouncedbutisnotinproduction.Samplesmayormaynotbeavailable. OBSOLETE:TIhasdiscontinuedtheproductionofthedevice. (2)EcoPlan-Theplannedeco-friendlyclassification:Pb-Free(RoHS),Pb-Free(RoHSExempt),orGreen(RoHS&noSb/Br)-pleasecheck http://www.ti.com/productcontentforthelatestavailabilityinformationandadditionalproductcontentdetails. TBD:ThePb-Free/Greenconversionplanhasnotbeendefined. Pb-Free(RoHS):TI'sterms"Lead-Free"or"Pb-Free"meansemiconductorproductsthatarecompatiblewiththecurrentRoHSrequirements forall6substances,includingtherequirementthatleadnotexceed0.1%byweightinhomogeneousmaterials.Wheredesignedtobesoldered athightemperatures,TIPb-Freeproductsaresuitableforuseinspecifiedlead-freeprocesses. Pb-Free(RoHSExempt):ThiscomponenthasaRoHSexemptionforeither1)lead-basedflip-chipsolderbumpsusedbetweenthedieand package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS Addendum-Page2

PACKAGE OPTION ADDENDUM www.ti.com 15-Oct-2009 compatible)asdefinedabove. Green(RoHS&noSb/Br):TIdefines"Green"tomeanPb-Free(RoHScompatible),andfreeofBromine(Br)andAntimony(Sb)basedflame retardants(BrorSbdonotexceed0.1%byweightinhomogeneousmaterial) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incomingmaterialsandchemicals.TIandTIsuppliersconsidercertaininformationtobeproprietary,andthusCASnumbersandotherlimited informationmaynotbeavailableforrelease. InnoeventshallTI'sliabilityarisingoutofsuchinformationexceedthetotalpurchasepriceoftheTIpart(s)atissueinthisdocumentsoldbyTI toCustomeronanannualbasis. Addendum-Page3

PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0(mm) B0(mm) K0(mm) P1 W Pin1 Type Drawing Diameter Width (mm) (mm) Quadrant (mm) W1(mm) CD4070BM96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 CD4070BNSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 CD4070BPWR TSSOP PW 14 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1 CD4077BM96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 CD4077BNSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 CD4077BPWR TSSOP PW 14 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) CD4070BM96 SOIC D 14 2500 346.0 346.0 33.0 CD4070BNSR SO NS 14 2000 346.0 346.0 33.0 CD4070BPWR TSSOP PW 14 2000 346.0 346.0 29.0 CD4077BM96 SOIC D 14 2500 346.0 346.0 33.0 CD4077BNSR SO NS 14 2000 346.0 346.0 33.0 CD4077BPWR TSSOP PW 14 2000 346.0 346.0 29.0 PackMaterials-Page2

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MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,65 0,10 M 0,19 14 8 0,15 NOM 4,50 6,60 4,30 6,20 Gage Plane 0,25 1 7 0°–8° A 0,75 0,50 Seating Plane 0,15 1,20 MAX 0,10 0,05 PINS ** 8 14 16 20 24 28 DIM A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 4040064/F 01/97 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265

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PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) CD4070BE ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type -55 to 125 CD4070BE & no Sb/Br) CD4070BEE4 ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type -55 to 125 CD4070BE & no Sb/Br) CD4070BF ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type -55 to 125 CD4070BF CD4070BF3A ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type -55 to 125 CD4070BF3A CD4070BM ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CD4070BM & no Sb/Br) CD4070BM96 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CD4070BM & no Sb/Br) CD4070BM96E4 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CD4070BM & no Sb/Br) CD4070BMG4 ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CD4070BM & no Sb/Br) CD4070BMT ACTIVE SOIC D 14 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CD4070BM & no Sb/Br) CD4070BNSR ACTIVE SO NS 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CD4070B & no Sb/Br) CD4070BPW ACTIVE TSSOP PW 14 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CM070B & no Sb/Br) CD4070BPWR ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CM070B & no Sb/Br) CD4077BE ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type -55 to 125 CD4077BE & no Sb/Br) CD4077BF ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type -55 to 125 CD4077BF CD4077BF3A ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type -55 to 125 CD4077BF3A CD4077BM ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CD4077BM & no Sb/Br) CD4077BM96 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CD4077BM & no Sb/Br) CD4077BMT ACTIVE SOIC D 14 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CD4077BM & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) CD4077BNSR ACTIVE SO NS 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CD4077B & no Sb/Br) CD4077BPW ACTIVE TSSOP PW 14 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CM077B & no Sb/Br) JM38510/17203BCA ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/ 17203BCA M38510/17203BCA ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/ 17203BCA (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF CD4070B, CD4070B-MIL, CD4077B, CD4077B-MIL : •Catalog: CD4070B, CD4077B •Military: CD4070B-MIL, CD4077B-MIL NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 8-Nov-2018 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) CD4070BM96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 CD4070BMT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 CD4070BNSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 CD4070BPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 CD4077BM96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 CD4077BMT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 CD4077BNSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 8-Nov-2018 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) CD4070BM96 SOIC D 14 2500 367.0 367.0 38.0 CD4070BMT SOIC D 14 250 210.0 185.0 35.0 CD4070BNSR SO NS 14 2000 367.0 367.0 38.0 CD4070BPWR TSSOP PW 14 2000 367.0 367.0 35.0 CD4077BM96 SOIC D 14 2500 367.0 367.0 38.0 CD4077BMT SOIC D 14 250 210.0 185.0 35.0 CD4077BNSR SO NS 14 2000 367.0 367.0 38.0 PackMaterials-Page2

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PACKAGE OUTLINE J0014A CDIP - 5.08 mm max height SCALE 0.900 CERAMIC DUAL IN LINE PACKAGE PIN 1 ID A 4X .005 MIN (OPTIONAL) [0.13] .015-.060 TYP [0.38-1.52] 1 14 12X .100 [2.54] 14X .014-.026 14X .045-.065 [0.36-0.66] [1.15-1.65] .010 [0.25] C A B .754-.785 [19.15-19.94] 7 8 B .245-.283 .2 MAX TYP .13 MIN TYP [6.22-7.19] [5.08] [3.3] SEATING PLANE C .308-.314 [7.83-7.97] AT GAGE PLANE .015 GAGE PLANE [0.38] 0 -15 14X .008-.014 TYP [0.2-0.36] 4214771/A 05/2017 NOTES: 1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package is hermitically sealed with a ceramic lid using glass frit. 4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only. 5. Falls within MIL-STD-1835 and GDIP1-T14. www.ti.com

EXAMPLE BOARD LAYOUT J0014A CDIP - 5.08 mm max height CERAMIC DUAL IN LINE PACKAGE (.300 ) TYP [7.62] SEE DETAIL B SEE DETAIL A 1 14 12X (.100 ) [2.54] SYMM 14X ( .039) [1] 7 8 SYMM LAND PATTERN EXAMPLE NON-SOLDER MASK DEFINED SCALE: 5X .002 MAX (.063) [0.05] [1.6] METAL ALL AROUND ( .063) SOLDER MASK [1.6] OPENING METAL .002 MAX SOLDER MASK (R.002 ) TYP [0.05] OPENING [0.05] ALL AROUND DETAIL A DETAIL B SCALE: 15X 13X, SCALE: 15X 4214771/A 05/2017 www.ti.com

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