CD4049UB, CD4050B www.ti.com SCHS046K – AUGUST 1C99D84 –0 R4E9VUISBE,D C JDUN4E0 52002B0 SCHS046K – AUGUST 1998 – REVISED JUNE 2020 CD4049UB and CD4050B CMOS Hex Inverting Buffer and Converter 1 Features 3 Description • CD4049UB Inverting The CD4049UB and CD4050B devices are inverting • CD4050B Noninverting and noninverting hex buffers, and feature logic-level • High Sink Current for Driving 2 TTL Loads conversion using only one supply voltage (VCC). The input-signal high level (V ) can exceed the V • High-to-Low Level Logic Conversion IH CC supply voltage when these devices are used for logic- • 100% Tested for Quiescent Current at 20 V level conversions. These devices are intended for use • Maximum Input Current of 1 µA at 18 V Over Full as CMOS to DTL or TTL converters and can drive Package Temperature Range; 100 nA at 18 V and directly two DTL or TTL loads. (V = 5 V, CC 25°C V ≤ 0.4 V, and I ≥ 3.3 mA.) OL OL • 5-V, 10-V, and 15-V Parametric Ratings Device Information 2 Applications PART NUMBER(1) PACKAGE BODY SIZE (NOM) • CMOS to DTL or TTL Hex Converters CD4049UBE, • CMOS Current Sink or Source Drivers CD4050BE PDIP (16) 6.35 mm × 19.30 mm • CMOS High-to-Low Logic Level Converters CD4049UBD, SOIC (16) 9.90 mm × 3.91 mm CD4050BD CD4049UBDW, SOIC (16) 10.30 mm × 7.50 mm CD4050BDW CD4049UBNS, SO (16) 10.30 mm × 5.30 mm CD4050BNS CD4049UBPW, TSSOP (16) 5.00 mm × 4.40 mm CD4050BPW (1) For all available packages, see the orderable addendum at the end of the data sheet. VCC VCC P P P R OUT R IN IN OUT N N N VSS VSS Copyright © 2016, Texas Instruments Incorporated Copyright © 2016,Texas Instruments Incorporated 1 of 6 Identical Units 1 of 6 Identical Units Schematic Diagram of CD4049UB Schematic Diagram of CD4050B An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, Copyrighint t©e l2le0c2t0u Tael xparso Ipnesrtrtuym meanttste Irnsc oarnpdor aottehder important disclaimers. PRODUCTION DATA. Submit Document Feedback 1 Product Folder Links: CD4049UB CD4050B

CD4049UB, CD4050B SCHS046K – AUGUST 1998 – REVISED JUNE 2020 www.ti.com Table of Contents 1 Features............................................................................1 8.4 Device Functional Modes..........................................14 2 Applications.....................................................................1 9 Application and Implementation..................................15 3 Description.......................................................................1 9.1 Application Information.............................................15 4 Revision History..............................................................2 9.2 Typical Application....................................................15 5 Pin Configuration and Functions...................................3 10 Power Supply Recommendations..............................16 6 Specifications..................................................................4 11 Layout...........................................................................16 6.1 Absolute Maximum Ratings........................................4 11.1 Layout Guidelines...................................................16 6.2 ESD Ratings...............................................................4 11.2 Layout Example......................................................16 6.3 Recommended Operating Conditions.........................4 12 Device and Documentation Support..........................17 6.4 Thermal Information....................................................5 12.1 Documentation Support..........................................17 6.5 Electrical Characteristics: DC.....................................5 12.2 Related Links..........................................................17 6.6 Electrical Characteristics: AC......................................9 12.3 Receiving Notification of Documentation Updates..17 6.7 Typical Characteristics..............................................10 12.4 Support Resources.................................................17 7 Parameter Measurement Information..........................11 12.5 Trademarks.............................................................17 7.1 Test Circuits...............................................................11 12.6 Electrostatic Discharge Caution..............................17 8 Detailed Description......................................................13 12.7 Glossary..................................................................17 8.1 Overview...................................................................13 13 Mechanical, Packaging, and Orderable 8.2 Functional Block Diagram.........................................13 Information....................................................................17 8.3 Feature Description...................................................13 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision J (September 2016) to Revision K (June 2020) Page • Updated the numbering format for tables, figures, and cross-references throughout the document..................1 • Updated Device Information Table with correct package dimensions................................................................1 Changes from Revision I (May 2004) to Revision J (September 2016) Page • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section...................1 • Deleted Ordering Information table; see POA at the end of the data sheet.......................................................1 • Changed Storage temperature minimum value from 65 to –65..........................................................................4 • Changed R values for the CD4049UB device: D (SOIC) from 73 to 81.6, DW (SOIC) from 57 to 81.6, E θJA (PDIP) from 67 to 49.5, NS (SO) from 64 to 84.3, and PW (TSSOP) from 108 to 108.9...................................5 • Changed R values for the CD4050B device: D (SOIC) from 73 to 81.6, DW (SOIC) from 57 to 81.2, E θJA (PDIP) from 67 to 49.7, NS (SO) from 64 to 83.8, and PW (TSSOP) from 108 to 108.4...................................5 2 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: CD4049UB CD4050B

CD4049UB, CD4050B www.ti.com SCHS046K – AUGUST 1998 – REVISED JUNE 2020 5 Pin Configuration and Functions VCC 1 16 NC VCC 1 16 NC G 2 15 L G 2 15 L A 3 14 F A 3 14 F H 4 13 NC H 4 13 NC B 5 12 K B 5 12 K I 6 11 E I 6 11 E C 7 10 J C 7 10 J VSS 8 9 D VSS 8 9 D Not to scale Not to scale Figure 5-1. CD4049UB D, DW, N, NS, and PW Figure 5-2. CD4050B D, DW, N, NS, and PW Packages 16-Pin SOIC, PDIP, SO, and TSSOP Top Packages 1G6-Pin SOIC, PDIP, SO, and TSSOP Top View View Pin Functions: CD4049UB PIN I/O DESCRIPTION NAME NO. A 3 I Input 1 B 5 I Input 2 C 7 I Input 3 D 9 I Input 4 E 11 I Input 5 F 14 I Input 6 G 2 O Inverting output 1. G = A H 4 O Inverting output 2. H = B I 6 O Inverting output 3. I = C J 10 O Inverting output 4. J = D K 12 O Inverting output 5. K = E L 15 O Inverting output 6. L = F NC 13, 16 — No connection VCC 1 — Power pin VSS 8 — Negative supply Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: CD4049UB CD4050B

CD4049UB, CD4050B SCHS046K – AUGUST 1998 – REVISED JUNE 2020 www.ti.com Pin Functions: CD4050B PIN I/O DESCRIPTION NAME NO. A 3 I Input 1 B 5 I Input 2 C 7 I Input 3 D 9 I Input 4 E 11 I Input 5 F 14 I Input 6 G 2 O Inverting output 1. G = A H 4 O Inverting output 2. H = B I 6 O Inverting output 3. I = C J 10 O Inverting output 4. J = D K 12 O Inverting output 5. K = E L 15 O Inverting output 6. L = F NC 13, 16 — No connection VCC 1 — Power pin VSS 8 — Negative supply 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT Supply voltage VCC to VSS –0.5 20 V DC input current, I Any one input ±10 mA IK Lead temperature (soldering, 10 s) SOIC, lead tips only 265 °C Junction temperature, T 150 °C J Storage temperature, T –65 150 °C stg (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Section 6.3. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings VALUE UNIT Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1500 V Electrostatic discharge V (ESD) Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT V Supply voltage 3 18 V CC T Operating temperature –55 125 °C A 4 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: CD4049UB CD4050B

CD4049UB, CD4050B www.ti.com SCHS046K – AUGUST 1998 – REVISED JUNE 2020 6.4 Thermal Information CD4049UB CD4050B D DW E NS PW D DW E NS PW THERMAL METRIC(1) UNIT (SOIC) (SOIC) (PDIP) (SO) (TSSOP) (SOIC) (SOIC) (PDIP) (SO) (TSSOP) 16 PINS 16 PINS 16 PINS 16 PINS 16 PINS 16 PINS 16 PINS 16 PINS 16 PINS 16 PINS Junction-to-ambient RθJA thermal resistance(2) 81.6 81.6 49.5 84.3 108.9 81.6 81.2 49.7 83.8 108.4 °C/W Junction-to-case (top) RθJC(top) thermal resistance 41.5 44.5 36.8 43 43.7 41.5 44.1 37 42.5 43.2 °C/W Junction-to-board RθJB thermal resistance 39 46.3 29.4 44.6 54 39 45.9 29.6 44.1 53.5 °C/W Junction-to-top ψJT characterization 10.7 16.5 21.7 12.8 4.6 10.7 16.1 21.9 12.5 4.5 °C/W parameter Junction-to-board ψJB characterization 38.7 45.8 29.3 44.3 53.4 38.7 45.4 29.5 43.8 52.9 °C/W parameter (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. (2) The package thermal impedance is calculated in accordance with JESD 51-7. 6.5 Electrical Characteristics: DC PARAMETER TEST CONDITIONS MIN TYP MAX UNIT T = –55 °C 1 A T = –40 °C 1 A V = 0 or 5 V, V = 5 V T = 25 °C 0.02 1 IN CC A T = 85 °C 30 A T = 125 °C 30 A T = –55 °C 2 A T = –40 °C 2 A V = 0 or 10 V, V = 10 V T = 25 °C 0.02 2 IN CC A T = 85 °C 60 A T = 125 °C 60 A I (Max) Quiescent device current µA DD T = –55 °C 4 A T = –40 °C 4 A V = 0 or 15 V, V = 4 V T = 25 °C 0.02 4 IN CC A T = 85 °C 120 A T = 125 °C 120 A T = –55 °C 20 A T = –40 °C 20 A V = 0 or 20 V, V = 20 V T = 25 °C 0.04 20 IN CC A T = 85 °C 600 A T = 125 °C 600 A Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: CD4049UB CD4050B

CD4049UB, CD4050B SCHS046K – AUGUST 1998 – REVISED JUNE 2020 www.ti.com PARAMETER TEST CONDITIONS MIN TYP MAX UNIT T = –55 °C 3.3 A T = –40 °C 3.1 A V = 0.4 V, V = 0 or 5 V, V = 4.5 V T = 25 °C 2.6 5.2 OUT IN CC A T = 85 °C 2.1 A T = 125 °C 1.8 A T = –55 °C 4 A T = –40 °C 3.8 A V = 0.4 V, V = 0 or 5 V, V = 5 V T = 25 °C 3.2 6.4 OUT IN CC A T = 85 °C 2.9 A T = 125 °C 2.4 A I (Min) Output low (sink) current mA OL T = –55 °C 10 A T = –40 °C 9.6 A V = 0.5 V, V = 0 or 10 V, V = 10 V T = 25 °C 8 16 OUT IN CC A T = 85 °C 6.6 A T = 125 °C 5.6 A T = –55 °C 26 A T = –40 °C 25 A V = 1.5 V, V = 0 or 15 V, V = 15 V T = 25 °C 24 48 OUT IN CC A T = 85 °C 20 A T = 125 °C 18 A T = –55 °C –0.81 A T = –40 °C –0.73 A V = 4.6 V, V = 0 or 5 V, V = 5 V T = 25 °C –0.65 –1.2 OUT IN CC A T = 85 °C –0.58 A T = 125 °C –0.48 A T = –55 °C –2.6 A T = –40 °C –2.4 A V = 2.5 V, V = 0 or 5 V, V = 5 V T = 25 °C –2.1 –3.9 OUT IN CC A T = 85 °C –1.9 A Output high (source) TA = 125 °C –1.55 I (Min) mA OH current T = –55 °C –2 A T = –40 °C –1.8 A V = 9.5 V, V = 0 or 10 V, V = 10 V T = 25 °C –1.65 –3 OUT IN CC A T = 85 °C –1.35 A T = 125 °C –1.18 A T = –55 °C –5.2 A T = –40 °C –4.8 A V = 1.3 V, V = 0 or 15 V, V = 15 V T = 25 °C –4.3 –8 OUT IN CC A T = 85 °C –3.5 A T = 125 °C –3.1 A 6 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: CD4049UB CD4050B

CD4049UB, CD4050B www.ti.com SCHS046K – AUGUST 1998 – REVISED JUNE 2020 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT T = –55 °C 0.05 A T = –40 °C 0.05 A V = 0 or 5 V, V = 5 V T = 25 °C 0 0.05 IN CC A T = 85 °C 0.05 A T = 125 °C 0.05 A T = –55 °C 0.05 A T = –40 °C 0.05 A V (Max) Out voltage low level V = 0 or 10 V, V = 10 V T = 25 °C 0 0.05 V OL IN CC A T = 85 °C 0.05 A T = 125 °C 0.05 A T = –55 °C 0.05 A T = –40 °C 0.05 A V = 0 or 15 V, V = 15 V T = 25 °C 0 0.05 IN CC A T = 85 °C 0.05 A T = 125 °C 0.05 A T = –55 °C 4.95 A T = –40 °C 4.95 A V = 0 or 5 V, V = 5 V T = 25 °C 4.95 5 IN CC A T = 85 °C 4.95 A T = 125 °C 4.95 A T = –55 °C 9.95 A T = –40 °C 9.95 A V (Min) Output voltage high level V = 0 or 10 V, V = 10 V T = 25 °C 9.95 10 V OH IN CC A T = 85 °C 9.95 A T = 125 °C 9.95 A T = –55 °C 14.95 A T = –40 °C 14.95 A V = 0 or 15 V, V = 15 V T = 25 °C 14.95 15 IN CC A T = 85 °C 14.95 A T = 125 °C 14.95 A V = 4.5 V, V = 5 V, Full temperature range 1 OUT CC Input low voltage V = 9 V, V = 10 V, Full temperature range 2 (CD4049UB) OUT CC V = 13.5 V, V = 15 V, Full temperature range 2.5 OUT CC V (Max) V IL V = 0.5 V, V = 5 V, Full temperature range 1.5 OUT CC Input low voltage V = 1 V, V = 10 V, Full temperature range 3 (CD4050B) OUT CC V = 1.5 V, V = 15 V, Full temperature range 4 OUT CC Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: CD4049UB CD4050B

CD4049UB, CD4050B SCHS046K – AUGUST 1998 – REVISED JUNE 2020 www.ti.com PARAMETER TEST CONDITIONS MIN TYP MAX UNIT T = –55 °C 4 A T = –40 °C 4 A V = 0.5 V, V = 5 V T = 25 °C 4 OUT CC A T = 85 °C 4 A T = 125 °C 4 A T = –55 °C 8 A T = –40 °C 8 A Input high voltage V (Min) V = 1 V, V = 10 V T = 25 °C 8 V IH (CD4049UB) OUT CC A T = 85 °C 8 A T = 125 °C 8 A T = –55 °C 12.5 A T = –40 °C 12.5 A V = 1.5 V, V = 15 V T = 25 °C 12.5 OUT CC A T = 85 °C 12.5 A T = 125 °C 12.5 A T = –55 °C 3.5 A T = –40 °C 3.5 A V = 4.5 V, V = 5 V T = 25 °C 3.5 OUT CC A T = 85 °C 3.5 A T = 125 °C 3.5 A T = –55 °C 7 A T = –40 °C 7 A Input high voltage V V = 9 V, V = 10 V T = 25 °C 7 V IH (CD4050B) OUT CC A T = 85 °C 7 A T = 125 °C 7 A T = –55 °C 11 A T = –40 °C 11 A V = 13.5 V, V = 15 V T = 25 °C 11 OUT CC A T = 85 °C 11 A T = 125 °C 11 A T = –55 °C ±0.1 A T = –40 °C ±0.1 A I (Max) Input current V = 0 or 18 V, V = 18 V T = 25 °C ±10–5 ±0.1 µA IN IN CC A T = 85 °C ±1 A T = 125 °C ±1 A 8 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: CD4049UB CD4050B

CD4049UB, CD4050B www.ti.com SCHS046K – AUGUST 1998 – REVISED JUNE 2020 6.6 Electrical Characteristics: AC T = 25°C, Input t and t = 20 ns, C = 50 pF, R = 200 kΩ (unless otherwise noted) A r f L L PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V = 5 V, V = 5 V 60 120 IN CC V = 10 V, V = 10 V 32 65 IN CC Propagation delay time V = 10 V, V = 5 V 45 90 ns Low to high (CD4049UB) IN CC V = 15 V, V = 15 V 25 50 IN CC V = 15 V, V = 5 V 45 90 IN CC t PLH V = 5 V, V = 5 V 70 140 IN CC V = 10 V, V = 10 V 40 80 IN CC Propagation delay time V = 10 V, V = 5 V 45 90 ns Low to high (CD4050B) IN CC V = 15 V, V = 15 V 30 60 IN CC V = 15 V, V = 5 V 40 80 IN CC V = 5 V, V = 5 V 32 65 IN CC V = 10 V, V = 10 V 20 40 IN CC Propagation delay time V = 10 V, V = 5 V 15 30 ns High to low (CD4049UB) IN CC V = 15 V, V = 15 V 15 30 IN CC V = 15 V, V = 5 V 10 20 IN CC t PHL V = 5 V, V = 5 V 55 110 IN CC V = 10 V, V = 10 V 22 55 IN CC Propagation delay time V = 10 V, V = 5 V 50 100 ns High to low (CD4050B) IN CC V = 15 V, V = 15 V 15 30 IN CC V = 15 V, V = 5 V 50 100 IN CC V = 5 V, V = 5 V 80 160 IN CC Transition time t V = 10 V, V = 10 V 40 80 ns TLH Low to high IN CC V = 15 V, V = 15 V 30 60 IN CC V = 5 V, V = 5 V 30 60 IN CC Transition time t V = 10 V, V = 10 V 20 40 ns THL High to low IN CC V = 15 V, V = 15 V 15 30 IN CC Input capacitance (CD4049UB) 15 22.5 pF C IN Input capacitance (CD4050B) 5 7.5 pF Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: CD4049UB CD4050B

CD4049UB, CD4050B SCHS046K – AUGUST 1998 – REVISED JUNE 2020 www.ti.com 6.7 Typical Characteristics TA= 25oC TA= 25oC SUPPLYVOLTAGE (VCC) = 5V SUPPLYVOLTAGE (VCC) = 5V V) V) E ( 5 E ( 5 G G TA TA MINIMUM MAXIMUM L 4 L 4 O O V MINIMUM MAXIMUM V T T U 3 U 3 P P T T U U , OO 2 , OO 2 V V 1 1 0 1 2 3 4 0 1 2 3 4 VI, INPUT VOLTAGE (V) VI, INPUT VOLTAGE (V) Figure 6-1. Minimum and Maximum Voltage Figure 6-2. Minimum and Maximum Voltage Transfer Characteristics for CD4049UB Transfer Characteristics for CD4050B mA) TA= 25oC mA) TA= 25oC T ( 70 T ( 70 15V 10V N N RE 60 15V RE 60 R R U 10V U C 50 C 50 K) K) N N SI 40 SI 40 W ( W ( O 30 O 30 L L T GATE TO SOURCE VOLTAGE (VGS) = 5V T PU 20 PU 20 UT UT GATE TO SOURCE VOLTAGE (VGS) = 5V O 10 O 10 , OL , OL I I 0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8 VDS, DRAIN TO SOURCE VOLTAGE (V) VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 6-3. Typical Output Low (Sink) Current Figure 6-4. Minimum Output Low (Sink) Current Characteristics Drain Characteristics VDS, DRAIN TO SOURCE VOLTAGE (V) VDS, DRAIN TO SOURCE VOLTAGE (V) -8 -7 -6 -5 -4 -3 -2 -1 0 -8 -7 -6 -5 -4 -3 -2 -1 0 TA= 25oC TA= 25oC -5 -5 GVGAST-1E=0 T-V5OV SOURCE VOLTAGE -----1122305050 OUTPUT HIGH (SOURCE) RRENT CHARACTERISTICS GVGASTE= T-5O-1V- 15S0VOVURCE VOLTAGE -----1122305050 OUTPUT HIGH (SOURCE) RRENT CHARACTERISTICS U U C C -15V -35 -35 Figure 6-5. Typical Output High (Source) Current Figure 6-6. Minimum Output High (Source) Current Characteristics Characteristics 10 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: CD4049UB CD4050B

CD4049UB, CD4050B www.ti.com SCHS046K – AUGUST 1998 – REVISED JUNE 2020 10 10 V, OUTPUT VOLTAGE (V)O 98765432 1V25C1oC2C5=o 5CV -55oSVCUCTCPAP==L 1-Y505VVoOCLTAGE V, OUTPUT VOLTAGE (V)O 98765432 125oC 1V-2C55C5ooC=C 5V SVTCUACP=P= L -15Y05VVoOCLTAGE 1 1 0 0 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10 VI, INPUT VOLTAGE (V) VI, INPUT VOLTAGE (V) Figure 6-7. Typical Voltage Transfer Characteristics Figure 6-8. Typical Voltage Transfer Characteristics as a Function of Temperature for CD4049UB as a Function of Temperature for CD4050B µR INVERTER (W)110054 TA=S U2P5PoLCY V O LT A G E V C C = 15V 10V10V 5V PE103 N O TI A P SI102 LOAD CAPACITANCE DIS (C1L1p=F 5 F0IpXFTURE + 39pF EXT) ER CL= 15pF OW10 (11pF FIXTURE + 4pF EXT) P 10 102 103 104 105 f, INPUT FREQUENCY(kHz) Figure 6-9. Typical Power Dissipation versus Frequency Characteristics 7 Parameter Measurement Information 7.1 Test Circuits VCC VCC VCC INPUTS OUTPUTS INPUTS VIH + DVM VSS - VIL VSS IDD Test any one input with other inputs at VCC or VSS. Figure 7-2. Input Voltage Test Circuit VSS Figure 7-1. Quiescent Device Current Test Circuit Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: CD4049UB CD4050B

CD4049UB, CD4050B SCHS046K – AUGUST 1998 – REVISED JUNE 2020 www.ti.com VCC CMOS 10V LEVELTO DTL/TTL5V LEVEL INPUTS OUTPUTS VCC= 5V VCC COS/MOS OUTPUT IN TO DTL/TTL I INPUTS VSS 10V = VIH VSS 0 = VIL VSS Measure inputs sequentially, to both VCC and VSS connect all IN Pin: A, B, C, D, E, or F unused inputs to either VCC or VSS. B. OUT Pin: G, H, I, J, K, or L Figure 7-3. Input Current Test Circuit C. VCC Pin D. VSS Pin Figure 7-4. Logic Level Conversion Application VDD µF 0.1µF 500 I 1 16 2 15 CL 3 B 14 U 4 9 13 4 10kHz, 5 40 12 100kHz, 1MHz 6 CD 11 7 10 8 9 C includes fixture capacitance. L Figure 7-5. Dynamic Power Dissipation Test Circuits 12 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: CD4049UB CD4050B

CD4049UB, CD4050B www.ti.com SCHS046K – AUGUST 1998 – REVISED JUNE 2020 8 Detailed Description 8.1 Overview The CD4049UB device is an inverting hex buffer; the CD4050B device is a noninverting hex buffer. These devices do logic-level conversions and have a high sink current that can drive two TTL loads. These devices also have low input current of 1 µA across the full temperature range at 18 V. The CD4049UB and CD4050B devices are designated as replacements for CD4009UB and CD4010B devices, respectively. Because the CD4049UB and CD4050B require only one power supply, they are preferred over the CD4009UB and CD4010B and should be used in place of the CD4009UB and CD4010B in all inverter, current driver, or logic-level conversion applications. In these applications the CD4049UB and CD4050B are pin compatible with the CD4009UB and CD4010B respectively, and can be substituted for these devices in existing as well as in new designs. Pin 16 (NC) is not connected internally on the CD4049UB or CD4050B, therefore, connection to this terminal is of no consequence to circuit operation. TI recommends the CD4069UB hex inverter is recommended for applications not requiring high sink-current or voltage conversion. 8.2 Functional Block Diagram CD4050B 3 2 3 2 A G=A A G =A 5 4 5 4 B H=B B H = B 7 6 7 6 C I=C C I = C 9 10 9 10 D J=D D J = D 11 12 11 12 E K=E E K = E 14 15 14 15 F L=F F L= F 1 1 VCC VCC 8 8 VSS VSS NC = 13 NC = 13 NC = 16 NC = 16 Copyright © 2016,Texas Instruments Incorporated 8.3 Feature Description CD4049UB and CD4050B have standardized symmetrical output characteristics and a wide operating voltage from 3 V to 18 V with quiescent current tested at 20 V. These devices have transition times of t = 40 ns and TLH t = 20 ns (typical) at 10 V. The operating temperature is from –55°C to 125°C. THL Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: CD4049UB CD4050B

CD4049UB, CD4050B SCHS046K – AUGUST 1998 – REVISED JUNE 2020 www.ti.com 8.4 Device Functional Modes Table 8-1 shows the functional modes for CD4049UB. Table 8-2 shows the functional modes for CD4050B. Table 8-1. Function Table for CD4049UB INPUT OUTPUT A, B, C, D, E, F G, H, I, J, K, L H L L H Table 8-2. Function Table for CD4050B INPUT OUTPUT A, B, C, D, E, F G, H, I, J, K, L H H L L 14 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: CD4049UB CD4050B

CD4049UB, CD4050B www.ti.com SCHS046K – AUGUST 1998 – REVISED JUNE 2020 9 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The CD4049UB and CD4050B devices have low input currents of 1 µA at 18 V over full package-temperature range and 100 nA at 18 V, 25°C. These devices have a wide operating voltage from 3 V to 18 V and used in high-voltage applications. 9.2 Typical Application V CC C Logic signal LED R Copyright © 2016, Texas Instruments Incorporated Figure 9-1. CD4049UB Application 9.2.1 Design Requirements The CD4049UB device is the industry's highest logic inverter operating at 18 V under recommended conditions. These devices have high sink current capabilities. 9.2.2 Detailed Design Procedure The recommended input conditions for Figure 9-1 includes rise time and fall time specifications (see Δt/ΔV in Recommended Operating Conditions) and specified high and low levels (see V and V in Recommended IH IL Operating Conditions). Inputs are not overvoltage tolerant and must be below V level because of the presence CC of input clamp diodes to VCC. The recommended output condition for the CD4049UB application includes specific load currents. Load currents must be limited so as to not exceed the total power (continuous current through VCC or GND) for the device. These limits are in the Absolute Maximum Ratings. Outputs must not be pulled above V . CC Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: CD4049UB CD4050B

CD4049UB, CD4050B SCHS046K – AUGUST 1998 – REVISED JUNE 2020 www.ti.com 9.2.3 Application Curves µTER (W)105 TA= 25oC µER (W) 110065 TA= 25oC R T E R PER INV104 11115505VVVV;;;; 1111M00000kHkkHzHHzzz ER INVE 104 111550VVV;;; 111M0000HkkzHHzz ATION 103 1105VV;; 110kkHHzz TION P 103 1150VV;; 1100kkHHzz SSIP102 SIPA 102 ER DI 10 R DIS 10 W E PO SUPPLYVOLTAGE VCC= 5V FREQUENCY(f) = 10kHz POW 1 SUPPLYVOLTAGE VCC= 5V FREQUENCY(f) = 10kHz 10 102 103 104 105 10 102 103 104 105 106 107 108 tr, tf, INPUT RISEAND FALLTIME (ns) tr, tf, INPUT RISEAND FALLTIME (ns) Figure 9-2. Typical Power Dissipation vs Input Rise Figure 9-3. Typical Power Dissipation vs Input Rise and Fall Times Per Inverter for CD4049UB and Fall Times Per Buffer for CD4050B 10 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating in Recommended Operating Conditions. Each VCC pin must have a good bypass capacitor to prevent power disturbance. For devices with a single supply, TI recommends a 0.1-µF capacitor. If there are multiple VCC pins, then TI recommends a 0.01-µF or 0.022-µF capacitor for each power pin. It is acceptable to parallel multiple bypass capacitors to reject different frequencies of noise. 0.1-µF and 1-µF capacitors are commonly used in parallel. The bypass capacitor must be installed as close to the power pin as possible for best results. 11 Layout 11.1 Layout Guidelines When using multiple bit logic devices, inputs must never float. In many cases, digital logic device functions or parts of these functions are unused (for example, when only two inputs of a triple-input and gate are used, or only 3 of the 4 buffer gates are used). Such input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. This rule must be observed under all circumstances specified in the next paragraph. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. See Implications of Slow or Floating CMOS Inputs for more information on the effects of floating inputs. The logic level must apply to any particular unused input depending on the function of the device. Generally, they are tied to GND or VCC (whichever is convenient). 11.2 Layout Example VCC Input Unused Input Output Unused Input Output Input Figure 11-1. Layout Diagram 16 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: CD4049UB CD4050B

CD4049UB, CD4050B www.ti.com SCHS046K – AUGUST 1998 – REVISED JUNE 2020 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation For related documentation see the following: Implications of Slow or Floating CMOS Inputs (SCBA004) 12.2 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 12-1. Related Links TECHNICAL TOOLS & SUPPORT & PARTS PRODUCT FOLDER SAMPLE & BUY DOCUMENTS SOFTWARE COMMUNITY CD4049UB Click here Click here Click here Click here Click here CD4050B Click here Click here Click here Click here Click here 12.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.4 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 12.5 Trademarks TI E2E™ is a trademark of Texas Instruments Incorporated. All other trademarks are the property of their respective owners. 12.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.7 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: CD4049UB CD4050B

PACKAGE OPTION ADDENDUM www.ti.com 16-Jun-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) CD4049UBD ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CD4049UBM & no Sb/Br) CD4049UBDE4 ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CD4049UBM & no Sb/Br) CD4049UBDR ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CD4049UBM & no Sb/Br) CD4049UBDRE4 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CD4049UBM & no Sb/Br) CD4049UBDRG4 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CD4049UBM & no Sb/Br) CD4049UBDT ACTIVE SOIC D 16 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CD4049UBM & no Sb/Br) CD4049UBDW ACTIVE SOIC DW 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CD4049UBM & no Sb/Br) CD4049UBDWG4 ACTIVE SOIC DW 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CD4049UBM & no Sb/Br) CD4049UBE ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -55 to 125 CD4049UBE & no Sb/Br) CD4049UBEE4 ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -55 to 125 CD4049UBE & no Sb/Br) CD4049UBF ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type -55 to 125 CD4049UBF CD4049UBF3A ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type -55 to 125 CD4049UBF3A CD4049UBNSR ACTIVE SO NS 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CD4049UB & no Sb/Br) CD4049UBPW ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CM049UB & no Sb/Br) CD4049UBPWR ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CM049UB & no Sb/Br) CD4050BD ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CD4050BM & no Sb/Br) CD4050BDE4 ACTIVE SOIC D 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CD4050BM & no Sb/Br) Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 16-Jun-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) CD4050BDR ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CD4050BM & no Sb/Br) CD4050BDRG4 ACTIVE SOIC D 16 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CD4050BM & no Sb/Br) CD4050BDT ACTIVE SOIC D 16 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CD4050BM & no Sb/Br) CD4050BDW ACTIVE SOIC DW 16 40 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CD4050BM & no Sb/Br) CD4050BDWR ACTIVE SOIC DW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CD4050BM & no Sb/Br) CD4050BE ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -55 to 125 CD4050BE & no Sb/Br) CD4050BEE4 ACTIVE PDIP N 16 25 Green (RoHS NIPDAU N / A for Pkg Type -55 to 125 CD4050BE & no Sb/Br) CD4050BF ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type -55 to 125 CD4050BF CD4050BF3A ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type -55 to 125 CD4050BF3A CD4050BNSR ACTIVE SO NS 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CD4050B & no Sb/Br) CD4050BPW ACTIVE TSSOP PW 16 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CM050B & no Sb/Br) CD4050BPWR ACTIVE TSSOP PW 16 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CM050B & no Sb/Br) JM38510/05553BEA ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/ 05553BEA JM38510/05554BEA ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/ 05554BEA M38510/05553BEA ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/ 05553BEA M38510/05554BEA ACTIVE CDIP J 16 1 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/ 05554BEA (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 16-Jun-2020 OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF CD4049UB, CD4049UB-MIL, CD4050B, CD4050B-MIL : •Catalog: CD4049UB, CD4050B •Military: CD4049UB-MIL, CD4050B-MIL NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 16-Jun-2020 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) CD4049UBDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD4049UBPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 CD4050BDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD4050BDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 CD4050BNSR SO NS 16 2000 330.0 16.4 8.45 10.55 2.5 12.0 16.2 Q1 CD4050BPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 16-Jun-2020 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) CD4049UBDR SOIC D 16 2500 333.2 345.9 28.6 CD4049UBPWR TSSOP PW 16 2000 367.0 367.0 35.0 CD4050BDR SOIC D 16 2500 333.2 345.9 28.6 CD4050BDWR SOIC DW 16 2000 350.0 350.0 43.0 CD4050BNSR SO NS 16 2000 367.0 367.0 38.0 CD4050BPWR TSSOP PW 16 2000 367.0 367.0 35.0 PackMaterials-Page2

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PACKAGE OUTLINE PW0016A TSSOP - 1.2 mm max height SCALE 2.500 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 14X 0.65 16 1 2X 5.1 4.55 4.9 NOTE 3 8 9 0.30 B 4.5 16X 0.19 1.2 MAX 4.3 0.1 C A B NOTE 4 (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.05 0.75 0.50 0 -8 DETA 20AIL A TYPICAL 4220204/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com

EXAMPLE BOARD LAYOUT PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL UNDER SOLDER MASK OPENING METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX 0.05 MIN ALL AROUND ALL AROUND NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDE15.000R MASK DETAILS 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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GENERIC PACKAGE VIEW DW 16 SOIC - 2.65 mm max height 7.5 x 10.3, 1.27 mm pitch SMALL OUTLINE INTEGRATED CIRCUIT This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4224780/A www.ti.com

PACKAGE OUTLINE DW0016A SOIC - 2.65 mm max height SCALE 1.500 SOIC C 10.63 SEATING PLANE TYP 9.97 A PIN 1 ID 0.1 C AREA 14X 1.27 16 1 10.5 2X 10.1 8.89 NOTE 3 8 9 0.51 16X 0.31 7.6 B 7.4 0.25 C A B 2.65 MAX NOTE 4 0.33 TYP 0.10 SEE DETAIL A 0.25 GAGE PLANE 0.3 0 - 8 0.1 1.27 0.40 DETAIL A (1.4) TYPICAL 4220721/A 07/2016 NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side. 5. Reference JEDEC registration MS-013. www.ti.com

EXAMPLE BOARD LAYOUT DW0016A SOIC - 2.65 mm max height SOIC 16X (2) SEE SYMM DETAILS 1 16 16X (0.6) SYMM 14X (1.27) 8 9 R0.05 TYP (9.3) LAND PATTERN EXAMPLE SCALE:7X METAL SOLDER MASK SOLDER MASK METAL OPENING OPENING 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4220721/A 07/2016 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DW0016A SOIC - 2.65 mm max height SOIC 16X (2) SYMM 1 16 16X (0.6) SYMM 14X (1.27) 8 9 R0.05 TYP (9.3) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:7X 4220721/A 07/2016 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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