Product Sample & Technical Tools & Support & Folder Buy Documents Software Community CD4013B SCHS023E–NOVEMBER1998–REVISEDSEPTEMBER2016 CD4013B CMOS Dual D-Type Flip-Flop 1 Features 3 Description • AsynchronousSet-ResetCapability The CD4013B device consists of two identical, 1 independent data-type flip-flops. Each flip-flop has • StaticFlip-FlopOperation independent data, set, reset, and clock inputs and Q • Medium-SpeedOperation:16MHz(Typical)Clock and Q outputs. These devices can be used for shift ToggleRateat10-VSupply register applications, and, by connecting Q output to • StandardizedSymmetricalOutputCharacteristics the data input, for counter and toggle applications. The logic level present at the D input is transferred to • MaximumInputCurrentOf1-µAat18VOverFull theQoutputduringthepositive-goingtransitionofthe PackageTemperatureRange: clock pulse. Setting or resetting is independent of the – 100nAat18Vand25°C clock and is accomplished by a high level on the set • NoiseMargin(OverFullPackageTemperature orresetline,respectively. Range): The CD4013B types are supplied in 14-pin dual-in- – 1VatV =5V line plastic packages (E suffix), 14-pin small-outline DD packages (M, MT, M96, and NSR suffixes), and – 2VatV =10V DD 14-pin thin shrink small-outline packages (PW and – 2.5VatV =15V DD PWRsuffixes). 2 Applications DeviceInformation(1) • PowerDelivery PARTNUMBER PACKAGE BODYSIZE(NOM) • GridInfrastructure CD4013BE PDIP(14) 19.30mmx6.35mm • Medical,Healthcare,andFitness CD4013BF CDIP(14) 19.50mmx6.92mm CD4013BM SOIC(14) 8.65mmx3.90mm • BodyElectronicsandLighting CD4013BNS SO(14) 10.20mmx5.30mm • BuildingAutomation CD4013BPW TSSOP(14) 5.00mmx4.40mm • TelecomInfrastructure (1) For all available packages, see the orderable addendum at • TestandMeasurement theendofthedatasheet. LogicDiagram 4 (10) CL All inputs are protected by RESET MASTER SECTION SLAVE SECTION CMOS protection network CL p VDD p TG 5 (9) TG n DATA n CL CL CL CL p p TG TG n n CL CL VSS 6 (8) SET Q 1 (13) CL CL Buffered Outputs 3 (11) Q CL 2 (12) VDD = Pin 14 VSS = Pin 7 Copyright © 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

CD4013B SCHS023E–NOVEMBER1998–REVISEDSEPTEMBER2016 www.ti.com Table of Contents 1 Features.................................................................. 1 7.4 DeviceFunctionalModes........................................10 2 Applications........................................................... 1 8 ApplicationandImplementation........................ 11 3 Description............................................................. 1 8.1 ApplicationInformation............................................11 4 RevisionHistory..................................................... 2 8.2 TypicalApplication..................................................11 5 PinConfigurationandFunctions......................... 3 9 PowerSupplyRecommendations...................... 12 6 Specifications......................................................... 4 10 Layout................................................................... 12 6.1 AbsoluteMaximumRatings......................................4 10.1 LayoutGuidelines ................................................12 6.2 ESDRatings..............................................................4 10.2 LayoutExample....................................................12 6.3 RecommendedOperatingConditions.......................4 11 DeviceandDocumentationSupport................. 14 6.4 ThermalInformation..................................................5 11.1 DocumentationSupport........................................14 6.5 ElectricalCharacteristics:Static................................5 11.2 ReceivingNotificationofDocumentationUpdates14 6.6 ElectricalCharacteristics:Dynamic...........................7 11.3 CommunityResources..........................................14 6.7 TypicalCharacteristics..............................................8 11.4 Trademarks...........................................................14 7 DetailedDescription............................................ 10 11.5 ElectrostaticDischargeCaution............................14 7.1 Overview ................................................................10 11.6 Glossary................................................................14 7.2 FunctionalBlockDiagram.......................................10 12 Mechanical,Packaging,andOrderable Information........................................................... 14 7.3 FeatureDescription................................................10 4 Revision History ChangesfromRevisionD(March2005)toRevisionE Page • AddedESDRatingstable,FeatureDescriptionsection,DeviceFunctionalModes,ApplicationandImplementation section,PowerSupplyRecommendationssection,Layoutsection,DeviceandDocumentationSupportsection,and Mechanical,Packaging,andOrderableInformationsection.................................................................................................. 1 • AddedThermalInformationtable........................................................................................................................................... 5 2 SubmitDocumentationFeedback Copyright©1998–2016,TexasInstrumentsIncorporated ProductFolderLinks:CD4013B

CD4013B www.ti.com SCHS023E–NOVEMBER1998–REVISEDSEPTEMBER2016 5 Pin Configuration and Functions D,J,N,NS,PWPackage 14-PinSOIC,CDIP,PDIP,SO,TSSOP TopView Q1 1 14 VDD Q1 2 13 Q2 CLOCK1 3 12 Q2 RESET1 4 11 CLOCK2 D1 5 10 RESET2 SET1 6 9 D2 VSS 7 8 SET2 Not to scale PinFunctions PIN I/O DESCRIPTION NO. NAME 1 Q1 O Channel1output 2 Q1 O Invertedchannel1output 3 CLOCK1 I Channel1clockinput 4 RESET1 I Channel1reset 5 D1 I Channel1datainput 6 SET1 I Channel1set 7 V — Ground SS 8 SET2 I Channel2set 9 D2 I Channel2datainput 10 RESET2 I Channel2reset 11 CLOCK2 I Channel2clockinput 12 Q2 O Invertedchannel2output 13 Q2 O Channel2output 14 V — Powersupply DD Copyright©1998–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:CD4013B

CD4013B SCHS023E–NOVEMBER1998–REVISEDSEPTEMBER2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) MIN MAX UNIT DCsupplyvoltage,V (2) –0.5 20 V DD Inputvoltage,allinputs –0.5 V +0.5 V DD DCinputcurrent,anyoneinput 10 mA T =–55°Cto100°C 500 A Powerdissipation,P mW D T =100°Cto125°C(3) 200 A Devicedissipationperoutputtransistor 100 mW Operatingtemperature,T –55 125 °C A Storagetemperature,T –65 150 °C stg (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,whichdonotimplyfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommended OperatingConditions.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) VoltagesreferencetoV terminal SS (3) Deratelinearityat12mW/°C 6.2 ESD Ratings VALUE UNIT Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±2000 V Electrostaticdischarge V (ESD) Charged-devicemodel(CDM),perJEDECspecificationJESD22-C101(2) ±1000 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess. 6.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN TYP MAX UNIT Supplyvoltage 3 18 V V =5 40 DD t Datasetuptime V =10 20 ns S DD V =15 15 DD V =5 140 DD t Clockpulsewidth V =10 60 ns W DD V =15 40 DD V =5 3.5 7 DD f Clockinputfrequency V =10 8 16 MHz CL DD V =15 12 24 DD V =5 15 DD tCL(1) r Clockriseorfalltime V =10 10 µs tCL DD f V =15 5 DD V =5 180 DD t Setorresetpulsewidth V =10 80 ns W DD V =15 50 DD (1) Ifmorethanoneunitiscascadedinaparallelclockedoperation,tCLmustbemadelessthanorequaltothesumofthefixed r propagationdelaytimeat15pFandthetransistiontimeoftheoutputdrivingstagefortheestimatedcapacitiveload. 4 SubmitDocumentationFeedback Copyright©1998–2016,TexasInstrumentsIncorporated ProductFolderLinks:CD4013B

CD4013B www.ti.com SCHS023E–NOVEMBER1998–REVISEDSEPTEMBER2016 6.4 Thermal Information CD4013B THERMALMETRIC(1) N(PDIP) D(SOIC) NS(SO) PW(TSSOP) UNIT 14PINS 14PINS 14PINS 14PINS R Junction-to-ambientthermalresistance 47.1 92.5 89.3 121 °C/W θJA R Junction-to-case(top)thermalresistance 34.5 54 47.1 49.6 °C/W θJC(top) R Junction-to-boardthermalresistance 27.1 46.8 48 62.7 °C/W θJB ψ Junction-to-topcharacterizationparameter 19.4 19 17 5.9 °C/W JT ψ Junction-to-boardcharacterizationparameter 27 46.5 47.7 62.1 °C/W JB (1) Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplication report. 6.5 Electrical Characteristics: Static overoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT T =–55°C 1 A T =–40°C 1 A V =0or5,V =5 T =25°C 0.02 1 IN DD A T =85°C 30 A T =125°C 30 A T =–55°C 2 A T =–40°C 2 A V =0or10,V =10 T =25°C 0.02 2 IN DD A T =85°C 60 A T =125°C 60 A I max Quiescentdevicecurrent µA DD T =–55°C 4 A T =–40°C 4 A V =0or15,V =15 T =25°C 0.02 4 IN DD A T =85°C 120 A T =125°C 120 A T =–55°C 20 A T =–40°C 20 A V =0or20,V =20 T =25°C 0.04 20 IN DD A T =85°C 600 A T =125°C 600 A Copyright©1998–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLinks:CD4013B

CD4013B SCHS023E–NOVEMBER1998–REVISEDSEPTEMBER2016 www.ti.com Electrical Characteristics: Static (continued) overoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT T =–55°C 0.64 A T =–40°C 0.61 A V =0.4,V =0or5, O IN T =25°C 0.51 1 V =5 A DD T =85°C 0.42 A T =125°C 0.36 A T =–55°C 1.6 A T =–40°C 1.5 A V =0.5,V =0or10, I min Outputlow(sink)current O IN T =25°C 1.3 2.6 mA OL V =10 A DD T =85°C 1.1 A T =125°C 0.9 A T =–55°C 4.2 A T =–40°C 4 A V =1.5,V =0or15, O IN T =25°C 3.4 6.8 V =15 A DD T =85°C 2.8 A T =125°C 2.4 A T =–55°C –0.64 A T =–40°C –0.61 A V =4.6,V =0or5, O IN T =25°C –0.51 –1 V =5 A DD T =85°C –0.42 A T =125°C –0.36 A T =–55°C –2 A T =–40°C –1.8 A V =2.5,V =0or5, O IN T =25°C –1.6 –3.2 V =5 A DD T =85°C –1.3 A Outputhigh(source) TA=125°C –1.15 I min mA OH current T =–55°C –1.6 A T =–40°C –1.5 A V =9.5,V =0or10, O IN T =25°C –1.3 –2.6 V =10 A DD T =85°C –1.1 A T =125°C –0.9 A T =–55°C –4.2 A T =–40°C –4 A V =13.5,V =0or15, O IN T =25°C –3.4 –6.8 V =15 A DD T =85°C –2.8 A T =125°C –2.4 A T =–55°C,–40°C, V =0or5,V =5 A 0 0.05 IN DD 25°C,85°C,and125°C T =–55°C,–40°C, V max Low-leveloutputvoltage V =0or10,V =10 A 0 0.05 V OL IN DD 25°C,85°C,and125°C T =–55°C,–40°C, V =0or15,V =15 A 0 0.05 IN DD 25°C,85°C,and125°C T =–55°C,–40°C, V =0or5,V =5 A 4.95 5 IN DD 25°C,85°C,and125°C T =–55°C,–40°C, V min High-leveloutputvoltage V =0or10,V =10 A 9.95 10 V OH IN DD 25°C,85°C,and125°C T =–55°C,–40°C, V =0or15,V =15 A 14.95 15 IN DD 25°C,85°C,and125°C 6 SubmitDocumentationFeedback Copyright©1998–2016,TexasInstrumentsIncorporated ProductFolderLinks:CD4013B

CD4013B www.ti.com SCHS023E–NOVEMBER1998–REVISEDSEPTEMBER2016 Electrical Characteristics: Static (continued) overoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT T =–55°C,–40°C, V =0.5or4.5,V =5 A 1.5 O DD 25°C,85°C,and125°C T =–55°C,–40°C, V max Inputlowvoltage V =1or9,V =10 A 3 V IL O DD 25°C,85°C,and125°C V =1.5or13.5, T =–55°C,–40°C, O A 4 V =15 25°C,85°C,and125°C DD T =–55°C,–40°C, V =0.5or4.5,V =5 A 3.5 O DD 25°C,85°C,and125°C T =–55°C,–40°C, V min Inputhighvoltage V =1or9,V =10 A 7 V IH O DD 25°C,85°C,and125°C V =1.5or13.5, T =–55°C,–40°C, O A 11 V =15 25°C,85°C,and125°C DD T =–55°C ±0.1 A T =–40°C ±0.1 A I max Inputcurrent V =0or18,V =18 T =25°C ±10–5 ±0.1 µA IN IN DD A T =85°C ±1 A T =125°C ±1 A 6.6 Electrical Characteristics: Dynamic atT =25°C,inputt,t =20ns,C =50pF,R =20kΩ(unlessotherwisenoted) A r f L L PARAMETER TESTCONDITIONS MIN TYP MAX UNIT V =5 150 300 DD t , Propagationdelaytime, PHL V =10 65 130 ns t clocktoQorQoutputs DD PLH V =15 45 90 DD V =5 150 300 DD t SettoQorresettoQ V =10 65 130 ns PLH DD V =15 45 90 DD V =5 200 400 DD t SettoQorresettoQ V =10 85 170 ns PHL DD V =15 60 120 DD V =5 100 200 DD t , THL Transitiontime V =10 50 100 ns t DD TLH V =15 40 80 DD V =5 3.5 7 DD f Maximumclockinputfrequency(1) V =10 8 16 MHz CL DD V =15 12 24 DD V =5 70 140 DD Minimumclockpulsewidth V =10 30 60 ns DD V =15 20 40 DD t W V =5 90 180 DD Minimumsetorresetpulsewidth V =10 40 80 ns DD V =15 25 50 DD V =5 20 40 DD t Minimumdatasetuptime V =10 10 20 ns S DD V =15 7 15 DD t Minimumdataholdtime V =5,10,15 2 5 ns H DD (1) Inputt,t =5ns r f Copyright©1998–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:CD4013B

CD4013B SCHS023E–NOVEMBER1998–REVISEDSEPTEMBER2016 www.ti.com Electrical Characteristics: Dynamic (continued) atT =25°C,inputt,t =20ns,C =50pF,R =20kΩ(unlessotherwisenoted) A r f L L PARAMETER TESTCONDITIONS MIN TYP MAX UNIT V =5 15 DD tCL, r Clockinputriseorfalltime V =10 10 µs tCL DD f V =15 5 DD C Inputcapacitance Anyinput 5 7.5 pF IN 6.7 Typical Characteristics 40 20 Gate-to-Source Voltage = 5 V Gate-to-Source Voltage = 5 V 35 Gate-to-Source Voltage = 10 V 17.5 Gate-to-Source Voltage = 10 V A) Gate-to-Source Voltage = 15 V A) Gate-to-Source Voltage = 15 V m m nt ( 30 nt ( 15 e e urr 25 urr 12.5 C C nk) 20 nk) 10 Si Si w ( 15 w ( 7.5 o o L L ut 10 ut 5 p p ut ut O O 5 2.5 0 0 0 5 10 15 20 25 0 5 10 15 20 25 Drain-to-Source Voltage (V) Drain-to-Source Voltage (V) D001 D002 Figure1.TypicalOutputLow(Sink)Current Figure2.MinimumOutputLow(Sink)Current 0 0 Gate-to-Source Voltage = -5 V Gate-to-Source Voltage = -5 V A) -5 Gate-to-Source Voltage = -10 V A) Gate-to-Source Voltage = -10 V m Gate-to-Source Voltage = -15 V m Gate-to-Source Voltage = -15 V nt ( -10 nt ( -5 e e Curr -15 Curr e) e) urc -20 urc -10 o o S S h ( -25 h ( g g Hi Hi ut -30 ut -15 p p Out -35 Out -40 -20 -25 -20 -15 -10 -5 0 -25 -20 -15 -10 -5 0 Drain-to-Source Voltage (V) Drain-to-Source Voltage (V) D003 D004 Figure3.TypicalOutputHigh(Source)Current Figure4.MinimumOutputHigh(Source)Current 8 SubmitDocumentationFeedback Copyright©1998–2016,TexasInstrumentsIncorporated ProductFolderLinks:CD4013B

CD4013B www.ti.com SCHS023E–NOVEMBER1998–REVISEDSEPTEMBER2016 Typical Characteristics (continued) 300 300 Supply Voltage = 5 V Supply Voltage = 5 V Supply Voltage = 10 V Supply Voltage = 10 V s) 250 Supply Voltage = 15 V s) 250 Supply Voltage = 15 V n n e ( e ( m 200 m 200 Ti Ti y y a a Del 150 Del 150 n n o o gati 100 gati 100 a a p p o o Pr 50 Pr 50 0 0 0 20 40 60 80 100 0 20 40 60 80 100 Load Capacitance (pF) Load Capacitance (pF) D023 D024 CLOCKorSETtoQ,CLOCKorRESETtoQ SETtoQorRESETtoQ Figure5.TypicalPropagationDelayTime Figure6.TypicalPropagationDelayTime vsLoadCapacitance vsLoadCapacitance 40 10k 35 W) P z) 30 ce ( 1k H vi M e cy ( 25 er D n P ue 20 n e100 q o Fre 15 pati k si c s Clo 10 er Di 10 Supply Voltage = 5 V w Supply Voltage = 10 V (CL = 15 pF) 5 Po Supply Voltage = 10 V (CL = 50 pF) Supply Voltage = 15 V 0 1 0 5 10 15 20 25 100 1k 10k 100k 1M 10M Supply Voltage (V) Input Clock Frequency (kHz) D025 D026 Figure7.TypicalMaximumClockFrequency Figure8.TypicalPowerDissipationvsFrequency vsSupplyVoltage Copyright©1998–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:CD4013B

CD4013B SCHS023E–NOVEMBER1998–REVISEDSEPTEMBER2016 www.ti.com 7 Detailed Description 7.1 Overview The CD4013B device consists of two identical, independent data-type flip-flops. Each flip-flop has independent data, set, reset, and clock inputs and Q and Q outputs. These devices are ideal for data and memory hold functions, including shift register applications, or by connecting Q output to the data input, this device is used for counter and toggle applications. The CD4013B is a positive-edge triggered device, meaning that the logic level present at the D input is transferred to the Q output during the positive-going transition of the clock pulse. Setting orresettingisindependentoftheclockandisaccomplishedbyahighlevelonthesetorresetline,respectively. 7.2 Functional Block Diagram VDD 6 SET1 5 2 D1 Q1 3 F/F1 1 CLOCK1 Q1 4 RESET1 8 SET2 9 12 D2 Q2 11 F/F2 13 CLOCK2 Q2 10 RESET2 VSS Copyright © 2016, Texas Instruments Incorporated 7.3 Feature Description CD4013B has standardized symmetrical output characteristics and a wide operating voltage range from 3 V to 18 V with quiescent current tested at 20 V. This has a medium operation speed –t , t = 30 ns (typical) at 10 PHL PLH V.Theoperatingtemperatureisfrom –55°Cto125°C. 7.4 Device Functional Modes Table1liststhefunctionalmodesoftheCD4013B. Table1.FunctionTable INPUTS OUTPUT(Q) INVERTEDOUTPUT(Q) CLOCK SET RESET D ↑ 0 0 0 0 1 ↑ 0 0 1 1 0 ↓ 0 0 X Q Q 0 X 0 1 X 0 1 X 1 0 X 1 0 X 1 1 X 1 1 10 SubmitDocumentationFeedback Copyright©1998–2016,TexasInstrumentsIncorporated ProductFolderLinks:CD4013B

CD4013B www.ti.com SCHS023E–NOVEMBER1998–REVISEDSEPTEMBER2016 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validateandtesttheirdesignimplementationtoconfirmsystemfunctionality. 8.1 Application Information A high level at the SET or RESET inputs sets or resets the outputs, regardless of the levels of the other inputs. When SET and RESET are inactive (low), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. The resistor and capacitor at the RESET pin are optional.Iftheyarenotused,theRESETandSETpinmustbeconnecteddirectlytogroundtobeinactive. 8.2 Typical Application 3V 3V 3V NC VCC A GND Y CLK VCC SN74LVC1G17 D SET Q RESET GND Q TOMCU CD4013B Copyright © 2016, Texas Instruments Incorporated Figure9. PowerButtonCircuit 8.2.1 DesignRequirements Input signals must be designed and implemented so that they do not exceed the voltage level of the power supply. 8.2.2 DetailedDesignProcedure The recommended input conditions for this application example includes rise time and fall time specifications (see Δt/ΔV in Recommended Operating Conditions) and specified high and low levels (see VIH and VIL in Recommended Operating Conditions). Inputs are not overvoltage tolerant and must be below V level because CC of the presence of input clamp diodes to V . The recommended output condition for the CD4013B application CC includes specific load currents. Load currents must be limited so as to not exceed the total power (continuous current through V or GND) for the device. These limits are located in Absolute Maximum Ratings. Outputs CC mustnotbepulledaboveV . CC Copyright©1998–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:CD4013B

CD4013B SCHS023E–NOVEMBER1998–REVISEDSEPTEMBER2016 www.ti.com Typical Application (continued) 8.2.3 ApplicationCurve 140 CL = 15 pF CL = 50 pF 120 s) n e ( 100 m Ti y 80 a el D n 60 o ati g a 40 p o Pr 20 0 0 5 10 15 20 25 Supply Voltage (V) D037 Figure10.TypicalTransitionTimevsLoadCapacitance 9 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in Recommended Operating Conditions. Each V pin must have a good bypass capacitor to prevent power CC disturbance. For devices with a single supply, TI recommends a 0.1-μF capacitor. If there are multiple V pins, CC then TI recommends a 0.01-μF or 0.022-μF capacitor for each power pin. It is acceptable to parallel multiple bypass capacitors to reject different frequencies of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel.Thebypasscapacitormustbeinstalledasclosetothepowerpinaspossibleforbestresults. 10 Layout 10.1 Layout Guidelines Whenusingmultiplebitlogicdevices,inputsmustneverfloat. In many cases, digital logic device functions or parts of these functions are unused (for example, when only two inputs of a triple-input and gate are used, or only 3 of the 4 buffer gates are used). Such input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states.Thisrulemustbeobservedunderallcircumstancesspecifiedinthenextparagraph. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. See application note, Implications of Slow or Floating CMOS Inputs (SCBA004), for more information on the effects of floating inputs. The logic level must apply to any particular unused input depending on the function of thedevice.Generally,theyaretiedtoGNDorV (whicheverisconvenient). CC 10.2 Layout Example VCC Input Unused Input Output Unused Input Output Input Figure11. LayoutExampleforCD4013B 12 SubmitDocumentationFeedback Copyright©1998–2016,TexasInstrumentsIncorporated ProductFolderLinks:CD4013B

CD4013B www.ti.com SCHS023E–NOVEMBER1998–REVISEDSEPTEMBER2016 Layout Example (continued) Figure12. DimensionsandPadLayoutforCD4013B Copyright©1998–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:CD4013B

CD4013B SCHS023E–NOVEMBER1998–REVISEDSEPTEMBER2016 www.ti.com 11 Device and Documentation Support 11.1 Documentation Support 11.1.1 RelatedDocumentation Forrelateddocumentationseethefollowing: ImplicationsofSloworFloatingCMOSInputs (SCBA004) 11.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed.Forchangedetails,reviewtherevisionhistoryincludedinanyreviseddocument. 11.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TIE2E™OnlineCommunity TI'sEngineer-to-Engineer(E2E)Community.Createdtofostercollaboration amongengineers.Ate2e.ti.com,youcanaskquestions,shareknowledge,exploreideasandhelp solveproblemswithfellowengineers. DesignSupport TI'sDesignSupport QuicklyfindhelpfulE2Eforumsalongwithdesignsupporttoolsand contactinformationfortechnicalsupport. 11.4 Trademarks E2EisatrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 11.5 Electrostatic Discharge Caution Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. 11.6 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of thisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 14 SubmitDocumentationFeedback Copyright©1998–2016,TexasInstrumentsIncorporated ProductFolderLinks:CD4013B

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) CD4013BE ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type -55 to 125 CD4013BE & no Sb/Br) CD4013BEE4 ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type -55 to 125 CD4013BE & no Sb/Br) CD4013BF ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type -55 to 125 CD4013BF CD4013BF3A ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type -55 to 125 CD4013BF3A CD4013BM ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CD4013BM & no Sb/Br) CD4013BM96 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CD4013BM & no Sb/Br) CD4013BM96E4 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CD4013BM & no Sb/Br) CD4013BM96G4 ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CD4013BM & no Sb/Br) CD4013BME4 ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CD4013BM & no Sb/Br) CD4013BMG4 ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CD4013BM & no Sb/Br) CD4013BMT ACTIVE SOIC D 14 250 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CD4013BM & no Sb/Br) CD4013BNSR ACTIVE SO NS 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CD4013B & no Sb/Br) CD4013BPW ACTIVE TSSOP PW 14 90 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CM013B & no Sb/Br) CD4013BPWR ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CM013B & no Sb/Br) CD4013BPWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CM013B & no Sb/Br) CD4013BPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 CM013B & no Sb/Br) JM38510/05151BCA ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/ 05151BCA Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) M38510/05151BCA ACTIVE CDIP J 14 1 TBD Call TI N / A for Pkg Type -55 to 125 JM38510/ 05151BCA (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF CD4013B, CD4013B-MIL : •Catalog: CD4013B Addendum-Page 2

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 •Military: CD4013B-MIL NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product •Military - QML certified for Military and Defense Applications Addendum-Page 3

PACKAGE MATERIALS INFORMATION www.ti.com 8-Nov-2018 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) CD4013BM96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 CD4013BM96G4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 CD4013BMT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 CD4013BNSR SO NS 14 2000 330.0 16.4 8.1 10.4 2.5 12.0 16.0 Q1 CD4013BPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 8-Nov-2018 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) CD4013BM96 SOIC D 14 2500 367.0 367.0 38.0 CD4013BM96G4 SOIC D 14 2500 367.0 367.0 38.0 CD4013BMT SOIC D 14 250 210.0 185.0 35.0 CD4013BNSR SO NS 14 2000 367.0 367.0 38.0 CD4013BPWR TSSOP PW 14 2000 367.0 367.0 35.0 PackMaterials-Page2

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PACKAGE OUTLINE J0014A CDIP - 5.08 mm max height SCALE 0.900 CERAMIC DUAL IN LINE PACKAGE PIN 1 ID A 4X .005 MIN (OPTIONAL) [0.13] .015-.060 TYP [0.38-1.52] 1 14 12X .100 [2.54] 14X .014-.026 14X .045-.065 [0.36-0.66] [1.15-1.65] .010 [0.25] C A B .754-.785 [19.15-19.94] 7 8 B .245-.283 .2 MAX TYP .13 MIN TYP [6.22-7.19] [5.08] [3.3] SEATING PLANE C .308-.314 [7.83-7.97] AT GAGE PLANE .015 GAGE PLANE [0.38] 0 -15 14X .008-.014 TYP [0.2-0.36] 4214771/A 05/2017 NOTES: 1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package is hermitically sealed with a ceramic lid using glass frit. 4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only. 5. Falls within MIL-STD-1835 and GDIP1-T14. www.ti.com

EXAMPLE BOARD LAYOUT J0014A CDIP - 5.08 mm max height CERAMIC DUAL IN LINE PACKAGE (.300 ) TYP [7.62] SEE DETAIL B SEE DETAIL A 1 14 12X (.100 ) [2.54] SYMM 14X ( .039) [1] 7 8 SYMM LAND PATTERN EXAMPLE NON-SOLDER MASK DEFINED SCALE: 5X .002 MAX (.063) [0.05] [1.6] METAL ALL AROUND ( .063) SOLDER MASK [1.6] OPENING METAL .002 MAX SOLDER MASK (R.002 ) TYP [0.05] OPENING [0.05] ALL AROUND DETAIL A DETAIL B SCALE: 15X 13X, SCALE: 15X 4214771/A 05/2017 www.ti.com

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