Product Order Technical Tools & Support & Folder Now Documents Software Community CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 CC430F613x, CC430F612x, CC430F513x MSP430™ SoC With RF Core 1 Device Overview 1.1 Features 1 • TrueSystem-on-Chip(SoC)forLow-Power – SerialOnboardProgramming,NoExternal WirelessCommunicationApplications ProgrammingVoltageNeeded • WideSupplyVoltageRange: – EmbeddedEmulationModule(EEM) 3.6VDownto1.8V • High-PerformanceSub-1GHzRFTransceiver • Ultra-LowPowerConsumption Core – CPUActiveMode(AM):160 µA/MHz – SameasinCC1101 – StandbyMode(LPM3RTCMode):2.0 µA – WideSupplyVoltageRange:2Vto3.6V – OffMode(LPM4RAMRetention):1.0 µA – FrequencyBands:300MHzto348MHz, 389MHzto464MHz,and779MHzto928MHz – RadioinRX:15mA,250kbps,915MHz – ProgrammableDataRateFrom0.6kBaudto • MSP430™SystemandPeripherals 500kBaud – 16-BitRISCArchitecture,ExtendedMemory,up – HighSensitivity(–117dBmat0.6kBaud, to20-MHzSystemClock –111dBmat1.2kBaud,315MHz,1%Packet – WakeupFromStandbyModeinLess ErrorRate) Than6µs – ExcellentReceiverSelectivityandBlocking – FlexiblePower-ManagementSystemWithSVS Performance andBrownout – ProgrammableOutputPowerupto+12dBmfor – UnifiedClockSystemWithFLL AllSupportedFrequencies – 16-BitTimerTA0,Timer_AWithFive – 2-FSK,2-GFSK,andMSKSupported,Also Capture/CompareRegisters OOKandFlexibleASKShaping – 16-BitTimerTA1,Timer_AWithThree – FlexibleSupportforPacket-OrientedSystems: Capture/CompareRegisters On-ChipSupportforSyncWordDetection, – HardwareReal-TimeClock(RTC) AddressCheck,FlexiblePacketLength,and – TwoUniversalSerialCommunicationInterfaces AutomaticCRCHandling (USCIs) – SupportforAutomaticClearChannel – USCI_A0SupportsUART,IrDA,SPI Assessment(CCA)BeforeTransmitting(for – USCI_B0SupportsI2C,SPI Listen-Before-TalkSystems) – 12-BitAnalog-to-DigitalConverter(ADC)With – DigitalRSSIOutput InternalReference,Sample-and-Hold,and – SuitedforSystemsTargetingComplianceWith AutoscanFeatures(CC430F613xand EN300220(Europe)and CC430F513xOnly) FCCCFRPart15(US) – Comparator – SuitedforSystemsTargetingComplianceWith – IntegratedLCDDriverWithContrastControlfor WirelessM-BusStandardEN13757‑4:2005 upto96Segments(OnlyCC430F61xx) – SupportforAsynchronousandSynchronous – 128-BitAESSecurityEncryptionandDecryption SerialReceiveorTransmitModeforBackward Coprocessor CompatibilityWithExistingRadio – 32-BitHardwareMultiplier CommunicationProtocols – 3-ChannelInternalDMA • DeviceComparisonSummarizestheAvailable FamilyMembers 1.2 Applications • WirelessAnalogandDigitalSensorSystems • AMRorAMIMetering • HeatCostAllocators • SmartGridWirelessNetworks • Thermostats 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com 1.3 Description The TI CC430 family of ultra-low-power system-on-chip (SoC) microcontrollers with integrated RF transceiver cores consists of several devices that feature different sets of peripherals targeted for a wide range of applications. The architecture, combined with five low-power modes, is optimized to achieve extended battery life in portable measurement applications. The devices feature the powerful MSP430 16‑bitRISCCPU,16-bitregisters,andconstantgeneratorsthatcontributetomaximumcodeefficiency. The CC430 family provides a tight integration between the microcontroller core, its peripherals, software, andtheRFtransceiver,makingthesetrueSoCsolutionseasytouseaswellasimprovingperformance. The CC430F61xx series are microcontroller SoC configurations that combine the excellent performance of the state-of-the-art CC1101 sub-1 GHz RF transceiver with the MSP430 CPUXV2, up to 32KB of in- systemprogrammableflashmemory,upto4KBofRAM,two16-bittimers,ahigh-performance12-bitADC with eight external inputs plus internal temperature and battery sensors on CC430F613x devices, a comparator, USCIs, a 128-bit AES security accelerator, a hardware multiplier, a DMA, an RTC module withalarmcapabilities,anLCDdriver,andupto44I/Opins. TheCC430F513xseriesaremicrocontrollerSoCconfigurationsthatcombinetheexcellentperformanceof the state-of-the-art CC1101 sub-1 GHz RF transceiver with the MSP430 CPUXV2, up to 32KB of in- systemprogrammableflashmemory,upto4KBofRAM,two16-bittimers,ahigh-performance12-bitADC with six external inputs plus internal temperature and battery sensors, a comparator, USCIs, a 128-bit AES security accelerator, a hardware multiplier, a DMA, an RTC module with alarm capabilities, and up to 30I/Opins. Forcompletemoduledescriptions,seethe CC430FamilyUser'sGuide. DeviceInformation(1) PARTNUMBER PACKAGE BODYSIZE(2) CC430F6137IRGC VQFN(64) 9mm×9mm CC430F5137IRGZ VQFN(48) 7mm×7mm (1) Forthemostcurrentpart,package,andorderinginformation,seethePackageOptionAddendumin Section9,orseetheTIwebsiteatwww.ti.com. (2) Thesizesshownhereareapproximations.Forthepackagedimensionswithtolerances,seethe MechanicalDatainSection9. 2 DeviceOverview Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 1.4 Functional Block Diagrams Figure1-1showstheCC430F613xfunctionalblockdiagram. XIN XOUT P1.x,P2.x P3.x,P4.x P5.x RF_XIN RF_XOUT (32 kHz) (26 MHz) 2x8 2x8 1x8 I/O Ports I/O Ports I/O Ports MCLK Unified ACLK REF P1, P2 P3, P4 P5 2x8I/Os 2x8I/Os 1x8I/Os Packet Clock Comp_B ADC12 Voltage Handler System SMCLK Reference PA PB DMA 1x16I/Os 1x16I/Os Digital RSSI Controller Carrier Sense PQI,CA 3Channel LQI MAB Bus Control MDB Logic Sub-1 GHz CPUXV2 Radio incl. 16 (CC1101) Registers SYS Flash RAM Watchdog 32KB 4KB CRC16 MPY32 CPU Interface 16KB 2KB Port EEM Mapping (S:3+1) Controller Modem MDB JTAG Interface MAB Frequency Spy-Bi- Synthesizer Wire Power USCI_A0 LCD_B AES128 Mgmt TA0 TA1 (UART, RTC_A IrDA,SPI) 96 Security RF,Analog LDO, 5CC 3CC Segments Encryption, TX and RX SVM, SVS, Registers Registers USCI_B0 1,2,3,4 Decryption Brownout (SPI,I2C) Mux RF_P RF_N Copyright © 2017,Texas Instruments Incorporated Figure1-1.CC430F613xFunctionalBlockDiagram Copyright©2009–2018,TexasInstrumentsIncorporated DeviceOverview 3 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com Figure1-2showstheCC430F612xfunctionalblockdiagram. XIN XOUT P1.x,P2.x P3.x,P4.x P5.x RF_XIN RF_XOUT (32 kHz) (26 MHz) 2x8 2x8 1x8 I/O Ports I/O Ports I/O Ports MCLK Unified ACLK REF P1,P2 P3,P4 P5 2x8I/Os 2x8I/Os 1x8I/Os Packet Clock Comp_B Voltage Handler System SMCLK Reference PA PB DMA 1x16I/Os 1x16I/Os Digital RSSI Controller Carrier Sense PQI, LQI 3Channel CCA MAB Bus Control MDB Logic Sub-1 GHz CPUXV2 Radio incl. 16 (CC1101) Registers SYS Flash RAM Watch- 32KB 4KB CRC16 dog MPY32 CPU Interface 32KB 2KB Port EEM 16KB 2KB Mapping (S:3+1) Controller Modem MDB JTAG Interface MAB Frequency Spy-Bi- Synthesizer Wire Power USCI_A0 LCD_B AES128 Mgmt TA0 TA1 (UART, RTC_A IrDA,SPI) 96 Security RF,Analog LDO, 5CC 3CC Segments Encryption, TX and RX SVM, SVS, Registers Registers USCI_B0 1,2,3,4 Decryption Brownout (SPI,I2C) Mux RF_P RF_N Copyright © 2017,Texas Instruments Incorporated Figure1-2.CC430F612xFunctionalBlockDiagram 4 DeviceOverview Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 Figure1-3showstheCC430F513xfunctionalblockdiagram. XIN XOUT P1.x,P2.x P3.x P5.x RF_XIN RF_XOUT (32 kHz) (26 MHz) 2x8 1x8 1x2 I/O Ports I/O Ports I/O Ports MCLK Unified ACLK REF P1,P2 P3 P5 2x8I/Os 1x8I/Os 1x2I/Os Packet Clock Comp_B ADC12 Voltage Handler System SMCLK Reference PA DMA 1x16I/Os Digital RSSI Controller Carrier Sense PQI, LQI 3Channel CCA MAB Bus Control MDB Logic Sub-1 GHz CPUXV2 Radio incl. 16 (CC1101) Registers SYS Flash RAM Watchdog 32KB 4KB CRC16 MPY32 CPU Interface 16KB 2KB Port EEM 8KB Mapping (S:3+1) Controller Modem MDB JTAG Interface MAB Frequency Spy-Bi- Synthesizer Wire Power USCI_A0 AES128 Mgmt TA0 TA1 (UART, SVLMD, OS,VS, Re5g CisCters Re3g CisCters RTC_A IUrDSAC,IS_BP0I) EDnSececrrcyyupprttiitiooynn, TRXF, aAnnda RloXg Brownout (SPI, I2C) RF_P RF_N Copyright © 2017,Texas Instruments Incorporated Figure1-3.CC430F513xFunctionalBlockDiagram Copyright©2009–2018,TexasInstrumentsIncorporated DeviceOverview 5 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com 2 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromSeptember6,2013toSeptember17,2018 Page • Documentformatandorganizationchangesthroughout,includingadditionofsectionnumbering ....................... 1 • AddedDeviceInformationtable .................................................................................................... 2 • AddedSection1.4andmovedallfunctionalblockdiagramstoit.............................................................. 3 • AddedSection3,DeviceComparison,andmovedTable3-1toit............................................................. 7 • AddedSection3.1,RelatedProducts ............................................................................................. 7 • AddedSection4,TerminalConfigurationandFunctions,andmovedallpinoutsandterminalfunctionstablestoit... 8 • AddedtypicalconditionsstatementsatthebeginningofSection5,Specifications ....................................... 17 • AddedSection5,Specifications,andmovedallelectricalandtimingspecificationstoit................................. 17 • AddedSection5.2,ESDRatings.................................................................................................. 17 • ChangedtheMINvalueoftheV parameterfrom60mVto50mVinSection5.19,PMM,Brownout (DVCC_BOR_hys) Reset(BOR)......................................................................................................................... 29 • Updatednotes(1)and(2)andaddednote(3)inSection5.25,Wake-upTimesFromLow-PowerModesand Reset ................................................................................................................................. 31 • RemovedADC12DIVfromtheformulafortheTYPvalueinthesecondrowofthet parameterin CONVERT Section5.36,12-BitADC,TimingParameters(removedbecauseADC12CLKisafterdivision)......................... 39 • Forthet parameterinSection5.42,Comparator_B:Removed"CBPWRMD=10"fromtheTest EN_CMP Conditionsinthefirstrow;addedsecondrowwithTestConditionsof"CBPWRMD=10"andaMAXvalueof 100µs................................................................................................................................. 44 • Changedthetestconditions"RFcrystaloscillatoronly"andaddednoteinSection5.48,CurrentConsumption, Reduced-PowerModes ............................................................................................................ 46 • CorrectedthelinkforDN013ProgrammingOutputPoweronCC1101 ..................................................... 56 • Changedallinstancesof"bootstraploader"to"bootloader"throughoutdocument........................................ 65 • CorrectedspellingofNMIIFGinTable6-8,SystemModuleInterruptVectorRegisters................................... 70 • AddedSection8,DeviceandDocumentationSupport,andmovedDeviceNomenclature,ESDCaution,and Trademarkssectionstoit......................................................................................................... 112 • AddedSection9,Mechanical,Packaging,andOrderableInformation..................................................... 118 6 RevisionHistory Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 3 Device Comparison Table3-1summarizestheavailablefamilymembers. Table3-1.DeviceComparison(1)(2) USCI DEVICE PRO(KGBR)AM S(RKABM) Timer_A(3) LCD_B CHAAN:NEL CHABN:NEL CAHDACN1N2E_LAS CCHOAMNNPE_BLS I/O PACKAGE UART,LIN, SPI,I2C IrDA,SPI 8ext, CC430F6137 32 4 5,3 96seg 1 1 8 44 64RGC 4int 8ext, CC430F6135 16 2 5,3 96seg 1 1 8 44 64RGC 4int CC430F6127 32 4 5,3 96seg 1 1 N/A(4) 8 44 64RGC CC430F6126 32 2 5,3 96seg 1 1 N/A 8 44 64RGC CC430F6125 16 2 5,3 96seg 1 1 N/A 8 44 64RGC CC430F5137 32 4 5,3 N/A(4) 1 1 6ext, 6 30 48RGZ 4int 6ext, CC430F5135 16 2 5,3 N/A 1 1 6 30 48RGZ 4int 6ext, CC430F5133 8 2 5,3 N/A 1 1 6 30 48RGZ 4int (1) Forthemostcurrentdevice,package,andorderinginformation,seethePackageOptionAddenduminSection9,orseetheTIwebsite atwww.ti.com. (2) Packagedrawings,thermaldata,andsymbolizationareavailableatwww.ti.com/packaging. (3) EachnumberinthesequencerepresentsaninstantiationofTimer_Awithitsassociatednumberofcapture/compareregistersandPWM outputgeneratorsavailable.Forexample,anumbersequenceof5,3representstwoinstantiationsofTimer_A,thefirstinstantiation having5capture/compareregistersandPWMoutputgenerators,andthesecondinstantiationhaving3capture/compareregistersand PWMoutputgenerators,respectively. (4) N/A=notavailable 3.1 Related Products Forinformationaboutotherdevicesinthisfamilyofproductsorrelatedproducts,seethefollowinglinks. ProductsforTIMicrocontrollers TI's low-power and high-performance MCUs, with wired and wireless connectivityoptions,areoptimizedforabroadrangeofapplications. ProductsforMSP430Ultra-Low-PowerMicrocontrollers One platform. One ecosystem. Endless possibilities. Enabling the connected world with innovations in ultra-low-power microcontrollerswithadvancedperipheralsforprecisesensingandmeasurement. CompanionProductsforCC430F6137 Review products that are frequently purchased or used in conjunctionwiththisproduct. ReferenceDesignsforCC430F6137 TI Designs Reference Design Library is a robust reference design library that spans analog, embedded processor, and connectivity. Created by TI experts to help you jump start your system design, all TI Designs include schematic or block diagrams, BOMs, and design files to speed your time to market. Search and download designs at ti.com/tidesigns. Copyright©2009–2018,TexasInstrumentsIncorporated DeviceComparison 7 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com 4 Terminal Configuration and Functions 4.1 Pin Diagrams Figure4-1showsthepinoutfortheCC430F613xdevicesinthe64-pinRGCpackage. + BOUT1/PM_TA1CLK/CB0/A0 A1CCR0A/CB1/A1 A1CCR1A/CB2/A2 A1CCR2A/CB3/A3 TCCLK/CB4/A4/VREF-/VeREF- VM/CB5OUT/A5/VREF+/VeREF CLK/CB6/A6 DC12CLK/PM_DM/CB7AE0/A7 BWTDIO TCK C T T T R S A A T S W 0/PM_ 1/PM_ 2/PM_ 3/PM_ 4/PM_ 5/PM_ 6/PM_ 7/PM_ CC 0/XIN 1/XOU SS CC T/NMI/ ST/SB 3/TCK 2. 2. 2. 2. 2. 2. 2. 2. V 5. 5. V V S E J. P P P P P P P P A P P A D R T P 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 P1.7/PM_UCA0CLK/PM_UCB0STE/R03 1 48 PJ.2/TMS P1.6/PM_UCA0TXD/PM_UCA0SIMO/R13/LCDREF 2 47 PJ.1/TDI/TCLK P1.5/PM_UCA0RXD/PM_UCA0SOMI/R23 3 46 PJ.0/TDO LCDCAP/R33 4 45 GUARD COM0 5 44 R_BIAS P5.7/COM1/S26 6 43 AVCC_RF P5.6/COM2/S25 7 42 AVCC_RF P5.5/COM3/S24 8 41 RF_N CC430F613x P5.4/S23 9 40 RF_P VCORE 10 39 AVCC_RF DVCC 11 38 AVCC_RF P1.4/PM_UCB0CLK/PM_UCA0STE/S22 12 37 RF_XOUT P1.3/PM_UCB0SIMO/PM_UCB0SDA/S21 13 36 RF_XIN P1.2/PM_UCB0SOMI/PM_UCB0SCL/S20 14 35 P5.2/S0 P1.1/PM_RFGDO2/S19 15 34 P5.3/S1 P1.0/PM_RFGDO0/S18 16 33 P4.0/S2 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 7 6 5 4 3 2 1 0 C 9 8 7 6 5 4 3 MCLK/S1 GDO1/S1 CR4A/S1 CR3A/S1 CR2A/S1 CR1A/S1 CR0A/S1 0CLK/S1 DVC P4.7/S P4.6/S P4.5/S P4.4/S P4.3/S P4.2/S P4.1/S VESxpSosed die 3.7/PM_S 6/PM_RF PM_TA0C PM_TA0C PM_TA0C PM_TA0C PM_TA0C T0/PM_TA attached pad P 3. 5/ 4/ 3/ 2/ 1/ U P P3. P3. P3. P3. P3. BO C _ M P 0/ 3. P CAUTION: TheLCDCAP/R33mustbeconnectedtoVSSifnotused. NOTE: The secondary digital functions on ports P1, P2, and P3 are fully mappable. This pinout shows only the default mapping.SeeTable6-6fordetails. Figure4-1.64-PinRGCPackage(TopView),CC430F613x 8 TerminalConfigurationandFunctions Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 Figure4-2showsthepinoutfortheCC430F612xdevicesinthe64-pinRGCpackage. 0 B C K/ L C 1 BOUT1/PM_TA A1CCR0A/CB1 A1CCR1A/CB2 A1CCR2A/CB3 TCCLK/CB4 VMOU/CB5T CLK/CB6 /MAE0CB7 BWTDIO TCK C T T T R S A D T S W 0/PM_ 1/PM_ 2/PM_ 3/PM_ 4/PM_ 5/PM_ 6/PM_ 7/PM_ CC 0/XIN 1/XOU SS CC T/NMI/ ST/SB 3/TCK 2. 2. 2. 2. 2. 2. 2. 2. V 5. 5. V V S E J. P P P P P P P P A P P A D R T P 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 P1.7/PM_UCA0CLK/PM_UCB0STE/R03 1 48 PJ.2/TMS P1.6/PM_UCA0TXD/PM_UCA0SIMO/R13/LCDREF 2 47 PJ.1/TDI/TCLK P1.5/PM_UCA0RXD/PM_UCA0SOMI/R23 3 46 PJ.0/TDO LCDCAP/R33 4 45 GUARD COM0 5 44 R_BIAS P5.7/COM1/S26 6 43 AVCC_RF P5.6/COM2/S25 7 42 AVCC_RF P5.5/COM3/S24 8 41 RF_N CC430F612x P5.4/S23 9 40 RF_P VCORE 10 39 AVCC_RF DVCC 11 38 AVCC_RF P1.4/PM_UCB0CLK/PM_UCA0STE/S22 12 37 RF_XOUT P1.3/PM_UCB0SIMO/PM_UCB0SDA/S21 13 36 RF_XIN P1.2/PM_UCB0SOMI/PM_UCB0SCL/S20 14 35 P5.2/S0 P1.1/PM_RFGDO2/S19 15 34 P5.3/S1 P1.0/PM_RFGDO0/S18 16 33 P4.0/S2 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 7 6 5 4 3 2 1 0 C 9 8 7 6 5 4 3 CLK/S1 DO1/S1 R4A/S1 R3A/S1 R2A/S1 R1A/S1 R0A/S1 CLK/S1 DVC P4.7/S P4.6/S P4.5/S P4.4/S P4.3/S P4.2/S P4.1/S VESxpSosed die M G C C C C C 0 attached pad 3.7/PM_S 6/PM_RF PM_TA0C PM_TA0C PM_TA0C PM_TA0C PM_TA0C T0/PM_TA P 3. 5/ 4/ 3/ 2/ 1/ U P P3. P3. P3. P3. P3. BO C _ M P 0/ 3. P CAUTION: TheLCDCAP/R33mustbeconnectedtoVSSifnotused. NOTE: The secondary digital functions on ports P1, P2, and P3 are fully mappable. This pinout shows only the default mapping.SeeTable6-6fordetails. Figure4-2.64-PinRGCPackage(TopView),CC430F612x Copyright©2009–2018,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 9 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com Figure4-3showsthepinoutfortheCC430F513xdevicesinthe48-pinRGZpackage. + F- EF E R R e e V REF-/V REF+/ 1CCR2A/CB3/A3 CCLK/CB4/A4/V MOUT/CB5/A5/V WTDIO CK A T V B T T R S T S W 3/PM_ 4/PM_ 5/PM_ CC 0/XIN 1/XOU SS CC T/NMI/ ST/SB 3/TCK 2/TMS 2. 2. 2. V 5. 5. V V S E J. J. P P P A P P A D R T P P 48 47 46 45 44 43 42 41 40 39 38 37 P2.2/PM_TA1CCR1A/CB2/A2 1 36 PJ.1/TDI/TCLK P2.1/PM_TA1CCR0A/CB1/A1 2 35 PJ.0/TDO P2.0/PM_CBOUT1/PM_TA1CLK/CB0/A0 3 34 GUARD P1.7/PM_UCA0CLK/PM_UCB0STE 4 33 R_BIAS P1.6/PM_UCA0TXD/PM_UCA0SIMO 5 32 AVCC_RF P1.5/PM_UCA0RXD/PM_UCA0SOMI 6 31 AVCC_RF CC430F513x VCORE 7 30 RF_N DVCC 8 29 RF_P P1.4/PM_UCB0CLK/PM_UCA0STE 9 28 AVCC_RF P1.3/PM_UCB0SIMO/PM_UCB0SDA 10 27 AVCC_RF P1.2/PM_UCB0SOMI/PM_UCB0SCL 11 26 RF_XOUT P1.1/PM_RFGDO2 12 25 RF_XIN 13 14 15 16 17 18 19 20 21 22 23 24 0 K 1 A A A A A K C 0 K O L O 4 3 2 1 0 L C E L D C D R R R R R C V A C G M G C C C C C 0 D M A VSS 0/PM_RF 3.7/PM_S 6/PM_RF PM_TA0C PM_TA0C PM_TA0C PM_TA0C PM_TA0C T0/PM_TA LK/PM_D P2.6/PM_ Eatxtapcohseedd pdaied P1. P P3. 3.5/ 3.4/ 3.3/ 3.2/ 3.1/ OU 12C P P P P P B C C D _ A M _ P M 0/ P 3. 7/ P 2. P NOTE: The secondary digital functions on ports P1, P2, and P3 are fully mappable. This pinout shows only the default mapping.SeeTable6-6fordetails. Figure4-3.48-PinRGZPackage(TopView),CC430F513x 10 TerminalConfigurationandFunctions Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 4.2 Signal Descriptions Table 4-1 describes the signals for the CC430F613x and CC430F612x devices. See Table 4-2 for the CC430F513xdevices. Table4-1.CC430F613xandCC430F612xTerminalFunctions TERMINAL I/O(1) DESCRIPTION NAME NO. General-purposedigitalI/Owithportinterruptandmappablesecondaryfunction P1.7/PM_UCA0CLK/ 1 I/O Defaultmapping:USCI_A0clockinput/output;USCI_B0SPIslavetransmitenable PM_UCB0STE/R03 Input/outputportoflowestanalogLCDvoltage(V5) General-purposedigitalI/Owithportinterruptandmappablesecondaryfunction P1.6/PM_UCA0TXD/ Defaultmapping:USCI_A0UARTtransmitdata;USCI_A0SPIslaveinmasterout 2 I/O PM_UCA0SIMO/R13/LCDREF Input/outputportofthirdmostpositiveanalogLCDvoltage(V3orV4) ExternalreferencevoltageinputforregulatedLCDvoltage General-purposedigitalI/Owithportinterruptandmappablesecondaryfunction P1.5/PM_UCA0RXD/ 3 I/O Defaultmapping:USCI_A0UARTreceivedata;USCI_A0SPIslaveoutmasterin PM_UCA0SOMI/R23 Input/outputportofsecondmostpositiveanalogLCDvoltage(V2) LCDcapacitorconnection LCDCAP/R33 4 I/O Input/outputportofmostpositiveanalogLCDvoltage(V1) CAUTION:MustbeconnectedtoVSSifnotused. COM0 5 O LCDcommonoutputCOM0forLCDbackplane General-purposedigitalI/O P5.7/COM1/S26 6 I/O LCDcommonoutputCOM1forLCDbackplane LCDsegmentoutputS26 General-purposedigitalI/O P5.6/COM2/S25 7 I/O LCDcommonoutputCOM2forLCDbackplane LCDsegmentoutputS25 General-purposedigitalI/O P5.5/COM3/S24 8 I/O LCDcommonoutputCOM3forLCDbackplane LCDsegmentoutputS24 General-purposedigitalI/O P5.4/S23 9 I/O LCDsegmentoutputS23 VCORE 10 Regulatedcorepowersupply DVCC 11 Digitalpowersupply General-purposedigitalI/Owithportinterruptandmappablesecondaryfunction P1.4/PM_UCB0CLK/ Defaultmapping:USCI_B0clockinput/output 12 I/O PM_UCA0STE/S22 Defaultmapping:USCI_A0SPIslavetransmitenable LCDsegmentoutputS22 General-purposedigitalI/Owithportinterruptandmappablesecondaryfunction P1.3/PM_UCB0SIMO/ Defaultmapping:USCI_B0SPIslaveinmasterout PM_UCB0SDA/S21 13 I/O Defaultmapping:USCI_B0I2Cdata LCDsegmentoutputS21 General-purposedigitalI/Owithportinterruptandmappablesecondaryfunction P1.2/PM_UCB0SOMI/ Defaultmapping:USCI_B0SPIslaveoutmasterin PM_UCB0SCL/S20 14 I/O Defaultmapping:UCSI_B0I2Cclock LCDsegmentoutputS20 General-purposedigitalI/Owithportinterruptandmappablesecondaryfunction P1.1/PM_RFGDO2/S19 15 I/O Defaultmapping:RadioGDO2output LCDsegmentoutputS19 General-purposedigitalI/Owithportinterruptandmappablesecondaryfunction P1.0/PM_RFGDO0/S18 16 I/O Defaultmapping:RadioGDO0output LCDsegmentoutputS18 General-purposedigitalI/Owithmappablesecondaryfunction P3.7/PM_SMCLK/S17 17 I/O Defaultmapping:SMCLKoutput LCDsegmentoutputS17 General-purposedigitalI/Owithmappablesecondaryfunction P3.6/PM_RFGDO1/S16 18 I/O Defaultmapping:RadioGDO1output LCDsegmentoutputS16 (1) I=input,O=output Copyright©2009–2018,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 11 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com Table4-1.CC430F613xandCC430F612xTerminalFunctions(continued) TERMINAL I/O(1) DESCRIPTION NAME NO. General-purposedigitalI/Owithmappablesecondaryfunction P3.5/PM_TA0CCR4A/S15 19 I/O Defaultmapping:TA0CCR4compareoutputorcaptureinput LCDsegmentoutputS15 General-purposedigitalI/Owithmappablesecondaryfunction P3.4/PM_TA0CCR3A/S14 20 I/O Defaultmapping:TA0CCR3compareoutputorcaptureinput LCDsegmentoutputS14 General-purposedigitalI/Owithmappablesecondaryfunction P3.3/PM_TA0CCR2A/S13 21 I/O Defaultmapping:TA0CCR2compareoutputorcaptureinput LCDsegmentoutputS13 General-purposedigitalI/Owithmappablesecondaryfunction P3.2/PM_TA0CCR1A/S12 22 I/O Defaultmapping:TA0CCR1compareoutputorcaptureinput LCDsegmentoutputS12 General-purposedigitalI/Owithmappablesecondaryfunction P3.1/PM_TA0CCR0A/S11 23 I/O Defaultmapping:TA0CCR0compareoutputorcaptureinput LCDsegmentoutputS11 General-purposedigitalI/Owithmappablesecondaryfunction P3.0/PM_CBOUT0/PM_TA0CLK/ Defaultmapping:Comparator_Boutput 24 I/O S10 Defaultmapping:TA0clockinput LCDsegmentoutputS10 DVCC 25 Digitalpowersupply General-purposedigitalI/O P4.7/S9 26 I/O LCDsegmentoutputS9 General-purposedigitalI/O P4.6/S8 27 I/O LCDsegmentoutputS8 General-purposedigitalI/O P4.5/S7 28 I/O LCDsegmentoutputS7 General-purposedigitalI/O P4.4/S6 29 I/O LCDsegmentoutputS6 General-purposedigitalI/O P4.3/S5 30 I/O LCDsegmentoutputS5 General-purposedigitalI/O P4.2/S4 31 I/O LCDsegmentoutputS4 General-purposedigitalI/O P4.1/S3 32 I/O LCDsegmentoutputS3 General-purposedigitalI/O P4.0/S2 33 I/O LCDsegmentoutputS2 General-purposedigitalI/O P5.3/S1 34 I/O LCDsegmentoutputS1 General-purposedigitalI/O P5.2/S0 35 I/O LCDsegmentoutputS0 RF_XIN 36 I InputterminalforRFcrystaloscillator,orexternalclockinput RF_XOUT 37 O OutputterminalforRFcrystaloscillator AVCC_RF 38 Radioanalogpowersupply AVCC_RF 39 Radioanalogpowersupply RF PositiveRFinputtoLNAinreceivemode RF_P 40 I/O PositiveRFoutputfromPAintransmitmode RF NegativeRFinputtoLNAinreceivemode RF_N 41 I/O NegativeRFoutputfromPAintransmitmode AVCC_RF 42 Radioanalogpowersupply AVCC_RF 43 Radioanalogpowersupply RBIAS 44 Externalbiasresistorforradioreferencecurrent GUARD 45 Powersupplyconnectionfordigitalnoiseisolation General-purposedigitalI/O PJ.0/TDO 46 I/O Testdataoutputport 12 TerminalConfigurationandFunctions Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 Table4-1.CC430F613xandCC430F612xTerminalFunctions(continued) TERMINAL I/O(1) DESCRIPTION NAME NO. General-purposedigitalI/O PJ.1/TDI/TCLK 47 I/O Testdatainputortestclockinput General-purposedigitalI/O PJ.2/TMS 48 I/O Testmodeselect General-purposedigitalI/O PJ.3/TCK 49 I/O Testclock Testmodepin–selectdigitalI/OonJTAGpins TEST/SBWTCK 50 I Spy-Bi-Wireinputclock Resetinputactivelow RST/NMI/SBWTDIO 51 I/O Nonmaskableinterruptinput Spy-Bi-Wiredatainput/output DVCC 52 Digitalpowersupply AVSS 53 AnaloggroundsupplyforADC12 General-purposedigitalI/O P5.1/XOUT 54 I/O OutputterminalofcrystaloscillatorXT1 General-purposedigitalI/O P5.0/XIN 55 I/O InputterminalforcrystaloscillatorXT1 AVCC 56 Analogpowersupply General-purposedigitalI/Owithportinterruptandmappablesecondaryfunction Defaultmapping:ADC12CLKoutput P2.7/PM_ADC12CLK/ 57 I/O Defaultmapping:DMAexternaltriggerinput PM_DMAE0/CB7(/A7) Comparator_BinputCB7 AnaloginputA7–12-bitADC(CC430F613xonly) General-purposedigitalI/Owithportinterruptandmappablesecondaryfunction Defaultmapping:ACLKoutput P2.6/PM_ACLK/CB6(/A6) 58 I/O Comparator_BinputCB6 AnaloginputA6–12-bitADC(CC430F613xonly) General-purposedigitalI/Owithportinterruptandmappablesecondaryfunction Defaultmapping:SVMoutput P2.5/PM_SVMOUT/CB5 Comparator_BinputCB5 59 I/O (/A5/VREF+/VeREF+) AnaloginputA5–12-bitADC(CC430F613xonly) OutputofreferencevoltagetotheADC(CC430F613xonly) InputforanexternalreferencevoltagetotheADC(CC430F613xonly) General-purposedigitalI/Owithportinterruptandmappablesecondaryfunction Defaultmapping:RTCCLKoutput P2.4/PM_RTCCLK/CB4 Comparator_BinputCB4 60 I/O (/A4/VREF-/VeREF-) AnaloginputA4–12-bitADC(CC430F613xonly) NegativeterminalfortheADCreferencevoltageforbothsources,theinternalreference voltage,oranexternalappliedreferencevoltage(CC430F613xonly) General-purposedigitalI/Owithportinterruptandmappablesecondaryfunction Defaultmapping:TA1CCR2compareoutputorcaptureinput P2.3/PM_TA1CCR2A/CB3(/A3) 61 I/O Comparator_BinputCB3 AnaloginputA3–12-bitADC(CC430F613xonly) General-purposedigitalI/Owithportinterruptandmappablesecondaryfunction Defaultmapping:TA1CCR1compareoutputorcaptureinput P2.2/PM_TA1CCR1A/CB2(/A2) 62 I/O Comparator_BinputCB2 AnaloginputA2–12-bitADC(CC430F613xonly) General-purposedigitalI/Owithportinterruptandmappablesecondaryfunction Defaultmapping:TA1CCR0compareoutputorcaptureinput P2.1/PM_TA1CCR0A/CB1(/A1) 63 I/O Comparator_BinputCB1 AnaloginputA1–12-bitADC(CC430F613xonly) General-purposedigitalI/Owithportinterruptandmappablesecondaryfunction Defaultmapping:Comparator_Boutput P2.0/PM_CBOUT1/PM_TA1CLK/ 64 I/O Defaultmapping:TA1clockinput CB0(/A0) Comparator_BinputCB0 AnaloginputA0–12-bitADC(CC430F613xonly) Groundsupply VSS,Exposeddieattachpad CAUTION:Theexposeddieattachpadmustbeconnectedtoasolidgroundplaneas thisisthegroundconnectionforthechip. Copyright©2009–2018,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 13 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com Table 4-2 describes the signals for the CC430F513x devices. See Table 4-1 for the CC430F613x and CC430F612xdevices. Table4-2.CC430F513xTerminalFunctions TERMINAL I/O(1) DESCRIPTION NAME NO. General-purposedigitalI/Owithportinterruptandmappablesecondaryfunction Defaultmapping:TA1CCR1compareoutputorcaptureinput P2.2/PM_TA1CCR1A/CB2/A2 1 I/O Comparator_BinputCB2 AnaloginputA2–12-bitADC General-purposedigitalI/Owithportinterruptandmappablesecondaryfunction Defaultmapping:TA1CCR0compareoutputorcaptureinput P2.1/PM_TA1CCR0A/CB1/A1 2 I/O Comparator_BinputCB1 AnaloginputA1–12-bitADC General-purposedigitalI/Owithportinterruptandmappablesecondaryfunction Defaultmapping:Comparator_Boutput P2.0/PM_CBOUT1/PM_TA1CLK/ 3 I/O Defaultmapping:TA1clockinput CB0/A0 Comparator_BinputCB0 AnaloginputA0–12-bitADC General-purposedigitalI/Owithportinterruptandmappablesecondaryfunction P1.7/PM_UCA0CLK/ 4 I/O Defaultmapping:USCI_A0clockinput/output PM_UCB0STE Defaultmapping:USCI_B0SPIslavetransmitenable P1.6/PM_UCA0TXD/ General-purposedigitalI/Owithportinterruptandmappablesecondaryfunction 5 I/O PM_UCA0SIMO Defaultmapping:USCI_A0UARTtransmitdata;USCI_A0SPIslaveinmasterout General-purposedigitalI/Owithportinterruptandmappablesecondaryfunction P1.5/PM_UCA0RXD/ 6 I/O Defaultmapping:USCI_A0UARTreceivedata PM_UCA0SOMI Defaultmapping:USCI_A0SPIslaveoutmasterin VCORE 7 Regulatedcorepowersupply DVCC 8 Digitalpowersupply General-purposedigitalI/Owithportinterruptandmappablesecondaryfunction P1.4/PM_UCB0CLK/ 9 I/O Defaultmapping:USCI_B0clockinput/output PM_UCA0STE Defaultmapping:USCI_A0SPIslavetransmitenable General-purposedigitalI/Owithportinterruptandmappablesecondaryfunction P1.3/PM_UCB0SIMO/ 10 I/O Defaultmapping:USCI_B0SPIslaveinmasterout PM_UCB0SDA Defaultmapping:USCI_B0I2Cdata General-purposedigitalI/Owithportinterruptandmappablesecondaryfunction P1.2/PM_UCB0SOMI/ 11 I/O Defaultmapping:USCI_B0SPIslaveoutmasterin PM_UCB0SCL Defaultmapping:UCSI_B0I2Cclock General-purposedigitalI/Owithportinterruptandmappablesecondaryfunction P1.1/PM_RFGDO2 12 I/O Defaultmapping:RadioGDO2output General-purposedigitalI/Owithportinterruptandmappablesecondaryfunction P1.0/PM_RFGDO0 13 I/O Defaultmapping:RadioGDO0output General-purposedigitalI/Owithmappablesecondaryfunction P3.7/PM_SMCLK 14 I/O Defaultmapping:SMCLKoutput General-purposedigitalI/Owithmappablesecondaryfunction P3.6/PM_RFGDO1 15 I/O Defaultmapping:RadioGDO1output General-purposedigitalI/Owithmappablesecondaryfunction P3.5/PM_TA0CCR4A 16 I/O Defaultmapping:TA0CCR4compareoutputorcaptureinput General-purposedigitalI/Owithmappablesecondaryfunction P3.4/PM_TA0CCR3A 17 I/O Defaultmapping:TA0CCR3compareoutputorcaptureinput General-purposedigitalI/Owithmappablesecondaryfunction P3.3/PM_TA0CCR2A 18 I/O Defaultmapping:TA0CCR2compareoutputorcaptureinput General-purposedigitalI/Owithmappablesecondaryfunction P3.2/PM_TA0CCR1A 19 I/O Defaultmapping:TA0CCR1compareoutputorcaptureinput General-purposedigitalI/Owithmappablesecondaryfunction P3.1/PM_TA0CCR0A 20 I/O Defaultmapping:TA0CCR0compareoutputorcaptureinput General-purposedigitalI/Owithmappablesecondaryfunction P3.0/PM_CBOUT0/PM_TA0CLK 21 I/O Defaultmapping:Comparator_Boutput Defaultmapping:TA0clockinput (1) I=input,O=output 14 TerminalConfigurationandFunctions Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 Table4-2.CC430F513xTerminalFunctions(continued) TERMINAL I/O(1) DESCRIPTION NAME NO. DVCC 22 Digitalpowersupply General-purposedigitalI/Owithportinterruptandmappablesecondaryfunction P2.7/PM_ADC12CLK/ 23 I/O Defaultmapping:ADC12CLKoutput PM_DMAE0 Defaultmapping:DMAexternaltriggerinput General-purposedigitalI/Owithportinterruptandmappablesecondaryfunction P2.6/PM_ACLK 24 I/O Defaultmapping:ACLKoutput RF_XIN 25 I InputterminalforRFcrystaloscillator,orexternalclockinput RF_XOUT 26 O OutputterminalforRFcrystaloscillator AVCC_RF 27 Radioanalogpowersupply AVCC_RF 28 Radioanalogpowersupply RF PositiveRFinputtoLNAinreceivemode RF_P 29 I/O PositiveRFoutputfromPAintransmitmode RF NegativeRFinputtoLNAinreceivemode RF_N 30 I/O NegativeRFoutputfromPAintransmitmode AVCC_RF 31 Radioanalogpowersupply AVCC_RF 32 Radioanalogpowersupply RBIAS 33 Externalbiasresistorforradioreferencecurrent GUARD 34 Powersupplyconnectionfordigitalnoiseisolation General-purposedigitalI/O PJ.0/TDO 35 I/O Testdataoutputport General-purposedigitalI/O PJ.1/TDI/TCLK 36 I/O Testdatainputortestclockinput General-purposedigitalI/O PJ.2/TMS 37 I/O Testmodeselect General-purposedigitalI/O PJ.3/TCK 38 I/O Testclock Testmodepin–selectdigitalI/OonJTAGpins TEST/SBWTCK 39 I Spy-Bi-Wireinputclock Resetinputactivelow RST/NMI/SBWTDIO 40 I/O Nonmaskableinterruptinput Spy-Bi-Wiredatainput/output DVCC 41 Digitalpowersupply AVSS 42 AnaloggroundsupplyforADC12 General-purposedigitalI/O P5.1/XOUT 43 I/O OutputterminalofcrystaloscillatorXT1 General-purposedigitalI/O P5.0/XIN 44 I/O InputterminalforcrystaloscillatorXT1 AVCC 45 Analogpowersupply General-purposedigitalI/Owithportinterruptandmappablesecondaryfunction Defaultmapping:SVMoutput P2.5/PM_SVMOUT/CB5/ Comparator_BinputCB5 46 I/O A5/VREF+/VeREF+ AnaloginputA5–12-bitADC OutputofreferencevoltagetotheADC InputforanexternalreferencevoltagetotheADC General-purposedigitalI/Owithportinterruptandmappablesecondaryfunction Defaultmapping:RTCCLKoutput P2.4/PM_RTCCLK/CB4/ Comparator_BinputCB4 47 I/O A4/VREF-/VeREF- AnaloginputA4–12-bitADC NegativeterminalfortheADCreferencevoltageforbothsources,theinternalreference voltage,oranexternalappliedreferencevoltage General-purposedigitalI/Owithportinterruptandmappablesecondaryfunction Defaultmapping:TA1CCR2compareoutputorcaptureinput P2.3/PM_TA1CCR2A/CB3/A3 48 I/O Comparator_BinputCB3 AnaloginputA3–12-bitADC Copyright©2009–2018,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 15 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com Table4-2.CC430F513xTerminalFunctions(continued) TERMINAL I/O(1) DESCRIPTION NAME NO. Groundsupply VSS,Exposeddieattachpad Theexposeddieattachpadmustbeconnectedtoasolidgroundplaneasthisis thegroundconnectionforthechip. 16 TerminalConfigurationandFunctions Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 5 Specifications Allgraphsinthissectionarefortypicalconditions,unlessotherwisenoted. Typical(TYP)valuesarespecifiedatV =3.3VandT =25°C,unlessotherwisenoted. CC A 5.1 Absolute Maximum Ratings(1) overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN MAX UNIT VoltageappliedatDVCCandAVCCpinstoV –0.3 4.1 V SS Voltageappliedtoanypin(excludingVCORE,RF_P,RF_N,andR_BIAS)(2) –0.3 VCC+0.3 V (4.1VMaximum) VoltageappliedtoVCORE,RF_P,RF_N,andR_BIAS(2) –0.3 2.0 V InputRFlevelatpinsRF_PandRF_N 10 dBm Diodecurrentatanydeviceterminal ±2 mA Storagetemperature,T (3) –55 150 °C stg Maximumjunctiontemperature,T 95 °C J (1) StressesbeyondthoselistedunderAbsoluteMaximumRatingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderRecommendedOperating Conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) AllvoltagesreferencedtoV . SS (3) HighertemperaturemaybeappliedduringboardsolderingaccordingtothecurrentJEDECJ-STD-020specificationwithpeakreflow temperaturesnothigherthanclassifiedonthedevicelabelontheshippingboxesorreels. 5.2 ESD Ratings VALUE UNIT Human-bodymodel(HBM),perANSI/ESDA/JEDECJS-001(1) ±1000 V Electrostaticdischarge V (ESD) Charged-devicemodel(CDM),perJEDECspecificationJESD22-C101(2) ±250 (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess.Pinslistedas ±1000Vmayactuallyhavehigherperformance. (2) JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess.Pinslistedas±250V mayactuallyhavehigherperformance. 5.3 Recommended Operating Conditions MIN NOM MAX UNIT SupplyvoltagerangeappliedatallDVCCand PMMCOREVx=0 AVCCpins(1)duringprogramexecutionand (defaultafterPOR) 1.8 3.6 flashprogrammingwithPMMdefaultsettings, RadioisnotoperationalwithPMMCOREVx=0 PMMCOREVx=1 2.0 3.6 or1(2)(3) SupplyvoltagerangeappliedatallDVCCand PMMCOREVx=2 2.2 3.6 AVCCpins(1)duringprogramexecution,flash VCC programming,andradiooperationwithPMM PMMCOREVx=3 2.4 3.6 V defaultsettings(2)(3) SupplyvoltagerangeappliedatallDVCCand AVCCpins(1)duringprogramexecution,flash PMMCOREVx=2, programmingandradiooperationwith SVSHRVLx=SVSHRRRLx=1 2.0 3.6 PMMCOREVx=2,high-sideSVSlevellowered orSVSHE=0 (SVSHRVL=SVSMHRRL=1)orhigh-sideSVS disabled(SVSHE=0)(2)(3)(4) V SupplyvoltageappliedattheexposeddieattachVSSandAVSSpin 0 V SS T Operatingfree-airtemperature –40 85 °C A (1) TIrecommendspoweringAVCCandDVCCfromthesamesource.Amaximumdifferenceof0.3VbetweenAVCCandDVCCcanbe toleratedduringpowerupandoperation. (2) Modulesmayhaveadifferentsupplyvoltagerangespecification.Seethespecificationoftherespectivemoduleinthisdatasheet. (3) TheminimumsupplyvoltageisdefinedbythesupervisorSVSlevelswhenitisenabled.SeetheSection5.21thresholdparametersfor theexactvaluesandfurtherdetails. (4) Loweringthehigh-sideSVSlevelordisablingthehigh-sideSVSmightcausetheLDOtooperateoutofregulation,butthecorevoltage willstillstaywithinitslimitsandisstillsupervisedbythelow-sideSVS,ensuringreliableoperation. Copyright©2009–2018,TexasInstrumentsIncorporated Specifications 17 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com Recommended Operating Conditions (continued) MIN NOM MAX UNIT T Operatingjunctiontemperature –40 85 °C J C RecommendedcapacitoratVCORE(5) 470 nF VCORE C / DVCC CapacitorratioofcapacitoratDVCCtocapacitoratVCORE 10 C VCORE PMMCOREVx=0 0 8 (defaultcondition) f Processor(MCLK)frequency(6)(seeFigure5-1) PMMCOREVx=1 0 12 MHz SYSTEM PMMCOREVx=2 0 16 PMMCOREVx=3 0 20 P Internalpowerdissipation V ×I W INT CC DVCC (V –V )× P I/OpowerdissipationofI/OpinspoweredbyDVCC CC IOH W IO I +V ×I IOH IOL IOL P Maximumallowedpowerdissipation,P >P +P (T –T )/θ W MAX MAX IO INT J A JA (5) Acapacitortoleranceof±20%orbetterisrequired. (6) Modulesmayhaveadifferentmaximuminputclockspecification.Seethespecificationoftherespectivemoduleinthisdatasheet. 20 z 3 H M y - 16 c en 2 2, 3 u q e Fr 12 m e 1 1, 2 1, 2, 3 st y S 8 0 0, 1 0, 1, 2 0, 1, 2, 3 0 1.8 2.0 2.2 2.4 3.6 Supply Voltage - V NOTE:The numbers within the fields are the supported PMMCOREVx settings. Figure5-1.MaximumSystemFrequency 18 Specifications Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 5.4 Active Mode Supply Current Into V Excluding External Current CC overrecommendedoperatingfree-airtemperature(unlessotherwisenoted)(1) (2) (3) FREQUENCY(fDCO=fMCLK=fSMCLK) EXECUTION PARAMETER MEMORY VCC PMMCOREVx 1MHz 8MHz 12MHz 16MHz 20MHz UNIT TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX 0 0.23 0.26 1.35 1.60 1 0.25 0.28 1.55 2.30 2.65 IAM,Flash(4) Flash 3V mA 2 0.27 0.30 1.75 2.60 3.45 3.90 3 0.28 0.32 1.85 2.75 3.65 4.55 5.10 0 0.18 0.20 0.95 1.10 1 0.20 0.22 1.10 1.60 1.85 IAM,RAM(5) RAM 3V mA 2 0.21 0.24 1.20 1.80 2.40 2.70 3 0.22 0.25 1.30 1.90 2.50 3.10 3.60 (1) Allinputsaretiedto0VortoV .Outputsdonotsourceorsinkanycurrent. CC (2) ThecurrentsarecharacterizedwithaMicroCrystalMS1V-T1Kcrystalwithaloadcapacitanceof12.5pF.Theinternalandexternalload capacitancearechosentocloselymatchtherequired12.5pF. (3) Characterizedwithprogramexecutingtypicaldataprocessing. f =32786Hz,f = f =f atspecifiedfrequency. ACLK DCO MCLK SMCLK XTS=CPUOFF=SCG0=SCG1=OSCOFF=SMCLKOFF=0. (4) Activemodesupplycurrentwhenprogramexecutesinflashatanominalsupplyvoltageof3V. (5) ActivemodesupplycurrentwhenprogramexecutesinRAMatanominalsupplyvoltageof3V. 5.5 Typical Characteristics – Active Mode Supply Currents 5 V = 3.0 V CC PMMVCOREx = 3 A m 4 – nt e urr C y 3 pl p PMMVCOREx = 2 u S e od 2 M e PMMVCOREx = 1 v cti A – 1 IAM PMMVCOREx = 0 0 0 5 10 15 20 MCLK Frequency–MHz Figure5-2. ActiveModeSupplyCurrentvsMCLKFrequency Copyright©2009–2018,TexasInstrumentsIncorporated Specifications 19 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com 5.6 Low-Power Mode Supply Currents (Into V ) Excluding External Current CC overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)(1) (2) TEMPERATURE(TA) PARAMETER VCC PMMCOREVx –40°C 25°C 60°C 85°C UNIT TYP MAX TYP MAX TYP MAX TYP MAX 2.2V 0 80 100 80 100 80 100 80 100 ILPM0,1MHz Low-powermode0(3)(4) µA 3V 3 90 110 90 110 90 110 90 110 2.2V 0 6.5 11 6.5 11 6.5 11 6.5 11 ILPM2 Low-powermode2(5)(4) µA 3V 3 7.5 12 7.5 12 7.5 12 7.5 12 0 1.8 2.0 2.6 3.0 4.0 4.4 5.9 Low-powermode3,crystal 1 1.9 2.1 3.2 4.8 ILPM3,XT1LF mode(6)(4) 3V 2 2.0 2.2 3.4 5.1 µA 3 2.0 2.2 2.9 3.5 4.8 5.3 7.4 0 0.9 1.1 2.3 2.1 3.7 3.5 5.6 Low-powermode3, 1 1.0 1.2 2.3 3.9 ILPM3,VLO VLOmode(7)(4) 3V 2 1.1 1.3 2.5 4.2 µA 3 1.1 1.3 2.6 2.6 4.5 4.4 7.1 0 0.8 1.0 2.2 2.0 3.6 3.4 5.5 1 0.9 1.1 2.2 3.8 ILPM4 Low-powermode4(8)(4) 3V µA 2 1.0 1.2 2.4 4.1 3 1.0 1.2 2.5 2.5 4.4 4.3 7.0 (1) Allinputsaretiedto0VortoV .Outputsdonotsourceorsinkanycurrent. CC (2) ThecurrentsarecharacterizedwithaMicroCrystalMS1V-T1Kcrystalwithaloadcapacitanceof12.5pF.Theinternalandexternalload capacitancearechosentocloselymatchtherequired12.5pF. (3) CurrentforwatchdogtimerclockedbySMCLKincluded.ACLK=lowfrequencycrystaloperation(XTS=0,XT1DRIVEx=0). CPUOFF=1,SCG0=0,SCG1=0,OSCOFF=0(LPM0),f =32768Hz,f =0MHz,f =f =1MHz ACLK MCLK SMCLK DCO (4) Currentforbrownout,high-sidesupervisor(SVS )normalmodeincluded.Low-sidesupervisor(SVS )andlow-sidemonitor(SVM ) H L L disabled.High-sidemonitor(SVM )disabled.RAMretentionenabled. H (5) CurrentforwatchdogtimerandRTCclockedbyACLKincluded.ACLK=lowfrequencycrystaloperation(XTS=0,XT1DRIVEx=0). CPUOFF=1,SCG0=0,SCG1=1,OSCOFF=0(LPM2),f =32768Hz,f =0MHz,f =f =0MHz,DCOsetting= ACLK MCLK SMCLK DCO 1MHzoperation,DCObiasgeneratorenabled. (6) CurrentforwatchdogtimerandRTCclockedbyACLKincluded.ACLK=lowfrequencycrystaloperation(XTS=0,XT1DRIVEx=0). CPUOFF=1,SCG0=1,SCG1=1,OSCOFF=0(LPM3),f =32768Hz,f = f =f =0MHz ACLK MCLK SMCLK DCO (7) CurrentforwatchdogtimerandRTCclockedbyACLKincluded.ACLK=VLO. CPUOFF=1,SCG0=1,SCG1=1,OSCOFF=0(LPM3),f =f ,f = f =f =0MHz ACLK VLO MCLK SMCLK DCO (8) CPUOFF=1,SCG0=1,SCG1=1,OSCOFF=1(LPM4),f =f = f =f =0MHz DCO ACLK MCLK SMCLK 20 Specifications Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 5.7 Typical Characteristics – Low-Power Mode Supply Currents 5 5 V = 3.0 V CC V = 3.0 V CC µA 4 A 4 y Current - 3 Current - µ 3 pl y 3 Sup PMMCOREVx = 3 Suppl M 2 4 2 P M L P - L ILPM3,XT1LF 1 PMMCOREVx = 0 I- LPM4 1 PMMCOREVx = 3 PMMCOREVx = 0 0 0 -40 -20 0 20 40 60 80 -40 -20 0 20 40 60 80 T - Free-AirTemperature - °C T - Free-AirTemperature - °C A A Figure5-3.LPM3SupplyCurrentvsTemperature Figure5-4.LPM4SupplyCurrentvsTemperature Copyright©2009–2018,TexasInstrumentsIncorporated Specifications 21 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com 5.8 Low-Power Mode With LCD Supply Currents (Into V ) Excluding External Current CC overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)(1) (2) TEMPERATURE(T ) A PARAMETER V PMMCOREVx –40°C 25°C 60°C 85°C UNIT CC TYP MAX TYP MAX TYP MAX TYP MAX 0 2.2 2.4 3.5 4.9 Low-powermode3 ILPM3 (LPM3)current,LCD4- 1 2.3 2.5 3.7 5.3 LCD, 3V µA ext.bias mbiausxinmgo(3d)e(,4)external 2 2.4 2.6 3.9 5.6 3 2.4 2.6 4.0 5.8 Low-powermode3 0 3.1 3.3 4.0 4.3 5.8 7.4 ILPM3 (LPM3)current,LCD4- 1 3.2 3.4 4.5 6.2 LCD, muxmode,internal 3V µA int.bias biasing,chargepump 2 3.3 3.5 4.7 6.5 disabled(3) (5) 3 3.3 3.5 4.3 4.8 6.7 8.9 0 4.0 2.2V 1 4.1 Low-powermode3 2 4.2 (LPM3)current,LCD4- I LPM3 muxmode,internal 0 4.2 µA LCD,CP biasing,chargepump 1 4.3 enabled(3) (6) 3V 2 4.5 3 4.5 (1) Allinputsaretiedto0VortoV .Outputsdonotsourceorsinkanycurrent. CC (2) ThecurrentsarecharacterizedwithaMicroCrystalMS1V-T1Kcrystalwithaloadcapacitanceof12.5pF.Theinternalandexternalload capacitancearechosentocloselymatchtherequired12.5pF. (3) CurrentforwatchdogtimerandRTCclockedbyACLKincluded.ACLK=lowfrequencycrystaloperation(XTS=0,XT1DRIVEx=0). CPUOFF=1,SCG0=1,SCG1=1,OSCOFF=0(LPM3),f =32768Hz,f = f =f =0MHz ACLK MCLK SMCLK DCO Currentforbrownout,high-sidesupervisor(SVS )normalmodeincluded.Low-sidesupervisor(SVS )andlow-sidemonitor(SVM ) H L L disabled.High-sidemonitor(SVM )disabled.RAMretentionenabled. H (4) LCDMx=11(4-muxmode),LCDREXT=1,LCDEXTBIAS=1(externalbiasing),LCD2B=0(1/3bias),LCDCPEN=0(chargepump disabled),LCDSSEL=0,LCDPREx=101,LCDDIVx=00011(f =32768Hz/32/4=256Hz) LCD Currentthroughexternalresistorsnotincluded(voltagelevelsaresuppliedbytestequipment). EvensegmentsS0,S2,...=0,oddsegmentsS1,S3,...=1.NoLCDpanelload. (5) LCDMx=11(4-muxmode),LCDREXT=0,LCDEXTBIAS=0(internalbiasing),LCD2B=0(1/3bias),LCDCPEN=0(chargepump disabled),LCDSSEL=0,LCDPREx=101,LCDDIVx=00011(f =32768Hz/32/4=256Hz) LCD EvensegmentsS0,S2,...=0,oddsegmentsS1,S3,...=1.NoLCDpanelload. (6) LCDMx=11(4-muxmode),LCDREXT=0,LCDEXTBIAS=0(internalbiasing),LCD2B=0(1/3bias),LCDCPEN=1(chargepump enabled),VLCDx=1000(V =3V,typical),LCDSSEL=0,LCDPREx=101,LCDDIVx=00011(f =32768Hz/32/4=256Hz) LCD LCD EvensegmentsS0,S2,...=0,oddsegmentsS1,S3,...=1.NoLCDpanelload. 5.9 Thermal Resistance Characteristics, CC430F51xx PACKAGE VALUE Low-Kboard 98°C/W θ Junction-to-ambientthermalresistance,stillair 48QFN(RGZ) JA High-Kboard 28°C/W 5.10 Thermal Resistance Characteristics, CC430F61xx PACKAGE VALUE Low-Kboard 83°C/W θ Junction-to-ambientthermalresistance,stillair 64QFN(RGC) JA High-Kboard 26°C/W 22 Specifications Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 5.11 Digital Inputs overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC 1.8V 0.80 1.40 V Positive-goinginputthresholdvoltage V IT+ 3V 1.50 2.10 1.8V 0.45 1.00 V Negative-goinginputthresholdvoltage V IT– 3V 0.75 1.65 1.8V 0.3 0.8 V Inputvoltagehysteresis(V –V ) V hys IT+ IT– 3V 0.4 1.0 Forpullup:V =V R Pulluporpulldownresistor IN SS 20 35 50 kΩ Pull Forpulldown:V =V IN CC C Inputcapacitance V =V orV 5 pF I IN SS CC I High-impedanceleakagecurrent See (1) (2) 1.8V,3V ±50 nA lkg(Px.y) Portswithinterruptcapability[see Externalinterrupttiming(externaltrigger blockdiagram(Section1.4)and t(int) pulsedurationtosetinterruptflag)(3) terminalfunctiondescriptions 1.8V,3V 20 ns (Section4.2)] (1) TheleakagecurrentismeasuredwithV orV appliedtothecorrespondingpins,unlessotherwisenoted. SS CC (2) Theleakageofthedigitalportpinsismeasuredindividually.Theportpinisselectedforinputandthepulluporpulldownresistoris disabled. (3) Anexternalsignalsetstheinterruptflageverytimetheminimuminterruptpulsedurationt ismet.Itmaybesetbytriggersignals (int) shorterthant . (int) Copyright©2009–2018,TexasInstrumentsIncorporated Specifications 23 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com 5.12 Digital Outputs overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN MAX UNIT CC I =–1mA,PxDS.y=0(2) V –0.25 V (OHmax) CC CC 1.8V High-leveloutputvoltage, I(OHmax)=–3mA,PxDS.y=0(3) VCC–0.60 VCC VOH reduceddrivestrength(1) I =–2mA,PxDS.y=0(2) V –0.25 V V (OHmax) CC CC 3V I =–6mA,PxDS.y=0(3) V –0.60 V (OHmax) CC CC I =1mA,PxDS.y=0(2) V V +0.25 (OLmax) SS SS 1.8V Low-leveloutputvoltage, I(OLmax)=3mA,PxDS.y=0(3) VSS VSS+0.60 VOL reduceddrivestrength(1) I =2mA,PxDS.y=0(2) V V +0.25 V (OLmax) SS SS 3V I =6mA,PxDS.y=0(3) V V +0.60 (OLmax) SS SS I =–3mA,PxDS.y=1(2) V –0.25 V (OHmax) CC CC 1.8V High-leveloutputvoltage, I(OHmax)=–10mA,PxDS.y=1(3) VCC–0.60 VCC V V OH fulldrivestrength I =–5mA,PxDS.y=1(2) V –0.25 V (OHmax) CC CC 3V I =–15mA,PxDS.y=1(3) V –0.60 V (OHmax) CC CC I =3mA,PxDS.y=1(2) V V +0.25 (OLmax) SS SS 1.8V Low-leveloutputvoltage, I(OLmax)=10mA,PxDS.y=1(3) VSS VSS+0.60 V V OL fulldrivestrength I =5mA,PxDS.y=1(2) V V +0.25 (OLmax) SS SS 3V I =15mA,PxDS.y=1(3) V V +0.60 (OLmax) SS SS V =1.8V, CC 16 f Portoutputfrequency C =20pF,R (4) (5) PMMCOREVx=0 MHz Px.y (withload) L L V =3V, CC 25 PMMCOREVx=2 V =1.8V, CC 16 PMMCOREVx=0 f Clockoutputfrequency C =20pF(5) MHz Port_CLK L V =3V, CC 25 PMMCOREVx=2 (1) SelectingreduceddrivestrengthmayreduceEMI. (2) Themaximumtotalcurrent,I andI ,foralloutputscombinedshouldnotexceed±48mAtoholdthemaximumvoltagedrop (OHmax) (OLmax) specified. (3) Themaximumtotalcurrent,I andI ,foralloutputscombinedshouldnotexceed±100mAtoholdthemaximumvoltage (OHmax) (OLmax) dropspecified. (4) Aresistivedividerwith2×R1betweenV andV isusedasload.Theoutputisconnectedtothecentertapofthedivider.Forfull CC SS drivestrength,R1=550Ω.Forreduceddrivestrength,R1=1.6kΩ.C =20pFisconnectedtotheoutputtoV . L SS (5) Theoutputvoltagereachesatleast10%and90%V atthespecifiedtogglefrequency. CC 24 Specifications Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 5.13 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0) 25 8 mA VP4CC.3= 3.0 V mA 7 VP4CC.3= 1.8 V TA= 25°C - - nt 20 TA= 25°C nt e e rr rr 6 u u T = 85°C C C A put 15 TA= 85°C put 5 ut ut O O el el 4 v v e e L 10 L - - 3 w w o o L L al al 2 c c pi 5 pi y y T T 1 - - OL OL I I 0 0 0 0.5 1 1.5 2 2.5 3 3.5 0 0.5 1 1.5 2 V - Low-Level Output Voltage - V V - Low-Level Output Voltage - V OL OL Figure5-5. TypicalLow-LevelOutputCurrentvsLow-Level Figure5-6. TypicalLow-LevelOutputCurrentvsLow-Level OutputVoltage OutputVoltage 0 0 A VCC= 3.0 V A VCC= 1.8 V m P4.3 m P4.3 -1 - - nt -5 nt e e rr rr -2 u u C C put -10 put -3 ut ut O O el el -4 v v e e h-L -15 h-L -5 Hig TA= 85°C Hig TA= 85°C al al -6 c c pi -20 pi y y T = 25°C T T = 25°C T -7 A - A - H H O O I I -25 -8 0 0.5 1 1.5 2 2.5 3 3.5 0 0.5 1 1.5 2 V - High-Level Output Voltage - V V - High-Level Output Voltage - V OH OH Figure5-7. TypicalHigh-LevelOutputCurrentvsHigh-Level Figure5-8. TypicalHigh-LevelOutputCurrentvsHigh-Level OutputVoltage OutputVoltage Copyright©2009–2018,TexasInstrumentsIncorporated Specifications 25 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com 5.14 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1) 60 25 V = 3.0 V T = 25°C V = 1.8 V A CC A A CC m P4.3 m P4.3 - 50 - TA= 25°C rrent TA= 85°C rrent 20 u u utC 40 utC TA= 85°C p p 15 ut ut O O el 30 el v v e e L L 10 - - w w o 20 o L L al al c c pi pi 5 y 10 y T T - - OL OL I I 0 0 0 0.5 1 1.5 2 2.5 3 3.5 0 0.5 1 1.5 2 V - Low-Level Output Voltage - V V - Low-Level Output Voltage - V OL OL Figure5-9. TypicalLow-LevelOutputCurrentvsLow-Level Figure5-10. TypicalLow-LevelOutputCurrentvsLow-Level OutputVoltage OutputVoltage 0 0 V = 3.0 V V = 1.8 V A CC A CC m P4.3 m P4.3 - - nt -10 nt -5 e e rr rr u u C C ut -20 ut p p -10 ut ut O O el -30 el v v e e -L -L -15 T = 85°C h h A g -40 g Hi Hi al al pic TA= 85°C pic -20 TA= 25°C y -50 y T T - - H H O T = 25°C O I A I -60 -25 0 0.5 1 1.5 2 2.5 3 3.5 0 0.5 1 1.5 2 V - High-Level Output Voltage - V V - High-Level Output Voltage - V OH OH Figure5-11. TypicalHigh-LevelOutputCurrentvsHigh-Level Figure5-12. TypicalHigh-LevelOutputCurrentvsHigh-Level OutputVoltage OutputVoltage 26 Specifications Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 5.15 Crystal Oscillator, XT1, Low-Frequency Mode(1) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC f =32768Hz,XTS=0, OSC XT1BYPASS=0,XT1DRIVEx=1, 0.075 T =25°C A DifferentialXT1oscillatorcrystal f =32768Hz,XTS=0, OSC ΔI currentconsumptionfromlowest XT1BYPASS=0,XT1DRIVEx=2, 3V 0.170 µA DVCC.LF drivesetting,LFmode T =25°C A f =32768Hz,XTS=0, OSC XT1BYPASS=0,XT1DRIVEx=3, 0.290 T =25°C A XT1oscillatorcrystalfrequency, f XTS=0,XT1BYPASS=0 32768 Hz XT1,LF0 LFmode f XT1oscillatorlogic-levelsquare- XTS=0,XT1BYPASS=1(2) (3) 10 32.768 50 kHz XT1,LF,SW waveinputfrequency,LFmode XTS=0, XT1BYPASS=0,XT1DRIVEx=0, 210 Oscillationallowancefor fXT1,LF=32768Hz,CL,eff=6pF OALF LFcrystals(4) XTS=0, kΩ XT1BYPASS=0,XT1DRIVEx=1, 300 f =32768Hz,C =12pF XT1,LF L,eff XTS=0,XCAPx=0(6) 2 Integratedeffectiveload XTS=0,XCAPx=1 5.5 CL,eff capacitance,LFmode(5) XTS=0,XCAPx=2 8.5 pF XTS=0,XCAPx=3 12.0 XTS=0,MeasuredatACLK, Dutycycle,LFmode 30% 70% f =32768Hz XT1,LF fFault,LF OLFscmilloadtoer(7f)aultfrequency, XTS=0(8) 10 10000 Hz f =32768Hz,XTS=0, OSC XT1BYPASS=0,XT1DRIVEx=0, 1000 T =25°C,C =6pF A L,eff t Start-uptime,LFmode 3V ms START,LF f =32768Hz,XTS=0, OSC XT1BYPASS=0,XT1DRIVEx=3, 500 T =25°C,C =12pF A L,eff (1) ToimproveEMIontheXT1oscillator,thefollowingguidelinesshouldbeobserved. • Keepthetracebetweenthedeviceandthecrystalasshortaspossible. • Designagoodgroundplanearoundtheoscillatorpins. • PreventcrosstalkfromotherclockordatalinesintooscillatorpinsXINandXOUT. • AvoidrunningPCBtracesunderneathoradjacenttotheXINandXOUTpins. • UseassemblymaterialsandprocessesthatavoidanyparasiticloadontheoscillatorXINandXOUTpins. • Ifconformalcoatingisused,makesurethatitdoesnotinducecapacitiveorresistiveleakagebetweentheoscillatorpins. (2) WhenXT1BYPASSisset,XT1circuitsareautomaticallypowereddown.Inputsignalisadigitalsquarewavewithparametricsdefinedin theSchmitt-triggerInputssectionofthisdatasheet. (3) Maximumfrequencyofoperationoftheentiredevicecannotbeexceeded. (4) Oscillationallowanceisbasedonasafetyfactorof5forrecommendedcrystals.Theoscillationallowanceisafunctionofthe XT1DRIVExsettingsandtheeffectiveload.Ingeneral,comparableoscillatorallowancecanbeachievedbasedonthefollowing guidelines,butshouldbeevaluatedbasedontheactualcrystalselectedfortheapplication: • ForXT1DRIVEx=0,C ≤6pF L,eff • ForXT1DRIVEx=1,6pF≤C ≤9pF L,eff • ForXT1DRIVEx=2,6pF≤C ≤10pF L,eff • ForXT1DRIVEx=3,C ≥6pF L,eff (5) Includesparasiticbondandpackagecapacitance(approximately2pFperpin). BecausethePCBaddsadditionalcapacitance,verifythecorrectloadbymeasuringtheACLKfrequency.Foracorrectsetup,the effectiveloadcapacitanceshouldalwaysmatchthespecificationoftheusedcrystal. (6) Requiresexternalcapacitorsatbothterminals.Valuesarespecifiedbycrystalmanufacturers. (7) FrequenciesbelowtheMINspecificationsetthefaultflag.FrequenciesabovetheMAXspecificationdonotsetthefaultflag. FrequenciesbetweentheMINandMAXspecificationsmightsettheflag. (8) Measuredwithlogic-levelinputfrequencybutalsoappliestooperationwithcrystals. Copyright©2009–2018,TexasInstrumentsIncorporated Specifications 27 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com 5.16 Internal Very-Low-Power Low-Frequency Oscillator (VLO) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC f VLOfrequency MeasuredatACLK 1.8Vto3.6V 6 9.4 14 kHz VLO df /d VLOfrequencytemperaturedrift MeasuredatACLK(1) 1.8Vto3.6V 0.5 %/°C VLO T df /dV VLOfrequencysupplyvoltagedrift MeasuredatACLK(2) 1.8Vto3.6V 4 %/V VLO CC Dutycycle MeasuredatACLK 1.8Vto3.6V 40% 50% 60% (1) Calculatedusingtheboxmethod:(MAX(–40°Cto85°C)–MIN(–40°Cto85°C))/MIN(–40°Cto85°C)/(85°C–(–40°C)) (2) Calculatedusingtheboxmethod:(MAX(1.8Vto3.6V)–MIN(1.8Vto3.6V))/MIN(1.8Vto3.6V)/(3.6V–1.8V) 5.17 Internal Reference, Low-Frequency Oscillator (REFO) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC I REFOoscillatorcurrentconsumption T =25°C 1.8Vto3.6V 3 µA REFO A f REFOfrequencycalibrated MeasuredatACLK 1.8Vto3.6V 32768 Hz REFO Fulltemperaturerange 1.8Vto3.6V ±3.5% REFOabsolutetolerancecalibrated T =25°C 3V ±1.5% A df /d REFOfrequencytemperaturedrift MeasuredatACLK(1) 1.8Vto3.6V 0.01 %/°C REFO T dfREFO/dVC REFOfrequencysupplyvoltagedrift MeasuredatACLK(2) 1.8Vto3.6V 1.0 %/V C Dutycycle MeasuredatACLK 1.8Vto3.6V 40% 50% 60% t REFOstart-uptime 40%/60%dutycycle 1.8Vto3.6V 25 µs START (1) Calculatedusingtheboxmethod:(MAX(–40°Cto85°C)–MIN(–40°Cto85°C))/MIN(–40°Cto85°C)/(85°C–(–40°C)) (2) Calculatedusingtheboxmethod:(MAX(1.8Vto3.6V)–MIN(1.8Vto3.6V))/MIN(1.8Vto3.6V)/(3.6V–1.8V) 5.18 DCO Frequency overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT f DCOfrequency(0,0)(1) DCORSELx=0,DCOx=0,MODx=0 0.07 0.20 MHz DCO(0,0) f DCOfrequency(0,31)(1) DCORSELx=0,DCOx=31,MODx=0 0.70 1.70 MHz DCO(0,31) f DCOfrequency(1,0)(1) DCORSELx=1,DCOx=0,MODx=0 0.15 0.36 MHz DCO(1,0) f DCOfrequency(1,31)(1) DCORSELx=1,DCOx=31,MODx=0 1.47 3.45 MHz DCO(1,31) f DCOfrequency(2,0)(1) DCORSELx=2,DCOx=0,MODx=0 0.32 0.75 MHz DCO(2,0) f DCOfrequency(2,31)(1) DCORSELx=2,DCOx=31,MODx=0 3.17 7.38 MHz DCO(2,31) f DCOfrequency(3,0)(1) DCORSELx=3,DCOx=0,MODx=0 0.64 1.51 MHz DCO(3,0) f DCOfrequency(3,31)(1) DCORSELx=3,DCOx=31,MODx=0 6.07 14.0 MHz DCO(3,31) f DCOfrequency(4,0)(1) DCORSELx=4,DCOx=0,MODx=0 1.3 3.2 MHz DCO(4,0) f DCOfrequency(4,31)(1) DCORSELx=4,DCOx=31,MODx=0 12.3 28.2 MHz DCO(4,31) f DCOfrequency(5,0)(1) DCORSELx=5,DCOx=0,MODx=0 2.5 6.0 MHz DCO(5,0) f DCOfrequency(5,31)(1) DCORSELx=5,DCOx=31,MODx=0 23.7 54.1 MHz DCO(5,31) f DCOfrequency(6,0)(1) DCORSELx=6,DCOx=0,MODx=0 4.6 10.7 MHz DCO(6,0) f DCOfrequency(6,31)(1) DCORSELx=6,DCOx=31,MODx=0 39.0 88.0 MHz DCO(6,31) f DCOfrequency(7,0)(1) DCORSELx=7,DCOx=0,MODx=0 8.5 19.6 MHz DCO(7,0) f DCOfrequency(7,31)(1) DCORSELx=7,DCOx=31,MODx=0 60 135 MHz DCO(7,31) Frequencystepbetweenrange S S =f /f 1.2 2.3 ratio DCORSEL DCORSELandDCORSEL+1 RSEL DCO(DCORSEL+1,DCO) DCO(DCORSEL,DCO) (1) WhenselectingtheproperDCOfrequencyrange(DCORSELx),thetargetDCOfrequency,f ,shouldbesettoresidewithinthe DCO rangeoff ≤f ≤f ,wheref representsthemaximumfrequencyspecifiedfortheDCOfrequency, DCO(n,0),MAX DCO DCO(n,31),MIN DCO(n,0),MAX rangen,tap0(DCOx=0)andf representstheminimumfrequencyspecifiedfortheDCOfrequency,rangen,tap31 DCO(n,31),MIN (DCOx=31).ThisensuresthatthetargetDCOfrequencyresideswithintherangeselected.Itshouldalsobenotedthatiftheactual f frequencyfortheselectedrangecausestheFLLortheapplicationtoselecttap0or31,theDCOfaultflagissettoreportthatthe DCO selectedrangeisatitsminimumormaximumtapsetting. 28 Specifications Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 DCO Frequency (continued) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT FrequencystepbetweentapDCO S S =f /f 1.02 1.12 ratio DCO andDCO+1 DCO DCO(DCORSEL,DCO+1) DCO(DCORSEL,DCO) Dutycycle MeasuredatSMCLK 40% 50% 60% df /dT DCOfrequencytemperaturedrift f =1MHz 0.1 %/°C DCO DCO df /dV DCOfrequencyvoltagedrift f =1MHz 1.9 %/V DCO CC DCO 100 V = 3.0 V CC T = 25°C A 10 z H M – O fDC DCOx = 31 1 DCOx = 0 0.1 0 1 2 3 4 5 6 7 DCORSEL Figure5-13.TypicalDCOFrequency 5.19 PMM, Brownout Reset (BOR) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT V BOR onvoltage,DV fallinglevel |dDV /d |<3V/s 1.45 V (DVCC_BOR_IT–) H CC CC t V BOR offvoltage,DV risinglevel |dDV /d |<3V/s 0.80 1.30 1.50 V (DVCC_BOR_IT+) H CC CC t V BOR hysteresis 50 250 mV (DVCC_BOR_hys) H t PulsedurationrequiredatRST/NMIpintoacceptareset 2 µs RESET 5.20 PMM, Core Voltage overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT V (AM) Corevoltage,activemode,PMMCOREV=3 2.4V≤DV ≤3.6V 1.90 V CORE3 CC V (AM) Corevoltage,activemode,PMMCOREV=2 2.2V≤DV ≤3.6V 1.80 V CORE2 CC V (AM) Corevoltage,activemode,PMMCOREV=1 2V≤DV ≤3.6V 1.60 V CORE1 CC V (AM) Corevoltage,activemode,PMMCOREV=0 1.8V≤DV ≤3.6V 1.40 V CORE0 CC V (LPM) Corevoltage,low-currentmode,PMMCOREV=3 2.4V≤DV ≤3.6V 1.94 V CORE3 CC V (LPM) Corevoltage,low-currentmode,PMMCOREV=2 2.2V≤DV ≤3.6V 1.84 V CORE2 CC V (LPM) Corevoltage,low-currentmode,PMMCOREV=1 2V≤DV ≤3.6V 1.64 V CORE1 CC V (LPM) Corevoltage,low-currentmode,PMMCOREV=0 1.8V≤DV ≤3.6V 1.44 V CORE0 CC Copyright©2009–2018,TexasInstrumentsIncorporated Specifications 29 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com 5.21 PMM, SVS High Side overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT SVSHE=0,DV =3.6V 0 CC nA I SVScurrentconsumption SVSHE=1,DV =3.6V,SVSHFP=0 200 (SVSH) CC SVSHE=1,DV =3.6V,SVSHFP=1 1.5 µA CC SVSHE=1,SVSHRVL=0 1.53 1.60 1.67 SVSHE=1,SVSHRVL=1 1.73 1.80 1.87 V SVS onvoltagelevel(1) V (SVSH_IT–) H SVSHE=1,SVSHRVL=2 1.93 2.00 2.07 SVSHE=1,SVSHRVL=3 2.03 2.10 2.17 SVSHE=1,SVSMHRRL=0 1.60 1.70 1.80 SVSHE=1,SVSMHRRL=1 1.80 1.90 2.00 SVSHE=1,SVSMHRRL=2 2.00 2.10 2.20 SVSHE=1,SVSMHRRL=3 2.10 2.20 2.30 V SVS offvoltagelevel(1) V (SVSH_IT+) H SVSHE=1,SVSMHRRL=4 2.25 2.35 2.50 SVSHE=1,SVSMHRRL=5 2.52 2.65 2.78 SVSHE=1,SVSMHRRL=6 2.85 3.00 3.15 SVSHE=1,SVSMHRRL=7 2.85 3.00 3.15 SVSHE=1,dV /dt=10mV/µs,SVSHFP=1 2.5 DVCC t SVS propagationdelay µs pd(SVSH) H SVSHE=1,dV /dt=1mV/µs,SVSHFP=0 20 DVCC SVSHE=0→1,dV /dt=10mV/µs,SVSHFP=1 12.5 DVCC t SVS onoroffdelaytime µs (SVSH) H SVSHE=0→1,dV /dt=1mV/µs,SVSHFP=0 100 DVCC dV /dt DV risetime 0 1000 V/s DVCC CC (1) TheSVS settingsavailabledependontheVCORE(PMMCOREVx)setting.SeethePowerManagementModuleandSupplyVoltage H SupervisorchapterintheCC430FamilyUser'sGuideonrecommendedsettingsanduse. 5.22 PMM, SVM High Side overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT SVMHE=0,DV =3.6V 0 CC nA I SVM currentconsumption SVMHE=1,DV =3.6V,SVMHFP=0 200 (SVMH) H CC SVMHE=1,DV =3.6V,SVMHFP=1 1.5 µA CC SVMHE=1,SVSMHRRL=0 1.60 1.70 1.80 SVMHE=1,SVSMHRRL=1 1.80 1.90 2.00 SVMHE=1,SVSMHRRL=2 2.00 2.10 2.20 SVMHE=1,SVSMHRRL=3 2.10 2.20 2.30 V SVM onoroffvoltagelevel(1) SVMHE=1,SVSMHRRL=4 2.25 2.35 2.50 V (SVMH) H SVMHE=1,SVSMHRRL=5 2.52 2.65 2.78 SVMHE=1,SVSMHRRL=6 2.85 3.00 3.15 SVMHE=1,SVSMHRRL=7 2.85 3.00 3.15 SVMHE=1,SVMHOVPE=1 3.75 SVMHE=1,dV /dt=10mV/µs,SVMHFP=1 2.5 DVCC t SVM propagationdelay µs pd(SVMH) H SVMHE=1,dV /dt=1mV/µs,SVMHFP=0 20 DVCC SVMHE=0→1,dV /dt=10mV/µs,SVMHFP=1 12.5 DVCC t SVM onoroffdelaytime µs (SVMH) H SVMHE=0→1,dV /dt=1mV/µs,SVMHFP=0 100 DVCC (1) TheSVM settingsavailabledependontheVCORE(PMMCOREVx)setting.SeethePowerManagementModuleandSupplyVoltage H SupervisorchapterintheCC430FamilyUser'sGuideonrecommendedsettingsanduse. 30 Specifications Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 5.23 PMM, SVS Low Side overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT SVSLE=0,PMMCOREV=2 0 nA I SVS currentconsumption SVSLE=1,PMMCOREV=2,SVSLFP=0 200 nA (SVSL) L SVSLE=1,PMMCOREV=2,SVSLFP=1 1.5 µA SVSLE=1,dV /dt=10mV/µs,SVSLFP=1 2.5 CORE t SVS propagationdelay µs pd(SVSL) L SVSLE=1,dV /dt=1mV/µs,SVSLFP=0 20 CORE SVSLE=0→1,dV /dt=10mV/µs,SVSLFP=1 12.5 CORE t SVS onoroffdelaytime µs (SVSL) L SVSLE=0→1,dV /dt=1mV/µs,SVSLFP=0 100 CORE 5.24 PMM, SVM Low Side overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT SVMLE=0,PMMCOREV=2 0 nA I SVM currentconsumption SVMLE=1,PMMCOREV=2,SVMLFP=0 200 nA (SVML) L SVMLE=1,PMMCOREV=2,SVMLFP=1 1.5 µA SVMLE=1,dV /dt=10mV/µs,SVMLFP=1 2.5 CORE t SVM propagationdelay µs pd(SVML) L SVMLE=1,dV /dt=1mV/µs,SVMLFP=0 20 CORE SVMLE=0→1,dV /dt=10mV/µs,SVMLFP=1 12.5 CORE t SVM onoroffdelaytime µs (SVML) L SVMLE=0→1,dV /dt=1mV/µs,SVMLFP=0 100 CORE 5.25 Wake-up Times From Low-Power Modes and Reset overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT PMMCOREV=SVSMLRRL=n f ≥4.0MHz 5 Wake-uptimefromLPM2,LPM3,or MCLK tWAKE-UP-FAST LPM4toactivemode(1) (SwVhSeLreFPn==10,1,2,or3), fMCLK<4.0MHz 6 µs PMMCOREV=SVSMLRRL=n Wake-uptimefromLPM2,LPM3,or tWAKE-UP-SLOW LPM4toactivemode(2)(3) (wheren=0,1,2,or3), 150 165 µs SVSLFP=0 Wake-uptimefromRSTorBOR tWAKE-UP-RESET eventtoactivemode(4) 2 3 ms (1) Thisvaluerepresentsthetimefromthewake-upeventtothefirstactiveedgeofMCLK.Thewake-uptimedependsontheperformance modeofthelow-sidesupervisor(SVS )andlow-sidemonitor(SVM ).t ispossiblewithSVS andSVM infullperformance L L WAKE-UP-FAST L L modeordisabled.Forspecificregistersettings,seetheLow-SideSVSandSVMControlandPerformanceModeSelectionsectionin thePowerManagementModuleandSupplyVoltageSupervisorchapteroftheCC430FamilyUser'sGuide. (2) Thisvaluerepresentsthetimefromthewake-upeventtothefirstactiveedgeofMCLK.Thewake-uptimedependsontheperformance modeofthelow-sidesupervisor(SVS )andlow-sidemonitor(SVM ).t issetwithSVS andSVM innormalmode(low L L WAKE-UP-SLOW L L currentmode).Forspecificregistersettings,seetheLow-SideSVSandSVMControlandPerformanceModeSelectionsectioninthe PowerManagementModuleandSupplyVoltageSupervisorchapteroftheCC430FamilyUser'sGuide. (3) Thewake-uptimesfromLPM0andLPM1toAMarenotspecified.TheyareproportionaltoMCLKcycletimebutarenotaffectedbythe performancemodesettingsasforLPM2,LPM3,andLPM4. (4) Thisvaluerepresentsthetimefromthewake-upeventtotheresetvectorexecution. 5.26 Timer_A overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN MAX UNIT CC Internal:SMCLKorACLK, f Timer_Ainputclockfrequency External:TACLK, 1.8V,3V 25 MHz TA Dutycycle=50%±10% Allcaptureinputs, t Timer_Acapturetiming 1.8V,3V 20 ns TA,cap Minimumpulsedurationrequiredforcapture Copyright©2009–2018,TexasInstrumentsIncorporated Specifications 31 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com 5.27 USCI (UART Mode) Clock Frequency PARAMETER TESTCONDITIONS MIN MAX UNIT Internal:SMCLKorACLK, f USCIinputclockfrequency External:UCLK, f MHz USCI SYSTEM Dutycycle=50%±10% f BITCLKclockfrequency(equalsbaudrateinMBaud) 1 MHz BITCLK 5.28 USCI (UART Mode) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER V MIN MAX UNIT CC 2.2V 50 600 t UARTreceivedeglitchtime(1) ns τ 3V 50 600 (1) PulsesontheUARTreceiveinput(UCxRX)shorterthantheUARTreceivedeglitchtimearesuppressed.Toensurethatpulsesare correctlyrecognized,theirdurationshouldexceedthemaximumspecificationofthedeglitchtime. 5.29 USCI (SPI Master Mode) Clock Frequency PARAMETER TESTCONDITIONS MIN MAX UNIT Internal:SMCLKorACLK, f USCIinputclockfrequency f MHz USCI Dutycycle=50%±10% SYSTEM 5.30 USCI (SPI Master Mode) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)(1)(seeFigure5-14 andFigure5-15) PARAMETER TESTCONDITIONS PMMCOREVx V MIN MAX UNIT CC 1.8V 55 0 3V 38 t SOMIinputdatasetuptime ns SU,MI 2.4V 30 3 3V 25 1.8V 0 0 3V 0 t SOMIinputdataholdtime ns HD,MI 2.4V 0 3 3V 0 1.8V 20 0 t SIMOoutputdatavalidtime(2) UCLKedgetoSIMOvalid, 3V 18 ns VALID,MO CL=20pF 2.4V 16 3 3V 15 1.8V –10 0 3V –8 t SIMOoutputdataholdtime(3) C =20pF ns HD,MO L 2.4V –10 3 3V –8 (1) f =1/2t witht ≥max(t +t ,t +t ) UCxCLK LO/HI LO/HI VALID,MO(USCI) SU,SI(Slave) SU,MI(USCI) VALID,SO(Slave) Fortheslaveparameterst andt ,seetheSPIparametersoftheattachedslave. SU,SI(Slave) VALID,SO(Slave) (2) SpecifiesthetimetodrivethenextvaliddatatotheSIMOoutputaftertheoutputchangingUCLKclockedge.Seethetimingdiagrams inFigure5-14andFigure5-15. (3) SpecifieshowlongdataontheSIMOoutputisvalidaftertheoutputchangingUCLKclockedge.Negativevaluesindicatethatthedata ontheSIMOoutputcanbecomeinvalidbeforetheoutputchangingclockedgeobservedonUCLK.SeethetimingdiagramsinFigure5- 14andFigure5-15. 32 Specifications Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 1/f UCxCLK CKPL= 0 UCLK CKPL= 1 t t LO/HI LO/HI t SU,MI t HD,MI SOMI t HD,MO t VALID,MO SIMO Figure5-14.SPIMasterMode,CKPH=0 1/f UCxCLK CKPL= 0 UCLK CKPL= 1 t t LO/HI LO/HI t t HD,MI SU,MI SOMI t HD,MO t VALID,MO SIMO Figure5-15.SPIMasterMode,CKPH=1 Copyright©2009–2018,TexasInstrumentsIncorporated Specifications 33 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com 5.31 USCI (SPI Slave Mode) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)(1)(seeFigure5-16 andFigure5-17) PARAMETER TESTCONDITIONS PMMCOREVx V MIN MAX UNIT CC 1.8V 11 0 3V 8 t STEleadtime,STElowtoclock ns STE,LEAD 2.4V 7 3 3V 6 1.8V 3 0 STElagtime,LastclocktoSTE 3V 3 t ns STE,LAG high 2.4V 3 3 3V 3 1.8V 66 0 STEaccesstime,STElowto 3V 50 t ns STE,ACC SOMIdataout 2.4V 36 3 3V 30 1.8V 30 0 STEdisabletime,STEhighto 3V 23 t ns STE,DIS SOMIhighimpedance 2.4V 16 3 3V 13 1.8V 5 0 3V 5 t SIMOinputdatasetuptime ns SU,SI 2.4V 2 3 3V 2 1.8V 5 0 3V 5 t SIMOinputdataholdtime ns HD,SI 2.4V 5 3 3V 5 1.8V 76 0 t SOMIoutputdatavalidtime(2) UCLKedgetoSOMIvalid, 3V 60 ns VALID,SO CL=20pF 2.4V 44 3 3V 40 1.8V 18 0 3V 12 t SOMIoutputdataholdtime(3) C =20pF ns HD,SO L 2.4V 10 3 3V 8 (1) f =1/2t witht ≥max(t +t ,t +t ) UCxCLK LO/HI LO/HI VALID,MO(Master) SU,SI(USCI) SU,MI(Master) VALID,SO(USCI) Forthemasterparameterst andt ,seetheSPIparametersoftheattachedmaster. SU,MI(Master) VALID,MO(Master) (2) SpecifiesthetimetodrivethenextvaliddatatotheSOMIoutputaftertheoutputchangingUCLKclockedge.Seethetimingdiagrams inFigure5-16andFigure5-17. (3) SpecifieshowlongdataontheSOMIoutputisvalidaftertheoutputchangingUCLKclockedge.SeethetimingdiagramsinFigure5-16 andFigure5-17. 34 Specifications Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 t t STE,LEAD STE,LAG STE 1/f UCxCLK CKPL= 0 UCLK CKPL= 1 t t t LO/HI LO/HI SU,SI t HD,SI SIMO t HD,SO t t t STE,ACC VALID,SO STE,DIS SOMI Figure5-16.SPISlaveMode,CKPH=0 t t STE,LEAD STE,LAG STE 1/f UCxCLK CKPL= 0 UCLK CKPL= 1 t t LO/HI LO/HI t HD,SI t SU,SI SIMO t HD,MO t t t STE,ACC VALID,SO STE,DIS SOMI Figure5-17.SPISlaveMode,CKPH=1 Copyright©2009–2018,TexasInstrumentsIncorporated Specifications 35 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com 5.32 USCI (I2C Mode) overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)(seeFigure5-18) PARAMETER TESTCONDITIONS V MIN MAX UNIT CC Internal:SMCLK,ACLK f USCIinputclockfrequency External:UCLK f MHz USCI SYSTEM Dutycycle=50%±10% f SCLclockfrequency 2.2V,3V 0 400 kHz SCL f ≤100kHz 4.0 SCL t Holdtime(repeated)START 2.2V,3V µs HD,STA f >100kHz 0.6 SCL f ≤100kHz 4.7 SCL t SetuptimeforarepeatedSTART 2.2V,3V µs SU,STA f >100kHz 0.6 SCL t Dataholdtime 2.2V,3V 0 ns HD,DAT t Datasetuptime 2.2V,3V 250 ns SU,DAT f ≤100kHz 4.0 SCL t SetuptimeforSTOP 2.2V,3V µs SU,STO f >100kHz 0.6 SCL 2.2V 50 600 t Pulsedurationofspikessuppressedbyinputfilter ns SP 3V 50 600 t t t t HD,STA SU,STA HD,STA BUF SDA t t t LOW HIGH SP SCL t t SU,DAT SU,STO t HD,DAT Figure5-18.I2CModeTiming 36 Specifications Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 5.33 LCD_B Operating Conditions PARAMETER CONDITIONS MIN NOM MAX UNIT Supplyvoltagerange,charge LCDCPEN=1,0000<VLCDx≤1111 V 2.2 3.6 V CC,LCD_B,CPen,3.6 pumpenabled,V ≤3.6V (chargepumpenabled,V ≤3.6V) LCD LCD Supplyvoltagerange,charge LCDCPEN=1,0000<VLCDx≤1100 V 2.0 3.6 V CC,LCD_B,CPen,3.3 pumpenabled,V ≤3.3V (chargepumpenabled,V ≤3.3V) LCD LCD Supplyvoltagerange,internal V LCDCPEN=0,VLCDEXT=0 2.4 3.6 V CC,LCD_B,int.bias biasing,chargepumpdisabled Supplyvoltagerange,external V LCDCPEN=0,VLCDEXT=0 2.4 3.6 V CC,LCD_B,ext.bias biasing,chargepumpdisabled Supplyvoltagerange,external LCDvoltage,internalor V LCDCPEN=0,VLCDEXT=1 2.0 3.6 V CC,LCD_B,VLCDEXT externalbiasing,chargepump disabled ExternalLCDvoltageat LCDCAP/R33,internalor V LCDCPEN=0,VLCDEXT=1 2.4 3.6 V LCDCAP/R33 externalbiasing,chargepump disabled CapacitoronLCDCAPwhen LCDCPEN=1,VLCDx>0000(charge C 4.7 4.7 10 µF LCDCAP chargepumpenabled pumpenabled) f =2×mux×f with f LCDframefrequencyrange LCD FRAME 0 100 Hz Frame mux=1(static),2,3,4 f ACLKinputfrequencyrange 30 32 40 kHz ACLK,in C Panelcapacitance 100-Hzframefrequency 10000 pF Panel V AnaloginputvoltageatR33 LCDCPEN=0,VLCDEXT=1 2.4 V +0.2 V R33 CC V + R03 LCDREXT=1,LCDEXTBIAS=1, 2/3× V AnaloginputvoltageatR23 V V V R23,1/3bias LCD2B=0 R13 (V – R33 R33 V ) R03 V + R03 AnaloginputvoltageatR13 LCDREXT=1,LCDEXTBIAS=1, 1/3× V V V V R13,1/3bias with1/3biasing LCD2B=0 R03 (V – R23 R33 V ) R03 V + R03 AnaloginputvoltageatR13 LCDREXT=1,LCDEXTBIAS=1, 1/2× V V V V R13,1/2bias with1/2biasing LCD2B=1 R03 (V – R33 R33 V ) R03 V AnaloginputvoltageatR03 R0EXT=1 V V R03 SS Voltagedifferencebetween V –V LCDCPEN=0,R0EXT=1 2.4 V +0.2 V LCD R03 V andR03 CC LCD ExternalLCDreference V voltageappliedat VLCDREFx= 01 0.8 1.2 1.5 V LCDREF/R13 LCDREF/R13 Copyright©2009–2018,TexasInstrumentsIncorporated Specifications 37 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com 5.34 LCD_B Electrical Characteristics overoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC VLCDx=0000,VLCDEXT=0 2.4Vto3.6V V CC LCDCPEN=1,VLCDx=0001 2Vto3.6V 2.54 LCDCPEN=1,VLCDx=0010 2Vto3.6V 2.60 LCDCPEN=1,VLCDx=0011 2Vto3.6V 2.66 LCDCPEN=1,VLCDx=0100 2Vto3.6V 2.72 LCDCPEN=1,VLCDx=0101 2Vto3.6V 2.78 LCDCPEN=1,VLCDx=0110 2Vto3.6V 2.84 LCDCPEN=1,VLCDx=0111 2Vto3.6V 2.90 V LCDvoltage V LCD LCDCPEN=1,VLCDx=1000 2Vto3.6V 2.96 LCDCPEN=1,VLCDx=1001 2Vto3.6V 3.02 LCDCPEN=1,VLCDx=1010 2Vto3.6V 3.08 LCDCPEN=1,VLCDx=1011 2Vto3.6V 3.14 LCDCPEN=1,VLCDx=1100 2Vto3.6V 3.20 LCDCPEN=1,VLCDx=1101 2.2Vto3.6V 3.26 LCDCPEN=1,VLCDx=1110 2.2Vto3.6V 3.32 LCDCPEN=1,VLCDx=1111 2.2Vto3.6V 3.38 3.6 Peaksupplycurrentsdueto I LCDCPEN=1,VLCDx=1111 2.2V 200 µA CC,Peak,CP chargepumpactivities C =4.7µF, TimetochargeC when LCDCAP t LCD LCDCPEN=0→1, 2.2V 100 500 ms LCD,CP,on discharged VLCDx=1111 Maximumchargepumpload I LCDCPEN=1,VLCDx=1111 2.2V 50 µA CP,Load current LCDdriveroutput LCDCPEN=1,VLCDx=1000, R 2.2V 10 kΩ LCD,Seg impedance,segmentlines I =±10µA LOAD LCDdriveroutput LCDCPEN=1,VLCDx=1000, R 2.2V 10 kΩ LCD,COM impedance,commonlines I =±10µA LOAD 38 Specifications Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 5.35 12-Bit ADC, Power Supply and Input Range Conditions overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)(1) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC AVCCandDVCCareconnectedtogether, Analogsupplyvoltage, AV AVSSandDVSSareconnectedtogether, 2.2 3.6 V CC fullperformance V =V =0V (AVSS) (DVSS) V Analoginputvoltagerange(2) AllADC12analoginputpinsAx 0 AV V (Ax) CC f =5.0MHz,ADC12ON=1, 2.2V 125 155 Operatingsupplycurrentinto ADC12CLK IADC12_A AVCCterminal(3) RADEFCO12ND=IV0=,S0HT0=0,SHT1=0, 3V 150 220 µA OnlyoneterminalAxcanbeselectedat C Inputcapacitance 2.2V 20 25 pF I onetime R InputMUXONresistance 0V≤V ≤AV 10 200 1900 Ω I Ax CC (1) TheleakagecurrentisspecifiedbythedigitalI/Oinputleakage. (2) TheanaloginputvoltagerangemustbewithintheselectedreferencevoltagerangeV toV forvalidconversionresults.Ifthe R+ R– referencevoltageissuppliedbyanexternalsourceoriftheinternalreferencevoltageisusedandREFOUT=1,thendecoupling capacitorsarerequired.SeeSection5.40andSection5.41. (3) TheinternalreferencesupplycurrentisnotincludedincurrentconsumptionparameterI . ADC12_A 5.36 12-Bit ADC, Timing Parameters overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC ForspecifiedperformanceofADC12linearity parametersusinganexternalreference 0.45 4.8 5.0 voltageorAVCCasreference(1) f ADCconversionclock ForspecifiedperformanceofADC12linearity 2.2V,3V MHz ADC12CLK parametersusingtheinternalreference(2) 0.45 2.4 4.0 ForspecifiedperformanceofADC12linearity parametersusingtheinternalreference(3) 0.45 2.4 2.7 InternalADC12 fADC12OSC oscillator(4) ADC12DIV=0,fADC12CLK=fADC12OSC 2.2V,3V 4.2 4.8 5.4 MHz REFON=0,Internaloscillator, 2.2V,3V 2.4 3.1 f =4.2MHzto5.4MHz ADC12OSC t Conversiontime µs CONVERT Externalf fromACLK,MCLKor 13× ADC12CLK SMCLK,ADC12SSEL≠0 1/f ADC12CLK R =400Ω,R =1000Ω,C =30pF, tSample Samplingtime τ=S(R +R)×IC (5) I 2.2V,3V 1000 ns S I I (1) REFOUT=0,externalreferencevoltage:SREF2=0,SREF1=1,SREF0=0.AVCCasreferencevoltage:SREF2=0,SREF1=0, SREF0=0.ThespecifiedperformanceoftheADC12linearityisensuredwhenusingtheADC12OSC.Forotherclocksources,the specifiedperformanceoftheADC12linearityisensuredwithf maximumof5.0MHz. ADC12CLK (2) SREF2=0,SREF1=1,SREF0=0,ADC12SR=0,REFOUT=1 (3) SREF2=0,SREF1=1,SREF0=0,ADC12SR=0,REFOUT=0.ThespecifiedperformanceoftheADC12linearityisensuredwhen usingtheADC12OSCdividedby2. (4) TheADC12OSCissourceddirectlyfromMODOSCinsidetheUCS. (5) Approximately10Tau(τ)areneededtogetanerroroflessthan±0.5LSB: t =ln(2n+1)×(R +R)×C +800ns,wheren=ADCresolution=12,R =externalsourceresistance Sample S I I S Copyright©2009–2018,TexasInstrumentsIncorporated Specifications 39 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com 5.37 12-Bit ADC, Linearity Parameters Using an External Reference Voltage or AVCC as Reference Voltage overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC 1.4V≤dVREF≤1.6V(2) ±2.0 E Integrallinearityerror(1) 2.2V,3V LSB I 1.6V<dVREF(2) ±1.7 E Differentiallinearityerror(1) See (2) 2.2V,3V ±1.0 LSB D dVREF≤2.2V(2) 2.2V,3V ±1.0 ±2.0 E Offseterror(3) LSB O dVREF>2.2V(2) 2.2V,3V ±1.0 ±2.0 E Gainerror(3) See (2) 2.2V,3V ±1.0 ±2.0 LSB G dVREF≤2.2V(2) 2.2V,3V ±1.4 ±3.5 E Totalunadjustederror LSB T dVREF>2.2V(2) 2.2V,3V ±1.4 ±3.5 (1) Parametersarederivedusingthehistogrammethod. (2) Theexternalreferencevoltageisselectedby:SREF2=0or1,SREF1=1,SREF0=0.dVREF=V –V ,V <AVCC,V >AVSS. R+ R– R+ R– Unlessotherwisementioned,dVREF>1.5V.ImpedanceoftheexternalreferencevoltageR<100Ωandtwodecouplingcapacitors, 10µFand100nF,shouldbeconnectedtoVREF+/VREF-todecouplethedynamiccurrent.AlsoseetheCC430FamilyUser'sGuide. (3) Parametersarederivedusingabestfitcurve. 5.38 12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS(1) V MIN TYP MAX UNIT CC Integrallinearity ADC12SR=0,REFOUT=1 fADC12CLK≤4.0MHz ±1.7 EI error(2) ADC12SR=0,REFOUT=0 f ≤2.7MHz 2.2V,3V ±2.5 LSB ADC12CLK ADC12SR=0,REFOUT=1 f ≤4.0MHz –1.0 +2.0 ADC12CLK Differential ED linearityerror(2) ADC12SR=0,REFOUT=1 fADC12CLK≤2.7MHz 2.2V,3V –1.0 +1.5 LSB ADC12SR=0,REFOUT=0 f ≤2.7MHz –1.0 +2.5 ADC12CLK ADC12SR=0,REFOUT=1 f ≤4.0MHz ±1.0 ±2.0 E Offseterror(3) ADC12CLK 2.2V,3V LSB O ADC12SR=0,REFOUT=0 f ≤2.7MHz ±1.0 ±2.0 ADC12CLK ADC12SR=0,REFOUT=1 f ≤4.0MHz ±1.0 ±2.0 LSB E Gainerror(3) ADC12CLK 2.2V,3V G ADC12SR=0,REFOUT=0 f ≤2.7MHz ±1.5%(4) VREF ADC12CLK Totalunadjusted ADC12SR=0,REFOUT=1 fADC12CLK≤4.0MHz ±1.4 ±3.5 LSB E 2.2V,3V T error ADC12SR=0,REFOUT=0 f ≤2.7MHz ±1.5%(4) VREF ADC12CLK (1) Theinternalreferencevoltageisselectedby:SREF2=0or1,SREF1=1,SREF0=1.dVREF=V –V . R+ R– (2) Parametersarederivedusingthehistogrammethod. (3) Parametersarederivedusingabestfitcurve. (4) Thegainerrorandtotalunadjustederroraredominatedbytheaccuracyoftheintegratedreferencemoduleabsoluteaccuracy.Inthis modethereferencevoltageusedbytheADC12_Aisnotavailableonapin. 40 Specifications Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 5.39 12-Bit ADC, Temperature Sensor and Built-In V (1) MID overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC V See (2) (3) ADC12ON=1,INCH=0Ah, 2.2V 680 mV SENSOR TA=0°C 3V 680 2.2V 2.25 TC See (3) ADC12ON=1,INCH=0Ah mV/°C SENSOR 3V 2.25 Sampletimerequiredif ADC12ON=1,INCH=0Ah, 2.2V 30 tSENSOR(sample) channel10isselected(4) Errorofconversionresult≤1LSB 3V 30 µs AV divideratchannel11, CC ADC12ON=1,INCH=0Bh 0.48 0.5 0.52 V V factor AVCC AVCC V MID 2.2V 1.06 1.1 1.14 AV divideratchannel11 ADC12ON=1,INCH=0Bh V CC 3V 1.44 1.5 1.56 Sampletimerequiredif ADC12ON=1,INCH=0Bh, tVMID(sample) channel11isselected(5) Errorofconversionresult≤1LSB 2.2V,3V 1000 ns (1) ThetemperaturesensorisprovidedbytheREFmodule.SeetheREFmoduleparametric,I ,regardingthecurrentconsumptionof REF+ thetemperaturesensor. (2) Thetemperaturesensoroffsetcanbesignificant.TIrecommendsasingle-pointcalibrationtominimizetheoffseterrorofthebuilt-in temperaturesensor. (3) Thedevicedescriptorstructurecontainscalibrationvaluesfor30°C±3°Cand85°C±3°Cforeachoftheavailablereferencevoltage levels.ThesensorvoltagecanbecomputedasV =TC ×(Temperature,°C)+V ,whereTC andV can SENSE SENSOR SENSOR SENSOR SENSOR becomputedfromthecalibrationvaluesforhigheraccuracy. (4) Thetypicalequivalentimpedanceofthesensoris51kΩ.Thesampletimerequiredincludesthesensor-ontimet . SENSOR(on) (5) Theontimet isincludedinthesamplingtimet ;noadditionalontimeisneeded. VMID(on) VMID(sample) 1000 950 V) m 900 e ( g a olt 850 V or 800 s n e e S 750 ur erat 700 p m e 650 T al pic 600 y T 550 500 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 AmbientTemperature (°C) Figure5-19.TypicalTemperatureSensorVoltage Copyright©2009–2018,TexasInstrumentsIncorporated Specifications 41 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com 5.40 REF, External Reference overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)(1) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC V Positiveexternalreference V >V /V (2) 1.4 AV V eREF+ voltageinput eREF+ REF– eREF– CC V /V Negativeexternalreference V >V /V (3) 0 1.2 V REF– eREF– voltageinput eREF+ REF– eREF– (VeREF+– Differentialexternalreference V >V /V (4) 1.4 AV V V /V ) voltageinput eREF+ REF– eREF– CC REF– eREF– 1.4V≤V ≤V ,V =0V, eREF+ AVCC eREF– f =5MHz,ADC12SHTx=1h, 2.2V,3V ±8.5 ±26 ADC12CLK I Conversionrate200ksps VeREF+ Staticinputcurrent µA IVREF–/VeREF- 1.4V≤VeREF+≤VAVCC,VeREF–=0V, f =5MHz,ADC12SHTx=8h, 2.2V,3V ±1 ADC12CLK Conversionrate20ksps CapacitanceatVREF+or C VREF-terminal,external 10 µF VREF+/- reference(5) (1) TheexternalreferenceisusedduringADCconversiontochargeanddischargethecapacitancearray.Theinputcapacitance,C,isalso i thedynamicloadforanexternalreferenceduringconversion.Thedynamicimpedanceofthereferencesupplyshouldfollowthe recommendationsonanalog-sourceimpedancetoallowthechargetosettlefor12-bitaccuracy. (2) Theaccuracylimitstheminimumpositiveexternalreferencevoltage.Lowerreferencevoltagelevelsmaybeappliedwithreduced accuracyrequirements. (3) Theaccuracylimitsthemaximumnegativeexternalreferencevoltage.Higherreferencevoltagelevelsmaybeappliedwithreduced accuracyrequirements. (4) Theaccuracylimitsminimumexternaldifferentialreferencevoltage.Lowerdifferentialreferencevoltagelevelsmaybeappliedwith reducedaccuracyrequirements. (5) Twodecouplingcapacitors,10µFand100nF,shouldbeconnectedtoVREFtodecouplethedynamiccurrentrequiredforanexternal referencesourceifitisusedfortheADC12_A.AlsoseetheCC430FamilyUser'sGuide. 42 Specifications Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 5.41 REF, Built-In Reference overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted)(1) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC REFVSEL=2for2.5V, 3V 2.41 ±1.5% REFON=REFOUT=1,I =0A VREF+ Positivebuilt-inreference REFVSEL=1for2V, V 3V 1.93 ±1.5% V REF+ voltageoutput REFON=REFOUT=1,I =0A VREF+ REFVSEL=0for1.5V, 2.2V,3V 1.45 ±1.5% REFON=REFOUT=1,I =0A VREF+ REFVSEL=0for1.5V,reducedperformance 1.8 AVCCminimumvoltage, REFVSEL=0for1.5V 2.2 AV Positivebuilt-inreference V CC(min) active REFVSEL=1for2V 2.3 REFVSEL=2for2.5V 2.8 Operatingsupplycurrentinto REFON=1,REFOUT=0,REFBURST=0 3V 100 140 µA IREF+ AVCCterminal(2)(3) REFON=1,REFOUT=1,REFBURST=0 3V 0.9 1.5 mA REFVSEL=0,1,or2, Load-currentregulation, I =+10µAor–1000µA, IL(VREF+) VREF+terminal(4) AVVREF+=AV foreachreferencelevel, 2500 µV/mA CC CC(min) REFON=REFOUT=1 CapacitanceatVREF+ C REFON=REFOUT=1 20 100 pF VREF+ terminals,internalreference I =0A, Temperaturecoefficientof VREF+ ppm/ TCREF+ built-inreference(5) REFVSEL=0,1,or2, 30 50 °C REFON=1,REFOUT=0or1 AV =AV toAV , Powersupplyrejectionratio CC CC(min) CC(max) PSRR_DC T =25°C,REFVSEL=0,1,or2, 120 300 µV/V (DC) A REFON=1,REFOUT=0or1 AV =AV toAV CC CC(min) CC(max) Powersupplyrejectionratio T =25°C,f=1kHz,ΔVpp=100mV, PSRR_AC A 6.4 mV/V (AC) REFVSEL=0,1,or2, REFON=1,REFOUT=0or1 AV =AV toAV , CC CC(min) CC(max) REFVSEL=0,1,or2, 75 REFOUT=0,REFON=0→1 Settlingtimeofreference tSETTLE voltage(6) AVCC=AVCC(min)toAVCC(max), µs C =C (maximum), VREF VREF 75 REFVSEL=0,1,or2, REFOUT=1,REFON=0→1 (1) ThereferenceissuppliedtotheADCbytheREFmoduleandisbufferedlocallyinsidetheADC.TheADCusestwointernalbuffers,one smallerandonelargerfordrivingtheVREF+terminal.WhenREFOUT=1,thereferenceisavailableattheVREF+terminal,aswellas, usedasthereferencefortheconversionandusesthelargerbuffer.WhenREFOUT=0,thereferenceisonlyusedasthereferencefor theconversionandusesthesmallerbuffer. (2) TheinternalreferencecurrentissuppliedfromtheAVCCterminal.ConsumptionisindependentoftheADC12ONcontrolbit,unlessa conversionisactive.TheREFONbitenablestosettlethebuilt-inreferencebeforestartingananalog-to-digitalconversion.REFOUT=0 representsthecurrentcontributionofthesmallerbuffer.REFOUT=1representsthecurrentcontributionofthelargerbufferwithout externalload. (3) ThetemperaturesensorisprovidedbytheREFmodule.ItscurrentissuppliedfromtheAVCCterminalandisequivalenttoI with REF+ REFON=1andREFOUT=0. (4) Contributiononlyduetothereferenceandbufferincludingpackage.ThisdoesnotincluderesistanceduetoPCBtraceorothercauses. (5) Calculatedusingtheboxmethod:(MAX(–40°Cto85°C)–MIN(–40°Cto85°C))/MIN(–40°Cto85°C)/(85°C–(–40°C)). (6) Theconditionisthattheerrorinaconversionstartedaftert islessthan±0.5LSB.Thesettlingtimedependsontheexternal REFON capacitiveloadwhenREFOUT=1. Copyright©2009–2018,TexasInstrumentsIncorporated Specifications 43 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com 5.42 Comparator_B overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER TESTCONDITIONS V MIN TYP MAX UNIT CC V Supplyvoltage 1.8 3.6 V CC 1.8V 40 CBPWRMD=00 2.2V 30 50 Comparatoroperatingsupply I currentintoAVCC,Excludes 3V 40 65 µA AVCC_COMP referenceresistorladder CBPWRMD=01 2.2V,3V 10 30 CBPWRMD=10 2.2V,3V 0.1 0.5 Quiescentcurrentoflocalreference I CBREFACC=1,CBREFLx=01 22 µA AVCC_REF voltageamplifierintoAVCC V Commonmodeinputrange 0 V –1 V IC CC CBPWRMD=00 ±20 V Inputoffsetvoltage mV OFFSET CBPWRMD=01or10 ±10 C Inputcapacitance 5 pF IN On(switchclosed) 3 4 kΩ R Seriesinputresistance SIN Off(switchopen) 30 MΩ CBPWRMD=00,CBF=0 450 ns t Propagationdelay,responsetime CBPWRMD=01,CBF=0 600 PD CBPWRMD=10,CBF=0 50 µs CBPWRMD=00,CBON=1, 0.35 0.6 1.0 CBF=1,CBFDLY=00 CBPWRMD=00,CBON=1, 0.6 1.0 1.8 CBF=1,CBFDLY=01 t Propagationdelaywithfilteractive µs PD,filter CBPWRMD=00,CBON=1, 1.0 1.8 3.4 CBF=1,CBFDLY=10 CBPWRMD=00,CBON=1, 1.8 3.4 6.5 CBF=1,CBFDLY=11 CBON=0toCBON=1, 1 2 Comparatorenabletime,settling CBPWRMD=00or01 t µs EN_CMP time CBON=0toCBON=1, 100 CBPWRMD=10 t Resistorreferenceenabletime CBON=0toCBON=1 0.3 1.5 µs EN_REF VIN× VIN=referenceintoresistorladder, V Referencevoltageforagiventap (n+1) V CB_REF n=0to31 /32 44 Specifications Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 5.43 Flash Memory overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER T MIN TYP MAX UNIT J DV Programanderasesupplyvoltage 1.8 3.6 V CC(PGM/ERASE) I AveragesupplycurrentfromDVCCduringprogram 3 5 mA PGM I AveragesupplycurrentfromDVCCduringerase 2 6.5 mA ERASE I ,I AveragesupplycurrentfromDVCCduringmasseraseorbankerase 2 6.5 mA MERASE BANK t Cumulativeprogramtime(1) 16 ms CPT Programanderaseendurance 104 105 cycles t Dataretentionduration 25°C 100 years Retention t Wordorbyteprogramtime(2) 64 85 µs Word t Blockprogramtimeforfirstbyteorword(2) 49 65 µs Block,0 Blockprogramtimeforeachadditionalbyteorword,exceptforlastbyteor tBlock,1–(N–1) word(2) 37 49 µs t Blockprogramtimeforlastbyteorword(2) 55 73 µs Block,N Erasetimeforsegmenterase,masserase,andbankerasewhen tErase available(2) 23 32 ms MCLKfrequencyinmarginalreadmode f 0 1 MHz MCLK,MGR (FCTL4.MGR0=1orFCTL4.MGR1=1) (1) Thecumulativeprogramtimemustnotbeexceededwhenwritingtoa128-byteflashblock.Thisparameterappliestoallprogramming methods:individualwordwrite,individualbytewrite,andblockwritemodes. (2) Thesevaluesarehardwiredintothestatemachineoftheflashcontroller. 5.44 JTAG and Spy-Bi-Wire Interface overrecommendedrangesofsupplyvoltageandoperatingfree-airtemperature(unlessotherwisenoted) PARAMETER V MIN TYP MAX UNIT CC f Spy-Bi-Wireinputfrequency 2.2V,3V 0 20 MHz SBW t Spy-Bi-Wirelowclockpulseduration 2.2V,3V 0.025 15 µs SBW,Low t Spy-Bi-Wireenabletime(TESThightoacceptanceoffirstclockedge)(1) 2.2V,3V 1 µs SBW,En t Spy-Bi-Wirereturntonormaloperationtime 15 100 µs SBW,Rst 2.2V 0 5 MHz f TCKinputfrequency,4-wireJTAG(2) TCK 3V 0 10 MHz R InternalpulldownresistanceonTEST 2.2V,3V 45 60 80 kΩ internal (1) ToolsthataccesstheSpy-Bi-Wireinterfaceneedtowaitfortheminimumt timeafterpullingtheTEST/SBWTCKpinhighbefore SBW,En applyingthefirstSBWTCKclockedge. (2) f mayberestrictedtomeetthetimingrequirementsofthemoduleselected. TCK Copyright©2009–2018,TexasInstrumentsIncorporated Specifications 45 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com 5.45 RF1A CC1101-Based Radio Parameters 5.46 Recommended Operating Conditions PARAMETER TESTCONDITIONS MIN TYP MAX UNIT V Supplyvoltagerangeduringradiooperation 2.0 3.6 V CC PMMCOREVx Corevoltagerange,PMMCOREVxsettingduringradiooperation 2 3 300 348 RFrange 389(1) 464 MHz 779 928 2-FSK 0.6 500 Datarate 2-GFSK,OOK,andASK 0.6 250 kBaud (Shaped)MSK(alsoknownasdifferentialoffsetQPSK)(2) 26 500 RFcrystalfrequency 26 26 27 MHz Totaltoleranceincludinginitialtolerance,crystalloading,aging, RFcrystaltolerance andtemperaturedependency.(3) ±40 ppm RFcrystalloadcapacitance 10 13 20 pF RFcrystaleffectiveseriesresistance 100 Ω (1) Ifusinga27-MHzcrystal,thelowerfrequencylimitforthisbandis392MHz. (2) IfusingoptionalManchesterencoding,thedatarateinkbpsishalfthebaudrate. (3) Theacceptablecrystaltolerancedependsonfrequencyband,channelbandwidth,andspacing.AlsoseeDN005--CC11xxSensitivity versusFrequencyOffsetandCrystalAccuracy. 5.47 RF Crystal Oscillator, XT2 T =25°C,V =3V(unlessotherwisenoted)(1) A CC PARAMETER MIN TYP MAX UNIT Start-uptime(2) 150 810 µs Dutycycle 45% 50% 55% (1) AllmeasurementresultsareobtainedusingtheEM430F6137RF900withBOMaccordingtotestedfrequencyrange(seeTable7-1). (2) Thestart-uptimedependstoaverylargedegreeontheusedcrystal. 5.48 Current Consumption, Reduced-Power Modes T =25°C,V =3V(unlessotherwisenoted)(1) A CC PARAMETER TESTCONDITIONS MIN TYP MAX UNIT RFcrystaloscillatoronly(2) 100 µA Currentconsumption IDLEstate(includingRFcrystaloscillator) 1.7 mA FSTXONstate(onlythefrequencysynthesizerisrunning)(3) 9.5 (1) AllmeasurementresultsareobtainedusingtheEM430F6137RF900withBOMaccordingtotestedfrequencyrange(seeTable7-1). (2) Tomeasurethecurrent,followthissequence: • EnableXT2withXOSC_FORCE_ON=1. • Setradiotosleepmode. • DisableXT2clockrequestsfromanymodule. (3) ThiscurrentconsumptionisalsorepresentativeofotherintermediatestateswhengoingfromIDLEtoRXorTX,includingthecalibration state. 46 Specifications Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 5.49 Current Consumption, Receive Mode T =25°C,V =3V(unlessotherwisenoted)(1) (2) A CC DATARATE PARAMETER FREQ(MHz) TESTCONDITIONS TYP UNIT (kBaud) Inputat–100dBm(closeto 17 sensitivitylimit) 1.2 Inputat–40dBm(well 16 abovesensitivitylimit) Inputat–100dBm(closeto 17 Registersettingsoptimizedfor sensitivitylimit) 315 38.4 reducedcurrent Inputat–40dBm(well 16 abovesensitivitylimit) Inputat–100dBm(closeto 18 sensitivitylimit) 250 Inputat–40dBm(well 16.5 abovesensitivitylimit) Inputat–100dBm(closeto 18 sensitivitylimit) 1.2 Inputat–40dBm(well 17 abovesensitivitylimit) Inputat–100dBm(closeto 18 Current Registersettingsoptimizedfor sensitivitylimit) 433 38.4 mA consumption,RX reducedcurrent Inputat–40dBm(well 17 abovesensitivitylimit) Inputat–100dBm(closeto 18.5 sensitivitylimit) 250 Inputat–40dBm(well 17 abovesensitivitylimit) Inputat–100dBm(closeto 16 sensitivitylimit) 1.2 Inputat–40dBm(well 15 abovesensitivitylimit) Inputat–100dBm(closeto 16 Registersettingsoptimizedfor sensitivitylimit) 868,915 38.4 reducedcurrent(3) Inputat–40dBm(well 15 abovesensitivitylimit) Inputat–100dBm(closeto 16 sensitivitylimit) 250 Inputat–40dBm(well 15 abovesensitivitylimit) (1) AllmeasurementresultsareobtainedusingtheEM430F6137RF900withBOMaccordingtotestedfrequencyrange(seeTable7-1). (2) Reducedcurrentsetting(MDMCFG2.DEM_DCFILT_OFF=1)givesaslightlylowercurrentconsumptionatthecostofareductionin sensitivity.SeeSection5.55throughSection5.58foradditionaldetailsoncurrentconsumptionandsensitivity. (3) For868or915MHz,seeFigure5-20forcurrentconsumptionwithregistersettingsoptimizedforsensitivity. Copyright©2009–2018,TexasInstrumentsIncorporated Specifications 47 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com 19 19 T = 85°C T = 85°C A A T = 25°C T = 25°C A A T = -40°C T = -40°C A A A) 18 A) 18 m m nt ( nt ( e e urr urr C C o o di di a a R 17 R 17 16 16 -100 -80 -60 -40 -20 -100 -80 -60 -40 -20 Input Power (dBm) Input Power (dBm) 1.2 kBaud GFSK 38.4 kBaud GFSK 19 19 TA= 85°C TA= 85°C TA= 25°C TA= 25°C TA= -40°C TA= -40°C A) 18 A) 18 m m nt ( nt ( e e urr urr C C o o di di a a R 17 R 17 16 16 -100 -80 -60 -40 -20 -100 -80 -60 -40 -20 Input Power (dBm) Input Power (dBm) 250 kBaud GFSK 500 kBaud MSK Figure5-20.TypicalRXCurrentConsumptionOverTemperatureandInputPowerLevel,868MHz, Sensitivity-OptimizedSetting 48 Specifications Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 5.50 Current Consumption, Transmit Mode T =25°C,V =3V(unlessotherwisenoted)(1) (2) A CC FREQUENCY PATABLE OUTPUT PARAMETER TYP UNIT [MHz} SETTING POWER(dBm) 0xC0 maximum 26 0xC4 +10 25 315 0x51 0 15 0x29 –6 15 0xC0 maximum 33 0xC6 +10 29 433 0x50 0 17 0x2D –6 17 Currentconsumption,TX mA 0xC0 maximum 36 0xC3 +10 33 868 0x8D 0 18 0x2D –6 18 0xC0 maximum 35 0xC3 +10 32 915 0x8D 0 18 0x2D –6 18 (1) AllmeasurementresultsareobtainedusingtheEM430F6137RF900withBOMaccordingtotestedfrequencyrange(seeTable7-1). (2) Reducedcurrentsetting(MDMCFG2.DEM_DCFILT_OFF=1)givesaslightlylowercurrentconsumptionatthecostofareductionin sensitivity.SeeSection5.55throughSection5.58foradditionaldetailsoncurrentconsumptionandsensitivity. Copyright©2009–2018,TexasInstrumentsIncorporated Specifications 49 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com 5.51 Typical TX Current Consumption, 315 MHz OUTPUT V 2V 3V 3.6V PATABLE CC PARAMETER POWER UNIT SETTING (dBm) TA 25°C 25°C 25°C 0xC0 maximum 27.5 26.4 28.1 0xC4 +10 25.1 25.2 25.3 Currentconsumption,TX mA 0x51 0 14.4 14.6 14.7 0x29 –6 14.2 14.7 15.0 5.52 Typical TX Current Consumption, 433 MHz OUTPUT V 2V 3V 3.6V PATABLE CC PARAMETER POWER UNIT SETTING (dBm) TA 25°C 25°C 25°C 0xC0 maximum 33.1 33.4 33.8 0xC6 +10 28.6 28.8 28.8 Currentconsumption,TX mA 0x50 0 16.6 16.8 16.9 0x2D –6 16.8 17.5 17.8 5.53 Typical TX Current Consumption, 868 MHz OUTPUT V 2V 3V 3.6V PATABLE CC PARAMETER POWER UNIT SETTING (dBm) TA –40°C 25°C 85°C –40°C 25°C 85°C –40°C 25°C 85°C 0xC0 maximum 36.7 35.2 34.2 38.5 35.5 34.9 37.1 35.7 34.7 Current 0xC3 +10 34.0 32.8 32.0 34.2 33.0 32.5 34.3 33.1 32.2 mA consumption,TX 0x8D 0 18.0 17.6 17.5 18.3 17.8 18.1 18.4 18.0 17.7 0x2D –6 17.1 17.0 17.2 17.8 17.8 18.3 18.2 18.1 18.1 5.54 Typical TX Current Consumption, 915 MHz OUTPUT V 2V 3V 3.6V PATABLE CC PARAMETER POWER UNIT SETTING (dBm) TA –40°C 25°C 85°C –40°C 25°C 85°C –40°C 25°C 85°C 0xC0 maximum 35.5 33.8 33.2 36.2 34.8 33.6 36.3 35.0 33.8 Current 0xC3 +10 33.2 32.0 31.0 33.4 32.1 31.2 33.5 32.3 31.3 mA consumption,TX 0x8D 0 17.8 17.4 17.1 18.1 17.6 17.3 18.2 17.8 17.5 0x2D –6 17.0 16.9 16.9 17.7 17.6 17.6 18.1 18.0 18.0 50 Specifications Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 5.55 RF Receive, Overall T =25°C,V =3V(unlessotherwisenoted)(1) A CC PARAMETER TESTCONDITIONS MIN TYP MAX UNIT Digitalchannelfilterbandwidth(2) 58 812 kHz 25MHzto1GHz –68 –57 Spuriousemissions(3) (4) dBm Above1GHz –66 –47 RXlatency Serialoperation(5) 9 bit (1) AllmeasurementresultsareobtainedusingtheEM430F6137RF900withBOMaccordingtotestedfrequencyrange(seeTable7-1). (2) Userprogrammable.Thebandwidthlimitsareproportionaltocrystalfrequency(givenvaluesassumea26.0MHzcrystal) (3) Typicalradiatedspuriousemissionis–49dBmmeasuredattheVCOfrequency (4) MaximumfigureistheETSIEN300220limit (5) Timefromstartofreceptionuntildataisavailableonthereceiverdataoutputpinisequalto9bit. 5.56 RF Receive, 315 MHz T =25°C,V =3V(unlessotherwisenoted)(1) A CC 2-FSK,1%packeterrorrate,20-bytepacketlength,Sensitivityoptimized,MDMCFG2.DEM_DCFILT_OFF=0(unless otherwisenoted) DATARATE PARAMETER TESTCONDITIONS TYP UNIT (kBaud) 0.6 14.3-kHzdeviation,58-kHzdigitalchannelfilterbandwidth –117 1.2 5.2-kHzdeviation,58-kHzdigitalchannelfilterbandwidth(2) –111 Receiversensitivity 38.4 20-kHzdeviation,100-kHzdigitalchannelfilterbandwidth(3) –103 dBm 250 127-kHzdeviation,540-kHzdigitalchannelfilterbandwidth (4) –95 500 MSK,812-kHzdigitalchannelfilterbandwidth(4) –86 (1) AllmeasurementresultsareobtainedusingtheEM430F6137RF900withBOMaccordingtotestedfrequencyrange(seeTable7-1). (2) SensitivitycanbetradedforcurrentconsumptionbysettingMDMCFG2.DEM_DCFILT_OFF=1.Thetypicalcurrentconsumptionisthen reducedbyapproximately2mAclosetothesensitivitylimit.Thesensitivityistypicallyreducedto–109dBm. (3) SensitivitycanbetradedforcurrentconsumptionbysettingMDMCFG2.DEM_DCFILT_OFF=1.Thetypicalcurrentconsumptionisthen reducedbyapproximately2mAclosetothesensitivitylimit.Thesensitivityistypicallyreducedto–102dBm. (4) MDMCFG2.DEM_DCFILT_OFF=1cannotbeusedfordatarates≥250kBaud. 5.57 RF Receive, 433 MHz T =25°C,V =3V(unlessotherwisenoted)(1) A CC 2-FSK,1%packeterrorrate,20-bytepacketlength,Sensitivityoptimized,MDMCFG2.DEM_DCFILT_OFF=0(unless otherwisenoted) DATARATE PARAMETER TESTCONDITIONS TYP UNIT (kBaud) 0.6 14.3-kHzdeviation,58-kHzdigitalchannelfilterbandwidth –114 1.2 5.2-kHzdeviation,58-kHzdigitalchannelfilterbandwidth(2) –111 Receiversensitivity 38.4 20-kHzdeviation,100-kHzdigitalchannelfilterbandwidth(3) –104 dBm 250 127-kHzdeviation,540-kHzdigitalchannelfilterbandwidth (4) –93 500 MSK,812-kHzdigitalchannelfilterbandwidth(4) –85 (1) AllmeasurementresultsareobtainedusingtheEM430F6137RF900withBOMaccordingtotestedfrequencyrange(seeTable7-1). (2) SensitivitycanbetradedforcurrentconsumptionbysettingMDMCFG2.DEM_DCFILT_OFF=1.Thetypicalcurrentconsumptionisthen reducedbyapproximately2mAclosetothesensitivitylimit.Thesensitivityistypicallyreducedto–109dBm. (3) SensitivitycanbetradedforcurrentconsumptionbysettingMDMCFG2.DEM_DCFILT_OFF=1.Thetypicalcurrentconsumptionisthen reducedbyapproximately2mAclosetothesensitivitylimit.Thesensitivityistypicallyreducedto–101dBm. (4) MDMCFG2.DEM_DCFILT_OFF=1cannotbeusedfordatarates≥250kBaud. Copyright©2009–2018,TexasInstrumentsIncorporated Specifications 51 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com 5.58 RF Receive, 868 or 915 MHz T =25°C,V =3V(unlessotherwisenoted)(1) A CC 1%packeterrorrate,20-bytepacketlength,Sensitivityoptimized,MDMCFG2.DEM_DCFILT_OFF=0(unlessotherwise noted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT 0.6-kBauddatarate,2-FSK,14.3-kHzdeviation,58-kHzdigitalchannelfilterbandwidth(unlessotherwisenoted) Receiversensitivity –115 dBm 1.2-kBauddatarate,2-FSK,5.2-kHzdeviation,58-kHzdigitalchannelfilterbandwidth(unlessotherwisenoted) –109 Receiversensitivity(2) 2-GFSKmodulationbysettingMDMCFG2.MOD_FORMAT=2, dBm –109 GaussianfilterwithBT=0.5 Saturation FIFOTHR.CLOSE_IN_RX=0(3) –28 dBm Adjacentchannel Desiredchannel3dBabovethesensitivitylimit,100- –100-kHzoffset 39 rejection kHzchannelspacing(4) +100-kHzoffset 39 dB IF152kHz,desiredchannel3dBabovethesensitivity Imagechannelrejection 29 dB limit ±2-MHzoffset –48 dBm Blocking Desiredchannel3dBabovethesensitivitylimit(5) ±10-MHzoffset –40 dBm 38.4-kBauddatarate,2-FSK,20-kHzdeviation,100-kHzdigitalchannelfilterbandwidth(unlessotherwisenoted) –102 Receiversensitivity(6) 2-GFSKmodulationbysettingMDMCFG2.MOD_FORMAT=2, dBm –101 GaussianfilterwithBT=0.5 Saturation FIFOTHR.CLOSE_IN_RX=0(3) –19 dBm Adjacentchannel Desiredchannel3dBabovethesensitivitylimit,200- –200-kHzoffset 20 rejection kHzchannelspacing(5) +200-kHzoffset 25 dB Imagechannelrejection IF152kHz,desiredchannel3dBabovethesensitivitylimit 23 dB ±2-MHzoffset –48 dBm Blocking Desiredchannel3dBabovethesensitivitylimit(5) ±10-MHzoffset –40 dBm 250-kBauddatarate,2-FSK,127-kHzdeviation,540-kHzdigitalchannelfilterbandwidth(unlessotherwisenoted) –90 Receiversensitivity (7) 2-GFSKmodulationbysettingMDMCFG2.MOD_FORMAT=2, dBm –90 GaussianfilterwithBT=0.5 Saturation FIFOTHR.CLOSE_IN_RX=0(3) –19 dBm Adjacentchannel Desiredchannel3dBabovethesensitivitylimit,750- –750-kHzoffset 24 rejection kHzchannelspacing(8) +750-kHzoffset 30 dB Imagechannelrejection IF304kHz,desiredchannel3dBabovethesensitivitylimit 18 dB ±2-MHzoffset –53 dBm Blocking Desiredchannel3dBabovethesensitivitylimit(8) ±10-MHzoffset –39 dBm 500-kBauddatarate,MSK,812-kHzdigitalchannelfilterbandwidth(unlessotherwisenoted) Receiversensitivity(7) –84 dBm Imagechannelrejection IF355kHz,desiredchannel3dBabovethesensitivitylimit –2 dB ±2-MHzoffset –53 dBm Blocking Desiredchannel3dBabovethesensitivitylimit(9) ±10-MHzoffset –38 dBm (1) AllmeasurementresultsareobtainedusingtheEM430F6137RF900withBOMaccordingtotestedfrequencyrange(seeTable7-1). (2) SensitivitycanbetradedforcurrentconsumptionbysettingMDMCFG2.DEM_DCFILT_OFF=1.Thetypicalcurrentconsumptionisthen reducedbyapproximately2mAclosetothesensitivitylimit.Thesensitivityistypicallyreducedto–107dBm (3) SeeDN010Close-inReceptionwithCC1101. (4) SeeFigure5-21forblockingperformanceatotheroffsetfrequencies. (5) SeeFigure5-22forblockingperformanceatotheroffsetfrequencies. (6) SensitivitycanbetradedforcurrentconsumptionbysettingMDMCFG2.DEM_DCFILT_OFF=1.Thetypicalcurrentconsumptionisthen reducedbyapproximately2mAclosetothesensitivitylimit.Thesensitivityistypicallyreducedto–100dBm. (7) MDMCFG2.DEM_DCFILT_OFF=1cannotbeusedfordatarates≥250kBaud. (8) SeeFigure5-23forblockingperformanceatotheroffsetfrequencies. (9) SeeFigure5-24forblockingperformanceatotheroffsetfrequencies. 52 Specifications Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 80 60 70 50 60 50 40 ng (dB) 3400 vity (dB) 30 Blocki 20 Selecti 20 10 10 0 0 -10 -20 -10 -40 -30 -20 -10 0 10 20 30 40 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 Offset (MHz) Offset (MHz) NOTE: 868.3MHz,2-FSK,5.2-kHzdeviation,IFis152.3kHz,digitalchannelfilterbandwidthis58kHz Figure5-21.TypicalSelectivityat1.2-kBaudDataRate 80 50 70 40 60 50 30 ng (dB) 3400 vity (dB) 20 Blocki 20 Selecti 10 10 0 0 -10 -10 -20 -20 -40 -30 -20 -10 0 10 20 30 40 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 Offset (MHz) Offset (MHz) NOTE: 868MHz,2-FSK,20kHzdeviation,IFis152.3kHz,digitalchannelfilterbandwidthis100kHz Figure5-22.TypicalSelectivityat38.4-kBaudDataRate Copyright©2009–2018,TexasInstrumentsIncorporated Specifications 53 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com 80 50 70 40 60 50 30 ng (dB) 3400 vity (dB) 20 Blocki 20 Selecti 10 10 0 0 -10 -10 -20 -20 -40 -30 -20 -10 0 10 20 30 40 -3 -2 -1 0 1 2 3 Offset (MHz) Offset (MHz) NOTE: 868MHz,2-FSK,IFis304kHz,digitalchannelfilterbandwidthis540kHz Figure5-23.TypicalSelectivityat250-kBaudDataRate 80 50 70 40 60 50 30 B) 40 dB) ng (d 30 vity ( 20 ki cti Bloc 20 Sele 10 10 0 0 -10 -10 -20 -20 -40 -30 -20 -10 0 10 20 30 40 -3 -2 -1 0 1 2 3 Offset (MHz) Offset (MHz) NOTE: 868MHz,2-FSK,IFis355kHz,digitalchannelfilterbandwidthis812kHz Figure5-24.TypicalSelectivityat500-kBaudDataRate 54 Specifications Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 5.59 Typical Sensitivity, 315 MHz, Sensitivity Optimized Setting DATARATE VCC 2V 3V 3.6V PARAMETER UNIT (kBaud) T –40°C 25°C 85°C –40°C 25°C 85°C –40°C 25°C 85°C A 1.2 –112 –112 –110 –112 –111 –109 –112 –111 –108 Sensitivity, 38.4 –105 –105 –104 –105 –103 –102 –105 –104 –102 dBm 315MHz 250 –95 –95 –92 –94 –95 –92 –95 –94 –91 5.60 Typical Sensitivity, 433 MHz, Sensitivity Optimized Setting DATARATE VCC 2V 3V 3.6V PARAMETER UNIT (kBaud) T –40°C 25°C 85°C –40°C 25°C 85°C –40°C 25°C 85°C A 1.2 –111 –110 –108 –111 –111 –108 –111 –110 –107 Sensitivity, 38.4 –104 –104 –101 –104 –104 –101 –104 –103 –101 dBm 433MHz 250 –93 –94 –91 –93 –93 –90 –93 –93 –90 5.61 Typical Sensitivity, 868 MHz, Sensitivity Optimized Setting DATARATE VCC 2V 3V 3.6V PARAMETER UNIT (kBaud) T –40°C 25°C 85°C –40°C 25°C 85°C –40°C 25°C 85°C A 1.2 –109 –109 –107 –109 –109 –106 –109 –108 –106 Sensitivity, 38.4 –102 –102 –100 –102 –102 –99 –102 –101 –99 dBm 868MHz 250 –90 –90 –88 –89 –90 –87 –89 –90 –87 500 –84 –84 –81 –84 –84 –80 –84 –84 -80 5.62 Typical Sensitivity, 915 MHz, Sensitivity Optimized Setting DATARATE VCC 2V 3V 3.6V PARAMETER UNIT (kBaud) T –40°C 25°C 85°C –40°C 25°C 85°C –40°C 25°C 85°C A 1.2 –109 –109 –107 –109 –109 –106 –109 –108 –105 Sensitivity, 38.4 –102 –102 –100 –102 –102 –99 –103 –102 –99 dBm 915MHz 250 –92 –92 –89 –92 –92 –88 –92 –92 –88 500 –87 –86 –81 –86 –86 –81 –86 –85 –80 Copyright©2009–2018,TexasInstrumentsIncorporated Specifications 55 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com 5.63 RF Transmit T =25°C,V =3V(unlessotherwisenoted)(1) A CC P =+10dBm(unlessotherwisenoted) TX FREQUENCY PARAMETER TESTCONDITIONS TYP UNIT (MHz) 315 122+j31 Differentialloadimpedance(2) 433 116+j41 Ω 868,915 86.5+j43 315 +12 Outputpower,highest 433 Deliveredtoa50-Ωsingle-endedloadfromCC430reference +13 setting(3) 868 designRFmatchingnetwork +11 dBm 915 +11 Outputpower,lowest Deliveredtoa50-Ωsingle-endedloadfromCC430reference setting(3) designRFmatchingnetwork –30 dBm Secondharmonic –56 433 Thirdharmonic –57 Secondharmonic –50 Harmonics,radiated(4)(5)(6) 868 dBm Thirdharmonic –52 Secondharmonic –50 915 Thirdharmonic –54 Frequenciesbelow960MHz <–38 315 +10dBmCW Frequenciesabove960MHz <–48 Frequenciesbelow1GHz –45 433 +10dBmCW Frequenciesabove1GHz <–48 Harmonics,conducted dBm Secondharmonic –59 868 +10dBmCW Otherharmonics <–71 Secondharmonic –53 915 +11dBmCW(7) Otherharmonics <–47 Frequenciesbelow960MHz <–58 315 +10dBmCW Frequenciesabove960MHz <–53 Frequenciesbelow1GHz <–54 Frequenciesabove1GHz <–54 433 +10dBmCW Frequenciesfrom47to74,87.5to118, Spuriousemissions, 174to230,470to862MHz <–63 conducted,harmonicsnot dBm included(8) Frequenciesbelow1GHz <–46 Frequenciesabove1GHz <–59 868 +10dBmCW Frequenciesfrom47to74,87.5to118, <–56 174to230,470to862MHz Frequenciesbelow960MHz <–49 915 +11dBmCW Frequenciesabove960MHz <–63 TXlatency(9) Serialoperation 8 bits (1) AllmeasurementresultsareobtainedusingtheEM430F6137RF900withBOMaccordingtotestedfrequencyrange(seeTable7-1). (2) DifferentialimpedanceasseenfromtheRFport(RF_PandRF_N)towardstheantenna.FollowtheCC430referencedesignsavailable fromtheTIwebsite. (3) Outputpowerisprogrammable,andthefullrangeisavailableinallfrequencybands.Outputpowermayberestrictedbyregulatory limits.AlsoseeAN050UsingtheCC1101intheEuropean868MHzSRDBandandDN013ProgrammingOutputPoweronCC1101, whichgivestheoutputpowerandharmonicswhenusingmultilayerinductors.Theoutputpoweristhentypically+10dBmwhen operatingat868or915MHz. (4) Theantennasusedduringtheradiatedmeasurements(SMAFF-433fromR.W.BadlandandNearsonS331868/915)playapartin attenuatingtheharmonics. (5) MeasuredonEM430F6137RF900withCW,maximumoutputpower (6) Allharmonicsarebelow–41.2dBmwhenoperatinginthe902to928MHzband. (7) Requirementis–20dBcunderFCC15.247. (8) AllradiatedspuriousemissionsarewithinthelimitsofETSI.AlsoseeDN017CC11xx868/915MHzRFMatching. (9) TimefromsamplingthedataonthetransmitterdatainputpinuntilitisobservedontheRFoutputports 56 Specifications Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 5.64 Optimum PATABLE Settings for Various Output Power Levels and Frequency Bands T =25°C,V =3V(unlessotherwisenoted)(1) A CC PATABLESETTING OUTPUTPOWER(dBm) 315MHz 433MHz 868MHz 915MHz –30 0x12 0x05 0x03 0x03 –12 0x33 0x26 0x25 0x25 –6 0x29 0x2D 0x2D 0x2D 0 0x51 0x50 0x8D 0x8D 10 0xC4 0xC4 0xC3 0xC3 Maximum 0xC0 0xC0 0xC0 0xC0 (1) AllmeasurementresultsareobtainedusingtheEM430F6137RF900withBOMaccordingtotestedfrequencyrange(seeTable7-1). Copyright©2009–2018,TexasInstrumentsIncorporated Specifications 57 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com 5.65 Typical Output Power, 315 MHz(1) V 2V 3V 3.6V CC PARAMETER PATABLESETTING UNIT T 25°C 25°C 25°C A 0xC0(maximum) 11.9 11.8 11.8 0xC4(10dBm) 10.3 10.3 10.3 Outputpower,315MHz 0xC6(default) 9.3 dBm 0x51(0dBm) 0.7 0.6 0.7 0x29(–6dBm) –6.8 –5.6 –5.3 (1) AllmeasurementresultsareobtainedusingtheEM430F6137RF900withBOMaccordingtotestedfrequencyrange(seeTable7-1). 5.66 Typical Output Power, 433 MHz(1) V 2V 3V 3.6V CC PARAMETER PATABLESETTING UNIT T 25°C 25°C 25°C A 0xC0(maximum) 12.6 12.6 12.6 0xC4(10dBm) 10.3 10.2 10.2 Outputpower,433MHz 0xC6(default) 10.0 dBm 0x50(0dBm) 0.3 0.3 0.3 0x2D(–6dBm) –6.4 –5.4 –5.1 (1) AllmeasurementresultsareobtainedusingtheEM430F6137RF900withBOMaccordingtotestedfrequencyrange(seeTable7-1). 5.67 Typical Output Power, 868 MHz(1) V 2V 3V 3.6V CC PARAMETER PATABLESETTING UNIT T –40°C 25°C 85°C –40°C 25°C 85°C –40°C 25°C 85°C A 0xC0(maximum) 11.9 11.2 10.5 11.9 11.2 10.5 11.9 11.2 10.5 0xC3(10dBm) 10.8 10.1 9.4 10.8 10.1 9.4 10.7 10.1 9.4 Outputpower, 0xC6(default) 8.8 dBm 868MHz 0x8D(0dBm) 1.0 0.3 –0.3 1.1 0.3 –0.3 1.1 0.3 –0.3 0x2D(–6dBm) –6.5 –6.8 –7.3 –5.3 –5.8 –6.3 –4.9 –5.4 –6.0 (1) AllmeasurementresultsareobtainedusingtheEM430F6137RF900withBOMaccordingtotestedfrequencyrange(seeTable7-1). 5.68 Typical Output Power, 915 MHz(1) V 2V 3V 3.6V CC PARAMETER PATABLESETTING UNIT T –40°C 25°C 85°C –40°C 25°C 85°C –40°C 25°C 85°C A 0xC0(maximum) 12.2 11.4 10.6 12.1 11.4 10.7 12.1 11.4 10.7 0xC3(10dBm) 11.0 10.3 9.5 11.0 10.3 9.5 11.0 10.3 9.6 Outputpower, 0xC6(default) 8.8 dBm 915MHz 0x8D(0dBm) 1.9 1.0 0.3 1.9 1.0 0.3 1.9 1.1 0.3 0x2D(–6dBm) –5.5 –6.0 –6.5 –4.3 –4.8 –5.5 –3.9 –4.4 –5.1 (1) AllmeasurementresultsareobtainedusingtheEM430F6137RF900withBOMaccordingtotestedfrequencyrange(seeTable7-1). 58 Specifications Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 5.69 Frequency Synthesizer Characteristics T =25°C,V =3V(unlessotherwisenoted)(1) A CC MINfiguresaregivenusinga27MHzcrystal.TYPandMAXfiguresaregivenusinga26MHzcrystal. PARAMETER TESTCONDITIONS MIN TYP MAX UNIT Programmedfrequencyresolution(2) 26-to27-MHzcrystal 397 f /216 412 Hz XOSC Synthesizerfrequencytolerance(3) ±40 ppm 50-kHzoffsetfromcarrier –95 100-kHzoffsetfromcarrier –94 200-kHzoffsetfromcarrier –94 500-kHzoffsetfromcarrier –98 RFcarrierphasenoise dBc/Hz 1-MHzoffsetfromcarrier –107 2-MHzoffsetfromcarrier –112 5-MHzoffsetfromcarrier –118 10-MHzoffsetfromcarrier –129 PLLturnonandhoptime(4) Crystaloscillatorrunning 85.1 88.4 88.4 µs PLLRXtoTXsettlingtime(5) 9.3 9.6 9.6 µs PLLTXtoRXsettlingtime(6) 20.7 21.5 21.5 µs PLLcalibrationtime(7) 694 721 721 µs (1) AllmeasurementresultsareobtainedusingtheEM430F6137RF900withBOMaccordingtotestedfrequencyrange(seeTable7-1). (2) Theresolution(inHz)isequalforallfrequencybands. (3) Dependsoncrystalused.Requiredaccuracy(includingtemperatureandaging)dependsonfrequencybandandchannelbandwidthand spacing. (4) TimefromleavingtheIDLEstateuntilarrivingintheRX,FSTXON,orTXstate,whennotperformingcalibration. (5) Settlingtimeforthe1-IFstepfromRXtoTX (6) Settlingtimeforthe1-IFstepfromTXtoRX (7) CalibrationcanbeinitiatedmanuallyorautomaticallybeforeenteringorafterleavingRXorTX. Copyright©2009–2018,TexasInstrumentsIncorporated Specifications 59 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com 5.70 Typical RSSI_offset Values T =25°C,V =3V(unlessotherwisenoted)(1) A CC RSSI_OFFSET(dB) DATARATE(kBaud) 433MHz 868MHz 1.2 74 74 38.4 74 74 250 74 74 500 74 74 (1) AllmeasurementresultsareobtainedusingtheEM430F6137RF900withBOMaccordingtotestedfrequencyrange(seeTable7-1). 0 0 1.2kBaud 250kBaud -20 -20 500kBaud 38.4kBaud m) -40 m) -40 B B d d ut ( ut ( o o d -60 d -60 a a e e R R SI SI S -80 S -80 R R -100 -100 -120 -120 -120 -100 -80 -60 -40 -20 0 -120 -100 -80 -60 -40 -20 0 Input Power (dBm) Input Power (dBm) Figure5-25.TypicalRSSIValuevsInputPowerLevelforDifferentDataRatesat868MHz 60 Specifications Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 6 Detailed Description 6.1 Sub-1 GHz Radio The implemented sub-1 GHz radio module is based on the industry-leading CC1101, requiring very few externalcomponents.Figure6-1showsahigh-levelblockdiagramoftheimplementedradio. Radio Control ADC or at O LNA dul FIF mo X ADC De R er CU dl M RF_P 0 Frequency an o RF_N 90 Synthesizer acket H erface t P nt I PA or FO at FI odul TX M RC OSC BIAS XOSC RBIAS RF_XIN RF_XOUT Copyright © 2017,Texas Instruments Incorporated Figure6-1.Sub-1GHzRadioBlockDiagram The radio features a low-IF receiver. The received RF signal is amplified by a low-noise amplifier (LNA) and down-converted in quadrature to the intermediate frequency (IF). At IF, the I/Q signals are digitized. Automatic gain control (AGC), fine channel filtering, demodulation bit, and packet synchronization are performeddigitally. The transmitter part is based on direct synthesis of the RF. The frequency synthesizer includes a completely on-chip LC VCO and a 90° phase shifter for generating the I and Q LO signals to the down- conversionmixersinreceivemode. The 26-MHz crystal oscillator generates the reference frequency for the synthesizer, as well as clocks for theADCandthedigitalpart. A memory mapped register interface is used for data access, configuration, and status request by the CPU. Thedigitalbasebandincludessupportforchannelconfiguration,packethandling,anddatabuffering. Forcompletemoduledescriptions,seethe CC430FamilyUser'sGuide. Copyright©2009–2018,TexasInstrumentsIncorporated DetailedDescription 61 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com 6.2 CPU The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with sevenaddressingmodesforsourceoperandandfouraddressingmodesfordestinationoperand. The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to- registeroperationexecutiontimeisonecycleoftheCPUclock. Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constantgenerator,respectively.Theremainingregistersaregeneral-purposeregisters. Peripherals are connected to the CPU using data, address, and control buses. The peripherals can be managedwithallinstructions. The instruction set consists of the original 51 instructions with three formats and seven address modes and additional instructions for the expanded address range. Each instruction can operate on word and bytedata. 6.3 Operating Modes The CC430 has one active mode and five software-selectable low-power modes of operation. An interrupt event can wake up the device from any of the low-power modes, service the request, and restore back to thelow-powermodeonreturnfromtheinterruptprogram. Softwarecanconfigurethefollowingoperatingmodes: • Activemode(AM) – Allclocksareactive • Low-powermode0(LPM0) – CPUisdisabled – ACLKandSMCLKremainactive,MCLKisdisabled – FLLloopcontrolremainsactive • Low-powermode1(LPM1) – CPUisdisabled – FLLloopcontrolisdisabled – ACLKandSMCLKremainactive,MCLKisdisabled • Low-powermode2(LPM2) – CPUisdisabled – MCLKandFLLloopcontrolandDCOCLKaredisabled – DCgeneratoroftheDCOremainsenabled – ACLKremainsactive • Low-powermode3(LPM3) – CPUisdisabled – MCLK,FLLloopcontrol,andDCOCLKaredisabled – DCgeneratoroftheDCOisdisabled – ACLKremainsactive • Low-powermode4(LPM4) – CPUisdisabled – ACLKisdisabled – MCLK,FLLloopcontrol,andDCOCLKaredisabled – DCgeneratoroftheDCOisdisabled – Crystaloscillatorisstopped – Completedataretention 62 DetailedDescription Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 6.4 Interrupt Vector Addresses The interrupt vectors and the power-up start address are located in the address range 0FFFFh–0FF80h (see Table 6-1). The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence. asd Table6-1.InterruptSources,Flags,andVectors SYSTEM WORD INTERRUPTSOURCE INTERRUPTFLAG PRIORITY INTERRUPT ADDRESS SystemReset Power-Up ExternalReset WDTIFG,KEYV(SYSRSTIV)(1)(2) Reset 0FFFEh 63,highest WatchdogTime-out,Password Violation FlashMemoryPasswordViolation SystemNMI SVMLIFG,SVMHIFG,DLYLIFG,DLYHIFG, PMM VLRLIFG,VLRHIFG,VMAIFG,JMBNIFG, (Non)maskable 0FFFCh 62 VacantMemoryAccess JMBOUTIFG(SYSSNIV)(1)(3) JTAGMailbox UserNMI NMI NMIIFG,OFIFG,ACCVIFG(SYSUNIV)(1)(3) (Non)maskable 0FFFAh 61 OscillatorFault FlashMemoryAccessViolation Comparator_B Comparator_BInterruptFlags(CBIV)(1) Maskable 0FFF8h 60 WatchdogIntervalTimerMode WDTIFG Maskable 0FFF6h 59 USCI_A0ReceiveorTransmit UCA0RXIFG,UCA0TXIFG(UCA0IV)(1) Maskable 0FFF4h 58 UCB0RXIFG,UCB0TXIFG,I2CStatusInterrupt USCI_B0ReceiveorTransmit Flags(UCB0IV)(1) Maskable 0FFF2h 57 ADC12_A ADC12IFG0...ADC12IFG15(ADC12IV)(1) Maskable 0FFF0h 56 (ReservedonCC430F612x) TA0 TA0CCR0CCIFG0 Maskable 0FFEEh 55 TA0CCR1CCIFG1...TA0CCR4CCIFG4, TA0 TA0IFG(TA0IV)(1) Maskable 0FFECh 54 RadioInterfaceInterruptFlags(RF1AIFIV) RF1ACC1101-basedRadio Maskable 0FFEAh 53 RadioCoreInterruptFlags(RF1AIV) DMA DMA0IFG,DMA1IFG,DMA2IFG(DMAIV)(1) Maskable 0FFE8h 52 TA1 TA1CCR0CCIFG0 Maskable 0FFE6h 51 TA1CCR1CCIFG1...TA1CCR2CCIFG2, TA1 TA1IFG(TA1IV)(1) Maskable 0FFE4h 50 I/OPortP1 P1IFG.0toP1IFG.7(P1IV)(1) Maskable 0FFE2h 49 I/OPortP2 P2IFG.0toP2IFG.7(P2IV)(1) Maskable 0FFE0h 48 LCD_B LCD_BInterruptFlags(LCDBIV)(1) Maskable 0FFDEh 47 (ReservedonCC430F513x) RTCRDYIFG,RTCTEVIFG,RTCAIFG, RTC_A RT0PSIFG,RT1PSIFG(RTCIV)(1) Maskable 0FFDCh 46 AES AESRDYIFG Maskable 0FFDAh 45 0FFD8h 44 Reserved Reserved(4) ⋮ ⋮ 0FF80h 0,lowest (1) Multiplesourceflags (2) AresetisgeneratediftheCPUtriestofetchinstructionsfromwithinperipheralspace. (3) (Non)maskable:theindividualinterrupt-enablebitcandisableaninterruptevent,butthegeneral-interruptenablecannotdisableit. (4) Reservedinterruptvectorsataddressesarenotusedinthisdeviceandcanbeusedforregularprogramcodeifnecessary.Tomaintain compatibilitywithotherdevices,reservetheselocations. Copyright©2009–2018,TexasInstrumentsIncorporated DetailedDescription 63 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com 6.5 Memory Organization Table6-2summarizesthememorymapofthedevices. Table6-2.MemoryOrganization CC430F6137 CC430F6135 CC430F6127 CC430F6126(1) CC430F6125 CC430F5133(1) CC430F5137(1) CC430F5135(1) MainMemory Total 32KB 32KB 16KB 8KB (flash) Size Main:Interrupt 00FFFFh–00FF80h 00FFFFh–00FF80h 00FFFFh–00FF80h 00FFFFh–00FF80h vector Main:code 32KB 32KB 16KB 8KB Bank0 memory 00FFFFh–008000h 00FFFFh–008000h 00FFFFh–00C000h 00FFFFh–00E000h Total RAM 4KB 2KB 2KB 2KB Size 2KB Sect1 notavailable notavailable notavailable 002BFFh–002400h 2KB 2KB 2KB 2KB Sect0 0023FFh–001C00h 0023FFh–001C00h 0023FFh–001C00h 0023FFh–001C00h 128B 128B 128B 128B Device 001AFFh–001A80h 001AFFh–001A80h 001AFFh–001A80h 001AFFh–001A80h Descriptor 128B 128B 128B 128B 001A7Fh–001A00h 001A7Fh–001A00h 001A7Fh–001A00h 001A7Fh–001A00h 128B 128B 128B 128B InfoA 0019FFh–001980h 0019FFh–001980h 0019FFh–001980h 0019FFh–001980h 128B 128B 128B 128B InfoB Information 00197Fh–001900h 00197Fh–001900h 00197Fh–001900h 00197Fh–001900h memory(flash) 128B 128B 128B 128B InfoC 0018FFh–001880h 0018FFh–001880h 0018FFh–001880h 0018FFh–001880h 128B 128B 128B 128B InfoD 00187Fh–001800h 00187Fh–001800h 00187Fh–001800h 00187Fh–001800h 512B 512B 512B 512B BSL3 0017FFh–001600h 0017FFh–001600h 0017FFh–001600h 0017FFh–001600h 512B 512B 512B 512B Bootloader BSL2 0015FFh–001400h 0015FFh–001400h 0015FFh–001400h 0015FFh–001400h (BSL)memory (flash) BSL1 512B 512B 512B 512B 0013FFh–001200h 0013FFh–001200h 0013FFh–001200h 0013FFh–001200h 512B 512B 512B 512B BSL0 0011FFh–001000h 0011FFh–001000h 0011FFh–001000h 0011FFh–001000h 4KB 4KB 4KB 4KB Peripherals 000FFFh–0h 000FFFh–0h 000FFFh–0h 000FFFh–0h (1) Allmemoryregionsnotspecifiedherearevacantmemory,andanyaccesstothemcausesaVacantMemoryInterrupt. 64 DetailedDescription Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 6.6 Bootloader (BSL) The BSL enables users to program the flash memory or RAM using various serial interfaces. Table 6-3 lists the pin requirements. Access to the device memory through the BSL is protected by a user-defined password. BSL entry requires a specific entry sequence on the RST/NMI/SBWTDIO and TEST/SBWTCK pins. For a complete description of the features of the BSL and its implementation, see MSP430 ProgrammingWiththeBootloader(BSL). Table6-3.UARTBSLPinRequirementsandFunctions DEVICESIGNAL BSLFUNCTION RST/NMI/SBWTDIO Entrysequencesignal TEST/SBWTCK Entrysequencesignal P1.6 Datatransmit P1.5 Datareceive VCC Powersupply VSS Groundsupply 6.7 JTAG Operation 6.7.1 JTAG Standard Interface The CC430 family supports the standard JTAG interface which requires four signals for sending and receiving data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin is used to enable the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO is required to interface with MSP430 development tools and device programmers. Table 6-4 lists the JTAG pin requirements. For further details on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's Guide. For a complete description of the features of the JTAG interface and its implementation,see MSP430ProgrammingWiththeJTAGInterface. Table6-4.JTAGPinRequirementsandFunctions DEVICESIGNAL DIRECTION FUNCTION PJ.3/TCK IN JTAGclockinput PJ.2/TMS IN JTAGstatecontrol PJ.1/TDI/TCLK IN JTAGdatainput,TCLKinput PJ.0/TDO OUT JTAGdataoutput TEST/SBWTCK IN EnableJTAGpins RST/NMI/SBWTDIO IN Externalreset VCC Powersupply VSS Groundsupply Copyright©2009–2018,TexasInstrumentsIncorporated DetailedDescription 65 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com 6.7.2 Spy-Bi-Wire Interface In addition to the standard JTAG interface, the CC430 family supports the two wire Spy-Bi-Wire interface. Spy-Bi-WirecanbeusedtointerfacewithMSP430developmenttoolsanddeviceprogrammers.Table6-5 liststheSpy-Bi-Wireinterfacepinrequirements.Forfurtherdetailsoninterfacingtodevelopmenttoolsand device programmers, see the MSP430 Hardware Tools User's Guide. For a complete description of the features of the JTAG interface and its implementation, see MSP430 Programming With the JTAG Interface. Table6-5.Spy-Bi-WirePinRequirementsandFunctions DEVICESIGNAL DIRECTION FUNCTION TEST/SBWTCK IN Spy-Bi-Wireclockinput RST/NMI/SBWTDIO IN,OUT Spy-Bi-Wiredatainput/output VCC Powersupply VSS Groundsupply 6.8 Flash Memory The flash memory can be programmed through the JTAG port, Spy-Bi-Wire (SBW), or in-system by the CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features oftheflashmemoryinclude: • Flash memory has n segments of main memory and four segments of information memory (Info A to InfoD)of128byteseach.Eachsegmentinmainmemoryis512bytesinsize. • Segments0tonmaybeerasedinonestep,oreachsegmentmaybeindividuallyerased. • Segments Info A to Info D can be erased individually, or as a group with the main memory segments. SegmentsInfoAtoInfoDarealsocalled informationmemory. • SegmentAcanbelockedseparately. 6.9 RAM The RAM is made up of n sectors. Each sector can be completely powered down to save leakage; however,alldataarelost.FeaturesoftheRAMinclude: • RAMhasnsectorsof2KBeach. • Eachsector0toncanbecompletelydisabled;however,dataretentionislost. • Eachsector0tonautomaticallyenterslowpowerretentionmodewhenpossible. 66 DetailedDescription Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 6.10 Peripherals Peripherals are connected to the CPU through data, address, and control buses. The peripherals can be managedusingallinstructions.Forcompletemoduledescriptions,seethe CC430FamilyUser'sGuide. 6.10.1 Oscillator and System Clock The Unified Clock System (UCS) module includes support for a 32768-Hz watch crystal oscillator, an internal very-low-power low-frequency oscillator (VLO), an internal trimmed low-frequency oscillator (REFO), an integrated internal digitally controlled oscillator (DCO), and a high-frequency crystal oscillator. The UCS module is designed to meet the requirements of both low system cost and low-power consumption. The UCS module features digital frequency locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency.TheinternalDCOprovidesafastturnonclocksourceandstabilizesinlessthan5 µs.TheUCS moduleprovidesthefollowingclocksignals: • Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal, a high-frequency crystal, the internal low-frequencyoscillator(VLO),orthetrimmedlow-frequencyoscillator(REFO). • Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced by same sources made availabletoACLK. • Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be sourcedbysamesourcesmadeavailabletoACLK. • ACLK/n,thebufferedoutputofACLK,ACLK/2,ACLK/4,ACLK/8,ACLK/16,ACLK/32. 6.10.2 Power-Management Module (PMM) The PMM includes an integrated voltage regulator that supplies the core voltage to the device and contains programmable output levels to provide for power optimization. The PMM also includes supply voltage supervisor (SVS) and supply voltage monitoring (SVM) circuitry, as well as brownout protection. The brownout circuit is implemented to provide the proper internal reset signal to the device during power- on and power-off. The SVS/SVM circuitry detects if the supply voltage drops below a user-selectable level and supports both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (the device is not automatically reset). SVS and SVM circuitry is available on the primary supplyandcoresupply. 6.10.3 Digital I/O Uptofive8-bitI/Oportsareimplemented:portsP1throughP5. • AllindividualI/Obitsareindependentlyprogrammable. • Anycombinationofinput,output,andinterruptconditionsispossible. • Programmablepulluporpulldownonallports. • Programmabledrivestrengthonallports. • Edge-selectableinterruptinputcapabilityforalltheeightbitsofportsP1andP2. • Readandwriteaccesstoport-controlregistersissupportedbyallinstructions. • Portscanbeaccessedbyte-wise(P1throughP5)orword-wiseinpairs(PAandPB). Copyright©2009–2018,TexasInstrumentsIncorporated DetailedDescription 67 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com 6.10.4 Port Mapping Controller The port mapping controller allows the flexible and reconfigurable mapping of digital functions to port pins of ports P1 through P3 (see Table 6-6). Table 6-7 lists the default settings for all pins that support port mapping. Table6-6.PortMapping,MnemonicsandFunctions INPUTPINFUNCTION OUTPUTPINFUNCTION VALUE PxMAPyMNEMONIC (PxDIR.y=0) (PxDIR.y=1) 0 PM_NONE None DVSS Comparator_Boutput(onTA0clock PM_CBOUT0 – 1(1) input) PM_TA0CLK TA0clockinput – Comparator_Boutput(onTA1clock PM_CBOUT1 – 2(1) input) PM_TA1CLK TA1clockinput – 3 PM_ACLK None ACLKoutput 4 PM_MCLK None MCLKoutput 5 PM_SMCLK None SMCLKoutput 6 PM_RTCCLK None RTCCLKoutput PM_ADC12CLK – ADC12CLKoutput 7(1) PM_DMAE0 DMAexternaltriggerinput – 8 PM_SVMOUT None SVMoutput 9 PM_TA0CCR0A TA0CCR0captureinputCCI0A TA0CCR0compareoutputOut0 10 PM_TA0CCR1A TA0CCR1captureinputCCI1A TA0CCR1compareoutputOut1 11 PM_TA0CCR2A TA0CCR2captureinputCCI2A TA0CCR2compareoutputOut2 12 PM_TA0CCR3A TA0CCR3captureinputCCI3A TA0CCR3compareoutputOut3 13 PM_TA0CCR4A TA0CCR4captureinputCCI4A TA0CCR4compareoutputOut4 14 PM_TA1CCR0A TA1CCR0captureinputCCI0A TA1CCR0compareoutputOut0 15 PM_TA1CCR1A TA1CCR1captureinputCCI1A TA1CCR1compareoutputOut1 16 PM_TA1CCR2A TA1CCR2captureinputCCI2A TA1CCR2compareoutputOut2 PM_UCA0RXD USCI_A0UARTRXD(directioncontrolledbyUSCI–input) 17(2) PM_UCA0SOMI USCI_A0SPIslaveoutmasterin(directioncontrolledbyUSCI) PM_UCA0TXD USCI_A0UARTTXD(directioncontrolledbyUSCI–output) 18(2) PM_UCA0SIMO USCI_A0SPIslaveinmasterout(directioncontrolledbyUSCI) PM_UCA0CLK USCI_A0clockinput/output(directioncontrolledbyUSCI) 19(3) PM_UCB0STE USCI_B0SPIslavetransmitenable(directioncontrolledbyUSCI–input) PM_UCB0SOMI USCI_B0SPIslaveoutmasterin(directioncontrolledbyUSCI) 20(4) PM_UCB0SCL USCI_B0I2Cclock(opendrainanddirectioncontrolledbyUSCI) PM_UCB0SIMO USCI_B0SPIslaveinmasterout(directioncontrolledbyUSCI) 21(4) PM_UCB0SDA USCI_B0I2Cdata(opendrainanddirectioncontrolledbyUSCI) PM_UCB0CLK USCI_B0clockinput/output(directioncontrolledbyUSCI) 22(5) PM_UCA0STE USCI_A0SPIslavetransmitenable(directioncontrolledbyUSCI–input) 23 PM_RFGDO0 RadioGDO0(directioncontrolledbyRadio) 24 PM_RFGDO1 RadioGDO1(directioncontrolledbyRadio) 25 PM_RFGDO2 RadioGDO2(directioncontrolledbyRadio) (1) InputoroutputfunctionisselectedbythecorrespondingsettingintheportdirectionregisterPxDIR. (2) UARTorSPIfunctionalityisdeterminedbytheselectedUSCImode. (3) UCA0CLKfunctiontakesprecedenceoverUCB0STEfunction.IfthemappedpinisrequiredasUCA0CLKinputoroutput,USCI_B0is forcedto3-wireSPImodeevenif4-wiremodeisselected. (4) SPIorI2CfunctionalityisdeterminedbytheselectedUSCImode.IncasetheI2Cfunctionalityisselectedtheoutputofthemappedpin drivesonlythelogical0toV level. SS (5) UCB0CLKfunctiontakesprecedenceoverUCA0STEfunction.IfthemappedpinisrequiredasUCB0CLKinputoroutput,USCI_A0is forcedto3-wireSPImodeevenif4-wiremodeisselected. 68 DetailedDescription Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 Table6-6.PortMapping,MnemonicsandFunctions(continued) INPUTPINFUNCTION OUTPUTPINFUNCTION VALUE PxMAPyMNEMONIC (PxDIR.y=0) (PxDIR.y=1) 26 Reserved None DVSS 27 Reserved None DVSS 28 Reserved None DVSS 29 Reserved None DVSS 30 Reserved None DVSS 31(0FFh)(6) PM_ANALOG DisablestheoutputdriverandtheinputSchmitt-triggertopreventparasitic crosscurrentswhenapplyinganalogsignals. (6) ThevalueofthePM_ANALOGmnemonicissetto0FFh.Theportmappingregistersareonly5bitswideandtheupperbitsareignored, resultinginareadvalueof31. Table6-7.DefaultMapping INPUTPINFUNCTION OUTPUTPINFUNCTION PIN PxMAPyMNEMONIC (PxDIR.y=0) (PxDIR.y=1) P1.0/P1MAP0 PM_RFGDO0 None RadioGDO0 P1.1/P1MAP1 PM_RFGDO2 None RadioGDO2 USCI_B0SPIslaveoutmasterin(directioncontrolledbyUSCI), P1.2/P1MAP2 PM_UCB0SOMI/PM_UCB0SCL USCI_B0I2Cclock(opendrainanddirectioncontrolledbyUSCI) USCI_B0SPIslaveinmasterout(directioncontrolledbyUSCI), P1.3/P1MAP3 PM_UCB0SIMO/PM_UCB0SDA USCI_B0I2Cdata(opendrainanddirectioncontrolledbyUSCI) USCI_B0clockinput/output(directioncontrolledbyUSCI), P1.4/P1MAP4 PM_UCB0CLK/PM_UCA0STE USCI_A0SPIslavetransmitenable(directioncontrolledbyUSCI–input) USCI_A0UARTRXD(directioncontrolledbyUSCI–input), P1.5/P1MAP5 PM_UCA0RXD/PM_UCA0SOMI USCI_A0SPIslaveoutmasterin(directioncontrolledbyUSCI) USCI_A0UARTTXD(directioncontrolledbyUSCI–output), P1.6/P1MAP6 PM_UCA0TXD/PM_UCA0SIMO USCI_A0SPIslaveinmasterout(directioncontrolledbyUSCI) USCI_A0clockinput/output(directioncontrolledbyUSCI), P1.7/P1MAP7 PM_UCA0CLK/PM_UCB0STE USCI_B0SPIslavetransmitenable(directioncontrolledbyUSCI–input) P2.0/P2MAP0 PM_CBOUT1/PM_TA1CLK TA1clockinput Comparator_Boutput P2.1/P2MAP1 PM_TA1CCR0A TA1CCR0captureinputCCI0A TA1CCR0compareoutputOut0 P2.2/P2MAP2 PM_TA1CCR1A TA1CCR1captureinputCCI1A TA1CCR1compareoutputOut1 P2.3/P2MAP3 PM_TA1CCR2A TA1CCR2captureinputCCI2A TA1CCR2compareoutputOut2 P2.4/P2MAP4 PM_RTCCLK None RTCCLKoutput P2.5/P2MAP5 PM_SVMOUT None SVMoutput P2.6/P2MAP6 PM_ACLK None ACLKoutput P2.7/P2MAP7 PM_ADC12CLK/PM_DMAE0 DMAexternaltriggerinput ADC12CLKoutput P3.0/P3MAP0 PM_CBOUT0/PM_TA0CLK TA0clockinput Comparator_Boutput P3.1/P3MAP1 PM_TA0CCR0A TA0CCR0captureinputCCI0A TA0CCR0compareoutputOut0 P3.2/P3MAP2 PM_TA0CCR1A TA0CCR1captureinputCCI1A TA0CCR1compareoutputOut1 P3.3/P3MAP3 PM_TA0CCR2A TA0CCR2captureinputCCI2A TA0CCR2compareoutputOut2 P3.4/P3MAP4 PM_TA0CCR3A TA0CCR3captureinputCCI3A TA0CCR3compareoutputOut3 P3.5/P3MAP5 PM_TA0CCR4A TA0CCR4captureinputCCI4A TA0CCR4compareoutputOut4 P3.6/P3MAP6 PM_RFGDO1 None RadioGDO1 P3.7/P3MAP7 PM_SMCLK None SMCLKoutput Copyright©2009–2018,TexasInstrumentsIncorporated DetailedDescription 69 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com 6.10.5 System Module (SYS) The SYS module handles many of the system functions within the device. These functions include power on reset and power up clear handling, NMI source selection and management, reset interrupt vector generators (see Table 6-8), bootloader entry mechanisms, and configuration management (device descriptors). SYS also includes a data exchange mechanism through JTAG called a JTAG mailbox that canbeusedintheapplication. Table6-8.SystemModuleInterruptVectorRegisters INTERRUPTVECTORREGISTER ADDRESS INTERRUPTEVENT VALUE PRIORITY Nointerruptpending 00h Brownout(BOR) 02h Highest RST/NMI(POR) 04h PMMSWBOR(BOR) 06h Reserved 08h Securityviolation(BOR) 0Ah SVSL(POR) 0Ch SVSH(POR) 0Eh SVML_OVP(POR) 10h SYSRSTIV,SystemReset 019Eh SVMH_OVP(POR) 12h PMMSWPOR(POR) 14h WDTtime-out(PUC) 16h WDTpasswordviolation(PUC) 18h KEYVflashpasswordviolation(PUC) 1Ah Reserved 1Ch Peripheralareafetch(PUC) 1Eh PMMpasswordviolation(PUC) 20h Reserved 22hto3Eh Lowest Nointerruptpending 00h SVMLIFG 02h Highest SVMHIFG 04h DLYLIFG 06h DLYHIFG 08h SYSSNIV,SystemNMI 019Ch VMAIFG 0Ah JMBINIFG 0Ch JMBOUTIFG 0Eh VLRLIFG 10h VLRHIFG 12h Reserved 14hto1Eh Lowest Nointerruptpending 00h NMIIFG 02h Highest SYSUNIV,UserNMI 019Ah OFIFG 04h ACCVIFG 06h Reserved 08hto1Eh Lowest 70 DetailedDescription Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 6.10.6 DMA Controller The DMA controller allows movement of data from one memory address to another without CPU intervention. Using the DMA controller can increase the throughput of peripheral modules. The DMA controller reduces system power consumption by allowing the CPU to remain in sleep mode, without having to awaken to move data to or from a peripheral. Table 6-9 lists the available triggers for DMA operation. Table6-9.DMATriggerAssignments(1) CHANNEL TRIGGER 0 1 2 0 DMAREQ DMAREQ DMAREQ 1 TA0CCR0CCIFG TA0CCR0CCIFG TA0CCR0CCIFG 2 TA0CCR2CCIFG TA0CCR2CCIFG TA0CCR2CCIFG 3 TA1CCR0CCIFG TA1CCR0CCIFG TA1CCR0CCIFG 4 TA1CCR2CCIFG TA1CCR2CCIFG TA1CCR2CCIFG 5 Reserved Reserved Reserved 6 Reserved Reserved Reserved 7 Reserved Reserved Reserved 8 Reserved Reserved Reserved 9 Reserved Reserved Reserved 10 Reserved Reserved Reserved 11 Reserved Reserved Reserved 12 Reserved Reserved Reserved 13 Reserved Reserved Reserved 14 Reserved Reserved Reserved 15 Reserved Reserved Reserved 16 UCA0RXIFG UCA0RXIFG UCA0RXIFG 17 UCA0TXIFG UCA0TXIFG UCA0TXIFG 18 UCB0RXIFG UCB0RXIFG UCB0RXIFG 19 UCB0TXIFG UCB0TXIFG UCB0TXIFG 20 Reserved Reserved Reserved 21 Reserved Reserved Reserved 22 Reserved Reserved Reserved 23 Reserved Reserved Reserved 24 ADC12IFGx(2) ADC12IFGx(2) ADC12IFGx(2) 25 Reserved Reserved Reserved 26 Reserved Reserved Reserved 27 Reserved Reserved Reserved 28 Reserved Reserved Reserved 29 MPYready MPYready MPYready 30 DMA2IFG DMA0IFG DMA1IFG 31 DMAE0 DMAE0 DMAE0 (1) ReservedDMAtriggersmaybeusedbyotherdevicesinthefamily.ReservedDMAtriggerswillnot causeanyDMAtriggereventwhenselected. (2) OnlyonCC430F613xandCC430F513x.ReservedonCC430F612x. Copyright©2009–2018,TexasInstrumentsIncorporated DetailedDescription 71 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com 6.10.7 Watchdog Timer (WDT_A) The primary function of the watchdog timer is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the timer can be configured as an interval timer and can generate interruptsatselectedtimeintervals. 6.10.8 CRC16 The CRC16 module produces a signature based on a sequence of entered data values and can be used fordatacheckingpurposes.TheCRC16modulesignatureisbasedontheCRC-CCITTstandard. 6.10.9 Hardware Multiplier The multiplication operation is supported by a dedicated peripheral module. The module performs operations with 32-, 24-, 16-, and 8-bit operands. The module supports signed and unsigned multiplication aswellassignedandunsignedmultiply-and-accumulateoperations. 6.10.10 AES128 Accelerator The AES accelerator module performs encryption and decryption of 128-bit data with 128-bit keys accordingtotheAdvancedEncryptionStandard(AES)(FIPSPUB197)inhardware. 6.10.11 Universal Serial Communication Interface (USCI) The USCI module is used for serial data communication. The USCI module supports synchronous communication protocols such as SPI (3-pin or 4-pin) and I2C, and asynchronous communication protocolssuchasUART,enhancedUARTwithautomaticbaud-ratedetection,andIrDA. TheUSCI_AnmoduleprovidessupportforSPI(3-pinor4-pin),UART,enhancedUART,andIrDA. TheUSCI_BnmoduleprovidessupportforSPI(3-pinor4-pin)andI2C. OneUSCI_A0andoneUSCI_B0modulesareimplemented. 72 DetailedDescription Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 6.10.12 TA0 TA0 is a 16-bit timer/counter (Timer_A type) with five capture/compare registers. TA0 can support multiple capture/compares, PWM outputs, and interval timing. TA0 also has extensive interrupt capabilities (see Table 6-10). Interrupts may be generated from the counter on overflow conditions and from each of the capture/compareregisters. Table6-10.TA0SignalConnections MODULEOUTPUT DEVICEOUTPUT DEVICEINPUTSIGNAL MODULEINPUTNAME MODULEBLOCK SIGNAL SIGNAL PM_TA0CLK TACLK ACLK(internal) ACLK Timer NA SMCLK(internal) SMCLK RFCLK/192(1) INCLK PM_TA0CCR0A CCI0A PM_TA0CCR0A DV CCI0B SS CCR0 TA0 DV GND SS DV V CC CC PM_TA0CCR1A CCI1A PM_TA0CCR1A ADC12(internal)(2) CBOUT(internal) CCI1B CCR1 TA1 ADC12SHSx={1} DV GND SS DV V CC CC PM_TA0CCR2A CCI2A PM_TA0CCR2A ACLK(internal) CCI2B CCR2 TA2 DV GND SS DV V CC CC PM_TA0CCR3A CCI3A PM_TA0CCR3A GDO1fromRadio CCI3B (internal) CCR3 TA3 DV GND SS DV V CC CC PM_TA0CCR4A CCI4A PM_TA0CCR4A GDO2fromRadio CCI4B (internal) CCR4 TA4 DV GND SS DV V CC CC (1) IfadifferentRFCLKdividersettingisselectedforaradioGDOoutput,thisdividersettingisalsousedfortheTimer_AINCLK. (2) OnlyonCC430F613xandCC430F513x Copyright©2009–2018,TexasInstrumentsIncorporated DetailedDescription 73 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com 6.10.13 TA1 TA1 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. TA1 can support multiple capture/compares, PWM outputs, and interval timing (see Table 6-11). TA1 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each ofthecapture/compareregisters. Table6-11.TA1SignalConnections DEVICEOUTPUT DEVICEINPUTSIGNAL MODULEINPUTNAME MODULEBLOCK MODULEOUTPUT SIGNAL SIGNAL PZ PM_TA1CLK TACLK ACLK(internal) ACLK Timer NA SMCLK(internal) SMCLK RFCLK/192(1) INCLK PM_TA1CCR0A CCI0A PM_TA1CCR0A RFAsync.Output CCI0B RFAsync.Input(internal) (internal) CCR0 TA0 DV GND SS DV V CC CC PM_TA1CCR1A CCI1A PM_TA1CCR1A CBOUT(internal) CCI1B CCR1 TA1 DV GND SS DV V CC CC PM_TA1CCR2A CCI2A PM_TA1CCR2A ACLK(internal) CCI2B CCR2 TA2 DV GND SS DV V CC CC (1) IfadifferentRFCLKdividersettingisselectedforaradioGDOoutput,thisdividersettingisalsousedfortheTimer_AINCLK. 6.10.14 Real-Time Clock (RTC_A) The RTC_A module can be used as a general-purpose 32-bit counter (counter mode) or as an integrated real-time clock (RTC) (calendar mode). In counter mode, the RTC_A also includes two independent 8-bit timers that can be cascaded to form a 16-bit timer/counter. Both timers can be read and written by software. Calendar mode integrates an internal calendar which compensates for months with less than 31 days and includes leap year correction. The RTC_A also supports flexible alarm functions and offset- calibrationhardware. 6.10.15 Voltage Reference (REF) REF generates all of the critical reference voltages that can be used by the various analog peripherals in thedevice.TheseperipheralsincludetheADC12_A,LCD_B,andCOMP_Bmodules. 6.10.16 LCD_B (Only CC430F613x and CC430F612x) The LCD_B driver generates the segment and common signals required to drive a liquid crystal display (LCD). The LCD_B controller has dedicated data memories to hold segment drive information. Common and segment signals are generated as defined by the mode. Static, 2-, 3-, and 4-mux LCDs are supported. The module can provide a LCD voltage independent of the supply voltage with its integrated charge pump. It is possible to control the level of the LCD voltage and thus contrast by software. The modulealsoprovidesanautomaticblinkingcapabilityforindividualsegments. 74 DetailedDescription Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 6.10.17 Comparator_B The primary function of the Comparator_B module is to support precision slope analog-to-digital conversions,batteryvoltagesupervision,andmonitoringofexternalanalogsignals. 6.10.18 ADC12_A (Only CC430F613x and CC430F513x) The ADC12_A module supports fast 12-bit analog-to-digital conversions. The module implements a 12-bit SAR core, sample select control, reference generator, and a 16-word conversion-and-control buffer. The conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored withoutanyCPUintervention. 6.10.19 Embedded Emulation Module (EEM) (S Version) TheEEMsupportsreal-timein-systemdebugging.TheSversionoftheEEMhasthefollowingfeatures: • Threehardwaretriggersorbreakpointsonmemoryaccess • OnehardwaretriggerorbreakpointonCPUregisterwriteaccess • Uptofourhardwaretriggerscanbecombinedtoformcomplextriggersorbreakpoints • Onecyclecounter • Clockcontrolonmodulelevel Copyright©2009–2018,TexasInstrumentsIncorporated DetailedDescription 75 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com 6.10.20 Peripheral File Map Table6-12liststhebaseaddressfortheregistersofeachperipheral. Table6-12.Peripherals OFFSETADDRESS MODULENAME BASEADDRESS RANGE SpecialFunctions(seeTable6-13) 0100h 000h–01Fh PMM(seeTable6-14) 0120h 000h–00Fh FlashControl(seeTable6-15) 0140h 000h–00Fh CRC16(seeTable6-16) 0150h 000h–007h RAMControl(seeTable6-17) 0158h 000h–001h Watchdog(seeTable6-18) 015Ch 000h–001h UCS(seeTable6-19) 0160h 000h–01Fh SYS(seeTable6-20) 0180h 000h–01Fh SharedReference(seeTable6-21) 01B0h 000h–001h PortMappingControl(seeTable6-22) 01C0h 000h–007h PortMappingPortP1(seeTable6-23) 01C8h 000h–007h PortMappingPortP2(seeTable6-24) 01D0h 000h–007h PortMappingPortP3(seeTable6-25) 01D8h 000h–007h PortP1,P2(seeTable6-26) 0200h 000h–01Fh PortP3,P4(seeTable6-27) 0220h 000h–01Fh (P4notavailableonCC430F513x) PortP5(seeTable6-28) 0240h 000h–01Fh PortPJ(seeTable6-29) 0320h 000h–01Fh TA0(seeTable6-30) 0340h 000h–03Fh TA1(seeTable6-31) 0380h 000h–03Fh RTC_A(seeTable6-32) 04A0h 000h–01Fh 32-BitHardwareMultiplier(seeTable6-33) 04C0h 000h–02Fh DMAModuleControl(seeTable6-34) 0500h 000h–00Fh DMAChannel0(seeTable6-35) 0510h 000h–00Fh DMAChannel1(seeTable6-36) 0520h 000h–00Fh DMAChannel2(seeTable6-37) 0530h 000h–00Fh USCI_A0(seeTable6-38) 05C0h 000h–01Fh USCI_B0(seeTable6-39) 05E0h 000h–01Fh ADC12(seeTable6-40) 0700h 000h–03Fh (onlyCC430F613xandCC430F513x) Comparator_B(seeTable6-41) 08C0h 000h–00Fh AESAccelerator(seeTable6-42) 09C0h 000h–00Fh LCD_B(seeTable6-43) 0A00h 000h–05Fh (onlyCC430F613xandCC430F612x) RadioInterface(seeTable6-44) 0F00h 000h–03Fh 76 DetailedDescription Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 Table6-13.SpecialFunctionRegisters(BaseAddress:0100h) REGISTERDESCRIPTION ACRONYM OFFSET SFRinterruptenable SFRIE1 00h SFRinterruptflag SFRIFG1 02h SFRresetpincontrol SFRRPCR 04h Table6-14.PMMRegisters(BaseAddress:0120h) REGISTERDESCRIPTION ACRONYM OFFSET PMMcontrol0 PMMCTL0 00h PMMcontrol1 PMMCTL1 02h SVShighsidecontrol SVSMHCTL 04h SVSlowsidecontrol SVSMLCTL 06h PMMinterruptflags PMMIFG 0Ch PMMinterruptenable PMMIE 0Eh PMMpowermode5control PM5CTL0 10h Table6-15.FlashControlRegisters(BaseAddress:0140h) REGISTERDESCRIPTION ACRONYM OFFSET Flashcontrol1 FCTL1 00h Flashcontrol3 FCTL3 04h Flashcontrol4 FCTL4 06h Table6-16.CRC16Registers(BaseAddress:0150h) REGISTERDESCRIPTION ACRONYM OFFSET CRCdatainput CRC16DI 00h CRCinitializationandresult CRCINIRES 04h Table6-17.RAMControlRegisters(BaseAddress:0158h) REGISTERDESCRIPTION ACRONYM OFFSET RAMcontrol0 RCCTL0 00h Table6-18.WatchdogRegisters(BaseAddress:015Ch) REGISTERDESCRIPTION ACRONYM OFFSET Watchdogtimercontrol WDTCTL 00h Table6-19.UCSRegisters(BaseAddress:0160h) REGISTERDESCRIPTION ACRONYM OFFSET UCScontrol0 UCSCTL0 00h UCScontrol1 UCSCTL1 02h UCScontrol2 UCSCTL2 04h UCScontrol3 UCSCTL3 06h UCScontrol4 UCSCTL4 08h UCScontrol5 UCSCTL5 0Ah UCScontrol6 UCSCTL6 0Ch UCScontrol7 UCSCTL7 0Eh UCScontrol8 UCSCTL8 10h Copyright©2009–2018,TexasInstrumentsIncorporated DetailedDescription 77 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com Table6-20.SYSRegisters(BaseAddress:0180h) REGISTERDESCRIPTION ACRONYM OFFSET Systemcontrol SYSCTL 00h Bootloaderconfigurationarea SYSBSLC 02h JTAGmailboxcontrol SYSJMBC 06h JTAGmailboxinput0 SYSJMBI0 08h JTAGmailboxinput1 SYSJMBI1 0Ah JTAGmailboxoutput0 SYSJMBO0 0Ch JTAGmailboxoutput1 SYSJMBO1 0Eh Buserrorvectorgenerator SYSBERRIV 18h UserNMIvectorgenerator SYSUNIV 1Ah SystemNMIvectorgenerator SYSSNIV 1Ch Resetvectorgenerator SYSRSTIV 1Eh Table6-21.SharedReferenceRegisters(BaseAddress:01B0h) REGISTERDESCRIPTION ACRONYM OFFSET Sharedreferencecontrol REFCTL 00h Table6-22.PortMappingControlRegisters(BaseAddress:01C0h) REGISTERDESCRIPTION ACRONYM OFFSET Portmappingkey PMAPKEYID 00h Portmappingcontrol PMAPCTL 02h Table6-23.PortMappingPortP1Registers(BaseAddress:01C8h) REGISTERDESCRIPTION ACRONYM OFFSET PortP1.0mapping P1MAP0 00h PortP1.1mapping P1MAP1 01h PortP1.2mapping P1MAP2 02h PortP1.3mapping P1MAP3 03h PortP1.4mapping P1MAP4 04h PortP1.5mapping P1MAP5 05h PortP1.6mapping P1MAP6 06h PortP1.7mapping P1MAP7 07h Table6-24.PortMappingPortP2Registers(BaseAddress:01D0h) REGISTERDESCRIPTION ACRONYM OFFSET PortP2.0mapping P2MAP0 00h PortP2.1mapping P2MAP1 01h PortP2.2mapping P2MAP2 02h PortP2.3mapping P2MAP3 03h PortP2.4mapping P2MAP4 04h PortP2.5mapping P2MAP5 05h PortP2.6mapping P2MAP6 06h PortP2.7mapping P2MAP7 07h 78 DetailedDescription Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 Table6-25.PortMappingPortP3Registers(BaseAddress:01D8h) REGISTERDESCRIPTION ACRONYM OFFSET PortP3.0mapping P3MAP0 00h PortP3.1mapping P3MAP1 01h PortP3.2mapping P3MAP2 02h PortP3.3mapping P3MAP3 03h PortP3.4mapping P3MAP4 04h PortP3.5mapping P3MAP5 05h PortP3.6mapping P3MAP6 06h PortP3.7mapping P3MAP7 07h Table6-26.PortP1,P2Registers(BaseAddress:0200h) REGISTERDESCRIPTION ACRONYM OFFSET PortP1input P1IN 00h PortP1output P1OUT 02h PortP1direction P1DIR 04h PortP1pullup/pulldownenable P1REN 06h PortP1drivestrength P1DS 08h PortP1selection P1SEL 0Ah PortP1interruptvectorword P1IV 0Eh PortP1interruptedgeselect P1IES 18h PortP1interruptenable P1IE 1Ah PortP1interruptflag P1IFG 1Ch PortP2input P2IN 01h PortP2output P2OUT 03h PortP2direction P2DIR 05h PortP2pullup/pulldownenable P2REN 07h PortP2drivestrength P2DS 09h PortP2selection P2SEL 0Bh PortP2interruptvectorword P2IV 1Eh PortP2interruptedgeselect P2IES 19h PortP2interruptenable P2IE 1Bh PortP2interruptflag P2IFG 1Dh Table6-27.PortP3,P4Registers(BaseAddress:0220h) REGISTERDESCRIPTION ACRONYM OFFSET PortP3input P3IN 00h PortP3output P3OUT 02h PortP3direction P3DIR 04h PortP3pullup/pulldownenable P3REN 06h PortP3drivestrength P3DS 08h PortP3selection P3SEL 0Ah PortP4input P4IN 01h PortP4output P4OUT 03h PortP4direction P4DIR 05h PortP4pullup/pulldownenable P4REN 07h PortP4drivestrength P4DS 09h PortP4selection P4SEL 0Bh Copyright©2009–2018,TexasInstrumentsIncorporated DetailedDescription 79 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com Table6-28.PortP5Registers(BaseAddress:0240h) REGISTERDESCRIPTION ACRONYM OFFSET PortP5input P5IN 00h PortP5output P5OUT 02h PortP5direction P5DIR 04h PortP5pullup/pulldownenable P5REN 06h PortP5drivestrength P5DS 08h PortP5selection P5SEL 0Ah Table6-29.PortJRegisters(BaseAddress:0320h) REGISTERDESCRIPTION ACRONYM OFFSET PortPJinput PJIN 00h PortPJoutput PJOUT 02h PortPJdirection PJDIR 04h PortPJpullup/pulldownenable PJREN 06h PortPJdrivestrength PJDS 08h Table6-30.TA0Registers(BaseAddress:0340h) REGISTERDESCRIPTION ACRONYM OFFSET TA0control TA0CTL 00h Capture/comparecontrol0 TA0CCTL0 02h Capture/comparecontrol1 TA0CCTL1 04h Capture/comparecontrol2 TA0CCTL2 06h Capture/comparecontrol3 TA0CCTL3 08h Capture/comparecontrol4 TA0CCTL4 0Ah TA0counter TA0R 10h Capture/compare0 TA0CCR0 12h Capture/compare1 TA0CCR1 14h Capture/compare2 TA0CCR2 16h Capture/compare3 TA0CCR3 18h Capture/compare4 TA0CCR4 1Ah TA0expansion0 TA0EX0 20h TA0interruptvector TA0IV 2Eh Table6-31.TA1Registers(BaseAddress:0380h) REGISTERDESCRIPTION ACRONYM OFFSET TA1control TA1CTL 00h Capture/comparecontrol0 TA1CCTL0 02h Capture/comparecontrol1 TA1CCTL1 04h Capture/comparecontrol2 TA1CCTL2 06h TA1counter TA1R 10h Capture/compare0 TA1CCR0 12h Capture/compare1 TA1CCR1 14h Capture/compare2 TA1CCR2 16h TA1expansion0 TA1EX0 20h TA1interruptvector TA1IV 2Eh 80 DetailedDescription Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 Table6-32.Real-TimeClockRegisters(BaseAddress:04A0h) REGISTERDESCRIPTION ACRONYM OFFSET RTCcontrol0 RTCCTL0 00h RTCcontrol1 RTCCTL1 01h RTCcontrol2 RTCCTL2 02h RTCcontrol3 RTCCTL3 03h RTCprescaler0control RTCPS0CTL 08h RTCprescaler1control RTCPS1CTL 0Ah RTCprescaler0 RTCPS0 0Ch RTCprescaler1 RTCPS1 0Dh RTCinterruptvectorword RTCIV 0Eh RTCseconds/counter1 RTCSEC/RTCNT1 10h RTCminutes/counter2 RTCMIN/RTCNT2 11h RTChours/counter3 RTCHOUR/RTCNT3 12h RTCdayofweek/counter4 RTCDOW/RTCNT4 13h RTCdays RTCDAY 14h RTCmonth RTCMON 15h RTCyearlow RTCYEARL 16h RTCyearhigh RTCYEARH 17h RTCalarmminutes RTCAMIN 18h RTCalarmhours RTCAHOUR 19h RTCalarmdayofweek RTCADOW 1Ah RTCalarmdays RTCADAY 1Bh Table6-33.32-BitHardwareMultiplierRegisters(BaseAddress:04C0h) REGISTERDESCRIPTION ACRONYM OFFSET 16-bitoperand1–multiply MPY 00h 16-bitoperand1–signedmultiply MPYS 02h 16-bitoperand1–multiplyaccumulate MAC 04h 16-bitoperand1–signedmultiplyaccumulate MACS 06h 16-bitoperand2 OP2 08h 16×16resultlowword RESLO 0Ah 16×16resulthighword RESHI 0Ch 16×16sumextension SUMEXT 0Eh 32-bitoperand1–multiplylowword MPY32L 10h 32-bitoperand1–multiplyhighword MPY32H 12h 32-bitoperand1–signedmultiplylowword MPYS32L 14h 32-bitoperand1–signedmultiplyhighword MPYS32H 16h 32-bitoperand1–multiplyaccumulatelowword MAC32L 18h 32-bitoperand1–multiplyaccumulatehighword MAC32H 1Ah 32-bitoperand1–signedmultiplyaccumulatelowword MACS32L 1Ch 32-bitoperand1–signedmultiplyaccumulatehighword MACS32H 1Eh 32-bitoperand2–lowword OP2L 20h 32-bitoperand2–highword OP2H 22h 32×32result0–leastsignificantword RES0 24h 32×32result1 RES1 26h 32×32result2 RES2 28h 32×32result3–mostsignificantword RES3 2Ah MPY32control0 MPY32CTL0 2Ch Copyright©2009–2018,TexasInstrumentsIncorporated DetailedDescription 81 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com Table6-34.DMAModuleControlRegisters(BaseAddress:0500h) REGISTERDESCRIPTION ACRONYM OFFSET DMAmodulecontrol0 DMACTL0 00h DMAmodulecontrol1 DMACTL1 02h DMAmodulecontrol2 DMACTL2 04h DMAmodulecontrol3 DMACTL3 06h DMAmodulecontrol4 DMACTL4 08h DMAinterruptvector DMAIV 0Ah Table6-35.DMAChannel0Registers(BaseAddress:0510h) REGISTERDESCRIPTION ACRONYM OFFSET DMAchannel0control DMA0CTL 00h DMAchannel0sourceaddresslow DMA0SAL 02h DMAchannel0sourceaddresshigh DMA0SAH 04h DMAchannel0destinationaddresslow DMA0DAL 06h DMAchannel0destinationaddresshigh DMA0DAH 08h DMAchannel0transfersize DMA0SZ 0Ah Table6-36.DMAChannel1Registers(BaseAddress:0520h) REGISTERDESCRIPTION ACRONYM OFFSET DMAchannel1control DMA1CTL 00h DMAchannel1sourceaddresslow DMA1SAL 02h DMAchannel1sourceaddresshigh DMA1SAH 04h DMAchannel1destinationaddresslow DMA1DAL 06h DMAchannel1destinationaddresshigh DMA1DAH 08h DMAchannel1transfersize DMA1SZ 0Ah Table6-37.DMAChannel2Registers(BaseAddress:0530h) REGISTERDESCRIPTION ACRONYM OFFSET DMAchannel2control DMA2CTL 00h DMAchannel2sourceaddresslow DMA2SAL 02h DMAchannel2sourceaddresshigh DMA2SAH 04h DMAchannel2destinationaddresslow DMA2DAL 06h DMAchannel2destinationaddresshigh DMA2DAH 08h DMAchannel2transfersize DMA2SZ 0Ah 82 DetailedDescription Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 Table6-38.USCI_A0Registers(BaseAddress:05C0h) REGISTERDESCRIPTION ACRONYM OFFSET USCIcontrol1 UCA0CTL1 00h USCIcontrol0 UCA0CTL0 01h USCIbaudrate0 UCA0BR0 06h USCIbaudrate1 UCA0BR1 07h USCImodulationcontrol UCA0MCTL 08h USCIstatus UCA0STAT 0Ah USCIreceivebuffer UCA0RXBUF 0Ch USCItransmitbuffer UCA0TXBUF 0Eh USCILINcontrol UCA0ABCTL 10h USCIIrDAtransmitcontrol UCA0IRTCTL 12h USCIIrDAreceivecontrol UCA0IRRCTL 13h USCIinterruptenable UCA0IE 1Ch USCIinterruptflags UCA0IFG 1Dh USCIinterruptvectorword UCA0IV 1Eh Table6-39.USCI_B0Registers(BaseAddress:05E0h) REGISTERDESCRIPTION ACRONYM OFFSET USCIsynchronouscontrol1 UCB0CTL1 00h USCIsynchronouscontrol0 UCB0CTL0 01h USCIsynchronousbitrate0 UCB0BR0 06h USCIsynchronousbitrate1 UCB0BR1 07h USCIsynchronousstatus UCB0STAT 0Ah USCIsynchronousreceivebuffer UCB0RXBUF 0Ch USCIsynchronoustransmitbuffer UCB0TXBUF 0Eh USCII2Cownaddress UCB0I2COA 10h USCII2Cslaveaddress UCB0I2CSA 12h USCIinterruptenable UCB0IE 1Ch USCIinterruptflags UCB0IFG 1Dh USCIinterruptvectorword UCB0IV 1Eh Copyright©2009–2018,TexasInstrumentsIncorporated DetailedDescription 83 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com Table6-40.ADC12_ARegisters(BaseAddress:0700h) REGISTERDESCRIPTION ACRONYM OFFSET Control0 ADC12CTL0 00h Control1 ADC12CTL1 02h Control2 ADC12CTL2 04h Interruptflag ADC12IFG 0Ah Interruptenable ADC12IE 0Ch Interruptvectorword ADC12IV 0Eh ADCmemory-control0 ADC12MCTL0 10h ADCmemory-control1 ADC12MCTL1 11h ADCmemory-control2 ADC12MCTL2 12h ADCmemory-control3 ADC12MCTL3 13h ADCmemory-control4 ADC12MCTL4 14h ADCmemory-control5 ADC12MCTL5 15h ADCmemory-control6 ADC12MCTL6 16h ADCmemory-control7 ADC12MCTL7 17h ADCmemory-control8 ADC12MCTL8 18h ADCmemory-control9 ADC12MCTL9 19h ADCmemory-control10 ADC12MCTL10 1Ah ADCmemory-control11 ADC12MCTL11 1Bh ADCmemory-control12 ADC12MCTL12 1Ch ADCmemory-control13 ADC12MCTL13 1Dh ADCmemory-control14 ADC12MCTL14 1Eh ADCmemory-control15 ADC12MCTL15 1Fh Conversionmemory0 ADC12MEM0 20h Conversionmemory1 ADC12MEM1 22h Conversionmemory2 ADC12MEM2 24h Conversionmemory3 ADC12MEM3 26h Conversionmemory4 ADC12MEM4 28h Conversionmemory5 ADC12MEM5 2Ah Conversionmemory6 ADC12MEM6 2Ch Conversionmemory7 ADC12MEM7 2Eh Conversionmemory8 ADC12MEM8 30h Conversionmemory9 ADC12MEM9 32h Conversionmemory10 ADC12MEM10 34h Conversionmemory11 ADC12MEM11 36h Conversionmemory12 ADC12MEM12 38h Conversionmemory13 ADC12MEM13 3Ah Conversionmemory14 ADC12MEM14 3Ch Conversionmemory15 ADC12MEM15 3Eh 84 DetailedDescription Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 Table6-41.Comparator_BRegisters(BaseAddress:08C0h) REGISTERDESCRIPTION ACRONYM OFFSET Comp_Bcontrol0 CBCTL0 00h Comp_Bcontrol1 CBCTL1 02h Comp_Bcontrol2 CBCTL2 04h Comp_Bcontrol3 CBCTL3 06h Comp_Binterrupt CBINT 0Ch Comp_Binterruptvectorword CBIV 0Eh Table6-42.AESAcceleratorRegisters(BaseAddress:09C0h) REGISTERDESCRIPTION ACRONYM OFFSET AESacceleratorcontrol0 AESACTL0 00h Reserved 02h AESacceleratorstatus AESASTAT 04h AESacceleratorkey AESAKEY 06h AESacceleratordatain AESADIN 008h AESacceleratordataout AESADOUT 00Ah Table6-43.LCD_BRegisters(BaseAddress:0A00h) REGISTERDESCRIPTION ACRONYM OFFSET LCD_Bcontrol0 LCDBCTL0 000h LCD_Bcontrol1 LCDBCTL1 002h LCD_Bblinkingcontrol LCDBBLKCTL 004h LCD_Bmemorycontrol LCDBMEMCTL 006h LCD_Bvoltagecontrol LCDBVCTL 008h LCD_Bportcontrol0 LCDBPCTL0 00Ah LCD_Bportcontrol1 LCDBPCTL1 00Ch LCD_Bchargepumpcontrol LCDBCTL0 012h LCD_Binterruptvectorword LCDBIV 01Eh LCD_Bmemory1 LCDM1 020h LCD_Bmemory2 LCDM2 021h ... LCD_Bmemory14 LCDM14 02Dh LCD_Bblinkingmemory1 LCDBM1 040h LCD_Bblinkingmemory2 LCDBM2 041h ... LCD_Bblinkingmemory14 LCDBM14 04Dh Copyright©2009–2018,TexasInstrumentsIncorporated DetailedDescription 85 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com Table6-44.RadioInterfaceRegisters(BaseAddress:0F00h) REGISTERDESCRIPTION ACRONYM OFFSET Radiointerfacecontrol0 RF1AIFCTL0 00h Radiointerfacecontrol1 RF1AIFCTL1 02h Radiointerfaceerrorflag RF1AIFERR 06h Radiointerfaceerrorvectorword RF1AIFERRV 0Ch Radiointerfaceinterruptvectorword RF1AIFIV 0Eh Radioinstructionword RF1AINSTRW 10h Radioinstructionword,1-byteauto-read RF1AINSTR1W 12h Radioinstructionword,2-byteauto-read RF1AINSTR2W 14h Radiodatain RF1ADINW 16h Radiostatusword RF1ASTATW 20h Radiostatusword,1-byteauto-read RF1ASTAT1W 22h Radiostatusword,2-byteauto-read RF1AISTAT2W 24h Radiodataout RF1ADOUTW 28h Radiodataout,1-byteauto-read RF1ADOUT1W 2Ah Radiodataout,2-byteauto-read RF1ADOUT2W 2Ch Radiocoresignalinput RF1AIN 30h Radiocoreinterruptflag RF1AIFG 32h Radiocoreinterruptedgeselect RF1AIES 34h Radiocoreinterruptenable RF1AIE 36h Radiocoreinterruptvectorword RF1AIV 38h 86 DetailedDescription Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 6.11 Input/Output Diagrams 6.11.1 Port P1 (P1.0 to P1.4) Input/Output With Schmitt Trigger Figure6-2showstheportdiagram.Table6-45 summarizestheselectionofthepinfunctions. S18...S22 (not available onCC430F513x) LCDS18...LCDS22 Pad Logic P1REN.x P1MAP.x = PMAP_ANALOG DVSS 0 DVCC 1 1 P1DIR.x 0 Direction from Port Mapping 1 0: Input 1: Output P1OUT.x 0 from Port Mapping 1 P1.0/P1MAP0(/S18) P1DS.x P1.1/P1MAP1(/S19) P1SEL.x 0: Low drive P1.2/P1MAP2(/S20) 1: High drive P1.3/P1MAP3(/S21) P1IN.x P1.4/P1MAP4(/S22) EN Bus Keeper to Port Mapping D P1IE.x EN P1IRQ.x Q P1IFG.x Set P1SEL.x Interrupt Edge P1IES.x Select CC430F513xdevicesdonotprovideLCDfunctionalityonportP1pins. Figure6-2.PortP1(P1.0toP1.4)Diagram Copyright©2009–2018,TexasInstrumentsIncorporated DetailedDescription 87 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com Table6-45.PortP1(P1.0toP1.4)PinFunctions CONTROLBITSORSIGNALS(1) PINNAME(P1.x) x FUNCTION LCDS18to P1DIR.x P1SEL.x P1MAPx LCDS22(2) P1.0(I/O) I:0;O:1 0 X 0 Mappedsecondarydigitalfunction–seeTable6-6 0;1(3) 1 ≤30(3) 0 P1.0/P1MAP/S18 0 OutputdriverandinputSchmitttriggerdisabled X 1 =31 0 S18(notavailableonCC430F513x) X X X 1 P1.1(I/O) I:0;O:1 0 X 0 Mappedsecondarydigitalfunction–seeTable6-6 0;1(3) 1 ≤30(3) 0 P1.1/P1MAP1/S19 1 OutputdriverandinputSchmitttriggerdisabled X 1 =31 0 S19(notavailableonCC430F513x) X X X 1 P1.2(I/O) I:0;O:1 0 X 0 Mappedsecondarydigitalfunction–seeTable6-6 0;1(3) 1 ≤30(3) 0 P1.2/P1MAP2/S20 2 OutputdriverandinputSchmitttriggerdisabled X 1 =31 0 S22(notavailableonCC430F513x) X X X 1 P1.3(I/O) I:0;O:1 0 X 0 Mappedsecondarydigitalfunction–seeTable6-6 0;1(3) 1 ≤30(3) 0 P1.3/P1MAP3/S21 3 OutputdriverandinputSchmitttriggerdisabled X 1 =31 0 S21(notavailableonCC430F513x) X X X 1 P1.4(I/O) I:0;O:1 0 X 0 Mappedsecondarydigitalfunction–seeTable6-6 0;1(3) 1 ≤30(3) 0 P1.4/P1MAP4/S22 4 OutputdriverandinputSchmitttriggerdisabled X 1 =31 0 S22(notavailableonCC430F513x) X X X 1 (1) X=don'tcare (2) LCDSxnotavailableinCC430F513x. (3) Accordingtomappedfunction–seeTable6-6. 88 DetailedDescription Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 6.11.2 Port P1 (P1.5 to P1.7) Input/Output With Schmitt Trigger Figure6-3showstheportdiagram.Table6-46 summarizestheselectionofthepinfunctions. to LCD_B (n/a CC430F513x) Pad Logic P1REN.x P1MAP.x = PMAP_ANALOG DVSS 0 DVCC 1 1 P1DIR.x 0 Direction from Port Mapping 1 0: Input 1: Output P1OUT.x 0 from Port Mapping 1 P1.5/P1MAP5(/R23) P1DS.x P1.6/P1MAP6(/R13) P1SEL.x 0: Low drive P1.7/P1MAP7(/R03) 1: High drive P1IN.x EN Bus Keeper to Port Mapping D P1IE.x EN P1IRQ.x Q P1IFG.x Set P1SEL.x Interrupt Edge P1IES.x Select CC430F513xdevicesdonotprovideLCDfunctionalityonportP1pins. Figure6-3.PortP1(P1.5toP1.7)Diagram Copyright©2009–2018,TexasInstrumentsIncorporated DetailedDescription 89 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com Table6-46.PortP1(P1.5toP1.7)PinFunctions CONTROLBITSORSIGNALS(1) PINNAME(P1.x) x FUNCTION P1DIR.x P1SEL.x P1MAPx P1.5(I/O) I:0;O:1 0 X P1.5/P1MAP5/R23 5 Mappedsecondarydigitalfunction–seeTable6-6 0;1(2) 1 ≤30(2) R23(3)(notavailableonCC430F513x) X 1 =31 P1.6(I/O) I:0;O:1 0 X P1.6/P1MAP6/R13/ 6 Mappedsecondarydigitalfunction–seeTable6-6 0;1(2) 1 ≤30(2) LCDREF R13/LCDREF(3)(notavailableonCC430F513x) X 1 =31 P1.7(I/O) I:0;O:1 0 X P1.7/P1MAP7/R03 7 Mappedsecondarydigitalfunction–seeTable6-6 0;1(2) 1 ≤30(2) R03(3)(notavailableonCC430F513x) X 1 =31 (1) X=don'tcare (2) Accordingtomappedfunction–seeTable6-6. (3) SettingP1SEL.xbittogetherwithP1MAPx=PM_ANALOGdisablestheoutputdriverandtheinputSchmitttrigger. 90 DetailedDescription Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 6.11.3 Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger Figure 6-4 through Figure 6-6 show the port diagrams. Table 6-47 summarizes the selection of the pin functions. Pad Logic ToADC12 (n/a CC430F612x) INCHx = x To Comparator_B from Comparator_B CBPD.x P2REN.x P2MAP.x = PMAP_ANALOG DVSS 0 DVCC 1 1 P2DIR.x 0 Direction from Port Mapping 1 0: Input 1: Output P2OUT.x 0 from Port Mapping 1 P2.0/P2MAP0/CB0(/A0) P2DS.x P2.1/P2MAP2/CB1(/A1) P2SEL.x 0: Low drive P2.2/P2MAP2/CB2(/A2) 1: High drive P2.3/P2MAP3/CB3(/A3) P2IN.x EN Bus Keeper to Port Mapping D P2IE.x EN P2IRQ.x Q P2IFG.x Set P2SEL.x Interrupt Edge P2IES.x Select Figure6-4.PortP2(P2.0toP2.3)Diagram Copyright©2009–2018,TexasInstrumentsIncorporated DetailedDescription 91 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com Pad Logic To or from Reference (not available on CC430F612x) ToADC12 (not available onCC430F612x) INCHx = x To Comparator_B from Comparator_B CBPD.x P2REN.x P2MAP.x = PMAP_ANALOG DVSS 0 DVCC 1 1 P2DIR.x 0 Direction from Port Mapping 1 0: Input 1: Output P2OUT.x 0 from Port Mapping 1 P2.4/P2MAP4/CB4(/A4/VREF-/VeREF-) P2DS.x P2SEL.x 0: Low drive P2.5/P2MAP5/CB5(/A5/VREF+/VeRF+) 1: High drive P2IN.x EN Bus Keeper to Port Mapping D P2IE.x EN P2IRQ.x Q P2IFG.x Set P2SEL.x Interrupt Edge P2IES.x Select Figure6-5.PortP2(P2.4andP2.5)Diagram 92 DetailedDescription Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 Pad Logic ToADC12 (n/a CC430F513x) INCHx = x To Comparator_B (n/a CC430F513x) from Comparator_B CBPD.x (n/a CC430F513x) P2REN.x P2MAP.x = PMAP_ANALOG DVSS 0 DVCC 1 1 P2DIR.x 0 Direction from Port Mapping 1 0: Input 1: Output P2OUT.x 0 from Port Mapping 1 P2.6/P2MAP6(/CB6/A6) P2DS.x P2.7/P2MAP7(/CB7/A7) P2SEL.x 0: Low drive 1: High drive P2IN.x EN Bus Keeper to Port Mapping D P2IE.x EN P2IRQ.x Q P2IFG.x Set P2SEL.x Interrupt Edge P2IES.x Select CC430F513xdevicesdonotprovideanalogfunctionalityonportP2.6andP2.7pins. Figure6-6.PortP2(P2.6andP2.7)Diagram Copyright©2009–2018,TexasInstrumentsIncorporated DetailedDescription 93 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com Table6-47.PortP2(P2.0toP2.7)PinFunctions CONTROLBITSORSIGNALS(1) PINNAME(P2.x) x FUNCTION P2DIR.x P2SEL.x P2MAPx CBPD.x P2.0(I/O) I:0;O:1 0 X 0 P2.0/P2MAP0/CB0 Mappedsecondarydigitalfunction–seeTable6-6 0;1(2) 1 ≤30(2) 0 0 (/A0) A0(notavailableonCC430F612x)(3) X 1 =31 X CB0(4) X X X 1 P2.1(I/O) I:0;O:1 0 X 0 P2.1/P2MAP1/CB1 Mappedsecondarydigitalfunction–seeTable6-6 0;1(2) 1 ≤30(2) 0 1 (/A1) A1(notavailableonCC430F612x)(3) X 1 =31 X CB1(4) X X X 1 P2.2(I/O) I:0;O:1 0 X 0 P2.2/P2MAP2/CB2 Mappedsecondarydigitalfunction–seeTable6-6 0;1(2) 1 ≤30(2) 0 2 (/A2) A2(notavailableonCC430F612x)(3) X 1 =31 X CB2(4) X X X 1 P2.3(I/O) I:0;O:1 0 X 0 P2.3/P2MAP3/CB3 Mappedsecondarydigitalfunction–seeTable6-6 0;1(2) 1 ≤30(2) 0 3 (/A3) A3(notavailableonCC430F612x)(3) X 1 =31 X CB3(4) X X X 1 P2.4(I/O) I:0;O:1 0 X 0 P2.4/P2MAP4/CB4 Mappedsecondarydigitalfunction–seeTable6-6 0;1(2) 1 ≤30(2) 0 4 (/A4/VREF-/VeREF-) A4/VREF-/VeREF-(notavailableonCC430F612x)(3) X 1 =31 X CB4(4) X X X 1 P2.5(I/O) I:0;O:1 0 X 0 P2.5/P2MAP5/CB5 Mappedsecondarydigitalfunction–seeTable6-6 0;1(2) 1 ≤30(2) 0 5 (/A5/VREF+/VeREF+) A5/VREF+/VeREF+(notavailableonCC430F612x)(3) X 1 =31 X CB5(4) X X X 1 P2.6(I/O) I:0;O:1 0 X 0 Mappedsecondarydigitalfunction–seeTable6-6 0;1(2) 1 ≤30(2) 0 P2.6/P2MAP6(/CB6) (/A6) 6 AC6C4(n3o0tFa5v1a3ilxa)b(3le) onCC430F612xand X 1 =31 X CB6(notavailableonCC430F513x)(4) X X X 1 P2.7(I/O) I:0;O:1 0 X 0 Mappedsecondarydigitalfunction–seeTable6-6 0;1(2) 1 ≤30(2) 0 P2.7/P2MAP7(/CB7) (/A7) 7 AC7C4(n3o0tFa5v1a3ilxa)b(3le) onCC430F612xand X 1 =31 X CB7(notavailableonCC430F513x)(4) X X X 1 (1) X=don'tcare (2) Accordingtomappedfunction–seeTable6-6. (3) SettingP2SEL.xbittogetherwithP2MAPx=PM_ANALOGdisablestheoutputdriverandtheinputSchmitttrigger. (4) SettingtheCBPD.xbitdisablestheoutputdriverandtheinputSchmitttriggertopreventparasiticcrosscurrentswhenapplyinganalog signals.SelectingtheCBxinputpintothecomparatormultiplexerwiththeCBxbitsautomaticallydisablesoutputdriverandinputbuffer forthatpin,regardlessofthestateoftheassociatedCBPD.xbit. 94 DetailedDescription Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 6.11.4 Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger Figure6-7showstheportdiagram.Table6-48 summarizestheselectionofthepinfunctions. S10...S17 (n/a CC430F513x) LCDS10...LCDS17 Pad Logic P3REN.x P3MAP.x = PMAP_ANALOG DVSS 0 DVCC 1 1 P3DIR.x 0 Direction from Port Mapping 1 0: Input 1: Output P3OUT.x 0 from Port Mapping 1 P3.0/P3MAP0(/S10) P3DS.x P3.1/P3MAP1(/S11) P3SEL.x 0: Low drive P3.2/P3MAP2(/S12) 1: High drive P3.3/P3MAP3(/S13) P3IN.x P3.4/P3MAP4(/S14) P3.5/P3MAP5(/S15) P3.6/P3MAP6(/S16) EN Bus P3.7/P3MAP7(/S17) Keeper to Port Mapping D CC430F513xdevicesdonotprovideLCDfunctionalityonportP3pins. Figure6-7.PortP3(P3.0toP3.7)Diagram Copyright©2009–2018,TexasInstrumentsIncorporated DetailedDescription 95 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com Table6-48.PortP3(P3.0toP3.7)PinFunctions CONTROLBITSORSIGNALS(1) PINNAME(P3.x) x FUNCTION LCDS10to P3DIR.x P3SEL.x P3MAPx LCDS17(2) P3.0(I/O) I:0;O:1 0 X 0 Mappedsecondarydigitalfunction–seeTable6-6 0;1(3) 1 ≤30(3) 0 P3.0/P3MAP0/S10 0 OutputdriverandinputSchmitttriggerdisabled X 1 =31 0 S10(notavailableonCC430F513x) X X X 1 P3.1(I/O) I:0;O:1 0 X 0 Mappedsecondarydigitalfunction–seeTable6-6 0;1(3) 1 ≤30(3) 0 P3.1/P3MAP1/S11 1 OutputdriverandinputSchmitttriggerdisabled X 1 =31 0 S11(notavailableonCC430F513x) X X X 1 P3.2(I/O) I:0;O:1 0 X 0 Mappedsecondarydigitalfunction–seeTable6-6 0;1(3) 1 ≤30(3) 0 P3.2/P3MAP7/S12 2 OutputdriverandinputSchmitttriggerdisabled X 1 =31 0 S12(notavailableonCC430F513x) X X X 1 P3.3(I/O) I:0;O:1 0 X 0 Mappedsecondarydigitalfunction–seeTable6-6 0;1(3) 1 ≤30(3) 0 P3.3/P3MAP3/S13 3 OutputdriverandinputSchmitttriggerdisabled X 1 =31 0 S13(notavailableonCC430F513x) X X X 1 P3.4(I/O) I:0;O:1 0 X 0 Mappedsecondarydigitalfunction–seeTable6-6 0;1(3) 1 ≤30(3) 0 P3.4/P3MAP4/S14 4 OutputdriverandinputSchmitttriggerdisabled X 1 =31 0 S14(notavailableonCC430F513x) X X X 1 P3.5(I/O) I:0;O:1 0 X 0 Mappedsecondarydigitalfunction–seeTable6-6 0;1(3) 1 ≤30(3) 0 P3.5/P3MAP5/S15 5 OutputdriverandinputSchmitttriggerdisabled X 1 =31 0 S15(notavailableonCC430F513x) X X X 1 P3.6(I/O) I:0;O:1 0 X 0 Mappedsecondarydigitalfunction–seeTable6-6 0;1(3) 1 ≤30(3) 0 P3.6/P3MAP6/S16 6 OutputdriverandinputSchmitttriggerdisabled X 1 =31 0 S16(notavailableonCC430F513x) X X X 1 P3.7(I/O) I:0;O:1 0 X 0 Mappedsecondarydigitalfunction–seeTable6-6 0;1(3) 1 ≤30(3) 0 P3.7/P3MAP7/S17 7 OutputdriverandinputSchmitttriggerdisabled X 1 =31 0 S17(notavailableonCC430F513x) X X X 1 (1) X=don'tcare (2) LCDSxnotavailableinCC430F513x. (3) Accordingtomappedfunction–seeTable6-6. 96 DetailedDescription Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 6.11.5 Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger (CC430F613x and CC430F612x Only) Figure6-8showstheportdiagram.Table6-49 summarizestheselectionofthepinfunctions. S2...S9 LCDS2...LCDS9 Pad Logic P4REN.x DVSS 0 DVCC 1 1 P4DIR.x 0 Direction 0: Input 1 1: Output P4OUT.x 0 DVSS 1 P4.0/S2 P4DS.x P4.1/S3 P4SEL.x 0: Low drive P4.2/S4 1: High drive P4.3/S5 P4IN.x P4.4/S6 P4.5/S7 P4.6/S8 EN Bus P4.7/S9 Keeper Not Used D Figure6-8.PortP4(P4.0toP4.7)Diagram(CC430F613xandCC430F612xOnly) Copyright©2009–2018,TexasInstrumentsIncorporated DetailedDescription 97 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com Table6-49.PortP4(P4.0toP4.7)PinFunctions(CC430F613xandCC430F612xOnly) CONTROLBITSORSIGNALS(1) PINNAME(P4.x) x FUNCTION LCDS2to P4DIR.x P4SEL.x LCDS9 P4.0(I/O) I:0;O:1 0 0 N/A 0 1 0 P4.0/P4MAP0/S2 0 DVSS 1 1 0 S2 X X 1 P4.1(I/O) I:0;O:1 0 0 N/A 0 1 0 P4.1/P4MAP1/S3 1 DVSS 1 1 0 S3 X X 1 P4.2(I/O) I:0;O:1 0 0 N/A 0 1 0 P4.2/P4MAP7/S4 2 DVSS 1 1 0 S4 X X 1 P4.3(I/O) I:0;O:1 0 0 N/A 0 1 0 P4.3/P4MAP3/S5 3 DVSS 1 1 0 S5 X X 1 P4.4(I/O) I:0;O:1 0 0 N/A 0 1 0 P4.4/P4MAP4/S6 4 DVSS 1 1 0 S6 X X 1 P4.5(I/O) I:0;O:1 0 0 N/A 0 1 0 P4.5/P4MAP5/S7 5 DVSS 1 1 0 S7 X X 1 P4.6(I/O) I:0;O:1 0 0 N/A 0 1 0 P4.6/P4MAP6/S8 6 DVSS 1 1 0 S8 X X 1 P4.7(I/O) I:0;O:1 0 0 N/A 0 1 0 P4.7/P4MAP7/S9 7 DVSS 1 1 0 S9 X X 1 (1) X=don'tcare 98 DetailedDescription Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 6.11.6 Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger Figure 6-9 and Figure 6-10 show the port diagrams. Table 6-50 summarizes the selection of the pin functions. Pad Logic to XT1 P5REN.0 DVSS 0 DVCC 1 1 P5DIR.0 0 1 P5OUT.0 0 Module X OUT 1 P5.0/XIN P5DS.x P5SEL.0 0: Low drive 1: High drive P5IN.0 EN Bus Keeper Module X IN D Figure6-9.PortP5(P5.0)Diagram Copyright©2009–2018,TexasInstrumentsIncorporated DetailedDescription 99 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com Pad Logic to XT1 P5REN.1 DVSS 0 DVCC 1 1 P5DIR.1 0 1 P5OUT.1 0 Module X OUT 1 P5.1/XOUT P5SEL.0 P5DS.x 0: Low drive XT1BYPASS 1: High drive P5IN.1 EN Bus Keeper Module X IN D Figure6-10.PortP5(P5.1)Diagram Table6-50.PortP5(P5.0andP5.1)PinFunctions CONTROLBITSORSIGNALS(1) PINNAME(P5.x) x FUNCTION P5DIR.x P5SEL.0 P5SEL.1 XT1BYPASS P5.0(I/O) I:0;O:1 0 X X P5.0/XIN 0 XINcrystalmode(2) X 1 X 0 XINbypassmode(2) X 1 X 1 P5.1(I/O) I:0;O:1 0 X X P5.1/XOUT 1 XOUTcrystalmode(3) X 1 X 0 P5.1(I/O)(3) X 1 X 1 (1) X=don'tcare (2) SettingP5SEL.0causesthegeneral-purposeI/Otobedisabled.PendingthesettingofXT1BYPASS,P5.0isconfiguredforcrystal modeorbypassmode. (3) SettingP5SEL.0causesthegeneral-purposeI/Otobedisabledincrystalmode.Whenusingbypassmode,P5.1canbeusedas general-purposeI/O. 100 DetailedDescription Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 6.11.7 Port P5 (P5.2 to P5.4) Input/Output With Schmitt Trigger (CC430F613x and CC430F612x Only) Figure 6-11 shows the port diagram. Table 6-51 and Table 6-52 summarize the selection of the pin functions. S0(P5.2)/S1(P5.3)/S23(P5.4) LCDS0(P5.2)/LCDS1(P5.3)/LCDS23(P5.4) Pad Logic P5REN.x DVSS 0 DVCC 1 1 P5DIR.x 0 1 P5OUT.x 0 DVSS 1 P5.2/S0 P5DS.x P5.3/S1 P5SEL.x 0: Low drive P5.4/S23 1: High drive P5IN.x EN Bus Keeper Not Used D Figure6-11.PortP5(P5.2toP5.4)Diagram(CC430F613xandCC430F612xOnly) Copyright©2009–2018,TexasInstrumentsIncorporated DetailedDescription 101 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com Table6-51.PortP5(P5.2toP5.3)PinFunctions(CC430F613xandCC430F612xOnly) CONTROLBITSORSIGNALS(1) PINNAME(P5.x) x FUNCTION LCDS0to P5DIR.x P5SEL.x LCDS1 P5.2(I/O) I:0;O:1 0 0 N/A 0 1 0 P5.2/S0 2 DVSS 1 1 0 S0 X X 1 P5.3(I/O) I:0;O:1 0 0 N/A 0 1 0 P5.3/S1 3 DVSS 1 1 0 S1 X X 1 (1) X=don'tcare Table6-52.PortP5(P5.4)PinFunctions(CC430F613xandCC430F612xOnly) CONTROLBITSORSIGNALS(1) PINNAME(P5.x) x FUNCTION P5DIR.x P5SEL.x LCDS23 P5.4(I/O) I:0;O:1 0 0 N/A 0 1 0 P5.4/S23 4 DVSS 1 1 0 S23 X X 1 (1) X=don'tcare 102 DetailedDescription Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 6.11.8 Port P5 (P5.5 to P5.7) Input/Output With Schmitt Trigger (CC430F613x and CC430F612x Only) Figure6-12showstheportdiagram.Table6-53summarizestheselectionofthepinfunctions. S24(P5.5)/S25(P5.6)/S26(P5.7) LCDS24(P5.5)/LCDS25(P5.6)/LCDS26(P5.7) COM3(P5.5)/COM2(P5.6)/COM1(P5.7) Pad Logic P5REN.x DVSS 0 DVCC 1 1 P5DIR.x P5OUT.x P5.5/COM3/S24 P5DS.x P5SEL.x 0: Low drive P5.6/COM2/S25 P5.7/COM1/S26 1: High drive P5IN.x Bus Keeper Figure6-12.PortP5(P5.5toP5.7)Diagram(CC430F613xandCC430F612xOnly) Table6-53.PortP5(P5.5toP5.7)PinFunctions(CC430F613xandCC430F612xOnly) CONTROLBITSORSIGNALS(1) PINNAME(P5.x) x FUNCTION LCDS24to P5DIR.x P5SEL.x LCDS26 P5.5(I/O) I:0;O:1 0 0 P5.5/COM3/S24 5 COM3(2) X 1 X S24(2) X 0 1 P5.6(I/O) I:0;O:1 0 0 P5.6/COM2/S25 6 COM2(2) X 1 X S25(2) X 0 1 P5.7(I/O) I:0;O:1 0 0 P5.7/COM1/S26 7 COM1(2) X 1 X S26(2) X 0 1 (1) X=don'tcare (2) SettingP5SEL.xbitdisablestheoutputdriverandtheinputSchmitttrigger. Copyright©2009–2018,TexasInstrumentsIncorporated DetailedDescription 103 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com 6.11.9 Port J (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output Figure6-13showstheportdiagram.Table6-54summarizestheselectionofthepinfunctions. Pad Logic PJREN.0 DVSS 0 DVCC 1 1 PJDIR.0 0 DVCC 1 PJOUT.0 0 From JTAG 1 PJ.0/TDO PJDS.0 From JTAG 0: Low drive 1: High drive PJIN.0 Figure6-13.PortPJ(PJ.0)Diagram 104 DetailedDescription Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 6.11.10 Port J (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output Figure6-14showstheportdiagram.Table6-54summarizestheselectionofthepinfunctions. Pad Logic PJREN.x DVSS 0 DVCC 1 1 PJDIR.x 0 DVSS 1 PJOUT.x 0 From JTAG 1 PJ.1/TDI/TCLK PJDS.x PJ.2/TMS From JTAG 0: Low drive PJ.3/TCK 1: High drive PJIN.x EN To JTAG D Figure6-14.PortPJ(PJ.1toPJ.3)Diagram Table6-54.PortPJ(PJ.0toPJ.3)PinFunctions CONTROLBITSOR PINNAME(PJ.x) x FUNCTION SIGNALS(1) PJDIR.x PJ.0(I/O)(2) I:0;O:1 PJ.0/TDO 0 TDO(3) X PJ.1(I/O)(2) I:0;O:1 PJ.1/TDI/TCLK 1 TDI/TCLK(3) (4) X PJ.2(I/O)(2) I:0;O:1 PJ.2/TMS 2 TMS(3) (4) X PJ.3(I/O)(2) I:0;O:1 PJ.3/TCK 3 TCK(3) (4) X (1) X=don'tcare (2) Defaultcondition (3) ThepindirectioniscontrolledbytheJTAGmodule. (4) InJTAGmode,pullupsareactivatedautomaticallyonTMS,TCK,andTDI/TCLK.PJREN.xaredonotcare. Copyright©2009–2018,TexasInstrumentsIncorporated DetailedDescription 105 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com 6.12 Device Descriptor Table 6-55 lists the content of the device descriptor tag-length-value (TLV) structure for CC430F613x and CC430F513xdevicetypes. Table 6-56 lists the content of the device descriptor tag-length-value (TLV) structure for CC430F612x devicetypes. Table6-55.DeviceDescriptorTable(CC430F613xandCC430F513x) SIZE VALUE DESCRIPTION ADDRESS (bytes) F6137 F6135 F5137 F5135 F5133 Infolength 01A00h 1 06h 06h 06h 06h 06h CRClength 01A01h 1 06h 06h 06h 06h 06h CRCvalue 01A02h 2 Perunit Perunit Perunit Perunit Perunit InfoBlock DeviceID 01A04h 1 61h 61h 51h 51h 51h DeviceID 01A05h 1 37h 35h 37h 35h 33h Hardwarerevision 01A06h 1 Perunit Perunit Perunit Perunit Perunit Firmwarerevision 01A07h 1 Perunit Perunit Perunit Perunit Perunit Dierecordtag 01A08h 1 08h 08h 08h 08h 08h Dierecordlength 01A09h 1 0Ah 0Ah 0Ah 0Ah 0Ah Lot/waferID 01A0Ah 4 Perunit Perunit Perunit Perunit Perunit DieRecord DieXposition 01A0Eh 2 Perunit Perunit Perunit Perunit Perunit DieYposition 01A10h 2 Perunit Perunit Perunit Perunit Perunit Testresults 01A12h 2 Perunit Perunit Perunit Perunit Perunit ADC12calibrationtag 01A14h 1 11h 11h 11h 11h 11h ADC12calibrationlength 01A15h 1 10h 10h 10h 10h 10h ADCgainfactor 01A16h 2 Perunit Perunit Perunit Perunit Perunit ADCoffset 01A18h 2 Perunit Perunit Perunit Perunit Perunit ADC1.5-Vreference 01A1Ah 2 Perunit Perunit Perunit Perunit Perunit Temperaturesensor30°C ADC1.5-Vreference ADC12 Temperaturesensor85°C 01A1Ch 2 Perunit Perunit Perunit Perunit Perunit Calibration ADC2.0-Vreference 01A1Eh 2 Perunit Perunit Perunit Perunit Perunit Temperaturesensor30°C ADC2.0-Vreference 01A20h 2 Perunit Perunit Perunit Perunit Perunit Temperaturesensor85°C ADC2.5-Vreference 01A22h 2 Perunit Perunit Perunit Perunit Perunit Temperaturesensor30°C ADC2.5-Vreference 01A24h 2 Perunit Perunit Perunit Perunit Perunit Temperaturesensor85°C REFcalibrationtag 01A26h 1 12h 12h 12h 12h 12h REFcalibrationlength 01A27h 1 06h 06h 06h 06h 06h REF 1.5-Vreferencefactor 01A28h 2 Perunit Perunit Perunit Perunit Perunit Calibration 2.0-Vreferencefactor 01A2Ah 2 Perunit Perunit Perunit Perunit Perunit 2.5-Vreferencefactor 01A2Ch 2 Perunit Perunit Perunit Perunit Perunit Peripheraldescriptortag 01A2Eh 1 02h 02h 02h 02h 02h Peripheral Descriptor Peripheraldescriptorlength 01A2Fh 1 57h 57h 55h 55h 55h (PD) Peripheraldescriptors 01A30h PDLength ... ... ... ... ... 106 DetailedDescription Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 Table6-56.DeviceDescriptorTable(CC430F612x) SIZE VALUE DESCRIPTION ADDRESS (bytes) F6127 F6126 F6125 Infolength 01A00h 1 06h 06h 06h CRClength 01A01h 1 06h 06h 06h CRCvalue 01A02h 2 Perunit Perunit Perunit InfoBlock DeviceID 01A04h 1 61h 61h 61h DeviceID 01A05h 1 27h 26h 25h Hardwarerevision 01A06h 1 Perunit Perunit Perunit Firmwarerevision 01A07h 1 Perunit Perunit Perunit Dierecordtag 01A08h 1 08h 08h 08h Dierecordlength 01A09h 1 0Ah 0Ah 0Ah Lot/waferID 01A0Ah 4 Perunit Perunit Perunit DieRecord DieXposition 01A0Eh 2 Perunit Perunit Perunit DieYposition 01A10h 2 Perunit Perunit Perunit Testresults 01A12h 2 Perunit Perunit Perunit Emptytag 01A14h 1 05h 05h 05h EmptyDescriptor Emptytaglength 01A15h 1 10h 10h 10h 01A16h 16 undefined undefined undefined REFcalibrationl 01A26h 1 12h 12h 12h REFcalibrationlength 01A27h 1 06h 06h 06h REFCalibration 1.5-Vreferencefactor 01A28h 2 Perunit Perunit Perunit 2.0-Vreferencefactor 01A2Ah 2 Perunit Perunit Perunit 2.5-Vreferencefactor 01A2Ch 2 Perunit Perunit Perunit Peripheraldescriptortag 01A2Eh 1 02h 02h 02h PeripheralDescriptor Peripheraldescriptorlength 01A2Fh 1 55h 55h 55h (PD) Peripheraldescriptors 01A30h PDLength ... ... ... Copyright©2009–2018,TexasInstrumentsIncorporated DetailedDescription 107 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com 7 Applications, Implementation, and Layout NOTE InformationinthefollowingApplicationssectionisnotpartoftheTIcomponentspecification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test theirdesignimplementationtoconfirmsystemfunctionality. 7.1 Application Circuits Figure7-1showsatypicalapplicationcircuitfortheCC430F61xx.Table7-1 liststhebillofmaterials. 108 Applications,Implementation,andLayout Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 MT MASTRAIGHTJACK, S C29 S L7 C28 L6 L5 C27 L3 C26 C25 C24 C23 L4 L2 L1 C18 C17 C16 (May be added close to the respective pinstoreduceemissionsat5GHztolevelsrequired by ETSI.) C4 C3C2C1 C5C6C7 C22 (JTAG / SBW signals) TMS TDI/TCLKR1AVDDTDO GUARD R_BIAS AVCC_RF AVCC_RF RF_N RF_P AVCC_RF AVCC_RF RF_XOUT RF_XIN 26MHz C21 C20 KCT 4948 4746 45 4443 42 4140 39 38 37 36 35 34 3332 KCTWBS/TSET 50 31 R2 OIDTWBS/IMN/TSRn 51 30 VDD C15 C14 CSCSVVAD 5253 2928 AVDD C13 C12 CCVA 57565554 430F61xx 24252627 CCVDVDD C8C9 8 C 3 5 C 2 9 2 5 2 60 21 61 20 2 9 6 1 3 8 6 1 4 7 61 23 45 6 78 9 10 11 1213 1415 161 COREDVCC C10 V VDD C11 C19 Copyright © 2017,Texas Instruments Incorporated Foracompletereferencedesignincludinglayout,seetheCC430wirelessdevelopmenttoolsandtheMSP430 HardwareToolsUser'sGuide. Figure7-1.TypicalApplicationCircuitCC430F61xx Copyright©2009–2018,TexasInstrumentsIncorporated Applications,Implementation,andLayout 109 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com Figure7-2showsatypicalapplicationcircuitfortheCC430F51xx.Table7-1 liststhebillofmaterials. MT CK, S JA HT G RAI MAST C29 S L7 C28 L6 L5 C27 L3 C26 C25 C24 C23 L4 L2 L1 C3 C7 C18 C17 C16 (May be added close to the respective pinstoreduceemissionsat5GHztolevelsrequired by ETSI.) R1 C4 C2C1 C5C6 MHz C22 (JTAG / SBW signals) TDI/TCLKAVDD TDO GUARD R_BIAS AVCC_RF AVCC_RF RF_N RF_P AVCC_RF AVCC_RF RF_XOUT RF_XIN 26 C21 C20 KCTWBS/TSKSMCETTT 37393836 35 34 33 32 31 30 29 28 27 26 25224223 CCVDVDD C8C9 R2 OIDTWBS/IMN/TSRn 40 21 VDD C15 C14 CSCSVVAD 4241 0F51xx 1920 43 C43 18 44 C 17 AVDD C13 C12 CCVA 4645 1516 47 14 481 2 3 4 5 6 7 8 9 10 11 1213 EC CORDVC C10 V VDD C11 C19 Copyright © 2017,Texas Instruments Incorporated Foracompletereferencedesignincludinglayout,seetheCC430wirelessdevelopmenttoolsandtheMSP430 HardwareToolsUser'sGuide. Figure7-2.TypicalApplicationCircuitCC430F51xx 110 Applications,Implementation,andLayout Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 Table7-1.BillofMaterials Components For315MHz For433MHz For868or915MHz Comment C1,C3,C4,C5,C7, 100nF Decouplingcapacitors C9,C11,C13,C15 C8,C10,C12,C14 10µF Decouplingcapacitors C2,C6,C16,C17, 2pF Decouplingcapacitors C18 C19 470nF V capacitor CORE C20 2.2nF RSTdecouplingcap(optimizedforSBW) C21,C22 27pF Loadcapacitorsfor26MHzcrystal(1) R1 56kΩ R_BIAS(±1%required) R2 47kΩ RSTpullup L1,L2 Capacitors:220pF 0.016µH 0.012µH L3,L4 0.033µH 0.027µH 0.018µH L5 0.033µH 0.047µH 0.015µH L6 dnp(2) dnp(2) 0.0022µH L7 0.033µH 0.051µH 0.015µH C23 dnp(2) 2.7pF 1pF C24 220pF 220pF 100pF C25 6.8pF 3.9pF 1.5pF C26 6.8pF 3.9pF 1.5pF C27 220pF 220pF 1.5pF C28 10pF 4.7pF 8.2pF C29 220pF 220pF 1.5pF (1) TheloadcapacitanceC seenbythecrystalisC =1/((1/C21)+(1/C22))+C .TheparasiticcapacitanceC includespin L L parasitic parasitic capacitanceandPCBstraycapacitance.Itcantypicallybeestimatedtobeapproximately2.5pF. (2) dnp=donotpopulate Copyright©2009–2018,TexasInstrumentsIncorporated Applications,Implementation,andLayout 111 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com 8 Device and Documentation Support 8.1 Getting Started and Next Steps For an introduction to the MSP430™ family of devices and the tools and libraries that are available to help withyourdevelopment,visittheGettingStartedpage. 8.2 Device Nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all MSP MCU devices. Each MSP MCU commercial family member has one of two prefixes: MSP or XMS. These prefixes represent evolutionary stages of product development from engineering prototypes (XMS) throughfullyqualifiedproductiondevices(MSP). XMS – Experimental device that is not necessarily representative of the final device's electrical specifications MSP–Fullyqualifiedproductiondevice XMSdevicesareshippedagainstthefollowingdisclaimer: "Developmentalproductisintendedforinternalevaluationpurposes." MSP devices have been characterized fully, and the quality and reliability of the device have been demonstratedfully.TI'sstandardwarrantyapplies. Predictions show that prototype devices (XMS) have a greater failure rate than the standard production devices. TI recommends that these devices not be used in any production system because their expected end-usefailureratestillisundefined.Onlyqualifiedproductiondevicesaretobeused. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the temperature range, package type, and distribution format. Figure 8-1 provides a legend for reading the completedevicename. 112 DeviceandDocumentationSupport Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 MSP 430 F 5 438 A I ZQW T -EP Processor Family Optional:Additional Features MCU Platform Optional:Tape and Reel DeviceType Packaging Series Optional:Temperature Range Feature Set Optional:A= Revision Processor Family CC = Embedded RF Radio MSP= Mixed-Signal Processor XMS = Experimental Silicon PMS = Prototype Device MCU Platform 430 = MSP430 low-power microcontroller platform Device Type Memory Type SpecializedApplication C = ROM AFE =Analog Front End F = Flash BQ = Contactless Power FR = FRAM CG = ROM Medical G = Flash or FRAM (Value Line) FE = Flash Energy Meter L= No Nonvolatile Memory FG = Flash Medical FW = Flash Electronic Flow Meter Series 1 = Up to 8 MHz 5 = Up to 25 MHz 2 = Up to 16 MHz 6 = Up to 25 MHz with LCD 3 = Legacy 0 = Low-Voltage Series 4 = Up to 16 MHz with LCD Feature Set Various levels of integration within a series Optional:A= Revision N/A Optional: Temperature Range S = 0°C to 50°C C = 0°C to 70°C I =–40°C to 85°C T=–40°C to 105°C Packaging http://www.ti.com/packaging Optional: Tape and Reel T= Small reel R = Large reel No markings =Tube or tray Optional:Additional Features -EP= Enhanced Product (–40°C to 105°C) -HT= ExtremeTemperature Parts (–55°C to 150°C) -Q1 =Automotive Q100 Qualified Figure8-1.DeviceNomenclature Copyright©2009–2018,TexasInstrumentsIncorporated DeviceandDocumentationSupport 113 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com 8.3 Tools and Software The CC430 microcontrollers are supported by a wide variety of software and hardware development tools. ToolsareavailablefromTIandvariousthirdparties. DesignKitsandEvaluationModules CC430Sub-GHzRFExperimenter'sBoard The MSP-EXPCC430RFx Experimenter Kit is a complete sub-GHz development platform for the CC430 devices from the MSP430 family of ultra-low- power microcontrollers. The kit provides two sub-GHz wireless modules: the MSP- EXP430F6137Rx Base Board with the CC430F6137, and the MSP-EXP430F5137Rx SatelliteBoardwiththeCC430F5137. Chronos:WirelessDevelopmentToolinaWatch The eZ430-Chronos is a highly integrated, wearable wireless development system based for the CC430 in a sports watch. It may be used as a reference platform for watch systems, a personal display for personal area networks, or as a wirelesssensornodeforremotedatacollection. Sub-1GHzRFSpectrumAnalyzerTool The MSP-SA430-SUB1GHZ Spectrum Analyzer is CC430- based reference design that can be used to implement an easy and affordable tool to jumpstart RF development in the sub-GHz frequency range. More and more electronic devices include a built-in RF link. RF transceivers are inexpensive - but the equipment to design and debug such systems is not. The CC430-based spectrum analyzer provides an affordable development tool that reduces the time needed on expensive measurement equipment. Software MSP430Ware™Software MSP430Ware software is a collection of code examples, data sheets, and other design resources for all MSP430 devices delivered in a convenient package. In addition to providing a complete collection of existing MSP430 design resources, MSP430Ware software also includes a high-level API called MSP Driver Library. This library makes it easy to program MSP430 hardware. MSP430Ware software is available as a componentofCCSorasastand-alonepackage. CC430F613xCodeExamples C Code examples that configure each of the integrated peripherals for variousapplicationneeds. ULP(Ultra-LowPower)Advisor ULP (Ultra-Low Power) Advisor is a tool for guiding developers to write more efficient code to fully utilize the unique ultra-low power features of MSP430 and MSP432 microcontrollers. Aimed at both experienced and new microcontroller developers, ULP Advisor checks your code against a thorough ULP checklist to squeeze every last nano ampoutofyourapplication. DevelopmentTools CodeComposerStudio™IntegratedDevelopmentEnvironmentforMSPMicrocontrollers Code Composer Studio is an integrated development environment (IDE) that supports all MSP microcontroller devices. Code Composer Studio comprises a suite of embedded software utilities used to develop and debug embedded applications. It includes an optimizing C/C++ compiler, source code editor, project build environment, debugger, profiler, and many other features. GCC-OpenSourceCompilerforMSP430Microcontrollers TI has partnered with Red Hat to bring you a new and fully supported open source compiler as the successor to the community driven MSPGCC. This free GCC 4.9 compiler supports all MSP430 devices and has no code size limit. In addition, this compiler can be used stand-alone or selected within Code ComposerStudiov6.0orlater. MSPMCUProgrammerandDebugger The MSP-FET is a powerful emulation development tool – often called a debug probe – which allows users to quickly begin application development on MSP low-powermicrocontrollers(MCU). MSP-GANGProductionProgrammer The MSP Gang Programmer is a device programmer that can program up to eight identical devices at the same time. The MSP Gang Programmer connects to a host PC using a standard RS-232 or USB connection and provides flexible programmingoptionsthatallowtheusertofullycustomizetheprocess. 114 DeviceandDocumentationSupport Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 8.4 Documentation Support The following documents describe the CC430F613x, CC430F612x, and CC430F513x devices. Copies of thesedocumentsareavailableontheInternetat www.ti.com. ReceivingNoficationofDocumentUpdates To receive notification of documentation updates—including silicon errata—go to the product folder for your device on ti.com (for links to the product folder, see Section 8.5). In the upper right corner, click the "Alert me" button. This registers you to receive a weekly digest of product information that has changed (if any).Forchangedetails,checktherevisionhistoryofanyreviseddocument. Errata CC430F6137DeviceErratasheet Describestheknownexceptionstothefunctionalspecifications. CC430F6135DeviceErratasheet Describestheknownexceptionstothefunctionalspecifications. CC430F6127DeviceErratasheet Describestheknownexceptionstothefunctionalspecifications. CC430F6126DeviceErratasheet Describestheknownexceptionstothefunctionalspecifications. CC430F6125DeviceErratasheet Describestheknownexceptionstothefunctionalspecifications. CC430F5137DeviceErratasheet Describestheknownexceptionstothefunctionalspecifications. CC430F5135DeviceErratasheet Describestheknownexceptionstothefunctionalspecifications. CC430F5133DeviceErratasheet Describestheknownexceptionstothefunctionalspecifications. User'sGuides CC430FamilyUser'sGuide Detailed information on the modules and peripherals available in this devicefamily. CodeComposerStudioforMSP430User'sGuide This user's guide describes how to use the TI Code ComposerStudioIDEwiththeMSP430ultra-low-powermicrocontrollers. MSP430™FlashDeviceBootloader(BSL)User'sGuide The MSP430 bootloader (BSL, formerly known as the bootstrap loader) allows users to communicate with embedded memory in the MSP430 microcontroller during the prototyping phase, final production, and in service. Both the programmable memory (flash memory) and the data memory (RAM) can be modified as required. Do not confuse the bootloader with the bootstrap loader programs found in some digital signal processors (DSPs) that automatically load program code (and data) from externalmemorytotheinternalmemoryoftheDSP. MSP430ProgrammingWiththeJTAGInterface This document describes the functions that are required to erase, program, and verify the memory module of the MSP430 flash-based and FRAM-based microcontroller families using the JTAG communication port. In addition, it describes how to program the JTAG access security fuse that is available on all MSP430 devices. This document describes device access using both the standard 4-wire JTAG interfaceandthe2-wireJTAGinterface,whichisalsoreferredtoasSpy-Bi-Wire(SBW). MSP430HardwareToolsUser'sGuide This manual describes the hardware of the TI MSP-FET430 FlashEmulationTool(FET).TheFETistheprogramdevelopmenttoolfortheMSP430ultra- low-power microcontroller. Both available interface types, the parallel port interface and the USBinterface,aredescribed. ApplicationReports MSP43032-kHzCrystalOscillators Selection of the right crystal, correct load circuit, and proper board layout are important for a stable crystal oscillator. This application report summarizes crystal oscillator function and explains the parameters to select the correct crystal for MSP430 ultra- low-power operation. In addition, hints and examples for correct board layout are given. The document also contains detailed information on the possible oscillator tests to ensure stable oscillatoroperationinmassproduction. MSP430System-LevelESDConsiderations System-Level ESD has become increasingly demanding with silicon technology scaling towards lower voltages and the need for designing cost- effective and ultra-low-power components. This application report addresses three different ESD topics to help board designers and OEMs understand and design robust system-level designs: (1) Component-level ESD testing and system-level ESD testing, their differences Copyright©2009–2018,TexasInstrumentsIncorporated DeviceandDocumentationSupport 115 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com and why component-level ESD rating does not ensure system-level robustness. (2) General design guidelines for system-level ESD protection at different levels including enclosures, cables, PCB layout, and on-board ESD protection devices. (3) Introduction to System Efficient ESD Design (SEED), a co-design methodology of on-board and on-chip ESD protection to achieve system-level ESD robustness, with example simulations and test results. A few real-world system-level ESD protection design examples and their results are alsodiscussed. DN005CC11xxSensitivityversusFrequencyOffsetandCrystalAccuracy This design note provides plots of CC11xx (CC1100, CC1100E, CC1101, CC1110, and CC1111) sensitivity versus frequency offset for different data rates. The required crystal accuracy is calculated from theseplots.TheresultsarealsoapplicableforCC430. AN050UsingtheCC1101intheEuropean868MHzSRDBand The CC1101 is a truly low cost, highly integrated, and very flexible RF transceiver. The CC1101 is primarily designed for use in low-power applications in the 315, 433, 868 and 915 MHz SRD/ISM bands. This application note describes how to use the CC1101 in the European 863 – 870 MHz SRD frequency bands in order to comply with EN 300 220 requirements. The application note is also applicableforCC1110,CC1111,andCC430SoCsastheyusethesameradioasCC1101. DN010Close-inReceptionwithCC1101 This document describes how the CC1100E and CC1101 can be used in close-range applications. The chips have a saturation limit of approximately −15 dBm at 250 kbps, which might be a challenge for some short-range applications. Two suggested solutions are presented, the first is a double-transmit scheme and the second is toshiftthereceiversdynamicrangeduringclose-rangereception. DN013ProgrammingOutputPoweronCC1101 The CC1101 RF output power level is set by the PATABLE register setting. This register setting also influences the power levels at the different harmonics and the current consumption for the device. These parameters must therefore be considered when choosing the optimal register settings. This document gives complete CC1101 PA tables with typical output power, harmonics, and current consumption forthedifferentregistersettingsat25°Cand3.0Vsupplyvoltage. DN017CC11xx868/915MHzRFMatching This design note gives a short introduction to RF matching and important aspects when designing products using the CC11xx parts. Because all of the CC11xx parts have the same RF front end, the same matching network can be used between the radio and the antenna. TI provides a reference design for all CC11xx products. These reference designs show recommended placement and values for decoupling capacitorsandcomponentsinthematchingnetwork. 116 DeviceandDocumentationSupport Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 www.ti.com SLAS554I–MAY2009–REVISEDSEPTEMBER2018 8.5 Related Links Table 8-1 lists quick access links. Categories include technical documents, support and community resources,toolsandsoftware,andquickaccesstosampleorbuy. Table8-1.RelatedLinks TECHNICAL TOOLS& SUPPORT& PARTS PRODUCTFOLDER ORDERNOW DOCUMENTS SOFTWARE COMMUNITY CC430F6137 Clickhere Clickhere Clickhere Clickhere Clickhere CC430F6135 Clickhere Clickhere Clickhere Clickhere Clickhere CC430F6127 Clickhere Clickhere Clickhere Clickhere Clickhere CC430F6126 Clickhere Clickhere Clickhere Clickhere Clickhere CC430F6125 Clickhere Clickhere Clickhere Clickhere Clickhere CC430F5137 Clickhere Clickhere Clickhere Clickhere Clickhere CC430F5135 Clickhere Clickhere Clickhere Clickhere Clickhere CC430F5133 Clickhere Clickhere Clickhere Clickhere Clickhere 8.6 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; seeTI's TermsofUse. TIE2E™Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas, and help solve problems with fellow engineers. TIEmbeddedProcessorsWiki TexasInstrumentsEmbeddedProcessorsWiki.Establishedtohelpdevelopersgetstartedwithembedded processors from Texas Instruments and to foster innovation and growth of general knowledge about the hardwareandsoftwaresurroundingthesedevices. 8.7 Trademarks MSP430,MSP430Ware,E2EaretrademarksofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 8.8 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. 8.9 Export Control Notice Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled product restricted by other applicable national regulations, received from disclosing party under nondisclosure obligations (if any), or any direct product of such technology, to any destination to which such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from U.S. Department of Commerce and other competent Government authorities to the extentrequiredbythoselaws. 8.10 Glossary TIGlossary Thisglossarylistsandexplainsterms,acronyms,anddefinitions. Copyright©2009–2018,TexasInstrumentsIncorporated DeviceandDocumentationSupport 117 SubmitDocumentationFeedback

CC430F6137,CC430F6135,CC430F6127,CC430F6126,CC430F6125 CC430F5137,CC430F5135,CC430F5133 SLAS554I–MAY2009–REVISEDSEPTEMBER2018 www.ti.com 9 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revisionofthisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 118 Mechanical,Packaging,andOrderableInformation Copyright©2009–2018,TexasInstrumentsIncorporated SubmitDocumentationFeedback

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) CC430F5133IRGZ ACTIVE VQFN RGZ 48 52 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 CC430 & no Sb/Br) F5133 CC430F5133IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 CC430 & no Sb/Br) F5133 CC430F5133IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 CC430 & no Sb/Br) F5133 CC430F5135IRGZ ACTIVE VQFN RGZ 48 52 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 CC430 & no Sb/Br) F5135 CC430F5135IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 CC430 & no Sb/Br) F5135 CC430F5135IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 CC430 & no Sb/Br) F5135 CC430F5137IRGZ ACTIVE VQFN RGZ 48 52 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 CC430 & no Sb/Br) F5137 CC430F5137IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 CC430 & no Sb/Br) F5137 CC430F5137IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS NIPDAU Level-3-260C-168 HR -40 to 85 CC430 & no Sb/Br) F5137 CC430F6125IRGCR ACTIVE VQFN RGC 64 2000 Green (RoHS NIPDAU | NIPDAUAG Level-3-260C-168 HR -40 to 85 CC430F6125 & no Sb/Br) CC430F6126IRGCR ACTIVE VQFN RGC 64 2000 Green (RoHS NIPDAU | NIPDAUAG Level-3-260C-168 HR -40 to 85 CC430F6126 & no Sb/Br) CC430F6127IRGCR ACTIVE VQFN RGC 64 2000 Green (RoHS NIPDAU | NIPDAUAG Level-3-260C-168 HR -40 to 85 CC430F6127 & no Sb/Br) CC430F6127IRGCT ACTIVE VQFN RGC 64 250 Green (RoHS NIPDAU | NIPDAUAG Level-3-260C-168 HR -40 to 85 CC430F6127 & no Sb/Br) CC430F6135IRGCR ACTIVE VQFN RGC 64 2000 Green (RoHS NIPDAU | NIPDAUAG Level-3-260C-168 HR -40 to 85 CC430F6135 & no Sb/Br) CC430F6137IRGCR ACTIVE VQFN RGC 64 2000 Green (RoHS NIPDAU | NIPDAUAG Level-3-260C-168 HR -40 to 85 CC430F6137 & no Sb/Br) CC430F6137IRGCT ACTIVE VQFN RGC 64 250 Green (RoHS NIPDAU | NIPDAUAG Level-3-260C-168 HR -40 to 85 CC430F6137 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 29-May-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) CC430F6125IRGCR VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 CC430F6126IRGCR VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 CC430F6127IRGCR VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 CC430F6127IRGCT VQFN RGC 64 250 180.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 CC430F6135IRGCR VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 CC430F6137IRGCR VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 CC430F6137IRGCT VQFN RGC 64 250 180.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 29-May-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) CC430F6125IRGCR VQFN RGC 64 2000 350.0 350.0 43.0 CC430F6126IRGCR VQFN RGC 64 2000 350.0 350.0 43.0 CC430F6127IRGCR VQFN RGC 64 2000 350.0 350.0 43.0 CC430F6127IRGCT VQFN RGC 64 250 213.0 191.0 55.0 CC430F6135IRGCR VQFN RGC 64 2000 350.0 350.0 43.0 CC430F6137IRGCR VQFN RGC 64 2000 350.0 350.0 43.0 CC430F6137IRGCT VQFN RGC 64 250 213.0 191.0 55.0 PackMaterials-Page2

GENERIC PACKAGE VIEW RGC 64 VQFN - 1 mm max height 9 x 9, 0.5 mm pitch PLASTIC QUAD FLATPACK - NO LEAD Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4224597/A www.ti.com

PACKAGE OUTLINE RGC0064B VQFN - 1 mm max height SCALE 1.500 PLASTIC QUAD FLATPACK - NO LEAD 9.15 A B 8.85 PIN 1 INDEX AREA 9.15 8.85 1.0 0.8 C SEATING PLANE 0.05 0.08 C 0.00 2X 7.5 EXPOSED SYMM (0.2) TYP THERMAL PAD 17 32 16 33 SYMM 65 2X 7.5 4.25 0.1 60X 0.5 1 48 0.30 64X PIN 1 ID 64 49 0.18 0.1 C A B 0.5 64X 0.3 0.05 4219010/A 10/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com

EXAMPLE BOARD LAYOUT RGC0064B VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD ( 4.25) SEE SOLDER MASK SYMM 64X (0.6) DETAIL 64 49 64X (0.24) 1 48 60X (0.5) (R0.05) TYP (1.18) TYP (8.8) 65 SYMM (0.695) TYP ( 0.2) TYP VIA 16 33 17 32 (0.695) TYP (1.18) TYP (8.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X 0.07 MIN 0.07 MAX ALL AROUND ALL AROUND METAL UNDER METAL EDGE SOLDER MASK EXPOSED METAL SOLDER MASK EXPOSED SOLDER MASK OPENING METAL OPENING NON SOLDER MASK DEFINED SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS 4219010/A 10/2018 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com

EXAMPLE STENCIL DESIGN RGC0064B VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD SYMM 64X (0.6) 64 49 64X (0.24) 1 48 60X (0.5) (R0.05) TYP 9X ( 1.19) 65 SYMM (8.8) (1.39) 16 33 17 32 (1.39) (8.8) SOLDER PASTE EXAMPLE BASED ON 0.125 MM THICK STENCIL SCALE: 10X EXPOSED PAD 65 71% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE 4219010/A 10/2018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

GENERIC PACKAGE VIEW RGZ 48 VQFN - 1 mm max height 7 x 7, 0.5 mm pitch PLASTIC QUADFLAT PACK- NO LEAD Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4224671/A www.ti.com

PACKAGE OUTLINE RGZ0048B VQFN - 1 mm max height SCALE 2.000 PLASTIC QUAD FLATPACK - NO LEAD B 7.15 A 6.85 PIN 1 INDEX AREA 7.15 6.85 1 MAX C SEATING PLANE 0.05 0.00 0.08 C 2X 5.5 4.1 0.1 (0.2) TYP EXPOSED 13 24 44X 0.5 THERMAL PAD 12 25 2X 49 SYMM 5.5 0.30 36 48X 1 0.18 0.1 C B A 48 37 0.05 PIN 1 ID SYMM 0.5 (OPTIONAL) 48X 0.3 4218795/B 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. www.ti.com

EXAMPLE BOARD LAYOUT RGZ0048B VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD ( 4.1) (1.115) TYP (0.685) TYP 48 37 48X (0.6) 1 36 48X (0.24) (1.115) TYP 44X (0.5) (0.685) SYMM 49 TYP ( 0.2) TYP (6.8) VIA (R0.05) TYP 12 25 13 24 SYMM (6.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:12X 0.07 MAX 0.07 MIN ALL AROUND ALL AROUND SOLDER MASK METAL OPENING EXPOSED METAL EXPOSED METAL SOLDER MASK METAL UNDER OPENING SOLDER MASK NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4218795/B 02/2017 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com

EXAMPLE STENCIL DESIGN RGZ0048B VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD (1.37) TYP 48 37 48X (0.6) 1 36 48X (0.24) 44X (0.5) (1.37) TYP SYMM 49 (R0.05) TYP (6.8) 9X METAL ( 1.17) TYP 12 25 13 24 SYMM (6.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 49 73% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:12X 4218795/B 02/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com

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