Product Sample & Technical Tools & Support & Folder Buy Documents Software Community CC115L SWRS105B–MAY2011–REVISEDJUNE2014 CC115L Value Line Transmitter 1 Device Overview 1.1 Features 1 • RFPerformance • General – ProgrammableOutputPowerupto+12dBm – FewExternalComponents;FullyIntegrated – ProgrammableDataRatefrom0.6to600kbps FrequencySynthesizer – FrequencyBands:300–348MHz, – GreenPackage:RoHSCompliantandNo 387–464MHz,and779–928MHz AntimonyorBromine – 2-FSK,4-FSK,GFSK,andOOKSupported – SmallSize(QLP4-x4-mmPackage,20Pins) • DigitalFeatures – SuitedforSystemsTargetingCompliancewith EN300220V2.3.1(Europe)andFCCCFRPart – FlexibleSupportforPacketOrientedSystems 15(US) – On-chipSupportforSyncWordInsertion, – SupportforAsynchronousandSynchronous FlexiblePacketLength,andAutomaticCRC SerialTransmitModeforBackward Calculation CompatibilitywithExistingRadio • Low-PowerFeatures CommunicationProtocols – 200-nASleepModeCurrentConsumption – FastStartupTime;240 μsFromSleeptoTX Mode – 64-ByteTXFIFO 1.2 Applications • UltraLow-PowerWirelessApplicationsOperating • RemoteControls inthe315-,433-,868-,915-MHzISMorSRD • Toys Bands • HomeandBuildingAutomation • WirelessAlarmandSecuritySystems • ActiveRFID • IndustrialMonitoringandControl 1.3 Description The CC115L is a cost optimized sub-1 GHz RF transmitter. The circuit is based on the popular CC1101 RF transceiver, and RF performance characteristics are identical. The CC115L value line transmitter togetherwiththeCC113Lvaluelinereceiverenablesalow-costRFlink. The RF transmitter is integrated with a highly configurable baseband modulator. The modem supports variousmodulationformatsandhasaconfigurabledataratesfrom0.6to600kbps. The CC115L provides extensive hardware support for packet handling, data buffering, and burst transmissions. The main operating parameters and the 64-byte transmit FIFO of CC115L can be controlled through a serial peripheral interface (SPI). In a typical system, the CC115L will be used together with a microcontrollerandafewadditionalpassivecomponents. DeviceInformation(1) PARTNUMBER PACKAGE BODYSIZE CC115LRGP QFN(20) 4.00mm×4.00mm (1) Formoreinformationonthesedevices,seeSection8,MechanicalPackagingandOrderable Information. 1 AnIMPORTANTNOTICEattheendofthisdatasheetaddressesavailability,warranty,changes,useinsafety-criticalapplications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

CC115L SWRS105B–MAY2011–REVISEDJUNE2014 www.ti.com 1.4 Functional Block Diagram Figure1-1showsafunctionalblockdiagramofthedevice. Radio Control SCLK SO (GDO1) U C RRFF__PN PA SFYRNETQH Modulator acket Handler TX FIFO Interface to M CSISn P al git Di GDO0 GDO2 BIAS XOSC RBIAS XOSC_Q1 XOSC_Q2 Figure1-1.FunctionalBlockDiagram 2 DeviceOverview Copyright©2011–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L www.ti.com SWRS105B–MAY2011–REVISEDJUNE2014 Table of Contents 1 DeviceOverview......................................... 1 5.9 ModulationFormats................................. 26 .............................................. ........................................ 1.1 Features 1 5.10 RadioControl 27 ........................................... ............................................. 1.2 Applications 1 5.11 TX FIFO 32 ............................................ ............................ 1.3 Description 1 5.12 FrequencyProgramming 34 ............................ ................................................. 1.4 FunctionalBlockDiagram 2 5.13 VCO 35 2 Revision History......................................... 4 5.14 VoltageRegulators.................................. 35 3 TerminalConfigurationandFunctions.............. 5 5.15 OutputPowerProgramming........................ 36 .......................................... .... 3.1 PinDiagram 5 5.16 GeneralPurposeandTestOutputControlPins 38 ................................... .. 3.2 SignalDescriptions 6 5.17 AsynchronousandSynchronousSerialOperation 40 4 Specifications ............................................ 7 5.18 SystemConsiderationsandGuidelines............. 41 .......................... ............................. 4.1 AbsoluteMaximumRatings 7 5.19 ConfigurationRegisters 43 ..................................... .............. 4.2 Handling Ratings 7 5.20 DevelopmentKitOrderingInformation 57 4.3 RecommendedOperatingConditions................ 7 6 Applications,Implementation,andLayout........ 58 .............................. ........................................ 4.4 General Characteristics 7 6.1 BiasResistor 58 ................................. ............................. 4.5 CurrentConsumption 8 6.2 BalunandRFMatching 58 .................................. ............................................... 4.6 RFTransmitSection 9 6.3 Crystal 60 .................................... .................................... 4.7 CrystalOscillator 11 6.4 Reference Signal 60 ............. .................................. 4.8 FrequencySynthesizerCharacteristics 11 6.5 AdditionalFiltering 60 .................................. ........................... 4.9 DCCharacteristics 11 6.6 PowerSupplyDecoupling 60 .................................... ..................... 4.10 Power-OnReset 12 6.7 PCBLayoutRecommendations 61 4.11 Thermal Characteristics............................. 12 7 DeviceandDocumentationSupport............... 62 5 DetailedDescription................................... 13 7.1 DeviceSupport...................................... 62 ............................................ ............................. 5.1 Overview 13 7.2 DocumentationSupport 63 ........................... .......................................... 5.2 FunctionalBlockDiagram 13 7.3 Trademarks 63 ............................. ..................... 5.3 ConfigurationOverview 14 7.4 ElectrostaticDischargeCaution 64 .............................. ............................... 5.4 ConfigurationSoftware 16 7.5 ExportControlNotice 64 ..... ............................................. 5.5 4-wireSerialConfigurationandDataInterface 17 7.6 Glossary 64 ..... ................................ 5.6 MicrocontrollerInterfaceandPinConfiguration 21 7.7 AdditionalAcronyms 64 5.7 DataRateProgramming............................ 22 8 MechanicalPackagingandOrderable ................. Information.............................................. 66 5.8 PacketHandlingHardwareSupport 23 .............................. 8.1 PackagingInformation 66 Copyright©2011–2014,TexasInstrumentsIncorporated TableofContents 3 SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L SWRS105B–MAY2011–REVISEDJUNE2014 www.ti.com 2 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionA(September2011)toRevisionB Page • ChangedformatofdatasheettostandardTIformat. ........................................................................... 1 • Changedresetvaluefrom0x09to0x19......................................................................................... 55 • ChangedthepackagedesignatorfromRTKtoRGP .......................................................................... 66 4 RevisionHistory Copyright©2011–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L www.ti.com SWRS105B–MAY2011–REVISEDJUNE2014 3 Terminal Configuration and Functions 3.1 Pin Diagram The CC115L pinout is shown in Figure 3-1 and Table 3-1. See Section 5.16 for details on the I/O configuration. D R A S D U A D N G BI N SI G D R G 20 19 18 17 16 SCLK1 15 AVDD SO(GDO1)2 14AVDD GDO23 13RF_N DVDD4 12 RF_P DCOUPL5 11 AVDD GND 6 7 8 9 10 Exposed die G C X A X D S O V O attach pad O n S D S 0 C D C _ _ Q Q 1 2 Figure3-1.PinoutTopView NOTE The exposed die attach pad must be connected to a solid ground plane as this is the main groundconnectionforthechip. Copyright©2011–2014,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 5 SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L SWRS105B–MAY2011–REVISEDJUNE2014 www.ti.com 3.2 Signal Descriptions Table3-1.SignalDescriptions PinNo. PinName PinType Description 1 SCLK Digital Serialconfigurationinterface,clockinput Input 2 SO Digital Serialconfigurationinterface,dataoutput (GDO1) Output OptionalgeneraloutputpinwhenCSnishigh 3 GDO2 Digital Digitaloutputpinforgeneraluse: Output • Testsignals • TXFIFOstatussignals • Clockoutput,down-dividedfromXOSC 4 DVDD Power 1.8-3.6VdigitalpowersupplyfordigitalI/Osandforthedigitalcorevoltageregulator (Digital) 5 DCOUPL Power 1.6-2.0Vdigitalpowersupplyoutputfordecoupling (Digital) NOTE: This pin is intended for use with the CC115L only. It can not be used to provide supply voltagetootherdevices 6 GDO0 DigitalI/O Digitaloutputpinforgeneraluse: • Testsignals • TXFIFOstatussignals • Clockoutput,down-dividedfromXOSC • SerialinputTXdata 7 CSn Digital Serialconfigurationinterface,chipselect Input 8 XOSC_Q1 AnalogI/O Crystaloscillatorpin1,orexternalclockinput 9 AVDD Power 1.8-3.6Vanalogpowersupplyconnection (Analog) 10 XOSC_Q2 AnalogI/O Crystaloscillatorpin2 11 AVDD Power 1.8-3.6Vanalogpowersupplyconnection (Analog) 12 RF_P RFI/O PositiveRFoutputsignalfromPAintransmitmode 13 RF_N RFI/O NegativeRFoutputsignalfromPAintransmitmode 14 AVDD Power 1.8-3.6Vanalogpowersupplyconnection (Analog) 15 AVDD Power 1.8-3.6Vanalogpowersupplyconnection (Analog) 16 GND Ground Analoggroundconnection (Analog) 17 RBIAS AnalogI/O Externalbiasresistorforreferencecurrent 18 DGUARD Power Powersupplyconnectionfordigitalnoiseisolation (Digital) 19 GND Ground Groundconnectionfordigitalnoiseisolation (Digital) 20 SI Digital Serialconfigurationinterface,datainput Input 6 TerminalConfigurationandFunctions Copyright©2011–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L www.ti.com SWRS105B–MAY2011–REVISEDJUNE2014 4 Specifications 4.1 Absolute Maximum Ratings Undernocircumstancesmusttheabsolutemaximumratingsbeviolated.Stressexceedingoneormoreofthelimitingvalues maycausepermanentdamagetothedevice. Parameter Min Max Unit Condition Supplyvoltage –0.3 3.9 V Allsupplypinsmusthavethesamevoltage VDD+0.3, Voltageonanydigitalpin –0.3 V max3.9 VoltageonthepinsRF_P,RF_N, –0.3 2.0 V DCOUPL,RBIAS Voltageramp-uprate 120 kV/µs InputRFlevel +10 dBm 4.2 Handling Ratings Parameter MIN MAX UNIT Storagetemperature (default) –50 150 °C range,T stg ESDStressVoltage, HumanBodyModel(HBM),perANSI/ESDA/JEDECJS001(1) 750 V VESD ChargedDeviceModel(CDM),perJJESD22-C101(2) 400 V (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. 4.3 Recommended Operating Conditions Parameter Min Max Unit Condition Operatingtemperature –40 85 °C Operatingsupplyvoltage 1.8 3.6 V Allsupplypinsmusthavethesamevoltage 4.4 General Characteristics Parameter Min Typ Max Unit Condition 300 348 MHz Ifusinga27MHzcrystal,thelowerfrequencylimitforthis Frequencyrange 387 464 MHz bandis392MHz 779 928 MHz 0.6 500 kBaud 2-FSK 0.6 250 kBaud GFSKandOOK Datarate 0.6 300 kBaud 4-FSK(thedatarateinkbpswillbetwicethebaudrate) OptionalManchesterencoding(thedatarateinkbpswillbe halfthebaudrate) Copyright©2011–2014,TexasInstrumentsIncorporated Specifications 7 SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L SWRS105B–MAY2011–REVISEDJUNE2014 www.ti.com 4.5 Current Consumption T = 25°C, VDD = 3.0 V if nothing else stated. All measurement results are obtained using SWRR046 and A SWRR045. spacer Parameter Min Typ Max Unit Condition Voltageregulatortodigitalpartoff,registervaluesretained 0.2 1 µA (SLEEPstate).AllGDOpinsprogrammedto0x2F(HWto 0) Currentconsumption Voltageregulatortodigitalpartoff,registervalues inpowerdownmodes 100 µA retained,XOSCrunning(SLEEPstatewith MCSM0.OSC_FORCE_ONset) Voltageregulatortodigitalparton,allothermodulesin 165 µA powerdown(XOFFstate) Onlyvoltageregulatortodigitalpartandcrystaloscillator 1.7 mA running(IDLEstate) Currentconsumption Onlythefrequencysynthesizerisrunning(FSTXONstate). Thiscurrentconsumptionisalsorepresentativeforthe 8.4 mA otherintermediatestateswhengoingfromIDLEtoTX, includingthecalibrationstate 27.4 mA Transmitmode,+10dBmoutputpower Currentconsumption, 15.0 mA Transmitmode,0dBmoutputpower 315MHz 12.3 mA Transmitmode,–6dBmoutputpower 29.2 mA Transmitmode,+10dBmoutputpower Currentconsumption, 16.0 mA Transmitmode,0dBmoutputpower 433MHz 13.1 mA Transmitmode,–6dBmoutputpower 34.2 mA Transmitmode,+12dBmoutputpower,868MHz 30.0 mA Transmitmode,+10dBmoutputpower,868MHz 16.8 mA Transmitmode,0dBmoutputpower,868MHz Currentconsumption, 16.4 mA Transmitmode,–6dBmoutputpower,868MHz. 868/915MHz 33.4 mA Transmitmode,+11dBmoutputpower,915MHz 30.7 mA Transmitmode,+10dBmoutputpower,915MHz 17.2 mA Transmitmode,0dBmoutputpower,915MHz 17.0 mA Transmitmode,–6dBmoutputpower,915MHz 4.5.1 Typical TX Current Consumption over Temperature and Supply Voltage, 868 MHz SupplyVoltage SupplyVoltage SupplyVoltage VDD=1.8V VDD=3.0V VDD=3.6V Temperature[°C] −40 25 85 −40 25 85 −40 25 85 Current[mA],PATABLE=0xC0,+12dBm 32.7 31.5 30.5 35.3 34.2 33.3 35.5 34.4 33.5 Current[mA],PATABLE=0xC5,+10dBm 30.1 29.2 28.3 30.9 30.0 29.4 31.1 30.3 29.6 Current[mA],PATABLE=0x50,0dBm 16.4 16.0 15.6 17.3 16.8 16.4 17.6 17.1 16.7 4.5.2 Typical TX Current Consumption over Temperature and Supply Voltage, 915 MHz SupplyVoltage SupplyVoltage SupplyVoltage VDD=1.8V VDD=3.0V VDD=3.6V Temperature[°C] −40 25 85 −40 25 85 −40 25 85 Current[mA],PATABLE=0xC0,+11dBm 31.9 30.7 29.8 34.6 33.4 32.5 34.8 33.6 32.7 Current[mA],PATABLE=0xC3,+10dBm 30.9 29.8 28.9 31.7 30.7 30.0 31.9 31.0 30.2 Current[mA],PATABLE=0x8E,0dBm 17.2 16.8 16.4 17.6 17.2 16.9 17.8 17.4 17.1 8 Specifications Copyright©2011–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L www.ti.com SWRS105B–MAY2011–REVISEDJUNE2014 4.6 RF Transmit Section T =25°C,VDD=3.0V,+10dBmifnothingelsestated.AllmeasurementresultsareobtainedusingSWRR046and A SWRR045. Parameter Min Typ Max Unit Condition Differentialload impedance 315MHz 122+j31 Ω DifferentialimpedanceasseenfromtheRF-port(RF_P andRF_N)towardstheantenna. 433MHz 116+j41 Ω 868/915MHz 86.5+j43 Ω Outputpower,highest Outputpowerisprogrammable,andfullrangeis setting availableinallfrequencybands.Outputpowermaybe restrictedbyregulatorylimits. 315MHz +10 dBm SeeDesignNoteDN013SWRA168,whichgivesthe 433MHz +10 dBm outputpowerandharmonicswhenusingmulti-layer inductors.Theoutputpoweristhentypically+10dBm 868MHz +12 dBm whenoperatingat868/915MHz. 915MHz +11 dBm Deliveredtoa50-Ωsingle-endedloadthroughtheRF matchingnetworkinSWRR046andSWRR045 Outputpowerisprogrammable,andfullrangeis Outputpower,lowest availableinallfrequencybands −30 dBm setting Deliveredtoa50-Ωsingle-endedloadthroughtheRF matchingnetworkinSWRR046andSWRR045 Harmonics,radiated MeasuredonSWRR046andSWRR045withCW, maximumoutputpower 2ndHarm,433MHz −49 dBm Theantennasusedduringtheradiatedmeasurements 3rdHarm,433MHz −40 dBm (SMAFF-433fromR.W.BadlandandNearsonS331 868/915)playapartinattenuatingtheharmonics 2ndHarm,868MHz −47 dBm Note:Allharmonicsarebelow−41.2dBmwhen 3rdHarm,868MHz −55 dBm operatinginthe902-928MHzband 2ndHarm,915MHz −50 dBm 3rdHarm,915MHz −54 dBm Harmonics,conducted Measuredwith+10dBmCWat315MHzand433MHz 315MHz <−35 dBm Frequenciesbelow960MHz <−53 dBm Frequenciesabove960MHz 433MHz −43 dBm Frequenciesbelow1GHz <−45 dBm Frequenciesabove1GHz 868MHz2ndHarm −36 dBm Measuredwith+12dBmCWat868MHz otherharmonics <−46 dBm 915MHz2ndHarm −34 dBm Measuredwith+11dBmCWat915MHz(requirementis otherharmonics −20dBcunderFCC15.247) Otherharmonics <−50 dBm Spuriousemissions Measuredwith+10dBmCWat315MHzand433MHz conducted,harmonics notincluded 315MHz <−58 Frequenciesbelow960MHz <−53 Frequenciesabove960MHz 433MHz <−50 Frequenciesbelow1GHz <−54 Frequenciesabove1GHz <−56 Frequencieswithin47-74,87.5-118,174-230,470-862 MHz Measuredwith+12dBmCWat868MHz 868MHz <−50 Frequenciesbelow1GHz <−52 Frequenciesabove1GHz <−53 Frequencieswithin47-74,87.5-118,174-230,470-862 MHz Copyright©2011–2014,TexasInstrumentsIncorporated Specifications 9 SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L SWRS105B–MAY2011–REVISEDJUNE2014 www.ti.com T =25°C,VDD=3.0V,+10dBmifnothingelsestated.AllmeasurementresultsareobtainedusingSWRR046and A SWRR045. Parameter Min Typ Max Unit Condition Allradiatedspuriousemissionsarewithinthelimitsof ETSI.Thepeakconductedspuriousemissionis−53 dBmat699MHz(868MHz-169MHz),whichisina frequencybandlimitedto−54dBmbyEN300220 V2.3.1.Analternativefiltercanbeusedtoreducethe emissionat699MHzbelow−54dBm,forconducted measurements,andisshowninFigure6-2.Seemore informationinDN017SWRA168. Forcompliancewithmodulationbandwidthrequirements underEN300220V2.3.1inthe863to870MHz frequencyrangeitisrecommendedtousea26MHz crystalforfrequenciesbelow869MHzanda27MHz crystalforfrequenciesabove869MHz. Measuredwith+11dBmCWat915MHz <−51 Frequenciesbelow960MHz 915MHz <−54 Frequenciesabove960MHz TXlatency 8 bit Serialoperation.Timefromsamplingthedataonthe transmitterdatainputpinuntilitisobservedontheRF outputports. 4.6.1 Typical Variation in Output Power over Temperature and Supply Voltage, 868 MHz SupplyVoltage SupplyVoltage SupplyVoltage VDD=1.8V VDD=3.0V VDD=3.6V Temperature[°C] −40 25 85 −40 25 85 −40 25 85 OutputPower[dBm],PATABLE=0xC0,+12dBm 12 11 10 12 12 11 12 12 11 OutputPower[dBm],PATABLE=0xC5,+10dBm 11 10 9 11 10 10 11 10 10 OutputPower[dBm],PATABLE=0x50,0dBm 1 0 -1 2 1 0 2 1 0 4.6.2 Typical Variation in Output Power over Temperature and Supply Voltage, 915 MHz SupplyVoltage SupplyVoltage SupplyVoltage VDD=1.8V VDD=3.0V VDD=3.6V Temperature[°C] −40 25 85 −40 25 85 −40 25 85 OutputPower[dBm],PATABLE=0xC0,+11dBm 11 10 10 12 11 11 12 11 11 OutputPower[dBm],PATABLE=0x8E,+0dBm 2 1 0 2 1 0 2 1 0 10 Specifications Copyright©2011–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L www.ti.com SWRS105B–MAY2011–REVISEDJUNE2014 4.7 Crystal Oscillator T =25°C,VDD=3.0Vifnothingelseisstated.AllmeasurementresultsobtainedusingSWRR046andSWRR045. A Parameter Min Typ Max Unit Condition Forcompliancewithmodulationbandwidth requirementsunderEN300220V2.3.1inthe 863to870MHzfrequencyrangeitis Crystalfrequency 26 26 27 MHz recommendedtousea26MHzcrystalfor frequenciesbelow869MHzanda27MHz crystalforfrequenciesabove869MHz. Thisisthetotaltoleranceincludinga)initial tolerance,b)crystalloading,c)aging,andd) Tolerance ±40 ppm temperaturedependence.Theacceptable crystaltolerancedependsonRFfrequency andchannelspacing/bandwidth. Loadcapacitance 10 13 20 pF Simulatedoveroperatingconditions ESR 100 Ω Thisparameteristoalargedegreecrystal Start-uptime 150 µs dependent.MeasuredonSWRR046and SWRR045usingcrystalAT-41CD2fromNDK 4.8 Frequency Synthesizer Characteristics T =25°C,VDD=3.0Vifnothingelseisstated.AllmeasurementresultsareobtainedusingSWRR046andSWRR045. A Minimumfiguresaregivenusinga27MHzcrystal.Typicalandmaximumfiguresaregivenusinga26MHzcrystal. Parameter Min Typ Max Unit Condition Programmedfrequencyresolution 397 F /216 412 Hz 26-to27-MHzcrystal.Theresolution(inHz) XOSC isequalforallfrequencybands Givenbycrystalused.Requiredaccuracy (includingtemperatureandaging)depends Synthesizerfrequencytolerance ±40 ppm onfrequencybandandchannelbandwidth/ spacing RFcarrierphasenoise –92 dBc/Hz at50kHzoffsetfromcarrier RFcarrierphasenoise –92 dBc/Hz at100kHzoffsetfromcarrier RFcarrierphasenoise –92 dBc/Hz at200kHzoffsetfromcarrier RFcarrierphasenoise –98 dBc/Hz at500kHzoffsetfromcarrier RFcarrierphasenoise –107 dBc/Hz at1MHzoffsetfromcarrier RFcarrierphasenoise –113 dBc/Hz at2MHzoffsetfromcarrier RFcarrierphasenoise –119 dBc/Hz at5MHzoffsetfromcarrier RFcarrierphasenoise –129 dBc/Hz at10MHzoffsetfromcarrier TimefromleavingtheIDLEstateuntilarriving PLLturn-onorhoptime intheFSTXONorTXstate,whennot 72 75 75 µs (SeeTable5-5) performingcalibration.Crystaloscillator running. Calibrationcanbeinitiatedmanuallyor PLLcalibrationtime 685 712 724 µs automaticallybeforeenteringorafterleaving (SeeTable5-6) TX 4.9 DC Characteristics T =25°Cifnothingelsestated. A DigitalInputs/Outputs Min Max Unit Condition Logic"0"inputvoltage 0 0.7 V Logic"1"inputvoltage VDD–0.7 VDD V Logic"0"outputvoltage 0 0.5 V Forupto4mAoutputcurrent Logic"1"outputvoltage VDD–0.3 VDD V Forupto4mAoutputcurrent Logic"0"inputcurrent N/A –50 nA Inputequals0V Logic"1"inputcurrent N/A 50 nA InputequalsVDD Copyright©2011–2014,TexasInstrumentsIncorporated Specifications 11 SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L SWRS105B–MAY2011–REVISEDJUNE2014 www.ti.com 4.10 Power-On Reset ForproperPower-On-ResetfunctionalitythepowersupplyshouldcomplywiththerequirementsinSection4.10.Otherwise, thechipshouldbeassumedtohaveunknownstateuntiltransmittinganSRESstrobeovertheSPIinterface.See Section5.10.1,Power-OnStart-UpSequence,forfurtherdetails. Parameter Min Typ Max Unit Condition Power-upramp-uptime 5 ms From0Vuntilreaching1.8V Minimumtimebetweenpower-onandpower- Powerofftime 1 ms off 4.11 Thermal Characteristics NAME DESCRIPTION QFN(°C/W) R Junction-to-ambientthermalresistance 47 θJA R Junction-to-case(top)thermalresistance 45 θJC(top) R Junction-to-boardthermalresistance 13.6 θJB R Junction-to-case(bottom)thermalresistance 5.12 θJC(bot) 12 Specifications Copyright©2011–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L www.ti.com SWRS105B–MAY2011–REVISEDJUNE2014 5 Detailed Description 5.1 Overview The CC115L transmitter is based on direct synthesis of the RF frequency. The frequency synthesizer includesacompletelyon-chipLCVCO. A crystal is to be connected to XOSC_Q1 and XOSC_Q2. The crystal oscillator generates the reference frequencyforthesynthesizer,aswellasclocksfortheADCandthedigitalpart. A4-wireSPIisusedforconfigurationanddatabufferaccess. Thedigitalbasebandincludessupportforchannelconfiguration,packethandling,anddatabuffering. 5.2 Functional Block Diagram AsimplifiedblockdiagramofCC115LisshowninFigure5-1. Radio Control SCLK SO (GDO1) U C RRFF__PN PA SFYRNETQH Modulator acket Handler TX FIFO Interface to M CSISn P al git Di GDO0 GDO2 BIAS XOSC RBIAS XOSC_Q1 XOSC_Q2 Figure5-1.CC115LSimplifiedBlockDiagram Copyright©2011–2014,TexasInstrumentsIncorporated DetailedDescription 13 SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L SWRS105B–MAY2011–REVISEDJUNE2014 www.ti.com 5.3 Configuration Overview CC115L can be configured to achieve optimum performance for many different applications. Configuration is done using the SPI interface. See Section 5.5 for more description of the SPI interface. The following keyparameterscanbeprogrammed: • Power-down/powerupmode • Crystaloscillatorpower-up/power-down • Carrierfrequency/RFchannel • Transmitmode • Datarate • Modulationformat • RFoutputpower • Databufferingwithseparate64-byteTXFIFO • Packetradiohardwaresupport DetailsofeachconfigurationregistercanbefoundinSection5.19. Figure 5-2 shows a simplified state diagram that explains the main CC115L states together with typical usage and current consumption. For detailed information on controlling the CC115L state machine, and a completestatediagram,seeSection5.10. 14 DetailedDescription Copyright©2011–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L www.ti.com SWRS105B–MAY2011–REVISEDJUNE2014 Lowest power mode. Most register values are retained. Sleep Typ. current consumption: SIDLE SPWD 200 nA Default state when the radio is not transmitting.Typ.current CSn=0 consumption: 1.7 mA. IDLE SXOFF Used for calibrating frequency SCAL synthesizer upfront (entering CSn=0 All register values are transmit mode can then be Manual freq. Crystal retained.Typ. current done quicker).Transitional synth. calibration oscillator off STX or SFSTXON consumption: 165 uA. state.Typ.current consumption: 8.4 mA. Frequency Frequency synthesizer is turned on, can optionally be synthesizer startup, calibrated, and then settles to the correct frequency. SFSTXON optional calibration, Frequency synthesizer is on, Transitional state.Typ. current consumption: 8.4 mA. settling ready to start transmitting. Transmission starts very Frequency quickly after receiving the STX synthesizer on command strobe.Typ. current consumption: 8.4 mA. STX STX TXOFF_MODE=01 Typ. current consumption: 16.8 mAat 0 dBm output Transmit mode power, 868 MHz TXOFF_MODE=00 In Normal mode, this state is enetered if theTX FIFO is emptied TX FIFO Optional transitional state. Optional freq. before the complete packet has underflow Typ. current consumption: 8.4 mA. synth. calibration been written to the FIFO. Typ. current consumption: 1.7 mA. SFTX IDLE Figure5-2.SimplifiedRadioControlStateDiagramwithTypicalCurrentConsumption Copyright©2011–2014,TexasInstrumentsIncorporated DetailedDescription 15 SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L SWRS105B–MAY2011–REVISEDJUNE2014 www.ti.com 5.4 Configuration Software CC115L can be configured using the SmartRF™ Studio software SWRC176. The SmartRF Studio software is highly recommended for obtaining optimum register settings, and for evaluating performance andfunctionality. After chip reset, all the registers have default values as shown Section 5.19. The optimum register setting might differ from the default value. After a reset all registers that shall be different from the default value thereforeneedstobeprogrammedthroughtheSPIinterface. 16 DetailedDescription Copyright©2011–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L www.ti.com SWRS105B–MAY2011–REVISEDJUNE2014 5.5 4-wire Serial Configuration and Data Interface CC115L is configured through a simple 4-wire SPI-compatible interface (SI, SO, SCLK and CSn) where CC115L is the slave. This interface is also used write buffered data. All transfers on the SPI interface are donemostsignificantbitfirst. All transactions on the SPI interface start with a header byte containing a R/W bit, a burst access bit (B), anda6-bitaddress(A –A ). 5 0 The CSn pin must be kept low during transfers on the SPI bus. If CSn goes high during the transfer of a header byte or during read/write from/to a register, the transfer will be cancelled. The timing for the addressanddatatransferontheSPIinterfaceisshowninFigure5-3 withreferencetoTable5-1. When CSn is pulled low, the MCU must wait until CC115L SO pin goes low before starting to transfer the header byte. This indicates that the crystal is running. Unless the chip was in the SLEEP or XOFF states, theSOpinwillalwaysgolowimmediatelyaftertakingCSnlow. t t t t t t sp ch cl sd hd ns SCLK: CSn: Write to register: SI X 0 B A5 A4 A3 A2 A1 A0 X DW7 DW6 DW5 DW4 DW3 DW2 DW1 DW0 X SO Hi-Z S7 B S5 S4 S3 S2 S1 S0 S7 S6 S5 S4 S3 S2 S1 S0 Hi-Z Read from register: SI X 1 B A5 A4 A3 A2 A1 A0 X SO Hi-Z S7 B S5 S4 S3 S2 S1 S0 DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 Hi-Z Figure5-3.ConfigurationRegistersWriteandReadOperations Table5-1.SPIInterfaceTimingRequirements Parameter Description Min Max Units SCLKfrequency 100nsdelayinsertedbetweenaddressbyteanddatabyte(singleaccess),or – 10 betweenaddressanddata,andbetweeneachdatabyte(burstaccess). f SCLKfrequency,singleaccess MHz SCLK – 9 Nodelaybetweenaddressanddatabyte SCLKfrequency,burstaccess – 6.5 Nodelaybetweenaddressanddatabyte,orbetweendatabytes t CSnlowtopositiveedgeonSCLK,inpower-downmode 150 – µs sp,pd t CSnlowtopositiveedgeonSCLK,inactivemode 20 – ns sp t Clockhigh 50 – ns ch t Clocklow 50 – ns cl t Clockrisetime – 40 ns rise t Clockfalltime – 40 ns fall Setupdata(negativeSCLKedge)topositiveedgeon Singleaccess 55 – t SCLK(tsdappliesbetweenaddressanddatabytes, ns sd andbetweendatabytes) Burstaccess 76 – t HolddataafterpositiveedgeonSCLK 20 – ns hd t NegativeedgeonSCLKtoCSnhigh. 20 – ns ns Copyright©2011–2014,TexasInstrumentsIncorporated DetailedDescription 17 SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L SWRS105B–MAY2011–REVISEDJUNE2014 www.ti.com NOTE The minimum t figure in Table 5-1 can be used in cases where the user does not read sp,pd the CHIP_RDYn signal. CSn low to positive edge on SCLK when the chip is woken from power-downdependsonthestart-uptimeofthecrystalbeingused.The150μsinTable5-1 is the crystal oscillator start-up time measured on SWRR046 and SWRR045 using crystal AT-41CD2fromNDK. 5.5.1 Chip Status Byte When the header byte, data byte, or command strobe is sent on the SPI interface, the chip status byte is sent by the CC115L on the SO pin. The status byte contains key status signals, useful for the MCU. The first bit, s7, is the CHIP_RDYn signal and this signal must go low before the first positive edge of SCLK. TheCHIP_RDYnsignalindicatesthatthecrystalisrunning. Bits6,5,and4comprisetheSTATE value.Thisvaluereflectsthestateofthechip.TheXOSCandpower to the digital core are on in the IDLE state, but all other modules are in power down. The frequency and channelconfigurationshouldonlybeupdatedwhenthechipisinthisstate. The last four bits (3:0) in the status byte contains FIFO_BYTES_AVAILABLE. For these bits to give any valid information, the R/W bit in the header byte must be set to 0. The FIFO_BYTES_AVAILABLE field containsthenumberofbytesthatcanbewrittentotheTXFIFO.WhenFIFO_BYTES_AVAILABLE=15,15 ormorebytescanbewritten. Table5-2givesastatusbytesummary. Table5-2.StatusByteSummary Bits Name Description Stayshighuntilpowerandcrystalhavestabilized.Shouldalwaysbelowwhen 7 CHIP_RDYn usingtheSPIinterface. Indicatesthecurrentmainstatemachinemode Value State Description IDLEstate 000 IDLE (Alsoreportedforsometransitionalstates insteadofSETTLINGorCALIBRATE) 001 Reserved 010 TX Transmitmode 6:4 STATE[2:0] 011 FSTXON FastTXready Frequencysynthesizercalibrationis 100 CALIBRATE running 101 SETTLING PLLissettling 110 Reserved TXFIFOhasunderflowed.Acknowledge 111 TXFIFO_UNDERFLOW withSFTX 3:0 FIFO_BYTES_AVAILABLE[3:0] ThenumberofbytesthatcanbewrittentotheTXFIFO 18 DetailedDescription Copyright©2011–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L www.ti.com SWRS105B–MAY2011–REVISEDJUNE2014 5.5.2 Register Access The configuration registers on the CC115L are located on SPI addresses from 0x00 to 0x2E. Table 5-14 lists all configuration registers. It is highly recommended to use SmartRF Studio SWRC176 to generate optimum register settings. The detailed description of each register is found in Section 5.19.1 and Section 5.19.2. All configuration registers can be both written to and read. The R/W bit controls if the register should be written to or read. When writing to registers, the status byte is sent on the SO pin each time a header byte or data byte is transmitted on the SI pin. When reading from registers, the status byte issentontheSOpineachtimeaheaderbyteistransmittedontheSIpin. Registers with consecutive addresses can be accessed in an efficient way by setting the burst bit (B) in the header byte. The address bits (A - A ) set the start address in an internal address counter. This 5 0 counter is incremented by one each new byte (every 8 clock pulses). The burst access is either a read or awriteaccessandmustbeterminatedbysettingCSnhigh. For register addresses in the range 0x30 - 0x3D, the burst bit is used to select between status registers when burst bit is one, and between command strobes when burst bit is zero (see Section 5.5.3). Because of this, burst access is not available for status registers and they must be accessed one at a time. The statusregisterscanonlyberead. 5.5.3 SPI Read When reading register fields over the SPI interface while the register fields are updated by the radio hardware (that is, MARCSTATE or TXBYTES), there is a small, but finite, probability that a single read from the register is being corrupt. As an example, the probability of any single read from TXBYTES being corrupt, assuming the maximum data rate is used, is approximately 80 ppm. Refer to the CC115L Errata NotesSWRZ037formoredetails. 5.5.4 Command Strobes Command Strobes may be viewed as single byte instructions to CC115L. By addressing a command strobe register, internal sequences will be started. These commands are used to disable the crystal oscillator,enabletransmitmode,enablecalibrationetc.The11commandstrobesarelistedinTable5-13. NOTE An SIDLE strobe will clear all pending command strobes until IDLE state is reached. This meansthatifforexampleanSIDLEstrobeisissuedwhiletheradioisinTXstate,anyother commandstrobesissuedbeforetheradioreachesIDLEstatewillbeignored. The command strobe registers are accessed by transferring a single header byte (no data is being transferred). That is, only the R/W bit, the burst access bit (set to 0), and the six address bits (in the range 0x30 through 0x3D) are written. The R/W bit should be set to zero if the FIFO_BYTES_AVAILABLE field inthestatusbyteshouldbeinterpreted. Whenwritingcommandstrobes,thestatusbyteissentontheSOpin. A command strobe may be followed by any other SPI access without pulling CSn high. However, if an SRESstrobeisbeingissued,onewillhavetowaitforSOtogolowagainbeforethenextheaderbytecan be issued as shown in Figure 5-4. The command strobes are executed immediately, with the exception of theSPWDandtheSXOFFstrobes,whichareexecutedwhenCSngoeshigh. CSn SO SI HeaderSRES HeaderAddr Data Figure5-4.SRESCommandStrobe Copyright©2011–2014,TexasInstrumentsIncorporated DetailedDescription 19 SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L SWRS105B–MAY2011–REVISEDJUNE2014 www.ti.com 5.5.5 TX FIFO Access The 64-byte TX FIFO is accessed through the 0x3F address. The TX FIFO is write-only and the R/W bit shouldthereforebezero. The burst bit is used to determine if the TX FIFO access is a single byte access or a burst access. The single byte access method expects a header byte with the burst bit set to zero and one data byte. After the data byte, a new header byte is expected; hence CSn can remain low. The burst access method expects one header byte and then consecutive data bytes until terminating the access by setting CSn high. ThefollowingheaderbytesaccesstheFIFO: • 0x3F:SinglebyteaccesstoTXFIFO • 0x7F:BurstaccesstoTXFIFO When writing to the TX FIFO, the status byte (see Section 5.5.1) is output on SO for each new data byte as shown in Figure 5-3. This status byte can be used to detect TX FIFO underflow while writing data to the TX FIFO. Note that the status byte contains the number of bytes free before writing the byte in progress to the TX FIFO. When the last byte that fits in the TX FIFO is transmitted on SI, the status byte receivedconcurrentlyonSOwillindicatethatonebyteisfreeintheTXFIFO. The TX FIFO may be flushed by issuing a SFTX command strobe. A SFTX command strobe can only be issued in the IDLE, or TXFIFO_UNDERFLOW states. The TX FIFO is flushed when going to the SLEEP state. Figure5-5givesabriefoverviewofdifferentregisteraccesstypespossible. 5.5.6 PATABLE Access The 0x3E address is used to access the PATABLE, which is used for selecting PA power control settings. The SPI expects one or two data bytes after receiving the address (the burst bit must be set if two bytes are to be written). For OOK, two bytes should be written to PATABLE; the first byte after the address will set the logic 0 power level and the second byte written will set the logic 1 power level. For all other modulations formats, only one byte should be written to PATABLE. Use SmartRF Studio SWRC176 or DN013SWRA168forrecommendedregistervaluesforagivenoutputpower. The PATABLE can also be read by setting the R/W bit to 1. The read operation can be done as a single byte or burst access, depending on how many bytes should be read (one or two). Note that pulling CSn high will reset the index counter to zero, meaning that burst access needs to be used for reading/writing the second PATABLE entry. For the same reason, if one byte is written to the PATABLE and this value is to be read out, CSn must be set high before the read access in order to set the index counter back to zero. ThecontentofthePATABLEislostwhenenteringtheSLEEPstate,exceptforthefirstbyte,meaningthat ifOOKisused,thePATABLEneedstobereprogrammedwhenwakingupfromSLEEP. CSn: Command strobe(s): HeaderStrobe HeaderStrobe HeaderStrobe Read or write register(s): HeaderReg Data HeaderReg Data HeaderReg Data Read or write rceognissteecrsu t(isv)e: HeaderReg n Datan Datan + 1 Datan + 2 Wtroit eth ne +T X1 FbIyFteOs: HeaderFIFO DataByte 0 DataByte 1 DataByte 2 DataByte n - 1 DataByte n Combinations: HeaderReg Data HeaderStrobe HeaderReg Data HeaderStrobe HeaderFIFO DataByte 0 DataByte 1 Figure5-5.RegisterAccessTypes 20 DetailedDescription Copyright©2011–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L www.ti.com SWRS105B–MAY2011–REVISEDJUNE2014 5.6 Microcontroller Interface and Pin Configuration Inatypicalsystem,CC115Lwillinterfacetoamicrocontroller.Thismicrocontrollermustbeableto: • ProgramCC115Lintodifferentmodes • Writebuffereddata • Read back status information through the 4-wire SPI-bus configuration interface (SI, SO, SCLK, and CSn) 5.6.1 Configuration Interface The microcontroller uses four I/O pins for the SPI configuration interface (SI, SO, SCLK, and CSn). The SPIisdescribedinSection5.5. 5.6.2 General Control and Status Pins The CC115L has two dedicated configurable pins (GDO0 and GDO2) and one shared pin (GDO1) that can output internal status information useful for control software. These pins can be used to generate interruptsontheMCU.SeeSection5.16 formoredetailsonthesignalsthatcanbeprogrammed. GDO1 is shared with the SO pin in the SPI interface. The default setting for GDO1/SO is 3-state output. By selecting any other of the programming options, the GDO1/SO pin will become a generic pin. When CSnislow,thepinwillalwaysfunctionasanormalSOpin. In the synchronous and asynchronous serial modes, the GDO0 pin is used as a serial TX data input pin whileintransmitmode. Copyright©2011–2014,TexasInstrumentsIncorporated DetailedDescription 21 SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L SWRS105B–MAY2011–REVISEDJUNE2014 www.ti.com 5.7 Data Rate Programming The data rate used when transmitting is programmed by the MDMCFG3.DRATE_M and the MDMCFG4.DRATE_E configuration registers. The data rate is given by the formula below. As the formula shows,theprogrammeddataratedependsonthecrystalfrequency. (256+DRATE_M)×2DRATE_E R = ׃ DATA 228 XOSC (1) Thefollowingapproachcanbeusedtofindsuitablevaluesforagivendatarate: æR ×220 ö DRATE_E=log ç DATA ÷ 2ç ÷ è ƒXOSC ø (2) R ×228 DRATE_M= DATA -256 ƒ ×2DRATE_E XOSC (3) If DRATE_M is rounded to the nearest integer and becomes 256, increment DRATE_E and use DRATE_M=0. Thedataratecanbesetfrom0.6kBaudto500kBaudwiththeminimumstepsizeaccordingtoTable5-3. SeeSection4.4fortheminimumandmaximumdataratesforthedifferentmodulationformats. Table5-3.DataRateStepSize(Assuminga26-MHzCrystal) MinDataRate[kBaud] TypicalDataRate[kBaud] MaxDataRate[kBaud] DatarateStepSize[kBaud] 0.6 1.0 0.79 0.0015 0.79 1.2 1.58 0.0031 1.59 2.4 3.17 0.0062 3.17 4.8 6.33 0.0124 6.35 9.6 12.7 0.0248 12.7 19.6 25.3 0.0496 25.4 38.4 50.7 0.0992 50.8 76.8 101.4 0.1984 101.6 153.6 202.8 0.3967 203.1 250 405.5 0.7935 406.3 500 500 1.5869 22 DetailedDescription Copyright©2011–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L www.ti.com SWRS105B–MAY2011–REVISEDJUNE2014 5.8 Packet Handling Hardware Support The CC115L has built-in hardware support for packet oriented radio protocols. The packet handler can be configuredtoaddthefollowingelementstothepacketstoredintheTXFIFO: • Aprogrammablenumberofpreamblebytes • A two byte synchronization (sync) word. Can be duplicated to give a 4-byte sync word. It is not possibletoonlyinsertpreambleoronlyinsertasyncword • ACRCchecksumcomputedoverthedatafield. • In a system where the CC115L is transmitting packets to the CC110L, CC113L or CC1101, the recommendedsettingis4-bytepreambleand4-bytesyncword,exceptfor500kBauddataratewhere therecommendedpreamblelengthis8bytes. NOTE RegisterfieldsthatcontrolthepackethandlingfeaturesshouldonlybealteredwhenCC115L isintheIDLEstate. 5.8.1 Packet Format Theformatofthedatapacketcanbeconfiguredandconsistsofthefollowingitems(seeFigure5-6): • Preamble • Synchronizationword • Optionallengthbyte • Optionaladdressbyte • Payload • Optional2byteCRC Legend: Optional CRC-16Calculation Inserted automatically P(1r0ea1m0.b..l1e0b1i0ts) SyncWord Length Field Address Field Data Field CRC-16 Oprpotcioensasle uds beyr- tphreo vriaddeido)fields (the length field is Unprocesseduser data 8 8 8x nbits 16/32 bits 8x nbits 16 bits bits bits Figure5-6.PacketFormat The preamble pattern is an alternating sequence of ones and zeros (10101010…). The minimum length of the preamble is programmable through the value of MDMCFG1.NUM_PREAMBLE. When enabling TX, the modulator will start transmitting the preamble. When the programmed number of preamble bytes has been transmitted, the modulator will send the sync word and then data from the TX FIFO if data is available. If the TX FIFO is empty, the modulator will continue to send preamble bytes until the first byte is writtentotheTXFIFO.Themodulatorwillthensendthesyncwordandthenthedatabytes. The synchronization word is a two-byte value set in the SYNC1 and SYNC0 registers. If the CC110L, CC113L, or CC1101 are used at the receiving end, they will need the sync word for byte synchronization of the incoming packet. The synchronization word is automatically inserted by the CC115L. A one-byte sync word can be emulated by setting the SYNC1 value to the preamble pattern. It is also possible to emulatea32bitsyncwordbysettingMDMCFG2.SYNC_MODEto3.Thesyncwordwillthenberepeated twice. CC115L supports both constant packet length protocols and variable length protocols. Variable or fixed packet length mode can be used for packets up to 255 bytes. For longer packets, infinite packet length modemustbeused. Copyright©2011–2014,TexasInstrumentsIncorporated DetailedDescription 23 SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L SWRS105B–MAY2011–REVISEDJUNE2014 www.ti.com Fixed packet length mode is selected by setting PKTCTRL0.LENGTH_CONFIG=0. The desired packet lengthissetbythePKTLEN register.Thisvaluemustbedifferentfrom0. In variable packet length mode, PKTCTRL0.LENGTH_CONFIG=1, the packet length is configured by the first byte transmitted after the sync word. The packet length is defined as the payload data, excluding the lengthbyteandtheoptionalCRC.ThePKTLEN valuemustbedifferentfrom0. With PKTCTRL0.LENGTH_CONFIG=2, the packet length is set to infinite and transmission will continue until turned off manually. As described in , this can be used to support packet formats with different length configuration than natively supported by CC115L. One should make sure that TX mode is not turned off during the transmission of the first half of any byte. Refer to the CC115L Errata Notes SWRZ036 for more details. NOTE The minimum packet length supported (excluding the optional length byte and CRC) is one byteofpayloaddata. 5.8.1.1 PacketLength> 255 The packet automation control register, PKTCTRL0, can be reprogrammed during TX. This opens the possibility to transmit packets that are longer than 256 bytes and still be able to use the packet handling hardware support. At the start of the packet, the infinite packet length mode ( PKTCTRL0.LENGTH_CONFIG=2) must be active and the PKTLEN register is set to mod(length, 256). When less than 256 bytes remains of the packet, the MCU disables infinite packet length mode and activates fixed packet length mode ( PKTCTRL0.LENGTH_CONFIG=0). When the internal byte counter reaches the PKTLEN value, the transmission ends (the radio enters the state determined by TXOFF_MODE). Automatic CRC appending/checking can also be used (by setting PKTCTRL0.CRC_EN=1). When for example a 600-byte packet is to be transmitted, the MCU should do the following (see Figure 5- 7). • SetPKTCTRL0.LENGTH_CONFIG=2. • Pre-programthePKTLEN registertomod(600,256)=88. • Transmitatleast345bytes(600-255),forexamplebyfillingthe64-byteTXFIFOsixtimes(384bytes transmitted). • SetPKTCTRL0.LENGTH_CONFIG=0. • Thetransmissionendswhenthepacketcounterreaches88.Atotalof600bytesaretransmitted. Internal byte counter in packet handler counts from 0 to 255 and then starts at 0 again 0, 1............, 88,.............................................255, 0, ........, 88, .............................................255, 0, ........, 88, .............................................255, 0, .. Infinite packet length mode enabled Fixed packet length mode anbled when 600 bytes transmitted less than 256 bytes remains of packet Length field transmitted. PKTLEN set to mod(600, 256) = 88 Figure5-7.PacketLength > 255 24 DetailedDescription Copyright©2011–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L www.ti.com SWRS105B–MAY2011–REVISEDJUNE2014 5.8.2 Packet Handling The payload that is to be transmitted must be written into the TX FIFO. The first byte written must be the length byte when variable packet length is enabled. The length byte has a value equal to the payload of the packet (including the optional address byte). If the receiver is the CC110L, CC113L, or CC1101, and addressrecognitionisenabled,thesecondbytewrittentotheTXFIFOmustbetheaddressbyte. Iffixedpacketlengthisenabled,thefirstbytewrittentotheTXFIFOshouldbetheaddress(assumingthe receiverusesaddressrecognition). The modulator will first send the programmed number of preamble bytes. If data is available in the TX FIFO, the modulator will send the two-byte (optionally 4-byte) sync word followed by the payload in the TX FIFO. If CRC is enabled, the checksum is calculated over all the data pulled from the TX FIFO, and the result is sent as two extra bytes following the payload data. If the TX FIFO runs empty before the complete packet has been transmitted, the radio will enter TXFIFO_UNDERFLOW state. The only way to exit this state is by issuing an SFTX strobe. Writing to the TX FIFO after it has underflowed will not restart TXmode. 5.8.3 Packet Handling in Firmware When implementing a packet oriented radio protocol in firmware, the MCU needs to know when a packet has been transmitted. Additionally, for packets longer than 64 bytes, the TX FIFO needs to be refilled while in TX. This means that the MCU needs to know the number of bytes that can be written to the TX FIFO.Therearetwopossiblesolutionstogetthenecessarystatusinformation: a.InterruptDrivenSolution The GDO pins can be used to give an interrupt when a sync word has been transmitted or when a complete packet has been transmitted by setting IOCFGx.GDOx_CFG=0x06. In addition, there are two configurations for the IOCFGx.GDOx_CFG register that can be used as an interrupt source to provide information on how many bytes that are in the TX FIFO (IOCFGx.GDOx_CFG=0x02 and IOCFGx.GDOx_CFG=0x03).SeeTable5-12 formoreinformation. b.SPIPolling The PKTSTATUS register can be polled at a given rate to get information about the current GDO2 and GDO0 values respectively. The TXBYTES registers can be polled at a given rate to get information about the number of bytes in the and TX FIFO. Alternatively, the number of bytes in the TX FIFO can be read from the chip status byte returned on the MISO line each time a header byte, data byte, or command strobeissentontheSPIbus. It is recommended to employ an interrupt driven solution due to a small, but finite, probability that a single read from registers PKTSTATUS and TXBYTES is being corrupt. The same is the case when reading the chipstatusbyte(seeSection5.5.3andtheCC115LErrataNotesSWRZ036). Copyright©2011–2014,TexasInstrumentsIncorporated DetailedDescription 25 SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L SWRS105B–MAY2011–REVISEDJUNE2014 www.ti.com 5.9 Modulation Formats CC115L supports amplitude, frequency, and phase shift modulation formats. The desired modulation formatissetintheMDMCFG2.MOD_FORMATregister. Optionally, the data stream can be Manchester coded by the modulator by setting MDMCFG2.MANCHESTER_EN=1. NOTE Manchesterencodingisnotsupportedatthesametimeasusing4-FSKmodulation. 5.9.1 Frequency Shift Keying CC115L supports 2-(G)FSK and 4-FSK modulation. When selecting 4-FSK, the preamble and sync word issentusing2-FSK(seeFigure5-8). The frequency deviation is programmed with the DEVIATION_M and DEVIATION_E values in the DEVIATN register.Thevaluehasanexponent/mantissaform,andtheresultantdeviationisgivenby: ƒ ƒ = XOSC ×(8+DEVIATION_M)×2DEVIATION_E dev 217 (4) ThesymbolencodingisshowninTable5-4. Table5-4.SymbolEncodingfor2-FSK/GFSKand4-FSKModulation Format Symbol Coding 0 –Deviation 2-FSK/GFSK 1 +Deviation 01 –Deviation 00 –1/3×Deviation 4-FSK 10 +1/3×Deviation 11 +Deviation 1/Baud Rate 1/Baud Rate 1/Baud Rate +1 +1/3 -1/3 -1 1 0 1 0 1 0 1 0 1 1 0 1 0 0 1 1 00 01 01 11 10 00 11 01 Preamble Sync Data 0xAA 0xD3 0x17 0x8D Figure5-8.DataSentOvertheAir(MDMCFG2.MOD_FORMAT=100) 5.9.2 Amplitude Modulation The amplitude modulation supported by CC115L is On-Off Keying (OOK). OOK modulation simply turns thePAonorofftomodulateonesandzerosrespectively. TheDEVIATNregistersettinghasnoeffectwhenusingOOK. 26 DetailedDescription Copyright©2011–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L www.ti.com SWRS105B–MAY2011–REVISEDJUNE2014 5.10 Radio Control SIDLE SLEEP CAL_COMPLETE SPWD 0 MANCAL IDLE CSn = 0 3,4,5 1 SXOFF SCAL CSn = 0 STX | SFSTXON XOFF 2 FS_WAKEUP 6,7 FS_AUTOCAL= 01 and STX | SFSTXON FS_AUTOCAL= 00 | 10 | 11 and CALIBRATE STX | SFSTXON 8 CAL_COMPLETE SETTLING 9,10 SFSTXON FSTXON 18 STX STX TXOFF_MODE = 01 TX TXOFF_MODE = 10 19,20 TXFIFO_UNDERFLOW TXOFF_MODE = 00 and FS_AUTOCAL= 10 | 11 TXOFF_MODE = 00 CALIBRATE TX_UNDERFLOW and 12 22 FS_AUTOCAL= 00 | 01 SFTX IDLE 1 Figure5-9.CompleteRadioControlStateDiagram CC115L has a built-in state machine that is used to switch between different operational states (modes). The change of state is done either by using command strobes or by internal events such as TX FIFO underflow. A simplified state diagram, together with typical usage and current consumption, is shown in Figure 5-2. The complete radio control state diagram is shown in Figure 5-9. The numbers refer to the state number readableintheMARCSTATEstatusregister.Thisregisterisprimarilyfortestpurposes. Copyright©2011–2014,TexasInstrumentsIncorporated DetailedDescription 27 SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L SWRS105B–MAY2011–REVISEDJUNE2014 www.ti.com 5.10.1 Power-On Start-Up Sequence When the power supply is turned on, the system must be reset. This is achieved by one of the two sequences described below, that is, automatic power-on reset (POR) or manual reset. After the automatic power-on reset or manual reset, it is also recommended to change the signal that is output on the GDO0 pin. The default setting is to output a clock signal with a frequency of CLK_XOSC/192. However, to optimize performance in TX, an alternative GDO setting from the settings found in Table 5-12 should be selected. 5.10.1.1 AutomaticPOR A power-on reset circuit is included in the CC115L. The minimum requirements stated in Section 4.10 must be followed for the power-on reset to function properly. The internal power-up sequence is completed when CHIP_RDYn goes low. CHIP_RDYn is observed on the SO pin after CSn is pulled low. SeeSection5.5.1formoredetailsonCHIP_RDYn. When the CC115L reset is completed, the chip will be in the IDLE state and the crystal oscillator will be running. If the chip has had sufficient time for the crystal oscillator to stabilize after the power-on-reset, the SO pin will go low immediately after taking CSn low. If CSn is taken low before reset is completed, the SO pin will first go high, indicating that the crystal oscillator is not stabilized, before going low as shown in Figure5-10. CSn SO XOSC Stable Figure5-10.Power-OnResetwithSRES 5.10.1.2 ManualReset The other global reset possibility on CC115L uses the SRES command strobe. By issuing this strobe, all internal registers and states are set to the default, IDLE state. The manual power-up sequence is as follows(seeFigure5-11): • SetSCLK=1andSI=0. • StrobeCSnlow/high. • HoldCSnlowandthenhighforatleast40 µsrelativetopullingCSnlow • PullCSnlowandwaitforSOtogolow(CHIP_RDYn). • IssuetheSRESstrobeontheSIline. • WhenSOgoeslowagain,resetiscompleteandthechipisintheIDLEstate. XOSCandvoltageregulatorswitchedon XOSC and voltage regulator switched on 40 us CSn SO XOSC Stable SI SRES Figure5-11.Power-OnResetwithSRES 28 DetailedDescription Copyright©2011–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L www.ti.com SWRS105B–MAY2011–REVISEDJUNE2014 NOTE The above reset procedure is only required just after the power supply is first turned on. If the user wants to reset the CC115L after this, it is only necessary to issue an SRES commandstrobe. 5.10.2 Crystal Control The crystal oscillator (XOSC) is either automatically controlled or always on, if MCSM0.XOSC_FORCE_ONisset. In the automatic mode, the XOSC will be turned off if the SXOFF or SPWD command strobes are issued; the state machine then goes to XOFF or SLEEP respectively. This can only be done from the IDLE state. The XOSC will be turned off when CSn is released (goes high). The XOSC will be automatically turned on again when CSn goes low. The state machine will then go to the IDLE state. The SO pin on the SPI interfacemustbepulledlowbeforetheSPIinterfaceisreadytobeusedasdescribedinSection5.5.1. IftheXOSCisforcedon,thecrystalwillalwaysstayonevenintheSLEEPstate. Crystal oscillator start-up time depends on crystal ESR and load capacitances. The electrical specification forthecrystaloscillatorcanbefoundinSection4.7. 5.10.3 Voltage Regulator Control The voltage regulator to the digital core is controlled by the radio controller. When the chip enters the SLEEPstatewhichisthestatewiththelowestcurrentconsumption,thevoltageregulatorisdisabled.This occurs after CSn is released when a SPWD command strobe has been sent on the SPI interface. The chip is then in the SLEEP state. Setting CSn low again will turn on the regulator and crystal oscillator and makethechipentertheIDLEstate. Copyright©2011–2014,TexasInstrumentsIncorporated DetailedDescription 29 SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L SWRS105B–MAY2011–REVISEDJUNE2014 www.ti.com 5.10.4 Transmit Mode (TX) TransmitmodeisactivateddirectlybytheMCUbyusingtheSTXcommandstrobe. The frequency synthesizer must be calibrated regularly. CC115L has one manual calibration option (using the SCAL strobe), and three automatic calibration options that are controlled by the MCSM0.FS_AUTOCALsetting: • CalibratewhengoingfromIDLEtoTX(orFSTXON) • CalibratewhengoingfromTXtoIDLEautomatically(notforcedinIDLEbyissuinganSIDLEstrobe) • CalibrateeveryfourthtimewhengoingfromTXtoIDLEautomatically(notforcedinIDLEbyissuingan SIDLEstrobe) If the radio goes from TX to IDLE by issuing an SIDLE strobe, calibration will not be performed. The calibrationtakesaconstantnumberofXOSCcycles;seeTable5-5fortimingdetailsregardingcalibration. When TX is active the chip will remain in the TX state until the current packet has been successfully transmitted. Then the state will change as indicated by the MCSM1.TXOFF_MODE setting. The possible destinationsare: • IDLE • FSTXON:FrequencysynthesizeronandreadyattheTXfrequency.ActivateTXwithSTX • TX:Startsendingpreamble TheSIDLEcommandstrobecanalwaysbeusedtoforcetheradiocontrollertogototheIDLEstate. 5.10.5 Timing 5.10.5.1 OverallStateTransitionTimes The main radio controller needs to wait in certain states in order to make sure that the internal analog/digital parts have settled down and are ready to operate in the new states. A number of factors are importantforthestatetransitiontimes: • Thecrystaloscillatorfrequency,f xosc • OOKusedornot • ThedatarateincaseswhereOOKisused • ThevalueoftheTEST0,TEST1,andFSCAL3registers Table5-5showstimingincrystalclockcyclesforkeystatetransitions. Note that the TX to IDLE transition time is a function of data rate (f ). When OOK is used (that is, baudrate FREND0.PA_POWER=001b), TX to IDLE will require 1/8×f baudrate longer times than the time stated in Table5-5. 30 DetailedDescription Copyright©2011–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L www.ti.com SWRS105B–MAY2011–REVISEDJUNE2014 Table5-5.OverallStateTransitionTimes[Examplefor26-MHzCrystalOscillator,250kBaudDataRate, andTEST0=0x0B(MaximumCalibrationTime)]. Description TransitionTime(FREND0.PA_POWER=0) TransitionTime[µs] IDLEtoTX/FSTXON,nocalibration 1954/f 75.2 xosc IDLEtoTX/FSTXON,withcalibration 1953/f +FScalibrationTime 799 xosc TXtoIDLE,nocalibration ~0.25/f ~1 baudrate TXtoIDLE,withcalibration ~0.25/f +FScalibrationTime 725 baudrate Manualcalibration 283/f +FScalibrationTime 735 xosc 5.10.5.2 FrequencySynthesizerCalibrationTime Table 5-6 summarizes the frequency synthesizer (FS) calibration times for possible settings of TEST0 and FSCAL3.CHP_CURR_CAL_EN. Setting FSCAL3.CHP_CURR_CAL_EN to 00b disables the charge pump calibration stage. TEST0 is set to the values recommended by SmartRF Studio software SWRC176. The possible values for TEST0 when operating with different frequency bands are 0x09 and 0x0B. SmartRF StudiosoftwarealwayssetsFSCAL3.CHP_CURR_CAL_ENto10b. Thecalibrationtimecanbereducedfrom712/724 µsto145/157 µs.SeeSection5.18.2formoredetails. Table5-6.FrequencySynthesizerCalibrationTimes(26-and27-MHzCrystal) TEST0 FSCAL3.CHP_CURR_CAL_EN FSCalibrationTimef =26 FSCalibrationTimef =27 xosc xosc MHz MHz 0x09 00b 3764/f =145µs 3764/f =139µs xosc xosc 0x09 10b 18506/f =712µs 18506/f =685µs xosc xosc 0x0B 00b 4073/f =157µs 4073/f =151µs xosc xosc 0x0B 10b 18815/f =724µs 18815/f =697µs xosc xosc Copyright©2011–2014,TexasInstrumentsIncorporated DetailedDescription 31 SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L SWRS105B–MAY2011–REVISEDJUNE2014 www.ti.com 5.11 TX FIFO The CC115L contains a 64-byte TX FIFO for data to be transmitted and the SPI interface is used to write to the TX FIFO (see Section 5.5.5 for more details). The FIFO controller will detect underflow in the TX FIFO. When writing to the TX FIFO it is the responsibility of the MCU to avoid TX FIFO overflow. A TX FIFO overflowwillresultinanerrorintheTXFIFOcontent. The chip status byte that is available on the SO pin while transferring the SPI header and contains the fill gradeoftheTXFIFOiftheaccessisawriteoperation.Section5.5.1 containsmoredetailsonthis. ThenumberofbytesintheTXFIFOcanbereadfromthestatusregistersTXBYTES.NUM_TXBYTES. The4-bitFIFOTHR.FIFO_THRsettingisusedtoprogramthresholdpointsintheTXFIFO. Table5-7liststhe16FIFO_THRsettingsandthecorrespondingthresholdsfortheTXFIFO. Table5-7.FIFO_THRSettingsandtheCorrespondingFIFOThresholds FIFO_THR BytesinTXFIFO 0(0000) 61 1(0001) 57 2(0010) 53 3(0011) 49 4(0100) 45 5(0101) 41 6(0110) 37 7(0111) 33 8(1000) 29 9(1001) 25 10(1010) 21 11(1011) 17 12(1100) 13 13(1101) 9 14(1110) 5 15(1111) 1 A signal will assert when the number of bytes in the TX FIFO is equal to or higher than the programmed threshold.ThissignalcanbeviewedontheGDOpins(seeTable5-12). Figure 5-12 shows the number of bytes in the TX FIFO when the threshold signal toggles in the case of FIFO_THR=13.Figure5-13showsthesignalontheGDOpinastheTXFIFOisfilledabovethethreshold, andthendrainedbelowinthecaseofFIFO_THR=13. 32 DetailedDescription Copyright©2011–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L www.ti.com SWRS105B–MAY2011–REVISEDJUNE2014 FIFO_THR=13 Underflow 8 bytes margin TX FIFO Figure5-12.ExampleofFIFOatThreshold NUM_TXBYTES 6 7 8 9 10 9 8 7 6 GDO Figure5-13.NumberofBytesinTXFIFOvs.theGDOSignal(GDOx_CFG=0x02andFIFO_THR=13) Copyright©2011–2014,TexasInstrumentsIncorporated DetailedDescription 33 SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L SWRS105B–MAY2011–REVISEDJUNE2014 www.ti.com 5.12 Frequency Programming The frequency programming in CC115L is designed to minimize the programming needed when changing frequency. To set up a system with channel numbers, the desired channel spacing is programmed with the MDMCFG0.CHANSPC_M and MDMCFG1.CHANSPC_E registers. The channel spacing registers are mantissa and exponent respectively. The base or start frequency is set by the 24 bit frequency word located in the FREQ2, FREQ1, and FREQ0 registers. This word will typically be set to the center of the lowestchannelfrequencythatistobeused. The desired channel number is programmed with the 8-bit channel number register, CHANNR.CHAN, whichismultipliedbythechanneloffset.Theresultantcarrierfrequencyisgivenby: ƒ = ƒXOSC ×(FREQ+CHAN×((256+CHANSPC_M)×2CHANSPC_2-2)) carrier 216 (5) With a 26 MHz crystal the maximum channel spacing is 405 kHz. To get that is, 1-MHz channel spacing, onesolutionistouse333kHzchannelspacingandselecteachthirdchannelinCHANNR.CHAN. The preferred IF frequency is programmed with the FSCTRL1.FREQ_IF register. The IF frequency is givenby: ƒ ƒ = XOSC ×FREQ_IF IF 210 (6) If any frequency programming register is altered when the frequency synthesizer is running, the synthesizer may give an undesired response. Hence, the frequency should only be updated when the radioisintheIDLEstate. 34 DetailedDescription Copyright©2011–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L www.ti.com SWRS105B–MAY2011–REVISEDJUNE2014 5.13 VCO TheVCOiscompletelyintegratedon-chip. 5.13.1 VCO and PLL Self-Calibration The VCO characteristics vary with temperature and supply voltage changes as well as the desired operating frequency. In order to ensure reliable operation, CC115L includes frequency synthesizer self- calibration circuitry. This calibration should be done regularly, and must be performed after turning on power and before using a new frequency (or channel). The number of XOSC cycles for completing the PLLcalibrationisgiveninTable5-5. The calibration can be initiated automatically or manually. The synthesizer can be automatically calibrated each time the synthesizer is turned on, or each time the synthesizer is turned off automatically. This is configured with the MCSM0.FS_AUTOCAL register setting. In manual mode, the calibration is initiated whentheSCALcommandstrobeisactivatedintheIDLEmode. NOTE The calibration values are maintained in SLEEP mode, so the calibration is still valid after waking up from SLEEP mode unless supply voltage or temperature has changed significantly. To check that the PLL is in lock, the user can program register IOCFGx.GDOx_CFG to 0x0A, and use the lock detector output available on the GDOx pin as an interrupt for the MCU (x = 0, 1, or 2). A positive transition on the GDOx pin means that the PLL is in lock. As an alternative the user can read register FSCAL1. The PLL is in lock if the register content is different from 0x3F. Refer also to the CC115L Errata NotesSWRZ037. For more robust operation, the source code could include a check so that the PLL is re-calibrated until PLLlockisachievedifthePLLdoesnotlockthefirsttime. 5.14 Voltage Regulators CC115L contains several on-chip linear voltage regulators that generate the supply voltages needed by low-voltage modules. These voltage regulators are invisible to the user, and can be viewed as integral parts of the various modules. The user must however make sure that the absolute maximum ratings and requiredpinvoltagesinTable3-1andTable5-1arenotexceeded. By setting the CSn pin low, the voltage regulator to the digital core turns on and the crystal oscillator starts. The SO pin on the SPI interface must go low before the first positive edge of SCLK (setup time is giveninTable5-1). If the chip is programmed to enter power-down mode (SPWD strobe issued), the power will be turned off afterCSngoeshigh.ThepowerandcrystaloscillatorwillbeturnedonagainwhenCSngoeslow. Thevoltageregulatorforthedigitalcorerequiresoneexternaldecouplingcapacitor. ThevoltageregulatoroutputshouldonlybeusedfordrivingtheCC115L. Copyright©2011–2014,TexasInstrumentsIncorporated DetailedDescription 35 SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L SWRS105B–MAY2011–REVISEDJUNE2014 www.ti.com 5.15 Output Power Programming The RF output power level from the device has two levels of programmability. The PATABLE register can hold two user selected output power settings and the FREND0.PA_POWER value selects the PATABLE entry to use (0 or 1). PATABLE must be programmed in burst mode if writing to other entries than PATABLE[0].SeeSection5.5.6 formoreprogrammingdetails. For OOK modulation, FREND0.PA_POWER should be 1 and the logic 0 and logic 1 power levels shall be programmed to index 0 and 1 respectively. For all other modulation formats, the desired output power shouldbeprogrammedtoindex0. Table 5-8 contains the recommended PATABLE settings for various output levels and frequency bands. DN013 SWRA168 gives the complete tables for the different frequency bands using multi-layer inductors. Using PA settings from 0x61 to 0x6F is not allowed. Table 5-11 contains output power and current consumptionfordefaultPATABLEsetting(0xC6).ThemeasurementsaredoneonSWRR045. NOTE All content of the PATABLE except for the first byte (index 0) is lost when entering the SLEEPstate. Table5-8.OptimumPATABLESettingsforVariousOutputPowerLevelsUsingWire-WoundInductorsin 868-and915-MHzFrequencyBands 868MHz 915MHz CurrentConsumption, CurrentConsumption, OutputPower[dBm] Setting Setting Typ.[mA] Typ.[mA] 12/11 0xC0 34.2 0xC0 33.4 10 0xC5 30.0 0xC3 30.7 7 0xCD 25.8 0xCC 25.7 5 0x86 19.9 0x84 20.2 0 0x50 16.8 0x8E 17.2 −6 0x37 16.4 0x38 17.0 −10 0x26 14.5 0x27 14.8 −15 0x1D 13.3 0x1E 13.3 −20 0x17 12.6 0x0E 12.5 −30 0x03 12.0 0x03 11.9 Table5-9.OutputPowerandCurrentConsumptionforDefaultPATABLESettingUsingWire-Wound Inductorsin868-and915-MHzFrequencyBands 868MHz 915MHz DefaultPowerSetting OutputPower[dBm] CurrentConsumption, OutputPower[dBm] CurrentConsumption, Typ.[mA] Typ.[mA] 0xC6 9.6 29.4 8.9 28.7 36 DetailedDescription Copyright©2011–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L www.ti.com SWRS105B–MAY2011–REVISEDJUNE2014 Table5-10.OptimumPATABLESettingsforVariousOutputPowerLevelsUsingMulti-layerInductorsin 868-and915-MHzFrequencyBands 868MHz 915MHz CurrentConsumption, CurrentConsumption, OutputPower[dBm] Setting Setting Typ.[mA] Typ.[mA] 10 0xC2 32.4 0xC0 31.8 7 0xCB 26.8 0xC7 26.9 5 0x81 21.0 0xCD 24.3 0 0x50 16.9 0x8E 16.7 −10 0x27 15.0 0x27 14.9 −15 0x1E 13.4 0x1E 13.4 −20 0x0F 12.7 0x0E 12.6 −30 0x03 12.1 0x03 12.0 Table5-11.OutputPowerandCurrentConsumptionforDefaultPATABLESettingUsingMulti-layer Inductorsin868-and915-MHzFrequencyBands 868MHz 915MHz DefaultPowerSetting CurrentConsumption, OutputPower[dBm] CurrentConsumption, OutputPower[dBm] Typ.[mA] Typ.[mA] 0xC6 8.5 29.5 7.2 27.4 Copyright©2011–2014,TexasInstrumentsIncorporated DetailedDescription 37 SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L SWRS105B–MAY2011–REVISEDJUNE2014 www.ti.com 5.16 General Purpose and Test Output Control Pins The three digital output pins GDO0, GDO1, and GDO2 are general control pins configured with IOCFG0.GDO0_CFG, IOCFG1.GDO1_CFG, and IOCFG2.GDO2_CFG respectively. Table 5-12 shows the different signals that can be monitored on the GDO pins. These signals can be used as inputs to the MCU. GDO1 is the same pin as the SO pin on the SPI interface, thus the output programmed on this pin will only be valid when CSn is high. The default value for GDO1 is 3-stated which is useful when the SPI interfaceissharedwithotherdevices. The default value for GDO0 is a 135–141 kHz clock output (XOSC frequency divided by 192). Since the XOSC is turned on at power-on-reset, this can be used to clock the MCU in systems with only one crystal. WhentheMCUisupandrunning,itcanchangetheclockfrequencybywritingtoIOCFG0.GDO0_CFG. If the IOCFGx.GDOx_CFG setting is less than 0x20 and IOCFGx_GDOx_INV is 0 (1), the GDO0 and GDO2 pins will be hardwired to 0 (1), and the GDO1 pin will be hardwired to 1 (0) in the SLEEP state. ThesesignalswillbehardwireduntiltheCHIP_RDYnsignalgoeslow. If the IOCFGx.GDOx_CFG setting is 0x20 or higher, the GDO pins will work as programmed also in SLEEPstate.Asanexample,GDO1ishighimpedanceinallstatesifIOCFG1.GDO1_CFG=0x2E. Table5-12.GDOxSignalSelection(x=0,1,or2) GDOx_CFG Description [5:0] 0(0x00)–1 Reserved–usedfortest. (0x01) 2(0x02) AssociatedtotheTXFIFO:AssertswhentheTXFIFOisfilledatorabovetheTXFIFOthreshold.DeassertswhentheTX FIFOisbelowthesamethreshold. 3(0x03) AssociatedtotheTXFIFO:AssertswhenTXFIFOisfull.DeassertswhentheTXFIFOisdrainedbelowtheTXFIFO threshold. 4(0x04) Reserved–usedfortest. 5(0x05) AssertswhentheTXFIFOhasunderflowed.DeassertswhentheFIFOisflushed. 6(0x06) Assertswhensyncwordhasbeensent,andde-assertsattheendofthepacket.Thepinwillde-assertiftheTXFIFO underflows. 7(0x07)–9 Reserved-usedfortest. (0x09) 10(0x0A) Lockdetectoroutput.ThePLLisinlockifthelockdetectoroutputhasapositivetransitionorisconstantlylogichigh.To checkforPLLlockthelockdetectoroutputshouldbeusedasaninterruptfortheMCU. 11(0x0B) SerialClock.Synchronoustothedatainsynchronousserialmode.DataissampledbyCC115L115L115Lontherisingedge oftheserialclockwhenGDOx_INV=0. 12(0x0C) SerialSynchronousDataOutput.Usedforsynchronousserialmode. 13(0x0D) SerialDataOutput.Usedforasynchronousserialmode. 14(0x0E)– Reserved-usedfortest. 26(0x1A) 27(0x1B) PA_PD.Note:PA_PDwillhavethesamesignallevelinSLEEPandTXstates.TocontrolanexternalPAinapplications wheretheSLEEPstateisuseditisrecommendedtouseGDOx_CFGx=0x2Finstead. 28(0x1D)– Reserved-usedfortest. 40(0x28) 41(0x29) CHIP_RDYn 42(0x2A) Reserved-usedfortest. 43(0x2B) XOSC_STABLE 44(0x2C)- Reserved-usedfortest. 45(0x2D) 46(0x2E) Highimpedance(3-state) 47(0x2F) HWto0(HW1achievedbysettingGDOx_INV=1).CanbeusedtocontrolanexternalPA. 38 DetailedDescription Copyright©2011–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L www.ti.com SWRS105B–MAY2011–REVISEDJUNE2014 Table5-12.GDOxSignalSelection(x=0,1,or2)(continued) GDOx_CFG Description [5:0] 48(0x30) CLK_XOSC/1 Note:Thereare3GDOpins,butonlyone CLK_XOSC/ncanbeselectedasanoutputatany 49(0x31) CLK_XOSC/1.5 time.IfCLK_XOSC/nistobemonitoredononeof 50(0x32) CLK_XOSC/2 theGDOpins,theothertwoGDOpinsmustbe configuredtovalueslessthan0x30.TheGDO0 51(0x33) CLK_XOSC/3 defaultvalueisCLK_XOSC/192. 52(0x34) CLK_XOSC/4 TooptimizeRFperformance,thesesignalsshould 53(0x35) CLK_XOSC/6 notbeusedwhiletheradioisinTXmode. 54(0x36) CLK_XOSC/8 55(0x37) CLK_XOSC/12 56(0x38) CLK_XOSC/16 57(0x39) CLK_XOSC/24 58(0x3A) CLK_XOSC/32 59(0x3B) CLK_XOSC/48 60(0x3C) CLK_XOSC/64 61(0x3D) CLK_XOSC/96 62(0x3E) CLK_XOSC/128 63(0x3F) CLK_XOSC/192 Copyright©2011–2014,TexasInstrumentsIncorporated DetailedDescription 39 SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L SWRS105B–MAY2011–REVISEDJUNE2014 www.ti.com 5.17 Asynchronous and Synchronous Serial Operation Several features and modes of operation have been included in the CC115L to provide backward compatibility with previous Chipcon products and other existing RF communication systems. For new systems, it is recommended to use the built-in packet handling features, as they can give more robust communication,significantlyoffloadthemicrocontroller,andsimplifysoftwaredevelopment. 5.17.1 Asynchronous Serial Operation Asynchronous transfer is included in the CC115L for backward compatibility with systems that are already usingtheasynchronousdatatransfer. When asynchronous transfer is enabled, all packet handling support is disabled and it is not possible to useManchesterencoding. Asynchronous serial mode is enabled by setting PKTCTRL0.PKT_FORMAT to 3. Strobing STX will configure the GDO0 pin as data input (TX data) regardless of the content of the IOCFG0 register. Data output can be on GDO0, GDO1, or GDO2. This is set by the IOCFG0.GDO0_CFG, IOCFG1.GDO1_CFG andIOCFG2.GDO2_CFGfields. The CC115L modulator samples the level of the asynchronous input 8 times faster than the programmed data rate. The timing requirement for the asynchronous stream is that the error in the bit period must be lessthanoneeighthoftheprogrammeddatarate. 5.17.2 Synchronous Serial Operation Setting PKTCTRL0.PKT_FORMAT to 1 enables synchronous serial mode. When using this mode, sync detection should be disabled together with CRC calculation ( MDMCFG2.SYNC_MODE=000 and PKTCTRL0.CRC_EN=0). Infinite packet length mode should be used ( PKTCTRL0.LENGTH_CONFIG=10b). In synchronous serial mode, data is transferred on a two-wire serial interface. The CC115L provides a clock that is used to set up new data on the data input line or sample data on the data output line. Data input (TX data) is on the GDO0 pin. This pin will automatically be configured as an input when TX is active.TheTXlatencyis8bits. The MCU must handle preamble and sync word insertion/detection in software, together with CRC calculationandinsertion. 40 DetailedDescription Copyright©2011–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L www.ti.com SWRS105B–MAY2011–REVISEDJUNE2014 5.18 System Considerations and Guidelines 5.18.1 SRD Regulations International regulations and national laws regulate the use of radio receivers and transmitters. Short Range Devices (SRDs) for license free operation below 1 GHz are usually operated in the 315 MHz, 433 MHz, 868 MHz, or 915 MHz frequency bands. The CC115L is specifically designed for such use with its 300–348 MHz, 387–464 MHz, and 779–928 MHz operating ranges. The most important regulations when using the CC115L in the 315 MHz, 433 MHz, 868 MHz, or 915 MHz frequency bands are EN 300 220 V2.3.1(Europe)andFCCCFR47Part15(USA). For compliance with modulation bandwidth requirements under EN 300 220 V2.3.1 in the 863 to 870 MHz frequency range it is recommended to use a 26-MHz crystal for frequencies below 869 MHz and a 27 MHzcrystalforfrequenciesabove869MHz. Compliance with regulations is dependent on the complete system performance. It is the customer's responsibilitytoensurethatthesystemcomplieswithregulations. 5.18.2 Calibration in Multi-Channel Systems CC115L is highly suited for multi-channel systems due to its agile frequency synthesizer and effective communicationinterface. Charge pump current, VCO current, and VCO capacitance array calibration data is required for each frequency when implementing a multi-channel system. There are 3 ways of obtaining the calibration data fromthechip: 1. Calibrationforeveryfrequencychange.ThePLLcalibrationtimeis712/724 μs(26MHzcrystaland TEST0 =0x09/0B,seeTable5-6).Theblankingintervalbetweeneachfrequencyhopisthen787/799 µs. 2. PerformallnecessarycalibrationatstartupandstoretheresultingFSCAL3,FSCAL2,andFSCAL1 registervaluesinMCUmemory.TheVCOcapacitancecalibrationFSCAL1registervaluemustbe foundforeachRFfrequencytobeused.TheVCOcurrentcalibrationvalueandthechargepump currentcalibrationvalueavailableinFSCAL2andFSCAL3respectivelyarenotdependentontheRF frequency,sothesamevaluecanthereforebeusedforallRFfrequenciesforthesetworegisters. Betweeneachfrequencyhop,thecalibrationprocesscanthenbereplacedbywritingtheFSCAL3, FSCAL2andFSCAL1registervaluesthatcorrespondstothenextRFfrequency.ThePLLturnontime isapproximately75µs(seeTable5-5).Theblankingintervalbetweeneachfrequencyhopisthen approximately75µs. 3. Runcalibrationonasinglefrequencyatstartup.Nextwrite0toFSCAL3[5:4]todisablethecharge pumpcalibration.AfterwritingtoFSCAL3[5:4],strobeSTXwithMCSM0.FS_AUTOCAL=1foreach newfrequencyhop.Thatis,VCOcurrentandVCOcapacitancecalibrationisdone,butnotcharge pumpcurrentcalibration.Whenchargepumpcurrentcalibrationisdisabledthecalibrationtimeis reducedfrom712/724µsto145/157 µs(26MHzcrystalandTEST0=0x09/0B,seeTable5-6).The blankingintervalbetweeneachfrequencyhopisthen220/232µs. There is a trade off between blanking time and memory space needed for storing calibration data in non- volatile memory. Solution 2) above gives the shortest blanking interval, but requires more memory space to store calibration values. This solution also requires that the supply voltage and temperature do not vary muchinordertohavearobustsolution.Solution3)gives567 µssmallerblankingintervalthansolution1). The recommended settings for TEST0.VCO_SEL_CAL_EN change with frequency. This means that one should always use SmartRF Studio to get the correct settings for a specific frequency before doing a calibration,regardlessofwhichcalibrationmethodisbeingused. NOTE The content in the TEST0 register is not retained in SLEEP state, thus it is necessary to re- writethisregisterwhenreturningfromtheSLEEPstate. Copyright©2011–2014,TexasInstrumentsIncorporated DetailedDescription 41 SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L SWRS105B–MAY2011–REVISEDJUNE2014 www.ti.com 5.18.3 Wideband Modulation when not Using Spread Spectrum Digital modulation systems under FCC Section 15.247 include 2-FSK, GFSK, and 4-FSK modulation. A maximum peak output power of 1 W (+30 dBm) is allowed if the 6 dB bandwidth of the modulated signal exceeds 500 kHz. In addition, the peak power spectral density conducted to the antenna shall not be greaterthan+8dBminany3kHzband. Operating at high data rates and frequency separation, the CC115L is suited for systems targeting compliance with digital modulation system as defined by FCC Section 15.247. An external power amplifier such as CC1190 SWRS089 is needed to increase the output above +11 dBm. Refer to DN006 SWRA123 forfurtherdetailsconcerningwidebandmodulationandCC115L. 5.18.4 Data Burst Transmissions The high maximum data rate of CC115L opens up for burst transmissions. A low average data rate link (e.g. 10 kBaud) can be realized by using a higher over-the-air data rate. Buffering the data and transmitting in bursts at high data rate (e.g. 500 kBaud) will reduce the time in TX mode, and hence also reduce the average current consumption significantly. Reducing the time in TX mode will reduce the likelihoodofcollisionswithothersystemsinthesamefrequencyrange. 5.18.5 Continuous Transmissions In data streaming applications, the CC115L opens up for continuous transmissions at 500 kBaud effective data rate. As the modulation is done with a closed loop PLL, there is no limitation in the length of a transmission (open loop modulation used in some radios often prevents this kind of continuous data streamingandreducestheeffectivedatarate). 5.18.6 Increasing Output Power The PA portion of the CC1190 SWRS089 can be used together with CC115L in applications where increasedoutputpowerisneeded. 42 DetailedDescription Copyright©2011–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L www.ti.com SWRS105B–MAY2011–REVISEDJUNE2014 5.19 Configuration Registers The configuration of CC115L is done by programming 8-bit registers. The optimum configuration data based on selected system parameters are most easily found by using the SmartRF Studio software SWRC176. Complete descriptions of the registers are given in the following tables. After chip reset, all the registers have default values as shown in the tables. The optimum register setting might differ from the default value. After a reset, all registers that shall be different from the default value therefore needs to be programmedthroughtheSPIinterface. There are 9 command strobe registers, listed in Table 5-13. Accessing these registers will initiate the change of an internal state or mode. There are 34 normal 8-bit configuration registers listed in Table 5-14 and SmartRF Studio SWRC176 will provide recommended settings for these registers (Addresses marked as “Not Used” can be part of a burst access and one can write a dummy value to them. Addresses markedas“Reserved”mustbeconfiguredaccordingtoSmartRFStudioSWRC176). There are also 5 status registers that are listed in Table 5-15. These registers, which are read-only, containinformationaboutthestatusofCC115L. The TX FIFO is accessed through one 8-bit register. During the header byte transfer and while writing data to a register or the TX FIFO, a status byte is returned on the SO line. This status byte is described in Table5-2. Table 5-16 summarizes the SPI address space. The address to use is given by adding the base address to the left and the burst and read/write bits on the top. Note that the burst bit has different meaning for baseaddressesaboveandbelow0x2F. Table5-13.CommandStrobes Address StrobeName Description 0x30 SRES Resetchip. Enableandcalibratefrequencysynthesizer 0x31 SFSTXON (ifMCSM0.FS_AUTOCAL=1). 0x32 SXOFF Turnoffcrystaloscillator. Calibratefrequencysynthesizerandturnit off.SCALcanbestrobedfromIDLEmode 0x33 SCAL withoutsettingmanualcalibrationmode( MCSM0.FS_AUTOCAL=0) 0x34 Reserved InIDLEstate:EnableTX.Performcalibration 0x35 STX firstifMCSM0.FS_AUTOCAL=1. 0x36 SIDLE EnterIDLEstate 0x37-0x38 Reserved EnterpowerdownmodewhenCSngoes 0x39 SPWD high. 0x3A Reserved FlushtheTXFIFObuffer.OnlyissueSFTX 0x3B SFTX inIDLEorTXFIFO_UNDERFLOWstates. 0x3C Reserved Nooperation.Maybeusedtogetaccessto 0x3D SNOP thechipstatusbyte. Copyright©2011–2014,TexasInstrumentsIncorporated DetailedDescription 43 SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L SWRS105B–MAY2011–REVISEDJUNE2014 www.ti.com Table5-14.ConfigurationRegistersOverview Address Register Description PreservedinSLEEP DetailsonPageNumber State GDO2outputpin 0x00 IOCFG2 Yes Table5-17 configuration GDO1outputpin 0x01 IOCFG1 Yes Table5-18 configuration GDO0outputpin 0x02 IOCFG0 Yes Table5-19 configuration 0x03 FIFOTHR TXFIFOthresholds Yes Table5-20 0x04 SYNC1 Syncword,highbyte Yes Table5-21 0x05 SYNC0 Syncword,lowbyte Yes Table5-22 0x06 PKTLEN Packetlength Yes Table5-23 0x07 Notused 0x08 PKTCTRL0 Packetautomationcontrol Yes Table5-24 0x09 Notused 0x0A CHANNR Channelnumber Yes Table5-25 0x0B Notused Frequencysynthesizer 0x0C FSCTRL0 Yes Table5-26 control Frequencycontrolword, 0x0D FREQ2 Yes Table5-27 highbyte Frequencycontrolword, 0x0E FREQ1 Yes Table5-28 middlebyte Frequencycontrolword, 0x0F FREQ0 Yes Table5-29 lowbyte 0x10 MDMCFG4 Modemconfiguration Yes Table5-30 0x11 MDMCFG3 Modemconfiguration Yes Table5-31 0x12 MDMCFG2 Modemconfiguration Yes Table5-32 0x13 MDMCFG1 Modemconfiguration Yes Table5-33 0x14 MDMCFG0 Modemconfiguration Yes Table5-34 0x15 DEVIATN Modemdeviationsetting Yes Table5-35 0x16 Notused MainRadioControlState 0x17 MCSM1 Yes Table5-36 Machineconfiguration MainRadioControlState 0x18 MCSM0 Yes Table5-37 Machineconfiguration 0x19-0x1F NotUsed 0x20 RESERVED Yes Table5-38 0x21 NotUsed FrontendTX 0x22 FREND0 Yes Table5-39 configuration Frequencysynthesizer 0x23 FSCAL3 Yes Table5-40 calibration Frequencysynthesizer 0x24 FSCAL2 Yes Table5-41 calibration Frequencysynthesizer 0x25 FSCAL1 Yes Table5-42 calibration Frequencysynthesizer 0x26 FSCAL0 Yes Table5-43 calibration 0x27-0x28 NotUsed 0x29-0x2B RESERVED No Table5-44 0x2C TEST2 Varioustestsettings No Table5-47 0x2D TEST1 Varioustestsettings No Table5-48 44 DetailedDescription Copyright©2011–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L www.ti.com SWRS105B–MAY2011–REVISEDJUNE2014 Table5-14.ConfigurationRegistersOverview(continued) Address Register Description PreservedinSLEEP DetailsonPageNumber State 0x2E TEST0 Varioustestsettings No Table5-49 Table5-15.StatusRegistersOverview Address Register Description Detailsonpagenumber 0x30(0xF0) PARTNUM PartnumberforCC115L Table5-50 0x31(0xF1) VERSION Currentversionnumber Table5-51 0x32–0x34(0xF2–0xF4) Reserved 0x35(0xF5) MARCSTATE Controlstatemachinestate Table5-52 0x36-0x37(0xF6–0xF7) Reserved 0x38(0xF8) PKTSTATUS CurrentGDOxstatusandpacketstatus Table5-53 0x39(0xF9) Reserved 0x3A(0xFA) TXBYTES UnderflowandnumberofbytesintheTX Table5-54 FIFO 0x3B-0x3D(0xFB-0xFD) Reserved Copyright©2011–2014,TexasInstrumentsIncorporated DetailedDescription 45 SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L SWRS105B–MAY2011–REVISEDJUNE2014 www.ti.com Table5-16.SPIAddressSpace Write Read SingleByte Burst SingleByte Burst +0x00 +0x40 +0x80 +0xC0 0x00 IOCFG2 0x01 IOCFG1 0x02 IOCFG0 0x03 FIFOTHR 0x04 SYNC1 0x05 SYNC0 0x06 PKTLEN 0x07 NotUsed 0x08 PKTCTRL0 0x09 NotUsed 0x0A CHANNR 0x0B NotUsed 0x0C FSCTRL0 0x0D FREQ2 0x0E FREQ1 0x0F FREQ0 0x10 MDMCFG4 0x11 MDMCFG3 0x12 MDMCFG2 ble 0x13 MDMCFG1 ossi p 0x14 MDMCFG0 ess 0x15 DEVIATN acc 0x16 NotUsed urst b 0x17 MCSM1 ers, 0x18 MCSM0 gist 0x19 NotUsed re n 0x1A NotUsed atio 0x1B NotUsed gur nfi 0x1C NotUsed co W 0x1D NotUsed R/ 0x1E NotUsed 0x1F NotUsed 0x20 NotUsed 0x21 NotUsed 0x22 FREND0 0x23 FSCAL3 0x24 FSCAL2 0x25 FSCAL1 0x26 FSCAL0 0x27 NotUsed 0x28 NotUsed 0x29 RESERVED 0x2A RESERVED 0x2B RESERVED 0x2C TEST2 0x2D TEST1 0x2E TEST0 0x2F NotUsed 46 DetailedDescription Copyright©2011–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L www.ti.com SWRS105B–MAY2011–REVISEDJUNE2014 Table5-16.SPIAddressSpace(continued) Write Read SingleByte Burst SingleByte Burst +0x00 +0x40 +0x80 +0xC0 0x30 SRES SRES PARTNUM ers 0x31 SFSTXON SFSTXON VERSION gist e 0x32 SXOFF SXOFF Reserved r e 0x33 SCAL SCAL Reserved byt 0x34 NotUsed Reserved Reserved multi 0x35 STX STX MARCSTATE nd a 0x36 SIDLE SIDLE Reserved nly) o 0x37 Reserved Reserved Reserved d a e 0x38 Reserved Reserved PKTSTATUS (r 0x39 SPWD SPWD Reserved ers 0x3A Reserved Reserved TXBYTES egist r 0x3B SFTX SFTX Reserved us at 0x3C Reserved Reserved Reserved St 0x3D SNOP SNOP Reserved bes, o 0x3E PATABLE PATABLE PATABLE PATABLE Str d 0x3F TXFIFO TXFIFO Reserved Reserved an m m o C 5.19.1 Configuration Register Details - Registers with preserved values in SLEEP state Table5-17.0x00:IOCFG2-GDO2OutputPinConfiguration Bit FieldName Reset R/W Description 7 R0 Notused 6 GDO2_INV 0 R/W Invertoutput,thatis,selectactivelow(1)/high(0) 5:0 GDO2_CFG[5:0] 41(101001) R/W DefaultisCHP_RDYn(seeTable5-12). Table5-18.0x01:IOCFG1-GDO1OutputPinConfiguration Bit FieldName Reset R/W Description Sethigh(1)orlow(0)outputdrivestrengthontheGDO 7 GDO_DS 0 R/W pins. 6 GDO1_INV 0 R/W Invertoutput,thatis,selectactivelow(1)/high(0) 5:0 GDO1_CFG[5:0] 46(101110) R/W Defaultis3-state(seeTable5-12). Table5-19.0x02:IOCFG0-GDO0OutputPinConfiguration Bit FieldName Reset R/W Description 7 0 R/W UsesettingfromSmartRFStudio 6 GDO0_INV 0 R/W Invertoutput,thatis,selectactivelow(1)/high(0) DefaultisCLK_XOSC/192(seeTable5-12). 5:0 GDO0_CFG[5:0] 63(0x3F) R/W Itisrecommendedtodisabletheclockoutputin initialization,inordertooptimizeRFperformance. Copyright©2011–2014,TexasInstrumentsIncorporated DetailedDescription 47 SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L SWRS105B–MAY2011–REVISEDJUNE2014 www.ti.com Table5-20.0x03:FIFOTHR-TXFIFOThresholds Bit FieldName Reset R/W Description 7:4 0 R/W UsesettingfromSmartRFStudio SetthethresholdfortheTXFIFO.Thethresholdis exceededwhenthenumberofbytesintheTXFIFOis equaltoorhigherthanthethresholdvalue. Setting BytesinTXFIFO 0(0000) 61 1(0001) 57 2(0010) 53 3(0011) 49 4(0100) 45 5(0101) 41 3:0 FIFO_THR[3:0] 7(0111) R/W 6(0110) 37 7(0111) 33 8(1000) 29 9(1001) 25 10(1010) 21 11(1011) 17 12(1100) 13 13(1101) 9 14(1110) 5 15(1111) 1 Table5-21.0x04:SYNC1-SyncWord,HighByte Bit FieldName Reset R/W Description 7:0 SYNC[15:8] 211(0xD3) R/W 8MSBof16-bitsyncword Table5-22.0x05:SYNC0-SyncWord,LowByte Bit FieldName Reset R/W Description 7:0 SYNC[7:0] 145(0x91) R/W 8LSBof16-bitsyncword Table5-23.0x06:PKTLEN-PacketLength Bit FieldName Reset R/W Description Indicatesthepacketlengthwhenfixedpacketlengthmode 7:0 PACKET_LENGTH 255(0xFF) R/W isenabled.Thisvaluemustbedifferentfrom0. Table5-24.0x08:PKTCTRL0-PacketAutomationControl Bit FieldName Reset R/W Description 7 R0 Notused 6 1 R/W UsesettingfromSmartRFStudio 48 DetailedDescription Copyright©2011–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L www.ti.com SWRS105B–MAY2011–REVISEDJUNE2014 Table5-24.0x08:PKTCTRL0-PacketAutomationControl(continued) Bit FieldName Reset R/W Description FormatofTXdata Setting Packetformat 0(00) Normalmode,useTXFIFO Synchronousserialmode,Datainon 5:4 PKT_FORMAT[1:0] 0(00) R/W 1(01) GDO0 RandomTXmode;sendsrandomdata 2(10) usingPN9generator.Usedfortest. Asynchronousserialmode,Datainon 3(11) GDO0 3 0 R0 Notused 1:CRCcalculationenabled 2 CRC_EN 1 R/W 0:CRCcalculationdisabled 1:0 LENGTH_CONFIG[1:0] 1(01) R/W Configurethepacketlength Setting Packetlengthconfiguration 0(00) Fixedpacketlengthmode.Length configuredinPKTLENregister 1(01) Variablepacketlengthmode.Packet lengthconfiguredbythefirstbytewritten totheTXFIFO 2(10) Infinitepacketlengthmode 3(11) Reserved Table5-25.0x0A:CHANNR-ChannelNumber Bit FieldName Reset R/W Description The8-bitunsignedchannelnumber,whichismultipliedby 7:0 CHAN[7:0] 0(0x00) R/W thechannelspacingsettingandaddedtothebase frequency. Table5-26.0x0C:FSCTRL0-FrequencySynthesizerControl Bit FieldName Reset R/W Description Frequencyoffsetaddedtothebasefrequencybeforebeing usedbythefrequencysynthesizer.(2s-complement). 7:0 FREQOFF[7:0] 0(0x00) R/W ResolutionisFXTAL/214(1.59kHz-1.65kHz);rangeis±202 kHzto±210kHz,dependentofXTALfrequency. Table5-27.0x0D:FREQ2-FrequencyControlWord,HighByte Bit FieldName Reset R/W Description FREQ[23:22]isalways0(theFREQ2registerislessthan 7:6 FREQ[23:22] 0(00) R 36with26-27MHzcrystal) FREQ[23:0]isthebasefrequencyforthefrequency synthesizerinincrementsoffXOSC/216. 5:0 FREQ[21:16] 30(011110) R/W ƒ ƒ = XOSC ×FREQ[23:0] carrier 216 Table5-28.0x0E:FREQ1-FrequencyControlWord,MiddleByte Bit FieldName Reset R/W Description 7:0 FREQ[15:8] 196(0xC4) R/W SeeTable5-27. Copyright©2011–2014,TexasInstrumentsIncorporated DetailedDescription 49 SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L SWRS105B–MAY2011–REVISEDJUNE2014 www.ti.com Table5-29.0x0F:FREQ0-FrequencyControlWord,LowByte Bit FieldName Reset R/W Description 7:0 FREQ[7:0] 236(0xEC) R/W SeeTable5-27. Table5-30.0x10:MDMCFG4-ModemConfiguration Bit FieldName Reset R/W Description 7:4 8(1000) R/W UsesettingfromSmartRFStudioSWRC176 3:0 DRATE_E[3:0] 12(1100) R/W Theexponentoftheuserspecifiedsymbolrate Table5-31.0x11:MDMCFG3-ModemConfiguration Bit FieldName Reset R/W Description Themantissaoftheuserspecifiedsymbolrate.Thesymbol rateisconfiguredusinganunsigned,floating-pointnumber with9-bitmantissaand4-bitexponent.The9thbitisa hidden'1'.Theresultingdatarateis: (256+DRATE_M)×2DRATE_E 7:0 DRATE_M[7:0] 34(0x22) R/W R = ׃ DATA 228 XOSC Thedefaultvaluesgiveadatarateof115.051kBaud (closestsettingto115.2kBaud),assuminga26.0MHz crystal. 50 DetailedDescription Copyright©2011–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L www.ti.com SWRS105B–MAY2011–REVISEDJUNE2014 Table5-32.0x12:MDMCFG2-ModemConfiguration Bit FieldName Reset R/W Description 7 0 R/W UsesettingfromSmartRFStudioSWRC176 Themodulationformatoftheradiosignal Setting Modulationformat 0(000) 2-FSK 1(001) GFSK 2(010) Reserved 3(011) OOK 6:4 MOD_FORMAT[2:0] 0(000) R/W 4(100) 4-FSK 5(101) Reserved 6(110) Reserved 7(111) Reserved 4-FSKmodulationcannotbeusedtogetherwithManchester encoding EnablesManchesterencoding/decoding. 0=Disable 3 MANCHESTER_EN 0 R/W 1=Enable Manchesterencodingcannotbeusedwhenusing asynchronousserialmodeor4-FSKmodulation Numberofsyncbitstransmitted Setting Sync-wordqualifiermode 0(000) Nopreamble/sync 1(001) 16-bitssyncword 2:0 SYNC_MODE[2:0] 2(010) R/W 2(010) Reserved 3(011) 32-bitssyncword 4(100)–7 Reserved (111) Table5-33.0x13:MDMCFG1-ModemConfiguration Bit FieldName Reset R/W Description 7 0 R/W UsesettingfromSmartRFStudioSWRC176 Setstheminimumnumberofpreamblebytestobetransmitted Setting Numberofpreamblebytes 0(000) 2 1(001) 3 2(010) 4 6:4 NUM_PREAMBLE[2:0] 2(010) R/W 3(011) 6 4(100) 8 5(101) 12 6(110) 16 7(111) 24 3:2 R0 Notused 1:0 CHANSPC_E[1:0] 2(10) R/W 2bitexponentofchannelspacing Copyright©2011–2014,TexasInstrumentsIncorporated DetailedDescription 51 SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L SWRS105B–MAY2011–REVISEDJUNE2014 www.ti.com Table5-34.0x14:MDMCFG0-ModemConfiguration Bit FieldName Reset R/W Description 8-bitmantissaofchannelspacing.Thechannelspacingis multipliedbythechannelnumberCHANandaddedtothe basefrequency.Itisunsignedandhastheformat: ƒ 7:0 CHANSPC_M[7:0] 248(0xF8) R/W DƒCHANNEL = X2O18SC ×(256+CHANSPC_M)×2CHANSPC_E Thedefaultvaluesgive199.951kHzchannelspacing(the closestsettingto200kHz),assuming26.0MHzcrystal frequency. Table5-35.0x15:DEVIATN-ModemDeviationSetting Bit FieldName Reset R/W Description 7 R0 Notused. 6:4 DEVIATION_E[2:0] 4(100) R/W Deviationexponent. 3 R0 Notused. Specifiesthenominalfrequencydeviation fromthecarrierfora'0'(-DEVIATN)and'1' (+DEVIATN)inamantissa-exponent format,interpretedasa4-bitvaluewith MSBimplicit1.Theresultingfrequency 2-FSK/GFSK/4- deviationisgivenby: 2:0 DEVIATION_M[2:0] 7(111) R/W FSK ƒ =ƒXOSC×(8+DEVIATION_M)×2DEVIATION_E dev 217 Thedefaultvaluesgive±47.607kHz deviationassuming26.0MHzcrystal frequency. OOK Thissettinghasnoeffect Table5-36.0x17:MCSM1-MainRadioControlStateMachineConfiguration Bit FieldName Reset R/W Description 7:6 R0 Notused 5:2 3(1100) R/W UsesettingfromSmartRFStudioSWRC176 Selectwhatshouldhappenwhenapackethasbeensent Setting Nextstateafterfinishingpackettransmission 0(00) IDLE 1:0 TXOFF_MODE[1:0] 0(00) R/W 1(01) FSTXON 2(10) StayinTX(startsendingpreamble) 3(11) Reserved 52 DetailedDescription Copyright©2011–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L www.ti.com SWRS105B–MAY2011–REVISEDJUNE2014 Table5-37.0x18:MCSM0-MainRadioControlStateMachineConfiguration Bit FieldName Reset R/W Description 7:6 R0 Notused AutomaticallycalibratewhengoingtoorfromTXmode Setting Whentoperformautomaticcalibration 0(00) Never(manuallycalibrateusingSCALstrobe) 5:4 FS_AUTOCAL[1:0] 0(00) R/W 1(01) WhengoingfromIDLEtoTX(orFSTXON) WhengoingfromTXbacktoIDLE 2(10) automatically Every4thtimewhengoingfromTXtoIDLE 3(11) automatically Programsthenumberoftimesthesix-bitripplecountermust expireaftertheXOSChassettledbeforeCHP_RDYngoes low.(1) IfXOSCison(stable)duringpower-down,PO_TIMEOUT shallbesetsothattheregulateddigitalsupplyvoltagehas timetostabilizebeforeCHP_RDYngoeslow (PO_TIMEOUT=2recommended).Typicalstart-uptimeforthe voltageregulatoris50μs. ForrobustoperationitisrecommendedtousePO_TIMEOUT =2or3whenXOSCisoffduringpower-down. Timeoutafter Setting Expirecount 3:2 PO_TIMEOUT 1(01) R/W XOSCstart Approximately2.3 0(00) 1 -2.4μs Approximately37- 1(01) 16 39μs Approximately149 2(10) 64 -155μs Approximately597 3(11) 256 -620μs Exacttimeoutdependsoncrystalfrequency. 1 0 R/W UsesettingfromSmartRFStudioSWRC176 0 XOSC_FORCE_ON 0 R/W ForcetheXOSCtostayonintheSLEEPstate. (1) NotethattheXOSC_STABLEsignalwillbeassertedatthesametimeastheCHIP_RDYnsignal;thatis,thePO_TIMEOUTdelaysboth signalsanddoesnotinsertadelaybetweenthesignals. Table5-38.0x20:RESERVED Bit FieldName Reset R/W Description 7:3 31(11111) R/W UsesettingfromSmartRFStudioSWRC176 2 R0 Notused 1:0 0(00) R/W UsesettingfromSmartRFStudioSWRC176 Table5-39.0x22:FREND0-FrontEndTXConfiguration Bit FieldName Reset R/W Description 7:6 R0 Notused LODIV_BUF_CURRENT_ AdjustscurrentTXLObuffer(inputtoPA).Thevaluetousein 5:4 1(01) R/W TX[1:0] thisfieldisgivenbytheSmartRFStudiosoftwareSWRC176. 3 R0 Notused SelectsPApowersetting.Thisvalueisanindextothe PATABLE,whichcanbeprogrammedwithupto2differentPA 2:0 PA_POWER[2:0] 0(000) R/W settings.WhenusingOOK,PA_POWERshouldbe001,andfor allothermodulationformatsitshouldbe000,seeSection5.5.6. Copyright©2011–2014,TexasInstrumentsIncorporated DetailedDescription 53 SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L SWRS105B–MAY2011–REVISEDJUNE2014 www.ti.com Table5-40.0x23:FSCAL3-FrequencySynthesizerCalibration Bit FieldName Reset R/W Description Frequencysynthesizercalibrationconfiguration.Thevalueto 7:6 FSCAL3[7:6] 2(10) R/W writeinthisfieldbeforecalibrationisgivenbytheSmartRFStudio softwareSWRC176. CHP_CURR_CAL_EN[1: 5:4 2(10) R/W Disablechargepumpcalibrationstagewhen0. 0] Frequencysynthesizercalibrationresultregister.Digitalbitvector definingthechargepumpoutputcurrent,onanexponentialscale: 3:0 FSCAL3[3:0] 9(1001) R/W I_OUT=I ×2FSCAL3[3:0]/4 0 SeeSection5.18.2formoredetails. Table5-41.0x24:FSCAL2-FrequencySynthesizerCalibration Bit FieldName Reset R/W Description 7:6 R0 Notused 5 VCO_CORE_H_EN 0 R/W Choosehigh(1)/low(0)VCO Frequencysynthesizercalibrationresultregister.VCOcurrent 4:0 FSCAL2[4:0] 10(01010) R/W calibrationresultandoverridevalue.SeeSection5.18.2formore details. Table5-42.0x25:FSCAL1-FrequencySynthesizerCalibration Bit FieldName Reset R/W Description 7:6 R0 Notused Frequencysynthesizercalibrationresultregister.Capacitorarray 5:0 FSCAL1[5:0] 32(0x20) R/W settingforVCOcoarsetuning. SeeSection5.18.2formoredetails. Table5-43.0x26:FSCAL0-FrequencySynthesizerCalibration Bit FieldName Reset R/W Description 7 R0 Notused Frequencysynthesizercalibrationcontrol.Thevaluetouseinthis 6:0 FSCAL0[6:0] 13(0x0D) R/W registerisgivenbytheSmartRFStudiosoftware 5.19.2 Configuration Register Details - Registers that Lose Programming in SLEEP State Table5-44.0x29:RESERVED Bit FieldName Reset R/W Description 7:0 89(0x59) R/W UsesettingfromSmartRFStudioSWRC176 Table5-45.0x2A:RESERVED Bit FieldName Reset R/W Description 7:0 127(0x7F) R/W UsesettingfromSmartRFStudioSWRC176 Table5-46.0x2B:RESERVED Bit FieldName Reset R/W Description 7:0 63(0x3F) R/W UsesettingfromSmartRFStudioSWRC176 54 DetailedDescription Copyright©2011–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L www.ti.com SWRS105B–MAY2011–REVISEDJUNE2014 Table5-47.0x2C:TEST2-VariousTestSettings Bit FieldName Reset R/W Description UsesettingfromSmartRFStudioSWRC176 Thisregisterwillbeforcedto0x88or0x81whenitwakesupfrom SLEEPmode,dependingontheconfigurationof FIFOTHR.ADC_RETENTION. 7:0 TEST2[7:0] 136(0x88) R/W ThevaluereadfromthisregisterwhenwakingupfromSLEEP alwaysistheresetvalue(0x88)regardlessofthe ADC_RETENTIONsetting.Theinvertingofsomeofthebitsdueto theADC_RETENTIONsettingisonlyseenINTERNALLYinthe analogpart. Table5-48.0x2D:TEST1-VariousTestSettings Bit FieldName Reset R/W Description 7:0 TEST1[7:0] 49(0x31) R/W UsesettingfromSmartRFStudioSWRC176 Table5-49.0x2E:TEST0-VariousTestSettings Bit FieldName Reset R/W Description 7:2 TEST0[7:2] 2(000010) R/W UsesettingfromSmartRFStudioSWRC176 1 VCO_SEL_CAL_EN 1 R/W EnableVCOselectioncalibrationstagewhen1 0 TEST0[0] 1 R/W UsesettingfromSmartRFStudioSWRC176 5.19.3 Status Register Details Table5-50.0x30(0xF0):PARTNUM-ChipID Bit FieldName Reset R/W Description 7:0 PARTNUM[7:0] 0(0x00) R Chippartnumber Table5-51.0x31(0xF1):VERSION-ChipID Bit FieldName Reset R/W Description 7:0 VERSION[7:0] 25(0x19) R Chipversionnumber.Subjecttochangewithoutnotice. Copyright©2011–2014,TexasInstrumentsIncorporated DetailedDescription 55 SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L SWRS105B–MAY2011–REVISEDJUNE2014 www.ti.com Table5-52.0x35(0xF5):MARCSTATE-MainRadioControlStateMachineState Bit FieldName Reset R/W Description 7:5 R0 Notused MainRadioControlFSMState Value Statename State(seeFigure5-9) 0(0x00) SLEEP SLEEP 1(0x01) IDLE IDLE 2(0x02) XOFF XOFF 3(0x03) VCOON_MC MANCAL 4(0x04) REGON_MC MANCAL 5(0x05) MANCAL MANCAL 6(0x06) VCOON FS_WAKEUP 7(0x07) REGON FS_WAKEUP 8(0x08) STARTCAL CALIBRATE 9(0x09) BWBOOST SETTLING 4:0 MARC_STATE[4:0] R 10(0x0A) FS_LOCK SETTLING 11(0x0B) Reserved 12(0x0C) ENDCAL CALIBRATE 13(0x0D)–17 Reserved (0x11) 18(0x12) FSTXON FSTXON 19(0x13) TX TX 20(0x14) TX_END TX 21(0x15) Reserved TXFIFO_UNDERF 22(0x16) TXFIFO_UNDERFLOW LOW Note:itisnotpossibletoreadbacktheSLEEPorXOFFstate numbersbecausesettingCSnlowwillmakethechipentertheIDLE modefromtheSLEEPorXOFFstates. Table5-53.0x38(0xF8):PKTSTATUS-CurrentGDOxStatusandPacketStatus Bit FieldName Reset R/W Description 7:3 R Reserved CurrentGDO2value.Note:thereadinggivesthenon-invertedvalue irrespectiveofwhatIOCFG2.GDO2_INVisprogrammedto. 2 GDO2 R ItisnotrecommendedtocheckforPLLlockbyreading PKTSTATUS[2]withGDO2_CFG=0x0A. 1 R0 Notused CurrentGDO0value.Note:thereadinggivesthenon-invertedvalue irrespectiveofwhatIOCFG0.GDO0_INVisprogrammedto. 0 GDO0 R ItisnotrecommendedtocheckforPLLlockbyreading PKTSTATUS[0]withGDO0_CFG=0x0A. Table5-54.0x3A(0xFA):TXBYTES-UnderflowandNumberofBytes Bit FieldName Reset R/W Description 7 TXFIFO_UNDERFLOW R 6:0 NUM_TXBYTES R NumberofbytesinTXFIFO 56 DetailedDescription Copyright©2011–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L www.ti.com SWRS105B–MAY2011–REVISEDJUNE2014 5.20 Development Kit Ordering Information OrderableEvaluationModule Description MinimumOrderQuantity CC11xLDK-868-915 CC11xLDevelopmentKit,868/915MHz 1 CC11xLEMK-433 CC11xLEvaluationModuleKit,433MHz 1 Copyright©2011–2014,TexasInstrumentsIncorporated DetailedDescription 57 SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L SWRS105B–MAY2011–REVISEDJUNE2014 www.ti.com 6 Applications, Implementation, and Layout Thelowcostapplicationcircuits(SWRR081 andSWRR082),whichusemultilayerinductors,areshownin Figure6-1andFigure6-2(seeTable6-1forcomponentvalues). The designs in SWRR046 and SWRR045 were used for CC115L characterization. The 315 MHz and 433 MHz design SWRR046 use inexpensive multi-layer inductors similar to the low cost application circuit while the 868 MHz and 915 MHz design SWRR045 use wire-wound inductors. Wire-wound inductors give betteroutputpowerandattenuationofharmonicscomparedtousingmulti-layerinductors. Refer to design note DN032 SWRA346 for information about performance when using wire-wound inductors from different vendors. See also Design Note DN013 SWRA168, which gives the output power and harmonics when using multi-layer inductors. The output power is then typically +10 dBm when operatingat868/915MHz. 6.1 Bias Resistor The56-kΩ biasresistorR171isusedtosetanaccuratebiascurrent. 6.2 Balun and RF Matching The balun and LC filter component values and their placement are important to keep the performance optimized. Gerber files and schematics for the reference designs are available for download from the TI website. The components between the RF_N/RF_P pins and the point where the two signals are joined together (C131, C122, L122, and L132 in Figure 6-1 and L121, L131, C121, L122, C131, C122, and L132 in Figure 6-2) form a balun that converts the differential RF signal on CC115L to a single-ended RF signal. C124isneededforDCblocking.L123,L124,andC123(plusC125inFigure6-1)formalow-passfilterfor harmonicsattenuation. The balun and LC filter components also matches the CC115L input impedance to a 50-Ω load. C126 provides DC blocking and is only needed if there is a DC path in the antenna. For the application circuit in Figure6-2,thiscomponentmayalsobeusedforadditionalfiltering,seeSection6.5. 1.8V-3.6V Power Supply R171 SI SI 20 ND 19 RD 18 AS17 ND 16 Antenna SCLK G GUA RBI G (50W) 1SCLK D AVDD15 e SO 2SO CC115L C131 efac G(GDDOO21) (GDO1) AVDD14 L132 C126 nt (optional) 3GDO2 RF_N13 al I 4DVDD DIEATTACHPAD: RF_P12 L123 L124 Digit C51 5DCOUPL6GDO0 7CSn 8XOSC_Q1 9AVDD 10XOSC_Q2 AVDD11 CL112224C122 C123 C125 GDO0 (optional) CSn XTAL C81 C101 Figure6-1.TypicalApplicationandEvaluationCircuit315or433MHz (ExcludingSupplyDecouplingCapacitors) 58 Applications,Implementation,andLayout Copyright©2011–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L www.ti.com SWRS105B–MAY2011–REVISEDJUNE2014 1.8 V - 3.6 V Power Supply R171 SI 0 9 8 7 6 2 1 1 1 1 SI ND RD AS ND Antenna SCLK G UA RBI G C131 (50W) 1 SCLK G AVDD 15 D ce SO 2 SO AVDD 14 L131 L132 nterfa G((oGDpDtOiOo2n1a)l) 3( GGDDOO12) CC115LRF_N 13 L123 L124 C126 al I 4 DVDD DIEATTACH PAD: RF_P12 C121 C122 Digit C51 5 DCOUP6 GDO0L 7 CSn 8 XOSC_Q1 9AVDD 10 XOSC_Q2AVDD 11 L121 L122 C123 C127 L125 C127 and L125 GDO0 C124 may be added to (optional) CSn build an optional filter to reduce XTAL emission at 699 MHz C81 C101 Figure6-2.TypicalApplicationandEvaluationCircuit868/915MHz (ExcludingSupplyDecouplingCapacitors) Table6-1.ExternalComponents Component Valueat315MHz Valueat433MHz Valueat868/915MHz WithoutC127andL125 WithC127andL125 C121 1pF 1pF C122 6.8pF 3.9pF 1.5pF 1.5pF C123 12pF 8.2pF 3.3pF 3.3pF C124 220pF 220pF 100pF 100pF C125 6.8pF 5.6pF C126 220pF 220pF 100pF 12pF C127 47pF C131 6.8pF 3.9pF 1.5pF 1.5pF L121 12nH 12nH L122 33nH 27nH 18nH 18nH L123 18nH 22nH 12nH 12nH L124 33nH 27nH 12nH 12nH L125 3.3nH L131 12nH 12nH L132 33nH 27nH 18nH 18nH Copyright©2011–2014,TexasInstrumentsIncorporated Applications,Implementation,andLayout 59 SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L SWRS105B–MAY2011–REVISEDJUNE2014 www.ti.com 6.3 Crystal A crystal in the frequency range 26 - 27 MHz must be connected between the XOSC_Q1 and XOSC_Q2 pins. The oscillator is designed for parallel mode operation of the crystal. In addition, loading capacitors (C81 and C101) for the crystal are required. The loading capacitor values depend on the total load capacitance, CL, specified for the crystal. The total load capacitance seen between the crystal terminals shouldequalCLforthecrystaltooscillateatthespecifiedfrequency. 1 C = +C L 1 1 parasitic + C C 81 101 (7) The parasitic capacitance is constituted by pin input capacitance and PCB stray capacitance. Total parasiticcapacitanceistypically2.5pF. The crystal oscillator is amplitude regulated. This means that a high current is used to start up the oscillations. When the amplitude builds up, the current is reduced to what is necessary to maintain approximately 0.4 Vpp signal swing. This ensures a fast start-up, and keeps the drive level to a minimum. The ESR of the crystal should be within the specification in order to ensure a reliable start-up (see Section4.7). Theinitialtolerance,temperaturedrift,agingandloadpullingshouldbecarefullyspecifiedinordertomeet therequiredfrequencyaccuracyinacertainapplication. Avoid routing digital signals with sharp edges close to XOSC_Q1 PCB track or underneath the crystal dc operatingpointandresultindutycyclevariation. For compliance with modulation bandwidth requirements under EN 300 220 V2.3.1 in the 863 to 870 MHz frequencyrangeitisrecommendedtousea26MHzcrystalforfrequenciesbelow869MHzanda27MHz crystalforfrequenciesabove869MHz. 6.4 Reference Signal Thechipcanalternativelybeoperatedwithareferencesignalfrom26to27MHzinsteadofacrystal.This input clock can either be a full- swing digital signal (0 V to VDD) or a sine wave of maximum 1 V peak- peak amplitude. The reference signal must be connected to the XOSC_Q1 input. The sine wave must be connected to XOSC_Q1 using a serial capacitor. When using a full-swing digital signal, this capacitor can be omitted. The XOSC_Q2 line must be left un-connected. C81 and C101 can be omitted when using a referencesignal. 6.5 Additional Filtering In the 868/915 MHz reference design SWRR082, C127 and L125 together with C126 build an optional filter to reduce emission at carrier frequency - 169 MHz. This filter is necessary for applications with an external antenna connector that seek compliance with ETSI EN 300 220 V2.3.1. For more information, see DN017 SWRA168. If this filtering is not necessary, C126 will work as a DC block (only necessary if thereisaDCpathintheantenna).C127andL125shouldinthatcasebeleftunmounted. Additional external components (that is, an RF SAW filter) may be used in order to improve the performanceinspecificapplications. 6.6 Power Supply Decoupling The power supply must be properly decoupled close to the supply pins. Note that decoupling capacitors are not shown in the application circuit. The placement and the size of the decoupling capacitors are very importanttoachievetheoptimumperformance(SWRR081andSWRR082shouldbefollowedclosely). 60 Applications,Implementation,andLayout Copyright©2011–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L www.ti.com SWRS105B–MAY2011–REVISEDJUNE2014 6.7 PCB Layout Recommendations The top layer should be used for signal routing, and the open areas should be filled with metallization connectedtogroundusingseveralvias. The area under the chip is used for grounding and shall be connected to the bottom ground plane with severalviasforgoodthermalperformanceandsufficientlylowinductancetoground. In SWRR081 and SWRR082, 5 vias are placed inside the exposed die attached pad. These vias should be “tented” (covered with solder mask) on the component side of the PCB to avoid migration of solder throughtheviasduringthesolderreflowprocess. The solder paste coverage should not be 100%. If it is, out gassing may occur during the reflow process, which may cause defects (splattering, solder balling). Using “tented” vias reduces the solder paste coveragebelow100%.SeeFigure6-3fortopsolderresistandtoppastemasks. Each decoupling capacitor should be placed as close as possible to the supply pin it is supposed to decouple. Each decoupling capacitor should be connected to the power line (or power plane) by separate vias. The best routing is from the power line (or power plane) to the decoupling capacitor and then to the CC115Lsupplypin.Supplypowerfilteringisveryimportant. Each decoupling capacitor ground pad should be connected to the ground plane by separate vias. Direct connections between neighboring power pins will increase noise coupling and should be avoided unless absolutely necessary. Routing in the ground plane underneath the chip or the balun/RF matching circuit, or between the chip's ground vias and the decoupling capacitor's ground vias should be avoided. This improvesthegroundingandensurestheshortestpossiblecurrentreturnpath. Avoid routing digital signals with sharp edges close to XOSC_Q1 PCB track or underneath the crystal Q1 padasthismayshiftthecrystaldcoperatingpointandresultindutycyclevariation. The external components should ideally be as small as possible (0402 is recommended) and surface mount devices are highly recommended. Components with different sizes than those specified may have differingcharacteristics. Precaution should be used when placing the microcontroller in order to avoid noise interfering with the RF circuitry. A CC11xL Development Kit with a fully assembled CC115L Evaluation Module is available. It is strongly advised that this reference layout is followed very closely in order to get the best performance. The schematic,BOMandlayoutGerberfilesareallavailablefromtheTIwebsite(SWRR081 andSWRR082). Figure6-3.Left:TopSolderResistMask(Negative) – Right:TopPasteMask.CirclesareVias Copyright©2011–2014,TexasInstrumentsIncorporated Applications,Implementation,andLayout 61 SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L SWRS105B–MAY2011–REVISEDJUNE2014 www.ti.com 7 Device and Documentation Support 7.1 Device Support 7.1.1 Device Nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all microprocessors (MPUs) and support tools. Each device has one of three prefixes: X, P, or null (no prefix) (for example, CC115L). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development fromengineeringprototypes(TMDX)throughfullyqualifiedproductiondevicesandtools(TMDS). Devicedevelopmentevolutionaryflow: X Experimental device that is not necessarily representative of the final device's electrical specificationsandmaynotuseproductionassemblyflow. P Prototype device that is not necessarily the final silicon die and may not necessarily meet finalelectricalspecifications. null Productionversionofthesilicondiethatisfullyqualified. Supporttooldevelopmentevolutionaryflow: TMDX Development-support product that has not yet completed Texas Instruments internal qualificationtesting. TMDS Fully-qualifieddevelopment-supportproduct. XandPdevicesandTMDXdevelopment-supporttoolsareshippedagainstthefollowingdisclaimer: "Developmentalproductisintendedforinternalevaluationpurposes." Production devices and TMDS development-support tools have been characterized fully, and the quality andreliabilityofthedevicehavebeendemonstratedfully.TI'sstandardwarrantyapplies. Predictions show that prototype devices (X or P) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, RGP) and the temperature range (for example, blank is the default commercialtemperaturerange). For orderable part numbers of CC115L devices in the QFN package types, see the Package Option Addendumofthisdocument,theTIwebsite(www.ti.com),orcontactyourTIsalesrepresentative. 62 DeviceandDocumentationSupport Copyright©2011–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L www.ti.com SWRS105B–MAY2011–REVISEDJUNE2014 7.2 Documentation Support 7.2.1 Related Documentation from Texas Instruments The following documents describe the CC115L transmitter. Copies of these documents are available on theInternetatwww.ti.com. SWRR046 Characterization Design 315 - 433 MHz (Identical to the CC1101EM 315 - 433 MHz ReferenceDesign) SWRR045 Characterization Design 868 - 915 MHz (Identical to the CC1101EM 868 - 915 MHz ReferenceDesign) SWRZ036 CC115LErrataNotes SWRC176 SmartRFStudio SWRA168 DN017CC11xx868/915MHzRFMatching SWRA123 DN006CC11xxSettingsforFCC15.247Solutions SWRA168 DN013ProgrammingOutputPoweronCC1101 SWRS089 CC1190DataSheet SWRA346 DN032OptionsforCostOptimizedCC11xxMatching SWRR081 CC110LEM/CC115LEM433MHzReferenceDesign SWRR082 CC110LEM/CC115LEM868-915MHzReferenceDesign 7.2.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; seeTI'sTermsofUse. TIE2E™OnlineCommunity TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, exploreideasandhelpsolveproblemswithfellowengineers. TIEmbeddedProcessorsWiki Texas Instruments Embedded Processors Wiki. Established to help developers get started with Embedded Processors from Texas Instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding thesedevices. 7.3 Trademarks E2EisatrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. Copyright©2011–2014,TexasInstrumentsIncorporated DeviceandDocumentationSupport 63 SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L SWRS105B–MAY2011–REVISEDJUNE2014 www.ti.com 7.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. 7.5 Export Control Notice Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled product restricted by other applicable national regulations, received from Disclosing party under this Agreement, or any direct product of such technology, to any destination to which such export or re- exportisrestrictedorprohibitedbyU.S.orotherapplicablelaws,withoutobtainingpriorauthorizationfrom U.S. Department of Commerce and other competent Government authorities to the extent required by thoselaws. 7.6 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronymsanddefinitions. 7.7 Additional Acronyms Additionalacronymsusedinthisdatasheetaredescribedbelow. 2-FSK BinaryFrequencyShiftKeying 4-FSK QuaternaryFrequencyShiftKeying ADC AnalogtoDigitalConverter AMR AutomaticMeterReading BOM BillofMaterial BT Bandwidth-Timeproduct CFR CodeofFederalRegulations CRC CyclicRedundancyCheck CW ContinuousWave(UnmodulatedCarrier) DC DirectCurrent ESR EquivalentSeriesResistance FCC FederalCommunicationsCommission FIFO First-In-First-Out FS FrequencySynthesizer GFSK GaussianshapedFrequencyShiftKeying IF IntermediateFrequency I/Q In-Phase/Quadrature ISM Industrial,Scientific,Medical LC Inductor-Capacitor LO LocalOscillator LSB LeastSignificantBit MCU MicrocontrollerUnit 64 DeviceandDocumentationSupport Copyright©2011–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L www.ti.com SWRS105B–MAY2011–REVISEDJUNE2014 MSB MostSignificantBit N/A NotApplicable NRZ NonReturntoZero(Coding) OOK On-OffKeying PA PowerAmplifier PCB PrintedCircuitBoard PD PowerDown PER PacketErrorRate PLL PhaseLockedLoop POR Power-OnReset QLP QuadLeadlessPackage QPSK QuadraturePhaseShiftKeying RC Resistor-Capacitor RF RadioFrequency SPI SerialPeripheralInterface SRD ShortRangeDevices TX Transmit,TransmitMode VCO VoltageControlledOscillator XOSC CrystalOscillator XTAL Crystal Copyright©2011–2014,TexasInstrumentsIncorporated DeviceandDocumentationSupport 65 SubmitDocumentationFeedback ProductFolderLinks:CC115L

CC115L SWRS105B–MAY2011–REVISEDJUNE2014 www.ti.com 8 Mechanical Packaging and Orderable Information 8.1 Packaging Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revisionofthisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 66 MechanicalPackagingandOrderableInformation Copyright©2011–2014,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC115L

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) CC115LRGPR ACTIVE QFN RGP 20 3000 Green (RoHS NIPDAU | NIPDAUAG Level-3-260C-168 HR -40 to 85 CC115L & no Sb/Br) CC115LRGPT ACTIVE QFN RGP 20 250 Green (RoHS NIPDAU | NIPDAUAG Level-3-260C-168 HR -40 to 85 CC115L & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 12-Feb-2019 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) CC115LRGPR QFN RGP 20 3000 330.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2 CC115LRGPT QFN RGP 20 250 180.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 12-Feb-2019 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) CC115LRGPR QFN RGP 20 3000 350.0 350.0 43.0 CC115LRGPT QFN RGP 20 250 210.0 185.0 35.0 PackMaterials-Page2

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