CC11x1-Q1 www.ti.com SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 Low-Power Sub-1-GHz Fractional-N UHF Device Family for Automotive 1 Introduction 1.1 Features 12 • QualificationinAccordanceWithAEC-Q100 – SupportforAutomaticClearChannel Grade1 Assessment(CCA)BeforeTransmitting(for Listen-Before-TalkSystems) • ExtendedTemperatureRangeUpTo125°C – SupportforPer-PackageLinkQuality • Radio-Frequency(RF)Performance Indication(LQI) – HighSensitivity(–114dBmat1.2kBaud, – OptionalAutomaticWhiteningand 315MHz,1%PacketErrorRate) DewhiteningofData – LowCurrentConsumption(15.5mAin • Low-PowerFeatures Receive,1.2kBaud,315MHz) – FastStartupTime:240µsFromSleepto • ProgrammableOutputPowerupto+10dBmfor Receive(RX)orTransmit(TX)Mode AllSupportedFrequencies – Wake-On-RadioFunctionalityforAutomatic • ExcellentReceiverSelectivityandBlocking Low-PowerRXPolling Performance – Separate64-ByteRXandTXDataFIFOs • ProgrammableDataRateFrom1.2kBaudto (EnablesBurstModeDataTransmission) 250kBaud • General • FrequencyBands:310MHzto348MHz, 420MHzto450MHz,and779MHzto928MHz – FewExternalComponents:Completely On-ChipFrequencySynthesizer,NoExternal • AnalogFeatures FiltersorRFSwitchNeeded – 2-FSK,GFSK,andMSKSupported,asWell – GreenPackage:RoHSCompliantandNo asOOKandFlexibleASKShaping AntimonyorBromine – SuitableforFrequency-HoppingSystems – SmallSizeQFN5-mm×5-mm32-PinPackage DuetoaFastSettlingFrequency Synthesizer:90-µsSettlingTime – SuitedforSystemsCompliantWith EN300220(Europe)andFCCCFRPart15 – AutomaticFrequencyCompensation(AFC) (US) CanAlignFrequencySynthesizerto ReceivedCenterFrequency – SupportforAsynchronousandSynchronous SerialReceive/TransmitModeforBackward – IntegratedAnalogTemperatureSensor CompatibilityWithExistingRadio • DigitalFeatures CommunicationProtocols – FlexibleSupportforPacket-Oriented – DesignedforAutomotiveApplications Systems:On-ChipSupportforSyncWord Detection,AddressCheck,FlexiblePacket Length,andAutomaticCRCHandling 1.2 Applications – EfficientSPIInterface:AllRegistersCanBe • Ultra-Low-PowerWirelessApplicationsinthe ProgrammedWithOneBurstTransfer 315/433/868/915-MHzISM/SRDBands – DigitalRSSIOutput • RemoteKeylessEntrySystems – ProgrammableChannelFilterBandwidth • PassiveEntry/PassiveStartSystems – ProgrammableCarrierSense(CS)Indicator • VehicleServiceLinks – ProgrammablePreambleQualityIndicator (PQI)forImprovedProtectionAgainstFalse • GarageDoorOpener SyncWordDetectioninRandomNoise • TPMSSystems 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. SmartRFisaregisteredtrademarkofTexasInstruments. 2 PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2009–2010,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

CC11x1-Q1 SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 www.ti.com 1.3 Advantages • RelayAttackPreventionThroughFastChannelHopping • LowestSystemCostThroughHighestIntegrationLevel • OnlyOneCrystalNeededForKey-FobDesigns • IntegratedProtocolHandling,Wake-On-Radio,ClockOutputRelaxMicrocontrollerRequirements 1.4 Family Members Allfamilymembersarepin-to-pinandsoftwarecompatible. UHFTransceivers CC1101IRHBRG4Q1(–40°Cto85°C) CC1101TRHBRG4Q1(–40°Cto105°C) CC1101QRHBRG4Q1(–40°Cto125°C) UHFReceivers CC1131IRHBRG4Q1(–40°Cto85°C) CC1131TRHBRG4Q1(–40°Cto105°C) CC1131QRHBRG4Q1(–40°Cto125°C) UHFTransmitters CC1151IRHBRG4Q1(–40°Cto85°C) CC1151TRHBRG4Q1(–40°Cto105°C) CC1151QRHBRG4Q1(–40°Cto125°C) 1.5 Description The CC11x1-Q1 device family is designed for very low-power wireless applications. The circuits are mainly intended for the Industrial, Scientific and Medical (ISM) and Short Range Device (SRD) frequency bands at 315 MHz, 433 MHz, 868 MHz, and 915 MHz, but can easily be programmed for operation at otherfrequenciesinthe310-MHzto348-MHz,420-MHzto450-MHz,and779-MHzto928-MHzbands. The devices integrate a highly configurable baseband modem. The modem supports various modulation formats and has a configurable data rate up to 250 kBaud. CC11x1-Q1 family provides extensive hardware support for packet handling, data buffering, burst transmissions, clear channel assessment, link quality indication, and wake-on-radio. The main operating parameters and the 64-byte transmit/receive FIFOs can be controlled via an SPI interface. In a typical system, the devices are used together with a microcontrollerandafewadditionalpassivecomponents. WARNING This product shall not be used in any of the following products or systems withoutpriorexpresswrittenpermissionfromTexasInstruments: (i) implantable cardiac rhythm management systems, including without limitationpacemakers,defibrillatorsandcardiacresynchronizationdevices; (ii) external cardiac rhythm management systems that communicate directly withoneormoreimplantablemedicaldevices;or (iii) other devices used to monitor or treat cardiac function, including without limitationpressuresensors,biochemicalsensorsandneurostimulators. Please contact lpw-medical-approval@list.ti.com if your application might fall withinacategorydescribedabove. 2 Introduction Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC11x1-Q1 www.ti.com SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 1.6 Abbreviations Thefollowingabbreviationsareusedinthisdatamanual. ACP AdjacentChannelPower MSK MinimumShiftKeying ADC Analog-to-DigitalConverter N/A NotApplicable AFC AutomaticFrequencyCompensation NRZ NonReturntoZero(Coding) AGC AutomaticGainControl OOK On-OffKeying AMR AutomaticMeterReading PA PowerAmplifier ASK AmplitudeShiftKeying PCB PrintedCircuitBoard BER BitErrorRate PD PowerDown BT Bandwidth-TimeProduct PER PacketErrorRate CCA ClearChannelAssessment PLL Phase-LockedLoop CFR CodeofFederalRegulations POR Power-OnReset CRC CyclicRedundancyCheck PQI PreambleQualityIndicator CS CarrierSense PQT PreambleQualityThreshold CW ContinuousWave(UnmodulatedCarrier) PTAT ProportionalToAbsoluteTemperature DC DirectCurrent QLP QuadLeadlessPackage DVGA DigitalVariableGainAmplifier QPSK QuadraturePhaseShiftKeying ESR EquivalentSeriesResistance RC ResistorCapacitor FCC FederalCommunicationsCommission RF RadioFrequency FEC ForwardErrorCorrection RSSI ReceivedSignalStrengthIndicator FIFO FirstIn,FirstOut RX Receive,ReceiveMode FHSS FrequencyHoppingSpreadSpectrum SAW SurfaceAcousticWave 2-FSK BinaryFrequencyShiftKeying SMD SurfaceMountDevice GFSK GaussianshapedFrequencyShiftKeying SNR Signal-to-NoiseRatio IF IntermediateFrequency SPI SerialPeripheralInterface I/Q In-Phase/Quadrature SRD ShortRangeDevices ISM Industrial,Scientific,Medical TBD ToBeDefined LC Inductor-Capacitor T/R Transmit/Receive LNA LowNoiseAmplifier TX Transmit,TransmitMode LO LocalOscillator UHF Ultra-HighFrequency LSB Least-SignificantBit VCO VoltageControlledOscillator LQI LinkQualityIndicator WOR WakeonRadio,Lowpowerpolling MCU MicrocontrollerUnit XOSC CrystalOscillator MSB Most-SignificantBit XTAL Crystal Copyright©2009–2010,TexasInstrumentsIncorporated Introduction 3 SubmitDocumentationFeedback

CC11x1-Q1 SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 www.ti.com 1 Introduction .............................................. 1 3.7 MicrocontrollerInterfaceandPinConfiguration .... 28 .............................................. ............................ 1.1 Features 1 3.8 DataRateProgramming 29 .......................................... ................. 1.2 Applications 1 3.9 ReceiverChannelFilterBandwidth 29 1.3 Advantages .......................................... 2 3.10 Demodulator,SymbolSynchronizer,andData ............................................ Decision 30 ..................................... 1.4 FamilyMembers 2 ................ 3.11 PacketHandlingHardwareSupport 31 1.5 Description ........................................... 2 3.12 ModulationFormats ................................ 37 ........................................ 1.6 Abbreviations 3 3.13 ReceivedSignalQualifiersandLinkQuality 2 ElectricalSpecifications ............................... 5 Information.......................................... 38 ........ .......................... 3.14 ForwardErrorCorrectionWithInterleaving 43 2.1 AbsoluteMaximumRatings 5 ....................................... 3.15 RadioControl 44 ............... 2.2 RecommendedOperatingConditions 5 .......................................... 3.16 DataFIFO 50 .............................. 2.3 GeneralCharacteristics 5 ........................... 3.17 FrequencyProgramming 52 ................................ 2.4 CurrentConsumption 6 ................................................ 3.18 VCO 52 ................. 2.5 RFReceiveSectionCharacteristics 8 ................................. 3.19 VoltageRegulators 53 ........................................... 2.6 Selectivity 10 ........................ 3.20 OutputPowerProgramming 53 ....................... 2.7 RSSISectionCharacteristics 11 .......................... 3.21 ShapingandPARamping 54 ............... 2.8 RFTransmitSectionCharacteristics 12 ................................... 3.22 CrystalOscillator 55 ................... 2.9 CrystalOscillatorCharacteristics 13 .................................. 3.23 ExternalRFMatch 55 .......... 2.10 Low-PowerRCOscillatorCharacteristics 13 .................... 3.24 PCBLayoutRecommendations 56 ............ 2.11 FrequencySynthesizerCharacteristics 14 ....... 3.25 GeneralPurpose/TestOutputControlPins 56 ....... 2.12 AnalogTemperatureSensorCharacteristics 15 3.26 AsynchronousandSynchronousSerialOperation ...................................................... ............ 59 2.13 DigitalInput/OutputDCCharacteristics 15 ............ ................... 3.27 SystemConsiderationsandGuidelines 60 2.14 Power-OnResetCharacteristics 15 4 ConfigurationRegisters .............................. 63 ................................ 2.15 SPIInterfaceTiming 16 ............................................ 4.1 Overview 63 ..................... 2.16 TypicalStateTransitionTiming 16 ..................................... 4.2 RegisterDetails 68 3 DetailedDescription .................................. 17 5 PackageandShippingInformation ................ 86 .............................. 3.1 TerminalAssignments 17 ....................... 5.1 PackageThermalProperties 86 ...................................... 3.2 BlockDiagram 19 ............................... 5.2 SolderingInformation 86 .................................. 3.3 ApplicationCircuit 20 .............. 5.3 CarrierTapeandReelSpecifications 86 ............................. 3.4 ConfigurationOverview 22 ................................ 5.4 OrderingInformation 86 ............................. 3.5 ConfigurationSoftware 23 6 References .............................................. 87 .... 3.6 4-WireSerialConfigurationandDataInterface 24 RevisionHistory ............................................ 88 4 Contents Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC11x1-Q1 www.ti.com SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 2 Electrical Specifications 2.1 Absolute Maximum Ratings(1) overoperatingfree-airtemperaturerange(unlessotherwisenoted) V Supplyvoltage(2) –0.3Vto3.9V DD Voltageonanydigitalpin –0.3Vto(V +0.3V)(3) DD VoltageonthepinsRF_P,RF_N,DCOUPL1andDCOUPL2 –0.3Vto2V Voltageramp-uprate 120kV/µs InputRFlevel 10dBm T Storagetemperaturerange –50°Cto150°C stg T Solderreflowtemperature(4) 260°C solder Human-BodyModel(HBM)(6) ±750V ESD Electrostaticdischargerating(5) Charged-DeviceModel(CDM)(7) ±200V MachineModel(MM)(8) ±100V (1) Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperating conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Allsupplypinsmusthavethesamevoltage. (3) Maximumvoltageis3.9V. (4) MeasuredaccordingtoIPC/JEDECJ-STD-020C (5) High-sensitivityUHFdevicesmustbehandledwithspecialcaretoavoidESDdamage.TIisnotresponsiblefordamagetothisdevice causedbyexternalESDconditions.Thefollowingelectrostaticdischarge(ESD)precautionsarerecommended: • Protectiveoutergarments • HandlinginESD-safeguardedworkarea • TransportinginESD-shieldedcontainers • FrequentmonitoringandtestingofallESD-protectionequipment (6) MeasuredaccordingtoJEDECSTD22,MethodA114 (7) MeasuredaccordingtoJEDECSTD22,C101C (8) MeasuredaccordingtoJEDECSTD22,MethodA115A 2.2 Recommended Operating Conditions MIN MAX UNIT V Supplyvoltage 1.8 3.6 V DD Itemperaturesuffix –40 85 T Operatingfree-airtemperature Ttemperaturesuffix –40 105 °C A Qtemperaturesuffix –40 125 2.3 General Characteristics PARAMETER TESTCONDITIONS MIN TYP MAX UNIT 310 348 Frequencyrange T =–40°Cto105°C,V =1.8Vto3.3V 420 450 MHz A DD 779 928 Thedataratestepsizeisdeterminedbythereferencefrequency– 1.2 250 Datarate(1) seeDataRateProgramming kBaud ShapedMSK(alsoknownasdifferentialoffsetQPSK) 26to250 Deviceweight 0.0715 g (1) OptionalManchesterencodinghalvesthedatarate. Copyright©2009–2010,TexasInstrumentsIncorporated ElectricalSpecifications 5 SubmitDocumentationFeedback

CC11x1-Q1 SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 www.ti.com 2.4 Current Consumption V =1.8Vto3.3V,f =26MHz,AllvoltagesrefertoGND(unlessotherwisenoted).TypicalvaluesatT =25°C,V =3 DD REF A DD V.Allmeasurementresultsobtainedusingthereferencedesigns. PARAMETER TESTCONDITIONS T MIN TYP MAX UNIT A Voltageregulatortodigitalpartoff,registervalues –40°Cto105°C 0.7 5 retained,RCoscillatoroff,allGDOpinsprogrammedto 0X2F(SLEEPstate) 125°C 1.9 Voltageregulatortodigitalpartoff,registervalues –40°Cto105°C 2 6 retained,low-powerRCoscillatorrunning(SLEEPstate withWORenabled) 125°C 2.5 µA Voltageregulatortodigitalpartoff,registervalues –40°Cto105°C 370 490 retained,XOSCrunning(SLEEPstatewith Currentconsumptionin MCSM0.OSC_FORCE_ONset) 125°C 400 power-downmodes Voltageregulatortodigitalparton,allothermodulesin –40°Cto105°C 160 300 powerdown(XOFFstate) 125°C 190 Onlyvoltageregulatortodigitalpartandcrystaloscillator –40°Cto105°C 1.8 2.5 running(IDLEstate) 125°C 1.9 mA Onlythefrequencysynthesizerrunning(aftergoingfrom –40°Cto105°C 9 10.5 IDLEuntilreachingRXorTXstates,andfrequency calibrationstates) 125°C 9.1 Transmitmode(1),10-dBmoutputpower,Continuous –40°Cto105°C 29.5 32.9 wave 125°C 28.9 –40°Cto105°C 14.6 16.5 Transmitmode(1),0-dBmoutputpower,Continuouswave 125°C 14.3 Transmitmode(1),–5-dBmoutputpower,Continuous –40°Cto105°C 12.2 14 wave 125°C 12.1 Currentconsumption, Receivemode(2),1.2kbps,input20dBabovesensitivity –40°Cto105°C 17.5 21 315MHz limit 125°C 18.3 mA Receivemode(2),38.4kbps,input20dBabovesensitivity –40°Cto105°C 17.5 21 limit 125°C 18.4 Receivemode(2),38.4kbps,input20dBabovesensitivity –40°Cto105°C 15.5 17 limit,low-currentmode (MDMCFG2.DEM_DCFILT_OFF=1) 125°C 16.5 Receivemode(2),250kbps,input30dBabovesensitivity –40°Cto105°C 17.8 21.5 limit 125°C 18.4 –40°Cto105°C 30.5 33 Transmitmode(1),10-dBmoutputpower 125°C 30 –40°Cto105°C 15.4 17.5 Transmitmode(1),0-dBmoutputpower 125°C 15.1 –40°Cto105°C 13.1 14.9 Transmitmode(1),–5-dBmoutputpower 125°C 13 Currentconsumption, Receivemode(2),1.2kbps,input20dBabovesensitivity –40°Cto105°C 18.6 22 433MHz limit 125°C 19.2 mA Receivemode(2),38.4kbps,input20dBabovesensitivity –40°Cto105°C 18.6 22.2 limit 125°C 19.3 Receivemode(2),38.4kbps,input20dBabovesensitivity –40°Cto105°C 16.5 18 limit,low-currentmode (MDMCFG2.DEM_DCFILT_OFF=1) 125°C 17 Receivemode(2),250kbps,input30dBabovesensitivity –40°Cto105°C 18.6 22.2 limit 125°C 19.3 (1) TransmitparametersvalidforCC1101andCC1151only (2) ReceiveparametersvalidforCC1101andCC1131only 6 ElectricalSpecifications Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC11x1-Q1 www.ti.com SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 CurrentConsumption(continued) V =1.8Vto3.3V,f =26MHz,AllvoltagesrefertoGND(unlessotherwisenoted).TypicalvaluesatT =25°C,V =3 DD REF A DD V.Allmeasurementresultsobtainedusingthereferencedesigns. PARAMETER TESTCONDITIONS T MIN TYP MAX UNIT A –40°Cto105°C 35.5 39 Transmitmode(1),10-dBmoutputpower 125°C 33.9 –40°Cto105°C 16.4 18.5 Transmitmode(1),0-dBmoutputpower 125°C 16.2 –40°Cto105°C 15 17.5 Transmitmode(1),–5-dBmoutputpower 125°C 16 Currentconsumption, Receivemode(2),1.2kbps,input20dBabovesensitivity –40°Cto105°C 18.5 21.5 868MHz limit 125°C 19 mA Receivemode(2),38.4kbps,input20dBabovesensitivity –40°Cto105°C 18.4 21.5 limit 125°C 19 Receivemode(2),38.4kbps,input20dBabovesensitivity –40°Cto105°C 16 18 limit,low-currentmode (MDMCFG2.DEM_DCFILT_OFF=1) 125°C 16.5 Receivemode(2),250kbps,input30dBabovesensitivity –40°Cto105°C 18.5 22 limit 125°C 19.1 –40°Cto105°C 34 41 Transmitmode(1),10-dBmoutputpower 125°C 32 –40°Cto105°C 16 18 Transmitmode(1),0-dBmoutputpower 125°C 15.8 –40°Cto105°C 14.5 16.5 Transmitmode(1),–5-dBmoutputpower 125°C 15.5 Currentconsumption, Receivemode(2),1.2kbps,input20dBabovesensitivity –40°Cto105°C 18.2 21.5 915MHz limit 125°C 18.8 mA Receivemode(2),38.4kbps,input20dBabovesensitivity –40°Cto105°C 18.3 21.5 limit 125°C 18.8 Receivemode(2),38.4kbps,input20dBabovesensitivity –40°Cto105°C 16 18 limit,low-currentmode (MDMCFG2.DEM_DCFILT_OFF=1) 125°C 16.5 Receivemode(2),250kbps,input30dBabovesensitivity –40°Cto105°C 18.3 21.5 limit 125°C 18.8 Copyright©2009–2010,TexasInstrumentsIncorporated ElectricalSpecifications 7 SubmitDocumentationFeedback

CC11x1-Q1 SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 www.ti.com 2.5 RF Receive Section Characteristics V =1.8Vto3.3V,Forwarderrorcorrectiondisabled,AllvoltagesrefertoGND(unlessotherwisenoted).Typicalvaluesat DD T =25°C,V =3V.ReceiveparametersvalidforCC1101andCC1131only. A DD PARAMETER TESTCONDITIONS T MIN TYP MAX UNIT A DigitalchannelRX Userprogrammable,dependonreferencefrequency,f 58to REF kHz filterinputbandwidth =26MHz 812 1.2kBaud/2-FSK,1%packeterrorrate,TXdeviation5.2 –40°Cto105°C –114 kHz,58-kHzRXbandwidth,high-sensitivitymode (MDMCFG2.DEM_DCFILT_OFF=0) 125°C –113 1.2kBaud/2-FSK,1%packeterrorrate,TXdeviation5.2 –40°Cto105°C –109 kHz,58-kHzRXbandwidth,low-currentmode (MDMCFG2.DEM_DCFILT_OFF=1) 125°C –105 38.4kBaud/2-FSK,1%packeterrorrate,TXdeviation –40°Cto105°C –98 –105 Receiversensitivity, 19kHz,100-kHzRXbandwidth,high-sensitivitymode dBm 315MHz (MDMCFG2.DEM_DCFILT_OFF=0) 125°C –101 38.4kBaud/2-FSK,1%packeterrorrate,TXdeviation –40°Cto105°C –96 –103 19kHz,100-kHzRXbandwidth,low-currentmode (MDMCFG2.DEM_DCFILT_OFF=1) 125°C –100 1.2kBaud/ASK,1%packeterrorrate,58-kHzRX bandwidth,high-sensitivity –40°Cto105°C –108 mode(MDMCFG2.DEM_DCFILT_OFF=0) 1.2kBaud/2-FSK,1%packeterrorrate,TXdeviation5.2 –40°Cto105°C –114 kHz,58-kHzRXbandwidth,high-sensitivitymode (MDMCFG2.DEM_DCFILT_OFF=0) 125°C –113 1.2kBaud/2-FSK,1%packeterrorrate,TXdeviation5.2 –40°Cto105°C –109 kHz,58-kHzRXbandwidth,low-currentmode (MDMCFG2.DEM_DCFILT_OFF=1) 125°C –105 38.4kBaud/2-FSK,1%packeterrorrate,TXdeviation –40°Cto105°C –100 –107 Receiversensitivity, 19kHz,100-kHzRXbandwidth,high-sensitivitymode dBm 433MHz (MDMCFG2.DEM_DCFILT_OFF=0) 125°C –102 38.4kBaud/2-FSK,1%packeterrorrate,TXdeviation –40°Cto105°C –98 –104 19kHz,100-kHzRXbandwidth,low-currentmode (MDMCFG2.DEM_DCFILT_OFF=1) 125°C –101 1.2kBaud/ASK,1%packeterrorrate,58-kHzRX bandwidth,high-sensitivitymode. –40°Cto105°C –109 (MDMCFG2.DEM_DCFILT_OFF=0) 1.2kBaud/2-FSK,1%packeterrorrate,TXdeviation5.2 –40°Cto105°C –111 kHz,58-kHzRXbandwidth,high-sensitivitymode (MDMCFG2.DEM_DCFILT_OFF=0) 125°C –109 1.2kBaud/2-FSK,1%packeterrorrate,TXdeviation5.2 –40°Cto105°C –107 kHz,58-kHzRXbandwidth,low-currentmode (MDMCFG2.DEM_DCFILT_OFF=1) 125°C –102 38.4kBaud/2-FSK,1%packeterrorrate,TXdeviation –40°Cto105°C –100 –106 19kHz,100-kHzRXbandwidth,high-sensitivitymode Receiversensitivity, (MDMCFG2.DEM_DCFILT_OFF=0) 125°C –101 dBm 868MHz 38.4kBaud/2-FSK,1%packeterrorrate,TXdeviation –40°Cto105°C –96 –103 19kHz,100-kHzRXbandwidth,low-currentmode (MDMCFG2.DEM_DCFILT_OFF=1) 125°C –99 250kBaud/2-FSK,1%packeterrorrate,TXdeviation –40°Cto105°C –90 –98 127kHz,540-kHzRXbandwidth,high-sensitivitymode (MDMCFG2.DEM_DCFILT_OFF=0) 125°C –95 1.2kBaud/ASK,1%packeterrorrate,58-kHzRX bandwidth,high-sensitivitymode. –40°Cto105°C –108 (MDMCFG2.DEM_DCFILT_OFF=0) 8 ElectricalSpecifications Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC11x1-Q1 www.ti.com SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 RFReceiveSectionCharacteristics(continued) V =1.8Vto3.3V,Forwarderrorcorrectiondisabled,AllvoltagesrefertoGND(unlessotherwisenoted).Typicalvaluesat DD T =25°C,V =3V.ReceiveparametersvalidforCC1101andCC1131only. A DD PARAMETER TESTCONDITIONS T MIN TYP MAX UNIT A 1.2kBaud/2-FSK,1%packeterrorrate,TXdeviation5.2 –40°Cto105°C –111 kHz,58-kHzRXbandwidth,high-sensitivitymode (MDMCFG2.DEM_DCFILT_OFF=0) 125°C –109 1.2kBaud/2-FSK,1%packeterrorrate,TXdeviation5.2 –40°Cto105°C –107 kHz,58-kHzRXbandwidth,low-currentmode (MDMCFG2.DEM_DCFILT_OFF=1) 125°C –102 38.4kBaud/2-FSK,1%packeterrorrate,TXdeviation –40°Cto105°C –100 –107 Receiversensitivity, 19kHz,100-kHzRXbandwidth,high-sensitivitymode dBm 915MHz (MDMCFG2.DEM_DCFILT_OFF=0) 125°C –102 38.4kBaud/2-FSK,1%packeterrorrate,TXdeviation –40°Cto105°C –97 –103 19kHz,100-kHzRXbandwidth,low-currentmode (MDMCFG2.DEM_DCFILT_OFF=1) 125°C –100 250kBaud/2-FSK,1%packeterrorrate,TXdeviation –40°Cto105°C –98 127kHz,540-kHzRXbandwidth,high-sensitivitymode (MDMCFG2.DEM_DCFILT_OFF=0) 125°C –93 38.4kBaud/2-FSK,1%packeterrorrate,TXdeviation –40°Cto105°C –56 Receiveradjacent 19kHz,100-kHzRXbandwidth,low-currentmode channelrejection, (MDMCFG2.DEM_DCFILT_OFF=1),Channelspacing dB 315MHz/433MHz 200kHz,Desiredchannel3dBabovesensitivitylevel, 125°C –52 Signallevelat±200kHz 38.4kBaud/2-FSK,1%packeterrorrate,TXdeviation –40°Cto105°C –55 Receiveralternate 19kHz,100-kHzRXbandwidth,low-currentmode channelrejection, (MDMCFG2.DEM_DCFILT_OFF=1),Channelspacing dB 315MHz/433MHz 200kHz,Desiredchannel3dBabovesensitivitylevel, 125°C –50 Signallevelat±400kHz 38.4kBaud/2-FSK,1%packeterrorrate,TXdeviation –40°Cto105°C –46 Receiverblocking 19kHz,100-kHzRXbandwidth,low-currentmode ±2MHz, (MDMCFG2.DEM_DCFILT_OFF=1),Channelspacing dBm 315MHz/433MHz 200kHz,Desiredchannel3dBabovesensitivitylevel, 125°C –41 Signallevelat±2MHz 38.4kBaud/2-FSK,1%packeterrorrate,TXdeviation –40°Cto105°C –40 Receiverblocking 19kHz,100-kHzRXbandwidth,low-currentmode ±10MHz, dBm 315MHz/433MHz (MDMCFG2.DEM_DCFILT_OFF=1),Desiredchannel3 125°C –33 dBabovesensitivitylevel,Signallevelat±10MHz 38.4kBaud/2-FSK,1%packeterrorrate,TXdeviation –40°Cto105°C –65 Receiverimage 19kHz,100-kHzRXbandwidth,low-currentmode channelrejection, (MDMCFG2.DEM_DCFILT_OFF=1),Channelspacing dB 315MHz/433MHz 200kHz,Desiredchannel3dBabovesensitivitylevel, 125°C –61 Signallevelatf –608kHz Signal 38.4kBaud/2-FSK,1%packeterrorrate,TXdeviation –40°Cto105°C –64 Receiveradjacent 19kHz,100-kHzRXbandwidth,low-currentmode channelrejection, (MDMCFG2.DEM_DCFILT_OFF=1),Channelspacing dB 868MHz/915MHz 200kHz,Desiredchannel3dBabovesensitivitylevel, 125°C –61 Signallevelat±200kHz 38.4kBaud/2-FSK,1%packeterrorrate,TXdeviation –40°Cto105°C –58 Receiveralternate 19kHz,100-kHzRXbandwidth,low-currentmode channelrejection, (MDMCFG2.DEM_DCFILT_OFF=1),Channelspacing dB 868MHz/915MHz 200kHz,Desiredchannel3dBabovesensitivitylevel, 125°C –54 Signallevelat±400kHz 38.4kBaud/2-FSK,1%packeterrorrate,TXdeviation –40°Cto105°C –44 19kHz,100-kHzRXbandwidth,low-currentmode Receiverblocking, (MDMCFG2.DEM_DCFILT_OFF=1),Wantedsignal3dB dBm 868MHz±2MHz abovesensitivitylimit,levelofunmodulatedsignalat±2 125°C –40 MHzisrecorded 38.4kBaud/2-FSK,1%packeterrorrate,TXdeviation –40°Cto105°C –38 19kHz,100-kHzRXbandwidth,low-currentmode Receiverblocking, (MDMCFG2.DEM_DCFILT_OFF=1),Wantedsignal3dB dBm 868MHz±10MHz abovesensitivitylimit,Levelofunmodulatedsignalat±10 125°C –33 MHzisrecorded Copyright©2009–2010,TexasInstrumentsIncorporated ElectricalSpecifications 9 SubmitDocumentationFeedback

CC11x1-Q1 SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 www.ti.com RFReceiveSectionCharacteristics(continued) V =1.8Vto3.3V,Forwarderrorcorrectiondisabled,AllvoltagesrefertoGND(unlessotherwisenoted).Typicalvaluesat DD T =25°C,V =3V.ReceiveparametersvalidforCC1101andCC1131only. A DD PARAMETER TESTCONDITIONS T MIN TYP MAX UNIT A 38.4kBaud/2-FSK,1%packeterrorrate,TXdeviation –40°Cto105°C –60 Receiverimage 19kHz,100-kHzRXbandwidth,low-currentmode channelrejection, (MDMCFG2.DEM_DCFILT_OFF=1),Channelspacing dB 868MHz/915MHz 200kHz,Desiredchannel3dBabovesensitivitylevel, 125°C –55 Signallevelatf –608kHz Signal 38.4kBaud/2-FSK,1%packeterrorrate, 25MHzto –40°Cto105°C –57 Receiverspurious TXdeviation19kHz,100-kHzRX 1GHz dBm emission bandwidth,low-currentmode (MDMCFG2.DEM_DCFILT_OFF=1) >1GHz –40°Cto105°C –47 2.6 Selectivity Figure2-1toFigure2-3showthetypicalselectivityperformance(adjacentandalternaterejection). 50 40 30 B] d [ y 20 vit ecti 10 el S 0 -10 -20 -1.0 -0.9-0.8 -0.7-0.5 -0.4 -0.2-0.1 0.1 0.2 0.4 0.6 0.7 0.8 0.9 1.0 Frequencyoffset[MHz] Figure2-1.TypicalSelectivityat1.2-kBaudDataRate,868.3MHz,GFSK,5.2-kHzDeviation, IFFrequency152.3kHz,DigitalChannelFilterBandwidth58kHz 50.0 40.0 30.0 B] d 20.0 [ y vit ecti 10.0 el S 0.0 -10.0 -20.0 -1.0 -0.8 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.4 0.5 0.8 1.0 Frequencyoffset[MHz] Figure2-2.TypicalSelectivityat38.4-kBaudDataRate,868MHz,GFSK,20-kHzDeviation, IFFrequency152.3kHz,DigitalChannelFilterBandwidth100kHz 10 ElectricalSpecifications Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC11x1-Q1 www.ti.com SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 Selectivity(continued) 50.0 40.0 30.0 B] d 20.0 [ y vit ecti 10.0 el S 0.0 -10.0 -20.0 -3.00 -2.25 1.50 -1.00 -0.75 0.00 0.75 1.00 1.50 2.25 3.00 Frequencyoffset[MHz] Figure2-3.TypicalSelectivityat250-kBaudDataRate,868MHz,GFSK, IFFrequency304kHz,DigitalChannelFilterBandwidth540kHz 2.7 RSSI Section Characteristics(1) V =1.8Vto3.3V,AllvoltagesrefertoGND(unlessotherwisenoted).TypicalvaluesatT =25°C,V =3V.Receive DD A DD parametersvalidforCC1101andCC1131only. PARAMETER TESTCONDITIONS T MIN TYP MAX UNIT A RXmode,100-kHzRXbandwidth,Referencesignal –40°Cto105°C –90 CW,–90-dBmpowerlevel.ReadRSSIstatusregister andcalculatemeasuredRSSIlevel. 125°C RSSIaccuracy,310MHz dBm RXmode,100-kHzRXbandwidth,Referencesignal –40°Cto105°C –20 CW,–20-dBmpowerlevel.ReadRSSIstatusregister andcalculatemeasuredRSSIlevel. 125°C RXmode,100-kHzRXbandwidth,Referencesignal –40°Cto105°C –97 –89 –82 CW,–90-dBmpowerlevel.ReadRSSIstatusregister andcalculatemeasuredRSSIlevel. 125°C –91 RXmode,100-kHzRXbandwidth,Referencesignal –40°Cto105°C –62 –54 –45 RSSIaccuracy,928MHz CW,–55-dBmpowerlevel.ReadRSSIstatusregister dBm andcalculatemeasuredRSSIlevel. 125°C –56 RXmode,100-kHzRXbandwidth,Referencesignal –40°Cto105°C –27 –19 –10 CW,–20-dBmpowerlevel.ReadRSSIstatusregister andcalculatemeasuredRSSIlevel. 125°C –21 (1) RSSItolerancescanbecompensatedbyanoffsetcorrectionforeachdevice. Copyright©2009–2010,TexasInstrumentsIncorporated ElectricalSpecifications 11 SubmitDocumentationFeedback

CC11x1-Q1 SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 www.ti.com 2.8 RF Transmit Section Characteristics V =1.8Vto3.3V,AllvoltagesrefertoGND(unlessotherwisenoted).TypicalvaluesatT =25°C,V =3V.Transmit DD A DD parametersvalidforCC1101andCC1151only. PARAMETER TESTCONDITIONS T MIN TYP MAX UNIT A 315MHz 122+j31 Loadimpedanceasseenfromthe Differentialload RFportRF_NandRF_Ptowardsthe 433MHz 116+j41 –40°Cto105°C Ω impedance antenna.Formatchingfollowthe 868MHz/ referencedesign. 87+j43 915MHz 38.4kBaud/GFSK,TXdeviation19kHz,Outputpower –40°Cto105°C 9 11 12.5 setting:10dBm CW,Deliveredintoa50-Ωload,includingmatching 125°C 10 networkasoutlined 38.4kBaud/GFSK,TXdeviation19kHz,Outputpower –40°Cto105°C –3 –0.5 2.5 TXoutputpower, setting:0dBm dBm 315MHz CW,Deliveredintoa50-Ωload,includingmatching 125°C –1.5 networkasoutlined 38.4kBaud/GFSK,TXdeviation19kHz,Outputpower –40°Cto105°C –8.5 –5.7 –2.5 setting:–5dBm CW,Deliveredintoa50-Ωload,includingmatching 125°C –6.7 networkasoutlined 38.4kBaud/GFSK,TXdeviation19kHz,Outputpower –40°Cto105°C 9 10.8 12 setting:10dBm CW,Deliveredintoa50-Ωload,includingmatching 125°C 10.3 networkasoutlined 38.4kBaud/GFSK,TXdeviation19kHz,Outputpower –40°Cto105°C –4.5 –0.2 4 TXoutputpower, setting:0dBm dBm 433MHz CW,Deliveredintoa50-Ωload,includingmatching 125°C –1.1 networkasoutlined 38.4kBaud/GFSK,TXdeviation19kHz,Outputpower –40°Cto105°C –8 –5.3 –2.5 setting:–5dBm CW,Deliveredintoa50-Ωload,includingmatching 125°C –6.2 networkasoutlined 38.4kBaud/GFSK,TXdeviation19kHz,Outputpower –40°Cto105°C 8 10.4 12 setting:10dBm CW,Deliveredintoa50-Ωload,includingmatching 125°C 9.7 networkasoutlined 38.4kBaud/GFSK,TXdeviation19kHz,Outputpower –40°Cto105°C –4 –0.5 3.5 TXoutputpower, setting:0dBm dBm 868MHz CW,Deliveredintoa50-Ωload,includingmatching 125°C –1.9 networkasoutlined 38.4kBaud/GFSK,TXdeviation19kHz,Outputpower –40°Cto105°C –9 –5 –2.5 setting:–5dBm CW,Deliveredintoa50-Ωload,includingmatching 125°C –7 networkasoutlined 38.4kBaud/GFSK,TXdeviation19kHz,Outputpower –40°Cto105°C 7.5 9.6 12 setting:10dBm CW,Deliveredintoa50-Ωload,includingmatching 125°C 9.4 networkasoutlined 38.4kBaud/GFSK,TXdeviation19kHz,Outputpower –40°Cto105°C –4 –0.3 4 TXoutputpower, setting:0dBm dBm 915MHz CW,Deliveredintoa50-Ωload,includingmatching 125°C –0.9 networkasoutlined 38.4kBaud/GFSK,TXdeviation19kHz,Outputpower –40°Cto105°C –8 –5 –1.5 setting:–5dBm CW,Deliveredintoa50-Ωload,includingmatching 125°C –5.6 networkasoutlined ConductedmeasurementonreferencedesignwithCW –40°Cto105°C –50 Second-order andmaximumoutput-powersettings dBm harmonics,315MHz Note:PAoutputmatchingimpactsharmonicslevel 125°C –53 ConductedmeasurementonreferencedesignwithCW –40°Cto105°C –32 Third-order andmaximumoutput-powersettings dBm harmonics,315MHz Note:PAoutputmatchingimpactsharmonicslevel 125°C –40 12 ElectricalSpecifications Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC11x1-Q1 www.ti.com SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 RFTransmitSectionCharacteristics(continued) V =1.8Vto3.3V,AllvoltagesrefertoGND(unlessotherwisenoted).TypicalvaluesatT =25°C,V =3V.Transmit DD A DD parametersvalidforCC1101andCC1151only. PARAMETER TESTCONDITIONS T MIN TYP MAX UNIT A ConductedmeasurementonreferencedesignwithCW –40°Cto105°C –40 Second-order andmaximumoutputpowersettings dBm harmonics,433MHz Note:PAoutputmatchingimpactsharmonicslevel 125°C –41 ConductedmeasurementonreferencedesignwithCW –40°Cto105°C –26 Third-order andmaximumoutputpowersettings dBm harmonics,433MHz Note:PAoutputmatchingimpactsharmonicslevel 125°C –27 ConductedmeasurementonreferencedesignwithCW –40°Cto105°C –48 Second-order andmaximumoutputpowersettings dBm harmonics,868MHz Note:PAoutputmatchingimpactsharmonicslevel 125°C –44 ConductedmeasurementonreferencedesignwithCW –40°Cto105°C –45 Third-order andmaximumoutputpowersettings dBm harmonics,868MHz Note:PAoutputmatchingimpactsharmonicslevel 125°C –45 ConductedmeasurementonreferencedesignwithCW –40°Cto105°C –50 Second-order andmaximumoutputpowersettings dBm harmonics,915MHz Note:PAoutputmatchingimpactsharmonicslevel 125°C –53 ConductedmeasurementonreferencedesignwithCW –40°Cto105°C –45 Third-order andmaximumoutputpowersettings dBm harmonics,915MHz Note:PAoutputmatchingimpactsharmonicslevel 125°C –46 2.9 Crystal Oscillator Characteristics V =1.8Vto3.3V,T =–40°Cto105°C,withoutforwarderrorcorrection(unlessotherwisenoted).Allvoltagesreferto DD A GND.TypicalvaluesatT =25°C,V =3V. A DD PARAMETER TESTCONDITIONS MIN TYP MAX UNIT DependingontheUHFoperatingfrequencya26-MHzor27-MHzcrystal 26to Referencefrequency MHz shouldbeused. 27 Theacceptablecrystaltolerancedependonthesystemrequirementse.g., Tolerances RX/TXbandwidth,channelspacing,clocksynchronizationbetweenRX/TX ±20 ppm units ESR 100 Ω Measuredonthereferencedesign.Parameterdependsonthecrystalthat Start-uptime 150 µs isused.TimedoesnotincludePORofthedevice 10to Loadcapacitors Simulatedoveroperatingconditions pF 20 2.10 Low-Power RC Oscillator Characteristics V =1.8Vto3.3V,T =–40°Cto105°C,withoutforwarderrorcorrection(unlessotherwisenoted).Allvoltagesreferto DD A GND.TypicalvaluesatT =25°C,V =3V. A DD PARAMETER TESTCONDITIONS MIN TYP MAX UNIT Nominal,calibrated Aftercalibration:f =f /750,f =26MHz 34 34.666 35 kHz frequency RC REF REF Frequencyaccuracyafter ±0.3 % calibration TimetocalibrateRCoscillator,Calibrationiscontinuouslydoneinthe Calibrationtime 2 ms backgroundaslongasthecrystaloscillatorisrunning Copyright©2009–2010,TexasInstrumentsIncorporated ElectricalSpecifications 13 SubmitDocumentationFeedback

CC11x1-Q1 SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 www.ti.com 2.11 Frequency Synthesizer Characteristics V =1.8Vto3.3V,f =26MHz,withoutforwarderrorcorrection(unlessotherwisenoted).AllvoltagesrefertoGND. DD REF TypicalvaluesatT =25°C,V =3V. A DD PARAMETER TESTCONDITIONS T MIN TYP MAX UNIT A Synthesizerfrequency 26-MHzor27-MHzf ,Frequencyresolution REF –40°Cto105°C f /2 Hz resolution isequalforallfrequencybands REF 16 SinglesidebandnoisepowerindBc/Hz Phasenoiseat50-kHz measuredatnominalsupplyoverallfrequency –40°Cto105°C –80 dBc/Hz offset bandsatmaximumpowersetting SinglesidebandnoisepowerindBc/Hz Phasenoiseat100-kHz measuredatnominalsupplyoverallfrequency –40°Cto105°C –85 dBc/Hz offset bandsatmaximumpowersetting SinglesidebandnoisepowerindBc/Hz Phasenoiseat200-kHz measuredatnominalsupplyoverallfrequency –40°Cto105°C –92 dBc/Hz offset bandsatmaximumpowersetting SinglesidebandnoisepowerindBc/Hz Phasenoiseat500-kHz measuredatnominalsupplyoverallfrequency –40°Cto105°C –100 dBc/Hz offset bandsatmaximumpowersetting SinglesidebandnoisepowerindBc/Hz Phasenoiseat1-MHz measuredatnominalsupplyoverallfrequency –40°Cto105°C –100 dBc/Hz offset bandsatmaximumpowersetting TimefromIDLEstatecrystaloscillatorrunning Synthesizerturn-ontime untilarrivingtheRX,FSTXON,orTXstate, –40°Cto105°C 110 µs /hoptime RCoscillatorcalibrationdisabled TimefromIDLEstatecrystaloscillatorrunning Synthesizerturn-ontime untilarrivingtheRX,FSTXON,orTXstate, –40°Cto105°C 850 µs withsynthesizercalibration SynthesizerRX/TX TimetoswitchfromRXtoTX –40°Cto105°C 10 µs settlingtime SynthesizerTX/RX TimetoswitchfromTXtoRX –40°Cto105°C 25 µs settlingtime Synthesizercalibration Manualtriggeredcalibrationbeforeenteringor –40°Cto105°C 18739 f cycles time afterleavingtheRX/TXstate REF 14 ElectricalSpecifications Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC11x1-Q1 www.ti.com SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 2.12 Analog Temperature Sensor Characteristics V =1.8Vto3.3V,T =–40°Cto105°C,withoutforwarderrorcorrection(unlessotherwisenoted).Allvoltagesreferto DD A GND.TypicalvaluesatT =25°C,V =3V.Notethatitisnecessarytowrite0xBFtothePTESTregistertousetheanalog A DD temperaturesensorintheIDLEstate. PARAMETER TESTCONDITIONS MIN TYP MAX UNIT T =–40°C 0.60 0.70 0.80 A T =0°C 0.775 A T =25°C 0.815 A Outputvoltage T =70°C 0.880 V A T =85°C 0.912 A T =105°C 0.88 0.96 1.07 A T =125°C 0.968 A Temperaturecoefficient FittedfromT =–20°Cto80°C 1.6 mV/C A Errorincalculatedtemperature, FromT =–20°Cto80°Cwhenusing2.44mV/°C,after1-point A ±2 °C calibrated calibrationat25°Ctemperature 2.13 Digital Input/Output DC Characteristics V =1.8Vto3.3V,T =–40°Cto105°C,withoutforwarderrorcorrection(unlessotherwisenoted).Allvoltagesreferto DD A GND.TypicalvaluesatT =25°C,V =3V. A DD PARAMETER TESTCONDITIONS MIN TYP MAX UNIT Logic0 0 0.7 Inputvoltage V Logic1 V –0.7 V DD DD Logic0 0 0.5 Outputvoltage V Logic1 V –0.3 V DD DD Logic0,Inputequals0V –50 Inputcurrent nA Logic1,InputequalsVDD 50 2.14 Power-On Reset Characteristics(1) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT Power-upramp-uptime From0Vto3V 1 ms (1) Whenthepowersupplycomplieswiththerequirementsshownhere,properpower-on-resetfunctionalityisassured.Otherwise,thechip shouldbeassumedtohaveunknownstateuntilittransmitsanSRESstrobeovertheSPIinterface.SeePower-OnStartupSequence forfurtherdetails. Copyright©2009–2010,TexasInstrumentsIncorporated ElectricalSpecifications 15 SubmitDocumentationFeedback

CC11x1-Q1 SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 www.ti.com 2.15 SPI Interface Timing MIN TYP MAX UNIT f SCLKfrequency 6 MHz SCLK t Clockhightime 80 ns ch t Clocklowtime 80 ns cl t Setuptime,data(negativeSCLKedge)topositiveedgeonSCLK(1) 80 ns sd t Holdtime,dataafterpositiveedgeonSCLK 50 ns hd t NegativeedgeonSCLKtoCShigh 50 ns ns (1) t appliesbetweenaddressanddatabytes,andbetweendatabytes. sd 2.16 Typical State Transition Timing XOSC 26-MHz PARAMETER PERIODS CRYSTAL IDLEtoRX,nocalibration 2298 88.4µs IDLEtoRX,withcalibration ~21037 809µs IDLEtoTX/FSTXON,nocalibration 2298 88.4µs IDLEtoTX/FSTXON,withcalibration ~21037 809µs TXtoRXswitch 560 21.5µs RXtoTXswitch 250 9.6µs RXorTXtoIDLE,nocalibration 2 0.1µs RXorTXtoIDLE,withcalibration ~18739 721µs Manualcalibration ~18739 721µs 16 ElectricalSpecifications Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC11x1-Q1 www.ti.com SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 3 Detailed Description 3.1 Terminal Assignments RHB PACKAGE (TOPVIEW) E 1 OD1) COUPLVDD2VDD1NDDO2EST_MO (GDOCLK DDDGGTSS 3231302928272625 GND 1 24 NC DCOUPL2 2 23 SI GDO0 (ATEST) 3 22 AGND_GUARD CS 4 21 AVDD_GUARD XOSC_Q1 5 20 RBIAS AVDD_IF 6 19 GND XOSC_Q2 7 18 AVDD_CHP GND 8 17 NC 9 10111213141516 1D2PND3C FNF__NFN RGRFFGR _ _RR _ D D D D D D V V V A A A NC – No internal connection Copyright©2009–2010,TexasInstrumentsIncorporated DetailedDescription 17 SubmitDocumentationFeedback

CC11x1-Q1 SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 www.ti.com Table3-1.TerminalFunctions TERMINAL TYPE DESCRIPTION NO. NAME 1 GND Ground(Analog) Analoggroundconnection PowerInput 2 DCOUPL2 1.6-Vto2-Vdigitalpowersupplyinputfordecoupling (Digital) Digitaloutputpinforgeneraluse: • Testsignals • FIFOstatussignals • ClearChannelIndicator 3 GDO0(ATEST) DigitalI/O • Clockoutput,down-dividedfromXOSC • SerialoutputRXdata • SerialinputTXdata AlsousedasanalogtestI/Oforprototypeandproductiontesting. 4 CS DigitalInput Serialconfigurationinterface,chipselect 5 XOSC_Q1 AnalogI/O Crystaloscillatorpin1,orexternalclockinput 6 AVDD_IF Power(Analog) 1.8-Vto3.6-Vanalogpowersupplyconnection 7 XOSC_Q2 AnalogI/O Crystaloscillatorpin2 8 GND Ground(Analog) Analoggroundconnection 9 AVDD_RF1 Power(Analog) 1.8-Vto3.6-Vanalogpowersupplyconnection 10 GND Ground(Analog) Analoggroundconnection 11 AVDD_RF2 Power(Analog) 1.8-Vto3.6-Vanalogpowersupplyconnection PositiveRFinputsignaltoLNAinreceivemode.PositiveRFoutputsignalfromPAin 12 RF_P RFI/O transmitmode NegativeRFinputsignaltoLNAinreceivemode.NegativeRFoutputsignalfromPAin 13 RF_N RFI/O transmitmode 14 GND Ground(Analog) Analoggroundconnection 15 AVDD_RF3 Power(Analog) 1.8-Vto3.6-Vanalogpowersupplyconnection 16 NC Notconnected 17 NC Notconnected 18 AVDD_CHP Power(Analog) 1.8-Vto3.6-Vanalogpowersupplyconnection 19 GND Ground(Analog) Analoggroundconnection 20 RBIAS AnalogI/O Externalprecisionbiasresistorforreferencecurrent 21 AVDD_GUARD Power(Digital) Powersupplyconnectionfordigitalnoiseisolation 22 AGND_GUARD Ground(Digital) Groundconnectionfordigitalnoiseisolation 23 SI DigitalInput Serialconfigurationinterface,datainput 24 NC Notconnected 25 SCLK DigitalInput Serialconfigurationinterface,clockinput 26 SO(GDO1) DigitalOutput Serialconfigurationinterface,dataoutput.OptionalgeneraloutputpinwhenCSishigh. 27 TEST_MODE DigitalInput GNDenablesandNCdisableson-chipdatascrambling.Internalpullupresistor. Digitaloutputpinforgeneraluse: • Testsignals • FIFOstatussignals 28 GDO2 DigitalOutput • Clearchannelindicator • Clockoutput,down-dividedfromXOSC • SerialoutputRXdata 29 GND Ground(Analog) Analoggroundconnection 30 DVDD1 Power(Digital) 1.8-Vto3.6-VdigitalpowersupplyfordigitalI/Osandfordigitalcorevoltageregulator 31 DVDD2 1.6-Vto1.8-Vdigitalpowersupplyoutputfordigitalcore/decoupling. Outputregulator 32 DCOUPL1 NOTE:ThispinisintendedtosupplyonlytheCC11x1-Q1chip.Itcannotbeusedtoprovide digitalcore supplyvoltagetootherdevices. 18 DetailedDescription Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC11x1-Q1 www.ti.com SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 3.2 Block Diagram A simplified block diagram of CC11x1-Q1 is shown in Figure 3-1. The CC11x1-Q1 devices feature a low intermediate frequency (IF) receiver. The received radio frequency (RF) signal is amplified by the low-noise amplifier (LNA) and down-converted in a quadrature (I and Q) to the IF. At IF, the I/Q signals are digitized by the analog-to-digital converters (ADCs). Automatic gain control (AGC), fine channel filtering,anddemodulationbit/packetsynchronizationisperformeddigitally. The transmitter part of CC11x1-Q1 is based on direct synthesis of the RF frequency. The frequency synthesizer includes a completely on-chip LC voltage-controlled oscillator (VCO) and a 90° phase shifter for generating the I and Q signals, and it is also used for the down-conversion mixers in receive mode. A crystal must be connected to XOSC_Q1 and XOSC_Q2. The crystal oscillator generates the reference frequencyforthesynthesizeraswellastheclocksfortheADCandthedigitalpart. A 4-wire SPI serial interface is used for the register configuration and data buffer access. The digital base band modem includes support for channel configuration, packet handling, Forward Error Correction and databuffering. In the CC1131-Q1 devices, the TX path is not available. In the CC1151-Q1 devices, the RX path is not available. Radio Control ADC or at O LNA dul FIF o X m R ADC De CU SCLK RRFF__NP 090 FSryenqtuheensiczyer FEC / Interleaver Packet Handler gital Interface to M SSCGGOISDD OO(G02D (AOT1E)ST) PA ator FO Di ul FI d X Mo T RC OSC BIAS XOSC RBIAS XOSC_Q1XOSC_Q2 Figure3-1.SimplifiedBlockDiagram CC11x1-Q1featuresalowintermediatefrequency(IF)receiver.ThereceivedRFsignalisamplifiedbythe low-noise amplifier (LNA) and down-converted in quadrature (I and Q) to the IF. At IF, the I/Q signals are digitized by the ADCs. Automatic gain control (AGC), fine channel filtering and demodulation bit/packet synchronizationareperformeddigitally. The transmitter part of CC11x1-Q1 is based on direct synthesis of the RF frequency. The frequency synthesizer includes a completely on-chip LC VCO and a 90° phase shifter for generating the I and Q LO signalstothedown-conversionmixersinreceivemode. A crystal is to be connected to XOSC_Q1 and XOSC_Q2. The crystal oscillator generates the reference frequencyforthesynthesizer,aswellasclocksfortheADCandthedigitalpart. A4-wireSPIserialinterfaceisusedforconfigurationanddatabufferaccess. Thedigitalbasebandincludessupportforchannelconfiguration,packethandling,anddatabuffering. Copyright©2009–2010,TexasInstrumentsIncorporated DetailedDescription 19 SubmitDocumentationFeedback

CC11x1-Q1 SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 www.ti.com 3.3 Application Circuit Only a few external components are required for using the CC11x1-Q1. The recommended application circuits are shown in Figure 3-2 and Figure 3-3. Typical values for the external components are given in Table3-2. BiasResistor ThebiasresistorR171isusedtosetanaccuratebiascurrent. BalunandRFMatching The components between the RF_N/RF_P pins and the point where the two signals are joined together (C131, C122, L121, and L131 for the 315/433-MHz reference design [5], or L101, L111, C111, L121, C131, C122, and L131 for the 868/915-MHz reference design [6]) form a balun that converts the differential RF signal on CC11x1-Q1 to a single-ended RF signal. C125 is needed for dc blocking. Together with an appropriate LC network, the balun components also transform the impedance to match a 50-Ω antenna or cable. Suggested values for 315 MHz, 433 MHz, and 868/915 MHz are listed in Table3-2. Crystal The reference oscillator uses an external 26-MHz or 27-MHz crystal with two loading capacitors (C81 and C101).SeeSection3.22fordetails. AdditionalFiltering Additional external components (e.g., an RF SAW filter) may be used to improve the performance in specificapplications. PowerSupplyDecoupling The power supply must be properly decoupled close to the supply pins. A short and proper GND connectionisalsoessentialforthefunctionalityofthedevice. 20 DetailedDescription Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC11x1-Q1 www.ti.com SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 R171 VDD C31 SI NC 24 SI 23 RD 22 RD 21 AS 20 ND 19 HP 18 NC 17 A(n5t0enWn)a SO (GSDCOL1K) 2265 SSOCL (KGDO1) AGND_GUA AVDD_GUA RBI G AVDD_CAVDD_RNFC3 1165 C131 27 NC/GND GND 14 L131 L122 L123 C125 GDO2 28 GDO2 RF_N 13 29 GND CC11x1-Q1 RF_P 12 30 DVDD1 AVDD_RF2 11 C122 C123 C124 C21 31 DVDD2 GND 10 L121 32 DCOUPL1 ST) AVDD_RF1 9 GND DCOUPL2 GDO0(ATE CS XOSC_Q1 AVDD_IF XOSC_Q2 GND C121 C51 1 2 3 4 5 6 7 8 C41 GDO0 XTAL CS C81 C101 Figure3-2.TypicalApplicationCircuitfor315MHz/433MHz R171 VDD SI C31 NC 24 SI 23 RD 22 RD 21 AS 20 ND 19 HP 18 NC 17 Antenna SO (GSDCOL1K) 2265 SSOCL (KGDO1) AGND_GUA AVDD_GUA RBI G AVDD_CAVDD_RNFC3 1156 L111 CL113311 (50W) 27 NC/GND GND 14 L122 L123 C125 GDO2 28 GDO2 RF_N 13 C111 29 GND CC11x1-Q1 RF_P 12 C123 30 DVDD1 AVDD_RF2 11 L125 C21 31 DVDD2 GND 10 L101 C122 C126 32 DCOUPL1 ST) AVDD_RF1 9 L121 See Note A C51 GND DCOUPL2 GDO0(ATE CS XOSC_Q1 AVDD_IF XOSC_Q2 GND C121 1 2 3 4 5 6 7 8 C41 GDO0 XTAL CS C81 C101 A. C126andL125maybeaddedtobuildanoptionalfiltertoreduceemissionat699MHz. Figure3-3.TypicalApplicationCircuitfor868MHz/915MHz Copyright©2009–2010,TexasInstrumentsIncorporated DetailedDescription 21 SubmitDocumentationFeedback

CC11x1-Q1 SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 www.ti.com Table3-2.BillofMaterialsfortheApplicationCircuit COMPONENT VALUEAT315MHz VALUEAT433MHz VALUEAT868MHz VALUEAT915MHz C21 100nF±10%,0402X5R C31 100nF±10%,0402X5R C41 100nF±10%,0402X5R C51 100nF±10%,0402X5R C81 27pF±5%,0402NP0 C101 27pF±5%,0402NP0 C111 — — 1pF±0.25pF,0402NP0 1pF±0.25pF,0402NP0 C121 220pF±5%,0402NP0 220pF±5%,0402NP0 100pF±5%,0402NP0 100pF±5%,0402NP0 C122 6.8pF±0.5pF,0402NP0 3.9pF±0.25pF,0402NP0 1.5pF±0.25pF,0402NP0 1.5pF±0.25pF,0402NP0 C123 12pF±5%,0402NP0 8.2pF±0.5pF,0402NP0 3.3pF±0.25pF,0402NP0 3.3pF±0.25pF,0402NP0 C124 6.8pF±0.5pF,0402NP0 5.6pF±0.5pF,0402NP0 — — C125 220pF±5%,0402NP0 220pF±5%,0402NP0 100pF±5%,0402NP0 100pF±5%,0402NP0 C126 — — 47pF±5%,0402NP0 — C131 6.8pF±0.5pF,0402NP0 3.9pF±0.25pF,0402NP0 1.5pF±0.25pF,0402NP0 1.5pF±0.25pF,0402NP0 12nH±5%,0402/muRata 12nH±5%,0402/muRata L101 — — LQW15A LQW15A 12nH±5%,0402/muRata 12nH±5%,0402/muRata L111 — — LQW14A LQW15A 33nH±5%,0402/muRata 27nH±5%,0402/muRata 18nH±5%,0402/muRata 18nH±5%,0402/muRata L121 LQW15A LQW15A LQW15A LQW15A 18nH±5%,0402/muRata 22nH±5%,0402/muRata 12nH±5%,0402/muRata 12nH±5%,0402/muRata L122 LQW15A LQW15A LQW14A LQW14A 33nH±5%,0402/muRata 27nH±5%,0402/muRata 12nH±5%,0402/muRata 12nH±5%,0402/muRata L123 LQW15A LQW15A LQW15A LQW15A 3.3nH±5%,0402/muRata L125 — — — LQW15A 33nH±5%,0402/muRata 27nH±5%,0402/muRata 18nH±5%,0402/muRata 18nH±5%,0402/muRata L131 LQW15A LQW15A LQW15A LQW15A R171 56kΩ±1%,0402 XTAL 26MHz 27MHz 27MHz 26MHz 3.4 Configuration Overview CC11x1-Q1 can be configured to achieve optimum performance for many different applications. Configuration is done using the SPI interface. The following key parameters can be programmed: <br/> • Power-down/power-upmode • RFoutputpower • Crystaloscillatorpowerup/powerdown • Databufferingwithseparate64-byte • Receive/transmitmode receiveandtransmitFIFOs • RFchannelselection • Packetradiohardwaresupport • Datarate • Forwarderrorcorrection(FEC)with interleaving • Modulationformat • Datawhitening • RXchannelfilterbandwidth • Wake-on-radio(WOR) DetailsofeachconfigurationregisterareinSection4. Figure 3-4 shows a simplified state diagram that explains the main CC11x1-Q1 states, together with typical usage and current consumption. For detailed information on controlling the CC11x1-Q1 state machine,andacompletestatediagram,seeSection3.15. 22 DetailedDescription Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC11x1-Q1 www.ti.com SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 Lowest power mode. Most register values are retained. Sleep Typ current consumption: 700 nA SIDLE SPWDorwake-on-radio(WOR) (2 µAwhen wake-on-radio (WOR) is enabled) Default state when the radio is not receiving or transmitting. Typ current consumption: 1.8 mA CSn=0 IDLE SXOFF SCAL Used for calibrating frequency synthesizer up front (entering Manual CSn=0 Allregistervaluesare receive or transmit mode can frequency Crystal tThreann sbitei odnoanl es tmatoer.e quickly). scyanlitbhreastiizoenr SRXorSTXorSFSTXONorwake-on-radio(WOR) oscillatoroff rceotnasinuemdp.tTioynp:c1u6r0reµnAt Typ current consumption: 9 mA Frequency Frequencysynthesizeristurnedon,canoptionallybe synthesizerstartup, calibrated,andthensettlestothecorrectfrequency. SFSTXON optionalcalibration, Transitionalstate.Typcurrentconsumption:9 mA Frequency synthesizer is on, settling ready to start transmitting. Transmission starts very Frequency quickly after receiving the synthesizeron STX command strobe. Typ current consumption: 9 mA STX SRXorwake-on-radio(WOR) STX TXOFF_MODE=01 SFSTXONorRXOFF_MODE=01 Typcurrentconsumption: 12.2 mAat-5dBmoutput STXorRXOFF_MODE=10 Typcurrent 14.6 mAat0dBmoutput Transmitmode Receivemode consumption: 15.5 mA 29.5 mAat+10dBmoutput SRXorTXOFF_MODE=11 TXOFF_MODE=00 RXOFF_MODE=00 Optionaltransitionalstate. Typ current consumption: 8 mA InFIFO-basedmodes, InFIFO-basedmodes, transmissionisturnedoffand receptionisturnedoffandthis thisstateenterediftheTX TXFIFO Optionalfreq. RXFIFO stateenterediftheRXFIFO FIFObecomesemptyinthe underflow synth.calibration overflow overflows.Typcurrent middleofapacket.Typ consumption:1.8mA currentconsumption:1.8mA SFTX SFRX IDLE Figure3-4.SimplifiedStateDiagram,WithTypicalCurrentConsumptionat1.2-kBaudDataRateand MDMCFG2.DEM_DCFILT_OFF=1(CurrentOptimized),FrequencyBand=315MHz 3.5 Configuration Software CC11x1-Q1 can be configured using the SmartRF® Studio software. The SmartRF Studio software is highly recommended for obtaining optimum register settings and for evaluating performance and functionality.AscreenshotoftheSmartRFStudiouserinterfaceforCC11x1-Q1isshowninFigure3-5. After chip reset, all the registers have default values as shown in Section 4. The optimum register setting might differ from the default value. Therefore, after a reset, all registers that are different from the default value need to be programmed through the SPI interface. For the CC11x1-Q1 device, the settings of the CC1101arevalid. Copyright©2009–2010,TexasInstrumentsIncorporated DetailedDescription 23 SubmitDocumentationFeedback

CC11x1-Q1 SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 www.ti.com Figure3-5.SmartRFStudioUserInterface 3.6 4-Wire Serial Configuration and Data Interface CC11x1-Q1 is configured via a simple 4-wire SPI-compatible interface (SI, SO, SCLK, and CS) where CC11x1-Q1 is the slave. This interface is also used to read and write buffered data. All transfers on the SPIinterfacearedonemostsignificantbitfirst. All transactions on the SPI interface start with a header byte containing a R/W bit, a burst access bit (B), anda6-bitaddress(A toA ). 5 0 The CS pin must be kept low during transfers on the SPI bus. If CS goes high during the transfer of a headerbyteorduringread/writefrom/toaregister,thetransferiscanceled.Thetimingfortheaddressand datatransferontheSPIinterfaceisshowninFigure3-6withreferencetoSection2.15. When CS is pulled low, the MCU must wait until CC11x1-Q1 SO pin goes low before starting to transfer the header byte. This indicates that the crystal is running. Unless the chip was in the SLEEP or XOFF states,theSOpingoeslowimmediatelyaftertakingCSlow. 24 DetailedDescription Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC11x1-Q1 www.ti.com SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 Note: SeeSection2.15forSPIinterfacetimingspecifications. Figure3-6.ConfigurationRegistersWriteandReadOperations 3.6.1 Chip Status Byte When the header byte, data byte, or command strobe is sent on the SPI interface, the chip status byte is sent by the CC11x1-Q1 on the SO pin. The status byte contains key status signals, useful for the MCU. The first bit, s7, is the CHIP_RDYn signal. This signal must go low before the first positive edge of SCLK. TheCHIP_RDYnsignalindicatesthatthecrystalisrunning. The STATE value comprises bits 6, 5, and 4. This value reflects the state of the chip. The XOSC and power to the digital core is on in the IDLE state, but all other modules are in power down. The frequency and channel configuration should be updated only when the chip is in this state. The RX state is active whenthechipisinreceivemode.Likewise,TXisactivewhenthechipistransmitting. The last four bits (3:0) in the status byte contain FIFO_BYTES_AVAILABLE. For read operations (the R/W bit in the header byte is set to 1), the FIFO_BYTES_AVAILABLE field contains the number of bytes available for reading from the RX FIFO. For write operations (the R/W bit in the header byte is set to 0), the FIFO_BYTES_AVAILABLE field contains the number of bytes that can be written to the TX FIFO. WhenFIFO_BYTES_AVAILABLE=15,15ormorebytesareavailable/free. Table3-3givesastatusbytesummary. Table3-3.StatusByteSummary BITS NAME DESCRIPTION 7 CHIP_RDYn Stayshighuntilpowerandcrystalhavestabilized.ShouldalwaysbelowwhenusingtheSPI interface. 06:04 STATE[2:0] Indicatesthecurrentmainstatemachinemode Value State Description IDLEstate 0 IDLE (Alsoreportedforsometransitionalstatesinsteadof SETTLINGorCALIBRATE) 1 RX Receivemode 10 TX Transmitmode 11 FSTXON FastTXready 100 CALIBRATE Frequencysynthesizercalibrationisrunning 101 SETTLING PLLissettling RXFIFOhasoverflowed.Readoutanyusefuldata,then 110 RXFIFO_OVERFLOW flushtheFIFOwithSFRX. 111 TXFIFO_UNDERFLOW TXFIFOhasunderflowed.AcknowledgewithSFTX. 03:00 FIFO_BYTES_AVAILABLE[3:0] ThenumberofbytesavailableintheRXFIFOorfreebytesintheTXFIFO Copyright©2009–2010,TexasInstrumentsIncorporated DetailedDescription 25 SubmitDocumentationFeedback

CC11x1-Q1 SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 www.ti.com 3.6.2 Register Access TheconfigurationregistersontheCC11x1-Q1arelocatedonSPIaddressesfrom0x00to0x2E.Table4-2 lists all configuration registers. SmartRF Studio should be used to generate optimum register settings. The detailed description of each register is found in Section 4.2. All configuration registers can be both written to and read. The R/W bit controls if the register should be written to or read. When writing to registers, the status byte is sent on the SO pin each time a header byte or data byte is transmitted on the SI pin. When reading from registers, the status byte is sent on the SO pin each time a header byte is transmitted on the SIpin. Registers with consecutive addresses can be accessed efficiently by setting the burst bit (B) in the header byte. The address bits (A5 to A0) set the start address in an internal address counter. This counter is incremented by one each new byte (every 8 clock pulses). The burst access is either a read or a write accessandmustbeterminatedbysettingCShigh. For register addresses in the range 0x30 to 0x3D, the burst bit is used to select between status registers, burst bit is one, and command strobes, burst bit is zero (see 10.4 below). Because of this, burst access is not available for status registers and they must be accessed one at a time. The status registers can only beread. 3.6.3 SPI Read When reading register fields over the SPI interface while the register fields are updated by the radio hardware (e.g., MARCSTATE or TXBYTES), there is a small, but finite, probability that a single read from the register is being corrupt. As an example, the probability of any single read from TXBYTES being corrupt, assuming the maximum data rate is used, is approximately 80 ppm. See the CC1101 errata notes (SWRZ020)formoredetails. 3.6.4 Command Strobes Command strobes may be viewed as single byte instructions to CC11x1-Q1. By addressing a command stroberegister,internalsequencesarestarted.Thesecommandsareusedtodisablethecrystaloscillator, enablereceivemode,enablewake-on-radioetc.The13commandstrobesarelistedinTable4-1. The command strobe registers are accessed by transferring a single header byte (no data is being transferred). That is, only the R/W bit, the burst access bit (set to 0), and the six address bits (in the range 0x30 through 0x3D) are written. The R/W bit can be either one or zero and determines how the FIFO_BYTES_AVAILABLEfieldinthestatusbyteshouldbeinterpreted. Whenwritingcommandstrobes,thestatusbyteissentontheSOpin. A command strobe may be followed by any other SPI access without pulling CS high. However, if an SRES strobe is being issued, wait for SO to go low again before the next header byte is issued, as shown in Figure 3-7. The command strobes are executed immediately, with the exception of the SPWD and the SXOFFstrobesthatareexecutedwhenCSgoeshigh. CSn SO SI HeaderSRES HeaderAddr Data Figure3-7.SRESCommandStrobe 3.6.5 FIFO Access The 64-byte TX FIFO and the 64-byte RX FIFO are accessed through the 0x3F address. When the R/W bitiszero,theTXFIFOisaccessed,andtheRXFIFOisaccessedwhentheR/Wbitisone. TheTXFIFOiswrite-only,whiletheRXFIFOisread-only. 26 DetailedDescription Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC11x1-Q1 www.ti.com SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 The burst bit is used to determine if the FIFO access is a single byte access or a burst access. The single byte access method expects a header byte with the burst bit set to zero and one data byte. After the data byte a new header byte is expected; hence, CS can remain low. The burst access method expects one headerbyteandthenconsecutivedatabytesuntilterminatingtheaccessbysettingCShigh. ThefollowingheaderbytesaccesstheFIFOs: • 0x3F:SinglebyteaccesstoTXFIFO • 0x7F:BurstaccesstoTXFIFO • 0xBF:SinglebyteaccesstoRXFIFO • 0xFF:BurstaccesstoRXFIFO When writing to the TX FIFO, the status byte (see Section 3.6.1) is output for each new data byte on SO, as shown in Figure 3-6. This status byte can be used to detect TX FIFO underflow while writing data to the TX FIFO. Note that the status byte contains the number of bytes free before writing the byte in progress to the TX FIFO. When the last byte that fits in the TX FIFO is transmitted on SI, the status byte receivedconcurrentlyonSOindicatesthatonebyteisfreeintheTXFIFO. The TX FIFO may be flushed by issuing a SFTX command strobe. Similarly, a SFRX command strobe flushes the RX FIFO. A SFTX or SFRX command strobe can only be issued in the IDLE, TXFIFO_UNDERFLOW, or RXFIFO_OVERFLOW states. Both FIFOs are flushed when going to the SLEEPstate. Figure3-8givesabriefoverviewofdifferentregisteraccesstypespossible. Figure3-8.RegisterAccessTypes 3.6.6 PATABLE Access The 0x3E address is used to access the PATABLE, which is used for selecting PA power control settings. The SPI expects up to eight data bytes after receiving the address. By programming the PATABLE, controlled PA power ramp-up and ramp-down can be achieved, as well as ASK modulation shaping for reducedbandwidth.SeeSmartRFStudioforrecommendedshaping/PArampingsequences. SeeSection3.20fordetailsonoutputpowerprogramming. ThePATABLEisan8-bytetablethatdefinesthePAcontrolsettingstouseforeachoftheeightPApower values (selected by the 3-bit value FREND0.PA_POWER). The table is written and read from the lowest setting (0) to the highest (7), one byte at a time. An index counter is used to control the access to the table. This counter is incremented each time a byte is read or written to the table, and set to the lowest indexwhenCSishigh.Whenthehighestvalueisreachedthecounterrestartsatzero. The access to the PATABLE is either single byte or burst access depending on the burst bit. When using burst access the index counter counts up; when reaching 7 the counter restarts at 0. The R/W bit controls whethertheaccessisareadorawriteaccess. If one byte is written to the PATABLE and this value is to be read out then CS must be set high before the readaccesstosettheindexcounterbacktozero. Note that the content of the PATABLE is lost when entering the SLEEP state, except for the first byte (index0). Copyright©2009–2010,TexasInstrumentsIncorporated DetailedDescription 27 SubmitDocumentationFeedback

CC11x1-Q1 SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 www.ti.com 3.7 Microcontroller Interface and Pin Configuration Inatypicalsystem,CC11x1-Q1interfacestoamicrocontroller.Thismicrocontrollermustbeableto: • ProgramCC11x1-Q1intodifferentmodes • Readandwritebuffereddata • Readbackstatusinformationviathe4-wireSPI-busconfigurationinterface(SI,SO,SCLKandCS). 3.7.1 Configuration Interface The microcontroller uses four I/O pins for the SPI configuration interface (SI, SO, SCLK and CS). The SPI isdescribedinSection3.6. 3.7.2 General Control and Status Pins The CC11x1-Q1 has two dedicated configurable pins (GDO0 and GDO2) and one shared pin (GDO1) that can output internal status information useful for control software. These pins can be used to generate interrupts on the MCU. See Section 3.25 for more details on the signals that can be programmed. GDO1 is shared with the SO pin in the SPI interface. The default setting for GDO1/SO is 3-state output. By selecting any other of the programming options, the GDO1/SO pin becomes a generic pin. When CS is low,thepinfunctionsasanormalSOpin. In the synchronous and asynchronous serial modes, the GDO0 pin is used as a serial TX data input pin whileintransmitmode. The GDO0 pin can also be used for an on-chip analog temperature sensor. By measuring the voltage on theGDO0pinwithanexternalADC,thetemperaturecanbecalculated.Specificationsforthetemperature sensorarefoundinSection2.12. With default PTEST register setting (0x7F) the temperature sensor output is available only when the frequency synthesizer is enabled (e.g., the MANCAL, FSTXON, RX, and TX states). It is necessary to write 0xBF to the PTEST register to use the analog temperature sensor in the IDLE state. Before leaving theIDLEstate,thePTESTregistershouldberestoredtoitsdefaultvalue(0x7F). 3.7.3 Optional Radio-Control Feature The CC11x1-Q1 has an optional way of controlling the radio by reusing SI, SCLK, and CS from the SPI interface.Thisallowssimplethree-pincontrolofthemajorstatesoftheradio:SLEEP,IDLE,RX,andTX. ThisoptionalfunctionalityisenabledwiththeMCSM0.PIN_CTRL_ENconfigurationbit. State changes are commanded as follows: When CS is high, the SI and SCLK is set to the desired state according to Table 3-4. When CS goes low, the state of SI and SCLK is latched and a command strobe is generated internally according to the pin configuration. It is only possible to change state with this functionality. That means that, for instance, RX is not restarted if SI and SCLK are set to RX and CS toggles.WhenCSislow,theSIandSCLKhasnormalSPIfunctionality. All pin control command strobes are executed immediately, except the SPWD strobe, which is delayed untilCSgoeshigh. Table3-4.OptionalPinControlCoding CS SCLK SI FUNCTION 1 X X ChipunaffectedbySCLK/SI ↓ 0 0 GeneratesSPWDstrobe ↓ 0 1 GeneratesSTXstrobe ↓ 1 0 GeneratesSIDLEstrobe ↓ 1 1 GeneratesSRXstrobe 0 SPImode SPImode SPImode(wakesupintoIDLEifinSLEEP/XOFF) 28 DetailedDescription Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC11x1-Q1 www.ti.com SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 3.8 Data Rate Programming The data rate used when transmitting, or the data rate expected in receive is programmed by the MDMCFG3.DRATE_M and the MDMCFG4.DRATE_E configuration registers. The data rate is given by theformulabelow.Astheformulashows,theprogrammeddataratedependsonthecrystalfrequency. (1) Thefollowingapproachcanbeusedtofindsuitablevaluesforagivendatarate: DRATE_E=êêëêlog2ççèæRDfAXTOAS´C220÷÷øöúúûú DRATE_M= RDATA´228 -256 fXOSC´2DRATE_E (2) If DRATE_M is rounded to the nearest integer and becomes 256, increment DRATE_E and use DRATE_M=0. Thedataratecanbesetfrom1.2kBaudto500kBaudwiththeminimumstepsizeshowninTable3-5. Table3-5.DataRateStepSize DATARATE(kBaud) DATARATE STEPSIZE MINIMUM TYPICAL MAXIMUM (kBaud) 0.8 1.2/2.4 3.17 0.0062 3.17 4.8 6.35 0.0124 6.35 9.6 12.7 0.0248 12.7 19.6 25.4 0.0496 25.4 38.4 50.8 0.0992 50.8 76.8 101.6 0.1984 101.6 153.6 203.1 0.3967 203.1 250 406.3 0.7935 3.9 Receiver Channel Filter Bandwidth To meet different channel width requirements, the receiver channel filter is programmable. The MDMCFG4.CHANBW_E and MDMCFG4.CHANBW_M configuration registers control the receiver channel filter bandwidth, which scales with the crystal oscillator frequency. Equation 3 gives the relation between theregistersettingsandthechannelfilterbandwidth: f BW = XOSC channel 8 × (4 + CHANBW_M) × 2CHANBW_E (3) TheCC11x1-Q1supportsthechannelfilterbandwidthsshowninTable3-6. Copyright©2009–2010,TexasInstrumentsIncorporated DetailedDescription 29 SubmitDocumentationFeedback

CC11x1-Q1 SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 www.ti.com Table3-6.ChannelFilterBandwidths(kHz)(Assuminga26-MHzCrystal) MDMCFG4. MDMCFG4.CHANBW_E CHANBW_M 00 01 10 11 00 812 406 203 102 01 650 325 162 81 10 541 270 135 68 11 464 232 116 58 For best performance, the channel filter bandwidth should be selected so that the signal bandwidth occupies at most 80% of the channel filter bandwidth. The channel center tolerance due to crystal accuracyshouldalsobesubtractedfromthesignalbandwidth,asshowninthefollowingexample. With the channel filter bandwidth set to 500 kHz, the signal should stay within 80% of 500 kHz, which is 400 kHz. Assuming 915-MHz frequency and ±20-ppm frequency uncertainty for both the transmitting device and the receiving device, the total frequency uncertainty is ±40 ppm of 915 MHz, which is ±37 kHz. If the whole transmitted signal bandwidth is to be received within 400 kHz, the transmitted signal bandwidthshouldbemaximum400kHz– (2 ×37kHz),whichis326kHz. 3.10 Demodulator, Symbol Synchronizer, and Data Decision CC11x1-Q1 contains an advanced and highly configurable demodulator. Channel filtering and frequency offset compensation are performed digitally. To generate the RSSI level (see Section 3.13.3 for more information) the signal level in the channel is estimated. Data filtering is also included for enhanced performance. 3.10.1 Frequency Offset Compensation When using 2-FSK, GFSK, or MSK modulation, the demodulator compensates for the offset between the transmitter and receiver frequency, within certain limits, by estimating the center of the received data. This value is available in the FREQEST status register. Writing the value from FREQEST into FSCTRL0.FREQOFF the frequency synthesizer is automatically adjusted according to the estimated frequencyoffset. The tracking range of the algorithm is selectable as fractions of the channel bandwidth with the FOCCFG.FOC_LIMITconfigurationregister. If the FOCCFG.FOC_BS_CS_GATE bit is set, the offset compensator freezes until carrier sense asserts. ThismaybeusefulwhentheradioisinRXforlongperiodswithnotraffic,becausethealgorithmmaydrift totheboundarieswhentryingtotracknoise. The tracking loop has two gain factors, which affect the settling time and noise sensitivity of the algorithm. FOCCFG.FOC_PRE_K sets the gain before the sync word is detected, and FOCCFG.FOC_POST_K selectsthegainafterthesyncwordhasbeenfound. NOTE FrequencyoffsetcompensationisnotsupportedforASKorOOKmodulation. 3.10.2 Bit Synchronization The bit synchronization algorithm extracts the clock from the incoming symbols. The algorithm requires that the expected data rate is programmed as described in Section 3.8. Resynchronization is performed continuouslytoadjustforerrorintheincomingsymbolrate. 3.10.3 Byte Synchronization Byte synchronization is achieved by a continuous sync word search. The sync word is a 16-bit configurable field (can be repeated to get a 32 bit) that is automatically inserted at the start of the packet 30 DetailedDescription Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC11x1-Q1 www.ti.com SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 by the modulator in transmit mode. The demodulator uses this field to find the byte boundaries in the stream of bits. The sync word also functions as a system identifier, because only packets with the correct predefined sync word are received if the sync word detection in RX is enabled in register MDMCFG2 (see Section 3.13.1). The sync word detector correlates against the user-configured 16- or 32-bit sync word. The correlation threshold can be set to 15/16, 16/16, or 30/32 bits match. The sync word can be further qualified using the preamble quality indicator mechanism described below and/or a carrier sense condition.ThesyncwordisconfiguredthroughtheSYNC1andSYNC0registers. To make false detections of sync words less likely, a mechanism called preamble quality indication (PQI) can be used to qualify the sync word. A threshold value for the preamble quality must be exceeded in orderforadetectedsyncwordtobeaccepted.SeeSection3.13.2formoredetails. 3.11 Packet Handling Hardware Support TheCC11x1-Q1hasbuilt-inhardwaresupportforpacketorientedradioprotocols. In transmit mode, the packet handler can be configured to add the following elements to the packet stored intheTXFIFO: • Aprogrammablenumberofpreamblebytes • Atwobytesynchronization(sync)word.Canbeduplicatedtogivea4-bytesyncword(recommended). Itisnotpossibletoinsertonlypreambleorinsertonlyasyncword. • ACRCchecksumcomputedoverthedatafield. The recommended setting is 4-byte preamble and 4-byte sync word, except for 500 kBaud data rate wheretherecommendedpreamblelengthis8bytes. Inaddition,thefollowingcanbeimplementedonthedatafieldandtheoptional2-byteCRCchecksum: • WhiteningofthedatawithaPN9sequence. • Forwarderrorcorrectionbytheuseofinterleavingandcodingofthedata(convolutionalcoding) In receive mode, the packet handling support deconstructs the data packet by implementing the following (ifenabled): • Preambledetection • Syncworddetection • CRCcomputationandCRCcheck • Onebyteaddresscheck • Packetlengthcheck(lengthbytecheckedagainstaprogrammablemaximumlength) • Dewhitening • Deinterleavinganddecoding Optionally, two status bytes (see Table 3-7 and Table 3-8) with RSSI value, Link Quality Indication, and CRCstatuscanbeappendedintheRXFIFO. Table3-7.ReceivedPacketStatusByte1(FirstByteAppendedAfterData) BIT FIELDNAME DESCRIPTION 7:0 RSSI RSSIvalue Table3-8.ReceivedPacketStatusByte2(SecondByteAppendedAfterData) BIT FIELDNAME DESCRIPTION 7 CRC_OK 1:CRCforreceiveddataOK(orCRCdisabled) 0:CRCerrorinreceiveddata 6:0 LQI Indicatingthelinkquality Copyright©2009–2010,TexasInstrumentsIncorporated DetailedDescription 31 SubmitDocumentationFeedback

CC11x1-Q1 SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 www.ti.com NOTE Register fields that control the packet handling features should be altered only when CC11x1-Q1isintheIDLEstate. 3.11.1 Data Whitening Fromaradioperspective,theidealover-the-airdataarerandomanddcfree.Thisresultsinthesmoothest power distribution over the occupied bandwidth. This also gives the regulation loops in the receiver uniformoperationconditions(nodatadependencies). Real-world data often contain long sequences of zeros and ones. Performance can then be improved by whitening the data before transmitting, and dewhitening the data in the receiver. With CC11x1-Q1, this can be done automatically by setting PKTCTRL0.WHITE_DATA = 1. All data, except the preamble and the sync word, are then XORed with a 9-bit pseudo-random (PN9) sequence before being transmitted, as shown in Figure 3-9. At the receiver end, the data are XORed with the same pseudo-random sequence. This way, the whitening is reversed, and the original data appear in the receiver. The PN9 sequence is initializedtoallones. Figure3-9.DataWhiteninginTXMode 3.11.2 Packet Format Theformatofthedatapacketcanbeconfiguredandconsistsofthefollowingitems(seeFigure3-10): • Preamble • Synchronizationword • Optionallengthbyte • Optionaladdressbyte • Payload • Optional2-byteCRC 32 DetailedDescription Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC11x1-Q1 www.ti.com SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 Figure3-10.PacketFormat The preamble pattern is an alternating sequence of ones and zeros (10101010…). The minimum length of the preamble is programmable. When enabling TX, the modulator starts transmitting the preamble. When the programmed number of preamble bytes has been transmitted, the modulator sends the sync word and then data from the TX FIFO if data is available. If the TX FIFO is empty, the modulator continues to send preamble bytes until the first byte is written to the TX FIFO. The modulator then sends the sync word and then the data bytes. The number of preamble bytes is programmed with the MDMCFG1.NUM_PREAMBLEvalue. The synchronization word is a two-byte value set in the SYNC1 and SYNC0 registers. The sync word provides byte synchronization of the incoming packet. A one-byte synch word can be emulated by setting the SYNC1 value to the preamble pattern. It is also possible to emulate a 32-bit sync word by using MDMCFG2.SYNC_MODEsetto3or7.Thesyncwordisthenrepeatedtwice. CC11x1-Q1supportsbothconstantpacketlengthprotocolsandvariablelengthprotocols.Variableorfixed packet length mode can be used for packets up to 255 bytes. For longer packets, infinite packet length modemustbeused. Fixed packet length mode is selected by setting PKTCTRL0.LENGTH_CONFIG = 0. The desired packet lengthissetbythePKTLENregister. In variable packet length mode, PKTCTRL0.LENGTH_CONFIG = 1, the packet length is configured by the first byte after the sync word. The packet length is defined as the payload data, excluding the length byte andtheoptionalCRC.ThePKTLENregisterisusedtosetthemaximumpacketlengthallowedinRX.Any packetreceivedwithalengthbytewithavaluegreaterthanPKTLENisdiscarded. With PKTCTRL0.LENGTH_CONFIG = 2, the packet length is set to infinite, and transmission and reception continues until turned off manually. As described in the next section, this can be used to support packet formats with different length configuration than natively supported by CC11x1-Q1. One should make sure that TX mode is not turned off during the transmission of the first half of any byte. Refer to the erratanotesformoredetails. NOTE The minimum packet length supported (excluding the optional length byte and CRC) is one byteofpayloaddata. 3.11.2.1 ArbitraryLengthFieldConfiguration The packet length register, PKTLEN, can be reprogrammed during receive and transmit. In combination with fixed packet length mode (PKTCTRL0.LENGTH_CONFIG = 0) this opens the possibility to have a different length field configuration than supported for variable length packets (in variable packet length modethelengthbyteisthefirstbyteafterthesyncword).Atthestartofreception,thepacketlengthisset to a large value. The MCU reads out enough bytes to interpret the length field in the packet. Then the PKTLEN value is set according to this value. The end of packet occurs when the byte counter in the packet handler is equal to the PKTLEN register. Thus, the MCU must be able to program the correct length,beforetheinternalcounterreachesthepacketlength. Copyright©2009–2010,TexasInstrumentsIncorporated DetailedDescription 33 SubmitDocumentationFeedback

CC11x1-Q1 SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 www.ti.com 3.11.2.2 PacketLengthGreaterThan255 Also the packet automation control register, PKTCTRL0, can be reprogrammed during TX and RX. This opensthepossibilitytotransmitandreceivepacketsthatarelongerthan256bytesandstillbeabletouse the packet handling hardware support. At the start of the packet, the infinite packet length mode (PKTCTRL0.LENGTH_CONFIG = 2) must be active. On the TX side, the PKTLEN register is set to mod(length, 256). On the RX side the MCU reads out enough bytes to interpret the length field in the packet and sets the PKTLEN register to mod(length, 256). When less than 256 bytes remain of the packet, the MCU disables infinite packet length mode and activates fixed packet length mode. When the internal byte counter reaches the PKTLEN value, the transmission or reception ends (the radio enters the state determined by TXOFF_MODE or RXOFF_MODE). Automatic CRC appending/checking can also be used(bysettingPKTCTRL0.CRC_EN=1). When for example a 600-byte packet is to be transmitted, the MCU should do the following (see also Figure3-11). 1. SetPKTCTRL0.LENGTH_CONFIG=2. 2. PreprogramthePKTLENregistertomod(600,256)=88. 3. Transmitatleast345bytes(600– 255),forexamplebyfillingthe64-byteTXFIFOsixtimes(384 bytestransmitted). 4. SetPKTCTRL0.LENGTH_CONFIG=0. 5. Thetransmissionendswhenthepacketcounterreaches88.Atotalof600bytesaretransmitted. Figure3-11.PacketLengthGreaterThan255 3.11.3 Packet Filtering in Receive Mode CC11x1-Q1 supports three different types of packet filtering: address filtering, maximum length filtering, andCRCfiltering. 3.11.3.1 AddressFiltering Setting PKTCTRL1.ADR_CHK to any other value than zero enables the packet address filter. The packet handler engine compares the destination address byte in the packet with the programmed node address in the ADDR register and the 0x00 broadcast address when PKTCTRL1.ADR_CHK = 10 or both 0x00 and 0xFF broadcast addresses when PKTCTRL1.ADR_CHK = 11. If the received address matches a valid address, the packet is received and written into the RX FIFO. If the address match fails, the packet is discardedandreceivemoderestarted(regardlessoftheMCSM1.RXOFF_MODEsetting). If the received address matches a valid address when using infinite packet length mode and address filtering is enabled, 0xFF is written into the RX FIFO followed by the address byte and then the payload data. 34 DetailedDescription Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC11x1-Q1 www.ti.com SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 3.11.3.2 MaximumLengthFiltering In variable packet length mode, PKTCTRL0.LENGTH_CONFIG = 1, the PKTLEN.PACKET_LENGTH register value is used to set the maximum allowed packet length. If the received length byte has a larger value than this, the packet is discarded and receive mode restarted (regardless of the MCSM1.RXOFF_MODEsetting). 3.11.3.3 CRCFiltering The filtering of a packet when CRC check fails is enabled by setting PKTCTRL1.CRC_AUTOFLUSH = 1. The CRC auto flush function flushes the entire RX FIFO if the CRC check fails. After auto flushing the RX FIFO,thenextstatedependsontheMCSM1.RXOFF_MODEsetting. Whenusingtheautoflushfunction,themaximumpacketlengthis63bytesinvariablepacketlengthmode and 64 bytes in fixed packet length mode. Note that the maximum allowed packet length is reduced by two bytes when PKTCTRL1.APPEND_STATUS is enabled, to make room in the RX FIFO for the two status bytes appended at the end of the packet. Because the entire RX FIFO is flushed when the CRC check fails, the previously received packet must be read out of the FIFO before receiving the current packet.TheMCUmustnotreadfromthecurrentpacketuntiltheCRChasbeencheckedasOK. 3.11.4 Packet Handling in Transmit Mode The payload that is to be transmitted must be written into the TX FIFO. The first byte written must be the length byte when variable packet length is enabled. The length byte has a value equal to the payload of the packet (including the optional address byte). If address recognition is enabled on the receiver, the second byte written to the TX FIFO must be the address byte. If fixed packet length is enabled, then the firstbytewrittentotheTXFIFOshouldbetheaddress(ifthereceiverusesaddressrecognition). The modulator first sends the programmed number of preamble bytes. If data is available in the TX FIFO, the modulator sends the two-byte (optionally four-byte) sync word and then the payload in the TX FIFO. If CRC is enabled, the checksum is calculated over all the data pulled from the TX FIFO and the result is sent as two extra bytes following the payload data. If the TX FIFO runs empty before the complete packet has been transmitted, the radio enters TXFIFO_UNDERFLOW state. The only way to exit this state is by issuinganSFTXstrobe.WritingtotheTXFIFOafterithasunderfloweddoesnotrestartTXmode. If whitening is enabled, everything following the sync words is whitened. This is done before the optional FEC/Interleaverstage.WhiteningisenabledbysettingPKTCTRL0.WHITE_DATA=1. If FEC/Interleaving is enabled, everything following the sync words is scrambled by the interleaver and FECencodedbeforebeingmodulated.FECisenabledbysettingMDMCFG1.FEC_EN=1. 3.11.5 Packet Handling in Receive Mode In receive mode, the demodulator and packet handler searches for a valid preamble and the sync word. When found, the demodulator has obtained both bit and byte synchronism and receives the first payload byte. If FEC/Interleaving is enabled, the FEC decoder starts to decode the first payload byte. The interleaver descramblesthebitsbeforeanyotherprocessingisdonetothedata. Ifwhiteningisenabled,thedataisdewhitenedatthisstage. When variable packet length mode is enabled, the first byte is the length byte. The packet handler stores this value as the packet length and receives the number of bytes indicated by the length byte. If fixed packetlengthmodeisused,thepackethandleracceptstheprogrammednumberofbytes. Next, the packet handler optionally checks the address and only continues the reception if the address matches. If automatic CRC check is enabled, the packet handler computes CRC and matches it with the appendedCRCchecksum. Copyright©2009–2010,TexasInstrumentsIncorporated DetailedDescription 35 SubmitDocumentationFeedback

CC11x1-Q1 SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 www.ti.com At the end of the payload, the packet handler optionally writes two extra packet status bytes (see Table3-7andTable3-8)thatcontainCRCstatus,linkqualityindication,andRSSIvalue. 36 DetailedDescription Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC11x1-Q1 www.ti.com SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 3.11.6 Packet Handling in Firmware When implementing a packet oriented radio protocol in firmware, the MCU needs to know when a packet has been received/transmitted. Additionally, for packets longer than 64 bytes the RX FIFO needs to be read while in RX and the TX FIFO needs to be refilled while in TX. This means that the MCU needs to know the number of bytes that can be read from or written to the RX FIFO and TX FIFO respectively. Therearetwopossiblesolutionstogetthenecessarystatusinformation: InterruptDrivenSolution In both RX and TX one can use one of the GDO pins to give an interrupt when a sync word has been received/transmitted and/or when a complete packet has been received/transmitted (IOCFGx.GDOx_CFG = 0x06). In addition, there are two configurations for the IOCFGx.GDOx_CFG register that are associated with the RX FIFO (IOCFGx.GDOx_CFG = 0x00 and IOCFGx.GDOx_CFG = 0x01) and two that are associated with the TX FIFO (IOCFGx.GDOx_CFG = 0x02 and IOCFGx.GDOx_CFG = 0x03) that can be used as interrupt sources to provide information on how manybytesareintheRXFIFOandTXFIFOrespectively(seeTable3-17). SPIPolling The PKTSTATUS register can be polled at a given rate to get information about the current GDO2 and GDO0 values respectively. The RXBYTES and TXBYTES registers can be polled at a given rate to get informationaboutthenumberofbytesintheRXFIFOandTXFIFOrespectively.Alternatively,thenumber of bytes in the RX FIFO and TX FIFO can be read from the chip status byte returned on the MISO line eachtimeaheaderbyte,databyte,orcommandstrobeissentontheSPIbus. An interrupt-driven solution should be used, as high-rate SPI polling reduces the RX sensitivity. Furthermore, as explained in Section 3.6.3 and the errata notes, when using SPI polling, there is a small, but finite, probability that a single read from registers PKTSTATUS , RXBYTES, and TXBYTES is corrupt. Thesameisthecasewhenreadingthechipstatusbyte. SeetheTIwebsiteforsoftwareexamples. 3.12 Modulation Formats CC11x1-Q1 supports amplitude, frequency, and phase shift modulation formats. The desired modulation formatissetintheMDMCFG2.MOD_FORMATregister. Optionally, the data stream can be Manchester coded by the modulator and decoded by the demodulator. This option is enabled by setting MDMCFG2.MANCHESTER_EN = 1. Manchester encoding is not supportedatthesametimeasusingtheFEC/Interleaveroption. 3.12.1 Frequency Shift Keying CC11x1-Q1 can use Gaussian shaped 2-FSK (GFSK). The 2-FSK signal is then shaped by a Gaussian filter with BT = 1, producing a GFSK modulated signal. This spectrum-shaping feature improves adjacent channelpower(ACP)andoccupiedbandwidth. In 'true' 2-FSK systems with abrupt frequency shifting, the spectrum is inherently broad. By making the frequency shift 'softer', the spectrum can be made significantly narrower. Thus, higher data rates can be transmittedinthesamebandwidthusingGFSK. When FSK/GFSK modulation is used, the DEVIATN register specifies the expected frequency deviation of incoming signals in RX and should be the same as the TX deviation for demodulation to be performed reliablyandrobustly. The frequency deviation is programmed with the DEVIATION_M and DEVIATION_E values in the DEVIATNregister.Thevaluehasanexponent/mantissaform,andtheresultantdeviationisgivenby: fdev=fx2o1s7c´(8+DEVIATION_M)´2DEVIATION_E (4) Copyright©2009–2010,TexasInstrumentsIncorporated DetailedDescription 37 SubmitDocumentationFeedback

CC11x1-Q1 SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 www.ti.com ThesymbolencodingisshowninTable3-9. Table3-9.SymbolEncodingfor2-FSK/GFSK Modulation FORMAT SYMBOL CODING 0 –Deviation 2-FSK/GFSK 1 +Deviation 3.12.2 Minimum Shift Keying When using MSK [identical to offset QPSK with half-sine shaping (data coding may differ)], the complete transmission (preamble, sync word, and payload) is MSK modulated. Phase shifts are performed with a constant transition time. The fraction of a symbol period used to change the phase can be modified with the DEVIATN.DEVIATION_M setting. This is equivalent to changing the shaping of the symbol. The MSK modulation format implemented in CC11x1-Q1 inverts the sync word and data compared to, e.g., signal generators. 3.12.3 Amplitude Modulation CC11x1-Q1 supports two different forms of amplitude modulation: On-Off Keying (OOK) and Amplitude ShiftKeying(ASK). OOKmodulationsimplyturnsonoroffthePAtomodulate1and0respectively. The ASK variant supported by the CC11x1-Q1 allows programming of the modulation depth (the difference between 1 and 0), and shaping of the pulse amplitude. Pulse shaping produces a more bandwidthconstrainedoutputspectrum. 3.13 Received Signal Qualifiers and Link Quality Information CC11x1-Q1 has several qualifiers that can be used to increase the likelihood that a valid sync word is detected. 3.13.1 Sync Word Qualifier IfsyncworddetectioninRXisenabledinregisterMDMCFG2,theCC11x1-Q1doesnotstartfillingtheRX FIFO and performing the packet filtering described in Section 3.11.3.3 before a valid sync word has been detected. The sync word qualifier mode is set by MDMCFG2.SYNC_MODE and is summarized in Table3-10.CarriersenseisdescribedinSection3.13.4. Table3-10.SyncWordQualifierMode MDMCFG2.SYNC_MODE SYNCWORDQUALIFIERMODE 000 Nopreamble/sync 001 15/16syncwordbitsdetected 010 16/16syncwordbitsdetected 011 30/32syncwordbitsdetected 100 Nopreamble/sync,carriersenseabovethreshold 101 15/16+carriersenseabovethreshold 110 16/16+carriersenseabovethreshold 111 30/32+carriersenseabovethreshold 38 DetailedDescription Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC11x1-Q1 www.ti.com SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 3.13.2 Preamble Quality Threshold (PQT) The preamble quality threshold (PQT) sync-word qualifier adds the requirement that the received sync wordmustbeprecededwithapreamblewithaqualityabovetheprogrammedthreshold. Another use of the preamble quality threshold is as a qualifier for the optional RX termination timer. See Section3.15.7fordetails. The preamble quality estimator increases an internal counter by one each time a bit is received that is different from the previous bit, and decreases the counter by 8 each time a bit is received that is the same as the last bit. The threshold is configured with the register field PKTCTRL1.PQT. A threshold of 4 × PQT for this counter is used to gate sync word detection. By setting the value to zero, the preamble quality qualifierofthesynchwordisdisabled. A preamble quality reached signal can be observed on one of the GDO pins by setting IOCFGx.GDOx_CFG = 8. It is also possible to determine if preamble quality is reached by checking the PQT_REACHED bit in the PKTSTATUS register. This signal/bit asserts when the received signal exceeds thePQT. 3.13.3 RSSI The RSSI value is an estimate of the signal power level in the chosen channel. This value is based on the currentgainsettingintheRXchainandthemeasuredsignallevelinthechannel. In RX mode, the RSSI value can be read continuously from the RSSI status register until the demodulator detects a sync word (when sync word detection is enabled). At that point the RSSI readout value is frozen until the next time the chip enters the RX state. The RSSI value is in dBm with ½-dB resolution. The RSSI update rate, f , depends on the receiver filter bandwidth (BW defined in Section 3.9) and RSSI channel AGCCTRL0.FILTER_LENGTH. fRSSI=8´22F´ILBTWERc_hLaEnnNeGlTH (5) If PKTCTRL1.APPEND_STATUS is enabled the last RSSI value of the packet is automatically added to thefirstbyteappendedafterthepayload. The RSSI value read from the RSSI status register is a twos-complement number. The following procedurecanbeusedtoconverttheRSSIreadingtoanabsolutepowerlevel(RSSI_dBm). 1. ReadtheRSSIstatusregister 2. Convertthereadingfromahexadecimalnumbertoadecimalnumber(RSSI_dec) 3. IfRSSI_dec≥ 128thenRSSI_dBm=(RSSI_dec – 256)/2– RSSI_offset 4. ElseifRSSI_dec< 128thenRSSI_dBm=(RSSI_dec)/2– RSSI_offset Table 3-11 gives typical values for the RSSI_offset. Figure 3-12 and Figure 3-13 shows typical plots of RSSIreadingasafunctionofinputpowerlevelfordifferentdatarates. Table3-11.TypicalRSSI_offsetValues RSSI_offset(dB), RSSI_offset(dB), DATARATE(kBaud) 433MHz 868MHz 1.2 74 74 38.4 74 74 250 74 74 Copyright©2009–2010,TexasInstrumentsIncorporated DetailedDescription 39 SubmitDocumentationFeedback

CC11x1-Q1 SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 www.ti.com 0 1.2 kBaud 38.4 kBaud 250 kBaud -10 -20 -30 -40 m] B d -50 [ ut do -60 a e R SI -70 S R -80 -90 -100 -110 -120 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 Input Power [dBm] Figure3-12.TypicalRSSIValuevsInputPowerLevelforDifferentDataRatesat433MHz 0 1.2 kBaud 38.4 kBaud 250 kBaud -10 -20 -30 m] -40 B d -50 [ ut do -60 a e R -70 SI S R -80 -90 -100 -110 -120 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 Input Power [dBm] Figure3-13.TypicalRSSIValuevsInputPowerLevelforDifferentDataRatesat868MHz 3.13.4 Carrier Sense (CS) Carrier sense (CS) is used as a sync word qualifier and for CCA and can be asserted based on two conditions,whichcanbeindividuallyadjusted: • CSisassertedwhentheRSSIisaboveaprogrammableabsolutethresholdanddeassertedwhen RSSIisbelowthesamethreshold(withhysteresis). • CSisassertedwhentheRSSIhasincreasedwithaprogrammablenumberofdBfromoneRSSI sampletothenextanddeassertedwhenRSSIhasdecreasedwiththesamenumberofdB.This settingisnotdependentontheabsolutesignallevelandisthususefultodetectsignalsin environmentswithtimevaryingnoisefloor. Carrier sense can be used as a sync word qualifier that requires the signal level to be higher than the threshold for a sync word search to be performed. The signal can also be observed on one of the GDO pinsbysettingIOCFGx.GDOx_CFG=14andinthestatusregisterbitPKTSTATUS.CS. 40 DetailedDescription Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC11x1-Q1 www.ti.com SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 Other uses of carrier sense include the TX-if-CCA function (see Section 3.13.5) and the optional fast RX termination(seeSection3.15.7). CScanbeusedtoavoidinterferencefromotherRFsourcesintheISMbands. 3.13.4.1 CSAbsoluteThreshold TheabsolutethresholdrelatedtotheRSSIvaluedependsonthefollowingregisterfields: • AGCCTRL2.MAX_LNA_GAIN • AGCCTRL2.MAX_DVGA_GAIN • AGCCTRL1.CARRIER_SENSE_ABS_THR • AGCCTRL2.MAGN_TARGET For a given AGCCTRL2.MAX_LNA_GAIN and AGCCTRL2.MAX_DVGA_GAIN setting the absolute thresholdcanbeadjusted±7dBinstepsof1dBusingCARRIER_SENSE_ABS_THR. The MAGN_TARGET setting is a compromise between blocker tolerance/selectivity and sensitivity. The value sets the desired signal level in the channel into the demodulator. Increasing this value reduces the headroomforblockers,andthereforeclose-inselectivity. ItisstronglyrecommendedtouseSmartRFStudiotogeneratethecorrectMAGN_TARGETsetting. Table 3-12 and Table 3-13 show the typical RSSI readout values at the CS threshold at 2.4 kBaud and 250 kBaud data rate respectively. The default CARRIER_SENSE_ABS_THR = 0 (0 dB) and MAGN_TARGET=3(33dB)havebeenused. ForotherdataratestheusermustgeneratesimilartablestofindtheCSabsolutethreshold. Table3-12.TypicalRSSIValueindBmatCSThreshold WithDefaultMAGN_TARGETat2.4kBaud,868MHz MAX_DVGA_GAIN[1:0] 00 01 10 11 000 –97.5 –91.5 –85.5 –79.5 0] 001 –94 –88 –82.5 –76 2: N[ 010 –90.5 –84.5 –78.5 –72.5 AI G 011 –88 –82.5 –76.5 –70.5 _ NA 100 –85.5 –80 –73.5 –68 L _ 101 –84 –78 –72 –66 X A M 110 –82 –76 –70 –64 111 –79 –73.5 –67 –61 Copyright©2009–2010,TexasInstrumentsIncorporated DetailedDescription 41 SubmitDocumentationFeedback

CC11x1-Q1 SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 www.ti.com Table3-13.TypicalRSSIValueindBmatCSThreshold WithDefaultMAGN_TARGETat250kBaud,868MHz MAX_DVGA_GAIN[1:0] 00 01 10 11 000 –90.5 –84.5 –78.5 –72.5 0] 001 –88 –82 –76 –70 2: N[ 010 –84.5 –78.5 –72 –66 AI G 011 –82.5 –76.5 –70 –64 _ NA 100 –80.5 –74.5 –68 –62 L _ 101 –78 –72 –66 –60 X A M 110 –76.5 –70 –64 –58 111 –74.5 –68 –62 –56 If the threshold is set high (i.e., only strong signals are wanted) the threshold should be adjusted upwards by first reducing the MAX_LNA_GAIN value and then the MAX_DVGA_GAIN value. This reduces power consumptioninthereceiverfrontend,becausethehighestgainsettingsareavoided. 3.13.4.2 CSRelativeThreshold The relative threshold detects sudden changes in the measured signal level. This setting is not dependent on the absolute signal level and is thus useful to detect signals in environments with a time varying noise floor. The register field AGCCTRL1.CARRIER_SENSE_REL_THR is used to enable/disable relative CS, andtoselectthresholdof6dB,10dB,or14dBRSSIchange. 3.13.5 Clear Channel Assessment (CCA) The Clear Channel Assessment (CCA) is used to indicate if the current channel is free or busy. The currentCCAstateisviewableonanyoftheGDOpinsbysettingIOCFGx.GDOx_CFG=0x09. MCSM1.CCA_MODEselectsthemodetousewhendeterminingCCA. When the STX or SFSTXON command strobe is given while CC11x1-Q1 is in the RX state, the TX or FSTXONstateisonlyenterediftheclearchannelrequirementsarefulfilled.Thechipotherwiseremainsin RX (if the channel becomes available, the radio does not enter TX or FSTXON state before a new strobe command is sent on the SPI interface). This feature is called TX-if-CCA. Four CCA requirements can be programmed: • Always(CCAdisabled,alwaysgoestoTX) • IfRSSIisbelowthreshold • Unlesscurrentlyreceivingapacket • Boththeabove(RSSIbelowthresholdandnotcurrentlyreceivingapacket) 3.13.6 Link Quality Indicator (LQI) The Link Quality Indicator (LQI) is a metric of the current quality of the received signal. If PKTCTRL1.APPEND_STATUS is enabled, the value is automatically added to the last byte appended after the payload. The value can also be read from the LQI status register. The LQI gives an estimate of how easily a received signal can be demodulated by accumulating the magnitude of the error between ideal constellations and the received signal over the 64 symbols immediately following the sync word. LQI is best used as a relative measurement of the link quality (a high value indicates a better link than a low valuedoes),becausethevalueisdependentonthemodulationformat. 42 DetailedDescription Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC11x1-Q1 www.ti.com SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 3.14 Forward Error Correction With Interleaving 3.14.1 Forward Error Correction (FEC) CC11x1-Q1 has built in support for Forward Error Correction (FEC). To enable this option, set MDMCFG1.FEC_EN to 1. FEC is supported only in fixed packet length mode (PKTCTRL0.LENGTH_CONFIG = 0). FEC is employed on the data field and CRC word to reduce the gross bit error rate when operating near the sensitivity limit. Redundancy is added to the transmitted data insuchawaythatthereceivercanrestoretheoriginaldatainthepresenceofsomebiterrors. The use of FEC allows correct reception at a lower SNR, thus extending communication range if the receiver bandwidth remains constant. Alternatively, for a given SNR, using FEC decreases the bit error rate(BER).Asthepacketerrorrate(PER)isrelatedtoBERby: PER=1–(1–BER)packet_length (6) A lower BER can be used to allow longer packets, or a higher percentage of packets of a given length, to be transmitted successfully. Finally, in realistic ISM radio environments, transient and time-varying phenomena produce occasional errors even in otherwise good reception conditions. FEC masks such errors and, combined with interleaving of the coded data, even correct relatively long periods of faulty reception(bursterrors). The FEC scheme adopted for CC11x1-Q1 is convolutional coding, in which n bits are generated based on k input bits and the m most recent input bits, forming a code stream able to withstand a certain number of biterrorsbetweeneachcodingstate(them-bitwindow). The convolutional coder is a rate 1/2 code with a constraint length of m = 4. The coder codes one input bit and produces two output bits; hence, the effective data rate is halved. I.e., to transmit at the same effective data rate when using FEC, it is necessary to use twice as high over-the-air data rate. This requires a higher receiver bandwidth, and thus reduce sensitivity. In other words the improved reception byusingFECandthedegradedsensitivityfromahigherreceiverbandwidtharecounteractingfactors. 3.14.2 Interleaving Data received through radio channels often experiences burst errors due to interference and time-varying signal strengths. To increase the robustness to errors spanning multiple bits, interleaving is used when FEC is enabled. After deinterleaving, a continuous span of errors in the received stream become single errorsspreadapart. CC11x1-Q1 employs matrix interleaving, which is illustrated in Figure 3-14. The on-chip interleaving and deinterleaving buffers are 4×4 matrices. In the transmitter, the data bits from the rate one-half convolutional coder are written into the rows of the matrix, whereas the bit sequence to be transmitted is read from the columns of the matrix. Conversely, in the receiver, the received symbols are written into the columns of the matrix, whereas the data passed onto the convolutional decoder is read from the rows of thematrix. When FEC and interleaving is used at least one extra byte is required for trellis termination. In addition, the amount of data transmitted over the air must be a multiple of the size of the interleaver buffer (two bytes). The packet control hardware therefore automatically inserts one or two extra bytes at the end of the packet, so that the total length of the data to be interleaved is an even number. Note that these extra bytesareinvisibletotheuser,astheyareremovedbeforethereceivedpacketenterstheRXFIFO. WhenFECandinterleavingareusedtheminimumdatapayloadis2bytes. Copyright©2009–2010,TexasInstrumentsIncorporated DetailedDescription 43 SubmitDocumentationFeedback

CC11x1-Q1 SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 www.ti.com Figure3-14.GeneralPrincipleofMatrixInterleaving 3.15 Radio Control CC11x1-Q1 has a built-in state machine that is used to switch between different operational states (modes). The change of state is done either by using command strobes or by internal events such as TX FIFOunderflow. A simplified state diagram, together with typical usage and current consumption, is shown in Figure 3-4. The complete radio control state diagram is shown in Figure 3-15. The numbers refer to the state number readableintheMARCSTATEstatusregister.Thisregisterisprimarilyfortestpurposes. 44 DetailedDescription Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC11x1-Q1 www.ti.com SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 SIDLE SPWD|SWOR SLEEP CAL_COMPLETE 0 MANCAL IDLE CSn=0|WOR 3,4,5 1 SXOFF SCAL CSn=0 XOFF SRX|STX|SFSTXON|WOR 2 FS_WAKEUP 6,7 FS_AUTOCAL=01 & SRX|STX|SFSTXON|WOR FS_AUTOCAL=00|10|11 & CALIBRATE SRX|STX |SFSTXON |WOR 8 SETTLING CAL_COMPLETE SFSTXON 9,10,11 FSTXON 18 STX SRX |WOR STX SRX SFSTXON |RXOFF_MODE=01 TXOFF_MODE=01 STX |RXOFF_MODE=10 RXTX_SETTLING (STX|SFSTXON)&CCA 21 | TXOFF_MODE=10 19T,X20 RXOFF_MODE=01|10 13,R14X,15 RXOFF_MODE=11 SRX|TXOFF_MODE=11 TXRX_SETTLING 16 TXFIFO_UNDERFLOW TXOFF_M&ODE=00 RXOFF_M&ODE=00 RXFIFO_OVERFLOW FS_AUTOCAL=10|11 FS_AUTOCAL=10|11 CALIBRATE TXOFF_M&ODE=00 12 RXOFF_M&ODE=00 TX_UNDERFLOW FS_AUTOCAL=00|01 FS_AUTOCAL=00|01 RX_OVERFLOW 22 17 SFTX SFRX IDLE 1 Figure3-15.CompleteRadio-ControlStateDiagram 3.15.1 Power-On Start-Up Sequence When the power supply is turned on, the system must be reset. This is achieved by one of the two sequencesdescribedbelow,i.e.automaticpower-onreset(POR)ormanualreset. After the automatic power-on reset or manual reset it is also recommended to change the signal that is output on the GDO0 pin. The default setting is to output a clock signal with a frequency of CLK_XOSC/192, but to optimize performance in TX and RX an alternative GDO setting should be selectedfromthesettingsfoundinTable3-17. 3.15.1.1 AutomaticPOR A power-on reset circuit is included in the CC11x1-Q1. The minimum requirements stated in Section 2.14 must be followed for the power-on reset to function properly. The internal power-up sequence is completed when CHIP_RDYn goes low. CHIP_RDYn is observed on the SO pin after CS is pulled low. SeeSection3.6.1formoredetailsonCHIP_RDYn. Copyright©2009–2010,TexasInstrumentsIncorporated DetailedDescription 45 SubmitDocumentationFeedback

CC11x1-Q1 SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 www.ti.com WhentheCC11x1-Q1resetiscompleted,thechipisintheIDLEstateandthecrystaloscillatorisrunning. If the chip has had sufficient time for the crystal oscillator to stabilize after the power-on-reset the SO pin goes low immediately after taking CS low. If CS is taken low before reset is completed the SO pin first goeshigh,indicatingthatthecrystaloscillatorisnotstabilized,beforegoinglowasshowninFigure3-16. Figure3-16.Power-OnReset 3.15.1.2 ManualReset The other global reset possibility on CC11x1-Q1 uses the SRES command strobe. By issuing this strobe, all internal registers and states are set to the default, IDLE state. The manual power-up sequence is as follows(seeFigure3-17): • SetSCLK=1andSI=0,toavoidpotentialproblemswithpincontrolmode(seeSection3.7.3). • StrobeCSlowthenhigh. • HoldCShighforatleast40µsrelativetopullingCSlow • PullCSlowandwaitforSOtogolow(CHIP_RDYn). • IssuetheSRESstrobeontheSIline. • WhenSOgoeslowagain,resetiscompleteandthechipisintheIDLEstate. XOSC and voltage regulator switched on 40 µs CS SO SI Figure3-17.Power-OnResetWithSRES NOTE This reset procedure is required only after the power supply is first turned on. If the user wants to reset the CC11x1-Q1 after this, it is only necessary to issue an SRES command strobe. 3.15.2 Crystal Control The crystal oscillator (XOSC) is either automatically controlled or always on, if MCSM0.XOSC_FORCE_ONisset. In the automatic mode, the XOSC is turned off if the SXOFF or SPWD command strobes are issued. The statemachinethengoestoXOFForSLEEP,respectively.ThiscanbedoneonlyfromtheIDLEstate.The XOSC is turned off when CS is released (goes high). The XOSC is automatically turned on again when CS goes low. The state machine then goes to the IDLE state. The SO pin on the SPI interface must be pulledlowbeforetheSPIinterfaceisreadytobeused,asdescribedinSection2.9. 46 DetailedDescription Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC11x1-Q1 www.ti.com SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 IftheXOSCisforcedon,thecrystalstayson,evenintheSLEEPstate. Crystal oscillator start-up time depends on crystal ESR and load capacitances. The electrical specification forthecrystaloscillatorcanbefoundinSection2.9. 3.15.3 Voltage Regulator Control The voltage regulator to the digital core is controlled by the radio controller. When the chip enters the SLEEP state, which is the state with the lowest current consumption, the voltage regulator is disabled. This occurs after CS is released when a SPWD command strobe has been sent on the SPI interface. The chip is now in the SLEEP state. Setting CS low again turns on the regulator and crystal oscillator and makethechipentertheIDLEstate. When wake on radio is enabled, the WOR module controls the voltage regulator as described in Section3.15.5. 3.15.4 Active Modes CC11x1-Q1 has two active modes: receive and transmit. These modes are activated directly by the MCU byusingtheSRXandSTXcommandstrobes,orautomaticallybyWakeonRadio. The frequency synthesizer must be calibrated regularly. CC11x1-Q1 has one manual calibration option (usingtheSCALstrobe),andthreeautomaticcalibrationoptions,controlledbytheMCSM0.FS_AUTOCAL setting: • CalibratewhengoingfromIDLEtoeitherRXorTX(orFSTXON) • CalibratewhengoingfromeitherRXorTXtoIDLEautomatically • CalibrateeveryfourthtimewhengoingfromeitherRXorTXtoIDLEautomatically If the radio goes from TX or RX to IDLE by issuing an SIDLE strobe, calibration is not performed. The calibrationtakesaconstantnumberofXOSCcycles(seeTable3-14fortimingdetails). When RX is activated, the chip remains in receive mode until a packet is successfully received or the RX terminationtimerexpires(seeSection3.15.7). NOTE The probability that a false sync word is detected can be reduced by using PQT, CS, maximumsyncwordlength,andsyncwordqualifiermodeasdescribedinSection3.13. After a packet is successfully received, the radio controller goes to the state indicated by the MCSM1.RXOFF_MODEsetting.Thepossibledestinationsare: • IDLE • FSTXON:FrequencysynthesizeronandreadyattheTXfrequency.ActivateTXwithSTX. • TX:Startsendingpreamble • RX:Startsearchforanewpacket Similarly,whenTXisactivethechipremainsintheTXstateuntilthecurrentpackethasbeensuccessfully transmitted. Then the state changes as indicated by the MCSM1.TXOFF_MODE setting. The possible destinationsarethesameasforRX. The MCU can manually change the state from RX to TX and vice versa by using the command strobes. If the radio controller is currently in transmit and the SRX strobe is used, the current transmission is ended andthetransitiontoRXisdone. If the radio controller is in RX when the STX or SFSTXON command strobes are used, the TX-if-CCA function is used. If the channel is not clear, the chip remains in RX. The MCSM1.CCA_MODE setting controlstheconditionsforclearchannelassessment(seeSection3.13.5fordetails). TheSIDLEcommandstrobecanalwaysbeusedtoforcetheradiocontrollertogototheIDLEstate. Copyright©2009–2010,TexasInstrumentsIncorporated DetailedDescription 47 SubmitDocumentationFeedback

CC11x1-Q1 SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 www.ti.com 3.15.5 Wake On Radio (WOR) TheoptionalWakeonRadio(WOR)functionalityenablesCC11x1-Q1toperiodicallywakeupfromSLEEP andlistenforincomingpacketswithoutMCUinteraction. When the WOR strobe command is sent on the SPI interface, the CC11x1-Q1 goes to the SLEEP state when CS is released. The RC oscillator must be enabled before the WOR strobe can be used, as it is the clock source for the WOR timer. The on-chip timer sets CC11x1-Q1 into IDLE state and then RX state. After a programmable time in RX, the chip goes back to the SLEEP state, unless a packet is received. SeeFigure3-18andSection3.15.7fordetailsonhowthetimeoutworks. SettheCC11x1-Q1intotheIDLEstatetoexitWORmode. CC11x1-Q1 can be set up to signal the MCU that a packet has been received by using the GDO pins. If a packet is received, the MCSM1.RXOFF_MODE determines the behavior at the end of the received packet. When the MCU has read the packet, it can put the chip back into SLEEP with the SWOR strobe fromtheIDLEstate.TheFIFOlosesitscontentsintheSLEEPstate. The WOR timer has two events, Event 0 and Event 1. In the SLEEP state with WOR activated, reaching Event 0 turns on the digital regulator and starts the crystal oscillator. Event 1 follows Event 0 after a programmedtimeout. The time between two consecutive Event 0 is programmed with a mantissa value given by WOREVT1.EVENT0 and WOREVT0.EVENT0, and an exponent value set by WORCTRL.WOR_RES. The equationis: tEvent0= 750 ´EVENT0´25´WOR_RES fXOSC (7) The Event 1 timeout is programmed with WORCTRL.EVENT1. Figure 3-18 shows the timing relationship betweenEvent0timeoutandEvent1timeout. Rxtimeout State: SLEEP IDLE RX SLEEP IDLE RX Event0 Event1 Event0 Event1 t t Event0 t Event0 t t Event1 Event1 t SLEEP Figure3-18.Event0andEvent1Relationship The time from the CC11x1-Q1 enters SLEEP state until the next Event0 is programmed to appear (tSLEEP in Figure 3-18) should be larger than 11.08 ms when using a 26-MHz crystal and 10.67 ms when a 27-MHz crystal is used. If t is less than 11.08 (10.67) ms, there is a chance that the consecutive SLEEP Event 0 will occur (750 / f ) × 128 seconds too early. CC1100/CC2500 – Wake-On-Radio (SWRA126) XOSC explains in detail the theory of operation and the different registers involved when using WOR, as well as highlightingimportantaspectswhenusingWORmode. 48 DetailedDescription Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC11x1-Q1 www.ti.com SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 3.15.5.1 RCOscillatorandTiming The frequency of the low-power RC oscillator used for the WOR functionality varies with temperature and supply voltage. To keep the frequency as accurate as possible, the RC oscillator is calibrated whenever possible, which is when the XOSC is running and the chip is not in the SLEEP state. When the power and XOSC is enabled, the clock used by the WOR timer is a divided XOSC clock. When the chip goes to the sleep state, the RC oscillator uses the last valid calibration result. The frequency of the RC oscillator is lockedtothemaincrystalfrequencydividedby750. In applications where the radio wakes up very often, typically several times every second, it is possible to do the RC oscillator calibration once and then turn off calibration (WORCTRL.RC_CAL = 0) to reduce the current consumption. This requires that RC oscillator calibration values are read from registers RCCTRL0_STATUS and RCCTRL1_STATUS and written back to RCCTRL0 and RCCTRL1 respectively. If the RC oscillator calibration is turned off, it must be manually turned on again if temperature and supply voltagechanges. SeeCC1100/CC2500– Wake-On-Radio(SWRA126)forfurtherdetails. 3.15.6 Timing The radio controller controls most of the timing in CC11x1-Q1, such as synthesizer calibration, PLL lock time, and RX/TX turnaround times. Timing from IDLE to RX and IDLE to TX is constant, dependent on the auto calibration setting. RX/TX and TX/RX turnaround times are constant. The calibration time is constant 18739clockperiods.Table3-14showstimingincrystalclockcyclesforkeystatetransitions. PowerontimeandXOSCstart-uptimesarevariable,butwithinthelimitsstatedinSection2.9. Note that in a frequency hopping spread spectrum or a multi-channel protocol the calibration time can be reducedfrom721µstoapproximately150 µs(seeSection3.27.2). Table3-14.StateTransitionTiming DESCRIPTION XOSCPERIODS 26-MHzCRYSTAL IDLEtoRX,nocalibration 2298 88.4µs IDLEtoRX,withcalibration ~21037 809µs IDLEtoTX/FSTXON,nocalibration 2298 88.4µs IDLEtoTX/FSTXON,withcalibration ~21037 809µs TXtoRXswitch 560 21.5µs RXtoTXswitch 250 9.6µs RXorTXtoIDLE,nocalibration 2 0.1µs RXorTXtoIDLE,withcalibration ~18739 721µs Manualcalibration ~18739 721µs 3.15.7 RX Termination Timer CC11x1-Q1 has optional functions for automatic termination of RX after a programmable time. The main use for this functionality is wake-on-radio (WOR), but it may be useful for other applications. The termination timer starts when in RX state. The timeout is programmable with the MCSM2.RX_TIME setting. When the timer expires, the radio controller checks the condition for staying in RX. If the condition isnotmet,RXterminates. Theprogrammableconditionsare: • MCSM2.RX_TIME_QUAL=0 Continuereceiveifsyncwordhasbeenfound • MCSM2.RX_TIME_QUAL=1 Continuereceiveifsyncwordhasbeenfoundorpreamblequalityisabovethreshold(PQT) Copyright©2009–2010,TexasInstrumentsIncorporated DetailedDescription 49 SubmitDocumentationFeedback

CC11x1-Q1 SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 www.ti.com If the system can expect the transmission to have started when enabling the receiver, the MCSM2.RX_TIME_RSSI function can be used. The radio controller then terminates RX if the first valid carrier sense sample indicates no carrier (RSSI below threshold) (see Section 3.13.4for details on Carrier Sense). For ASK/OOK modulation, lack of carrier sense is only considered valid after eight symbol periods. Thus, the MCSM2.RX_TIME_RSSI function can be used in ASK/OOK mode when the distance between "1" symbolsis8orless. If RX terminates due to no carrier sense when the MCSM2.RX_TIME_RSSI function is used, or if no sync word was found when using the MCSM2.RX_TIME timeout function, the chip goes back to IDLE if WOR is disabled and back to SLEEP if WOR is enabled. Otherwise, the MCSM1.RXOFF_MODE setting determines the state to go to when RX ends. This means that the chip does not automatically go back to SLEEP once a sync word has been received. It is therefore recommended to always wake up the microcontroller on sync word detection when using WOR mode. This can be done by selecting output signal 6 (see Table 3-17) on one of the programmable GDO output pins, and programming the microcontrollertowakeuponanedge-triggeredinterruptfromthisGDOpin. 3.16 Data FIFO The CC11x1-Q1 contains two 64 byte FIFOs, one for received data and one for data to be transmitted. The SPI interface is used to read from the RX FIFO and write to the TX FIFO. Section 3.6contains details on the SPI FIFO access. The FIFO controller detects overflow in the RX FIFO and underflow in the TX FIFO. When writing to the TX FIFO, it is the responsibility of the MCU to avoid TX FIFO overflow. A TX FIFO overflowresultsinanerrorintheTXFIFOcontent. Likewise, when reading the RX FIFO, the MCU must avoid reading the RX FIFO past its empty value, becauseanRXFIFOunderflowresultsinanerrorinthedatareadoutoftheRXFIFO. The chip status byte that is available on the SO pin while transferring the SPI header contains the fill grade of the RX FIFO if the access is a read operation and the fill grade of the TX FIFO if the access is a writeoperation.Section3.6.1containsmoredetailsonthis. The number of bytes in the RX FIFO and TX FIFO can be read from the status registers RXBYTES.NUM_RXBYTES and TXBYTES.NUM_TXBYTES respectively. If a received data byte is written to the RX FIFO at the exact same time as the last byte in the RX FIFO is read over the SPI interface, the RX FIFO pointer is not properly updated and the last read byte is duplicated. To avoid this problem one shouldneveremptytheRXFIFObeforethelastbyteofthepacketisreceived. For packet lengths less than 64 bytes it is recommended to wait until the complete packet has been receivedbeforereadingitoutoftheRXFIFO. If the packet length is larger than 64 bytes the MCU must determine how many bytes can be read from theRXFIFO(RXBYTES.NUM_RXBYTES-1)andthefollowingsoftwareroutinecanbeused: 1. ReadRXBYTES.NUM_RXBYTESrepeatedlyatarateensuredtobeatleasttwicethatatwhichRF bytesarereceiveduntilthesamevalueisreturnedtwice.Storevalueinn. 2. Ifn<#ofbytesremaininginpacket,readn – 1bytesfromtheRXFIFO. 3. Repeatsteps1and2untiln=#ofbytesremaininginpacket. 4. ReadtheremainingbytesfromtheRXFIFO. The 4-bit FIFOTHR.FIFO_THR setting is used to program threshold points in the FIFOs. Table 3-15 lists the 16 FIFO_THR settings and the corresponding thresholds for the RX and TX FIFOs. The threshold value is coded in opposite directions for the RX FIFO and TX FIFO. This gives equal margin to the overflowandunderflowconditionswhenthethresholdisreached. A signal asserts when the number of bytes in the FIFO is equal to or higher than the programmed threshold.ThissignalcanbeviewedontheGDOpins(seeTable3-17). 50 DetailedDescription Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC11x1-Q1 www.ti.com SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 Figure 3-20 shows the number of bytes in both the RX FIFO and TX FIFO when the threshold signal toggles, in the case of FIFO_THR = 13. Figure 3-19 shows the signal as the respective FIFO is filled abovethethreshold,andthendrainedbelow. NUM_RXBYTES 53 54 55 56 57 56 55 54 53 GDO NUM_TXBYTES 6 7 8 9 10 9 8 7 6 GDO Figure3-19.FIFO_THR=13vsNumberofBytesinFIFO (GDOx_CFG=0x00inRXandGDOx_CFG=0x02inTX) Table3-15.FIFO_THRSettingsandtheCorresponding FIFOThresholds FIFO_THR BYTESINTXFIFO BYTESINRXFIFO 0(0000) 61 4 1(0001) 57 8 2(0010) 53 12 3(0011) 49 16 4(0100) 45 20 5(0101) 41 24 6(0110) 37 28 7(0111) 33 32 8(1000) 29 36 9(1001) 25 40 10(1010) 21 44 11(1011) 17 48 12(1100) 13 52 13(1101) 9 56 14(1110) 5 60 15(1111) 1 64 Copyright©2009–2010,TexasInstrumentsIncorporated DetailedDescription 51 SubmitDocumentationFeedback

CC11x1-Q1 SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 www.ti.com Overflow margin FIFO_THR=13 56bytes FIFO_THR=13 Underflow 8bytes margin RXFIFO TXFIFO Figure3-20.ExampleofFIFOsatThreshold 3.17 Frequency Programming The frequency programming in CC11x1-Q1 is designed to minimize the programming needed in a channel-orientedsystem. To set up a system with channel numbers, the desired channel spacing is programmed with the MDMCFG0.CHANSPC_M and MDMCFG1.CHANSPC_E registers. The channel spacing registers are mantissaandexponentrespectively. The base or start frequency is set by the 24-bit frequency word located in the FREQ2, FREQ1, and FREQ0 registers. This word is typically set to the center of the lowest channel frequency that is to be used. The desired channel number is programmed with the 8-bit channel number register, CHANNR.CHAN, whichismultipliedbythechanneloffset.Theresultantcarrierfrequencyisgivenby: × × × (8) With a 26-MHz crystal the maximum channel spacing is 405 kHz. To get, for example, 1-MHz channel spacingonesolutionistouse333-kHzchannelspacingandselecteachthirdchannelinCHANNR.CHAN. The preferred IF frequency is programmed with the FSCTRL1.FREQ_IF register. The IF frequency is givenby: fIF=fX2O1S0C´FREQ_IF (9) NOTE The SmartRF Studio software automatically calculates the optimum FSCTRL1.FREQ_IF registersettingbasedonchannelspacingandchannelfilterbandwidth. If any frequency programming register is altered when the frequency synthesizer is running, the synthesizer may give an undesired response. Hence, the frequency programming should only be updated whentheradioisintheIDLEstate. 3.18 VCO TheVCOiscompletelyintegratedon-chip. 52 DetailedDescription Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC11x1-Q1 www.ti.com SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 3.18.1 VCO and PLL Self-Calibration The VCO characteristics vary with temperature and supply voltage changes, as well as the desired operating frequency. To ensure reliable operation, CC11x1-Q1 includes frequency synthesizer self-calibration circuitry. This calibration should be done regularly, and must be performed after turning on power and before using a new frequency (or channel). The number of XOSC cycles for completing the PLLcalibrationisgiveninTable3-14. The calibration can be initiated automatically or manually. The synthesizer can be automatically calibrated each time the synthesizer is turned on, or each time the synthesizer is turned off automatically. This is configured with the MCSM0.FS_AUTOCAL register setting. In manual mode, the calibration is initiated whentheSCALcommandstrobeisactivatedintheIDLEmode. NOTE The calibration values are maintained in SLEEP mode, so the calibration is still valid after waking up from SLEEP mode (unless supply voltage or temperature has changed significantly). To check that the PLL is in lock, the user can program register IOCFGx.GDOx_CFG to 0x0A and use the lock detector output available on the GDOx pin as an interrupt for the MCU (x = 0,1, or 2). A positive transition on the GDOx pin means that the PLL is in lock. As an alternative the user can read register FSCAL1. The PLL is in lock if the register content is different from 0x3F (see also the errata notes). For more robust operation the source code could include a check so that the PLL is re-calibrated until PLL lockisachievedifthePLLdoesnotlockthefirsttime. 3.19 Voltage Regulators CC11x1-Q1 contains several on-chip linear voltage regulators, which generate the supply voltage needed by low-voltage modules. These voltage regulators are invisible to the user, and can be viewed as integral parts of the various modules. The user must however make sure that the absolute maximum ratings and required pin voltages in Table 3-1 and Section 2.1 are not exceeded. The voltage regulator for the digital corerequiresoneexternaldecouplingcapacitor. Setting the CS pin low turns on the voltage regulator to the digital core and starts the crystal oscillator. The SO pin on the SPI interface must go low before the first positive edge of SCLK (setup time is given in Section2.15). If the chip is programmed to enter power-down mode, (SPWD strobe issued), the power is turned off after CSgoeshigh.ThepowerandcrystaloscillatorareturnedonagainwhenCSgoeslow. ThevoltageregulatoroutputshouldbeusedonlyfordrivingtheCC11x1-Q1. 3.20 Output Power Programming The RF output power level from the device has two levels of programmability, as illustrated in Figure 3-21. Firstly, the special PATABLE register can hold up to eight user selected output power settings. Secondly, the 3-bit FREND0.PA_POWER value selects the PATABLE entry to use. This two-level functionality provides flexible PA power ramp up and ramp down at the start and end of transmission, as well as ASK modulation shaping. All the PA power settings in the PATABLE from index 0 up to the FREND0.PA_POWERvalueareused. The power ramping at the start and at the end of a packet can be turned off by setting FREND0.PA_POWERtozeroandthenprogramthedesiredoutputpowertoindex0inthePATABLE. If OOK modulation is used, the logic 0 and logic 1 power levels shall be programmed to index 0 and 1 respectively. Copyright©2009–2010,TexasInstrumentsIncorporated DetailedDescription 53 SubmitDocumentationFeedback

CC11x1-Q1 SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 www.ti.com See Design Note DN013 Programming Output Power on CC1101 (SWRA151) for recommended PATABLE settings for various output levels and frequency bands. Using PA settings from 0x61 to 0x6F is notrecommended.SeeSection3.6.6forPATABLEprogrammingdetails. See Design Note DN013 Programming Output Power on CC1101 (SWRA151) for output power and current consumption for default PATABLE setting (0xC6). PATABLE must be programmed in burst mode towritetoentriesotherthanPATABLE[0]. NOTE All content of the PATABLE, except for the first byte (index 0), is lost when entering the SLEEPstate. 3.21 Shaping and PA Ramping With ASK modulation, up to eight power settings are used for shaping. The modulator contains a counter that counts up when transmitting a one and down when transmitting a zero. The counter counts at a rate equal to 8 times the symbol rate. The counter saturates at FREND0.PA_POWER and 0 respectively. This counter value is used as an index for a lookup in the power table. Thus, to utilize the whole table, FREND0.PA_POWER should be 7 when ASK is active. The shaping of the ASK signal is dependent on theconfigurationofthePATABLE. Figure3-22showssomeexamplesofASKshaping. PATABLE(7)[7:0] ThePAusesthis PATABLE(6)[7:0] setting. PATABLE(5)[7:0] PATABLE(4)[7:0] Settings0toPA_POWERare PATABLE(3)[7:0] usedduringramp-upatstartof transmissionandramp-downat PATABLE(2)[7:0] endoftransmission,andfor PATABLE(1)[7:0] ASK/OOKmodulation. PATABLE(0)[7:0] IndexintoPATABLE(7:0) TheSmartRF®Studiosoftware e.g6 shouldbeusedtoobtainoptimum PATABLEsettingsforvarious PA_POWER[2:0] outputpowers. inFREND0register Figure3-21.PA_POWERandPATABLE OutputPower PATABLE[7] PATABLE[6] PATABLE[5] PATABLE[4] PATABLE[3] PATABLE[2] PATABLE[1] PATABLE[0] Time 1 0 0 1 0 1 1 0 BitSequence FREND0.PA_POWER=3 FREND0.PA_POWER=7 Figure3-22.ShapingofASKSignal 54 DetailedDescription Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC11x1-Q1 www.ti.com SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 3.22 Crystal Oscillator A crystal in the frequency range 26-27 MHz must be connected between the XOSC_Q1 and XOSC_Q2 pins. The oscillator is designed for parallel mode operation of the crystal. In addition, loading capacitors (C81 and C101) for the crystal are required. The loading capacitor values depend on the total load capacitance, CL, specified for the crystal. The total load capacitance seen between the crystal terminals shouldequalCLforthecrystaltooscillateatthespecifiedfrequency. 1 CL= 1 1 +Cparasitic + C81 C101 (10) The parasitic capacitance is constituted by pin input capacitance and PCB stray capacitance. Total parasiticcapacitanceistypically2.5pF. The crystal oscillator circuit is shown in Figure 3-23. Typical component values for different values of CL aregiveninTable3-16. XTAL XOSC_Q1 XOSC_Q2 C81 C101 Figure3-23.CrystalOscillatorCircuit Table3-16.CrystalOscillatorComponentValues Component C =10pF C =13pF C =16pF L L L C81 15pF 22pF 27pF C101 15pF 22pF 27pF The crystal oscillator is amplitude regulated. This means that a high current is used to start up the oscillations. When the amplitude builds up, the current is reduced to what is necessary to maintain approximately 0.4-V signal swing. This ensures a fast start-up, and keeps the drive level to a minimum. pp TheESRofthecrystalshouldbewithinthespecificationtoensureareliablestart-up(seeSection2.9). The initial tolerance, temperature drift, aging and load pulling should be carefully specified to meet the requiredfrequencyaccuracyinacertainapplication. 3.22.1 Reference Signal Thechipcanalternativelybeoperatedwithareferencesignalfrom26to27MHzinsteadofacrystal.This input clock can either be a full-swing digital signal (0 V to V ) or a sine wave of maximum 1 V peak-peak DD amplitude. The reference signal must be connected to the XOSC_Q1 input. The sine wave must be connected to XOSC_Q1 using a serial capacitor. When using a full-swing digital signal this capacitor can be omitted. The XOSC_Q2 line must be left unconnected. C81 and C101 can be omitted when using a referencesignal. 3.23 External RF Match The balanced RF input and output of CC11x1-Q1 share two common pins and are designed for a simple, low-cost matching and balun network on the printed circuit board. The receive- and transmit switching at the CC11x1-Q1 front-end is controlled by a dedicated on-chip function, eliminating the need for an externalRX/TX-switch. A few passive external components combined with the internal RX/TX switch/termination circuitry ensures matchinbothRXandTXmode. Copyright©2009–2010,TexasInstrumentsIncorporated DetailedDescription 55 SubmitDocumentationFeedback

CC11x1-Q1 SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 www.ti.com Although CC11x1-Q1 has a balanced RF input/output, the chip can be connected to a single-ended antennawithfewexternallowcostcapacitorsandinductors. The passive matching/filtering network connected to CC11x1-Q1 should have the following differential impedanceasseenfromtheRF-port(RF_PandRF_N)towardtheantenna: Z =122+j31Ω out315MHz Z =116+j41Ω out433MHz Z =86.5+j43Ω out868/915MHz To ensure optimal matching of the CC11x1-Q1 differential output it is recommended to follow the reference design as closely as possible. Gerber files for the reference designs are available for download fromtheTIwebsite. 3.24 PCB Layout Recommendations The top layer should be used for signal routing, and the open areas should be filled with metallization connectedtogroundusingseveralvias. The area under the chip is used for grounding and shall be connected to the bottom ground plane with several vias. In the reference designs, five vias are placed inside the exposed die attached pad. These vias should be tented (covered with solder mask) on the component side of the PCB to avoid migration of solderthroughtheviasduringthesolderreflowprocess. The solder paste coverage should not be 100%. If it is, out gassing may occur during the reflow process, which may cause defects (splattering, solder balling). Using "tented" vias reduces the solder paste coveragebelow100%. Each decoupling capacitor should be placed as close as possible to the supply pin it is supposed to decouple. Each decoupling capacitor should be connected to the power line (or power plane) by separate vias. The best routing is from the power line (or power plane) to the decoupling capacitor and then to the CC11x1-Q1supplypin.Supplypowerfilteringisveryimportant. Each decoupling capacitor ground pad should be connected to the ground plane using a separate via. Direct connections between neighboring power pins increase noise coupling and should be avoided unlessabsolutelynecessary. The external components ideally should be as small as possible (0402 is recommended) and surface mount devices are highly recommended. Please note that components smaller than those specified may havedifferingcharacteristics. PrecautionshouldbeusedwhenplacingthemicrocontrollertoavoidnoiseinterferingwiththeRFcircuitry. A development kit with a fully assembled evaluation module is available. It is strongly advised that this reference layout is followed closely to get the best performance. The schematic, BOM, and layout Gerber filesareallavailablefromtheTIwebsite. 3.25 General Purpose / Test Output Control Pins The three digital output pins GDO0, GDO1, and GDO2 are general control pins configured with IOCFG0.GDO0_CFG, IOCFG1.GDO1_CFG, and IOCFG2.GDO3_CFG respectively. Table 3-17 shows the different signals that can be monitored on the GDO pins. These signals can be used as inputs to the MCU. GDO1 is the same pin as the SO pin on the SPI interface, thus the output programmed on this pin is valid only when CS is high. The default value for GDO1 is 3-stated, which is useful when the SPI interfaceissharedwithotherdevices. ThedefaultvalueforGDO0isa135-141kHzclockoutput(XOSCfrequencydividedby192).Becausethe XOSC is turned on at power-on-reset, this can be used to clock the MCU in systems with only one crystal. WhentheMCUisupandrunning,itcanchangetheclockfrequencybywritingtoIOCFG0.GDO0_CFG. 56 DetailedDescription Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC11x1-Q1 www.ti.com SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 An on-chip analog temperature sensor is enabled by writing the value 128 (0x80) to the IOCFG0 register. The voltage on the GDO0 pin is then proportional to temperature. See Section 2.12 for temperature sensorspecifications. If the IOCFGx.GDOx_CFG setting is less than 0x20 and IOCFGx_GDOx_INV is 0 (1), the GDO0 and GDO2 pins are hardwired to 0 (1) and the GDO1 pin is hardwired to 1 (0) in the SLEEP state. These signalsarehardwireduntiltheCHIP_RDYnsignalgoeslow. If the IOCFGx.GDOx_CFG setting is 0x20 or higher, the GDO pins also work as programmed in SLEEP state.Asanexample,GDO1ishighimpedanceinallstatesifIOCFG1.GDO1_CFG=0x2E. Copyright©2009–2010,TexasInstrumentsIncorporated DetailedDescription 57 SubmitDocumentationFeedback

CC11x1-Q1 SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 www.ti.com Table3-17.GDOxSignalSelection(x=0,1,or2) GDOx_CFG[5:0] DESCRIPTION 0(0x00) AssociatedtotheRXFIFO:AssertswhenRXFIFOisfilledatorabovetheRXFIFOthreshold.De-assertswhenRX FIFOisdrainedbelowthesamethreshold. 1(0x01) AssociatedtotheRXFIFO:AssertswhenRXFIFOisfilledatorabovetheRXFIFOthresholdortheendofpacketis reached.De-assertswhentheRXFIFOisempty. 2(0x02) AssociatedtotheTXFIFO:AssertswhentheTXFIFOisfilledatorabovetheTXFIFOthreshold.De-assertswhenthe TXFIFOisbelowthesamethreshold. 3(0x03) AssociatedtotheTXFIFO:AssertswhenTXFIFOisfull.De-assertswhentheTXFIFOisdrainedbelowtheTXFIFO threshold. 4(0x04) AssertswhentheRXFIFOhasoverflowed.De-assertswhentheFIFOhasbeenflushed. 5(0x05) AssertswhentheTXFIFOhasunderflowed.De-assertswhentheFIFOisflushed. 6(0x06) Assertswhensyncwordhasbeensent/received,andde-assertsattheendofthepacket.InRX,thepinde-asserts whentheoptionaladdresscheckfailsortheRXFIFOoverflows.InTX,thepinde-assertsiftheTXFIFOunderflows. 7(0x07) AssertswhenapackethasbeenreceivedwithCRCOK.De-assertswhenthefirstbyteisreadfromtheRXFIFO. 8(0x08) PreambleQualityReached.AssertswhenthePQIisabovetheprogrammedPQTvalue. 9(0x09) Clearchannelassessment.HighwhenRSSIlevelisbelowthreshold(dependentonthecurrentCCA_MODEsetting) 10(0x0A) Lockdetectoroutput.ThePLLisinlockifthelockdetectoroutputhasapositivetransitionorisconstantlylogichigh.To checkforPLLlockthelockdetectoroutputshouldbeusedasaninterruptfortheMCU. 11(0x0B) SerialClock.Synchronoustothedatainsynchronousserialmode.InRXmode,dataissetuponthefallingedgeby CC11x1-Q1whenGDOx_INV=0.InTXmode,dataissampledbyCC11x1-Q1ontherisingedgeoftheserialclock whenGDOx_INV=0. 12(0x0C) Serialsynchronousdataoutput.Usedforsynchronousserialmode. 13(0x0D) Serialdataoutput.Usedforasynchronousserialmode. 14(0x0E) Carriersense.HighifRSSIlevelisabovethreshold. 15(0x0F) CRC_OK.ThelastCRCcomparisonmatched.Clearedwhenentering/restartingRXmode. 16(0x10)to Reserved–usedfortest 21(0x15) 22(0x16) RX_HARD_DATA[1].CanbeusedtogetherwithRX_SYMBOL_TICKforalternativeserialRXoutput. 23(0x17) RX_HARD_DATA[0].CanbeusedtogetherwithRX_SYMBOL_TICKforalternativeserialRXoutput. 24(0x18)to Reserved–usedfortest 26(0x1A) 27(0x1B) PA_PD.Note:PA_PDhasthesamesignallevelinSLEEPandTXstates.TocontrolanexternalPAorRX/TXswitchin applicationswheretheSLEEPstateisused,itisrecommendedtouseGDOx_CFGx=0x2Finstead. 28(0x1C) LNA_PD.Note:LNA_PDhasthesamesignallevelinSLEEPandRXstates.TocontrolanexternalLNAorRX/TX switchinapplicationswheretheSLEEPstateisused,itisrecommendedtouseGDOx_CFGx=0x2Finstead. 29(0x1D) RX_SYMBOL_TICK.CanbeusedtogetherwithRX_HARD_DATAforalternativeserialRXoutput. 30(0x1E)to Reserved–usedfortest 35(0x23) 36(0x24) WOR_EVNT0 37(0x25) WOR_EVNT1 38(0x26) Reserved–usedfortest 39(0x27) CLK_32k 40(0x28) Reserved–usedfortest 41(0x29) CHIP_RDYn 42(0x2A) Reserved–usedfortest 43(0x2B) XOSC_STABLE 44(0x2C) Reserved–usedfortest 45(0x2D) GDO0_Z_EN_N.Whenthisoutputis0,GDO0isconfiguredasinput(forserialTXdata). 46(0x2E) Highimpedance(3-state) 47(0x2F) HWto0(HW1achievedbysettingGDOx_INV=1).CanbeusedtocontrolanexternalLNA/PAorRX/TXswitch. 58 DetailedDescription Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC11x1-Q1 www.ti.com SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 Table3-17.GDOxSignalSelection(x=0,1,or2)(continued) GDOx_CFG[5:0] DESCRIPTION 48(0x30) CLK_XOSC/1 49(0x31) CLK_XOSC/1. 5 50(0x32) CLK_XOSC/2 51(0x33) CLK_XOSC/3 52(0x34) CLK_XOSC/4 53(0x35) CLK_XOSC/6 54(0x36) CLK_XOSC/8 55(0x37) CLK_XOSC/12 Note:Thereare3GDOpins,butonlyoneCLK_XOSC/ncanbeselectedasanoutputatanytime.If CLK_XOSC/nistobemonitoredononeoftheGDOpins,theothertwoGDOpinsmustbeconfigured 56(0x38) CLK_XOSC/16 tovalueslessthan0x30.TheGDO0defaultvalueisCLK_XOSC/192. 57(0x39) CLK_XOSC/24 TooptimizeRFperformance,thesesignalshouldnotbeusedwhiletheradioisinRXorTXmode. 58(0x3A) CLK_XOSC/32 59(0x3B) CLK_XOSC/48 60(0x3C) CLK_XOSC/64 61(0x3D) CLK_XOSC/96 62(0x3E) CLK_XOSC/12 8 63(0x3F) CLK_XOSC/19 2 3.26 Asynchronous and Synchronous Serial Operation Several features and modes of operation have been included in the CC11x1-Q1 to provide backward compatibility with previous Chipcon products and other existing RF communication systems. For new systems, it is recommended to use the built-in packet handling features, as they can give more robust communication,significantlyoffloadthemicrocontroller,andsimplifysoftwaredevelopment. 3.26.1 Asynchronous Operation For backward compatibility with systems already using the asynchronous data transfer from other Chipcon products, asynchronous transfer is also included in CC11x1-Q1. When asynchronous transfer is enabled, several of the support mechanisms for the MCU that are included in CC11x1-Q1 are disabled, such as packet handling hardware, buffering in the FIFO, and so on. The asynchronous transfer mode does not allow the use of the data whitener, interleaver, and FEC, and it is not possible to use Manchester encoding. NOTE MSKisnotsupportedforasynchronoustransfer. SettingPKTCTRL0.PKT_FORMATto3enablesasynchronousserialmode. In TX, the GDO0 pin is used for data input (TX data). Data output can be on GDO0, GDO1, or GDO2. ThisissetbytheIOCFG0.GDO0_CFG,IOCFG1.GDO1_CFGandIOCFG2.GDO2_CFGfields. The CC11x1-Q1 modulator samples the level of the asynchronous input 8 times faster than the programmed data rate. The timing requirement for the asynchronous stream is that the error in the bit periodmustbelessthanoneeighthoftheprogrammeddatarate. 3.26.2 Synchronous Serial Operation Setting PKTCTRL0.PKT_FORMAT to 1 enables synchronous serial mode. In the synchronous serial Copyright©2009–2010,TexasInstrumentsIncorporated DetailedDescription 59 SubmitDocumentationFeedback

CC11x1-Q1 SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 www.ti.com mode, data is transferred on a two wire serial interface. The CC11x1-Q1 provides a clock that is used to set up new data on the data input line or sample data on the data output line. Data input (TX data) is the GDO0 pin. This pin is automatically configured as an input when TX is active. The data output pin can be any of the GDO pins (this is set by the IOCFG0.GDO0_CFG, IOCFG1.GDO1_CFG, and IOCFG2.GDO2_CFGfields). Preamble and sync word insertion/detection may or may not be active, dependent on the sync mode set by the MDMCFG2.SYNC_MODE. If preamble and sync word is disabled, all other packet handler features and FEC should also be disabled. The MCU must then handle preamble and sync word insertion and detection in software. If preamble and sync word insertion/detection is left on, all packet handling features and FEC can be used. One exception is that the address filtering feature is unavailable in synchronous serialmode. When using the packet handling features in synchronous serial mode, the CC11x1-Q1 inserts and detects the preamble and sync word and the MCU only provides/gets the data payload. This is equivalent to the recommendedFIFOoperationmode. 3.27 System Considerations and Guidelines 3.27.1 SRD Regulations International regulations and national laws regulate the use of radio receivers and transmitters. Short range devices (SRDs) for license-free operation below 1 GHz are usually operated in the 433 MHz, 868 MHz, or 915 MHz frequency bands. The CC11x1-Q1 is specifically designed for such use with its 310 MHz to 348 MHz, 420 MHz to 450 MHz, and 779 MHz to 928 MHz operating ranges. The most important regulations when using the CC11x1-Q1 in the 433 MHz, 868 MHz, or 915 MHz frequency bands are EN 300 220 (Europe) and FCC CFR47 Part 15 (USA). A summary of the most important aspects of theseregulationscanbefoundinSRDRegulationsforLicenceFreeTransceiverOperation(SWRA090). NOTE Compliance with regulations is dependent on complete system performance. It is the customer'sresponsibilitytoensurethatthesystemcomplieswithregulations. 3.27.2 Frequency Hopping and Multi-Channel Systems The 433-MHz, 868-MHz, and 915-MHz bands are shared by many systems both in industrial, office, and home environments. It is therefore recommended to use a frequency-hopping spread-spectrum (FHSS) or multi-channel protocol, because the frequency diversity makes the system more robust with respect to interference from other systems operating in the same frequency band. FHSS also combats multipath fading. CC11x1-Q1 is highly suited for FHSS or multi-channel systems due to its agile frequency synthesizer and effective communication interface. Using the packet handling support and data buffering is also beneficial insuchsystems,asthesefeaturessignificantlyoffloadthehostcontroller. Charge pump current, VCO current, and VCO capacitance array calibration data is required for each frequency when implementing frequency hopping for CC11x1-Q1. There are three ways of obtaining the calibrationdatafromthechip: 1. Frequencyhoppingwithcalibrationforeachhop.ThePLLcalibrationtimeisapproximately720µs. Theblankingintervalbetweeneachfrequencyhopisthenapproximately810µs. 2. Fastfrequencyhoppingwithoutcalibrationforeachhopcanbedonebycalibratingeachfrequencyat startupandsavingtheresultingFSCAL3,FSCAL2,andFSCAL1registervaluesinMCUmemory. Betweeneachfrequencyhop,thecalibrationprocesscanthenbereplacedbywritingtheFSCAL3, FSCAL2,andFSCAL1registervaluescorrespondingtothenextRFfrequency.ThePLLturn-ontime isapproximately90µs.Theblankingintervalbetweeneachfrequencyhopisthenapproximately 90µs.TheVCOcurrentcalibrationresultavailableinFSCAL2isnotdependentontheRFfrequency. 60 DetailedDescription Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC11x1-Q1 www.ti.com SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 NeitheristhechargepumpcurrentcalibrationresultavailableinFSCAL3.Thesamevaluecan, therefore,beusedforallfrequencies. 3. Runcalibrationonasinglefrequencyatstartup.Next,write0toFSCAL3[5:4]todisablethe charge-pumpcalibration.AfterwritingtoFSCAL3[5:4],strobeSRX(orSTX)with MCSM0.FS_AUTOCAL=1foreachnewfrequencyhop.Thatis,VCOcurrentandVCOcapacitance calibrationaredonebutnotcharge-pumpcurrentcalibration.Whenchargepumpcurrentcalibrationis disabled,thecalibrationtimeisreducedfromapproximately720µstoapproximately150µs.The blankingintervalbetweeneachfrequencyhopisthenapproximately240µs. There is a trade off between blanking time and memory space needed for storing calibration data in non-volatile memory. Solution 2 above gives the shortest blanking interval, but requires more memory space to store calibration values. Solution 3 gives approximately 570 µs smaller blanking interval than solution1. NOTE The recommended settings for TEST0.VCO_SEL_CAL_EN change with frequency. Therefore, SmartRF Studio should be used to determine the correct settings for a specific frequencybeforedoingacalibration,regardlessofwhichcalibrationmethodisused. It must be noted that the TESTn registers (n = 0, 1, or 2) content is not retained in SLEEP state, and thus itisnecessarytorewritetheseregisterswhenreturningfromtheSLEEPstate. 3.27.3 Wideband Modulation Not Using Spread Spectrum Digital modulation systems under FFC Part 15.247 include 2-FSK and GFSK modulation. A maximum peak output power of 1 W (+30 dBm) is allowed if the 6-dB bandwidth of the modulated signal exceeds 500 kHz. In addition, the peak power spectral density conducted to the antenna shall not be greater than 8dBminany3-kHzband. Operating at high data rates and frequency separation, the CC11x1-Q1 is suited for systems targeting compliance with digital modulation system as defined by FFC part 15.247. An external power amplifier is neededtoincreasetheoutputabove10dBm. 3.27.4 Data Burst Transmissions The high maximum data rate of CC11x1-Q1 allows burst transmissions. A low average data rate link (e.g., 10 kBaud), can be realized using a higher over-the-air data rate. Buffering the data and transmitting in bursts at high data rate (e.g., 500 kBaud) reduces the time in active mode and, therefore, reduces the average current consumption significantly. Reducing the time in active mode reduces the likelihood of collisionswithothersystemsinthesamefrequencyrange. 3.27.5 Continuous Transmissions In data streaming applications, the CC11x1-Q1 allows continuous transmissions at 500-kBaud effective data rate. As the modulation is done with a closed-loop PLL, there is no limitation on the length of a transmission (open-loop modulation used in some transceivers often prevents this continuous data streamingandreducestheeffectivedatarate). 3.27.6 Crystal Drift Compensation The CC11x1-Q1 has a very fine frequency resolution (see Section 2.11). This feature can be used to compensateforfrequencyoffsetanddrift. Copyright©2009–2010,TexasInstrumentsIncorporated DetailedDescription 61 SubmitDocumentationFeedback

CC11x1-Q1 SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 www.ti.com The frequency offset between an external transmitter and the receiver is measured in the CC11x1-Q1 and can be read back from the FREQEST status register as described in Section 3.10.1. The measured frequency offset can be used to calibrate the frequency using the external transmitter as the reference. That is, the received signal of the device matches the receiver's channel filter better. In the same way, the centerfrequencyofthetransmittedsignalmatchestheexternaltransmitter'ssignal. 3.27.7 Spectrum Efficient Modulation CC11x1-Q1 also allows the use of Gaussian shaped 2-FSK (GFSK). This spectrum-shaping feature improves adjacent channel power (ACP) and occupied bandwidth. In true 2-FSK systems with abrupt frequency shifting, the spectrum is inherently broad. By making the frequency shift softer, the spectrum can be made significantly narrower. Thus, higher data rates can be transmitted in the same bandwidth usingGFSK. 3.27.8 Low Cost Systems As the CC11x1-Q1 provides 250-kBaud multi-channel performance without any external filters, a very low-costsystemcanbemade. A differential antenna eliminates the need for a balun, and the dc biasing can be achieved in the antenna topology,seeFigure3-2andFigure3-3. A HC-49 type SMD crystal is used in the reference designs. Note that the crystal package strongly influencestheprice.Inasize-constrainedPCBdesignasmallerbutmoreexpensivecrystalcanbeused. 3.27.9 Battery Operated Systems In low-power applications, the SLEEP state with the crystal oscillator core switched off should be used when the CC11x1-Q1 is not active. The crystal oscillator core can be left running in the SLEEP state if start-uptimeiscritical. TheWORfunctionalityshouldbeusedinlowpowerapplications. 3.27.10 Increasing Output Power In some applications, it may be necessary to extend the link range. Adding an external power amplifier is themosteffectivewaytodothis. The power amplifier should be inserted between the antenna and the balun, and two T/R switches are neededtodisconnectthePAinRXmode(seeFigure3-24). Antenna Filter PA Balun TMS37171 T/R Switch T/R Switch Figure3-24.BlockDiagramofCC11x1-Q1WithExternalPowerAmplifier 62 DetailedDescription Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC11x1-Q1 www.ti.com SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 4 Configuration Registers 4.1 Overview The configuration of CC11x1-Q1 is done by programming 8-bit registers. The optimum configuration data based on selected system parameters are most easily found by using the SmartRF Studio software. Complete descriptions of the registers are given in the following tables. After chip reset, all the registers have default values as shown in the tables. The optimum register setting might differ from the default value. After a reset, all registers that should be different from the default value, therefore, need to be programmedthroughtheSPIinterface. There are 13 command strobe registers, listed in Table 4-1. Accessing these registers initiates the change of an internal state or mode. There are 47 normal 8-bit configuration registers, listed in Table 4-2. Many of theseregistersarefortestpurposesonlyandneednotbewrittenfornormaloperationofCC11x1-Q1. There are also 12 status registers, listed in Table 4-3. These registers, which are read-only, contain informationaboutthestatusofCC11x1-Q1. The two FIFOs are accessed through one 8-bit register. Write operations write to the TX FIFO, while read operationsreadfromtheRXFIFO. During the header byte transfer and while writing data to a register or the TX FIFO, a status byte is returnedontheSOline.ThisstatusbyteisdescribedinTable3-3. Table 4-7 summarizes the SPI address space. The address to use is given by adding the base address to the left and the burst and read/write bits on the top. Note that the burst bit has different meaning for base addressesaboveandbelow0x2F. Table4-1.CommandStrobes ADDRESS STROBENAME DESCRIPTION 0x30 SRES Resetchip. Enableandcalibratefrequencysynthesizer(ifMCSM0.FS_AUTOCAL=1).IfinRX(withCCA),go 0x31 SFSTXON toawaitstatewhereonlythesynthesizerisrunning(forquickRX/TXturnaround). 0x32 SXOFF Turnoffcrystaloscillator. Calibratefrequencysynthesizerandturnitoff.SCALcanbestrobedfromIDLEmodewithout 0x33 SCAL settingmanualcalibrationmode(MCSM0.FS_AUTOCAL=0). 0x34 SRX EnableRX.PerformcalibrationfirstifcomingfromIDLEandMCSM0.FS_AUTOCAL=1. InIDLEstate,enableTX.PerformcalibrationfirstifMCSM0.FS_AUTOCAL=1. 0x35 STX IfinRXstateandCCAisenabled,onlygotoTXifchannelisclear. 0x36 SIDLE ExitRX/TX,turnofffrequencysynthesizer,andexitWORmode,ifapplicable. StartautomaticRXpollingsequence(WOR)asdescribedinSection3.15.5ifWORCTRL.RC_PD 0x38 SWOR =0. 0x39 SPWD Enterpower-downmodewhenCSgoeshigh. 0x3A SFRX FlushtheRXFIFObuffer.OnlyissueSFRXinIDLEorRXFIFO_OVERFLOWstates. 0x3B SFTX FlushtheTXFIFObuffer.OnlyissueSFTXinIDLEorTXFIFO_UNDERFLOWstates. 0x3C SWORRST Resetreal-timeclocktoEvent1value. 0x3D SNOP Nooperation.Maybeusedtoaccessthechipstatusbyte. Copyright©2009–2010,TexasInstrumentsIncorporated ConfigurationRegisters 63 SubmitDocumentationFeedback

CC11x1-Q1 SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 www.ti.com Table4-2.ConfigurationRegisters PRESERVEDINSLEEP ADDRESS REGISTER DESCRIPTION STATE? 0x00 IOCFG2 GDO2outputpinconfiguration Yes 0x01 IOCFG1 GDO1outputpinconfiguration Yes 0x02 IOCFG0 GDO0outputpinconfiguration Yes 0x03 FIFOTHR RXFIFOandTXFIFOthresholds Yes 0x04 SYNC1 Syncword,highbyte Yes 0x05 SYNC0 Syncword,lowbyte Yes 0x06 PKTLEN Packetlength Yes 0x07 PKTCTRL1 Packetautomationcontrol Yes 0x08 PKTCTRL0 Packetautomationcontrol Yes 0x09 ADDR Deviceaddress Yes 0x0A CHANNR Channelnumber Yes 0x0B FSCTRL1 Frequencysynthesizercontrol Yes 0x0C FSCTRL0 Frequencysynthesizercontrol Yes 0x0D FREQ2 Frequencycontrolword,highbyte Yes 0x0E FREQ1 Frequencycontrolword,middlebyte Yes 0x0F FREQ0 Frequencycontrolword,lowbyte Yes 0x10 MDMCFG4 Modemconfiguration Yes 0x11 MDMCFG3 Modemconfiguration Yes 0x12 MDMCFG2 Modemconfiguration Yes 0x13 MDMCFG1 Modemconfiguration Yes 0x14 MDMCFG0 Modemconfiguration Yes 0x15 DEVIATN Modemdeviationsetting Yes 0x16 MCSM2 Mainradiocontrolstatemachineconfiguration Yes 0x17 MCSM1 Mainradiocontrolstatemachineconfiguration Yes 0x18 MCSM0 Mainradiocontrolstatemachineconfiguration Yes 0x19 FOCCFG Frequencyoffsetcompensationconfiguration Yes 0x1A BSCFG Bitsynchronizationconfiguration Yes 0x1B AGCTRL2 AGCcontrol Yes 0x1C AGCTRL1 AGCcontrol Yes 0x1D AGCTRL0 AGCcontrol Yes 0x1E WOREVT1 HighbyteEvent0timeout Yes 0x1F WOREVT0 LowbyteEvent0timeout Yes 0x20 WORCTRL Wake-on-radiocontrol Yes 0x21 FREND1 Front-endRXconfiguration Yes 0x22 FREND0 Front-endTXconfiguration Yes 0x23 FSCAL3 Frequencysynthesizercalibration Yes 0x24 FSCAL2 Frequencysynthesizercalibration Yes 0x25 FSCAL1 Frequencysynthesizercalibration Yes 0x26 FSCAL0 Frequencysynthesizercalibration Yes 0x27 RCCTRL1 RCoscillatorconfiguration Yes 0x28 RCCTRL0 RCoscillatorconfiguration Yes 0x29 FSTEST Frequencysynthesizercalibrationcontrol No 0x2A PTEST Productiontest No 0x2B AGCTEST AGCtest No 0x2C TEST2 Varioustestsettings No 0x2D TEST1 Varioustestsettings No 0x2E TEST0 Varioustestsettings No 64 ConfigurationRegisters Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC11x1-Q1 www.ti.com SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 Table4-3.StatusRegisters ADDRESS REGISTER DESCRIPTION 0x30(0xF0) PARTNUM Partnumber 0x31(0xF1) VERSION Currentversionnumber 0x32(0xF2) FREQEST Frequencyoffsetestimate 0x33(0xF3) LQI Demodulatorestimateforlinkquality 0x34(0xF4) RSSI Receivedsignalstrengthindication 0x35(0xF5) MARCSTATE Controlstatemachinestate 0x36(0xF6) WORTIME1 HighbyteofWORtimer 0x37(0xF7) WORTIME0 LowbyteofWORtimer 0x38(0xF8) PKTSTATUS CurrentGDOxstatusandpacketstatus 0x39(0xF9) VCO_VC_DAC CurrentsettingfromPLLcalibrationmodule 0x3A(0xFA) TXBYTES UnderflowandnumberofbytesintheTXFIFO 0x3B(0xFB) RXBYTES OverflowandnumberofbytesintheRXFIFO 0x3C(0xFC) RCCTRL1_STATUS LastRCoscillatorcalibrationresult 0x3D(0xFD) RCCTRL0_STATUS LastRCoscillatorcalibrationresult Table4-4.StatusByteSummary BIT FIELDNAME DESCRIPTION 7 CHIP_RDYn Stayshighuntilpowerandcrystalhavestabilized.ShouldalwaysbelowwhenusingtheSPI interface. 06:04 STATE[2:0] Indicatesthecurrentmainstatemachinemode Value State Description IDLEstate 0 IDLE (Alsoreportedforsometransitionalstatesinsteadof SETTLINGorCALIBRATE) 1 RX Receivemode 10 TX Transmitmode 11 FSTXON FastTXready 100 CALIBRATE Frequencysynthesizercalibrationisrunning 101 SETTLING PLLissettling RXFIFOhasoverflowed.Readoutanyusefuldata, 110 RXFIFO_OVERFLOW thenflushtheFIFOwithSFRX 111 TXFIFO_UNDERFLOW TXFIFOhasunderflowed.AcknowledgewithSFTX. 03:00 FIFO_BYTES_AVAILABLE[3:0] ThenumberofbytesavailableintheRXFIFOorfreebytesintheTXFIFO Table4-5.ReceivedPacketStatusByte1(FirstByteAppendedAfterData) BIT FIELDNAME DESCRIPTION 7:0 RSSI RSSIvalue Table4-6.ReceivedPacketStatusByte2(SecondByteAppendedAfterData) BIT FIELDNAME DESCRIPTION 7 CRC_OK 1:CRCforreceiveddataOK(orCRCdisabled) 0:CRCerrorinreceiveddata 6:0 LQI Indicatingthelinkquality Copyright©2009–2010,TexasInstrumentsIncorporated ConfigurationRegisters 65 SubmitDocumentationFeedback

CC11x1-Q1 SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 www.ti.com Table4-7.SPIAddressSpace WRITE READ SINGLEBYTE BURST SINGLEBYTE BURST +0x00 +0x40 +0x80 +0xC0 0x00 IOCFG2 0x01 IOCFG1 0x02 IOCFG0 0x03 FIFOTHR 0x04 SYNC1 0x05 SYNC0 0x06 PKTLEN 0x07 PKTCTRL1 0x08 PKTCTRL0 0x09 ADDR 0x0A CHANNR 0x0B FSCTRL1 0x0C FSCTRL0 0x0D FREQ2 0x0E FREQ1 0x0F FREQ0 0x10 MDMCFG4 0x11 MDMCFG3 e 0x12 MDMCFG2 sibl s 0x13 MDMCFG1 po s 0x14 MDMCFG0 es c 0x15 DEVIATN ac st 0x16 MCSM2 ur b 0x17 MCSM1 s, er 0x18 MCSM0 st gi 0x19 FOCCFG re n 0x1A BSCFG atio 0x1B AGCCTRL2 ur g 0x1C AGCCTRL1 onfi c 0x1D AGCCTRL0 W R/ 0x1E WOREVT1 0x1F WOREVT0 0x20 WORCTRL 0x21 FREND1 0x22 FREND0 0x23 FSCAL3 0x24 FSCAL2 0x25 FSCAL1 0x26 FSCAL0 0x27 RCCTRL1 0x28 RCCTRL0 0x29 FSTEST 0x2A PTEST 0x2B AGCTEST 0x2C TEST2 0x2D TEST1 0x2E TEST0 0x2F 66 ConfigurationRegisters Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC11x1-Q1 www.ti.com SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 Table4-7.SPIAddressSpace(continued) WRITE READ SINGLEBYTE BURST SINGLEBYTE BURST +0x00 +0x40 +0x80 +0xC0 0x30 SRES SRES PARTNUM s er 0x31 SFSTXON SFSTXON VERSION gist e 0x32 SXOFF SXOFF FREQEST r e 0x33 SCAL SCAL LQI byt 0x34 SRX SRX RSSI ulti m 0x35 STX STX MARCSTATE d n a 0x36 SIDLE SIDLE WORTIME1 y) nl 0x37 WORTIME0 o d 0x38 SWOR SWOR PKTSTATUS ea (r 0x39 SPWD SPWD VCO_VC_DAC s er 0x3A SFRX SFRX TXBYTES st gi e 0x3B SFTX SFTX RXBYTES r s u 0x3C SWORRST SWORRST RCCTRL1_STATUS at St 0x3D SNOP SNOP RCCTRL0_STATUS s, e 0x3E PATABLE PATABLE PATABLE PATABLE b o Str d n 0x3F TXFIFO TXFIFO RXFIFO RXFIFO ma m o C Copyright©2009–2010,TexasInstrumentsIncorporated ConfigurationRegisters 67 SubmitDocumentationFeedback

CC11x1-Q1 SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 www.ti.com 4.2 Register Details 4.2.1 Configuration Register Details – Registers With Preserved Values In Sleep State 0x00:IOCFG2–GDO2OutputPinConfiguration BIT FIELDNAME RESET R/W DESCRIPTION 7 Reserved R0 6 GDO2_INV 0 R/W Invertoutput;i.e.,selectactivelow(1)oractivehigh(0) 5:0 GDO2_CFG[5:0] 41(0x29) R/W DefaultisCHP_RDYn(seeTable3-17). 0x01:IOCFG1–GDO1OutputPinConfiguration BIT FIELDNAME RESET R/W DESCRIPTION 7 GDO_DS 0 R/W Sethigh(1)orlow(0)outputdrivestrengthontheGDOpins. 6 GDO1_INV 0 R/W Invertoutput;i.e.,selectactivelow(1)oractivehigh(0) 5:0 GDO1_CFG[5:0] 46(0x2E) R/W Defaultis3-state(seeTable3-17). 0x02:IOCFG0–GDO0OutputPinConfiguration BIT FIELDNAME RESET R/W DESCRIPTION 7 TEMP_SENSOR_ENABLE 0 R/W Enableanalogtemperaturesensor.Write0inallotherregisterbits whenusingtemperaturesensor. 6 GDO0_INV 0 R/W Invertoutput;i.e.,selectactivelow(1)oractivehigh(0) 5:0 GDO0_CFG[5:0] 63(0x3F) R/W DefaultisCLK_XOSC/192(seeTable3-17). Itisrecommendedtodisabletheclockoutputininitializationtooptimize RFperformance. 68 ConfigurationRegisters Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC11x1-Q1 www.ti.com SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 0x03:FIFOTHR–RXFIFOandTXFIFOThresholds BIT FIELDNAME RESET R/W DESCRIPTION 7 Reserved 0 R/W Write0forcompatibilitywithpossiblefutureextensions 6 ADC_RETENTION 0 R/W 0:TEST1=0x31andTEST2=0x88whenwakingupfromSLEEP 1:TEST1=0x35andTEST2=0x81whenwakingupfromSLEEP NotethatthechangesintheTESTregistersduetotheADC_RETENTIONbit settingareonlyseenINTERNALLYintheanalogpart.Thevaluesreadfrom theTESTregisterswhenwakingupfromSLEEPmodearealwaysthereset value.TheADC_RETENTIONbitshouldbesetto1beforegoingintoSLEEP modeifsettingswithanRXfilterbandwidthbelow325kHzarewantedattime ofwake-up. 5:4 CLOSE_IN_RX[1:0] 0(00) R/W Formoredetails,seeClose-inReceptionWithCC1101(SWRA147). RXAttenuation, Setting TypicalValues 0(00) 0dB 1(01) 6dB 2(10) 12dB 3(11) 18dB 3:0 FIFO_THR[3:0] 7(0111) R/W SetthethresholdfortheTXFIFOandRXFIFO.Thethresholdisexceeded whenthenumberofbytesintheFIFOisequaltoorhigherthanthethreshold value. Bytesin Bytesin Setting TXFIFO RXFIFO 0(0000) 61 4 1(0001) 57 8 2(0010) 53 12 3(0011) 49 16 4(0100) 45 20 5(0101) 41 24 6(0110) 37 28 7(0111) 33 32 8(1000) 29 36 9(1001) 25 40 10(1010) 21 44 11(1011) 17 48 12(1100) 13 52 13(1101) 9 56 14(1110) 5 60 15(1111) 1 64 0x04:SYNC1–SyncWord,HighByte BIT FIELDNAME RESET R/W DESCRIPTION 7:0 SYNC[15:8] 211(0xD3) R/W 8MSBof16-bitsyncword 0x05:SYNC0–SyncWord,LowByte BIT FIELDNAME RESET R/W DESCRIPTION 7:0 SYNC[7:0] 145(0x91) R/W 8LSBof16-bitsyncword 0x06:PKTLEN– PacketLength BIT FIELDNAME RESET R/W DESCRIPTION 7:0 PACKET_LENGTH 255(0xFF) R/W Indicatesthepacketlengthwhenfixedpacketlengthmodeisenabled.If variablepacketlengthmodeisused,thisvalueindicatesthemaximum packetlengthallowed. Copyright©2009–2010,TexasInstrumentsIncorporated ConfigurationRegisters 69 SubmitDocumentationFeedback

CC11x1-Q1 SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 www.ti.com 0x07:PKTCTRL1– PacketAutomationControl BIT FIELDNAME RESET R/W DESCRIPTION 7:5 PQT[2:0] 0(0x00) R/W Preamblequalityestimatorthreshold.Thepreamblequalityestimator increasesaninternalcounterbyoneeachtimeabitisreceivedthatis differentfromthepreviousbit,anddecreasesthecounterby8eachtime abitisreceivedthatisthesameasthelastbit. Athresholdof4×PQTforthiscounterisusedtogatesync-word detection.WhenPQT=0asyncwordisalwaysaccepted. 4 Reserved 0 R0 3 CRC_AUTOFLUSH 0 R/W EnableautomaticflushofRXFIFOwhenCRCinnotOK.Thisrequires thatonlyonepacketisintheRXFIFOandthatpacketlengthislimited totheRXFIFOsize. 2 APPEND_STATUS 1 R/W Whenenabled,twostatusbytesareappendedtothepayloadofthe packet.ThestatusbytescontainRSSIandLQIvalues,aswellasCRC OK. 1:0 ADR_CHK[1:0] 0(00) R/W Controlsaddresscheckconfigurationofreceivedpackages. Setting AddressCheckConfiguration 0(00) Noaddresscheck 1(01) Addresscheck,nobroadcast 2(10) Addresscheckand0(0x00)broadcast 3(11) Addresscheckand0(0x00)and255(0xFF)broadcast 0x08:PKTCTRL0– PacketAutomationControl BIT FIELDNAME RESET R/W DESCRIPTION 7 Reserved R0 6 WHITE_DATA 1 R/W Turndatawhiteningon/off 0:Whiteningoff 1:Whiteningon 5:4 PKT_FORMAT[1:0] 0(00) R/W FormatofRXandTXdata Setting PacketFormat 0(00) Normalmode,useFIFOsforRXandTX Synchronousserialmode.Usedforbackwards 1(01) compatibility.DatainonGDO0 RandomTXmode.SendsrandomdatausingPN9 2(10) generator.Usedfortest. Worksasnormalmode,setting0(00),inRX. Asynchronousserialmode.DatainonGDO0andData 3(11) outoneitheroftheGDO0pins 3 Reserved 0 R0 2 CRC_EN 1 R/W EnableCRC 1:CRCcalculationinTXandCRCcheckinRXenabled 0:CRCdisabledforTXandRX 1:0 LENGTH_CONFIG[1:0] 1(01) R/W Configurethepacketlength Setting PacketLengthConfiguration Fixedpacketlengthmode.Lengthconfiguredin 0(00) PKTLENregister Variablepacketlengthmode.Packetlengthconfigured 1(01) bythefirstbyteaftersyncword 2(10) Infinitepacketlengthmode 3(11) Reserved 0x09:ADDR– DeviceAddress BIT FIELDNAME RESET R/W DESCRIPTION 7:0 DEVICE_ADDR[7:0] 0(0x00) R/W Addressusedforpacketfiltration.Optionalbroadcastaddressesare0 (0x00)and255(0xFF). 70 ConfigurationRegisters Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC11x1-Q1 www.ti.com SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 0x0A:CHANNR– ChannelNumber BIT FIELDNAME RESET R/W DESCRIPTION 7:0 CHAN[7:0] 0(0x00) R/W The8-bitunsignedchannelnumber,whichismultipliedbythechannel spacingsettingandaddedtothebasefrequency. 0x0B:FSCTRL1–FrequencySynthesizerControl BIT FIELDNAME RESET R/W DESCRIPTION 7:5 Reserved R0 4:0 FREQ_IF[4:0] 15(0x0F) R/W The desired IF frequency to employ in RX. Subtracted from FS base frequency in RX and controls the digital complex mixer in the demodulator. f =(f /210)×FREQ_IF IF XOSC ThedefaultvaluegivesanIFfrequencyof381kHz,assuminga26-MHz crystal. 0x0C:FSCTRL0–FrequencySynthesizerControl BIT FIELDNAME RESET R/W DESCRIPTION 7:0 FREQOFF[7:0] 0(0x00) R/W Frequencyoffsetaddedtothebasefrequencybeforebeingusedbythe frequencysynthesizer(twoscomplement). Resolutionisf /214(1.59kHzto1.65kHz).Rangeis±202kHzto XTAL ±210kHz,dependentoncrystalfrequency. 0x0D:FREQ2– FrequencyControlWord,HighByte BIT FIELDNAME RESET R/W DESCRIPTION 7:6 FREQ[23:22] 0(00) R FREQ[23:22]isalways0(theFREQ2registerislessthan36with 26-MHzto27-MHzcrystal) 5:0 FREQ[21:16] 30(0x1E) R/W FREQ[23:22] is the base frequency for the frequency synthesizer in incrementsoff /216. XOSC f =(f /216)×FREQ[23:0] carrier XOSC 0x0E:FREQ1–FrequencyControlWord,MiddleByte BIT FIELDNAME RESET R/W DESCRIPTION 7:0 FREQ[15:8] 196(0xC4) R/W SeedescriptioninFREQ2register 0x0F:FREQ0– FrequencyControlWord,LowByte BIT FIELDNAME RESET R/W DESCRIPTION 7:0 FREQ[7:0] 236(0xEC) R/W SeedescriptioninFREQ2register 0x10:MDMCFG4–ModemConfiguration BIT FIELDNAME RESET R/W DESCRIPTION 7:6 CHANBW_E[1:0] 2(0x02) R/W 5:4 CHANBW_M[1:0] 0(0x00) R/W Setsthedecimationratioforthedelta-sigmaADCinputstreamandthus thechannelbandwidth. The default values give 203 kHz channel filter bandwidth, assuming a 26-MHzcrystal. 3:0 DRATE_E[3:0] 12(0x0C) R/W Theexponentoftheuserspecifiedsymbolrate Copyright©2009–2010,TexasInstrumentsIncorporated ConfigurationRegisters 71 SubmitDocumentationFeedback

CC11x1-Q1 SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 www.ti.com 0x11:MDMCFG3–ModemConfiguration BIT FIELDNAME RESET R/W DESCRIPTION 7:0 DRATE_M[7:0] 34(0x22) R/W The mantissa of the user specified symbol rate. The symbol rate is configuredusinganunsigned,floating-pointnumberwith9-bitmantissa and4-bitexponent.The9thbitisahidden1.Theresultingdatarateis: Thedefaultvaluesgiveadatarateof115.051kBaud(closestsettingto 115.2kBaud),assuminga26-MHzcrystal. 0x12:MDMCFG2–ModemConfiguration BIT FIELDNAME RESET R/W DESCRIPTION 7 DEM_DCFILT_OFF 0 R/W Disabledigitaldcblockingfilterbeforedemodulator. 0=Enable(bettersensitivity) 1=Disable(currentoptimized).Onlyfordatarates≤250kBaud. TherecommendedIFfrequencychangeswhenthedcblockingis disabled.UseSmartRFStudiotocalculatecorrectregistersetting. 6:4 MOD_FORMAT[2:0] 0(000) R/W Themodulationformatoftheradiosignal Setting ModulationFormat 0(000) 2-FSK 1(001) GFSK 2(010) Reserved 3(011) ASK/OOK 4(100) Reserved 5(101) Reserved 6(110) Reserved 7(111) MSK ASKissupportedonlyforoutputpowersupto–1dBm MSKissupportedonlyfordataratesabove26kBaud 3 MANCHESTER_EN 0 R/W EnablesManchesterencoding/decoding. 0=Disable 1=Enable 2:0 SYNC_MODE[2:0] 2(010) R/W Combinedsync-wordqualifiermode. Thevalues0(000)and4(100)disablespreambleandsyncword transmissioninTXandpreambleandsyncworddetectioninRX. Thevalues1(001),2(010),5(101)and6(110)enables16-bitsync wordtransmissioninTXand16-bitssyncworddetectioninRX.Only15 of16bitsneedtomatchinRXwhenusingsetting1(001)or5(101). Thevalues3(011)and7(111)enablesrepeatedsyncword transmissioninTXand32-bitssyncworddetectioninRX(only30of32 bitsneedtomatch). Setting Sync-WordQualifierMode 0(000) Nopreamble/sync 1(001) 15/16syncwordbitsdetected 2(010) 16/16syncwordbitsdetected 3(011) 30/32syncwordbitsdetected 4(100) Nopreamble/sync,carrier-senseabovethreshold 5(101) 15/16+carrier-senseabovethreshold 6(110) 16/16+carrier-senseabovethreshold 7(111) 30/32+carrier-senseabovethreshold 72 ConfigurationRegisters Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC11x1-Q1 www.ti.com SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 0x13:MDMCFG1–ModemConfiguration BIT FIELDNAME RESET R/W DESCRIPTION 7 FEC_EN 0 R/W EnableForwardErrorCorrection(FEC)withinterleavingforpacket payload 0=Disable 1=Enable(Onlysupportedforfixedpacketlengthmode,i.e. PKTCTRL0.LENGTH_CONFIG=0) 6:4 NUM_PREAMBLE[2:0] 2(010) R/W Setstheminimumnumberofpreamblebytestobetransmitted NumberofPreamble Setting Bytes 0(000) 2 1(001) 3 2(010) 4 3(011) 6 4(100) 8 5(101) 12 6(110) 16 7(111) 24 3:2 Reserved R0 1:0 CHANSPC_E[1:0] 2(10) R/W Twobitexponentofchannelspacing 0x14:MDMCFG0–ModemConfiguration BIT FIELDNAME RESET R/W DESCRIPTION 7:0 CHANSPC_M[7:0] 248(0xF8) R/W 8-bitmantissaofchannelspacing.Thechannelspacingismultipliedby the channel number CHAN and added to the base frequency. It is unsignedandhastheformat: The default values give 199.951 kHz channel spacing (the closest settingto200kHz),assuming26-MHzcrystalfrequency. 0x15:DEVIATN– ModemDeviationSetting BIT FIELDNAME RESET R/W DESCRIPTION 7 Reserved R0 Reserved 6:4 DEVIATION_E[2:0] 4(100b) R/W Deviationexponent 3 Reserved R0 Reserved 2:0 DEVIATION_M[2:0] 7(111b) R/W Transmit Specifiesthenominalfrequencydeviationfromthecarrierfora0 (–DEVIATN)and1(+DEVIATN)inamantissa-exponentformat, 2-FSK/ interpretedasa4-bitvaluewithMSBimplicit1.Theresulting GFSK frequencydeviationisgivenby: Thedefaultvaluesgive±47.607-kHzdeviationassuming 26.0-MHzcrystalfrequency. Specifiesthefractionofsymbolperiod(1/8-8/8)duringwhicha phasechangeoccurs(0:+90°,1:–90°).SeetheSmartRF MSK Studiosoftware[8]forcorrectDEVIATNsettingwhenusing MSK. ASK/ Thissettinghasnoeffect. OOK Receive Specifiestheexpectedfrequencydeviationofincomingsignal, 2-FSK/ andmustbeapproximatelycorrectfordemodulationtobe GFSK performedreliablyandrobustly. MSK/ ASK/ Thissettinghasnoeffect. OOK Copyright©2009–2010,TexasInstrumentsIncorporated ConfigurationRegisters 73 SubmitDocumentationFeedback

CC11x1-Q1 SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 www.ti.com 0x16:MCSM2– MainRadioControlStateMachineConfiguration BIT FIELDNAME RESET R/W DESCRIPTION 7:5 Reserved R0 Reserved 4 RX_TIME_RSSI 0 R/W DirectRXterminationbasedonRSSImeasurement(carriersense).For ASK/OOKmodulation,RXtimesoutifthereisnocarriersenseinthefirst8 symbolperiods. 3 RX_TIME_QUAL 0 R/W WhentheRX_TIMEtimerexpires,thechipchecksifsyncwordisfoundwhen RX_TIME_QUAL=0,oreithersyncwordisfoundorPQIissetwhen RX_TIME_QUAL=1. 2:0 RX_TIME[2:0] 7(111) R/W TimeoutforsyncwordsearchinRXforbothWORmodeandnormalRX operation.ThetimeoutisrelativetotheprogrammedEVENT0timeout. TheRXtimeoutinµsisgivenbyEVENT0×C(RX_TIME,WOR_RES)×26/X, whereCisgivenbythefollowingtable,andXisthecrystaloscillatorfrequencyin MHz. WOR_RES Setting 0 1 2 3 0(000) 3.6058 18.0288 32.4519 46.875 1(001) 1.8029 9.0144 16.226 23.4375 2(010) 0.9014 4.5072 8.113 11.7188 3(011) 0.4507 2.2536 4.0565 5.8594 4(100) 0.2254 1.1268 2.0282 2.9297 5(101) 0.1127 0.5634 1.0141 1.4648 6(110) 0.0563 0.2817 0.5071 0.7324 7(111) Untilendofpacket Asanexample,EVENT0=34666,WOR_RES=0andRX_TIME=6 correspondsto1.96-msRXtimeout,1-spollingintervaland0.195%dutycycle. NotethatWOR_RESshouldbe0or1whenusingWOR,becauseusing WOR_RES>1givesaverylowdutycycle.InapplicationswhereWORisnot usedallsettingsofWOR_REScanbeused. ThedutycycleusingWORisapproximatedby: WOR_RES Setting 0 1 0(000) 12.50% 1.95% 1(001) 6.25% 9765ppm 2(010) 3.13% 4883ppm 3(011) 1.56% 2441ppm 4(100) 0.78% NA 5(101) 0.39% NA 6(110) 0.20% NA 7(111) NA NotethattheRCoscillatormustbeenabledtousesetting0-6,becausethe timeoutcountsRCoscillatorperiods.WORmodedoesnotneedtobeenabled. Thetimeoutcounterresolutionislimited:WithRX_TIME=0,thetimeoutcountis givenbythe13MSBsofEVENT0,decreasingtothe7MSBsofEVENT0with RX_TIME=6. 74 ConfigurationRegisters Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC11x1-Q1 www.ti.com SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 0x17:MCSM1– MainRadioControlStateMachineConfiguration BIT FIELDNAME RESET R/W DESCRIPTION 7:6 Reserved R0 5:4 CCA_MODE[1:0] 3(11) R/W SelectsCCA_MODE.ReflectedinCCAsignal. Setting ClearChannelIndication 0(00) Always 1(01) IfRSSIbelowthreshold 2(10) Unlesscurrentlyreceivingapacket IfRSSIbelowthresholdunlesscurrentlyreceivinga 3(11) packet 3:2 RXOFF_MODE[1:0] 0(00) R/W Selectwhatshouldhappenwhenapackethasbeenreceived NextStateAfterFinishingPacket Setting Reception 0(00) IDLE 1(01) FSTXON 2(10) TX 3(11) StayinRX ItisnotpossibletosetRXOFF_MODEtobeTXorFSTXONandatthe sametimeuseCCA. 1:0 TXOFF_MODE[1:0] 0(00) R/W Selectwhatshouldhappenwhenapackethasbeensent(TX) NextStateAfterFinishingPacket Setting Transmission 0(00) IDLE 1(01) FSTXON 2(10) StayinTX(startsendingpreamble) 3(11) RX 0x18:MCSM0– MainRadioControlStateMachineConfiguration BIT FIELDNAME RESET R/W DESCRIPTION 7:6 Reserved R0 5:4 FS_AUTOCAL[1:0] 0(00) R/W AutomaticallycalibratewhengoingtoRXorTX,orbacktoIDLE Setting WhenToPerformAutomaticCalibration 0(00) Never(manuallycalibrateusingSCALstrobe) 1(01) WhengoingfromIDLEtoRXorTX(orFSTXON) 2(10) WhengoingfromRXorTXbacktoIDLEautomatically Every4thtimewhengoingfromRXorTXtoIDLE 3(11) automatically Insomeautomaticwake-on-radio(WOR)applications,usingsetting3(11) cansignificantlyreducecurrentconsumption. 3:2 PO_TIMEOUT 1(01) R/W Programsthenumberoftimesthesix-bitripplecountermustexpireafter XOSChasstabilizedbeforeCHP_RDYngoeslow. IfXOSCison(stable)duringpower-down,PO_TIMEOUTshouldbesetso thattheregulateddigitalsupplyvoltagehastimetostabilizebefore CHP_RDYngoeslow(PO_TIMEOUT=2recommended).Typicalstart-up timeforthevoltageregulatoris50us. IfXOSCisoffduringpower-downandtheregulateddigitalsupplyvoltage hassufficienttimetostabilizewhilewaitingforthecrystaltobestable, PO_TIMEOUTcanbesetto0.Forrobustoperationitisrecommendedto usePO_TIMEOUT=2. Setting ExpireCount TimeoutAfterXOSCStart 0(00) 1 Approximately2.3µsto2.4µs 1(01) 16 Approximately37µsto39µs 2(10) 64 Approximately149µsto155µs 3(11) 256 Approximately597µsto620µs Exacttimeoutdependsoncrystalfrequency. 1 PIN_CTRL_EN 0 R/W Enablesthepinradiocontroloption 0 XOSC_FORCE_ON 0 R/W ForcetheXOSCtostayonintheSLEEPstate. Copyright©2009–2010,TexasInstrumentsIncorporated ConfigurationRegisters 75 SubmitDocumentationFeedback

CC11x1-Q1 SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 www.ti.com 0x19:FOCCFG– FrequencyOffsetCompensationConfiguration BIT FIELDNAME RESET R/W DESCRIPTION 7:6 Reserved R0 5 FOC_BS_CS_GATE 1 R/W Ifset,thedemodulatorfreezesthefrequencyoffsetcompensationand clockrecoveryfeedbackloopsuntiltheCSsignalgoeshigh. 4:3 FOC_PRE_K[1:0] 2(10) R/W Thefrequencycompensationloopgaintobeusedbeforeasyncwordis detected. FrequencyCompensation Setting LoopGainBeforeSyncWord 0(00) K 1(01) 2K 2(10) 3K 3(11) 4K 2 FOC_POST_K 1 R/W Thefrequencycompensationloopgaintobeusedafterasyncwordis detected. FrequencyCompensation Setting LoopGainAfterSyncWord 0 SameasFOC_PRE_K 1 K/2 1:0 FOC_LIMIT[1:0] 2(10) R/W Thesaturationpointforthefrequencyoffsetcompensationalgorithm: SaturationPoint(Maximum Setting CompensatedOffset) ±0(nofrequencyoffset 0(00) compensation) 1(01) ±BW /8 CHAN 2(10) ±BW /4 CHAN 3(11) ±BW /2 CHAN FrequencyoffsetcompensationisnotsupportedforASK/OOK.Alwaysuse FOC_LIMIT=0withthesemodulationformats. 76 ConfigurationRegisters Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC11x1-Q1 www.ti.com SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 0x1A:BSCFG–BitSynchronizationConfiguration BIT FIELDNAME RESET R/W DESCRIPTION 7:6 BS_PRE_KI[1:0] 1(01) R/W Theclockrecoveryfeedbackloopintegralgaintobeusedbeforeasync wordisdetected(usedtocorrectoffsetsindatarate): ClockRecoveryLoopIntegral Setting GainBeforeSyncWord 0(00) K I 1(01) 2K I 2(10) 3K I 3(11) 4K I 5:4 BS_PRE_KP[1:0] 2(10) R/W Theclockrecoveryfeedbackloopproportionalgaintobeusedbeforea syncwordisdetected. ClockRecoveryLoop Setting ProportionalGainBefore SyncWord 0(00) K P 1(01) 2K P 2(10) 3K P 3(11) 4K P 3 BS_POST_KI 1 R/W Theclockrecoveryfeedbackloopintegralgaintobeusedafterasync wordisdetected. ClockRecoveryLoopIntegral Setting GainAfterSyncWord 0 SameasBS_PRE_KI 1 K /2 I 2 BS_POST_KP 1 R/W Theclockrecoveryfeedbackloopproportionalgaintobeusedafterasync wordisdetected. ClockRecoveryLoop Setting ProportionalGainAfterSync Word 0 SameasBS_PRE_KP 1 K P 1:0 BS_LIMIT[1:0] 0(00) R/W Thesaturationpointforthedatarateoffsetcompensationalgorithm: DataRateOffsetSaturation Setting (MaxDataRateDifference) ±0(Nodatarateoffset 0(00) compensationperformed) 1(01) ±3.125%datarateoffset 2(10) ±6.25%datarateoffset 3(11) ±12.5%datarateoffset Copyright©2009–2010,TexasInstrumentsIncorporated ConfigurationRegisters 77 SubmitDocumentationFeedback

CC11x1-Q1 SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 www.ti.com 0x1B:AGCCTRL2– AGCControl BIT FIELDNAME RESET R/W DESCRIPTION 7:6 MAX_DVGA_GAIN[1:0] 0(00) R/W ReducesthemaximumallowableDVGAgain. Setting AllowableDVGASettings 0(00) Allgainsettingscanbeused 1(01) Thehighestgainsettingcannotbeused 2(10) The2highestgainsettingscannotbeused 3(11) The3highestgainsettingscannotbeused 5:3 MAX_LNA_GAIN[2:0] 0(000) R/W SetsthemaximumallowableLNA+LNA2gainrelativetothemaximum possiblegain. Setting MaximumAllowableLNA+LNA2Gain 0(000) MaximumpossibleLNA+LNA2gain 1(001) Approximately2.6dBbelowmaximumpossiblegain 2(010) Approximately6.1dBbelowmaximumpossiblegain 3(011) Approximately7.4dBbelowmaximumpossiblegain 4(100) Approximately9.2dBbelowmaximumpossiblegain 5(101) Approximately11.5dBbelowmaximumpossiblegain 6(110) Approximately14.6dBbelowmaximumpossiblegain 7(111) Approximately17.1dBbelowmaximumpossiblegain 2:0 MAGN_TARGET[2:0] 3(011) R/W Thesebitssetthetargetvaluefortheaveragedamplitudefromthedigital channelfilter(1LSB=0dB). Setting TargetAmplitudeFromChannelFilter 0(000) 24dB 1(001) 27dB 2(010) 30dB 3(011) 33dB 4(100) 36dB 5(101) 38dB 6(110) 40dB 7(111) 42dB 78 ConfigurationRegisters Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC11x1-Q1 www.ti.com SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 0x1C:AGCCTRL1– AGCControl BIT FIELDNAME RESET R/W DESCRIPTION 7 Reserved R0 6 AGC_LNA_PRIORITY 1 R/W SelectsbetweentwodifferentstrategiesforLNAandLNA2gain adjustment.When1,theLNAgainisdecreasedfirst.When0,the LNA2gainisdecreasedtominimumbeforedecreasingLNAgain. 5:4 CARRIER_SENSE_REL_THR[1:0] 0(00) R/W Setstherelativechangethresholdforassertingcarriersense Setting CarrierSenseRelativeThreshold 0(00) Relativecarriersensethresholddisabled 1(01) 6dBincreaseinRSSIvalue 2(10) 10dBincreaseinRSSIvalue 3(11) 14dBincreaseinRSSIvalue 3:0 CARRIER_SENSE_ABS_THR[3:0] 0(0000) R/W SetstheabsoluteRSSIthresholdforassertingcarriersense.The twos-complementsignedthresholdisprogrammedinstepsof1dB andisrelativetotheMAGN_TARGETsetting. CarrierSenseAbsoluteThreshold Setting (EqualtochannelfilteramplitudewhenAGChasnot decreasedgain) -8(1000) Absolutecarriersensethresholddisabled -7(1001) 7dBbelowMAGN_TARGETsetting ⋮ ⋮ -1(1111) 1dBbelowMAGN_TARGETsetting 0(0000) AtMAGN_TARGETsetting 1(0001) 1dBaboveMAGN_TARGETsetting ⋮ ⋮ 7(0111) 7dBaboveMAGN_TARGETsetting Copyright©2009–2010,TexasInstrumentsIncorporated ConfigurationRegisters 79 SubmitDocumentationFeedback

CC11x1-Q1 SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 www.ti.com 0x1D:AGCCTRL0– AGCControl BIT FIELDNAME RESET R/W DESCRIPTION 7:6 HYST_LEVEL[1:0] 2(10) R/W Setsthelevelofhysteresisonthemagnitudedeviation(internalAGC signalthatdeterminegainchanges). Setting Description 0(00) Nohysteresis,smallsymmetricdeadzone,highgain Lowhysteresis,smallasymmetricdeadzone,medium 1(01) gain Mediumhysteresis,mediumasymmetricdeadzone, 2(10) mediumgain 3(11) Largehysteresis,largeasymmetricdeadzone,lowgain 5:4 WAIT_TIME[1:0] 1(01) R/W Setsthenumberofchannelfiltersamplesfromagainadjustmenthasbeen madeuntiltheAGCalgorithmstartsaccumulatingnewsamples. Setting ChannelFilterSamples 0(00) 8 1(01) 16 2(10) 24 3(11) 32 3:2 AGC_FREEZE[1:0] 0(00) R/W ControlswhentheAGCgainshouldbefrozen. Setting Function 0(00) Normaloperation.Alwaysadjustgainwhenrequired. Thegainsettingisfrozenwhenasyncwordhasbeen 1(01) found. Manuallyfreezetheanaloggainsettingandcontinueto 2(10) adjustthedigitalgain. Manuallyfreezesboththeanalogandthedigitalgain 3(11) setting.Usedformanuallyoverridingthegain. 1:0 FILTER_LENGTH[1:0] 1(01) R/W Setstheaveraginglengthfortheamplitudefromthechannelfilter.Setsthe OOK/ASKdecisionboundaryforOOK/ASKreception. Setting ChannelFilterSamples OOKDecision 0(00) 8 4dB 1(01) 16 8dB 2(10) 32 12dB 3(11) 64 16dB 0x1E:WOREVT1–HighByteEvent0Timeout BIT FIELDNAME RESET R/W DESCRIPTION 7:0 EVENT0[15:8] 135(0x87) R/W HighbyteofEVENT0timeoutregister 0x1F:WOREVT0– LowByteEvent0Timeout BIT FIELDNAME RESET R/W DESCRIPTION 7:0 EVENT0[7:0] 107(0x6B) R/W LowbyteofEVENT0timeoutregister. ThedefaultEVENT0valuegives1-stimeout,assuminga26-MHzcrystal. 80 ConfigurationRegisters Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC11x1-Q1 www.ti.com SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 0x20:WORCTRL– WakeOnRadioControl BIT FIELDNAME RESET R/W DESCRIPTION 7 RC_PD 1 R/W PowerdownsignaltoRCoscillator.Whenwrittento0,automaticinitial calibrationisperformed 6:4 EVENT1[2:0] 7(111) R/W Timeoutsettingfromregisterblock.DecodedtoEvent1timeout.RC oscillatorclockfrequencyequalsf /750,whichis34.7to36kHz, XOSC dependingoncrystalfrequency.Thefollowingtableliststhenumberof clockperiodsafterEvent0beforeEvent1timesout. Setting t Event1 0(000) 4(0.111to0.115ms) 1(001) 6(0.167to0.173ms) 2(010) 8(0.222to0.230ms) 3(011) 12(0.333to0.346ms) 4(100) 16(0.444to0.462ms) 5(101) 24(0.667to0.692ms) 6(110) 32(0.889to0.923ms) 7(111) 48(1.333to1.385ms) 3 RC_CAL 1 R/W Enables(1)ordisables(0)theRCoscillatorcalibration. 2 Reserved R0 1:0 WOR_RES 0(00) R/W ControlstheEvent0resolutionaswellasmaximumtimeoutoftheWOR moduleandmaximumtimeoutundernormalRXoperation:: Setting Resolution(1LSB) MaximumTimeout 0(00) 1period(28to29µs) 1.8to1.9seconds 1(01) 25periods(0.89to0.92ms) 58to61seconds 2(10) 210periods(28to30ms) 31to32minutes 3(11) 215periods(0.91to0.94s) 16.5to17.2hours NOTE WOR_RES should be 0 or 1 when using WOR, because WOR_RES > 1 results in averylowdutycycle. InnormalRXoperationallsettingsofWOR_REScanbeused. 0x21:FREND1– FrontEndRXConfiguration BIT FIELDNAME RESET R/W DESCRIPTION 7:6 LNA_CURRENT[1:0] 1(01) R/W Adjustsfront-endLNAPTATcurrentoutput 5:4 LNA2MIX_CURRENT[1:0] 1(01) R/W Adjustsfront-endPTAToutputs 3:2 LODIV_BUF_CURRENT_RX[1:0] 1(01) R/W AdjustscurrentinRXLObuffer(LOinputtomixer) 1:0 MIX_CURRENT[1:0] 2(10) R/W Adjustscurrentinmixer 0x22:FREND0– FrontEndTXConfiguration BIT FIELDNAME RESET R/W DESCRIPTION 7:6 Reserved R0 5:4 LODIV_BUF_CURRENT_TX[1:0] 1(0x01) R/W AdjustscurrentTXLObuffer(inputtoPA).Thevaluetouseinthis fieldisgivenbytheSmartRFStudiosoftware. 3 Reserved R0 2:0 PA_POWER[2:0] 0(0x00) R/W SelectsPApowersetting.ThisvalueisanindextothePATABLE, whichcanbeprogrammedwithupto8differentPAsettings.In OOK/ASKmode,thisselectsthePATABLEindextousewhen transmittinga1.PATABLEindexzeroisusedinOOK/ASKwhen transmittinga0.ThePATABLEsettingsfromindex0tothe PA_POWERvalueareusedforASKTXshaping,andforpower ramp-up/ramp-downatthestart/endoftransmissioninallTX modulationformats. Copyright©2009–2010,TexasInstrumentsIncorporated ConfigurationRegisters 81 SubmitDocumentationFeedback

CC11x1-Q1 SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 www.ti.com 0x23:FSCAL3– FrequencySynthesizerCalibration BIT FIELDNAME RESET R/W DESCRIPTION 7:6 FSCAL3[7:6] 2(0x02) R/W Frequencysynthesizercalibrationconfiguration.Thevaluetowriteinthis fieldbeforecalibrationisgivenbytheSmartRFStudiosoftware. 5:4 CHP_CURR_CAL_EN[1:0] 2(0x02) R/W Enablechargepumpcalibrationstagewhen1 3:0 FSCAL3[3:0] 9(1001) R/W Frequencysynthesizercalibrationresultregister.Digitalbitvectordefining thechargepumpoutputcurrent,onanexponentialscale: I =I ×2FSCAL3[3:0]/4 OUT 0 Fastfrequencyhoppingwithoutcalibrationforeachhopcanbedoneby calibratingearlierforeachfrequencyandsavingtheresultingFSCAL3, FSCAL2,andFSCAL1registervalues.Betweeneachfrequencyhop, calibrationcanbereplacedbywritingtheFSCAL3,FSCAL2,andFSCAL1 registervaluescorrespondingtothenextRFfrequency. 0x24:FSCAL2– FrequencySynthesizerCalibration BIT FIELDNAME RESET R/W DESCRIPTION 7:6 Reserved R0 5 VCO_CORE_H_EN 0 R/W Choosehigh(1)/low(0)VCO 4:0 FSCAL2[4:0] 10(0x0A) R/W Frequency synthesizer calibration result register. VCO current calibration resultandoverridevalue. Fast frequency hopping without calibration for each hop can be done by calibrating earlier for each frequency and saving the resulting FSCAL3, FSCAL2, and FSCAL1 register values. Between each frequency hop, calibration can be replaced by writing the FSCAL3, FSCAL2, and FSCAL1 registervaluescorrespondingtothenextRFfrequency. 0x25:FSCAL1– FrequencySynthesizerCalibration BIT FIELDNAME RESET R/W DESCRIPTION 7:6 Reserved R0 5:0 FSCAL1[5:0] 32(0x20) R/W Frequencysynthesizercalibrationresultregister.Capacitorarraysettingfor VCOcoarsetuning. Fast frequency hopping without calibration for each hop can be done by calibrating earlier for each frequency and saving the resulting FSCAL3, FSCAL2, and FSCAL1 register values. Between each frequency hop, calibration can be replaced by writing the FSCAL3, FSCAL2, and FSCAL1 registervaluescorrespondingtothenextRFfrequency. 0x26:FSCAL0– FrequencySynthesizerCalibration BIT FIELDNAME RESET R/W DESCRIPTION 7 Reserved R0 6:0 FSCAL0[6:0] 13(0x0D) R/W Frequencysynthesizercalibrationcontrol.Thevaluetouseinthisregisteris givenbytheSmartRFStudiosoftware. 0x27:RCCTRL1–RCOscillatorConfiguration BIT FIELDNAME RESET R/W DESCRIPTION 7 Reserved R0 6:0 FSCAL0[6:0] 65(0x41) R/W RCoscillatorconfiguration 0x28:RCCTRL0–RCOscillatorConfiguration BIT FIELDNAME RESET R/W DESCRIPTION 7 Reserved R0 6:0 RCCTRL0[6:0] 0(0x00) R/W RCoscillatorconfiguration 82 ConfigurationRegisters Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC11x1-Q1 www.ti.com SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 4.2.2 Configuration Register Details – Registers that Lose Programming in SLEEP State 0x29:FSTEST–FrequencySynthesizerCalibrationControl BIT FIELDNAME RESET R/W DESCRIPTION 7:0 FSTEST[7:0] 89(0x59) R/W Fortestonly.Donotwritetothisregister. 0x2A:PTEST– ProductionTest BIT FIELDNAME RESET R/W DESCRIPTION 7:0 PTEST[7:0] 127(0x7F) R/W Writing0xBFtothisregistermakestheon-chiptemperaturesensor availableintheIDLEstate.Thedefault0x7Fvalueshouldthenbewritten backbeforeleavingtheIDLEstate.Otheruseofthisregisterisfortestonly. 0x2B:AGCTEST–AGCTest BIT FIELDNAME RESET R/W DESCRIPTION 7:0 AGCTEST[7:0] 63(0x3F) R/W Fortestonly.Donotwritetothisregister. 0x2C:TEST2– VariousTestSettings BIT FIELDNAME RESET R/W DESCRIPTION 7:0 TEST2[7:0] 136(0x88) R/W ThevaluetouseinthisregisterisgivenbytheSmartRFStudiosoftware. Thisregisterisforcedto0x88or0x81whenitwakesupfromSLEEPmode, dependingontheconfigurationofFIFOTHR.ADC_RETENTION. 0x2D:TEST1– VariousTestSettings BIT FIELDNAME RESET R/W DESCRIPTION 7:0 TEST1[7:0] 49(0x31) R/W ThevaluetouseinthisregisterisgivenbytheSmartRFStudiosoftware. Thisregisterisforcedto0x31or0x35whenitwakesupfromSLEEPmode, dependingontheconfigurationofFIFOTHR.ADC_RETENTION. 0x2E:TEST0–VariousTestSettings BIT FIELDNAME RESET R/W DESCRIPTION 7:2 TEST0[7:2] 2(0x02) R/W ThevaluetouseinthisregisterisgivenbytheSmartRFStudiosoftware. 1 VCO_SEL_CAL_EN 1 R/W EnableVCOselectioncalibrationstagewhen1 0 TEST0[0] 1 R/W ThevaluetouseinthisregisterisgivenbytheSmartRFStudiosoftware. 4.2.3 Status Register Details 0x30(0xF0):PARTNUM–ChipID BIT FIELDNAME RESET R/W DESCRIPTION 7:0 PARTNUM[7:0] 0(0x00) R Chippartnumber 0x31(0xF1):VERSION–ChipID BIT FIELDNAME RESET R/W DESCRIPTION 7:0 VERSION[7:0] 4(0x04) R Chipversionnumber 0x32(0xF2):FREQEST– FrequencyOffsetEstimateFromDemodulator BIT FIELDNAME RESET R/W DESCRIPTION 7:0 FREQOFF_EST R Theestimatedfrequencyoffset(twoscomplement)ofthecarrier.Resolution isf /214(1.59to1.65kHz).Rangeis±202kHzto±210kHz,dependent XTAL onXTALfrequency. Frequency offset compensation is only supported for 2-FSK, GFSK, and MSK modulation. This register reads 0 when using ASK or OOK modulation. Copyright©2009–2010,TexasInstrumentsIncorporated ConfigurationRegisters 83 SubmitDocumentationFeedback

CC11x1-Q1 SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 www.ti.com 0x33(0xF3):LQI– DemodulatorEstimateforLinkQuality BIT FIELDNAME RESET R/W DESCRIPTION 7 CRCOK R ThelastCRCcomparisonmatched.Clearedwhenentering/restartingRX mode. 6:0 LQI_EST[6:0] R TheLinkQualityIndicatorestimateshoweasilyareceivedsignalcanbe demodulated.Calculatedoverthe64symbolsfollowingthesyncword. 0x34(0xF4):RSSI– ReceivedSignalStrengthIndication BIT FIELDNAME RESET R/W DESCRIPTION 7:0 RSSI R Receivedsignalstrengthindicator 0x35(0xF5):MARCSTATE– MainRadioControlStateMachineState BIT FIELDNAME RESET R/W DESCRIPTION 7:5 Reserved R0 4:0 MARC_STATE[4:0] R MainradiocontrolFSMstate Value StateName State(seeFigure3-15) 0(0x00) SLEEP SLEEP 1(0x01) IDLE IDLE 2(0x02) XOFF XOFF 3(0x03) VCOON_MC MANCAL 4(0x04) REGON_MC MANCAL 5(0x05) MANCAL MANCAL 6(0x06) VCOON FS_WAKEUP 7(0x07) REGON FS_WAKEUP 8(0x08) STARTCAL CALIBRATE 9(0x09) BWBOOST SETTLING 10(0x0A) FS_LOCK SETTLING 11(0x0B) IFADCON SETTLING 12(0x0C) ENDCAL CALIBRATE 13(0x0D) RX RX 14(0x0E) RX_END RX 15(0x0F) RX_RST RX 16(0x10) TXRX_SWITCH TXRX_SETTLING 17(0x11) RXFIFO_OVERFLOW RXFIFO_OVERFLOW 18(0x12) FSTXON FSTXON 19(0x13) TX TX 20(0x14) TX_END TX 21(0x15) RXTX_SWITCH RXTX_SETTLING 22(0x16) TXFIFO_UNDERFLOW TXFIFO_UNDERFLOW Note:ItisnotpossibletoreadbacktheSLEEPorXOFFstatenumbers becausesettingCSlowmakesthechipentertheIDLEmodefromthe SLEEPorXOFFstates. 0x36(0xF6):WORTIME1–HighByteofWORTime BIT FIELDNAME RESET R/W DESCRIPTION 7:0 TIME[15:8] R HighbyteoftimervalueinWORmodule 0x37(0xF7):WORTIME0–LowByteofWORTime BIT FIELDNAME RESET R/W DESCRIPTION 7:0 TIME[7:0] R LowbyteoftimervalueinWORmodule 84 ConfigurationRegisters Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC11x1-Q1 www.ti.com SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 0x38(0xF8):PKTSTATUS–CurrentGDOxStatusandPacketStatus BIT FIELDNAME RESET R/W DESCRIPTION 7 CRC_OK R ThelastCRCcomparisonmatched.Clearedwhenentering/restartingRX mode. 6 CS R Carriersense 5 PQT_REACHED R PreambleQualityreached 4 CCA R Channelisclear 3 SFD R Syncwordfound.Assertedwhensyncwordhasbeensent/received,and de-assertedattheendofthepacket.InRX,thisbitde-assertswhenthe optionaladdresscheckfailsortheradioentersRX_OVERFLOWstate.In TXthisbitde-assertsiftheradioentersTX_UNDERFLOWstate. 2 GDO2 R Current GDO2 value. Note: the reading gives the non-inverted value irrespectiveofwhatIOCFG2.GDO2_INVisprogrammedto. It is not recommended to check for PLL lock by reading PKTSTATUS[2] withGDO2_CFG=0x0A. 1 Reserved R0 0 GDO0 R CurrentGDO0value. Note: Gives the noninverted value, regardless of the IOCFG0.GDO0_INV setting. It is not recommended to check for PLL lock by reading PKTSTATUS[0] withGDO0_CFG=0x0A. 0x39(0xF9):VCO_VC_DAC– CurrentSettingfromPLLCalibrationModule BIT FIELDNAME RESET R/W DESCRIPTION 7:0 VCO_VC_DAC[7:0] R Statusregisterfortestonly 0x3A(0xFA):TXBYTES– UnderflowandNumberofBytes BIT FIELDNAME RESET R/W DESCRIPTION 7 TXFIFO_UNDERFLOW R 6:0 NUM_TXBYTES R NumberofbytesinTXFIFO 0x3B(0xFB):RXBYTES– OverflowandNumberofBytes BIT FIELDNAME RESET R/W DESCRIPTION 7 RXFIFO_OVERFLOW R 6:0 NUM_RXBYTES R NumberofbytesinRXFIFO 0x3C(0xFC):RCCTRL1_STATUS– LastRCOscillatorCalibrationResult BIT FIELDNAME RESET R/W DESCRIPTION 7 Reserved R0 6:0 RCCTRL1_STATUS[6:0] R ContainsthevaluefromthelastrunoftheRCoscillatorcalibrationroutine. Forusagedescription,seeCC1100/CC2500–Wake-On-Radio (SWRA126). 0x3D(0xFD):RCCTRL0_STATUS– LastRCOscillatorCalibrationResult BIT FIELDNAME RESET R/W DESCRIPTION 7 Reserved R0 6:0 RCCTRL0_STATUS[6:0] R ContainsthevaluefromthelastrunoftheRCoscillatorcalibrationroutine. Forusagedescription,seeCC1100/CC2500–Wake-On-Radio (SWRA126). Copyright©2009–2010,TexasInstrumentsIncorporated ConfigurationRegisters 85 SubmitDocumentationFeedback

CC11x1-Q1 SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 www.ti.com 5 Package and Shipping Information 5.1 Package Thermal Properties Table5-1.ThermalProperties ofQFN-32Package THERMALRESISTANCE Airvelocity(m/s) 0 R (K/W) 40.4 qJA 5.2 Soldering Information Therecommendationsforlead-freereflowinIPC/JEDECJ-STD-020Cshouldbefollowed. 5.3 Carrier Tape and Reel Specifications CarriertapeandreelisinaccordancewithEIASpecification481. Table5-2.CarrierTapeandReelSpecification COMPONENT REEL UNITSPER PACKAGE TAPEWIDTH HOLEPITCH PITCH DIAMETER REEL QFN-32 12mm 8mm 4mm 13inches 3000 5.4 Ordering Information Table5-3.OrderingInformation MINIMUMORDER TIPARTNUMBER DESCRIPTION QUANTITY(MOQ) CC1101IRHBRG4Q1 CC1101-Q1Transceiver,QFN-32(RHB),RoHSPb-free,–40°Cto85°C 3000(tapeandreel) CC1101TRHBRG4Q1 CC1101-Q1Transceiver,QFN-32(RHB),RoHSPb-free,–40°Cto105°C 3000(tapeandreel) CC1101QRHBRG4Q1 CC1101-Q1Transceiver,QFN-32(RHB),RoHSPb-free,–40°Cto125°C 3000(tapeandreel) CC1131IRHBRG4Q1 CC1131-Q1Receiver,QFN-32(RHB),RoHSPb-free,–40°Cto85°C 3000(tapeandreel) CC1131TRHBRG4Q1 CC1131-Q1Receiver,QFN-32(RHB),RoHSPb-free,–40°Cto105°C 3000(tapeandreel) CC1131QRHBRG4Q1 CC1131-Q1Receiver,QFN-32(RHB),RoHSPb-free,–40°Cto125°C 3000(tapeandreel) CC1151IRHBRG4Q1 CC1151-Q1Transmitter,QFN-32(RHB),RoHSPb-free,–40°Cto85°C 3000(tapeandreel) CC1151TRHBRG4Q1 CC1151-Q1Transmitter,QFN-32(RHB),RoHSPb-free,–40°Cto105°C 3000(tapeandreel) CC1151QRHBRG4Q1 CC1151-Q1Transmitter,QFN-32(RHB),RoHSPb-free,–40°Cto125°C 3000(tapeandreel) 86 PackageandShippingInformation Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback

CC11x1-Q1 www.ti.com SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 6 References [1]DN009UpgradefromCC1100toCC1101(SWRA145) [2]CC1101EM315–433MHzReferenceDesign(SWRR046) [3]CC1101EM868–915MHzReferenceDesign(SWRR045) [4]CC1101ErrataNotes(SWRZ020) [5]AN001SRDRegulationsforLicenceFreeTransceiverOperation(SWRA090) [6]AN050UsingtheCC1101intheEuropean868MHzSRDBand(SWRA146) [7]AN047CC1100/CC2500–Wake-On-Radio(SWRA126) [8]SmartRF®Studio(SWRC046) [9]CC1100CC2500ExamplesLibraries(SWRC021) [10] CC1100/CC1150DK, CC1101DK, and CC2500/CC2550DK Examples and Libraries User Manual (SWRU109) [11]DN010Close-inReceptionwithCC1101(SWRA147) [12]DN017CC11xx868/915MHzRFMatching(SWRA168) [13]DN015PermanentFrequencyOffsetCompensation(SWRA159) [14]DN006CC11xxSettingsforFCC15.247Solutions(SWRA123) [15]DN505RSSIInterpretationandTiming(SWRA114) [16]AN058AntennaSelectionGuide(SWRA161) [17]AN067WirelessMBUSImplementationwithCC1101andMSP430(SWRA234) [18]DN013ProgrammingOutputPoweronCC1101(SWRA168) [19]DN022CC11xxOOK/ASKregistersettings(SWRA215) [20]DN005CC11xxSensitivityversusFrequencyOffsetandCrystalAccuracy(SWRA122) Copyright©2009–2010,TexasInstrumentsIncorporated References 87 SubmitDocumentationFeedback

CC11x1-Q1 SWRS076B–11-07-22-013-APRIL2009–REVISEDAPRIL2010 www.ti.com Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. REVISION COMMENTS SWRS076 InitialProductPreviewrelease ChangedfirstTYPvaluefor"Currentconsumptioninpower-downmodes"inSection2.4from1.1µAto0.7µA. SWRS076A ChangedunitforrejectionparametersinSection2.5fromdBmtodB. UpdatedcurrentconsumptionvaluesinFigure3-4. SWRS076B Changeallinstancesof"387MHzto464MHz"to"420MHzto450MHz". 88 References Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback

PACKAGE OPTION ADDENDUM www.ti.com 9-Jun-2018 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) CC1101QRHBRG4Q1 ACTIVE VQFN RHB 32 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 CC1101 & no Sb/Br) QQ1 CC1131IRHBRG4Q1 ACTIVE VQFN RHB 32 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 CC1131 & no Sb/Br) IQ1 CC1131QRHBRG4Q1 ACTIVE VQFN RHB 32 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 CC1131 & no Sb/Br) QQ1 CC1151IRHBRG4Q1 ACTIVE VQFN RHB 32 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 CC1151 & no Sb/Br) IQ1 CC1151QRHBRG4Q1 ACTIVE VQFN RHB 32 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 105 CC1151 & no Sb/Br) QQ1 CC1151TRHBRG4Q1 ACTIVE VQFN RHB 32 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 CC1151 & no Sb/Br) TQ1 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 9-Jun-2018 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF CC1101-Q1 : •Catalog: CC1101 NOTE: Qualified Version Definitions: •Catalog - TI's standard catalog product Addendum-Page 2

GENERIC PACKAGE VIEW RHB 32 VQFN - 1 mm max height 5 x 5, 0.5 mm pitch PLASTIC QUAD FLATPACK - NO LEAD Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4224745/A www.ti.com

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