Product Sample & Technical Tools & Support & Folder Buy Documents Software Community CC110L SWRS109C–MAY2011–REVISEDDECEMBER2016 CC110L Value Line Transceiver 1 Device Overview 1.1 Features 1 • RFPerformance • ImprovedRangeUsingCC1190 – ProgrammableOutputPowerupto+12dBm – TheCC1190isaRangeExtenderfor – ReceiveSensitivityDownto −116dBmat 850–950MHzandisanIdealFitforCC110Lto 0.6kbps EnhanceRFPerformance – ProgrammableDataRatefrom0.6to600kbps – HighSensitivity – FrequencyBands:300–348MHz, – –118dBmat1.2kBaud,868MHz,1% 387–464MHz,and779–928MHz PacketErrorRate – 2-FSK,4-FSK,GFSK,MSK,andOOK – –120dBmat1.2kBaud,915MHz,1% Supported PacketErrorRate • DigitalFeatures – +20-dBmOutputPowerat868MHz – FlexibleSupportforPacketOrientedSystems – +26-dBmOutputPowerat915MHz – On-chipSupportforSyncWordInsertion, • General FlexiblePacketLength,andAutomaticCRC – FewExternalComponents;CompletelyOn-chip Calculation FrequencySynthesizer,NoExternalFiltersor • Low-PowerFeatures RFSwitchNeeded – 200-nASleepModeCurrentConsumption – GreenPackage:RoHSCompliantandNo AntimonyorBromine – FastStartupTime;240 μsFromSleeptoRX ModeorTXMode – SmallSize(QLP4-x4-mmPackage,20Pins) – 64-ByteRXandTXFIFO – SuitedforSystemsTargetingCompliancewith EN300220(Europe)andFCCCFRPart15 (US) – SupportforAsynchronousandSynchronous SerialTransmitModeforBackward CompatibilitywithExistingRadio CommunicationProtocols 1.2 Applications • UltraLow-PowerWirelessApplicationsOperating • IndustrialMonitoringandControl inthe315-,433-,868-,915-MHzISMorSRD • RemoteControls Bands • Toys • WirelessAlarmandSecuritySystems • HomeandBuildingAutomation 1.3 Description The CC110L is a cost optimized sub-1 GHz RF transceiver for the 300–348 MHz, 387–464 MHz, and 779–928 MHz frequency bands. The circuit is based on the popular CC1101 RF transceiver, and RF performance characteristics are identical. Two CC110L transceivers together enable a low-cost bidirectionalRFlink. The RF transceiver is integrated with a highly configurable baseband modem. The modem supports variousmodulationformatsandhasaconfigurabledatarateupto600kbps. The CC110L provides extensive hardware support for packet handling, data buffering, and burst transmissions. The main operating parameters and the 64-byte receive and transmit FIFOs of CC110L can be controlled through a serial peripheral interface (SPI). In a typical system, the CC110L will be used together with a microcontrollerandafewadditionalpassivecomponents. 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

CC110L SWRS109C–MAY2011–REVISEDDECEMBER2016 www.ti.com DeviceInformation(1) PARTNUMBER PACKAGE BODYSIZE CC110LRGP QFN(20) 4.00mm×4.00mm (1) Formoreinformationonthesedevices,seeSection8,MechanicalPackagingandOrderable Information. 1.4 Functional Block Diagram Figure1-1showsafunctionalblockdiagramofthedevice. Radio Control ADC or at O LNA dul FIF mo X R e ADC D U SCLK C M SO (GDO1) RF_P 0 FREQ Handler ace to SCISn RF_N 90 SYNTH Packet alInterf GGDDOO02 git Di PA or O at F ul FI od X M T RC OSC BIAS XOSC RBIAS XOSC_Q1 XOSC_Q2 Figure1-1.FunctionalBlockDiagram 2 DeviceOverview Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L www.ti.com SWRS109C–MAY2011–REVISEDDECEMBER2016 Table of Contents 1 DeviceOverview......................................... 1 5.12 MicrocontrollerInterfaceandPinConfiguration..... 26 .............................................. ............................ 1.1 Features 1 5.13 DataRateProgramming 27 ........................................... ................. 1.2 Applications 1 5.14 ReceiverChannelFilterBandwidth 28 1.3 Description............................................ 1 5.15 Demodulator,SymbolSynchronizer,andData ............................................. ............................ Decision 29 1.4 FunctionalBlockDiagram 2 ................. 2 Revision History......................................... 4 5.16 PacketHandlingHardwareSupport 30 ................................. 3 TerminalConfigurationandFunctions.............. 5 5.17 ModulationFormats 35 ............... .......................................... 5.18 ReceivedSignalQualifiersandRSSI 36 3.1 PinDiagram 5 ........................................ ................................... 5.19 RadioControl 40 3.2 SignalDescriptions 6 ........................................... 4 Specifications ............................................ 7 5.20 Data FIFO 45 ............................ .......................... 5.21 FrequencyProgramming 47 4.1 AbsoluteMaximumRatings 7 ................................................. ..................................... 5.22 VCO 48 4.2 Handling Ratings 7 .................................. ................ 5.23 VoltageRegulators 49 4.3 RecommendedOperatingConditions 7 ........................ .............................. 5.24 OutputPowerProgramming 50 4.4 General Characteristics 7 .... ................................. 5.25 GeneralPurposeandTestOutputControlPins 52 4.5 CurrentConsumption 8 .. 4.6 TypicalRXCurrentConsumptionOverTemperature 5.26 AsynchronousandSynchronousSerialOperation 54 ............ ............. andInputPowerLevel,868or915MHz 10 5.27 SystemConsiderationsandGuidelines 55 ................................. ............................. 4.7 RFReceiveSection 10 5.28 ConfigurationRegisters 58 ................................ .............. 4.8 RFTransmitSection 12 5.29 DevelopmentKitOrderingInformation 79 4.9 CrystalOscillator.................................... 14 6 Applications,Implementation,andLayout........ 80 ............. ........................................ 4.10 FrequencySynthesizerCharacteristics 15 6.1 BiasResistor 80 .................................. ............................. 4.11 DCCharacteristics 15 6.2 BalunandRFMatching 80 .................................... ............................................... 4.12 Power-OnReset 15 6.3 Crystal 82 ............................. .................................... 4.13 Thermal Characteristics 16 6.4 Reference Signal 82 .............................. .................................. 4.14 TypicalCharacteristics 16 6.5 AdditionalFiltering 82 5 DetailedDescription................................... 18 6.6 PowerSupplyDecoupling........................... 82 ............................................ ..................... 5.1 Overview 18 6.7 PCBLayoutRecommendations 83 5.2 FunctionalBlockDiagram........................... 18 7 DeviceandDocumentationSupport............... 84 ............................. ...................................... 5.3 ConfigurationOverview 19 7.1 DeviceSupport 84 .............................. ............................. 5.4 ConfigurationSoftware 21 7.2 DocumentationSupport 85 ..... .......................................... 5.5 4-wireSerialConfigurationandDataInterface 22 7.3 Trademarks 85 .................................... ..................... 5.6 ChipStatusByte 23 7.4 ElectrostaticDischargeCaution 85 ..................................... ............................... 5.7 Register Access 24 7.5 ExportControlNotice 86 ............................................ ............................................. 5.8 SPIRead 24 7.6 Glossary 86 .................................. ................................ 5.9 Command Strobes 24 7.7 AdditionalAcronyms 86 5.10 FIFOAccess........................................ 25 8 MechanicalPackagingandOrderable ................................... Information.............................................. 88 5.11 PATABLE Access 25 .............................. 8.1 PackagingInformation 88 Copyright©2011–2016,TexasInstrumentsIncorporated TableofContents 3 SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L SWRS109C–MAY2011–REVISEDDECEMBER2016 www.ti.com 2 Revision History NOTE:Pagenumbersforpreviousrevisionsmaydifferfrompagenumbersinthecurrentversion. ChangesfromRevisionB(June2014)toRevisionC Page • Updated/ChangedequationsinTable5-43andTable5-44................................................................... 68 4 RevisionHistory Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L www.ti.com SWRS109C–MAY2011–REVISEDDECEMBER2016 3 Terminal Configuration and Functions 3.1 Pin Diagram The CC110L pinout is shown in Figure 3-1 and Table 3-1. See Section 5.25 for details on the I/O configuration. D R A S D U A D N G BI N SI G D R G 20 19 18 17 16 SCLK1 15 AVDD SO(GDO1)2 14AVDD GDO23 13RF_N DVDD4 12 RF_P DCOUPL5 11 AVDD GND 6 7 8 9 10 Exposed die G C X A X D S O V O attach pad O n S D S 0 C D C _ _ Q Q 1 2 Figure3-1.PinoutTopView Copyright©2011–2016,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 5 SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L SWRS109C–MAY2011–REVISEDDECEMBER2016 www.ti.com 3.2 Signal Descriptions Table3-1.SignalDescriptions PinNo. PinName PinType Description 1 SCLK Digital Serialconfigurationinterface,clockinput Input 2 SO Digital Serialconfigurationinterface,dataoutput (GDO1) Output OptionalgeneraloutputpinwhenCSnishigh 3 GDO2 Digital Digitaloutputpinforgeneraluse: Output • Testsignals • FIFOstatussignals • Clearchannelindicator • Clockoutput,down-dividedfromXOSC • SerialoutputRXdata 4 DVDD Power 1.8-3.6VdigitalpowersupplyfordigitalI/O'sandforthedigitalcorevoltageregulator (Digital) 5 DCOUPL Power 1.6-2.0Vdigitalpowersupplyoutputfordecoupling (Digital) NOTE: This pin is intended for use with the CC110L only. It can not be used to provide supply voltagetootherdevices 6 GDO0 DigitalI/O Digitaloutputpinforgeneraluse: • Testsignals • FIFOstatussignals • Clearchannelindicator • Clockoutput,down-dividedfromXOSC • SerialoutputRXdata • SerialinputTXdata 7 CSn Digital Serialconfigurationinterface,chipselect Input 8 XOSC_Q1 AnalogI/O Crystaloscillatorpin1,orexternalclockinput 9 AVDD Power 1.8-3.6Vanalogpowersupplyconnection (Analog) 10 XOSC_Q2 AnalogI/O Crystaloscillatorpin2 11 AVDD Power 1.8-3.6Vanalogpowersupplyconnection (Analog) 12 RF_P RFI/O PositiveRFinputsignaltoLNAinreceivemode PositiveRFoutputsignalfromPAintransmitmode 13 RF_N RFI/O NegativeRFinputsignaltoLNAinreceivemode NegativeRFoutputsignalfromPAintransmitmode 14 AVDD Power 1.8-3.6Vanalogpowersupplyconnection (Analog) 15 AVDD Power 1.8-3.6Vanalogpowersupplyconnection (Analog) 16 GND Ground Analoggroundconnection (Analog) 17 RBIAS AnalogI/O Externalbiasresistorforreferencecurrent 18 DGUARD Power Powersupplyconnectionfordigitalnoiseisolation (Digital) 19 GND Ground Groundconnectionfordigitalnoiseisolation (Digital) 20 SI Digital Serialconfigurationinterface,datainput Input 6 TerminalConfigurationandFunctions Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L www.ti.com SWRS109C–MAY2011–REVISEDDECEMBER2016 4 Specifications 4.1 Absolute Maximum Ratings Undernocircumstancesmusttheabsolutemaximumratingsbeviolated.Stressexceedingoneormoreofthelimitingvalues maycausepermanentdamagetothedevice. Parameter Min Max Units Condition Supplyvoltage –0.3 3.9 V Allsupplypinsmusthavethesamevoltage VDD+0.3, Voltageonanydigitalpin –0.3 V max3.9 VoltageonthepinsRF_P,RF_N, –0.3 2.0 V DCOUPL,RBIAS Voltageramp-uprate 120 kV/µs InputRFlevel +10 dBm 4.2 Handling Ratings Parameter MIN MAX UNIT Storagetemperature (default) –50 150 °C range,T stg ESDStressVoltage, HumanBodyModel(HBM),perANSI/ESDA/JEDECJS001(1) 750 V VESD ChargedDeviceModel(CDM),perJJESD22-C101(2) 400 V (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. (2) JEDECdocumentJEP157statesthat250-VHBMallowssafemanufacturingwithastandardESDcontrolprocess. 4.3 Recommended Operating Conditions Parameter Min Max Unit Condition Operatingtemperature –40 85 °C Operatingsupplyvoltage 1.8 3.6 V Allsupplypinsmusthavethesamevoltage 4.4 General Characteristics Parameter Min Typ Max Unit Condition 300 348 MHz Ifusinga27MHzcrystal,thelowerfrequencylimitforthis Frequencyrange 387 464 MHz bandis392MHz 779 928 MHz 0.6 500 kBaud 2-FSK 0.6 250 kBaud GFSKandOOK Datarate 0.6 300 kBaud 4-FSK(thedatarateinkbpswillbetwicethebaudrate) OptionalManchesterencoding(thedatarateinkbpswillbe halfthebaudrate) Copyright©2011–2016,TexasInstrumentsIncorporated Specifications 7 SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L SWRS109C–MAY2011–REVISEDDECEMBER2016 www.ti.com 4.5 Current Consumption T = 25°C, VDD = 3.0 V if nothing else stated. All measurement results are obtained using SWRR046 and A SWRR045. Reduced current settings, MDMCFG2.DEM_DCFILT_OFF=1, gives a slightly lower current consumption at the cost of a reduction in sensitivity. See Section 4.7 for additional details on current consumptionandsensitivity. spacer Parameter Min Typ Max Unit Condition Voltageregulatortodigitalpartoff,registervaluesretained 0.2 1 µA (SLEEPstate).AllGDOpinsprogrammedto0x2F(HWto 0) Currentconsumption Voltageregulatortodigitalpartoff,registervalues inpowerdownmodes 100 µA retained,XOSCrunning(SLEEPstatewith MCSM0.OSC_FORCE_ONset) Voltageregulatortodigitalparton,allothermodulesin 165 µA powerdown(XOFFstate) Onlyvoltageregulatortodigitalpartandcrystaloscillator 1.7 mA running(IDLEstate) Currentconsumption Onlythefrequencysynthesizerisrunning(FSTXONstate). Thiscurrentsconsumptionisalsorepresentativeforthe 8.4 mA otherintermediatestateswhengoingfromIDLEtoRXor TX,includingthecalibrationstate Receivemode,1.2kBaud,reducedcurrent,inputat 15.4 mA sensitivitylimit Receivemode,1.2kBaud,registersettingsoptimizedfor 14.4 mA reducedcurrent,inputwellabovesensitivitylimit Receivemode,38.4kBaud,registersettingsoptimizedfor 15.2 mA reducedcurrent,inputatsensitivitylimit Receivemode,38.4kBaud,registersettingsoptimizedfor 14.3 mA Currentconsumption, reducedcurrent,inputwellabovesensitivitylimit 315MHz Receivemode,250kBaud,registersettingsoptimizedfor 16.5 mA reducedcurrent,inputatsensitivitylimit Receivemode,250kBaud,registersettingsoptimizedfor 15.1 mA reducedcurrent,inputwellabovesensitivitylimit 27.4 mA Transmitmode,+10dBmoutputpower 15.0 mA Transmitmode,0dBmoutputpower 12.3 mA Transmitmode,–6dBmoutputpower Receivemode,1.2kBaud,registersettingsoptimizedfor 16.0 mA reducedcurrent,inputatsensitivitylimit Receivemode,1.2kBaud,registersettingsoptimizedfor 15.0 mA reducedcurrent,inputwellabovesensitivitylimit Receivemode,38.4kBaud,registersettingsoptimizedfor 15.7 mA reducedcurrent,inputatsensitivitylimit Receivemode,38.4kBaud,registersettingsoptimizedfor 15.0 mA Currentconsumption, reducedcurrent,inputwellabovesensitivitylimit 433MHz Receivemode,250kBaud,registersettingsoptimizedfor 17.1 mA reducedcurrent,inputatsensitivitylimit Receivemode,250kBaud,registersettingsoptimizedfor 15.7 mA reducedcurrent,inputwellabovesensitivitylimit 29.2 mA Transmitmode,+10dBmoutputpower 16.0 mA Transmitmode,0dBmoutputpower 13.1 mA Transmitmode,–6dBmoutputpower 8 Specifications Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L www.ti.com SWRS109C–MAY2011–REVISEDDECEMBER2016 Parameter Min Typ Max Unit Condition Receivemode,1.2kBaud,registersettingsoptimizedfor reducedcurrent,inputatsensitivitylimit. 15.7 mA SeeFigure4-1throughFigure4-3forcurrentconsumption withregistersettingsoptimizedforsensitivity. Receivemode,1.2kBaud,registersettingsoptimizedfor reducedcurrent,inputwellabovesensitivitylimit. 14.7 mA SeeFigure4-1throughFigure4-3forcurrentconsumption withregistersettingsoptimizedforsensitivity. Receivemode,38.4kBaud,registersettingsoptimizedfor reducedcurrent,inputatsensitivitylimit. 15.6 mA SeeFigure4-1throughFigure4-3forcurrentconsumption withregistersettingsoptimizedforsensitivity. Receivemode,38.4kBaud,registersettingsoptimizedfor reducedcurrent,inputwellabovesensitivitylimit. 14.6 mA SeeFigure4-1throughFigure4-3forcurrentconsumption withregistersettingsoptimizedforsensitivity. Currentconsumption, Receivemode,250kBaud,registersettingsoptimizedfor 868/915MHz 16.9 mA reducedcurrent,inputatsensitivitylimit. SeeFigure4-1throughFigure4-3forcurrentconsumption withregistersettingsoptimizedforsensitivity. Receivemode,250kBaud,registersettingsoptimizedfor reducedcurrent,inputwellabovesensitivitylimit. 15.6 mA SeeFigure4-1throughFigure4-3forcurrentconsumption withregistersettingsoptimizedforsensitivity. 34.2 mA Transmitmode,+12dBmoutputpower,868MHz 30.0 mA Transmitmode,+10dBmoutputpower,868MHz 16.8 mA Transmitmode,0dBmoutputpower,868MHz 16.4 mA Transmitmode,–6dBmoutputpower,868MHz. 33.4 mA Transmitmode,+11dBmoutputpower,915MHz 30.7 mA Transmitmode,+10dBmoutputpower,915MHz 17.2 mA Transmitmode,0dBmoutputpower,915MHz 17.0 mA Transmitmode,–6dBmoutputpower,915MHz Copyright©2011–2016,TexasInstrumentsIncorporated Specifications 9 SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L SWRS109C–MAY2011–REVISEDDECEMBER2016 www.ti.com 4.5.1 Typical TX Current Consumption over Temperature and Supply Voltage, 868 MHz SupplyVoltage SupplyVoltage SupplyVoltage VDD=1.8V VDD=3.0V VDD=3.6V Temperature[°C] −40 25 85 −40 25 85 −40 25 85 Current[mA],PATABLE=0xC0,+12dBm 32.7 31.5 30.5 35.3 34.2 33.3 35.5 34.4 33.5 Current[mA],PATABLE=0xC5,+10dBm 30.1 29.2 28.3 30.9 30.0 29.4 31.1 30.3 29.6 Current[mA],PATABLE=0x50,0dBm 16.4 16.0 15.6 17.3 16.8 16.4 17.6 17.1 16.7 4.5.2 Typical TX Current Consumption over Temperature and Supply Voltage, 915 MHz SupplyVoltage SupplyVoltage SupplyVoltage VDD=1.8V VDD=3.0V VDD=3.6V Temperature[°C] −40 25 85 −40 25 85 −40 25 85 Current[mA],PATABLE=0xC0,+11dBm 31.9 30.7 29.8 34.6 33.4 32.5 34.8 33.6 32.7 Current[mA],PATABLE=0xC3,+10dBm 30.9 29.8 28.9 31.7 30.7 30.0 31.9 31.0 30.2 Current[mA],PATABLE=0x8E,0dBm 17.2 16.8 16.4 17.6 17.2 16.9 17.8 17.4 17.1 4.6 Typical RX Current Consumption Over Temperature and Input Power Level, 868 or 915 MHz SeeSection4.14.1. 4.7 RF Receive Section T =25°C,VDD=3.0Vifnothingelsestated.AllmeasurementresultsareobtainedusingSWRR046andSWRR045. A Parameter Min Typ Max Unit Condition Digitalchannelfilter Userprogrammable.Thebandwidthlimitsareproportionaltocrystal 58 812 kHz bandwidth frequency(givenvaluesassumea26.0MHzcrystal) 25MHz-1GHz –68 –57 dBm (MaximumfigureistheETSIEN300220V2.3.1limit) Above1GHz Spuriousemissions (MaximumfigureistheETSIEN300220V2.3.1limit) –66 –47 dBm Typicalradiatedspuriousemissionis–49dBmmeasuredattheVCO frequency Serialoperation.Timefromstartofreceptionuntildataisavailableon RXlatency 9 bit thereceiverdataoutputpinisequalto9bit 315MHz 1.2kBauddatarate,sensitivityoptimized,MDMCFG2.DEM_DCFILT_OFF=0 (2-FSK,1%packeterrorrate,20bytespacketlength,5.2kHzdeviation,58kHzdigitalchannelfilterbandwidth) Sensitivitycanbetradedforcurrentconsumptionbysetting MDMCFG2.DEM_DCFILT_OFF=1.Thetypicalcurrentconsumptionis Receiversensitivity –111 dBm thenreducedfrom17.2mAto15.4mAatthesensitivitylimit.The sensitivityistypicallyreducedto-109dBm 433MHz 0.6kBauddatarate,sensitivityoptimized,MDMCFG2.DEM_DCFILT_OFF=0 (GFSK,1%packeterrorrate,20bytespacketlength,14.3kHzdeviation,58kHzdigitalchannelfilterbandwidth) Receiversensitivity –116 dBm 1.2kBauddatarate,sensitivityoptimized,MDMCFG2.DEM_DCFILT_OFF=0 (GFSK,1%packeterrorrate,20bytespacketlength,5.2kHzdeviation,58kHzdigitalchannelfilterbandwidth) Sensitivitycanbetradedforcurrentconsumptionbysetting MDMCFG2.DEM_DCFILT_OFF=1.Thetypicalcurrentconsumptionis Receiversensitivity –112 dBm thenreducedfrom18.0mAto16.0mAatthesensitivitylimit.The sensitivityistypicallyreducedto–110dBm 38.4kBauddatarate,sensitivityoptimized,MDMCFG2.DEM_DCFILT_OFF=0 (GFSK,1%packeterrorrate,20bytespacketlength,20kHzdeviation,100kHzdigitalchannelfilterbandwidth) Receiversensitivity –104 dBm 10 Specifications Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L www.ti.com SWRS109C–MAY2011–REVISEDDECEMBER2016 T =25°C,VDD=3.0Vifnothingelsestated.AllmeasurementresultsareobtainedusingSWRR046andSWRR045. A Parameter Min Typ Max Unit Condition 250kBauddatarate,sensitivityoptimized,MDMCFG2.DEM_DCFILT_OFF=0 (GFSK,1%packeterrorrate,20bytespacketlength,127kHzdeviation,540kHzdigitalchannelfilterbandwidth) Receiversensitivity –95 dBm 868/915MHz 1.2kBauddatarate,sensitivityoptimized,MDMCFG2.DEM_DCFILT_OFF=0 (GFSK,1%packeterrorrate,20bytespacketlength,5.2kHzdeviation,58kHzdigitalchannelfilterbandwidth) Sensitivitycanbetradedforcurrentconsumptionbysetting MDMCFG2.DEM_DCFILT_OFF=1.Thetypicalcurrentconsumptionis Receiversensitivity –112 dBm thenreducedfrom17.7mAto15.7mAatsensitivitylimit.Thesensitivity istypicallyreducedto–109dBm Saturation –14 dBm FIFOTHR.CLOSE_IN_RX=0.SeemoreinDN010SWRA147 Desiredchannel3dBabovethesensitivitylimit. Adjacentchannelrejection 100kHzchannelspacing 37 dB ±100kHzoffset SeeFigure4-4andFigure4-5forselectivityperformanceatotheroffset frequencies IFfrequency152kHz Imagechannelrejection 31 dB Desiredchannel3dBabovethesensitivitylimit Blocking Desiredchannel3dBabovethesensitivitylimit SeeFigure4-4andFigure4-5forblockingperformanceatotheroffset ±2MHzoffset –50 dBm frequencies ±10MHzoffset –40 dBm 38.4kBauddatarate,sensitivityoptimized,MDMCFG2.DEM_DCFILT_OFF=0 (GFSK,1%packeterrorrate,20bytespacketlength,20kHzdeviation,100kHzdigitalchannelfilterbandwidth) Receiversensitivity Sensitivitycanbetradedforcurrentconsumptionbysetting MDMCFG2.DEM_DCFILT_OFF=1.Thetypicalcurrentconsumptionis –104 dBm thenreducedfrom17.7mAto15.6mAatthesensitivitylimit.The sensitivityistypicallyreducedto-102dBm Saturation –16 dBm FIFOTHR.CLOSE_IN_RX=0.SeemoreinDN010SWRA147 Adjacentchannelrejection Desiredchannel3dBabovethesensitivitylimit. 200kHzchannelspacing –200kHzoffset 12 dB SeeFigure4-6andFigure4-7forblockingperformanceatotheroffset +200kHzoffset 25 dB frequencies Imagechannelrejection IFfrequency152kHz 23 dB Desiredchannel3dBabovethesensitivitylimit Blocking Desiredchannel3dBabovethesensitivitylimit SeeFigure4-6andFigure4-7forblockingperformanceatotheroffset ±2MHzoffset –50 dBm frequencies ±10MHzoffset –40 dBm 250kBauddatarate,sensitivityoptimized,MDMCFG2.DEM_DCFILT_OFF=0 (GFSK,1%packeterrorrate,20bytespacketlength,127kHzdeviation,540kHzdigitalchannelfilterbandwidth) Sensitivitycanbetradedforcurrentconsumptionbysetting MDMCFG2.DEM_DCFILT_OFF=1.Thetypicalcurrentconsumptionis Receiversensitivity –95 dBm thenreducedfrom18.9mAto16.9mAatthesensitivitylimit.The sensitivityistypicallyreducedto-91dBm Saturation –17 dBm FIFOTHR.CLOSE_IN_RX=0.SeemoreinDN010SWRA147 Desiredchannel3dBabovethesensitivitylimit. 750-kHzchannelspacing Adjacentchannelrejection 25 dB SeeFigure4-8andFigure4-9forblockingperformanceatotheroffset frequencies IFfrequency304kHz Imagechannelrejection 14 dB Desiredchannel3dBabovethesensitivitylimit Blocking Desiredchannel3dBabovethesensitivitylimit SeeFigure4-8andFigure4-9forblockingperformanceatotheroffset frequencies Copyright©2011–2016,TexasInstrumentsIncorporated Specifications 11 SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L SWRS109C–MAY2011–REVISEDDECEMBER2016 www.ti.com 4.7.1 Typical Sensitivity over Temperature and Supply Voltage, 868 MHz, Sensitivity Optimized Setting SupplyVoltage SupplyVoltage SupplyVoltage VDD=1.8V VDD=3.0V VDD=3.6V Temperature[°C] –40 25 85 –40 25 85 –40 25 85 Sensitivity[dBm]1.2kBaud –113 –112 –110 –113 –112 –110 –113 –112 –110 Sensitivity[dBm]38.4kBaud –105 –104 –102 –105 –104 –102 –105 –104 –102 Sensitivity[dBm]250kBaud –97 –96 –92 –97 –95 –92 –97 –94 –92 4.7.2 Typical Sensitivity over Temperature and Supply Voltage, 915 MHz, Sensitivity Optimized Setting SupplyVoltage SupplyVoltage SupplyVoltage VDD=1.8V VDD=3.0V VDD=3.6V Temperature[°C] –40 25 85 –40 25 85 –40 25 85 Sensitivity[dBm]1.2kBaud –113 –112 –110 –113 –112 –110 –113 –112 –110 Sensitivity[dBm]38.4kBaud –105 –104 –102 –104 –104 –102 –105 –104 –102 Sensitivity[dBm]250kBaud –97 –94 –92 –97 –95 –92 –97 –95 –92 4.7.3 Blocking and Selectivity SeeSection4.14.2. 4.8 RF Transmit Section T =25°C,VDD=3.0V,+10dBmifnothingelsestated.AllmeasurementresultsareobtainedusingSWRR046and A SWRR045. Parameter Min Typ Max Unit Condition Differentialload impedance 315MHz 122+j31 Ω DifferentialimpedanceasseenfromtheRF-port(RF_P andRF_N)towardstheantenna. 433MHz 116+j41 Ω 868/915MHz 86.5+j43 Ω Outputpower,highest Outputpowerisprogrammable,andfullrangeis setting availableinallfrequencybands.Outputpowermaybe restrictedbyregulatorylimits. 315MHz +10 dBm SeeDesignNoteDN013SWRA168foroutputpower 433MHz +10 dBm andharmonicsfigureswhenusingmulti-layerinductors. Theoutputpoweristhentypically+10dBmwhen 868MHz +12 dBm operatingat868/915MHz. 915MHz +11 dBm Deliveredtoa50-Ωsingle-endedloadthroughtheRF matchingnetworkinSWRR046andSWRR045 Outputpowerisprogrammable,andfullrangeis Outputpower,lowest availableinallfrequencybands −30 dBm setting Deliveredtoa50-Ωsingle-endedloadthroughtheRF matchingnetworkinSWRR046andSWRR045 Harmonics,radiated MeasuredonSWRR046andSWRR045withCW, maximumoutputpower 2ndHarm,433MHz −49 dBm Theantennasusedduringtheradiatedmeasurements 3rdHarm,433MHz −40 dBm (SMAFF-433fromR.W.BadlandandNearsonS331 868/915)playapartinattenuatingtheharmonics 2ndHarm,868MHz −47 dBm Note:Allharmonicsarebelow−41.2dBmwhen 3rdHarm,868MHz −55 dBm operatinginthe902-928MHzband 2ndHarm,915MHz −50 dBm 3rdHarm,915MHz −54 dBm Harmonics,conducted Measuredwith+10dBmCWat315MHzand433MHz 315MHz <−35 dBm Frequenciesbelow960MHz <−53 dBm Frequenciesabove960MHz 12 Specifications Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L www.ti.com SWRS109C–MAY2011–REVISEDDECEMBER2016 T =25°C,VDD=3.0V,+10dBmifnothingelsestated.AllmeasurementresultsareobtainedusingSWRR046and A SWRR045. Parameter Min Typ Max Unit Condition 433MHz −43 dBm Frequenciesbelow1GHz <−45 dBm Frequenciesabove1GHz 868MHz2ndHarm −36 dBm Measuredwith+12dBmCWat868MHz otherharmonics <−46 dBm 915MHz2ndHarm −34 dBm Measuredwith+11dBmCWat915MHz(requirementis otherharmonics −20dBcunderFCC15.247) <−50 dBm Spuriousemissions Measuredwith+10dBmCWat315MHzand433MHz conducted,harmonics notincluded 315MHz <−58 Frequenciesbelow960MHz <−53 Frequenciesabove960MHz 433MHz <−50 Frequenciesbelow1GHz <−54 Frequenciesabove1GHz <−56 Frequencieswithin47-74,87.5-118,174-230,470-862 MHz Measuredwith+12dBmCWat868MHz 868MHz <−50 Frequenciesbelow1GHz <−52 Frequenciesabove1GHz <−53 Frequencieswithin47-74,87.5-118,174-230,470-862 MHz Allradiatedspuriousemissionsarewithinthelimitsof ETSI.Thepeakconductedspuriousemissionis−53 dBmat699MHz(868MHz-169MHz),whichisina frequencybandlimitedto−54dBmbyEN300220 V2.3.1.Analternativefiltercanbeusedtoreducethe emissionat699MHzbelow−54dBm,forconducted measurements,andisshowninFigure6-2.Seemore informationinDN017SWRA168. Forcompliancewithmodulationbandwidthrequirements underEN300220V2.3.1inthe863to870MHz frequencyrangeitisrecommendedtousea26MHz crystalforfrequenciesbelow869MHzanda27MHz crystalforfrequenciesabove869MHz. Measuredwith+11dBmCWat915MHz <−51 Frequenciesbelow960MHz 915MHz <−54 Frequenciesabove960MHz TXlatency 8 bit Serialoperation.Timefromsamplingthedataonthe transmitterdatainputpinuntilitisobservedontheRF outputports Copyright©2011–2016,TexasInstrumentsIncorporated Specifications 13 SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L SWRS109C–MAY2011–REVISEDDECEMBER2016 www.ti.com 4.8.1 Typical Variation in Output Power over Temperature and Supply Voltage, 868 MHz SupplyVoltage SupplyVoltage SupplyVoltage VDD=1.8V VDD=3.0V VDD=3.6V Temperature[°C] −40 25 85 −40 25 85 −40 25 85 OutputPower[dBm],PATABLE=0xC0,+12dBm 12 11 10 12 12 11 12 12 11 OutputPower[dBm],PATABLE=0xC5,+10dBm 11 10 9 11 10 10 11 10 10 OutputPower[dBm],PATABLE=0x50,0dBm 1 0 -1 2 1 0 2 1 0 4.8.2 Typical Variation in Output Power over Temperature and Supply Voltage, 915 MHz SupplyVoltage SupplyVoltage SupplyVoltage VDD=1.8V VDD=3.0V VDD=3.6V Temperature[°C] −40 25 85 −40 25 85 −40 25 85 OutputPower[dBm],PATABLE=0xC0,+11dBm 11 10 10 12 11 11 12 11 11 OutputPower[dBm],PATABLE=0x8E,+0dBm 2 1 0 2 1 0 2 1 0 4.9 Crystal Oscillator T =25°C,VDD=3.0Vifnothingelseisstated.AllmeasurementresultsobtainedusingSWRR046andSWRR045. A Parameter Min Typ Max Unit Condition Forcompliancewithmodulationbandwidth requirementsunderEN300220V2.3.1inthe 863to870MHzfrequencyrangeitis Crystalfrequency 26 26 27 MHz recommendedtousea26MHzcrystalfor frequenciesbelow869MHzanda27MHz crystalforfrequenciesabove869MHz. Thisisthetotaltoleranceincludinga)initial tolerance,b)crystalloading,c)aging,andd) Tolerance ±40 ppm temperaturedependence.Theacceptable crystaltolerancedependsonRFfrequency andchannelspacing/bandwidth. Loadcapacitance 10 13 20 pF Simulatedoveroperatingconditions ESR 100 Ω Thisparameteristoalargedegreecrystal Start-uptime 150 µs dependent.MeasuredonSWRR046and SWRR045usingcrystalAT-41CD2fromNDK 14 Specifications Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L www.ti.com SWRS109C–MAY2011–REVISEDDECEMBER2016 4.10 Frequency Synthesizer Characteristics T =25°C,VDD=3.0Vifnothingelseisstated.AllmeasurementresultsareobtainedusingSWRR046andSWRR045.Min A figuresaregivenusinga27-MHzcrystal.Typicalandmaximumfiguresaregivenusinga26-MHzcrystal. Parameter Min Typ Max Unit Condition Programmedfrequencyresolution 397 F /216 412 Hz 26-to27-MHzcrystal.Theresolution(inHz) XOSC isequalforallfrequencybands Givenbycrystalused.Requiredaccuracy (includingtemperatureandaging)depends Synthesizerfrequencytolerance ±40 ppm onfrequencybandandchannelbandwidth/ spacing RFcarrierphasenoise –92 dBc/Hz at50kHzoffsetfromcarrier RFcarrierphasenoise –92 dBc/Hz at100kHzoffsetfromcarrier RFcarrierphasenoise –92 dBc/Hz at200kHzoffsetfromcarrier RFcarrierphasenoise –98 dBc/Hz at500kHzoffsetfromcarrier RFcarrierphasenoise –107 dBc/Hz at1MHzoffsetfromcarrier RFcarrierphasenoise –113 dBc/Hz at2MHzoffsetfromcarrier RFcarrierphasenoise –119 dBc/Hz at5MHzoffsetfromcarrier RFcarrierphasenoise –129 dBc/Hz at10MHzoffsetfromcarrier TimefromleavingtheIDLEstateuntilarriving PLLturn-onorhoptime intheRX,FSTXON,orTXstate,whennot 72 75 75 µs (SeeTable5-11) performingcalibration.Crystaloscillator running. PLLRX/TXsettlingtime Settlingtimeforthe1×IFfrequencystepfrom 29 30 30 µs (SeeTable5-11) RXtoTX PLLTX/RXsettlingtime Settlingtimeforthe1×IFfrequencystepfrom 30 31 31 µs (SeeTable5-11) TXtoRX.250kbpsdatarate. Calibrationcanbeinitiatedmanuallyor PLLcalibrationtime 685 712 724 µs automaticallybeforeenteringorafterleaving (SeeTable5-12) RX/TX 4.11 DC Characteristics T =25°Cifnothingelsestated. A DigitalInputs/Outputs Min Max Unit Condition Logic"0"inputvoltage 0 0.7 V Logic"1"inputvoltage VDD–0.7 VDD V Logic"0"outputvoltage 0 0.5 V Forupto4mAoutputcurrent Logic"1"outputvoltage VDD–0.3 VDD V Forupto4mAoutputcurrent Logic"0"inputcurrent N/A –50 nA Inputequals0V Logic"1"inputcurrent N/A 50 nA InputequalsVDD 4.12 Power-On Reset ForproperPower-On-ResetfunctionalitythepowersupplyshouldcomplywiththerequirementsinSection4.12.Otherwise, thechipshouldbeassumedtohaveunknownstateuntiltransmittinganSRESstrobeovertheSPIinterface.See Section5.19.1,Power-OnStart-UpSequence,forfurtherdetails. Parameter Min Typ Max Unit Condition Power-upramp-uptime 5 ms From0Vuntilreaching1.8V Minimumtimebetweenpower-onandpower- Powerofftime 1 ms off Copyright©2011–2016,TexasInstrumentsIncorporated Specifications 15 SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L SWRS109C–MAY2011–REVISEDDECEMBER2016 www.ti.com 4.13 Thermal Characteristics NAME DESCRIPTION QFN(°C/W) R Junction-to-ambientthermalresistance 47 θJA R Junction-to-case(top)thermalresistance 45 θJC(top) R Junction-to-boardthermalresistance 13.6 θJB R Junction-to-case(bottom)thermalresistance 5.12 θJC(bot) 4.14 Typical Characteristics 4.14.1 Typical Characteristics, RX Current Consumption 17.8 17.8 25°C –40(cid:131)C 17.6 –40(cid:131)C 17.6 25°C 85°C 85°C 17.4 17.4 A) 17.2 A) 17.2 m m nt (17.0 nt (17.0 e e Curr16.8 Curr16.8 16.6 16.6 16.4 16.4 16.2 16.2 –110 –90 –70 –50 –30 –10 –100 –80 –60 –40 –20 Input Power Level (dBm) Input Power Level (dBm) C001 C002 Figure4-1.TypicalRXCurrentConsumptionOverTemperature Figure4-2.TypicalRXCurrentConsumptionOverTemperature andInputPowerLevel,868or915MHz,SensitivityOptimized andInputPowerLevel,868or915MHz,SensitivityOptimized Setting–1.2kBaudGFSK Setting–38.4kBaudGFSK 19.5 –40(cid:131)C 25°C 19.0 85°C A) 18.5 m nt (18.0 e urr C17.5 17.0 16.5 –100 –80 –60 –40 –20 Input Power Level (dBm) C003 Figure4-3.TypicalRXCurrentConsumptionOverTemperatureandInputPowerLevel,868or915MHz,SensitivityOptimized Setting–250kBaudGFSK 16 Specifications Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L www.ti.com SWRS109C–MAY2011–REVISEDDECEMBER2016 4.14.2 Typical Characteristics, Blocking and Selectivity 80 60 70 50 60 50 40 ng (dB) 3400 vity (dB) 30 Blocki 20 Selecti 20 10 10 0 0 –10 –20 –10 –40 –30 –20 –10 0 10 20 30 40 –1.0 –0.8 –0.6 –0.4 –0.2 0.0 0.2 0.4 0.6 0.8 1.0 Offset (MHz) Offset (MHz) C004 C005 Figure4-4.TypicalBlockingat1.2kBaudDataRate,868.3MHz, Figure4-5.TypicalSelectivityat1.2kBaudDataRate,868.3 GFSK,5.2kHzDeviation.IFis152.3kHzandtheDigitalChannel MHz,GFSK,5.2kHzDeviation.IFis152.3kHzandtheDigital FilterBandwidthis58kHz ChannelFilterBandwidthis58kHz 70 50 60 40 50 30 ng (dB) 3400 vity (dB) 20 Blocki 1200 Selecti 10 0 0 –10 –10 –20 –20 –40 –30 –20 –10 0 10 20 30 40 –1.0 –0.8 –0.6 –0.4 –0.2 0.0 0.2 0.4 0.6 0.8 1.0 Offset (MHz) Offset (MHz) C006 C007 Figure4-6.TypicalBlockingat38.4kBaudDataRate,868MHz, Figure4-7.TypicalSelectivityat38.4kBaudDataRate,868MHz, GFSK,20kHzDeviation.IFis152.3kHzandtheDigitalChannel GFSK,20kHzDeviation.IFis152.3kHzandtheDigitalChannel FilterBandwidthis100kHz FilterBandwidthis100kHz 60 50 50 40 40 30 ng (dB) 2300 vity (dB) 20 Blocki 10 Selecti 10 0 0 –10 –10 –20 –20 –40 –30 –20 –10 0 10 20 30 40 –2.0 –1.5 –1.0 –0.5 0.0 0.5 1.0 1.5 2.0 Offset (MHz) Offset (MHz) C008 C009 Figure4-8.TypicalBlockingat250kBaudDataRate,868MHz, Figure4-9.TypicalSelectivityat250kBaudDataRate,868MHz, GFSK,IFis304kHzandtheDigitalChannelFilterBandwidthis GFSK,IFis304kHzandtheDigitalChannelFilterBandwidthis 540kHz 540kHz Copyright©2011–2016,TexasInstrumentsIncorporated Specifications 17 SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L SWRS109C–MAY2011–REVISEDDECEMBER2016 www.ti.com 5 Detailed Description 5.1 Overview CC110L features a low-IF receiver. The received RF signal is amplified by the low-noise amplifier (LNA) and down-converted in quadrature (I and Q) to the intermediate frequency (IF). At IF, the I/Q signals are digitized by the ADCs. Automatic gain control (AGC), fine channel filtering, demodulation, and bit/packet synchronizationareperformeddigitally. The transmitter part of CC110L is based on direct synthesis of the RF frequency. The frequency synthesizer includes a completely on-chip LC VCO and a 90-degree phase shifter for generating the I and QLOsignalstothedown-conversionmixersinreceivemode. A crystal is to be connected to XOSC_Q1 and XOSC_Q2. The crystal oscillator generates the reference frequencyforthesynthesizer,aswellasclocksfortheADCandthedigitalpart. A4-wireSPIisusedforconfigurationanddatabufferaccess. Thedigitalbasebandincludessupportforchannelconfiguration,packethandling,anddatabuffering. 5.2 Functional Block Diagram AsimplifiedblockdiagramofCC110LisshowninFigure5-1. Radio Control ADC or at O LNA dul FIF mo X R e ADC D U SCLK C M SO (GDO1) RF_P 0 FREQ Handler ace to SCISn RF_N 90 SYNTH Packet alInterf GGDDOO02 git Di PA or O at F ul FI od X M T RC OSC BIAS XOSC RBIAS XOSC_Q1 XOSC_Q2 Figure5-1.CC110LSimplifiedBlockDiagram 18 DetailedDescription Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L www.ti.com SWRS109C–MAY2011–REVISEDDECEMBER2016 5.3 Configuration Overview CC110L can be configured to achieve optimum performance for many different applications. Configuration is done using the SPI interface. See Section 5.5 for more description of the SPI interface. The following keyparameterscanbeprogrammed: • Power-down/powerupmode • Crystaloscillatorpower-up/power-down • Receive/transmitmode • Carrierfrequency/RFchannel • Datarate • Modulationformat • RXchannelfilterbandwidth • RFoutputpower • Databufferingwithseparate64-byteRXandTXFIFOs • Packetradiohardwaresupport DetailsofeachconfigurationregistercanbefoundinSection5.28. Figure 5-2 shows a simplified state diagram that explains the main CC110L states together with typical usage and current consumption. For detailed information on controlling the CC110L state machine, and a completestatediagram,seeSection5.19. Copyright©2011–2016,TexasInstrumentsIncorporated DetailedDescription 19 SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L SWRS109C–MAY2011–REVISEDDECEMBER2016 www.ti.com Sleep SIDLE SPWD Lowest power mode. Most register values are retained. Typ. current consumption: Default state when the radio is not 200 nA receiving or transmitting.Typ. CSn = 0 current consumption: 1.7 mA. IDLE SXOFF Used for calibrating frequency SCAL synthesizer upfront (entering CSn = 0 All register values are receive or transmit mode can Manual freq. Crystal retained.Typ. current then be done quicker). synth. calibration SRX, STX, or SFSTXON oscillator off consumption: 165 µA. Transitional state.Typ. current consumption: 8.4 mA. Frequency Frequency synthesizer is turned on, can optionally be synthesizer startup, calibrated, and then settles to the correct frequency. SFSTXON optional calibration, Transitional state.Typ. current consumption: 8.4 mA. Frequency synthesizer is on, settling ready to start transmitting. Frequency Transmission starts very synthesizer on quickly after receiving the STX command strobe.Typ. current STX consumption: 8.4 mA. SRX STX TXOFF_MODE = 01 SFSTXON or RXOFF_MODE = 01 Typ. current consumption: STX or RXOFF_MODE=10 Typ. current 16.8 mAat 0 dBm output Transmit mode Receive mode consumption: power from 14.7 mA(strong SRX orTXOFF_MODE = 11 input signal) to 15.7 mA (weak input signal). TXOFF_MODE = 00 RXOFF_MODE = 00 Optional transitional state.Typ. current consumption: 8.4 mA. In Normal mode, this state is In Normal mode, this state is entered if theTX FIFO TX FIFO Optional freq. RX FIFO entered if the RX FIFO becomes empty in the middle underflow synth. calibration overflow overflows.Typ. current of a packet.Typ. current consumption: 1.7 mA. consumption: 1.7 mA. SFTX SFRX IDLE Figure5-2.SimplifiedRadioControlStateDiagram,withTypicalCurrentConsumptionat1.2kBaudData RateandMDMCFG2.DEM_DCFILT_OFF=1(currentoptimized) –FrequencyBand=868MHz 20 DetailedDescription Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L www.ti.com SWRS109C–MAY2011–REVISEDDECEMBER2016 5.4 Configuration Software CC110L can be configured using the SmartRF™ Studio software SWRC176. The SmartRF Studio software is highly recommended for obtaining optimum register settings, and for evaluating performance andfunctionality. Afterchipreset,alltheregistershavedefaultvaluesasshownSection5.28. The optimum register setting might differ from the default value. After a reset all registers that shall be differentfromthedefaultvaluethereforeneedstobeprogrammedthroughtheSPIinterface. Copyright©2011–2016,TexasInstrumentsIncorporated DetailedDescription 21 SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L SWRS109C–MAY2011–REVISEDDECEMBER2016 www.ti.com 5.5 4-wire Serial Configuration and Data Interface CC110L is configured through a simple 4-wire SPI-compatible interface (SI, SO, SCLK and CSn) where CC110L is the slave. This interface is also used to read and write buffered data. All transfers on the SPI interfacearedonemostsignificantbitfirst. All transactions on the SPI interface start with a header byte containing a R/W bit, a burst access bit (B), anda6-bitaddress(A5–A0). The CSn pin must be kept low during transfers on the SPI bus. If CSn goes high during the transfer of a header byte or during read/write from/to a register, the transfer will be cancelled. The timing for the addressanddatatransferontheSPIinterfaceisshowninFigure5-3 withreferencetoTable5-1. When CSn is pulled low, the MCU must wait until CC110L SO pin goes low before starting to transfer the header byte. This indicates that the crystal is running. Unless the chip was in the SLEEP or XOFF states, theSOpinwillalwaysgolowimmediatelyaftertakingCSnlow. t t t t t t sp ch cl sd hd ns SCLK: CSn: Write to register: SI X 0 B A5 A4 A3 A2 A1 A0 X DW7 DW6 DW5 DW4 DW3 DW2 DW1 DW0 X SO Hi-Z S7 B S5 S4 S3 S2 S1 S0 S7 S6 S5 S4 S3 S2 S1 S0 Hi-Z Read from register: SI X 1 B A5 A4 A3 A2 A1 A0 X SO Hi-Z S7 B S5 S4 S3 S2 S1 S0 DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 Hi-Z Figure5-3.ConfigurationRegistersWriteandReadOperations Table5-1.SPIInterfaceTimingRequirements Parameter Description Min Max Units SCLKfrequency 100nsdelayinsertedbetweenaddressbyteanddatabyte(singleaccess),or – 10 betweenaddressanddata,andbetweeneachdatabyte(burstaccess). f SCLKfrequency,singleaccess MHz SCLK – 9 Nodelaybetweenaddressanddatabyte SCLKfrequency,burstaccess – 6.5 Nodelaybetweenaddressanddatabyte,orbetweendatabytes t CSnlowtopositiveedgeonSCLK,inpower-downmode 150 – µs sp,pd t CSnlowtopositiveedgeonSCLK,inactivemode 20 – ns sp t Clockhigh 50 – ns ch t Clocklow 50 – ns cl t Clockrisetime – 40 ns rise t Clockfalltime – 40 ns fall Setupdata(negativeSCLKedge)topositiveedgeon Singleaccess 55 – t SCLK(tsdappliesbetweenaddressanddatabytes, ns sd andbetweendatabytes) Burstaccess 76 – t HolddataafterpositiveedgeonSCLK 20 – ns hd t NegativeedgeonSCLKtoCSnhigh. 20 – ns ns 22 DetailedDescription Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L www.ti.com SWRS109C–MAY2011–REVISEDDECEMBER2016 NOTE The minimum t figure in Table 5-1 can be used in cases where the user does not read sp,pd the CHIP_RDYn signal. CSn low to positive edge on SCLK when the chip is woken from power-downdependsonthestart-uptimeofthecrystalbeingused.The150μsinTable5-1 is the crystal oscillator start-up time measured on SWRR046 and SWRR045 using crystal AT-41CD2fromNDK. 5.6 Chip Status Byte When the header byte, data byte, or command strobe is sent on the SPI interface, the chip status byte is sent by the CC110L on the SO pin. The status byte contains key status signals, useful for the MCU. The first bit, s7, is the CHIP_RDYn signal and this signal must go low before the first positive edge of SCLK. TheCHIP_RDYnsignalindicatesthatthecrystalisrunning. Bits6,5,and4comprisetheSTATE value.Thisvaluereflectsthestateofthechip.TheXOSCandpower to the digital core are on in the IDLE state, but all other modules are in power down. The frequency and channel configuration should only be updated when the chip is in this state. The RX state will be active whenthechipisinreceivemode.Likewise,TXisactivewhenthechipistransmitting. The last four bits (3:0) in the status byte contains FIFO_BYTES_AVAILABLE. For read operations (the R/W bit in the header byte is set to 1), the FIFO_BYTES_AVAILABLE field contains the number of bytes available for reading from the RX FIFO. For write operations (the R/W bit in the header byte is set to 0), the FIFO_BYTES_AVAILABLE field contains the number of bytes that can be written to the TX FIFO. WhenFIFO_BYTES_AVAILABLE=15,15ormorebytesareavailable/free. Table5-2givesastatusbytesummary. Table5-2.StatusByteSummary Bits Name Description Stayshighuntilpowerandcrystalhavestabilized.Shouldalwaysbelowwhen 7 CHIP_RDYn usingtheSPIinterface. Indicatesthecurrentmainstatemachinemode Value State Description IDLEstate (Alsoreportedforsometransitional 000 IDLE statesinsteadofSETTLINGor CALIBRATE) 001 RX Receivemode 010 TX Transmitmode 6:4 STATE[2:0] 011 FSTXON FastTXready Frequencysynthesizercalibrationis 100 CALIBRATE running 101 SETTLING PLLissettling RXFIFOhasoverflowed.Readoutany 110 RXFIFO_OVERFLOW usefuldata,thenflushtheFIFOwith SFRX TXFIFOhasunderflowed.Acknowledge 111 TXFIFO_UNDERFLOW withSFTX 3:0 FIFO_BYTES_AVAILABLE[3:0] ThenumberofbytesavailableintheRXFIFOorfreebytesintheTXFIFO Copyright©2011–2016,TexasInstrumentsIncorporated DetailedDescription 23 SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L SWRS109C–MAY2011–REVISEDDECEMBER2016 www.ti.com 5.7 Register Access The configuration registers on the CC110L are located on SPI addresses from 0x00 to 0x2E. Table 5-20 lists all configuration registers. It is highly recommended to use SmartRF Studio SWRC176 to generate optimum register settings. The detailed description of each register is found in Section 5.28.1 and Section 5.28.2. All configuration registers can be both written to and read. The R/W bit controls if the register should be written to or read. When writing to registers, the status byte is sent on the SO pin each time a header byte or data byte is transmitted on the SI pin. When reading from registers, the status byte issentontheSOpineachtimeaheaderbyteistransmittedontheSIpin. Registers with consecutive addresses can be accessed in an efficient way by setting the burst bit (B) in the header byte. The address bits (A5 - A0) set the start address in an internal address counter. This counter is incremented by one each new byte (every 8 clock pulses). The burst access is either a read or awriteaccessandmustbeterminatedbysettingCSnhigh. For register addresses in the range 0x30 - 0x3D, the burst bit is used to select between status registers when burst bit is one, and between command strobes when burst bit is zero (see Section 5.8). Because of this,burstaccessisnotavailableforstatusregistersandtheymustbeaccessedoneatatime.Thestatus registerscanonlyberead. 5.8 SPI Read When reading register fields over the SPI interface while the register fields are updated by the radio hardware (that is, MARCSTATE or TXBYTES), there is a small, but finite, probability that a single read from the register is being corrupt. As an example, the probability of any single read from TXBYTES being corrupt, assuming the maximum data rate is used, is approximately 80 ppm. Refer to the CC110L Errata NotesSWRZ037 formoredetails. 5.9 Command Strobes Command Strobes may be viewed as single byte instructions to CC110L. By addressing a command strobe register, internal sequences will be started. These commands are used to disable the crystal oscillator,enablereceivemode,enablecalibrationetc.The11commandstrobesarelistedinTable5-19. NOTE An SIDLE strobe will clear all pending command strobes until IDLE state is reached. This meansthatifforexampleanSIDLEstrobeisissuedwhiletheradioisinRXstate,anyother commandstrobesissuedbeforetheradioreachesIDLEstatewillbeignored. The command strobe registers are accessed by transferring a single header byte (no data is being transferred). That is, only the R/W bit, the burst access bit (set to 0), and the six address bits (in the range 0x30 through 0x3D) are written. The R/W bit can be either one or zero and will determine how the FIFO_BYTES_AVAILABLE fieldinthestatusbyteshouldbeinterpreted. Whenwritingcommandstrobes,thestatusbyteissentontheSOpin. A command strobe may be followed by any other SPI access without pulling CSn high. However, if an SRESstrobeisbeingissued,onewillhavetowaitforSOtogolowagainbeforethenextheaderbytecan be issued as shown in Figure 5-4. The command strobes are executed immediately, with the exception of theSPWDandtheSXOFFstrobes,whichareexecutedwhenCSngoeshigh. CSn SO SI HeaderSRES HeaderAddr Data Figure5-4.SRESCommandStrobe 24 DetailedDescription Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L www.ti.com SWRS109C–MAY2011–REVISEDDECEMBER2016 5.10 FIFO Access The 64-byte TX FIFO and the 64-byte RX FIFO are accessed through the 0x3F address. When the R/W bitiszero,theTXFIFOisaccessed,andtheRXFIFOisaccessedwhentheR/Wbitisone. TheTXFIFOiswrite-only,whiletheRXFIFOisread-only. The burst bit is used to determine if the FIFO access is a single byte access or a burst access. The single byte access method expects a header byte with the burst bit set to zero and one data byte. After the data byte, a new header byte is expected; hence, CSn can remain low. The burst access method expects one headerbyteandthenconsecutivedatabytesuntilterminatingtheaccessbysettingCSnhigh. ThefollowingheaderbytesaccesstheFIFOs: • 0x3F:SinglebyteaccesstoTXFIFO • 0x7F:BurstaccesstoTXFIFO • 0xBF:SinglebyteaccesstoRXFIFO • 0xFF:BurstaccesstoRXFIFO When writing to the TX FIFO, the status byte (see Section 5.6) is output on SO for each new data byte as shown in Figure 5-3. This status byte can be used to detect TX FIFO underflow while writing data to the TXFIFO.Notethatthestatusbytecontainsthenumberofbytesfreebeforewritingthebyteinprogressto the TX FIFO. When the last byte that fits in the TX FIFO is transmitted on SI, the status byte received concurrently on SO will indicate that one byte is free in the TX FIFO. The TX FIFO may be flushed by issuing a SFTX command strobe. Similarly, a SFRX command strobe will flush the RX FIFO. A SFTX or SFRX command strobe can only be issued in the IDLE, TXFIFO_UNDERFLOW, or RXFIFO_OVERFLOW states.BothFIFOsareflushedwhengoingtotheSLEEPstate. Figure5-5givesabriefoverviewofdifferentregisteraccesstypespossible. 5.11 PATABLE Access The 0x3E address is used to access the PATABLE, which is used for selecting PA power control settings. The SPI expects one or two data bytes after receiving the address (the burst bit must be set if two bytes are to be written). For OOK, two bytes should be written to PATABLE; the first byte after the address will set the logic 0 power level and the second byte written will set the logic 1 power level. For all other modulations formats, only one byte should be written to PATABLE. Use SmartRF Studio SWRC176 or DN013SWRA168 forrecommendedregistervaluesforagivenoutputpower. The PATABLE can also be read by setting the R/W bit to 1. The read operation can be done as a single byte or burst access, depending on how many bytes should be read (one or two). Note that pulling CSn high will reset the index counter to zero, meaning that burst access needs to be used for reading/writing the second PATABLE entry. For the same reason, if one byte is written to the PATABLE and this value is to be read out, CSn must be set high before the read access in order to set the index counter back to zero. ThecontentofthePATABLEislostwhenenteringtheSLEEPstate,exceptforthefirstbyte,meaningthat ifOOKisused,thePATABLEneedstobereprogrammedwhenwakingupfromSLEEP. CSn: Command strobe(s): HeaderStrobe HeaderStrobe HeaderStrobe Read or write register(s): HeaderReg Data HeaderReg Data HeaderReg Data Read or wrreitgeis cteornss e(bcuurtsivt)e: HeaderReg n Datan Datan + 1 Datan + 2 Rfreoamd/ toor twhreit eR Xn /+T X1 FbIyFteOs: HeaderFIFO DataByte 0 DataByte 1 DataByte 2 DataByte n - 1 DataByte n Combinations: HeaderReg Data HeaderStrobe HeaderReg Data HeaderStrobe HeaderFIFO DataByte 0 DataByte 1 Figure5-5.RegisterAccessTypes Copyright©2011–2016,TexasInstrumentsIncorporated DetailedDescription 25 SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L SWRS109C–MAY2011–REVISEDDECEMBER2016 www.ti.com 5.12 Microcontroller Interface and Pin Configuration Inatypicalsystem,CC110Lwillinterfacetoamicrocontroller.Thismicrocontrollermustbeableto: • ProgramCC110Lintodifferentmodes • Readandwritebuffereddata • Read back status information through the 4-wire SPI-bus configuration interface (SI, SO, SCLK and CSn) 5.12.1 Configuration Interface The microcontroller uses four I/O pins for the SPI configuration interface (SI, SO, SCLK and CSn). The SPIisdescribedinSection5.5. 5.12.2 General Control and Status Pins The CC110L has two dedicated configurable pins (GDO0 and GDO2) and one shared pin (GDO1) that can output internal status information useful for control software. These pins can be used to generate interruptsontheMCU.SeeSection5.25 formoredetailsonthesignalsthatcanbeprogrammed. GDO1 is shared with the SO pin in the SPI interface. The default setting for GDO1/SO is 3-state output. By selecting any other of the programming options, the GDO1/SO pin will become a generic pin. When CSnislow,thepinwillalwaysfunctionasanormalSOpin. In the synchronous and asynchronous serial modes, the GDO0 pin is used as a serial TX data input pin whileintransmitmode. 26 DetailedDescription Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L www.ti.com SWRS109C–MAY2011–REVISEDDECEMBER2016 5.13 Data Rate Programming The data rate used when transmitting, or the data rate expected in receive is programmed by the MDMCFG3.DRATE_M and the MDMCFG4.DRATE_E configuration registers. The data rate is given by theformulabelow.Astheformulashows,theprogrammeddataratedependsonthecrystalfrequency. (256+DRATE_M)×2DRATE_E R = ׃ DATA 228 XOSC (1) Thefollowingapproachcanbeusedtofindsuitablevaluesforagivendatarate: æR ×220 ö DRATE_E=log ç DATA ÷ 2ç ÷ è ƒXOSC ø (2) R ×228 DRATE_M= DATA -256 ƒ ×2DRATE_E XOSC (3) If DRATE_M is rounded to the nearest integer and becomes 256, increment DRATE_E and use DRATE_M=0. Thedataratecanbesetfrom0.6kBaudto500kBaudwiththeminimumstepsizeaccordingtoTable5-3. SeeSection4.4fortheminimumandmaximumdataratesforthedifferentmodulationformats. Table5-3.DataRateStepSize(Assuminga26-MHzCrystal) MinDataRate[kBaud] TypicalDataRate[kBaud] MaxDataRate[kBaud] DatarateStepSize[kBaud] 0.6 1.0 0.79 0.0015 0.79 1.2 1.58 0.0031 1.59 2.4 3.17 0.0062 3.17 4.8 6.33 0.0124 6.35 9.6 12.7 0.0248 12.7 19.6 25.3 0.0496 25.4 38.4 50.7 0.0992 50.8 76.8 101.4 0.1984 101.6 153.6 202.8 0.3967 203.1 250 405.5 0.7935 406.3 500 500 1.5869 Copyright©2011–2016,TexasInstrumentsIncorporated DetailedDescription 27 SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L SWRS109C–MAY2011–REVISEDDECEMBER2016 www.ti.com 5.14 Receiver Channel Filter Bandwidth In order to meet different channel width requirements, the receiver channel filter is programmable. The MDMCFG4.CHANBW_E and MDMCFG4.CHANBW_M configuration registers control the receiver channel filterbandwidth,whichscaleswiththecrystaloscillatorfrequency. Thefollowingformulagivestherelationbetweentheregistersettingsandthechannelfilterbandwidth: ƒ BW = XOSC channel 8×(4+CHANBW_M)×2CHANBW_E (4) Table5-4liststhechannelfilterbandwidthssupportedbytheCC110L. Table5-4.ChannelFilterBandwidths[kHz](Assuminga26-MHzCrystal) MDMCFG4.CHANBW_E MDMCFG4.CHANBW_M 00 01 10 11 00 812 406 203 102 01 650 325 162 81 10 541 270 135 68 11 464 232 116 58 For best performance, the channel filter bandwidth should be selected so that the signal bandwidth occupies at most 80% of the channel filter bandwidth. The channel center tolerance due to crystal inaccuracy should also be subtracted from the channel filter bandwidth. The following example illustrates this: With the channel filter bandwidth set to 500 kHz, the signal should stay within 80% of 500 kHz, which is 400 kHz. Assuming 915 MHz frequency and ±20 ppm frequency uncertainty for both the transmitting device and the receiving device, the total frequency uncertainty is ±40 ppm of 915 MHz, which is ±37 kHz. If the whole transmitted signal bandwidth is to be received within 400 kHz, the transmitted signal bandwidth should be maximum 400 kHz – 2×37 kHz, which is 326 kHz. By compensating for a frequency offset between the transmitter and the receiver, the filter bandwidth can be reduced and the sensitivity can beimproved,seemoreinDN005SWRA122 andinSection5.15.1. 28 DetailedDescription Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L www.ti.com SWRS109C–MAY2011–REVISEDDECEMBER2016 5.15 Demodulator, Symbol Synchronizer, and Data Decision CC110L contains an advanced and highly configurable demodulator. Channel filtering and frequency offset compensation is performed digitally. To generate the RSSI level (see Section 5.18.2 for more information), the signal level in the channel is estimated. Data filtering is also included for enhanced performance. 5.15.1 Frequency Offset Compensation The CC110L has a very fine frequency resolution (see Section 4.10). This feature can be used to compensateforfrequencyoffsetanddrift. When using 2-FSK, GFSK, or 4-FSK modulation, the demodulator will compensate for the offset between the transmitter and receiver frequency within certain limits, by estimating the center of the received data. The frequency offset compensation configuration is controlled from the FOCCFG register. By compensating for a large frequency offset between the transmitter and the receiver, the sensitivity can be improved,seeDN005SWRA122. The tracking range of the algorithm is selectable as fractions of the channel bandwidth with the FOCCFG.FOC_LIMITconfigurationregister. If the FOCCFG.FOC_BS_CS_GATE bit is set, the offset compensator will freeze until carrier sense asserts. This may be useful when the radio is in RX for long periods with no traffic, since the algorithm maydrifttotheboundarieswhentryingtotracknoise. The tracking loop has two gain factors, which affects the settling time and noise sensitivity of the algorithm. FOCCFG.FOC_PRE_K sets the gain before the sync word is detected, and FOCCFG.FOC_POST_Kselectsthegainafterthesyncwordhasbeenfound NOTE FrequencyoffsetcompensationisnotsupportedforOOKmodulation. The estimated frequency offset value is available in the FREQEST status register. This can be used for permanentfrequencyoffsetcompensation.BywritingthevaluefromFREQEST intoFSCTRL0.FREQOFF, the frequency synthesizer will automatically be adjusted according to the estimated frequency offset. More detailsregardingthispermanentfrequencycompensationalgorithmcanbefoundinDN015 SWRA159. 5.15.2 Bit Synchronization The bit synchronization algorithm extracts the clock from the incoming symbols. The algorithm requires that the expected data rate is programmed as described in Section 5.13. Re-synchronization is performed continuouslytoadjustforerrorintheincomingsymbolrate. 5.15.3 Byte Synchronization Byte synchronization is achieved by a continuous sync word search. The sync word is a 16 bit configurable field (can be repeated to get a 32 bit) that is automatically inserted at the start of the packet bythemodulatorintransmitmode.TheMSBinthesyncwordissentfirst.Thedemodulatorusesthisfield to find the byte boundaries in the stream of bits. The sync word will also function as a system identifier, since only packets with the correct predefined sync word will be received if the sync word detection in RX is enabled in register MDMCFG2 (see Section 5.18.1). The sync word detector correlates against the user-configured 16 or 32 bit sync word. The correlation threshold can be set to 15/16, 16/16, or 30/32 bits match. The sync word can be further qualified using the preamble quality indicator mechanism described below and/or a carrier sense condition. The sync word is configured through the SYNC1 and SYNC0 registers. Copyright©2011–2016,TexasInstrumentsIncorporated DetailedDescription 29 SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L SWRS109C–MAY2011–REVISEDDECEMBER2016 www.ti.com 5.16 Packet Handling Hardware Support The CC110L has built-in hardware support for packet oriented radio protocols. In transmit mode, the packethandlercanbeconfiguredtoaddthefollowingelementstothepacketstoredintheTXFIFO: • Aprogrammablenumberofpreamblebytes • Atwobytesynchronization(sync)word.Canbeduplicatedtogivea4-bytesyncword(recommended). Itisnotpossibletoonlyinsertpreambleoronlyinsertasyncword • ACRCchecksumcomputedoverthedatafield. • The recommended setting is 4-byte preamble and 4-byte sync word, except for 500 kBaud data rate wheretherecommendedpreamblelengthis8bytes. In receive mode, the packet handling support will de-construct the data packet by implementing the following(ifenabled): • Preambledetection • Syncworddetection • CRCcomputationandCRCcheck • Onebyteaddresscheck • Packetlengthcheck(lengthbytecheckedagainstaprogrammablemaximumlength) Optionally, two status bytes (see Table 5-5 and Table 5-6) with RSSI value and CRC status can be appendedintheRXFIFO. Table5-5.ReceivedPacketStatusByte1(FirstByteAppendedAftertheData) Bit FieldName Description 7:0 RSSI RSSIvalue Table5-6.ReceivedPacketStatusByte2(SecondByteAppendedAftertheData) Bit FieldName Description 1:CRCforreceiveddataOK(orCRCdisabled) 7 CRC_OK 0:CRCerrorinreceiveddata 6:0 Reserved spacer NOTE RegisterfieldsthatcontrolthepackethandlingfeaturesshouldonlybealteredwhenCC110L isintheIDLEstate. 5.16.1 Packet Format Theformatofthedatapacketcanbeconfiguredandconsistsofthefollowingitems(seeFigure5-6): • Preamble • Synchronizationword • Optionallengthbyte • Optionaladdressbyte • Payload • Optional2byteCRC 30 DetailedDescription Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L www.ti.com SWRS109C–MAY2011–REVISEDDECEMBER2016 Legend: Optional CRC-16calculation Inserted automatically inTX, processed andremovedinRX. P(1r0ea1m0.b..l1e0b1i0ts) Syncword Lengthfield Address field Data field CRC-16 Oprpotcioensasle uds beur-t pnrootv rideemdofvieeldd sin pRroXc.essed inTX, Unprocesseduser data 8 8 8x nbits 16/32 bits 8x nbits 16 bits bits bits Figure5-6.PacketFormat The preamble pattern is an alternating sequence of ones and zeros (10101010…). The minimum length of the preamble is programmable through the value of MDMCFG1.NUM_PREAMBLE. When enabling TX, the modulator will start transmitting the preamble. When the programmed number of preamble bytes has been transmitted, the modulator will send the sync word and then data from the TX FIFO if data is available. If the TX FIFO is empty, the modulator will continue to send preamble bytes until the first byte is writtentotheTXFIFO.Themodulatorwillthensendthesyncwordandthenthedatabytes. The synchronization word is a two-byte value set in the SYNC1 and SYNC0 registers. The sync word provides byte synchronization of the incoming packet. A one-byte sync word can be emulated by setting the SYNC1 value to the preamble pattern. It is also possible to emulate a 32 bit sync word by setting MDMCFG2.SYNC_MODEto3or7.Thesyncwordwillthenberepeatedtwice. CC110L supports both constant packet length protocols and variable length protocols. Variable or fixed packet length mode can be used for packets up to 255 bytes. For longer packets, infinite packet length modemustbeused. Fixed packet length mode is selected by setting PKTCTRL0.LENGTH_CONFIG=0. The desired packet lengthissetbythePKTLEN register.Thisvaluemustbedifferentfrom0. In variable packet length mode, PKTCTRL0.LENGTH_CONFIG=1, the packet length is configured by the first byte after the sync word. The packet length is defined as the payload data, excluding the length byte andtheoptionalCRC.ThePKTLEN registerisusedtosetthemaximumpacketlengthallowedinRX.Any packet received with a length byte with a value greater than PKTLEN will be discarded. The PKTLEN valuemustbedifferentfrom0. With PKTCTRL0.LENGTH_CONFIG=2, the packet length is set to infinite and transmission and reception willcontinueuntilturnedoffmanually.AsdescribedinSection5.16.1.1,thiscanbeusedtosupportpacket formats with different length configuration than natively supported by CC110L. One should make sure that TX mode is not turned off during the transmission of the first half of any byte. Refer to the CC110L Errata NotesSWRZ037 formoredetails. NOTE The minimum packet length supported (excluding the optional length byte and CRC) is one byteofpayloaddata. 5.16.1.1 ArbitraryLengthFieldConfiguration The packet length register, PKTLEN, can be reprogrammed during receive and transmit. In combination with fixed packet length mode ( PKTCTRL0.LENGTH_CONFIG=0), this opens the possibility to have a different length field configuration than supported for variable length packets (in variable packet length modethelengthbyteisthefirstbyteafterthesyncword).Atthestartofreception,thepacketlengthisset to a large value. The MCU reads out enough bytes to interpret the length field in the packet. Then the PKTLEN value is set according to this value. The end of packet will occur when the byte counter in the packet handler is equal to the PKTLEN register. Thus, the MCU must be able to program the correct length,beforetheinternalcounterreachesthepacketlength. Copyright©2011–2016,TexasInstrumentsIncorporated DetailedDescription 31 SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L SWRS109C–MAY2011–REVISEDDECEMBER2016 www.ti.com 5.16.1.2 PacketLength> 255 The packet automation control register, PKTCTRL0, can be reprogrammed during TX and RX. This opens the possibility to transmit and receive packets that are longer than 256 bytes and still be able to use the packet handling hardware support. At the start of the packet, the infinite packet length mode ( PKTCTRL0.LENGTH_CONFIG=2) must be active. On the TX side, the PKTLEN register is set to mod(length, 256). On the RX side the MCU reads out enough bytes to interpret the length field in the packet and sets the PKTLEN register to mod(length, 256). When less than 256 bytes remains of the packet, the MCU disables infinite packet length mode and activates fixed packet length mode ( PKTCTRL0.LENGTH_CONFIG=0). When the internal byte counter reaches the PKTLEN value, the transmission or reception ends (the radio enters the state determined by TXOFF_MODE or RXOFF_MODE). Automatic CRC appending/checking can also be used (by setting PKTCTRL0.CRC_EN=1). When for example a 600-byte packet is to be transmitted, the MCU should do the following (see Figure 5- 7). • SetPKTCTRL0.LENGTH_CONFIG=2. • Pre-programthePKTLEN registertomod(600,256)=88. • Transmitatleast345bytes(600-255),forexamplebyfillingthe64-byteTXFIFOsixtimes(384bytes transmitted). • SetPKTCTRL0.LENGTH_CONFIG=0. • Thetransmissionendswhenthepacketcounterreaches88.Atotalof600bytesaretransmitted. Internal byte counterinpackethandlercountsfrom0to255andthenstartsat0again 0,1,..........,88,....................255,0,........,88,..................,255,0,........,88,..................,255,0,....................... Infinitepacketlengthenabled Fixedpacketlength 600 bytestransmittedand enabledwhenlessthan received 256bytesremainsof packet Length field transmittedand received.RxandTxPKTLENvaluesettomod(600,256)=88 Figure5-7.PacketLength > 255 5.16.2 Packet Filtering in Receive Mode CC110L supports three different types of packet-filtering; address filtering, maximum length filtering, and CRCfiltering. 5.16.2.1 AddressFiltering Setting PKTCTRL1.ADR_CHK to any other value than zero enables the packet address filter. The packet handler engine will compare the destination address byte in the packet with the programmed node address in the ADDR register and the 0x00 broadcast address when PKTCTRL1.ADR_CHK=10 or both the 0x00 and 0xFF broadcast addresses when PKTCTRL1.ADR_CHK=11. If the received address matches a valid address, the packet is received and written into the RX FIFO. If the address match fails, thepacketisdiscardedandreceivemoderestarted(regardlessoftheMCSM1.RXOFF_MODEsetting). If the received address matches a valid address when using infinite packet length mode and address filtering is enabled, 0xFF will be written into the RX FIFO followed by the address byte and then the payloaddata. 32 DetailedDescription Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L www.ti.com SWRS109C–MAY2011–REVISEDDECEMBER2016 5.16.2.2 MaximumLengthFiltering In variable packet length mode, PKTCTRL0.LENGTH_CONFIG=1, the PKTLEN.PACKET_LENGTH register value is used to set the maximum allowed packet length. If the received length byte has a larger value than this, the packet is discarded and receive mode restarted (regardless of the MCSM1.RXOFF_MODEsetting). 5.16.2.3 CRCFiltering The filtering of a packet when CRC check fails is enabled by setting PKTCTRL1.CRC_AUTOFLUSH=1. The CRC auto flush function will flush the entire RX FIFO if the CRC check fails. After auto flushing the RXFIFO,thenextstatedependsontheMCSM1.RXOFF_MODEsetting. Whenusingtheautoflushfunction,themaximumpacketlengthis63bytesinvariablepacketlengthmode and 64 bytes in fixed packet length mode. Note that when PKTCTRL1.APPEND_STATUS is enabled, the maximumallowedpacketlengthisreducedbytwobytesinordertomakeroomintheRXFIFOforthetwo status bytes appended at the end of the packet. Since the entire RX FIFO is flushed when the CRC check fails, the previously received packet must be read out of the FIFO before receiving the current packet. The MCUmustnotreadfromthecurrentpacketuntiltheCRChasbeencheckedasOK. 5.16.3 Packet Handling in Transmit Mode The payload that is to be transmitted must be written into the TX FIFO. The first byte written must be the length byte when variable packet length is enabled. The length byte has a value equal to the payload of the packet (including the optional address byte). If address recognition is enabled on the receiver, the secondbytewrittentotheTXFIFOmustbetheaddressbyte. Iffixedpacketlengthisenabled,thefirstbytewrittentotheTXFIFOshouldbetheaddress(assumingthe receiverusesaddressrecognition). The modulator will first send the programmed number of preamble bytes. If data is available in the TX FIFO, the modulator will send the two-byte (optionally 4-byte) sync word followed by the payload in the TX FIFO. If CRC is enabled, the checksum is calculated over all the data pulled from the TX FIFO, and the result is sent as two extra bytes following the payload data. If the TX FIFO runs empty before the complete packet has been transmitted, the radio will enter TXFIFO_UNDERFLOW state. The only way to exit this state is by issuing an SFTX strobe. Writing to the TX FIFO after it has underflowed will not restart TXmode. 5.16.4 Packet Handling in Receive Mode In receive mode, the demodulator and packet handler will search for a valid preamble and the sync word. When found, the demodulator has obtained both bit and byte synchronization and will receive the first payloadbyte.Whenvariablepacketlengthmodeisenabled,thefirstbyteisthelengthbyte. The packet handler stores this value as the packet length and receives the number of bytes indicated by the length byte. If fixed packet length mode is used, the packet handler will accept the programmed numberofbytes. Next, the packet handler optionally checks the address and only continues the reception if the address matches. If automatic CRC check is enabled, the packet handler computes CRC and matches it with the appendedCRCchecksum. At the end of the payload, the packet handler will optionally write two extra packet status bytes (see Table5-5andTable5-6)thatcontainCRCstatus,linkqualityindication,andRSSIvalue. Copyright©2011–2016,TexasInstrumentsIncorporated DetailedDescription 33 SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L SWRS109C–MAY2011–REVISEDDECEMBER2016 www.ti.com 5.16.5 Packet Handling in Firmware When implementing a packet oriented radio protocol in firmware, the MCU needs to know when a packet has been received/transmitted. Additionally, for packets longer than 64 bytes, the RX FIFO needs to be read while in RX and the TX FIFO needs to be refilled while in TX. This means that the MCU needs to know the number of bytes that can be read from or written to the RX FIFO and TX FIFO respectively. Therearetwopossiblesolutionstogetthenecessarystatusinformation: a. InterruptDrivenSolution The GDO pins can be used in both RX and TX to give an interrupt when a sync word has been received/transmitted or when a complete packet has been received/transmitted by setting IOCFGx.GDOx_CFG=0x06. In addition, there are two configurations for the IOCFGx.GDOx_CFG register that can be used as an interrupt source to provide information on how many bytes that are in the RX FIFO and TX FIFO respectively. The IOCFGx.GDOx_CFG=0x00 and the IOCFGx.GDOx_CFG=0x01 configurations are associated with the RX FIFO while the IOCFGx.GDOx_CFG=0x02 and the IOCFGx.GDOx_CFG=0x03 configurations are associated with the TX FIFO. See Table 5-18 for more information. a. SPIPolling The PKTSTATUS register can be polled at a given rate to get information about the current GDO2 and GDO0 values respectively. The RXBYTES and TXBYTES registers can be polled at a given rate to get informationaboutthenumberofbytesintheRXFIFOandTXFIFOrespectively.Alternatively,thenumber of bytes in the RX FIFO and TX FIFO can be read from the chip status byte returned on the MISO line eachtimeaheaderbyte,databyte,orcommandstrobeissentontheSPIbus. It is recommended to employ an interrupt driven solution since high rate SPI polling reduces the RX sensitivity. Furthermore, as explained in Section 5.8 and the CC110L Errata Notes SWRZ037, when using SPI polling, there is a small, but finite, probability that a single read from registers PKTSTATUS , RXBYTESandTXBYTES isbeingcorrupt.Thesameisthecasewhenreadingthechipstatusbyte. 34 DetailedDescription Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L www.ti.com SWRS109C–MAY2011–REVISEDDECEMBER2016 5.17 Modulation Formats CC110L supports amplitude, frequency, and phase shift modulation formats. The desired modulation formatissetintheMDMCFG2.MOD_FORMATregister. Optionally, the data stream can be Manchester coded by the modulator and decoded by the demodulator. ThisoptionisenabledbysettingMDMCFG2.MANCHESTER_EN=1. NOTE Manchesterencodingisnotsupportedatthesametimeasusing4-FSKmodulation. 5.17.1 Frequency Shift Keying CC110L supports 2-(G)FSK and 4-FSK modulation. When selecting 4-FSK, the preamble and sync word tobereceivedneedstobe2-FSK(seeFigure5-8). When 2-FSK/GFSK/4-FSK modulation is used, the DEVIATN register specifies the expected frequency deviation of incoming signals in RX and should be the same as the deviation of the transmitted signal for demodulationtobeperformedreliablyandrobustly. The frequency deviation is programmed with the DEVIATION_M and DEVIATION_E values in the DEVIATN register.Thevaluehasanexponent/mantissaform,andtheresultantdeviationisgivenby: ƒ ƒ = XOSC ×(8+DEVIATION_M)×2DEVIATION_E dev 217 (5) ThesymbolencodingisshowninTable5-7. Table5-7.SymbolEncodingfor2-FSK/GFSKand4-FSKModulation Format Symbol Coding 0 –Deviation 2-FSK/GFSK 1 +Deviation 01 –Deviation 00 –1/3×Deviation 4-FSK 10 +1/3×Deviation 11 +Deviation 1/Baud Rate 1/Baud Rate 1/Baud Rate +1 +1/3 -1/3 -1 1 0 1 0 1 0 1 0 1 1 0 1 0 0 1 1 00 01 01 11 10 00 11 01 Preamble Sync Data 0xAA 0xD3 0x17 0x8D Figure5-8.DataSentOvertheAir(MDMCFG2.MOD_FORMAT=100) 5.17.2 Amplitude Modulation TheamplitudemodulationsupportedbyCC110LisOn-OffKeying(OOK). OOKmodulationsimplyturnsthePAonorofftomodulateonesandzerosrespectively. When using OOK, the AGC settings from the SmartRF Studio SWRC176 preferred FSK settings are not optimum. DN022 SWRA215 gives guidelines on how to find optimum OOK settings from the preferred settings in SmartRF Studio SWRC176. The DEVIATN register setting has no effect in either TX or RX whenusingOOK. Copyright©2011–2016,TexasInstrumentsIncorporated DetailedDescription 35 SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L SWRS109C–MAY2011–REVISEDDECEMBER2016 www.ti.com 5.18 Received Signal Qualifiers and RSSI CC110L has several qualifiers that can be used to increase the likelihood that a valid sync word is detected: • SyncWordQualifier • RSSI • CarrierSense • ClearChannelAssessment 5.18.1 Sync Word Qualifier If sync word detection in RX is enabled in the MDMCFG2 register, the CC110L will not start filling the RX FIFO and perform the packet filtering described in Section 5.16.2 before a valid sync word has been detected.ThesyncwordqualifiermodeissetbyMDMCFG2.SYNC_MODEandissummarizedinTable5- 8.CarriersensedescribedinSection5.18.3. Table5-8.SyncWordQualifierMode MDMCFG2.SYNC_MODE SyncWordQualifierMode 000 Nopreamble/sync 001 15/16syncwordbitsdetected 010 16/16syncwordbitsdetected 011 30/32syncwordbitsdetected 100 Nopreamble/sync+carriersenseabovethreshold 101 15/16+carriersenseabovethreshold 110 16/16+carriersenseabovethreshold 111 30/32+carriersenseabovethreshold 36 DetailedDescription Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L www.ti.com SWRS109C–MAY2011–REVISEDDECEMBER2016 5.18.2 RSSI The RSSI value is an estimate of the signal power level in the chosen channel. This value is based on the currentgainsettingintheRXchainandthemeasuredsignallevelinthechannel. In RX mode, the RSSI value can be read continuously from the RSSI status register until the demodulator detects a sync word (when sync word detection is enabled). At that point the RSSI readout value is frozen untilthenexttimethechipenterstheRXstate. NOTE It takes some time from the radio enters RX mode until a valid RSSI value is present in the RSSI register. See DN505 SWRA114 for details on how the RSSI response time can be estimated. The RSSI value is given in dBm with a ½-dB resolution. The RSSI update rate, f , depends on the RSSI receiverfilterbandwidth(BW isdefinedinSection5.14)andAGCCTRL0.FILTER_LENGTH. channel 2×BW ƒ = channel RSSI 8×2FILTER_LENGTH (6) If PKTCTRL1.APPEND_STATUS is enabled, the last RSSI value of the packet is automatically added to thefirstbyteappendedafterthepayload. The RSSI value read from the RSSI status register is a 2s complement number. The following procedure canbeusedtoconverttheRSSIreadingtoanabsolutepowerlevel(RSSI_dBm). 1. ReadtheRSSIstatusregister 2. Convertthereadingfromahexadecimalnumbertoadecimalnumber(RSSI_dec) 3. IfRSSI_dec≥ 128thenRSSI_dBm=(RSSI_dec-256)/2 – RSSI_offset 4. ElseifRSSI_dec< 128thenRSSI_dBm=(RSSI_dec)/2 – RSSI_offset Table 5-9 gives typical values for the RSSI_offset. Figure 5-9 and Figure 5-10 show typical plots of RSSI readingsasafunctionofinputpowerlevelfordifferentdatarates. Table5-9.TypicalRSSI_offsetValues Datarate[kBaud] RSSI_offset[dB],433MHz RSSI_offset[dB],868MHz 1.2 74 74 38.4 74 74 250 74 74 spacer 0 0 –10 –10 –20 –20 m) –30 m) –30 B –40 B –40 d d ut ( –50 ut ( –50 do –60 do –60 a a Re –70 Re –70 SI –80 SI –80 RS –90 1.2 kBaud RS –90 1.2 kBaud –100 38.4 kBaud –100 38.4 kBaud –110 –110 250 kBaud 250 kBaud –120 –120 –120 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 –120 –110 –100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0 Input Power (dBm) Input Power (dBm) C010 C011 Figure5-9.TypicalRSSIValueVersusInputPowerLevelfor Figure5-10.TypicalRSSIValueVersusInputPowerLevelfor DifferentDataRatesat433MHz DifferentDataRatesat868MHz Copyright©2011–2016,TexasInstrumentsIncorporated DetailedDescription 37 SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L SWRS109C–MAY2011–REVISEDDECEMBER2016 www.ti.com 5.18.3 Carrier Sense (CS) Carrier sense (CS) is used as a sync word qualifier and for Clear Channel Assessment (see Section5.18.4).CScanbeassertedbasedontwoconditionswhichcanbeindividuallyadjusted: • CS is asserted when the RSSI is above a programmable absolute threshold, and deasserted when RSSIisbelowthesamethreshold(withhysteresis).SeemoreinSection5.18.3.1. • CS is asserted when the RSSI has increased with a programmable number of dB from one RSSI sample to the next, and deasserted when RSSI has decreased with the same number of dB. This setting is not dependent on the absolute signal level and is thus useful to detect signals in environmentswithtimevaryingnoisefloor.SeemoreinSection5.18.3.2. Carrier sense can be used as a sync word qualifier that requires the signal level to be higher than the threshold for a sync word search to be performed and is set by setting MDMCFG2 The carrier sense signal can be observed on one of the GDO pins by setting IOCFGx.GDOx_CFG=14 and in the status registerbitPKTSTATUS.CS. Other uses of Carrier sense include the TX-if-CCA function (see Section 5.18.4) and the optional fast RX termination (see Section 5.19.5). CS can be used to avoid interference from other RF sources in the ISM bands. 5.18.3.1 CSAbsoluteThreshold TheabsolutethresholdrelatedtotheRSSIvaluedependsonthefollowingregisterfields: • AGCCTRL2.MAX_LNA_GAIN • AGCCTRL2.MAX_DVGA_GAIN • AGCCTRL1.CARRIER_SENSE_ABS_THR • AGCCTRL2.MAGN_TARGET For given AGCCTRL2.MAX_LNA_GAIN and AGCCTRL2.MAX_DVGA_GAIN settings, the absolute thresholdcanbeadjusted±7dBinstepsof1dBusingCARRIER_SENSE_ABS_THR. The MAGN_TARGET setting is a compromise between blocker tolerance/selectivity and sensitivity. The value sets the desired signal level in the channel into the demodulator. Increasing this value reduces the headroom for blockers, and therefore close-in selectivity. It is strongly recommended to use SmartRF Studio SWRC176 to generate the correct MAGN_TARGET setting. Table 5-10 shows the typical RSSI readout values at the CS threshold at 250 kBaud data rate. The default reset value for CARRIER_SENSE_ABS_THR (0 dB) has been used. MAGN_TARGET=111 (42 dB) have been used for the 250 kBaud data rate. For other data rates, the user must generate similar tables to find the CS absolutethreshold. Table5-10.TypicalRSSIValueindBmatCSThresholdwithMAGN_TARGET=7(42dB)at250kBaud, 868MHz MAX_DVGA_GAIN[1:0] 00 01 10 11 000 −90.5 −84.5 −78.5 −72.5 001 −88 −82 −76 −70 010 −84.5 −78.5 −72 −66 011 −82.5 −76.5 −70 −64 MAX_LNA_GAIN[2:0] 100 −80.5 −74.5 −68 −62 101 −78 −72 −66 −60 110 −76.5 −70 −64 −58 111 −74.5 −68 −62 −56 38 DetailedDescription Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L www.ti.com SWRS109C–MAY2011–REVISEDDECEMBER2016 If the threshold is set high, that is, only strong signals are wanted, the threshold should be adjusted upwards by first reducing the MAX_LNA_GAIN value and then the MAX_DVGA_GAIN value. This will reducepowerconsumptioninthereceiverfrontend,sincethehighestgainsettingsareavoided. 5.18.3.2 CSRelativeThreshold The relative threshold detects sudden changes in the measured signal level. This setting does not depend on the absolute signal level and is thus useful to detect signals in environments with a time varying noise floor. The register field AGCCTRL1.CARRIER_SENSE_REL_THR is used to enable/disable relative CS, andtoselectthresholdof6dB,10dB,or14dBRSSIchange. 5.18.4 Clear Channel Assessment (CCA) The Clear Channel Assessment (CCA) is used to indicate if the current channel is free or busy. The currentCCAstateisviewableonanyoftheGDOpinsbysettingIOCFGx.GDOx_CFG=0x09. MCSM1.CCA_MODEselectsthemodetousewhendeterminingCCA. When the STX or SFSTXON command strobe is given while CC110L is in the RX state, the TX or FSTXON state is only entered if the clear channel requirements are fulfilled. Otherwise, the chip will remaininRX.Ifthechannelthenbecomesavailable,theradiowillnotenterTXorFSTXONstatebeforea new strobe command is sent on the SPI interface. This feature is called TX-if-CCA. Four CCA requirementscanbeprogrammed: • Always(CCAdisabled,alwaysgoestoTX) • IfRSSIisbelowthreshold • Unlesscurrentlyreceivingapacket • Boththeabove(RSSIbelowthresholdandnotcurrentlyreceivingapacket) Copyright©2011–2016,TexasInstrumentsIncorporated DetailedDescription 39 SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L SWRS109C–MAY2011–REVISEDDECEMBER2016 www.ti.com 5.19 Radio Control SIDLE SPWD SLEEP CAL_COMPLETE 0 MANCAL IDLE CSn=0 3,4,5 1 SXOFF SCAL CSn = 0 XOFF SRX | STX | SFSTXON 2 FS_WAKEUP 6,7 FS_AUTOCAL= 01 and SRX | STX | SFSTXON FS_AUTOCAL= 00 | 10 | 11 and SRX | STX | SFSTXON CALIBRATE 8 CAL_COMPLETE SETTLING SFSTXON 9,10,11 FSTXON 18 STX SRX SRX STX SFSTXON | RXOFF_MODE= 01 TXOFF_MODE=01 STX | RXOFF_MODE= 10 RXTX_SETTLING (STX|SFSTXON) and 21 CCA|RXOFF_MODE TXOFF_MODE = 10 19T,X 20 = 01|10 13,R14X,15 RXOFF_MODE= 11 SRX | TXOFF_MODE= 11 TXRX_SETTLING 16 TXFIFO_UNDERFLOW TXOFF_aMnOdDE = 00 RXOFF_aMnOdDE = 00 RXFIFO_OVERFLOW FS_AUTOCAL= 10 | 11 FS_AUTOCAL= 10 | 11 CALIBRATE TXOFF_MODE= 00 and 12 RXOFF_MODE= 00 FS_AUTOCAL= 00 | 01 and FS_AUTOCAL= 00 | 01 TX_UNDERFLOW RX_OVERFLOW 22 17 SFTX SFRX IDLE 1 Figure5-11.CompleteRadioControlStateDiagram CC110L has a built-in state machine that is used to switch between different operational states (modes). The change of state is done either by using command strobes or by internal events such as TX FIFO underflow. 40 DetailedDescription Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L www.ti.com SWRS109C–MAY2011–REVISEDDECEMBER2016 A simplified state diagram, together with typical usage and current consumption, is shown in Figure 5-2. The complete radio control state diagram is shown in Figure 5-11. The numbers refer to the state number readableintheMARCSTATEstatusregister.Thisregisterisprimarilyfortestpurposes. 5.19.1 Power-On Start-Up Sequence When the power supply is turned on, the system must be reset. This is achieved by one of the two sequences described below, that is, automatic power-on reset (POR) or manual reset. After the automatic power-on reset or manual reset, it is also recommended to change the signal that is output on the GDO0 pin. The default setting is to output a clock signal with a frequency of CLK_XOSC/192. However, to optimize performance in TX and RX, an alternative GDO setting from the settings found in Table 5-18 shouldbeselected. 5.19.1.1 AutomaticPOR A power-on reset circuit is included in the CC110L. The minimum requirements stated in Section 4.12 must be followed for the power-on reset to function properly. The internal power-up sequence is completed when CHIP_RDYn goes low. CHIP_RDYn is observed on the SO pin after CSn is pulled low. SeeSection5.6formoredetailsonCHIP_RDYn.WhentheCC110Lresetiscompleted,thechipwillbein the IDLE state and the crystal oscillator will be running. If the chip has had sufficient time for the crystal oscillator to stabilize after the power-on-reset, the SO pin will go low immediately after taking CSn low. If CSn is taken low before reset is completed, the SO pin will first go high, indicating that the crystal oscillatorisnotstabilized,beforegoinglowasshowninFigure5-12. CSn SO XOSC Stable Figure5-12.Power-OnResetwithSRES 5.19.1.2 ManualReset The other global reset possibility on CC110L uses the SRES command strobe. By issuing this strobe, all internal registers and states are set to the default, IDLE state. The manual power-up sequence is as follows(seeFigure5-13): • SetSCLK=1andSI=0. • StrobeCSnlow/high. • HoldCSnlowandthenhighforatleast40 µsrelativetopullingCSnlow • PullCSnlowandwaitforSOtogolow(CHIP_RDYn). • IssuetheSRESstrobeontheSIline. • WhenSOgoeslowagain,resetiscompleteandthechipisintheIDLEstate. XOSCandvoltageregulatorswitchedon Copyright©2011–2016,TexasInstrumentsIncorporated DetailedDescription 41 SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L SWRS109C–MAY2011–REVISEDDECEMBER2016 www.ti.com XOSC and voltage regulator switched on 40 us CSn SO XOSC Stable SI SRES Figure5-13.Power-OnResetwithSRES NOTE The above reset procedure is only required just after the power supply is first turned on. If the user wants to reset the CC110L after this, it is only necessary to issue an SRES commandstrobe. 5.19.2 Crystal Control The crystal oscillator (XOSC) is either automatically controlled or always on, if MCSM0.XOSC_FORCE_ONisset. In the automatic mode, the XOSC will be turned off if the SXOFF or SPWD command strobes are issued; the state machine then goes to XOFF or SLEEP respectively. This can only be done from the IDLE state. The XOSC will be turned off when CSn is released (goes high). The XOSC will be automatically turned on again when CSn goes low. The state machine will then go to the IDLE state. The SO pin on the SPI interfacemustbepulledlowbeforetheSPIinterfaceisreadytobeusedasdescribedinSection5.6. IftheXOSCisforcedon,thecrystalwillalwaysstayonevenintheSLEEPstate. Crystal oscillator start-up time depends on crystal ESR and load capacitances. The electrical specification forthecrystaloscillatorcanbefoundinSection4.9. 5.19.3 Voltage Regulator Control The voltage regulator to the digital core is controlled by the radio controller. When the chip enters the SLEEPstatewhichisthestatewiththelowestcurrentconsumption,thevoltageregulatorisdisabled.This occurs after CSn is released when a SPWD command strobe has been sent on the SPI interface. The chip is then in the SLEEP state. Setting CSn low again will turn on the regulator and crystal oscillator and makethechipentertheIDLEstate. 5.19.4 Active Modes (RX and TX) CC110L has two active modes: receive and transmit. These modes are activated directly by the MCU by usingtheSRXandSTXcommandstrobes. The frequency synthesizer must be calibrated regularly. CC110L has one manual calibration option (using the SCAL strobe), and three automatic calibration options that are controlled by the MCSM0.FS_AUTOCALsetting: • CalibratewhengoingfromIDLEtoeitherRXorTX(orFSTXON) • Calibrate when going from either RX or TX to IDLE automatically (not forced in IDLE by issuing an SIDLEstrobe) • Calibrate every fourth time when going from either RX or TX to IDLE automatically (not forced in IDLE byissuinganSIDLEstrobe) • RX:Startsearchforanewpacket 42 DetailedDescription Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L www.ti.com SWRS109C–MAY2011–REVISEDDECEMBER2016 NOTE When MCSM1.RXOFF_MODE=11 and a packet has been received, it will take some time before a valid RSSI value is present in the RSSI register again even if the radio has never exited RX mode. This time is the same as the RSSI response time discussed in DN505 SWRA114. Similarly, when TX is active the chip will remain in the TX state until the current packet has been successfully transmitted. Then the state will change as indicated by the MCSM1.TXOFF_MODE setting. ThepossibledestinationsarethesameasforRX. The MCU can manually change the state from RX to TX and vice versa by using the command strobes. If the radio controller is currently in transmit and the SRX strobe is used, the current transmission will be endedandthetransitiontoRXwillbedone. If the radio controller is in RX when the STX or SFSTXON command strobes are used, the TX- if-CCA function will be used. If the channel is not clear, the chip will remain in RX. The MCSM1.CCA_MODE settingcontrolstheconditionsforclearchannelassessment.SeeSection5.18.4. TheSIDLEcommandstrobecanalwaysbeusedtoforcetheradiocontrollertogototheIDLEstate. 5.19.5 RX Termination If the system expects the transmission to have started when entering RX mode, the MCSM2.RX_TIME_RSSI function can be used. The radio controller will then terminate RX if the first valid carrier sense sample indicates no carrier (RSSI below threshold). See Section 5.18.3 for details on Carrier Sense. For OOK modulation, lack of carrier sense is only considered valid after eight symbol periods. Thus, the MCSM2.RX_TIME_RSSI function can be used in OOK mode when the distance between two “1” symbols iseightorless. 5.19.6 Timing 5.19.6.1 OverallStateTransitionTimes The main radio controller needs to wait in certain states in order to make sure that the internal analog/digital parts have settled down and are ready to operate in the new states. A number of factors are importantforthestatetransitiontimes: • Thecrystaloscillatorfrequency,f xosc • OOKusedornot • ThedatarateincaseswhereOOKisused • ThevalueoftheTEST0,TEST1,andFSCAL3registers Table5-11showstimingincrystalclockcyclesforkeystatetransitions. Note that the TX to IDLE transition time is a function of data rate (fbaudrate). When OOK is used (that is, FREND0.PA_POWER=001b), TX to IDLE will require 1/8×f baudrate longer times than the time stated in Table5-11. Copyright©2011–2016,TexasInstrumentsIncorporated DetailedDescription 43 SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L SWRS109C–MAY2011–REVISEDDECEMBER2016 www.ti.com Table5-11.OverallStateTransitionTimes[Examplefor26-MHzCrystalOscillator,250kBaudDataRate, andTEST0=0x0B(MaximumCalibrationTime)]. Description TransitionTime(FREND0.PA_POWER=0) TransitionTime[µs] IDLEtoRX,nocalibration 1953/f 75.1 xosc IDLEtoRX,withcalibration 1953/ +FScalibrationTime 799 fxosc IDLEtoTX/FSTXON,nocalibration 1954/f 75.2 xosc IDLEtoTX/FSTXON,withcalibration 1953/f +FScalibrationTime 799 xosc TXtoRXswitch 782/f +0.25/f 31.1 xosc baudrate RXtoTXswitch 782/f 30.1 xosc TXtoIDLE,nocalibration ~0.25/f ~1 baudrate TXtoIDLE,withcalibration ~0.25/f +FScalibrationTime 725 baudrate RXtoIDLE,nocalibration 2/f ~0.1 xosc RXtoIDLE,withcalibration 2/f +FScalibrationTime 724 xosc Manualcalibration 283/f +FScalibrationTime 735 xosc 5.19.6.2 FrequencySynthesizerCalibrationTime Table 5-12 summarizes the frequency synthesizer (FS) calibration times for possible settings of TEST0 and FSCAL3.CHP_CURR_CAL_EN. Setting FSCAL3.CHP_CURR_CAL_EN to 00b disables the charge pump calibration stage. TEST0 is set to the values recommended by SmartRF Studio software . The possible values for TEST0 when operating with different frequency bands are 0x09 and 0x0B. SmartRF StudiosoftwarealwayssetsFSCAL3.CHP_CURR_CAL_ENto10b. Thecalibrationtimecanbereducedfrom712/724 µsto145/157 µs.SeeSection5.27.2formoredetails. Table5-12.FrequencySynthesizerCalibrationTimes(26-and27-MHzCrystal) TEST0 FSCAL3.CHP_CURR_CAL_EN FSCalibrationTimef =26 FSCalibrationTimef =27 xosc xosc MHz MHz 0x09 00b 3764/f =145µs 3764/f =139µs xosc xosc 0x09 10b 18506/f =712µs 18506/f =685µs xosc xosc 0x0B 00b 4073/f =157µs 4073/f =151µs xosc xosc 0x0B 10b 18815/f =724µs 18815/f =697µs xosc xosc 44 DetailedDescription Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L www.ti.com SWRS109C–MAY2011–REVISEDDECEMBER2016 5.20 Data FIFO The CC110L contains two 64-byte FIFOs, one for received data and one for data to be transmitted. The SPI interface is used to read from the RX FIFO and write to the TX FIFO. Section 5.10 contains details on the SPI FIFO access. The FIFO controller will detect overflow in the RX FIFO and underflow in the TX FIFO. When writing to the TX FIFO it is the responsibility of the MCU to avoid TX FIFO overflow. A TX FIFO overflowwillresultinanerrorintheTXFIFOcontent. Likewise,whenreadingtheRXFIFOtheMCUmustavoidreadingtheRXFIFOpastitsemptyvaluesince aRXFIFOunderflowwillresultinanerrorinthedatareadoutoftheRXFIFO. The chip status byte that is available on the SO pin while transferring the SPI header and contains the fill grade of the RX FIFO if the access is a read operation and the fill grade of the TX FIFO if the access is a writeoperation.Section5.6containsmoredetailsonthis. The number of bytes in the RX FIFO and TX FIFO can be read from the status registers RXBYTES.NUM_RXBYTES and TXBYTES.NUM_TXBYTES respectively. If a received data byte is written to the RX FIFO at the exact same time as the last byte in the RX FIFO is read over the SPI interface, the RX FIFO pointer is not properly updated and the last read byte will be duplicated. To avoid this problem, theRXFIFOshouldneverbeemptiedbeforethelastbyteofthepacketisreceived. For packet lengths less than 64 bytes it is recommended to wait until the complete packet has been receivedbeforereadingitoutoftheRXFIFO. If the packet length is larger than 64 bytes, the MCU must determine how many bytes can be read from theRXFIFO(RXBYTES.NUM_RXBYTES-1).Thefollowingsoftwareroutinecanbeused: 1. ReadRXBYTES.NUM_RXBYTESrepeatedlyataratespecifiedtobeatleasttwicethatofwhichRF bytesarereceiveduntilthesamevalueisreturnedtwice;storevalueinn. 2. Ifn<#ofbytesremaininginpacket,readn-1bytesfromtheRXFIFO. 3. Repeatsteps1and2untiln=numberofbytesremaininginpacket. 4. ReadtheremainingbytesfromtheRXFIFO. The4-bitFIFOTHR.FIFO_THRsettingisusedtoprogramthresholdpointsintheFIFOs. Table 5-13 lists the 16 FIFO_THR settings and the corresponding thresholds for the RX and TX FIFOs. ThethresholdvalueiscodedinoppositedirectionsfortheRXFIFOandTXFIFO.Thisgivesequalmargin totheoverflowandunderflowconditionswhenthethresholdisreached. Table5-13.FIFO_THRSettingsandtheCorrespondingFIFOThresholds FIFO_THR BytesinTXFIFO BytesinRXFIFO 0(0000) 61 4 1(0001) 57 8 2(0010) 53 12 3(0011) 49 16 4(0100) 45 20 5(0101) 41 24 6(0110) 37 28 7(0111) 33 32 8(1000) 29 36 9(1001) 25 40 10(1010) 21 44 11(1011) 17 48 12(1100) 13 52 13(1101) 9 56 Copyright©2011–2016,TexasInstrumentsIncorporated DetailedDescription 45 SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L SWRS109C–MAY2011–REVISEDDECEMBER2016 www.ti.com Table5-13.FIFO_THRSettingsandtheCorrespondingFIFOThresholds (continued) FIFO_THR BytesinTXFIFO BytesinRXFIFO 14(1110) 5 60 15(1111) 1 64 A signal will assert when the number of bytes in the FIFO is equal to or higher than the programmed threshold.ThissignalcanbeviewedontheGDOpins(seeTable5-18). Figure 5-14 shows the number of bytes in both the RX FIFO and TX FIFO when the threshold signal toggles in the case of FIFO_THR=13. Figure 5-15 shows the signal on the GDO pin as the respective FIFOisfilledabovethethreshold,andthendrainedbelowinthecaseofFIFO_THR=13. Overflow margin FIFO_THR=13 56 bytes FIFO_THR=13 Underflow 8 bytes margin RXFIFO TXFIFO Figure5-14.ExampleofFIFOsatThreshold NUM_RXBYTES 53 54 55 56 57 56 55 54 53 GDO NUM_TXBYTES 6 7 8 9 10 9 8 7 6 GDO Figure5-15.NumberofBytesinFIFOversustheGDOSignal(GDOx_CFG=0x00inRXand GDOx_CFG=0x02inTX,FIFO_THR=13) 46 DetailedDescription Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L www.ti.com SWRS109C–MAY2011–REVISEDDECEMBER2016 5.21 Frequency Programming The frequency programming in CC110L is designed to minimize the programming needed when changing frequency. To set up a system with channel numbers, the desired channel spacing is programmed with the MDMCFG0.CHANSPC_M and MDMCFG1.CHANSPC_E registers. The channel spacing registers are mantissa and exponent respectively. The base or start frequency is set by the 24 bit frequency word located in the FREQ2, FREQ1, and FREQ0 registers. This word will typically be set to the center of the lowestchannelfrequencythatistobeused. The desired channel number is programmed with the 8-bit channel number register, CHANNR.CHAN, whichismultipliedbythechanneloffset.Theresultantcarrierfrequencyisgivenby: ƒ = ƒXOSC ×(FREQ+CHAN×((256+CHANSPC_M)×2CHANSPC_2-2)) carrier 216 (7) With a 26 MHz crystal the maximum channel spacing is 405 kHz. To get that is, 1-MHz channel spacing, onesolutionistouse333kHzchannelspacingandselecteachthirdchannelinCHANNR.CHAN. The preferred IF frequency is programmed with the FSCTRL1.FREQ_IF register. The IF frequency is givenby: ƒ ƒ = XOSC ×FREQ_IF IF 210 (8) If any frequency programming register is altered when the frequency synthesizer is running, the synthesizer may give an undesired response. Hence, the frequency should only be updated when the radioisintheIDLEstate. Copyright©2011–2016,TexasInstrumentsIncorporated DetailedDescription 47 SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L SWRS109C–MAY2011–REVISEDDECEMBER2016 www.ti.com 5.22 VCO TheVCOiscompletelyintegratedon-chip. 5.22.1 VCO and PLL Self-Calibration The VCO characteristics vary with temperature and supply voltage changes as well as the desired operating frequency. In order to ensure reliable operation, CC110L includes frequency synthesizer self- calibration circuitry. This calibration should be done regularly, and must be performed after turning on power and before using a new frequency (or channel). The number of XOSC cycles for completing the PLLcalibrationisgiveninTable5-11. The calibration can be initiated automatically or manually. The synthesizer can be automatically calibrated each time the synthesizer is turned on, or each time the synthesizer is turned off automatically. This is configured with the MCSM0.FS_AUTOCAL register setting. In manual mode, the calibration is initiated whentheSCALcommandstrobeisactivatedintheIDLEmode. NOTE The calibration values are maintained in SLEEP mode, so the calibration is still valid after waking up from SLEEP mode unless supply voltage or temperature has changed significantly. To check that the PLL is in lock, the user can program register IOCFGx.GDOx_CFG to 0x0A, and use the lock detector output available on the GDOx pin as an interrupt for the MCU (x = 0,1, or 2). A positive transition on the GDOx pin means that the PLL is in lock. As an alternative the user can read register FSCAL1. The PLL is in lock if the register content is different from 0x3F. Refer also to the CC110L Errata NotesSWRZ037. For more robust operation, the source code could include a check so that the PLL is re-calibrated until PLLlockisachievedifthePLLdoesnotlockthefirsttime. 48 DetailedDescription Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L www.ti.com SWRS109C–MAY2011–REVISEDDECEMBER2016 5.23 Voltage Regulators CC110L contains several on-chip linear voltage regulators that generate the supply voltages needed by low-voltage modules. These voltage regulators are invisible to the user, and can be viewed as integral parts of the various modules. The user must however make sure that the absolute maximum ratings and requiredpinvoltagesinTable3-1andTable5-1arenotexceeded. By setting the CSn pin low, the voltage regulator to the digital core turns on and the crystal oscillator starts. The SO pin on the SPI interface must go low before the first positive edge of SCLK (setup time is giveninTable5-1). If the chip is programmed to enter power-down mode (SPWD strobe issued), the power will be turned off afterCSngoeshigh.ThepowerandcrystaloscillatorwillbeturnedonagainwhenCSngoeslow. Thevoltageregulatorforthedigitalcorerequiresoneexternaldecouplingcapacitor. ThevoltageregulatoroutputshouldonlybeusedfordrivingtheCC110L. Copyright©2011–2016,TexasInstrumentsIncorporated DetailedDescription 49 SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L SWRS109C–MAY2011–REVISEDDECEMBER2016 www.ti.com 5.24 Output Power Programming The RF output power level from the device has two levels of programmability. The PATABLE register can hold two user selected output power settings and the FREND0.PA_POWER value selects the PATABLE entry to use (0 or 1). PATABLE must be programmed in burst mode if writing to other entries than PATABLE[0].SeeSection5.11 formoreprogrammingdetails. For OOK modulation, FREND0.PA_POWER should be 1 and the logic 0 and logic 1 power levels shall be programmed to index 0 and 1 respectively. For all other modulation formats, the desired output power shouldbeprogrammedtoindex0. Table 5-14 contains the recommended PATABLE settings for various output levels and frequency bands. DN013 SWRA168 gives the complete tables for the different frequency bands using multi-layer inductors. Using PA settings from 0x61 to 0x6F is not allowed. Table 5-17 contains output power and current consumptionfordefaultPATABLEsetting(0xC6).Themeasurementsaredoneon SWRR045. NOTE All content of the PATABLE except for the first byte (index 0) is lost when entering the SLEEPstate. Table5-14.OptimumPATABLESettingsforVariousOutputPowerLevelsUsingWire-WoundInductorsin 868-and915-MHzFrequencyBands 868MHz 915MHz CurrentConsumption, CurrentConsumption, OutputPower[dBm] Setting Setting Typ.[mA] Typ.[mA] 12/11 0xC0 34.2 0xC0 33.4 10 0xC5 30.0 0xC3 30.7 7 0xCD 25.8 0xCC 25.7 5 0x86 19.9 0x84 20.2 0 0x50 16.8 0x8E 17.2 −6 0x37 16.4 0x38 17.0 −10 0x26 14.5 0x27 14.8 −15 0x1D 13.3 0x1E 13.3 −20 0x17 12.6 0x0E 12.5 −30 0x03 12.0 0x03 11.9 Table5-15.OutputPowerandCurrentConsumptionforDefaultPATABLESettingUsingWire-Wound Inductorsin868-and915-MHzFrequencyBands 868MHz 915MHz DefaultPowerSetting OutputPower[dBm] CurrentConsumption, OutputPower[dBm] CurrentConsumption, Typ.[mA] Typ.[mA] 0xC6 9.6 29.4 8.9 28.7 50 DetailedDescription Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L www.ti.com SWRS109C–MAY2011–REVISEDDECEMBER2016 Table5-16.OptimumPATABLESettingsforVariousOutputPowerLevelsUsingMulti-layerInductorsin 868-and915-MHzFrequencyBands 868MHz 915MHz CurrentConsumption, CurrentConsumption, OutputPower[dBm] Setting Setting Typ.[mA] Typ.[mA] 10 0xC2 32.4 0xC0 31.8 7 0xCB 26.8 0xC7 26.9 5 0x81 21.0 0xCD 24.3 0 0x50 16.9 0x8E 16.7 −10 0x27 15.0 0x27 14.9 −15 0x1E 13.4 0x1E 13.4 −20 0x0F 12.7 0x0E 12.6 −30 0x03 12.1 0x03 12.0 Table5-17.OutputPowerandCurrentConsumptionforDefaultPATABLESettingUsingMulti-layer Inductorsin868-and915-MHzFrequencyBands 868MHz 915MHz DefaultPowerSetting CurrentConsumption, OutputPower[dBm] CurrentConsumption, OutputPower[dBm] Typ.[mA] Typ.[mA] 0xC6 8.5 29.5 7.2 27.4 Copyright©2011–2016,TexasInstrumentsIncorporated DetailedDescription 51 SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L SWRS109C–MAY2011–REVISEDDECEMBER2016 www.ti.com 5.25 General Purpose and Test Output Control Pins The three digital output pins GDO0, GDO1, and GDO2 are general control pins configured with IOCFG0.GDO0_CFG, IOCFG1.GDO1_CFG, and IOCFG2.GDO2_CFG respectively. Table 5-18 shows the different signals that can be monitored on the GDO pins. These signals can be used as inputs to the MCU. GDO1 is the same pin as the SO pin on the SPI interface, thus the output programmed on this pin will only be valid when CSn is high. The default value for GDO1 is 3-stated which is useful when the SPI interfaceissharedwithotherdevices. The default value for GDO0 is a 135-141 kHz clock output (XOSC frequency divided by 192). Since the XOSC is turned on at power-on-reset, this can be used to clock the MCU in systems with only one crystal. WhentheMCUisupandrunning,itcanchangetheclockfrequencybywritingtoIOCFG0.GDO0_CFG. If the IOCFGx.GDOx_CFG setting is less than 0x20 and IOCFGx_GDOx_INV is 0 (1), the GDO0 and GDO2 pins will be hardwired to 0 (1), and the GDO1 pin will be hardwired to 1 (0) in the SLEEP state. ThesesignalswillbehardwireduntiltheCHIP_RDYnsignalgoeslow. If the IOCFGx.GDOx_CFG setting is 0x20 or higher, the GDO pins will work as programmed also in SLEEPstate.Asanexample,GDO1ishighimpedanceinallstatesifIOCFG1.GDO1_CFG=0x2E. Table5-18.GDOxSignalSelection(x=0,1,or2) GDOx_CFG Description(1) [5:0] 0(0x00) AssociatedtotheRXFIFO:AssertswhenRXFIFOisfilledatorabovetheRXFIFOthreshold.DeassertswhenRXFIFOis drainedbelowthesamethreshold. 1(0x01) AssociatedtotheRXFIFO:AssertswhenRXFIFOisfilledatorabovetheRXFIFOthresholdortheendofpacketis reached.DeassertswhentheRXFIFOisempty. 2(0x02) AssociatedtotheTXFIFO:AssertswhentheTXFIFOisfilledatorabovetheTXFIFOthreshold.DeassertswhentheTX FIFOisbelowthesamethreshold. 3(0x03) AssociatedtotheTXFIFO:AssertswhenTXFIFOisfull.DeassertswhentheTXFIFOisdrainedbelowtheTXFIFO threshold. 4(0x04) AssertswhentheRXFIFOhasoverflowed.DeassertswhentheFIFOhasbeenflushed. 5(0x05) AssertswhentheTXFIFOhasunderflowed.DeassertswhentheFIFOisflushed. 6(0x06) Assertswhensyncwordhasbeensent/received,andde-assertsattheendofthepacket.InRX,thepinwillalsode-assert whenapacketisdiscardedduetoaddressormaximumlengthfilteringorwhentheradioentersRXFIFO_OVERFLOWstate. InTXthepinwillde-assertiftheTXFIFOunderflows. 7(0x07) AssertswhenapackethasbeenreceivedwithCRCOK.DeassertswhenthefirstbyteisreadfromtheRXFIFO. 8(0x08) Reserved-usedfortest. 9(0x09) Clearchannelassessment.HighwhenRSSIlevelisbelowthreshold(dependentonthecurrentCCA_MODEsetting). 10(0x0A) Lockdetectoroutput.ThePLLisinlockifthelockdetectoroutputhasapositivetransitionorisconstantlylogichigh.To checkforPLLlockthelockdetectoroutputshouldbeusedasaninterruptfortheMCU. 11(0x0B) SerialClock.Synchronoustothedatainsynchronousserialmode. InRXmode,dataissetuponthefallingedgebyCC110LwhenGDOx_INV=0. InTXmode,dataissampledbyCC110LontherisingedgeoftheserialclockwhenGDOx_INV=0. 12(0x0C) SerialSynchronousDataOutput.Usedforsynchronousserialmode. 13(0x0D) SerialDataOutput.Usedforasynchronousserialmode. 14(0x0E) Carriersense.HighifRSSIlevelisabovethreshold.ClearedwhenenteringIDLEmode. 15(0x0F) CRC_OK.ThelastCRCcomparisonmatched.Clearedwhenentering/restartingRXmode. 16(0x10)– Reserved-usedfortest. 26(0x1A) 27(0x1B) PA_PD.Note:PA_PDwillhavethesamesignallevelinSLEEPandTXstates.TocontrolanexternalPAorRX/TXswitchin applicationswheretheSLEEPstateisuseditisrecommendedtouseGDOx_CFGx=0x2Finstead. (1) Thereare3GDOpins,butonlyoneCLK_XOSC/ncanbeselectedasanoutputatanytime.IfCLK_XOSC/nistobemonitoredonone oftheGDOpins,theothertwoGDOpinsmustbeconfiguredtovalueslessthan0x30.TheGDO0defaultvalueisCLK_XOSC/192. TooptimizeRFperformance,thesesignalsshouldnotbeusedwhiletheradioisinRXorTXmode. 52 DetailedDescription Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L www.ti.com SWRS109C–MAY2011–REVISEDDECEMBER2016 Table5-18.GDOxSignalSelection(x=0,1,or2)(continued) GDOx_CFG Description(1) [5:0] 28(0x1C) LNA_PD.Note:LNA_PDwillhavethesamesignallevelinSLEEPandRXstates.TocontrolanexternalLNAorRX/TX switchinapplicationswheretheSLEEPstateisuseditisrecommendedtouseGDOx_CFGx=0x2Finstead. 29(0x1D)– Reserved-usedfortest. 38(0x26) 39(0x27) CLK_32k. 40(0x28) Reserved-usedfortest. 41(0x29) CHIP_RDYn. 42(0x2A) Reserved-usedfortest. 43(0x2B) XOSC_STABLE. 44(0x2C)- Reserved-usedfortest. 45(0x2D) 46(0x2E) Highimpedance(3-state). 47(0x2F) HWto0(HW1achievedbysettingGDOx_INV=1).CanbeusedtocontrolanexternalLNA/PAorRX/TXswitch. 48(0x30) CLK_XOSC/1 Note:Thereare3GDOpins,butonlyone CLK_XOSC/ncanbeselectedasanoutputatany 49(0x31) CLK_XOSC/1.5 time.IfCLK_XOSC/nistobemonitoredononeof 50(0x32) CLK_XOSC/2 theGDOpins,theothertwoGDOpinsmustbe configuredtovalueslessthan0x30.TheGDO0 51(0x33) CLK_XOSC/3 defaultvalueisCLK_XOSC/192. 52(0x34) CLK_XOSC/4 TooptimizeRFperformance,thesesignalsshould 53(0x35) CLK_XOSC/6 notbeusedwhiletheradioisinRXmode. 54(0x36) CLK_XOSC/8 55(0x37) CLK_XOSC/12 56(0x38) CLK_XOSC/16 57(0x39) CLK_XOSC/24 58(0x3A) CLK_XOSC/32 59(0x3B) CLK_XOSC/48 60(0x3C) CLK_XOSC/64 61(0x3D) CLK_XOSC/96 62(0x3E) CLK_XOSC/128 63(0x3F) CLK_XOSC/192 Copyright©2011–2016,TexasInstrumentsIncorporated DetailedDescription 53 SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L SWRS109C–MAY2011–REVISEDDECEMBER2016 www.ti.com 5.26 Asynchronous and Synchronous Serial Operation Several features and modes of operation have been included in the CC110L to provide backward compatibility with previous Chipcon products and other existing RF communication systems. For new systems, it is recommended to use the built-in packet handling features, as they can give more robust communication,significantlyoffloadthemicrocontroller,andsimplifysoftwaredevelopment. 5.26.1 Asynchronous Serial Operation Asynchronous transfer is included in the CC110L for backward compatibility with systems that are already usingtheasynchronousdatatransfer. When asynchronous transfer is enabled, all packet handling support is disabled and it is not possible to useManchesterencoding. Asynchronous serial mode is enabled by setting PKTCTRL0.PKT_FORMAT to 3. Strobing STX will configure the GDO0 pin as data input (TX data) regardless of the content of the IOCFG0 register. Data output can be on GDO0, GDO1, or GDO2. This is set by the IOCFG0.GDO0_CFG, IOCFG1.GDO1_CFG andIOCFG2.GDO2_CFGfields. The CC110L modulator samples the level of the asynchronous input 8 times faster than the programmed data rate. The timing requirement for the asynchronous stream is that the error in the bit period must be lessthanoneeighthoftheprogrammeddatarate. In asynchronous serial mode no data decision is done on-chip and the raw data is put on the data output line. When using asynchronous serial mode make sure the interfacing MCU does proper oversampling and that it can handle the jitter on the data output line. The MCU should tolerate a jitter of ±1/8 of a bit periodasthedatastreamistime-discreteusing8samplesperbit. In asynchronous serial mode there will be glitches of 37 - 38.5 ns duration (1/XOSC) occurring infrequently and with random periods. A simple RC filter can be added to the data output line between CC110L and the MCU to get rid of the 37 - 38.5 ns glitches if considered a problem. The filter 3 dB cut-off frequency needs to be high enough so that the data is not filtered and at the same time low enough to remove the glitch. As an example, for 2.4 kBaud data rate a 1 kΩ resistor and 2.7 nF capacitor can be used.Thisgivesa3dBcut-offfrequencyof59kHz. 5.26.2 Synchronous Serial Operation Setting PKTCTRL0.PKT_FORMAT to 1 enables synchronous serial mode. When using this mode, sync detection should be disabled together with CRC calculation ( MDMCFG2.SYNC_MODE=000 and PKTCTRL0.CRC_EN=0). Infinite packet length mode should be used ( PKTCTRL0.LENGTH_CONFIG=10b). In synchronous serial mode, data is transferred on a two-wire serial interface. The CC110L provides a clock that is used to set up new data on the data input line or sample data on the data output line. Data input (TX data) is on the GDO0 pin. This pin will automatically be configured as an input when TX is active. The TX latency is 8 bits. The data output pin can be any of the GDO pins. This is set by the IOCFG0.GDO0_CFG,IOCFG1.GDO1_CFG,andIOCFG2.GDO2_CFGfields.TheRXlatencyis9bits. TheMCUmusthandlepreambleandsyncworddetectioninsoftware. The MCU must handle preamble and sync word insertion/detection in software, together with CRC calculationandinsertion. 54 DetailedDescription Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L www.ti.com SWRS109C–MAY2011–REVISEDDECEMBER2016 5.27 System Considerations and Guidelines 5.27.1 SRD Regulations International regulations and national laws regulate the use of radio receivers and transmitters. Short Range Devices (SRDs) for license free operation below 1 GHz are usually operated in the 315 MHz, 433 MHz, 868 MHz or 915 MHz frequency bands. The CC110L is specifically designed for such use with its 300 - 348 MHz, 387 - 464 MHz, and 779 - 928 MHz operating ranges. The most important regulations when using the CC110L in the 315 MHz, 433 MHz, 868 MHz, or 915 MHz frequency bands are EN 300 220V2.3.1(Europe)andFCCCFR47Part15(USA). For compliance with modulation bandwidth requirements under EN 300 220 V2.3.1 in the 863 to 870 MHz frequencyrangeitisrecommendedtousea26MHzcrystalforfrequenciesbelow869MHzanda27MHz crystalforfrequenciesabove869MHz. Compliance with regulations is dependent on the complete system performance. It is the customer's responsibilitytoensurethatthesystemcomplieswithregulations. 5.27.2 Frequency Hopping and Multi-Channel Systems CC110L is highly suited for FHSS or multi- channel systems due to its agile frequency synthesizer and effectivecommunicationinterface. Charge pump current, VCO current, and VCO capacitance array calibration data is required for each frequency when implementing frequency hopping for CC110L. There are 3 ways of obtaining the calibrationdatafromthechip: 1. Frequencyhoppingwithcalibrationforeachhop.ThePLLcalibrationtimeis712/724 µs(26MHz crystalandTEST0=0x09/0B,seeTable5-12).Theblankingintervalbetweeneachfrequencyhopis then787/799 µs. 2. Fastfrequencyhoppingwithoutcalibrationforeachhopcanbedonebyperformingthenecessary calibratingatstartupandsavingtheresultingFSCAL3,FSCAL2,andFSCAL1registervaluesinMCU memory.TheVCOcapacitancecalibrationFSCAL1registervaluemustbefoundforeachRF frequencytobeused.TheVCOcurrentcalibrationvalueandthechargepumpcurrentcalibration valueavailableinFSCAL2andFSCAL3respectivelyarenotdependentontheRFfrequency,sothe samevaluecanthereforebeusedforallRFfrequenciesforthesetworegisters.Betweeneach frequencyhop,thecalibrationprocesscanthenbereplacedbywritingtheFSCAL3,FSCAL2and FSCAL1registervaluesthatcorrespondstothenextRFfrequency.ThePLLturnontimeis approximately75µs(seeTable5-11).Theblankingintervalbetweeneachfrequencyhopisthen approximately75µs. 3. Runcalibrationonasinglefrequencyatstartup.Nextwrite0toFSCAL3[5:4]todisablethecharge pumpcalibration.AfterwritingtoFSCAL3[5:4],strobeSRX(orSTX)withMCSM0.FS_AUTOCAL=1for eachnewfrequencyhop.Thatis,VCOcurrentandVCOcapacitancecalibrationisdone,butnot chargepumpcurrentcalibration.Whenchargepumpcurrentcalibrationisdisabledthecalibrationtime isreducedfrom712/724µsto145/157 µs(26MHzcrystalandTEST0 =0x09/0B,seeTable5-12). Theblankingintervalbetweeneachfrequencyhopisthen220/232µs. There is a trade off between blanking time and memory space needed for storing calibration data in non- volatile memory. Solution 2) above gives the shortest blanking interval, but requires more memory space to store calibration values. This solution also requires that the supply voltage and temperature do not vary muchinordertohavearobustsolution.Solution3)gives567 µssmallerblankingintervalthansolution1). The recommended settings for TEST0.VCO_SEL_CAL_EN change with frequency. This means that one should always use SmartRF Studio to get the correct settings for a specific frequency before doing a calibration,regardlessofwhichcalibrationmethodisbeingused. Copyright©2011–2016,TexasInstrumentsIncorporated DetailedDescription 55 SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L SWRS109C–MAY2011–REVISEDDECEMBER2016 www.ti.com NOTE The content in the TEST0 register is not retained in SLEEP state, thus it is necessary to re- writethisregisterwhenreturningfromtheSLEEPstate. 5.27.3 Wideband Modulation when not Using Spread Spectrum Digital modulation systems under FCC Section 15.247 include 2-FSK, GFSK, and 4-FSK modulation. A maximum peak output power of 1 W (+30 dBm) is allowed if the 6 dB bandwidth of the modulated signal exceeds 500 kHz. In addition, the peak power spectral density conducted to the antenna shall not be greaterthan+8dBminany3kHzband. Operating at high data rates and frequency separation, the CC110L is suited for systems targeting compliance with digital modulation system as defined by FCC Section 15.247. An external power amplifier such as CC1190 SWRS089 is needed to increase the output above +11 dBm. Refer to DN006 SWRA123 forfurtherdetailsconcerningwidebandmodulationandCC110L. 5.27.4 Data Burst Transmissions The high maximum data rate of CC110L opens up for burst transmissions. A low average data rate link (that is, 10 kBaud) can be realized by using a higher over-the-air data rate. Buffering the data and transmitting in bursts at high data rate (that is, 500 kBaud) will reduce the time in active mode, and hence alsoreducetheaveragecurrentconsumptionsignificantly. Reducing the time in active mode will reduce the likelihood of collisions with other systems in the same frequencyrange. NOTE Thesensitivityandthustransmissionrangeisreducedforhighdatarateburstscomparedto lowerdatarates. 5.27.5 Continuous Transmissions In data streaming applications, the CC110L opens up for continuous transmissions at 500 kBaud effective data rate. As the modulation is done with a closed loop PLL, there is no limitation in the length of a transmission (open loop modulation used in some transceivers often prevents this kind of continuous data streamingandreducestheeffectivedatarate). 5.27.6 Increasing Range In some applications it may be necessary to extend the range. The CC1190 SWRS089 is a range extender for 850-950 MHz RF transceivers, transmitters, and System-on-Chip devices from Texas Instruments. It increases the link budget by providing a power amplifier (PA) for increased output power, and a low-noise amplifier (LNA) with low noise figure for improved receiver sensitivity in addition to switches and RF matching for simple design of high performance wireless systems. Refer to AN094 SWRA356 and AN096 SWRA361 for performance figures of the CC110L and CC1190 combination. Figure5-16showsasimplifiedapplicationcircuit. 56 DetailedDescription Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L www.ti.com SWRS109C–MAY2011–REVISEDDECEMBER2016 VDD VDD V V V D D D D D D _ _ _ PA_IN RF_P AP AP NL SAW PA_OUT 1 2 ALNA_OUT RF_N CC1190 CC110L TR_SW PA_EN GDOx LNA_EN LNA_IN HGM B A S Connected toMCU Connected to VDD/GND/MCU Figure5-16.SimplifiedCC110L-CC1190ApplicationCircuit Copyright©2011–2016,TexasInstrumentsIncorporated DetailedDescription 57 SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L SWRS109C–MAY2011–REVISEDDECEMBER2016 www.ti.com 5.28 Configuration Registers The configuration of CC110L is done by programming 8-bit registers. The optimum configuration data based on selected system parameters are most easily found by using the SmartRF Studio software . Complete descriptions of the registers are given in the following tables. After chip reset, all the registers have default values as shown in the tables. The optimum register setting might differ from the default value. After a reset, all registers that shall be different from the default value therefore needs to be programmedthroughtheSPIinterface. There are 11 command strobe registers, listed in Table 5-19. Accessing these registers will initiate the change of an internal state or mode. There are 44 normal 8-bit configuration registers listed in Table 5-20 and SmartRF Studio will provide recommended settings for these registers (Addresses marked as “Not Used” can be part of a burst access and one can write a dummy value to them. Addresses marked as “Reserved”mustbeconfiguredaccordingtoSmartRFStudio). There are also 9 status registers that are listed in Table 5-21. These registers, which are read- only, containinformationaboutthestatusofCC110L. The two FIFOs are accessed through one 8-bit register. Write operations write to the TX FIFO, while read operationsreadfromtheRXFIFO. During the header byte transfer and while writing data to a register or the TX FIFO, a status byte is returnedontheSOline.ThisstatusbyteisdescribedinTable5-2. Table 5-22 summarizes the SPI address space. The address to use is given by adding the base address to the left and the burst and read/write bits on the top. Note that the burst bit has different meaning for baseaddressesaboveandbelow0x2F. Table5-19.CommandStrobes Address StrobeName Description 0x30 SRES Resetchip. Enableandcalibratefrequencysynthesizer (ifMCSM0.FS_AUTOCAL=1).IfinRX(with 0x31 SFSTXON CCA):Gotoawaitstatewhereonlythe synthesizerisrunning(forquickRX/TX turnaround). 0x32 SXOFF Turnoffcrystaloscillator. Calibratefrequencysynthesizerandturnit off.SCALcanbestrobedfromIDLEmode 0x33 SCAL withoutsettingmanualcalibrationmode( MCSM0.FS_AUTOCAL=0) InIDLEstate:EnableRX.Performcalibration 0x34 SRX firstifMCSM0.FS_AUTOCAL=1. InIDLEstate:EnableTX.Performcalibration firstifMCSM0.FS_AUTOCAL=1.IfinRX 0x35 STX stateandCCAisenabled:OnlygotoTXif channelisclear. 0x36 SIDLE EnterIDLEstate 0x37-0x38 Reserved EnterpowerdownmodewhenCSngoes 0x39 SPWD high. FlushtheRXFIFObuffer.OnlyissueSFRX 0x3A SFRX inIDLEorRXFIFO_OVERFLOWstates. FlushtheTXFIFObuffer.OnlyissueSFTX 0x3B SFTX inIDLEorTXFIFO_UNDERFLOWstates. 0x3C Reserved Nooperation.Maybeusedtogetaccessto 0x3D SNOP thechipstatusbyte. 58 DetailedDescription Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L www.ti.com SWRS109C–MAY2011–REVISEDDECEMBER2016 Table5-20.ConfigurationRegistersOverview Address Register Description PreservedinSLEEP DetailsonPageNumber State GDO2outputpin 0x00 IOCFG2 Yes Table5-23 configuration GDO1outputpin 0x01 IOCFG1 Yes Table5-24 configuration GDO0outputpin 0x02 IOCFG0 Yes Table5-25 configuration RXFIFOandTXFIFO 0x03 FIFOTHR Yes Table5-26 thresholds 0x04 SYNC1 Syncword,highbyte Yes Table5-27 0x05 SYNC0 Syncword,lowbyte Yes Table5-28 0x06 PKTLEN Packetlength Yes Table5-29 0x07 PKTCTRL1 Packetautomationcontrol Yes Table5-30 0x08 PKTCTRL0 Packetautomationcontrol Yes Table5-31 0x09 ADDR Deviceaddress Yes Table5-32 0x0A CHANNR Channelnumber Yes Table5-33 Frequencysynthesizer 0x0B FSCTRL1 Yes Table5-34 control Frequencysynthesizer 0x0C FSCTRL0 Yes Table5-35 control Frequencycontrolword, 0x0D FREQ2 Yes Table5-36 highbyte Frequencycontrolword, 0x0E FREQ1 Yes Table5-37 middlebyte Frequencycontrolword, 0x0F FREQ0 Yes Table5-38 lowbyte 0x10 MDMCFG4 Modemconfiguration Yes Table5-39 0x11 MDMCFG3 Modemconfiguration Yes Table5-40 0x12 MDMCFG2 Modemconfiguration Yes Table5-41 0x13 MDMCFG1 Modemconfiguration Yes Table5-42 0x14 MDMCFG0 Modemconfiguration Yes Table5-43 0x15 DEVIATN Modemdeviationsetting Yes Table5-44 MainRadioControlState 0x16 MCSM2 Yes Table5-45 Machineconfiguration MainRadioControlState 0x17 MCSM1 Yes Table5-46 Machineconfiguration MainRadioControlState 0x18 MCSM0 Yes Table5-47 Machineconfiguration FrequencyOffset 0x19 FOCCFG Compensation Yes Table5-48 configuration BitSynchronization 0x1A BSCFG Yes Table5-49 configuration 0x1B AGCCTRL2 AGCcontrol Yes Table5-50 0x1C AGCCTRL1 AGCcontrol Yes Table5-51 0x1D AGCCTRL0 AGCcontrol Yes Table5-52 0x1E-0x1F NotUsed 0x20 RESERVED Yes Table5-53 FrontendRX 0x21 FREND1 Yes Table5-54 configuration FrontendTX 0x22 FREND0 Yes Table5-55 configuration Copyright©2011–2016,TexasInstrumentsIncorporated DetailedDescription 59 SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L SWRS109C–MAY2011–REVISEDDECEMBER2016 www.ti.com Table5-20.ConfigurationRegistersOverview(continued) Address Register Description PreservedinSLEEP DetailsonPageNumber State Frequencysynthesizer 0x23 FSCAL3 Yes Table5-56 calibration Frequencysynthesizer 0x24 FSCAL2 Yes Table5-57 calibration Frequencysynthesizer 0x25 FSCAL1 Yes Table5-58 calibration Frequencysynthesizer 0x26 FSCAL0 Yes Table5-59 calibration 0x27-0x28 NotUsed 0x29-0x2B RESERVED No Table5-60 0x2C TEST2 Varioustestsettings No Table5-63 0x2D TEST1 Varioustestsettings No Table5-64 0x2E TEST0 Varioustestsettings No Table5-65 Table5-21.StatusRegistersOverview Address Register Description Detailsonpagenumber 0x30(0xF0) PARTNUM PartnumberforCC110L Table5-66 0x31(0xF1) VERSION Currentversionnumber Table5-67 0x32(0xF2) FREQEST FrequencyOffsetEstimate Table5-68 0x33(0xF3) CRC_REG CRCOK Table5-69 0x34(0xF4) RSSI Receivedsignalstrength Table5-70 indication 0x35(0xF5) MARCSTATE Controlstatemachinestate Table5-71 0x36-0x37(0xF6–0xF7) Reserved 0x38(0xF8) PKTSTATUS CurrentGDOxstatusandpacket Table5-72 status 0x39(0xF9) Reserved 0x3A(0xFA) TXBYTES Underflowandnumberofbytes Table5-73 intheTXFIFO 0x3B(0xFB) RXBYTES Overflowandnumberofbytesin Table5-74 theRXFIFO 0x3C-0x3D(0xFC-0xFD) Reserved 60 DetailedDescription Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L www.ti.com SWRS109C–MAY2011–REVISEDDECEMBER2016 Table5-22.SPIAddressSpace Write Read SingleByte Burst SingleByte Burst +0x00 +0x40 +0x80 +0xC0 0x00 IOCFG2 0x01 IOCFG1 0x02 IOCFG0 0x03 FIFOTHR 0x04 SYNC1 0x05 SYNC0 0x06 PKTLEN 0x07 PKTCTRL1 0x08 PKTCTRL0 0x09 ADDR 0x0A CHANNR 0x0B FSCTRL1 0x0C FSCTRL0 0x0D FREQ2 0x0E FREQ1 0x0F FREQ0 0x10 MDMCFG4 0x11 MDMCFG3 0x12 MDMCFG2 ble 0x13 MDMCFG1 ossi p 0x14 MDMCFG0 ess 0x15 DEVIATN acc 0x16 MCSM2 urst b 0x17 MCSM1 ers, 0x18 MCSM0 gist 0x19 FOCCFG re n 0x1A BSCFG atio 0x1B AGCCTRL2 gur nfi 0x1C AGCCTRL1 co W 0x1D AGCCTRL0 R/ 0x1E NotUsed 0x1F NotUsed 0x20 RESERVED 0x21 FREND1 0x22 FREND0 0x23 FSCAL3 0x24 FSCAL2 0x25 FSCAL1 0x26 FSCAL0 0x27 NotUsed 0x28 NotUsed 0x29 RESERVED 0x2A RESERVED 0x2B RESERVED 0x2C TEST2 0x2D TEST1 0x2E TEST0 0x2F NotUsed Copyright©2011–2016,TexasInstrumentsIncorporated DetailedDescription 61 SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L SWRS109C–MAY2011–REVISEDDECEMBER2016 www.ti.com Table5-22.SPIAddressSpace(continued) Write Read SingleByte Burst SingleByte Burst +0x00 +0x40 +0x80 +0xC0 0x30 SRES SRES PARTNUM 0x31 SFSTXON SFSTXON VERSION 0x32 SXOFF SXOFF FREQEST 0x33 SCAL SCAL CRC_REG 00xx3345 SSRTXX SSRTXX MARRCSSSTIATE egisters r 0x36 SIDLE SIDLE Reserved us at 0x37 Reserved Reserved Reserved St 0x38 Reserved Reserved PKTSTATUS bes, o 0x39 SPWD SPWD Reserved Str d 0x3A SFRX SFRX TXBYTES an m 0x3B SFTX SFTX RXBYTES m o C 0x3C Reserved Reserved Reserved 0x3D SNOP SNOP Reserved 0x3E PATABLE PATABLE PATABLE PATABLE 0x3F TXFIFO TXFIFO RXFIFO RXFIFO 5.28.1 Configuration Register Details - Registers with preserved values in SLEEP state Table5-23.0x00:IOCFG2-GDO2OutputPinConfiguration Bit FieldName Reset R/W Description 7 R0 Notused 6 GDO2_INV 0 R/W Invertoutput,thatis,selectactivelow(1)/high(0) 5:0 GDO2_CFG[5:0] 41(101001) R/W DefaultisCHP_RDYn(seeTable5-18). Table5-24.0x01:IOCFG1-GDO1OutputPinConfiguration Bit FieldName Reset R/W Description Sethigh(1)orlow(0)outputdrivestrengthontheGDO 7 GDO_DS 0 R/W pins. 6 GDO1_INV 0 R/W Invertoutput,thatis,selectactivelow(1)/high(0) 5:0 GDO1_CFG[5:0] 46(101110) R/W Defaultis3-state(seeTable5-18). Table5-25.0x02:IOCFG0-GDO0OutputPinConfiguration Bit FieldName Reset R/W Description 7 0 R/W UsesettingfromSmartRFStudio 6 GDO0_INV 0 R/W Invertoutput,thatis,selectactivelow(1)/high(0) DefaultisCLK_XOSC/192(seeTable5-18). 5:0 GDO0_CFG[5:0] 63(0x3F) R/W Itisrecommendedtodisabletheclockoutputin initialization,inordertooptimizeRFperformance. 62 DetailedDescription Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L www.ti.com SWRS109C–MAY2011–REVISEDDECEMBER2016 Table5-26.0x03:FIFOTHR-RXFIFOandTXFIFOThresholds Bit FieldName Reset R/W Description 7 0 R/W UsesettingfromSmartRFStudio 0:TEST1=0x31andTEST2=0x88whenwakingupfrom SLEEP 1:TEST1=0x35andTEST2=0x81whenwakingup fromSLEEP NotethatthechangesintheTESTregistersduetothe 6 ADC_RETENTION 0 R/W ADC_RETENTIONbitsettingareonlyseenINTERNALLY intheanalogpart.ThevaluesreadfromtheTEST registerswhenwakingupfromSLEEPmodewillalways betheresetvalue. TheADC_RETENTIONbitshouldbesetto1beforegoing intoSLEEPmodeifsettingswithanRXfilterbandwidth below325kHzarewantedattimeofwake-up. Formoredetails,seeDN010SWRA147 Setting RXAttenuation,TypicalValues 0(00) 0dB 5:4 CLOSE_IN_RX[1:0] 0(00) R/W 1(01) 6dB 2(10) 12dB 3(11) 18dB SetthethresholdfortheRXFIFOandTXFIFO.The thresholdisexceededwhenthenumberofbytesinthe FIFOisequaltoorhigherthanthethresholdvalue. Setting BytesinRXFIFO BytesinTXFIFO 0(0000) 4 61 1(0001) 8 57 2(0010) 12 53 3(0011) 16 49 4(0100) 20 45 5(0101) 24 41 3:0 FIFO_THR[3:0] 7(0111) R/W 6(0110) 28 37 7(0111) 32 33 8(1000) 36 29 9(1001) 40 25 10(1010) 44 21 11(1011) 48 17 12(1100) 52 13 13(1101) 56 9 14(1110) 60 5 15(1111) 64 1 Table5-27.0x04:SYNC1-SyncWord,HighByte Bit FieldName Reset R/W Description 7:0 SYNC[15:8] 211(0xD3) R/W 8MSBof16-bitsyncword Table5-28.0x05:SYNC0-SyncWord,LowByte Bit FieldName Reset R/W Description 7:0 SYNC[7:0] 145(0x91) R/W 8LSBof16-bitsyncword Copyright©2011–2016,TexasInstrumentsIncorporated DetailedDescription 63 SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L SWRS109C–MAY2011–REVISEDDECEMBER2016 www.ti.com Table5-29.0x06:PKTLEN-PacketLength Bit FieldName Reset R/W Description Indicatesthepacketlengthwhenfixedpacketlengthmode isenabled.Ifvariablepacketlengthmodeisused,this 7:0 PACKET_LENGTH 255(0xFF) R/W valueindicatesthemaximumpacketlengthallowed.This valuemustbedifferentfrom0. Table5-30.0x07:PKTCTRL1-PacketAutomationControl Bit FieldName Reset R/W Description 7:5 0(000) R/W UsesettingfromSmartRFStudio 4 0 R0 NotUsed. EnableautomaticflushofRXFIFOwhenCRCisnotOK. 3 CRC_AUTOFLUSH 0 R/W ThisrequiresthatonlyonepacketisintheRXFIFOand thatpacketlengthislimitedtotheRXFIFOsize. Whenenabled,twostatusbyteswillbeappendedtothe 2 APPEND_STATUS 1 R/W payloadofthepacket.ThestatusbytescontaintheRSSI value,aswellasCRCOK. Controlsaddresscheckconfigurationofreceived packages. Addresscheck Setting configuration 0(00) Noaddresscheck 1:0 ADR_CHK[1:0] 0(00) R/W 1(01) Addresscheck,no broadcast Addresscheckand0 2(10) (0x00)broadcast Addresscheckand0 3(11) (0x00)and255 (0xFF)broadcast Table5-31.0x08:PKTCTRL0-PacketAutomationControl Bit FieldName Reset R/W Description 7 R0 Notused 6 1 R/W UsesettingfromSmartRFStudio FormatofRXdata Setting Packetformat 0(00) Normalmode,useFIFOsforRXandTX Synchronousserialmode.Datainon 1(01) GDO0anddataoutoneitheroftheGDOx 5:4 PKT_FORMAT[1:0] 0(00) R/W pins RandomTXmode;sendsrandomdata 2(10) usingPN9generator.Usedfortest.Works asnormalmode,setting0(00),inRX Asynchronousserialmode.Datainon 3(11) GDO0anddataoutoneitheroftheGDOx pins 3 0 R0 Notused 1:CRCcalculationenabled 2 CRC_EN 1 R/W 0:CRCcalculationdisabled 64 DetailedDescription Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L www.ti.com SWRS109C–MAY2011–REVISEDDECEMBER2016 Table5-31.0x08:PKTCTRL0-PacketAutomationControl(continued) Bit FieldName Reset R/W Description 1:0 LENGTH_CONFIG[1:0] 1(01) R/W Configurethepacketlength Setting Packetlengthconfiguration 0(00) Fixedpacketlengthmode.Length configuredinPKTLENregister 1(01) Variablepacketlengthmode.Packet lengthconfiguredbythefirstbyteafter syncword 2(10) Infinitepacketlengthmode 3(11) Reserved Table5-32.0x09:ADDR-DeviceAddress Bit FieldName Reset R/W Description Addressusedforpacketfiltration.Optionalbroadcast 7:0 DEVICE_ADDR[7:0] 0(0x00) R/W addressesare0(0x00)and255(0xFF). Table5-33.0x0A:CHANNR-ChannelNumber Bit FieldName Reset R/W Description The8-bitunsignedchannelnumber,whichismultipliedby 7:0 CHAN[7:0] 0(0x00) R/W thechannelspacingsettingandaddedtothebase frequency. Table5-34.0x0B:FSCTRL1-FrequencySynthesizerControl Bit FieldName Reset R/W Description 7:6 R0 Notused 5 0 R/W UsesettingfromSmartRFStudio ThedesiredIFfrequencytoemployinRX.Subtractedfrom FSbasefrequencyinRXandcontrolsthedigitalcomplex mixerinthedemodulator. ƒ 4:0 FREQ_IF[4:0] 15(01111) R/W ƒ = XOSC ×FREQ_IF IF 210 ThedefaultvaluegivesanIFfrequencyof381kHz, assuminga26.0MHzcrystal. Table5-35.0x0C:FSCTRL0-FrequencySynthesizerControl Bit FieldName Reset R/W Description Frequencyoffsetaddedtothebasefrequencybeforebeing usedbythefrequencysynthesizer.(2s-complement). 7:0 FREQOFF[7:0] 0(0x00) R/W ResolutionisFXTAL/214(1.59kHz-1.65kHz);rangeis±202 kHzto±210kHz,dependentofXTALfrequency. Table5-36.0x0D:FREQ2-FrequencyControlWord,HighByte Bit FieldName Reset R/W Description FREQ[23:22]isalways0(theFREQ2registerislessthan 7:6 FREQ[23:22] 0(00) R 36with26-27MHzcrystal) FREQ[23:0]isthebasefrequencyforthefrequency synthesizerinincrementsoffXOSC/216. 5:0 FREQ[21:16] 30(011110) R/W ƒ ƒ = XOSC ×FREQ[23:0] carrier 216 Copyright©2011–2016,TexasInstrumentsIncorporated DetailedDescription 65 SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L SWRS109C–MAY2011–REVISEDDECEMBER2016 www.ti.com Table5-37.0x0E:FREQ1-FrequencyControlWord,MiddleByte Bit FieldName Reset R/W Description 7:0 FREQ[15:8] 196(0xC4) R/W SeeTable5-36. Table5-38.0x0F:FREQ0-FrequencyControlWord,LowByte Bit FieldName Reset R/W Description 7:0 FREQ[7:0] 236(0xEC) R/W SeeTable5-36. Table5-39.0x10:MDMCFG4-ModemConfiguration Bit FieldName Reset R/W Description 7:6 CHANBW_E[1:0] 2(10) R/W Setsthedecimationratioforthedelta-sigmaADCinput streamandthusthechannelbandwidth. ƒ BW = XOSC 5:4 CHANBW_M[1:0] 0(00) R/W channel 8×(4+CHANBW_M)×2CHANBW_E Thedefaultvaluesgive203kHzchannelfilterbandwidth, assuminga26.0MHzcrystal. 3:0 DRATE_E[3:0] 12(1100) R/W Theexponentoftheuserspecifiedsymbolrate Table5-40.0x11:MDMCFG3-ModemConfiguration Bit FieldName Reset R/W Description Themantissaoftheuserspecifiedsymbolrate.Thesymbol rateisconfiguredusinganunsigned,floating-pointnumber with9-bitmantissaand4-bitexponent.The9thbitisa hidden'1'.Theresultingdatarateis: (256+DRATE_M)×2DRATE_E 7:0 DRATE_M[7:0] 34(0x22) R/W R = ׃ DATA 228 XOSC Thedefaultvaluesgiveadatarateof115.051kBaud (closestsettingto115.2kBaud),assuminga26.0MHz crystal. 66 DetailedDescription Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L www.ti.com SWRS109C–MAY2011–REVISEDDECEMBER2016 Table5-41.0x12:MDMCFG2-ModemConfiguration Bit FieldName Reset R/W Description DisabledigitalDCblockingfilterbeforedemodulator. 0=Enable(bettersensitivity) 1=Disable(currentoptimized).Onlyfordatarates≤250 7 DEM_DCFILT_OFF 0 R/W kBaud TherecommendedIFfrequencychangeswhentheDC blockingisdisabled.UseSmartRFStudiotocalculate correctregistersetting. Themodulationformatoftheradiosignal Setting Modulationformat 0(000) 2-FSK 1(001) GFSK 2(010) Reserved 3(011) OOK 6:4 MOD_FORMAT[2:0] 0(000) R/W 4(100) 4-FSK 5(101) Reserved 6(110) Reserved 7(111) Reserved 4-FSKmodulationcannotbeusedtogetherwithManchester encoding EnablesManchesterencoding/decoding. 0=Disable 3 MANCHESTER_EN 0 R/W 1=Enable Manchesterencodingcannotbeusedwhenusing asynchronousserialmodeor4-FSKmodulation Combinedsync-wordqualifiermode. Thevalues0and4disablespreambleandsyncword detection Thevalues1,2,5,and6enables16-bitsyncword detection.Only15of16bitsneedtomatchwhenusing setting1or5.Thevalues3and7enables32-bitssyncword detection(only30of32bitsneedtomatch). Setting Sync-wordqualifiermode 0(000) Nopreamble/sync 2:0 SYNC_MODE[2:0] 2(010) R/W 1(001) 15/16syncwordbitsdetected 2(010) 16/16syncwordbitsdetected 3(011) 30/32syncwordbitsdetected Nopreamble/sync,carrier-senseabove 4(100) threshold 5(101) 15/16+carrier-senseabovethreshold 6(110) 16/16+carrier-senseabovethreshold 7(111) 30/32+carrier-senseabovethreshold Copyright©2011–2016,TexasInstrumentsIncorporated DetailedDescription 67 SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L SWRS109C–MAY2011–REVISEDDECEMBER2016 www.ti.com Table5-42.0x13:MDMCFG1-ModemConfiguration Bit FieldName Reset R/W Description 7 0 R/W UsesettingfromSmartRFStudio Setstheminimumnumberofpreamblebytestobetransmitted Setting Numberofpreamblebytes 0(000) 2 1(001) 3 2(010) 4 6:4 NUM_PREAMBLE[2:0] 2(010) R/W 3(011) 6 4(100) 8 5(101) 12 6(110) 16 7(111) 24 3:2 R0 Notused 1:0 CHANSPC_E[1:0] 2(10) R/W 2bitexponentofchannelspacing Table5-43.0x14:MDMCFG0-ModemConfiguration Bit FieldName Reset R/W Description 8-bitmantissaofchannelspacing.Thechannelspacingis multipliedbythechannelnumberCHANandaddedtothe basefrequency.Itisunsignedandhastheformat: ƒ 7:0 CHANSPC_M[7:0] 248(0xF8) R/W DƒCHANNEL = X2O18SC ×(256+CHANSPC_M)×2CHANSPC_E Thedefaultvaluesgive199.951kHzchannelspacing(the closestsettingto200kHz),assuming26.0MHzcrystal frequency. Table5-44.0x15:DEVIATN-ModemDeviationSetting Bit FieldName Reset R/W Description 7 R0 Notused. 6:4 DEVIATION_E[2:0] 4(100) R/W Deviationexponent. 3 R0 Notused. RX Specifiestheexpectedfrequencydeviation 2-FSK/GFSK/4- ofincomingsignal,mustbeapproximately FSK rightfordemodulationtobeperformed reliablyandrobustly. OOK Thissettinghasnoeffect. TX Specifiesthenominalfrequencydeviation fromthecarrierfora'0'(-DEVIATN)and'1' 2:0 DEVIATION_M[2:0] 7(111) R/W (+DEVIATN)inamantissa-exponent format,interpretedasa4-bitvaluewith MSBimplicit1.Theresultingfrequency 2-FSK/GFSK/4- deviationisgivenby: FSK f f xosc (cid:152)(cid:11)8(cid:14)DEVIATION_M(cid:12)(cid:152)2DEVIATION_E dev 217 Thedefaultvaluesgive±47.607kHz deviationassuming26.0MHzcrystal frequency. OOK Thissettinghasnoeffect 68 DetailedDescription Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L www.ti.com SWRS109C–MAY2011–REVISEDDECEMBER2016 Table5-45.0x16:MCSM2-MainRadioControlStateMachineConfiguration Bit FieldName Reset R/W Description 7:5 R0 Notused DirectRXterminationbasedonRSSImeasurement(carrier 4 RX_TIME_RSSI 0 R/W sense).ForOOKmodulation,RXtimesoutifthereisno carriersenseinthefirst8symbolperiods. 3:0 7(0111) R/W UsesettingfromSmartRFStudio Table5-46.0x17:MCSM1-MainRadioControlStateMachineConfiguration Bit FieldName Reset R/W Description 7:6 R0 Notused SelectsCCA_MODE;ReflectedinCCAsignal Setting Clearchannelindication 0(00) Always 5:4 CCA_MODE 3(11) R/W 1(01) IfRSSIbelowthreshold 2(10) Unlesscurrentlyreceivingapacket IfRSSIbelowthresholdunlesscurrently 3(11) receivingapacket Selectwhatshouldhappenwhenapackethasbeenreceived. Setting Nextstateafterfinishingpacketreception 0(00) IDLE 3:2 RXOFF_MODE[1:0] 0(00) R/W 1(01) FSTXON 2(10) TX 3(11) StayinRX Selectwhatshouldhappenwhenapackethasbeensent Setting Nextstateafterfinishingpackettransmission 0(00) IDLE 1:0 TXOFF_MODE[1:0] 0(00) R/W 1(01) FSTXON 2(10) StayinTX(startsendingpreamble) 3(11) RX Copyright©2011–2016,TexasInstrumentsIncorporated DetailedDescription 69 SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L SWRS109C–MAY2011–REVISEDDECEMBER2016 www.ti.com Table5-47.0x18:MCSM0-MainRadioControlStateMachineConfiguration Bit FieldName Reset R/W Description 7:6 R0 Notused AutomaticallycalibratewhengoingtoRXorTX,orbackto IDLE Setting Whentoperformautomaticcalibration 0(00) Never(manuallycalibrateusingSCALstrobe) 5:4 FS_AUTOCAL[1:0] 0(00) R/W 1(01) WhengoingfromIDLEtoRXorTX(or FSTXON) WhengoingfromRXorTXbacktoIDLE 2(10) automatically Every4thtimewhengoingfromRXorTXto 3(11) IDLEautomatically Programsthenumberoftimesthesix-bitripplecountermust expireaftertheXOSChassettledbeforeCHP_RDYngoes low.(1) IfXOSCison(stable)duringpower-down,PO_TIMEOUT shallbesetsothattheregulateddigitalsupplyvoltagehas timetostabilizebeforeCHP_RDYngoeslow (PO_TIMEOUT=2recommended).Typicalstart-uptimeforthe voltageregulatoris50μs. ForrobustoperationitisrecommendedtousePO_TIMEOUT =2or3whenXOSCisoffduringpower-down. Timeoutafter Setting Expirecount 3:2 PO_TIMEOUT 1(01) R/W XOSCstart Approximately2.3 0(00) 1 -2.4μs Approximately37- 1(01) 16 39μs Approximately149 2(10) 64 -155μs Approximately597 3(11) 256 -620μs Exacttimeoutdependsoncrystalfrequency. 1 0 R/W UsesettingfromSmartRFStudio 0 XOSC_FORCE_ON 0 R/W ForcetheXOSCtostayonintheSLEEPstate. (1) NotethattheXOSC_STABLEsignalwillbeassertedatthesametimeastheCHIP_RDYnsignal;thatis,thePO_TIMEOUTdelaysboth signalsanddoesnotinsertadelaybetweenthesignals. Table5-48.0x19:FOCCFG-FrequencyOffsetCompensationConfiguration Bit FieldName Reset R/W Description 7:6 R0 Notused Ifset,thedemodulatorfreezesthefrequencyoffset 5 FOC_BS_CS_GATE 1 R/W compensationandclockrecoveryfeedbackloopsuntiltheCS signalgoeshigh. Thefrequencycompensationloopgaintobeusedbeforea syncwordisdetected. Setting Freq.compensationloopgainbeforesyncword 4:3 FOC_PRE_K[1:0] 2(10) R/W 0(00) K 1(01) 2K 2(10) 3K 3(11) 4K 70 DetailedDescription Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L www.ti.com SWRS109C–MAY2011–REVISEDDECEMBER2016 Table5-48.0x19:FOCCFG-FrequencyOffsetCompensationConfiguration(continued) Bit FieldName Reset R/W Description Thefrequencycompensationloopgaintobeusedafterasync wordisdetected. 2 FOC_POST_K 1 R/W Setting Freq.compensationloopgainaftersyncword 0 SameasFOC_PRE_K 1 K/2 Thesaturationpointforthefrequencyoffsetcompensation algorithm: Setting Saturationpoint(maxcompensatedoffset) 0(00) ±0(nofrequencyoffsetcompensation) 1:0 FOC_LIMIT[1:0] 2(10) R/W 1(01) ±BW /8 CHAN 2(10) ±BW /4 CHAN 3(11) ±BW /2 CHAN FrequencyoffsetcompensationisnotsupportedforOOK. AlwaysuseFOC_LIMIT=0withthismodulationformat. Table5-49.0x1A:BSCFG-BitSynchronizationConfiguration Bit FieldName Reset R/W Description Theclockrecoveryfeedbackloopintegralgaintobeused beforeasyncwordisdetected(usedtocorrectoffsetsindata rate): Clockrecoveryloopintegralgainbeforesync Setting word 7:6 BS_PRE_KI[1:0] 1(01) R/W 0(00) K I 1(01) 2K I 2(10) 3K I 3(11) 4K I Theclockrecoveryfeedbackloopproportionalgaintobeused beforeasyncwordisdetected. Clockrecoveryloopproportionalgainbefore Setting syncword 5:4 BS_PRE_KP[1:0] 2(10) R/W 0(00) K P 1(01) 2K P 2(10) 3K P 3(11) 4K P Theclockrecoveryfeedbackloopintegralgaintobeusedafter asyncwordisdetected. Clockrecoveryloopintegralgainaftersync 3 BS_POST_KI 1 R/W Setting word 0 SameasBS_PRE_KI 1 K /2 I Theclockrecoveryfeedbackloopproportionalgaintobeused afterasyncwordisdetected. Clockrecoveryloopproportionalgainaftersync 2 BS_POST_KP 1 R/W Setting word 0 SameasBS_PRE_KP 1 K P Copyright©2011–2016,TexasInstrumentsIncorporated DetailedDescription 71 SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L SWRS109C–MAY2011–REVISEDDECEMBER2016 www.ti.com Table5-49.0x1A:BSCFG-BitSynchronizationConfiguration(continued) Bit FieldName Reset R/W Description Thesaturationpointforthedatarateoffsetcompensation algorithm: Datarateoffsetsaturation(maxdatarate Setting difference) 1:0 BS_LIMIT[1:0] 0(00) R/W 0(00) ±0(Nodatarateoffsetcompensation performed) 1(01) ±3.125%datarateoffset 2(10) ±6.25%datarateoffset 3(11) ±12.5%datarateoffset Table5-50.0x1B:AGCCTRL2-AGCControl Bit FieldName Reset R/W Description ReducesthemaximumallowableDVGAgain. Setting AllowableDVGAsettings 0(00) Allgainsettingscanbeused 7:6 MAX_DVGA_GAIN[1:0] 0(00) R/W 1(01) Thehighestgainsettingcannotbeused 2(10) The2highestgainsettingscannotbeused 3(11) The3highestgainsettingscannotbeused SetsthemaximumallowableLNA+LNA2gainrelativetothe maximumpossiblegain. Setting MaximumallowableLNA+LNA2gain 0(000) MaximumpossibleLNA+LNA2gain Approximately2.6dBbelowmaximumpossible 1(001) gain Approximately6.1dBbelowmaximumpossible 2(010) gain 5:3 MAX_LNA_GAIN[2:0] 0(000) R/W 3(011) Approximately7.4dBbelowmaximumpossible gain Approximately9.2dBbelowmaximumpossible 4(100) gain Approximately11.5dBbelowmaximum 5(101) possiblegain Approximately14.6dBbelowmaximum 6(110) possiblegain Approximately17.1dBbelowmaximum 7(111) possiblegain Thesebitssetthetargetvaluefortheaveragedamplitudefrom thedigitalchannelfilter(1LSB=0dB). Setting Targetamplitudefromchannelfilter 0(000) 24dB 1(001) 27dB 2:0 MAGN_TARGET[2:0] 3(011) R/W 2(010) 30dB 3(011) 33dB 4(100) 36dB 5(101) 38dB 6(110) 40dB 7(111) 42dB 72 DetailedDescription Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L www.ti.com SWRS109C–MAY2011–REVISEDDECEMBER2016 Table5-51.0x1C:AGCCTRL1-AGCControl Bit FieldName Reset R/W Description 7 R0 Notused SelectsbetweentwodifferentstrategiesforLNAandLNA2gain adjustment.When1,theLNAgainisdecreasedfirst.When0, 6 AGC_LNA_PRIORITY 1 R/W theLNA2gainisdecreasedtominimumbeforedecreasingLNA gain. Setstherelativechangethresholdforassertingcarriersense Setting Carriersenserelativethreshold CARRIER_SENSE_REL_ 0(00) Relativecarriersensethresholddisabled 5:4 0(00) R/W THR[1:0] 1(01) 6dBincreaseinRSSIvalue 2(10) 10dBincreaseinRSSIvalue 3(11) 14dBincreaseinRSSIvalue SetstheabsoluteRSSIthresholdforassertingcarriersense.The 2-complementsignedthresholdisprogrammedinstepsof1dB andisrelativetotheMAGN_TARGETsetting. Carriersenseabsolutethreshold(Equalto Setting channelfilteramplitudewhenAGChasnot decreasedgain) -8(1000) Absolutecarriersensethresholddisabled 3:0 CARRIER_SENSE_ABS_ 0(0000) R/W -7(1001) 7dBbelowMAGN_TARGETsetting THR[3:0] … … -1(1111) 1dBbelowMAGN_TARGETsetting 0(0000) AtMAGN_TARGETsetting 1(0001) 1dBaboveMAGN_TARGETsetting … … 7(0111) 7dBaboveMAGN_TARGETsetting Table5-52.0x1D:AGCCTRL0-AGCControl Bit FieldName Reset R/W Description Setsthelevelofhysteresisonthemagnitudedeviation(internal AGCsignalthatdeterminegainchanges). Setting Description Nohysteresis,smallsymmetricdeadzone,high 0(00) gain 7:6 HYST_LEVEL[1:0] 2(10) R/W Lowhysteresis,smallasymmetricdeadzone, 1(01) mediumgain Mediumhysteresis,mediumasymmetricdead 2(10) zone,mediumgain Largehysteresis,largeasymmetricdeadzone, 3(11) lowgain Setsthenumberofchannelfiltersamplesfromagain adjustmenthasbeenmadeuntiltheAGCalgorithmstarts accumulatingnewsamples. Setting Channelfiltersamples 5:4 WAIT_TIME[1:0] 1(01) R/W 0(00) 8 1(01) 16 2(10) 24 3(11) 32 Copyright©2011–2016,TexasInstrumentsIncorporated DetailedDescription 73 SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L SWRS109C–MAY2011–REVISEDDECEMBER2016 www.ti.com Table5-52.0x1D:AGCCTRL0-AGCControl(continued) Bit FieldName Reset R/W Description ControlwhentheAGCgainshouldbefrozen. Setting Function Normaloperation.Alwaysadjustgainwhen 0(00) required. Thegainsettingisfrozenwhenasyncwordhas 3:2 AGC_FREEZE[1:0] 0(00) R/W 1(01) beenfound. Manuallyfreezetheanaloguegainsettingand 2(10) continuetoadjustthedigitalgain. Manuallyfreezesboththeanalogueandthe 3(11) digitalgainsetting.Usedformanuallyoverriding thegain. 2-FSKand4-FSK:Setstheaveraginglengthfortheamplitude fromthechannelfilter.OOK:SetstheOOKdecisionboundary forOOKreception. OOKdecision Setting Channelfiltersamples boundary 1:0 FILTER_LENGTH[1:0] 1(01) R/W 0(00) 8 4dB 1(01) 16 8dB 2(10) 32 12dB 3(11) 64 16dB Table5-53.0x20:RESERVED Bit FieldName Reset R/W Description 7:3 31(11111) R/W UsesettingfromSmartRFStudio 2 R0 Notused 1:0 0(00) R/W UsesettingfromSmartRFStudio Table5-54.0x21:FREND1-FrontEndRXConfiguration Bit FieldName Reset R/W Description 7:6 LNA_CURRENT[1:0] 1(01) R/W Adjustsfront-endLNAPTATcurrentoutput 5:4 LNA2MIX_CURRENT[1:0] 1(01) R/W Adjustsfront-endPTAToutputs LODIV_BUF_CURRENT_ 3:2 1(01) R/W AdjustscurrentinRXLObuffer(LOinputtomixer) RX[1:0] 1:0 MIX_CURRENT[1:0] 2(10) R/W Adjustscurrentinmixer Table5-55.0x22:FREND0-FrontEndTXConfiguration Bit FieldName Reset R/W Description 7:6 R0 Notused LODIV_BUF_CURRENT_ AdjustscurrentTXLObuffer(inputtoPA).Thevaluetousein 5:4 1(01) R/W TX[1:0] thisfieldisgivenbytheSmartRFStudiosoftware. 3 R0 Notused SelectsPApowersetting.Thisvalueisanindextothe PATABLE,whichcanbeprogrammedwithupto2differentPA 2:0 PA_POWER[2:0] 0(000) R/W settings.WhenusingOOK,PA_POWERshouldbe001,andfor allothermodulationformatsitshouldbe000,seeSection5.11. Table5-56.0x23:FSCAL3-FrequencySynthesizerCalibration Bit FieldName Reset R/W Description Frequencysynthesizercalibrationconfiguration.Thevalueto 7:6 FSCAL3[7:6] 2(10) R/W writeinthisfieldbeforecalibrationisgivenbytheSmartRFStudio software. 74 DetailedDescription Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L www.ti.com SWRS109C–MAY2011–REVISEDDECEMBER2016 Table5-56.0x23:FSCAL3-FrequencySynthesizerCalibration(continued) Bit FieldName Reset R/W Description CHP_CURR_CAL_EN[1: 5:4 2(10) R/W Disablechargepumpcalibrationstagewhen0. 0] Frequencysynthesizercalibrationresultregister.Digitalbitvector definingthechargepumpoutputcurrent,onanexponentialscale: 3:0 FSCAL3[3:0] 9(1001) R/W I_OUT=I ×2FSCAL3[3:0]/4 0 SeeSection5.27.2formoredetails. Table5-57.0x24:FSCAL2-FrequencySynthesizerCalibration Bit FieldName Reset R/W Description 7:6 R0 Notused 5 VCO_CORE_H_EN 0 R/W Choosehigh(1)/low(0)VCO Frequencysynthesizercalibrationresultregister.VCOcurrent 4:0 FSCAL2[4:0] 10(01010) R/W calibrationresultandoverridevalue.SeeSection5.27.2formore details. Table5-58.0x25:FSCAL1-FrequencySynthesizerCalibration Bit FieldName Reset R/W Description 7:6 R0 Notused Frequencysynthesizercalibrationresultregister.Capacitorarray 5:0 FSCAL1[5:0] 32(0x20) R/W settingforVCOcoarsetuning. SeeSection5.27.2formoredetails. Table5-59.0x26:FSCAL0-FrequencySynthesizerCalibration Bit FieldName Reset R/W Description 7 R0 Notused Frequencysynthesizercalibrationcontrol.Thevaluetouseinthis 6:0 FSCAL0[6:0] 13(0x0D) R/W registerisgivenbytheSmartRFStudiosoftware 5.28.2 Configuration Register Details - Registers that Loose Programming in SLEEP State Table5-60.0x29:RESERVED Bit FieldName Reset R/W Description 7:0 89(0x59) R/W UsesettingfromSmartRFStudio Table5-61.0x2A:RESERVED Bit FieldName Reset R/W Description 7:0 127(0x7F) R/W UsesettingfromSmartRFStudio Table5-62.0x2B:RESERVED Bit FieldName Reset R/W Description 7:0 63(0x3F) R/W UsesettingfromSmartRFStudio Copyright©2011–2016,TexasInstrumentsIncorporated DetailedDescription 75 SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L SWRS109C–MAY2011–REVISEDDECEMBER2016 www.ti.com Table5-63.0x2C:TEST2-VariousTestSettings Bit FieldName Reset R/W Description UsesettingfromSmartRFStudio Thisregisterwillbeforcedto0x88or0x81whenitwakesupfrom SLEEPmode,dependingontheconfigurationof FIFOTHR.ADC_RETENTION. 7:0 TEST2[7:0] 136(0x88) R/W ThevaluereadfromthisregisterwhenwakingupfromSLEEP alwaysistheresetvalue(0x88)regardlessofthe ADC_RETENTIONsetting.Theinvertingofsomeofthebitsdueto theADC_RETENTIONsettingisonlyseenINTERNALLYinthe analogpart. Table5-64.0x2D:TEST1-VariousTestSettings Bit FieldName Reset R/W Description UsesettingfromSmartRFStudioSWRC176 Thisregisterwillbeforcedto0x31or0x35whenitwakesupfrom SLEEPmode,dependingontheconfigurationof FIFOTHR.ADC_RETENTION. 7:0 TEST1[7:0] 49(0x31) R/W ThevaluereadfromthisregisterwhenwakingupfromSLEEP alwaysistheresetvalue(0x31)regardlessofthe ADC_RETENTIONsetting.Theinvertingofsomeofthebitsdueto theADC_RETENTIONsettingisonlyseenINTERNALLYinthe analogpart. Table5-65.0x2E:TEST0-VariousTestSettings Bit FieldName Reset R/W Description 7:2 TEST0[7:2] 2(000010) R/W UsesettingfromSmartRFStudioSWRC176 1 VCO_SEL_CAL_EN 1 R/W EnableVCOselectioncalibrationstagewhen1 0 TEST0[0] 1 R/W UsesettingfromSmartRFStudioSWRC176 5.28.3 Status Register Details Table5-66.0x30(0xF0):PARTNUM-ChipID Bit FieldName Reset R/W Description 7:0 PARTNUM[7:0] 0(0x00) R Chippartnumber Table5-67.0x31(0xF1):VERSION-ChipID Bit FieldName Reset R/W Description 7:0 VERSION[7:0] 23(0x17) R Chipversionnumber.Subjecttochangewithoutnotice. Table5-68.0x32(0xF2):FREQEST-FrequencyOffsetEstimatefromDemodulator Bit FieldName Reset R/W Description Theestimatedfrequencyoffset(2scomplement)ofthecarrier. ResolutionisF /214(1.59-1.65kHz);rangeis±202kHzto±210 XTAL kHz,dependingonXTALfrequency. 7:0 FREQOFF_EST R Frequencyoffsetcompensationisonlysupportedfor2-FSK,GFSK, and4-FSKmodulation.Thisregisterwillread0whenusingOOK modulation. Table5-69.0x33(0xF3):CRC_REG-CRCOK Bit FieldName Reset R/W Description ThelastCRCcomparisonmatched.Clearedwhen 7 CRCOK R entering/restartingRXmode. 6:0 R Reserved 76 DetailedDescription Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L www.ti.com SWRS109C–MAY2011–REVISEDDECEMBER2016 Table5-70.0x34(0xF4):RSSI-ReceivedSignalStrengthIndication Bit FieldName Reset R/W Description 7:0 RSSI R Receivedsignalstrengthindicator Table5-71.0x35(0xF5):MARCSTATE-MainRadioControlStateMachineState Bit FieldName Reset R/W Description 7:5 R0 Notused MainRadioControlFSMState Value Statename State(seeFigure5-11) 0(0x00) SLEEP SLEEP 1(0x01) IDLE IDLE 2(0x02) XOFF XOFF 3(0x03) VCOON_MC MANCAL 4(0x04) REGON_MC MANCAL 5(0x05) MANCAL MANCAL 6(0x06) VCOON FS_WAKEUP 7(0x07) REGON FS_WAKEUP 8(0x08) STARTCAL CALIBRATE 9(0x09) BWBOOST SETTLING 10(0x0A) FS_LOCK SETTLING 11(0x0B) IFADCON SETTLING 4:0 MARC_STATE[4:0] R 12(0x0C) ENDCAL CALIBRATE 13(0x0D) RX RX 14(0x0E) RX_END RX 15(0x0F) RX_RST RX 16(0x10) TXRX_SWITCH TXRX_SETTLING RXFIFO_OVERFL 17(0x11) RXFIFO_OVERFLOW OW 18(0x12) FSTXON FSTXON 19(0x13) TX TX 20(0x14) TX_END TX 21(0x15) RXTX_SWITCH RXTX_SETTLING TXFIFO_UNDERF 22(0x16) TXFIFO_UNDERFLOW LOW Note:itisnotpossibletoreadbacktheSLEEPorXOFFstate numbersbecausesettingCSnlowwillmakethechipentertheIDLE modefromtheSLEEPorXOFFstates. Table5-72.0x38(0xF8):PKTSTATUS-CurrentGDOxStatusandPacketStatus Bit FieldName Reset R/W Description ThelastCRCcomparisonmatched.Clearedwhenentering/restarting 7 CRC_OK R RXmode. 6 CS R Carriersense.ClearedwhenenteringIDLEmode. 5 Reserved 4 CCA R Channelisclear StartofFrameDelimiter.Thisbitisassertedwhensyncwordhas beenreceivedanddeassertedattheendofthepacket.Itwillalso 3 SFD R de-assertwhenapacketisdiscardedduetoaddressormaximum lengthfilteringortheradioentersRXFIFO_OVERFLOWstate. Copyright©2011–2016,TexasInstrumentsIncorporated DetailedDescription 77 SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L SWRS109C–MAY2011–REVISEDDECEMBER2016 www.ti.com Table5-72.0x38(0xF8):PKTSTATUS-CurrentGDOxStatusandPacketStatus(continued) Bit FieldName Reset R/W Description CurrentGDO2value.Note:thereadinggivesthenon-invertedvalue irrespectiveofwhatIOCFG2.GDO2_INVisprogrammedto. 2 GDO2 R ItisnotrecommendedtocheckforPLLlockbyreading PKTSTATUS[2]withGDO2_CFG=0x0A. 1 R Notused CurrentGDO0value.Note:thereadinggivesthenon-invertedvalue irrespectiveofwhatIOCFG0.GDO0_INVisprogrammedto. 0 GDO0 R ItisnotrecommendedtocheckforPLLlockbyreading PKTSTATUS[0]withGDO0_CFG=0x0A. Table5-73.0x3A(0xFA):TXBYTES-UnderflowandNumberofBytes Bit FieldName Reset R/W Description 7 TXFIFO_UNDERFLOW R 6:0 NUM_TXBYTES R NumberofbytesinTXFIFO Table5-74.0x3B(0xFB):RXBYTES-OverflowandNumberofBytes Bit FieldName Reset R/W Description 7 RXFIFO_OVERFLOW R 6:0 NUM_RXBYTES R NumberofbytesinRXFIFO 78 DetailedDescription Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L www.ti.com SWRS109C–MAY2011–REVISEDDECEMBER2016 5.29 Development Kit Ordering Information OrderableEvaluationModule Description MinimumOrderQuantity CC11xLDK-868-915 CC11xLDevelopmentKit,868/915MHz 1 CC11xLEMK-433 CC11xLEvaluationModuleKit,433MHz 1 RFBoosterPackforMSP430LaunchPad Plug-inboardsfortheMSP430ValueLine 1 LaunchPad(MSP-EXP430G2),868/915MHz Copyright©2011–2016,TexasInstrumentsIncorporated DetailedDescription 79 SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L SWRS109C–MAY2011–REVISEDDECEMBER2016 www.ti.com 6 Applications, Implementation, and Layout Thelowcostapplicationcircuits(SWRR081and SWRR082),whichusemultilayerinductors,areshownin Figure6-1andFigure6-2(seeTable6-1forcomponentvalues). The designs in SWRR046 and SWRR045 were used for CC110L characterization. The 315 MHz and 433 MHz design SWRR046 use inexpensive multi-layer inductors similar to the low cost application circuit while the 868 MHz and 915 MHz design SWRR045 use wire-wound inductors. Wire-wound inductors give betteroutputpowerandattenuationofharmonicscomparedtousingmulti-layerinductors. Refer to design note DN032 SWRA346 for information about performance when using wire-wound inductors from different vendors. See also Design Note DN013 SWRA168, which gives the output power and harmonics when using multi-layer inductors. The output power is then typically +10 dBm when operatingat868/915MHz. 6.1 Bias Resistor The56-kΩ biasresistorR171isusedtosetanaccuratebiascurrent. 6.2 Balun and RF Matching The balun and LC filter component values and their placement are important to keep the performance optimized. Gerber files and schematics for the reference designs are available for download from the TI website. The components between the RF_N/RF_P pins and the point where the two signals are joined together (C131, C122, L122, and L132 in Figure 6-1 and L121, L131, C121, L122, C131, C122, and L132 in Figure 6-2) form a balun that converts the differential RF signal on CC110L to a single-ended RF signal. C124isneededforDCblocking.L123,L124,andC123(plusC125inFigure6-1)formalow-passfilterfor harmonicsattenuation. The balun and LC filter components also matches the CC110L input impedance to a 50-Ω load. C126 provides DC blocking and is only needed if there is a DC path in the antenna. For the application circuit in Figure6-2,thiscomponentmayalsobeusedforadditionalfiltering,seeSection6.5. 1.8V-3.6V Power supply R171 SI SI 20 ND 19 RD 18 AS17 ND 16 Antenna SCLK G GUA RBI G (50Ohm) 1SCLK D AVDD15 e SO 2SO CC110L C131 efac G(GDDOO21) (GDO1) AVDD14 L132 C126 nt (optional) 3GDO2 RF_N13 al I 4DVDD DIEATTACHPAD: RF_P12 L123 L124 Digit C51 5DCOUPL6GDO0 7CSn 8XOSC_Q1 9AVDD 10XOSC_Q2 AVDD11 CL112224C122 C123 C125 GDO0 (optional) CSn XTAL C81 C101 Figure6-1.TypicalApplicationandEvaluationCircuit315or433MHz (ExcludingSupplyDecouplingCapacitors) 80 Applications,Implementation,andLayout Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L www.ti.com SWRS109C–MAY2011–REVISEDDECEMBER2016 1.8 V - 3.6 V Power Supply R171 SI 0 9 8 7 6 2 1 1 1 1 SI ND RD AS ND Antenna SCLK G UA RBI G C131 (50W) 1 SCLK G AVDD 15 D ce SO 2 SO AVDD 14 L131 L132 nterfa G((oGDpDtOiOo2n1a)l) 3( GGDDOO12) CC110LRF_N 13 L123 L124 C126 al I 4 DVDD DIEATTACH PAD: RF_P12 C121 C122 Digit C51 5 DCOUP6 GDO0L 7 CSn 8 XOSC_Q1 9AVDD 10 XOSC_Q2AVDD 11 L121 L122 C123 C127 L125 C127 and L125 GDO0 C124 may be added to (optional) CSn build an optional filter to reduce XTAL emission at 699 MHz C81 C101 Figure6-2.TypicalApplicationandEvaluationCircuit868/915MHz (ExcludingSupplyDecouplingCapacitors) Table6-1.ExternalComponents Component Valueat315MHz Valueat433MHz Valueat868/915MHz WithoutC127andL125 WithC127andL125 C121 1pF 1pF C122 6.8pF 3.9pF 1.5pF 1.5pF C123 12pF 8.2pF 3.3pF 3.3pF C124 220pF 220pF 100pF 100pF C125 6.8pF 5.6pF C126 220pF 220pF 100pF 12pF C127 47pF C131 6.8pF 3.9pF 1.5pF 1.5pF L121 12nH 12nH L122 33nH 27nH 18nH 18nH L123 18nH 22nH 12nH 12nH L124 33nH 27nH 12nH 12nH L125 3.3nH L131 12nH 12nH L132 33nH 27nH 18nH 18nH Copyright©2011–2016,TexasInstrumentsIncorporated Applications,Implementation,andLayout 81 SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L SWRS109C–MAY2011–REVISEDDECEMBER2016 www.ti.com 6.3 Crystal A crystal in the frequency range 26 - 27 MHz must be connected between the XOSC_Q1 and XOSC_Q2 pins. The oscillator is designed for parallel mode operation of the crystal. In addition, loading capacitors (C81 and C101) for the crystal are required. The loading capacitor values depend on the total load capacitance, CL, specified for the crystal. The total load capacitance seen between the crystal terminals shouldequalCLforthecrystaltooscillateatthespecifiedfrequency. 1 C = +C L 1 1 parasitic + C C 81 101 (9) The parasitic capacitance is constituted by pin input capacitance and PCB stray capacitance. Total parasiticcapacitanceistypically2.5pF. The crystal oscillator is amplitude regulated. This means that a high current is used to start up the oscillations. When the amplitude builds up, the current is reduced to what is necessary to maintain approximately 0.4 Vpp signal swing. This ensures a fast start-up, and keeps the drive level to a minimum. The ESR of the crystal should be within the specification in order to ensure a reliable start-up (see Section4.9). Theinitialtolerance,temperaturedrift,agingandloadpullingshouldbecarefullyspecifiedinordertomeet therequiredfrequencyaccuracyinacertainapplication. Avoid routing digital signals with sharp edges close to XOSC_Q1 PCB track or underneath the crystal dc operatingpointandresultindutycyclevariation. For compliance with modulation bandwidth requirements under EN 300 220 V2.3.1 in the 863 to 870 MHz frequencyrangeitisrecommendedtousea26MHzcrystalforfrequenciesbelow869MHzanda27MHz crystalforfrequenciesabove869MHz. 6.4 Reference Signal Thechipcanalternativelybeoperatedwithareferencesignalfrom26to27MHzinsteadofacrystal.This input clock can either be a full- swing digital signal (0 V to VDD) or a sine wave of maximum 1 V peak- peak amplitude. The reference signal must be connected to the XOSC_Q1 input. The sine wave must be connected to XOSC_Q1 using a serial capacitor. When using a full-swing digital signal, this capacitor can be omitted. The XOSC_Q2 line must be left un-connected. C81 and C101 can be omitted when using a referencesignal. 6.5 Additional Filtering In the 868/915 MHz reference design SWRR082, C127 and L125 together with C126 build an optional filter to reduce emission at carrier frequency - 169 MHz. This filter is necessary for applications with an external antenna connector that seek compliance with ETSI EN 300 220 V2.3.1. For more information, see DN017 SWRA168. If this filtering is not necessary, C126 will work as a DC block (only necessary if there is a DC path in the antenna). C127 and L125 should in that case be left unmounted. Additional external components (that is, an RF SAW filter) may be used in order to improve the performance in specificapplications. 6.6 Power Supply Decoupling The power supply must be properly decoupled close to the supply pins. Note that decoupling capacitors are not shown in the application circuit. The placement and the size of the decoupling capacitors are very importanttoachievetheoptimumperformance(SWRR081 andSWRR082 shouldbefollowedclosely). 82 Applications,Implementation,andLayout Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L www.ti.com SWRS109C–MAY2011–REVISEDDECEMBER2016 6.7 PCB Layout Recommendations The top layer should be used for signal routing, and the open areas should be filled with metallization connectedtogroundusingseveralvias. The area under the chip is used for grounding and shall be connected to the bottom ground plane with severalviasforgoodthermalperformanceandsufficientlylowinductancetoground. In SWRR081 and SWRR082, 5 vias are placed inside the exposed die attached pad. These vias should be “tented” (covered with solder mask) on the component side of the PCB to avoid migration of solder throughtheviasduringthesolderreflowprocess. The solder paste coverage should not be 100%. If it is, out gassing may occur during the reflow process, which may cause defects (splattering, solder balling). Using “tented” vias reduces the solder paste coveragebelow100%.SeeFigure6-3fortopsolderresistandtoppastemasks. Each decoupling capacitor should be placed as close as possible to the supply pin it is supposed to decouple. Each decoupling capacitor should be connected to the power line (or power plane) by separate vias. The best routing is from the power line (or power plane) to the decoupling capacitor and then to the CC110Lsupplypin.Supplypowerfilteringisveryimportant. Each decoupling capacitor ground pad should be connected to the ground plane by separate vias. Direct connections between neighboring power pins will increase noise coupling and should be avoided unless absolutely necessary. Routing in the ground plane underneath the chip or the balun/RF matching circuit, or between the chip's ground vias and the decoupling capacitor's ground vias should be avoided. This improvesthegroundingandensurestheshortestpossiblecurrentreturnpath. Avoid routing digital signals with sharp edges close to XOSC_Q1 PCB track or underneath the crystal Q1 padasthismayshiftthecrystaldcoperatingpointandresultindutycyclevariation. The external components should ideally be as small as possible (0402 is recommended) and surface mount devices are highly recommended. Components with different sizes than those specified may have differingcharacteristics. Precaution should be used when placing the microcontroller in order to avoid noise interfering with the RF circuitry. A CC11xL Development Kit with a fully assembled CC110L Evaluation Module is available. It is strongly advised that this reference layout is followed very closely in order to get the best performance. The schematic,BOMandlayoutGerberfilesareallavailablefromtheTIwebsite(SWRR081and SWRR082). Figure6-3.Left:TopSolderResistMask(Negative) – Right:TopPasteMask.CirclesareVias Copyright©2011–2016,TexasInstrumentsIncorporated Applications,Implementation,andLayout 83 SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L SWRS109C–MAY2011–REVISEDDECEMBER2016 www.ti.com 7 Device and Documentation Support 7.1 Device Support 7.1.1 Device Nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all microprocessors (MPUs) and support tools. Each device has one of three prefixes: X, P, or null (no prefix) (for example, CC110L). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development fromengineeringprototypes(TMDX)throughfullyqualifiedproductiondevicesandtools(TMDS). Devicedevelopmentevolutionaryflow: X Experimental device that is not necessarily representative of the final device's electrical specificationsandmaynotuseproductionassemblyflow. P Prototype device that is not necessarily the final silicon die and may not necessarily meet finalelectricalspecifications. null Productionversionofthesilicondiethatisfullyqualified. Supporttooldevelopmentevolutionaryflow: TMDX Development-support product that has not yet completed Texas Instruments internal qualificationtesting. TMDS Fully-qualifieddevelopment-supportproduct. XandPdevicesandTMDXdevelopment-supporttoolsareshippedagainstthefollowingdisclaimer: "Developmentalproductisintendedforinternalevaluationpurposes." Production devices and TMDS development-support tools have been characterized fully, and the quality andreliabilityofthedevicehavebeendemonstratedfully.TI'sstandardwarrantyapplies. Predictions show that prototype devices (X or P) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, RGP) and the temperature range (for example, blank is the default commercialtemperaturerange). For orderable part numbers of CC110L devices in the QFN package types, see the Package Option Addendumofthisdocument,theTIwebsite(www.ti.com),orcontactyourTIsalesrepresentative. 84 DeviceandDocumentationSupport Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L www.ti.com SWRS109C–MAY2011–REVISEDDECEMBER2016 7.2 Documentation Support 7.2.1 Related Documentation from Texas Instruments The following documents describe the CC110L transceiver. Copies of these documents are available on theInternetatwww.ti.com. SWRR046 Characterization Design 315 - 433 MHz (Identical to the CC1101EM 315 - 433 MHz ReferenceDesign) SWRR045 Characterization Design 868 - 915 MHz (Identical to the CC1101EM 868 - 915 MHz ReferenceDesign) SWRZ037 CC110LErrataNotes SWRC176 SmartRFStudio SWRA147 DN010Close-inReceptionwithCC1101 SWRA168 DN017CC11xx868/915MHzRFMatching SWRA159 DN015PermanentFrequencyOffsetCompensation SWRA123 DN006CC11xxSettingsforFCC15.247Solutions SWRA114 DN505RSSIInterpretationandTiming SWRA168 DN013ProgrammingOutputPoweronCC1101 SWRA215 DN022CC11xxOOK/ASKregistersettings SWRA122 DN005CC11xxSensitivityversusFrequencyOffsetandCrystalAccuracy SWRS089 CC1190DataSheet SWRA356 AN094UsingtheCC1190FrontEndwithCC1101underEN300220 SWRA361 AN096UsingtheCC1190FrontEndwithCC1101underFCC15.247 SWRA346 DN032OptionsforCostOptimizedCC11xxMatching SWRR081 CC110LEM/CC115LEM433MHzReferenceDesign SWRR082 CC110LEM/CC115LEM868-915MHzReferenceDesign 7.2.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; seeTI's TermsofUse. TIE2E™OnlineCommunity The TI engineer-to-engineer (E2E) community was created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, exploreideasandhelpsolveproblemswithfellowengineers. TIEmbeddedProcessorsWiki Established to help developers get started with Embedded Processors from Texas Instruments and to foster innovation and growth of general knowledge about the hardwareandsoftwaresurroundingthesedevices. 7.3 Trademarks E2EisatrademarkofTexasInstruments. Allothertrademarksarethepropertyoftheirrespectiveowners. 7.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. 7.5 Export Control Notice Copyright©2011–2016,TexasInstrumentsIncorporated DeviceandDocumentationSupport 85 SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L SWRS109C–MAY2011–REVISEDDECEMBER2016 www.ti.com Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled product restricted by other applicable national regulations, received from Disclosing party under this Agreement, or any direct product of such technology, to any destination to which such export or re- exportisrestrictedorprohibitedbyU.S.orotherapplicablelaws,withoutobtainingpriorauthorizationfrom U.S. Department of Commerce and other competent Government authorities to the extent required by thoselaws. 7.6 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronymsanddefinitions. 7.7 Additional Acronyms Additionalacronymsusedinthisdatasheetaredescribedbelow. 2-FSK BinaryFrequencyShiftKeying ADC AnalogtoDigitalConverter AFC AutomaticFrequencyCompensation AGC AutomaticGainControl AMR AutomaticMeterReading BER BitErrorRate BT Bandwidth-Timeproduct CCA ClearChannelAssessment CFR CodeofFederalRegulations CRC CyclicRedundancyCheck CS CarrierSense CW ContinuousWave(UnmodulatedCarrier) DC DirectCurrent DVGA DigitalVariableGainAmplifier ESR EquivalentSeriesResistance FCC FederalCommunicationsCommission FHSS FrequencyHoppingSpreadSpectrum FS FrequencySynthesizer GFSK GaussianshapedFrequencyShiftKeying IF IntermediateFrequency I/Q In-Phase/Quadrature ISM Industrial,Scientific,Medical LC Inductor-Capacitor LNA LowNoiseAmplifier LO LocalOscillator LSB LeastSignificantBit MCU MicrocontrollerUnit MSB MostSignificantBit NRZ NonReturntoZero(Coding) 86 DeviceandDocumentationSupport Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L www.ti.com SWRS109C–MAY2011–REVISEDDECEMBER2016 OOK On-OffKeying PA PowerAmplifier PCB PrintedCircuitBoard PD PowerDown PER PacketErrorRate PLL PhaseLockedLoop POR Power-OnReset PQI PreambleQualityIndicator PTAT ProportionalToAbsoluteTemperature QLP QuadLeadlessPackage QPSK QuadraturePhaseShiftKeying RC Resistor-Capacitor RF RadioFrequency RSSI ReceivedSignalStrengthIndicator RX Receive,ReceiveMode SMD SurfaceMountDevice SNR SignaltoNoiseRatio SPI SerialPeripheralInterface SRD ShortRangeDevices T/R Transmit/Receive TX Transmit,TransmitMode VCO VoltageControlledOscillator XOSC CrystalOscillator XTAL Crystal Copyright©2011–2016,TexasInstrumentsIncorporated DeviceandDocumentationSupport 87 SubmitDocumentationFeedback ProductFolderLinks:CC110L

CC110L SWRS109C–MAY2011–REVISEDDECEMBER2016 www.ti.com 8 Mechanical Packaging and Orderable Information 8.1 Packaging Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revisionofthisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 88 MechanicalPackagingandOrderableInformation Copyright©2011–2016,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC110L

PACKAGE OPTION ADDENDUM www.ti.com 1-Sep-2018 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) CC110LRGPR ACTIVE QFN RGP 20 3000 Green (RoHS CU NIPDAU | Level-3-260C-168 HR -40 to 85 CC110L & no Sb/Br) CU NIPDAUAG CC110LRGPT ACTIVE QFN RGP 20 250 Green (RoHS CU NIPDAU | Level-3-260C-168 HR -40 to 85 CC110L & no Sb/Br) CU NIPDAUAG (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 1-Sep-2018 Addendum-Page 2

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IMPORTANTNOTICE TexasInstrumentsIncorporated(TI)reservestherighttomakecorrections,enhancements,improvementsandotherchangestoits semiconductorproductsandservicesperJESD46,latestissue,andtodiscontinueanyproductorserviceperJESD48,latestissue.Buyers shouldobtainthelatestrelevantinformationbeforeplacingordersandshouldverifythatsuchinformationiscurrentandcomplete. TI’spublishedtermsofsaleforsemiconductorproducts(http://www.ti.com/sc/docs/stdterms.htm)applytothesaleofpackagedintegrated circuitproductsthatTIhasqualifiedandreleasedtomarket.AdditionaltermsmayapplytotheuseorsaleofothertypesofTIproductsand services. ReproductionofsignificantportionsofTIinformationinTIdatasheetsispermissibleonlyifreproductioniswithoutalterationandis accompaniedbyallassociatedwarranties,conditions,limitations,andnotices.TIisnotresponsibleorliableforsuchreproduced documentation.Informationofthirdpartiesmaybesubjecttoadditionalrestrictions.ResaleofTIproductsorserviceswithstatements differentfromorbeyondtheparametersstatedbyTIforthatproductorservicevoidsallexpressandanyimpliedwarrantiesforthe associatedTIproductorserviceandisanunfairanddeceptivebusinesspractice.TIisnotresponsibleorliableforanysuchstatements. BuyersandotherswhoaredevelopingsystemsthatincorporateTIproducts(collectively,“Designers”)understandandagreethatDesigners remainresponsibleforusingtheirindependentanalysis,evaluationandjudgmentindesigningtheirapplicationsandthatDesignershave fullandexclusiveresponsibilitytoassurethesafetyofDesigners'applicationsandcomplianceoftheirapplications(andofallTIproducts usedinorforDesigners’applications)withallapplicableregulations,lawsandotherapplicablerequirements.Designerrepresentsthat,with respecttotheirapplications,Designerhasallthenecessaryexpertisetocreateandimplementsafeguardsthat(1)anticipatedangerous consequencesoffailures,(2)monitorfailuresandtheirconsequences,and(3)lessenthelikelihoodoffailuresthatmightcauseharmand takeappropriateactions.DesigneragreesthatpriortousingordistributinganyapplicationsthatincludeTIproducts,Designerwill thoroughlytestsuchapplicationsandthefunctionalityofsuchTIproductsasusedinsuchapplications. TI’sprovisionoftechnical,applicationorotherdesignadvice,qualitycharacterization,reliabilitydataorotherservicesorinformation, including,butnotlimitedto,referencedesignsandmaterialsrelatingtoevaluationmodules,(collectively,“TIResources”)areintendedto assistdesignerswhoaredevelopingapplicationsthatincorporateTIproducts;bydownloading,accessingorusingTIResourcesinany way,Designer(individuallyor,ifDesignerisactingonbehalfofacompany,Designer’scompany)agreestouseanyparticularTIResource solelyforthispurposeandsubjecttothetermsofthisNotice. TI’sprovisionofTIResourcesdoesnotexpandorotherwisealterTI’sapplicablepublishedwarrantiesorwarrantydisclaimersforTI products,andnoadditionalobligationsorliabilitiesarisefromTIprovidingsuchTIResources.TIreservestherighttomakecorrections, enhancements,improvementsandotherchangestoitsTIResources.TIhasnotconductedanytestingotherthanthatspecifically describedinthepublisheddocumentationforaparticularTIResource. Designerisauthorizedtouse,copyandmodifyanyindividualTIResourceonlyinconnectionwiththedevelopmentofapplicationsthat includetheTIproduct(s)identifiedinsuchTIResource.NOOTHERLICENSE,EXPRESSORIMPLIED,BYESTOPPELOROTHERWISE TOANYOTHERTIINTELLECTUALPROPERTYRIGHT,ANDNOLICENSETOANYTECHNOLOGYORINTELLECTUALPROPERTY RIGHTOFTIORANYTHIRDPARTYISGRANTEDHEREIN,includingbutnotlimitedtoanypatentright,copyright,maskworkright,or otherintellectualpropertyrightrelatingtoanycombination,machine,orprocessinwhichTIproductsorservicesareused.Information regardingorreferencingthird-partyproductsorservicesdoesnotconstitutealicensetousesuchproductsorservices,orawarrantyor endorsementthereof.UseofTIResourcesmayrequirealicensefromathirdpartyunderthepatentsorotherintellectualpropertyofthe thirdparty,oralicensefromTIunderthepatentsorotherintellectualpropertyofTI. TIRESOURCESAREPROVIDED“ASIS”ANDWITHALLFAULTS.TIDISCLAIMSALLOTHERWARRANTIESOR REPRESENTATIONS,EXPRESSORIMPLIED,REGARDINGRESOURCESORUSETHEREOF,INCLUDINGBUTNOTLIMITEDTO ACCURACYORCOMPLETENESS,TITLE,ANYEPIDEMICFAILUREWARRANTYANDANYIMPLIEDWARRANTIESOF MERCHANTABILITY,FITNESSFORAPARTICULARPURPOSE,ANDNON-INFRINGEMENTOFANYTHIRDPARTYINTELLECTUAL PROPERTYRIGHTS.TISHALLNOTBELIABLEFORANDSHALLNOTDEFENDORINDEMNIFYDESIGNERAGAINSTANYCLAIM, INCLUDINGBUTNOTLIMITEDTOANYINFRINGEMENTCLAIMTHATRELATESTOORISBASEDONANYCOMBINATIONOF PRODUCTSEVENIFDESCRIBEDINTIRESOURCESOROTHERWISE.INNOEVENTSHALLTIBELIABLEFORANYACTUAL, DIRECT,SPECIAL,COLLATERAL,INDIRECT,PUNITIVE,INCIDENTAL,CONSEQUENTIALOREXEMPLARYDAMAGESIN CONNECTIONWITHORARISINGOUTOFTIRESOURCESORUSETHEREOF,ANDREGARDLESSOFWHETHERTIHASBEEN ADVISEDOFTHEPOSSIBILITYOFSUCHDAMAGES. UnlessTIhasexplicitlydesignatedanindividualproductasmeetingtherequirementsofaparticularindustrystandard(e.g.,ISO/TS16949 andISO26262),TIisnotresponsibleforanyfailuretomeetsuchindustrystandardrequirements. WhereTIspecificallypromotesproductsasfacilitatingfunctionalsafetyorascompliantwithindustryfunctionalsafetystandards,such productsareintendedtohelpenablecustomerstodesignandcreatetheirownapplicationsthatmeetapplicablefunctionalsafetystandards andrequirements.Usingproductsinanapplicationdoesnotbyitselfestablishanysafetyfeaturesintheapplication.Designersmust ensurecompliancewithsafety-relatedrequirementsandstandardsapplicabletotheirapplications.DesignermaynotuseanyTIproductsin life-criticalmedicalequipmentunlessauthorizedofficersofthepartieshaveexecutedaspecialcontractspecificallygoverningsuchuse. Life-criticalmedicalequipmentismedicalequipmentwherefailureofsuchequipmentwouldcauseseriousbodilyinjuryordeath(e.g.,life support,pacemakers,defibrillators,heartpumps,neurostimulators,andimplantables).Suchequipmentincludes,withoutlimitation,all medicaldevicesidentifiedbytheU.S.FoodandDrugAdministrationasClassIIIdevicesandequivalentclassificationsoutsidetheU.S. TImayexpresslydesignatecertainproductsascompletingaparticularqualification(e.g.,Q100,MilitaryGrade,orEnhancedProduct). Designersagreethatithasthenecessaryexpertisetoselecttheproductwiththeappropriatequalificationdesignationfortheirapplications andthatproperproductselectionisatDesigners’ownrisk.Designersaresolelyresponsibleforcompliancewithalllegalandregulatory requirementsinconnectionwithsuchselection. DesignerwillfullyindemnifyTIanditsrepresentativesagainstanydamages,costs,losses,and/orliabilitiesarisingoutofDesigner’snon- compliancewiththetermsandprovisionsofthisNotice. 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