Product Sample & Technical Tools & Support & Folder Buy Documents Software Community CC1020 SWRS046H–NOVEMBER2006–REVISEDMARCH2015 CC1020 Low-Power RF Transceiver for Narrowband Systems 1 Device Overview 1.1 Features 1 • TrueSingleChipUHFRFTransceiver • Pb-FreePackage • FrequencyRange402MHzto470MHz • DigitalRSSIandCarrierSenseIndicator and804MHzto960MHz • DataRateupto153.6kBaud • HighSensitivity • OOK,FSK,andGFSKDataModulation – Upto–118dBmfora12.5kHzChannel • IntegratedBitSynchronizer • ProgrammableOutputPower • ImageRejectionMixer • LowCurrentConsumption • ProgrammableFrequencyandAFCMakeCrystal – RX:19.9mA TemperatureDriftCompensationPossibleWithout • LowSupplyVoltage TCXO – 2.3Vto3.6V • SuitableforFrequencyHoppingSystems • NoExternalIFFilterNeeded • SuitedforSystemsTargetingComplianceWith EN300220,FCCCFR47Part15,ARIBSTD-T67, • Low-IFReceiver andARIBSTD-T96 • VeryFewExternalComponentsRequired • DevelopmentKitAvailable • SmallSize • Easy-to-UseSoftwareforGeneratingtheCC1020 – QFN32Package ConfigurationData 1.2 Applications • NarrowbandLow-PowerUHFWirelessData • AMR–AutomaticMeterReading TransmittersandReceiversWithChannel • WirelessAlarmandSecuritySystems SpacingasLowas12.5and25kHz • HomeAutomation • 402-,424-,426-,429-,433-,447-,449-,469-, • LowPowerTelemetry 868-,915-,960-MHzISM/SRDBandSystems 1.3 Description CC1020 is a true single-chip UHF transceiver designed for very low-power and very low-voltage wireless applications. The circuit is mainly intended for the ISM (Industrial, Scientific, and Medical) and SRD (Short Range Device) frequency bands at 402-, 424-, 426-, 429-, 433-, 447-, 449-, 469-, 868-, 915-, and 960- MHz, but can easily be programmed for multichannel operation at other frequencies in the 402- to 470- MHzand804-to960-MHzrange. The CC1020 device is especially suited for narrow-band systems with channel spacing of 12.5 or 25 kHz complyingwithARIBSTD-T67andEN300220. The main operating parameters of the CC1020 device can be programmed with a serial bus, thus making CC1020averyflexibleandeasy-to-usetransceiver. In a typical system, the CC1020 device will be used together with a microcontroller and a few external passivecomponents. TI recommends using the latest RF performance line device CC1120 as successor of CC1020: www.ti.com/rfperformanceline Table1-1.DeviceInformation(1) PARTNUMBER PACKAGE BODYSIZE(NOM) CC1020 VQFNP(32) 7.00mm×7.00mm (1) Formoreinformation,seeSection8,MechanicalPackagingandOrderableInformation. 1 AnIMPORTANTNOTICEattheendofthisdatasheetaddressesavailability,warranty,changes,useinsafety-criticalapplications, intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.

CC1020 SWRS046H–NOVEMBER2006–REVISEDMARCH2015 www.ti.com 1.4 Functional Block Diagram Figure1-1showsthesystemblockdiagramoftheCC1020device. ADC DIGITAL DEMODULATOR -DigitalRSSI RF_IN LNA LNA2 -GainControl -ImageSuppression -ChannelFiltering ADC -Demodulation 0 er :2 x 90 e Multipl 900 :2 SFYRNETQH NTROLOGIC INDTTIEGORITFmACALCE PDO OL PDI C PCLK Power PSEL Control DIGITAL Multiplexer MODULATOR -Modulation RF_OUT PA -Datashaping BIAS XOSC -PowerControl PA_EN LNA_EN R_BIAS XOSC_Q1 XOSC_Q2 VC CHP_OUT Figure1-1.FunctionalBlockDiagram 2 DeviceOverview Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 www.ti.com SWRS046H–NOVEMBER2006–REVISEDMARCH2015 Table of Contents 1 DeviceOverview......................................... 1 5.7 DataRateProgramming............................ 24 .............................................. ............................ 1.1 Features 1 5.8 FrequencyProgramming 26 ........................................... ............................................. 1.2 Applications 1 5.9 Receiver 27 ............................................ .......................................... 1.3 Description 1 5.10 Transmitter 39 ............................ ............ 1.4 FunctionalBlockDiagram 2 5.11 InputandOutputMatchingandFiltering 42 2 Revision History......................................... 4 5.12 FrequencySynthesizer.............................. 45 3 TerminalConfigurationandFunctions.............. 5 5.13 VCOandLNACurrentControl...................... 51 .......................................... ................................. 3.1 PinDiagram 5 5.14 PowerManagement 51 ..................................... ............................... 3.2 PinConfiguration 5 5.15 On-OffKeying(OOK) 53 4 Specifications ............................................ 7 5.16 CrystalOscillator.................................... 55 .......................... ..................... 4.1 AbsoluteMaximumRatings 7 5.17 Built-inTestPatternGenerator 56 .......................................... ............................... 4.2 ESDRatings 7 5.18 InterruptonPinDCLK 56 ................ ........... 4.3 RecommendedOperatingConditions 7 5.19 PA_ENandLNA_ENDigitalOutputPins 57 .......................................... ............. 4.4 RF Transmit 8 5.20 SystemConsiderationsandGuidelines 58 ........................................... ............................. 4.5 RF Receive 9 5.21 AntennaConsiderations 61 ................................ ............................. 4.6 RSSI/CarrierSense 12 5.22 ConfigurationRegisters 62 4.7 IntermediateFrequency(IF)........................ 12 6 Applications,Implementation,andLayout........ 83 .................................... .............................. 4.8 CrystalOscillator 13 6.1 ApplicationInformation 83 .............................. ............................... 4.9 FrequencySynthesizer 14 6.2 DesignRequirements 85 .......................... ..................... 4.10 DigitalInputsandOutputs 15 6.3 PCBLayoutRecommendations 86 4.11 CurrentConsumption............................... 16 7 DeviceandDocumentationSupport............... 87 4.12 ThermalResistanceCharacteristicsforVQFNP 7.1 DeviceSupport...................................... 87 ............................................. Package 16 ............................. 7.2 DocumentationSupport 87 5 DetailedDescription................................... 17 .......................................... 7.3 Trademarks 88 ............................................ 5.1 Overview 17 ..................... 7.4 ElectrostaticDischargeCaution 88 ........................... 5.2 FunctionalBlockDiagram 17 ............................... 7.5 ExportControlNotice 88 ............................. 5.3 ConfigurationOverview 18 ............................................. 7.6 Glossary 88 ............................. 5.4 MicrocontrollerInterface 19 8 MechanicalPackagingandOrderable 5.5 4-wireSerialConfigurationInterface................ 20 Information.............................................. 88 5.6 SignalInterface...................................... 21 8.1 PackagingInformation .............................. 88 Copyright©2006–2015,TexasInstrumentsIncorporated TableofContents 3 SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 SWRS046H–NOVEMBER2006–REVISEDMARCH2015 www.ti.com 2 Revision History This data manual revision history highlights the changes made to the SWRS046F device-specific data manualtomakeitanSWRS046Grevision. ChangesfromRevisionF(January2006)toRevisionG Page • ConverteddocumenttonewTIstandards......................................................................................... 1 • AddedThermalResistanceCharacteristicsforVQFNPPackage............................................................ 16 • ChangedRegistertableformattonewTIstandards........................................................................... 62 ChangesfromJanuary19,2015toFebruary19,2015 Page • UpdatedRUZpackagetoRSS.................................................................................................... 87 4 RevisionHistory Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 www.ti.com SWRS046H–NOVEMBER2006–REVISEDMARCH2015 3 Terminal Configuration and Functions 3.1 Pin Diagram Figure3-1showspinnamesandlocationsfortheCC1020device. TheCC1020comesinaQFN32-typepackage. C H A PSEL DVDD DGND AVDD P_OUT AVDD D_REF AGND 3231302928272625 PCLK 1 24VC PDI 2 23 AVDD PDO 3 22 AVDD DGND 4 21 RF_OUT DVDD 5 20AVDD DGND 6 19 RF_IN DCLK 7 18AVDD DIO 8 17 R_BIAS 9 10 11 12 13 14 15 16 LO XO XO AV AV LN PA AV AEGxpNoDsed die CK SC_Q SC_Q DD DD A_EN _EN DD attached pad 1 2 Figure3-1.Package7-mm ×7-mmVQFNP(TopView) 3.2 Pin Configuration Table3-1providesanoverviewoftheCC1020pinout. Table3-1.PinAttributes(1)(2) PINNO. PINNAME TYPE DESCRIPTION Exposeddieattachedpad.Mustbesolderedtoasolidgroundplaneas — AGND Ground(analog) thisisthegroundconnectionforallanalogmodules.SeeSection6.3for moredetails. 1 PCLK Digitalinput ProgrammingclockforSPIconfigurationinterface 2 PDI Digitalinput ProgrammingdatainputforSPIconfigurationinterface 3 PDO Digitaloutput ProgrammingdataoutputforSPIconfigurationinterface 4 DGND Ground(digital) Groundconnection(0V)fordigitalmodulesanddigitalI/O 5 DVDD Power(digital) Powersupply(3Vtypical)fordigitalmodulesanddigitalI/O 6 DGND Ground(digital) Groundconnection(0V)fordigitalmodules(substrate) Clockfordatainbothreceiveandtransmitmode. 7 DCLK Digitaloutput Canbeusedasreceivedataoutputinasynchronousmode Datainputintransmitmode;dataoutputinreceivemode. 8 DIO Digitalinput/output Canalsobeusedtostartpower-upsequencinginreceive PLLLockindicator,activelow.Outputisasserted(low)whenPLLisin 9 LOCK Digitaloutput lock.Thepincanalsobeusedasageneraldigitaloutput,orasreceive dataoutputinsynchronousNRZ/Manchestermode 10 XOSC_Q1 Analoginput Crystaloscillatororexternalclockinput 11 XOSC_Q2 Analogoutput Crystaloscillator 12 AVDD Power(analog) Powersupply(3Vtypical)forcrystaloscillator 13 AVDD Power(analog) Powersupply(3Vtypical)fortheIFVGA Generaldigitaloutput.CanbeusedforcontrollinganexternalLNAif 14 LNA_EN Digitaloutput highersensitivityisneeded. (1) DCLK,DIOandLOCKarehigh-impedance(3-state)inpowerdown(BIAS_PD=1intheMAINregister). (2) Theexposeddieattachedpadmustbesolderedtoasolidgroundplaneasthisisthemaingroundconnectionforthechip. Copyright©2006–2015,TexasInstrumentsIncorporated TerminalConfigurationandFunctions 5 SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 SWRS046H–NOVEMBER2006–REVISEDMARCH2015 www.ti.com Table3-1.PinAttributes(1)(2) (continued) PINNO. PINNAME TYPE DESCRIPTION Generaldigitaloutput.CanbeusedforcontrollinganexternalPAifhigher 15 PA_EN Digitaloutput outputpowerisneeded. 16 AVDD Power(analog) Powersupply(3Vtypical)forglobalbiasgeneratorandIFanti-aliasfilter 17 R_BIAS Analogoutput Connectionforexternalprecisionbiasresistor(82kΩ,±1%) 18 AVDD Power(analog) Powersupply(3Vtypical)forLNAinputstage 19 RF_IN RFInput RFsignalinputfromantenna(externalAC-coupling) 20 AVDD Power(analog) Powersupply(3Vtypical)forLNA 21 RF_OUT RFoutput RFsignaloutputtoantenna Powersupply(3Vtypical)forLObuffers,mixers,prescaler,andfirstPA 22 AVDD Power(analog) stage 23 AVDD Power(analog) Powersupply(3Vtypical)forVCO 24 VC Analoginput VCOcontrolvoltageinputfromexternalloopfilter 25 AGND Ground(analog) Groundconnection(0V)foranalogmodules(guard) 26 AD_REF Power(analog) 3VreferenceinputforADC 27 AVDD Power(analog) Powersupply(3Vtypical)forchargepumpandphasedetector 28 CHP_OUT Analogoutput PLLchargepumpoutputtoexternalloopfilter 29 AVDD Power(analog) Powersupply(3Vtypical)forADC 30 DGND Ground(digital) Groundconnection(0V)fordigitalmodules(guard) 31 DVDD Power(digital) Powersupplyconnection(3Vtypical)fordigitalmodules Programmingchipselect,activelow,forconfigurationinterface.Internal 32 PSEL Digitalinput pullupresistor. 6 TerminalConfigurationandFunctions Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 www.ti.com SWRS046H–NOVEMBER2006–REVISEDMARCH2015 4 Specifications 4.1 Absolute Maximum Ratings(1) PARAMETER MIN MAX UNIT CONDITION Allsupplypinsmusthavethesame Supplyvoltage,VDD –0.3 5.0 V voltage VDD+0.3, Voltageonanypin –0.3 V max5.0 InputRFlevel 10 dBm Packagebodytemperature 260 °C Norm:IPC/JEDECJ-STD-020(2) Humiditynon-condensing 5% 85% Storagetemperaturerange,T –50 150 °C stg (1) Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedundergeneralcharacteristicsisnot implied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) Thereflowpeaksolderingtemperature(bodytemperature)isspecifiedaccordingtoIPC/JEDECJ-STD_020“Moisture/ReflowSensitivity ClassificationforNonhermeticSolidStateSurfaceMountDevices”. 4.2 ESD Ratings VALUE UNIT HumanBodyModel(HBM),per AllpadsexceptRF ±1 kV V Electrostaticdischarge(ESD) ANSI/ESDA/JEDECJS001(1)(2) RFPads ±0.4 kV ESD performance: Charged-deviceModel(CDM) 250 V (1) JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess.Manufacturingwith lessthan500-VHBMispossiblewiththenecessaryprecautions. (2) AccordingtoJEDECSTD22,methodA114,HumanBodyModel 4.3 Recommended Operating Conditions overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN TYP MAX UNIT CONDITION 402 470 MHz Programmablein<300Hzsteps RFFrequencyRange 804 960 MHz Programmablein<600Hzsteps Operatingambienttemperaturerange –40 85 °C Thesamesupplyvoltageshouldbeusedfordigital (DVDD)andanalog(AVDD)power. Supplyvoltage 2.3 3.0 3.6 V A3.0±0.1Vsupplyisrecommendedtomeetthe ARIBSTD-T67selectivityandoutputpowertolerance requirements. Copyright©2006–2015,TexasInstrumentsIncorporated Specifications 7 SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 SWRS046H–NOVEMBER2006–REVISEDMARCH2015 www.ti.com 4.4 RF Transmit Allmeasurementswereperformedusingthetwo-layerPCBCC1020EMXreferencedesign.SeeFigure6-1.Theelectrical specificationsgivenfor868MHzarealsoapplicablefor902to928MHz.T =25°C,AVDD=DVDD=3.0V, A f =14.7456MHzifnothingelsestated. C PARAMETER MIN TYP MAX UNIT CONDITION Thedatarateisprogrammable.See Section5.7fordetails. NRZorManchesterencodingcanbe used.153.6kBaudequals153.6kbps Transmitdatarate 0.45 153.6 kBaud usingNRZcodingand76.8kbpsusing Manchestercoding.SeeSection5.4.2 fordetails. MinimumdatarateforOOKis2.4kBaud in402to470MHzrange 0 108 kHz 108/216kHzisthemaximumspecified BinaryFSK separationat1.84MHzreference frequency frequency.Largerseparationscanbe separation in804to960MHzrange 0 216 kHz achievedathigherreference frequencies. 433MHz –20to+10 dBm Deliveredto50Ωsingle-endedload.The outputpowerisprogrammableand shouldnotbeprogrammedtoexceed Outputpower +10/+5dBmat433/868MHzunderany 868MHz –20to+5 dBm operatingconditions(refertoCC1020 ErrataNote003intheCC1020product folder).SeeSection5.11fordetails. Outputpower At2.3V,+85°C –4 dB Atmaximumoutputpower tolerance At3.6V,–40°C 3 dB 2ndharmonic,433MHz, –50 dBc +10dBm 3rdharmonic,433MHz, HarmonicsaremeasuredasEIRP Harmonics, +10dBm –50 dBc valuesaccordingtoEN300220.The antenna(SMAFF-433andSMAFF-868 radiatedCW 2ndharmonic,868MHz, –50 dBc fromR.W.Badland)playsapartin +5dBm attenuatingtheharmonics. 3rdharmonic,868MHz, –50 dBc +5dBm 12.5kHzchannelspacing, For12.5kHzchannelspacingACPis –46 dBc 433MHz measuredina±4.25kHzbandwidthat ±12.5kHzoffset.Modulation:2.4kBaud 25kHzchannelspacing, –52 dBc NRZPN9sequence,±2.025kHz 433MHz Adjacentchannel frequencydeviation. power(GFSK) For25kHzchannelspacingACPis measuredina±8.5kHzbandwidthat 25kHzchannelspacing, –49 dBc ±25kHzoffset.Modulation:4.8kBaud 868MHz NRZPN9sequence,±2.475kHz frequencydeviation. 12.5kHzchannelspacing, Bandwidthfor99.5%oftotalaverage 7.5 kHz 433MHz power. Modulationfor12.5channelspacing: Occupied 25kHzchannelspacing, 9.6 kHz 2.4kBaudNRZPN9sequence, bandwidth 433MHz ±2.025kHzfrequencydeviation. (99.5%,GFSK) Modulationfor25kHzchannelspacing: 25kHzchannelspacing, 9.6 kHz 4.8kBaudNRZPN9sequence, 868MHz ±2.475kHzfrequencydeviation. Modulation 1fr9e.q2ukeBncayudd,e±v9ia.9tioknHz 48 kHz Bmaondduwlaidtiothnwehqeuraelsth–e36podwBemr.eSnpveeclotrpuemof bandwidth, 868MHz 3fr8e.q4ukeBncayudd,e±v1ia9t.io8nkHz 106 kHz aRnBaWlyz=er1kHz. 8 Specifications Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 www.ti.com SWRS046H–NOVEMBER2006–REVISEDMARCH2015 RF Transmit (continued) Allmeasurementswereperformedusingthetwo-layerPCBCC1020EMXreferencedesign.SeeFigure6-1.Theelectrical specificationsgivenfor868MHzarealsoapplicablefor902to928MHz.T =25°C,AVDD=DVDD=3.0V, A f =14.7456MHzifnothingelsestated. C PARAMETER MIN TYP MAX UNIT CONDITION 47to74,87.5to118,174to Atmaximumoutputpower,+10/+5dBm –54 dBm 230,470to862MHz at433/868MHz. TocomplywithEN300220,FCC 9kHzto1GHz –36 dBm CFR47part15andARIBSTD-T96an external(antenna)filter,asimplemented intheapplicationcircuitinSection5.11, mustbeusedandtailoredtoeach individualdesigntoreduceout-of-band spuriousemissionlevels. Spuriousemissionscanbemeasuredas EIRPvaluesaccordingtoEN300220. Theantenna(SMAFF-433andSMAFF- Spuriousemission, 868fromR.W.Badland)playsapartin radiatedCW attenuatingthespuriousemissions. 1to4GHz –30 dBm Iftheoutputpowerisincreasedusingan externalPA,afiltermustbeusedto attenuatespursbelow862MHzwhen operatinginthe868MHzfrequency bandinEurope.ApplicationNoteAN036 CC1020/1021ReducingSpurious Emission(SWRA057)presentsand discussesasolutionthatreducestheTX modespuriousemissioncloseto862 MHzbyincreasingtheREF_DIVfrom1 to7. 433MHz 54+j44 Ω Optimumload Transmitmode.Formatchingdetailssee 868MHz 15+j24 Ω impedance Section5.11. 915MHz 20+j35 Ω 4.5 RF Receive Allmeasurementswereperformedusingthetwo-layerPCBCC1020EMXreferencedesign.SeeFigure6-1.Theelectrical specificationsgivenfor868MHzarealsoapplicablefor902to928MHz.T =25°C,AVDD=DVDD=3.0V, A f =14.7456MHzifnothingelsestated. C PARAMETER MIN TYP MAX UNIT CONDITION 12.5kHzchannelspacing,optimized SensitivityismeasuredwithPN9 selectivity,±2.025kHzfreq.deviation –114 dBm sequenceatBER=10−3 12.5kHzchannelspacing: Receiversensitivity, 12.5kHzchannelspacing,optimized –118 dBm 2.4kBaud,Manchestercodeddata. 433MHz,FSK sensitivity,±2.025kHzfreq.deviation 25kHzchannelspacing: 25kHzchannelspacing –112 dBm 4.8kBaud,NRZcodeddata,±2.475 kHzfrequencydeviation. 500kHzchannelspacing –96 dBm 500kHzchannelspacing: 12.5kHzchannelspacing,±2.475kHz 153.6kBaud,NRZcodeddata,±72 –116 dBm freq.deviation kHzfrequencydeviation. Receiversensitivity, 868MHz,FSK 25kHzchannelspacing –111 dBm SeeTable5-6andTable5-7for typicalsensitivityfiguresatother 500kHzchannelspacing –94 dBm datarates. Receiversensitivity, 2.4kBaud –116 dBm SensitivityismeasuredwithPN9 433MHz,OOK 153.6kBaud –81 dBm sequenceatBER=10−3 Manchestercodeddata. Receiversensitivity, 4.8kBaud –107 dBm SeeTable5-14fortypicalsensitivity 868MHz,OOK 153.6kBaud –87 dBm figuresatotherdatarates. Saturation FSK:Manchester/NRZcodeddata (maximuminput FSKandOOK 10 dBm OOK:Manchestercodeddata level) BER=10−3 Thereceiverchannelfilter6dB Systemnoise bandwidthisprogrammablefrom 9.6to307.2 kHz bandwidth 9.6kHzto307.2kHz.See Section5.9.2. Copyright©2006–2015,TexasInstrumentsIncorporated Specifications 9 SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 SWRS046H–NOVEMBER2006–REVISEDMARCH2015 www.ti.com RF Receive (continued) Allmeasurementswereperformedusingthetwo-layerPCBCC1020EMXreferencedesign.SeeFigure6-1.Theelectrical specificationsgivenfor868MHzarealsoapplicablefor902to928MHz.T =25°C,AVDD=DVDD=3.0V, A f =14.7456MHzifnothingelsestated. C PARAMETER MIN TYP MAX UNIT CONDITION Noisefigure, 433and868MHz 7 dB NRZcodeddata cascaded –23 dBm LNA2maximumgain 433MHz,102.4kHz –18 dBm LNA2mediumgain channelfilterBW –16 dBm LNA2minimumgain InputIP3(1) –18 dBm LNA2maximumgain 868MHz,102.4kHz –15 dBm LNA2mediumgain channelfilterBW –13 dBm LNA2minimumgain 12.5kHzchannelspacing,433MHz –11 dB Wantedsignal3dBabovethe Co-channel sensitivitylevel,FMjammer(1kHz rejection,FSKand 25kHzchannelspacing,433MHz –11 dB sine,±2.5kHzdeviation)at OOK 25kHzchannelspacing,868MHz –11 dB operatingfrequency,BER=10–3. 12.5kHzchannelspacing,433MHz 32 dB Wantedsignal3dBabovethe sensitivitylevel,FMjammer(1kHz Adjacentchannel 25kHzchannelspacing,433MHz 37 dB sine,±2.5kHzdeviation)atadjacent rejection(ACR) channel.BER=10–3. 25kHzchannelspacing,868MHz 32 dB NoI/Qgainand Wantedsignal3dBabovethe 26/31 dB phasecalibration sensitivitylevel,CWjammerat Imagechannel imagefrequency,BER=10−3. 433/868MHz rejection I/Qgainandphase Imagerejectionaftercalibrationwill calibrated 49/52 dB dependontemperatureandsupply voltage.RefertoSection5.9.6. 12.5kHzchannelspacing,433MHz 41 dB Wantedsignal3dBabovethe sensitivitylevel.CWjammeris 25kHzchannelspacing,433MHz 41 dB Selectivity(2) sweptin12.5kHz/25kHzstepsto within±1MHzfromwantedchannel. 25kHzchannelspacing,868MHz 39 dB BER=10–3.Adjacentchanneland imagechannelareexcluded. ±1MHz 50/57 dB Wantedsignal3dBabovethe sensitivitylevel,CWjammerat±1, ±2MHz 64/71 dB 2,5and10MHzoffset.BER=10–3. Blocking/ Desensitization(3) 433/868MHz ±5MHz 64/71 dB 12.5kHz/25kHzchannelspacingat 433/868MHz. ±10MHz 75/78 dB ComplyingwithEN300220,class2 receiverrequirements. NoI/Qgainand Ratiobetweensensitivityfora 36/41 dB phasecalibration signalattheimagefrequencytothe sensitivityinthewantedchannel. Imagefrequency ImagefrequencyisRF-2IF.The 433/868MHz suppression I/Qgainandphase signalsourceisa2.4kBaud, calibrated 59/62 dB Manchestercodeddata,±2.025kHz frequencydeviation,signallevelfor BER=10–3. Ratiobetweensensitivityforan unwantedfrequencytothe sensitivityinthewantedchannel. Spuriousrejection 40 dB Thesignalsourceissweptoverall frequencies100MHzto2GHz. SignallevelforBER=10−3. 102.4kHzchannelfilterbandwidth. (1) Twotonetest(+10MHzand+20MHz) (2) Close-inspuriousresponserejection. (3) Out-of-bandspuriousresponserejection. 10 Specifications Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 www.ti.com SWRS046H–NOVEMBER2006–REVISEDMARCH2015 RF Receive (continued) Allmeasurementswereperformedusingthetwo-layerPCBCC1020EMXreferencedesign.SeeFigure6-1.Theelectrical specificationsgivenfor868MHzarealsoapplicablefor902to928MHz.T =25°C,AVDD=DVDD=3.0V, A f =14.7456MHzifnothingelsestated. C PARAMETER MIN TYP MAX UNIT CONDITION 12.5kHzchannelspacing,433MHz 30 dB Wantedsignal3dBabovethe sensitivitylevel,twoCWjammersat Intermodulation +2Chand+4ChwhereChis rejection(1) 25kHzchannelspacing,868MHz 30 dB channelspacing12.5kHzor 25kHz.BER=10–2. 12.5kHzchannelspacing,433MHz 56 dB Wantedsignal3dBabovethe Intermodulation sensitivitylevel,twoCWjammersat rejection(2) 25kHzchannelspacing,868MHz 55 dB +10MHzand+20MHzoffset. BER=10–2. LOleakage 433/868MHz <–80/–66 dBm VCOfrequencyresidesbetween VCOleakage –64 dBm 1608and1880MHz. 9kHzto1GHz <–60 dBm ComplyingwithEN300220,FCC CFR47part15andARIBSTD-T96. Spuriousemission, Spuriousemissionscanbe radiatedCW 1to4GHz <–60 dBm measuredasEIRPvalues accordingtoEN300220. 433MHz 58–j10 Ω Receivemode.SeeSection5.11for Inputimpedance 868MHz 54–j22 Ω details. 433MHz –14 dB Usingapplicationcircuitmatching Matchedinput network.SeeSection5.11for impedance,S11 868MHz –12 dB details. 433MHz 39–j14 Ω Usingapplicationcircuitmatching Matchedinput network.SeeSection5.11for impedance 868MHz 32–j10 Ω details. Themaximumbitrateoffset toleratedbythebitsynchronization Bitsynchronizationoffset 8000 ppm circuitfor6dBdegradation (synchronousmodesonly). NRZmode 4 Baud Timefromclockingthedataonthe Datalatency transmitterDIOpinuntildatais Manchestermode 8 Baud availableonreceiverDIOpin. Copyright©2006–2015,TexasInstrumentsIncorporated Specifications 11 SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 SWRS046H–NOVEMBER2006–REVISEDMARCH2015 www.ti.com 4.6 RSSI / Carrier Sense Allmeasurementswereperformedusingthetwo-layerPCBCC1020EMXreferencedesign.SeeFigure6-1.Theelectrical specificationsgivenfor868MHzarealsoapplicablefor902to928MHz.T =25°C,AVDD=DVDD=3.0V, A f =14.7456MHzifnothingelsestated. C PARAMETER TYP UNIT CONDITION RSSIdynamicrange 55 dB 12.5and25kHzchannelspacing RSSIaccuracy ±3 dB SeeSection5.9.5fordetails. RSSIlinearity ±1 dB 2.4kBaud,12.5kHzchannelspacing 3.8 ms ShorterRSSIattachtimescanbetradedfor lowerRSSIaccuracy.SeeSection5.9.5for 4.8kBaud,25kHzchannelspacing 1.9 ms details. RSSIattachtime ShorterRSSIattachtimescanalsobetraded forreducedsensitivityandselectivityby 153.6kBaud,500kHzchannelspacing 140 µs increasingthereceiverchannelfilter bandwidth. Carriersenseprogrammablerange 40 dB AccuracyisasforRSSI 12.5kHzchannelspacing –72 dBm Atcarriersenselevel–110dBm,FMjammer (1kHzsine,±2.5kHzdeviation)atadjacent channel. Adjacentchannelcarrier Adjacentchannelcarriersenseismeasured sense 25kHzchannelspacing –72 dBm byapplyingasignalontheadjacentchannel andobserveatwhichlevelcarriersenseis indicated. Atcarriersenselevel–110dBm,100MHzto Spuriouscarriersense –70 dBm 2GHz.Adjacentchannelandimagechannel areexcluded. 4.7 Intermediate Frequency (IF) Allmeasurementswereperformedusingthetwo-layerPCBCC1020EMXreferencedesign.SeeFigure6-1.Theelectrical specificationsgivenfor868MHzarealsoapplicablefor902to928MHz.T =25°C,AVDD=DVDD=3.0V, A f =14.7456MHzifnothingelsestated. C PARAMETER TYP UNIT CONDITION Intermediatefrequency(IF) 307.2 kHz SeeSection5.9.1fordetails. Thechannelfilter6dBbandwidthis Digitalchannelfilterbandwidth 9.6to307.2 kHz programmablefrom9.6kHzto307.2kHz.See Section5.9.2fordetails. At2.4kBaud AFCresolution 150 Hz GivenasBaudrate/16.SeeSection5.9.3for details. 12 Specifications Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 www.ti.com SWRS046H–NOVEMBER2006–REVISEDMARCH2015 4.8 Crystal Oscillator Allmeasurementswereperformedusingthetwo-layerPCBCC1020EMXreferencedesign.SeeFigure6-1.Theelectrical specificationsgivenfor868MHzarealsoapplicablefor902to928MHz.T =25°C,AVDD=DVDD=3.0V, A f =14.7456MHzifnothingelsestated. C PARAMETER MIN TYP MAX UNIT CONDITION Recommendedfrequencyis CrystalOscillatorFrequency 4.9152 14.7456 19.6608 MHz 14.7456MHz.SeeSection5.16for details. ±5.7 ppm 433MHz(EN300220) 868MHz(EN300220) Mustbelessthan±5.7/±2.8ppmto ±2.8 ppm Referencefrequency complywithEN30022025kHzchannel accuracyrequirement(1)(2) spacingat433/868MHz. Mustbelessthan±4ppmtocomplywith ±4 ppm Japanese12.5kHzchannelspacing regulations(ARIBSTD-T67). C4andC5areloadingcapacitors.See Crystaloperation Parallel Section5.16fordetails. 4.9to6MHz,22pF 12 22 30 pF recommended Crystalload 6to8MHz,16pF 12 16 30 pF capacitance recommended 8to19.6MHz,16pF 12 16 16 pF recommended 4.9152MHz,12pFload 1.55 ms 7.3728MHz,12pFload 1.0 ms Crystaloscillator 9.8304MHz,12pFload 0.90 ms start-uptime 14.7456MHz,16pFload 0.95 ms 17.2032MHz,12pFload 0.60 ms 19.6608MHz,12pFload 0.63 ms Theexternalclocksignalmustbe connectedtoXOSC_Q1usingaDC block(10nF).SetXOSC_BYPASS=0in Externalclocksignaldrive,sinewave 300 mVpp theINTERFACEregisterwhenusingan externalclocksignalwithlowamplitude oracrystal. Theexternalclocksignalmustbe connectedtoXOSC_Q1.NoDCblock Externalclocksignaldrive,full-swingdigital 0–VDD V shallbeused.SetXOSC_BYPASS=1in externalclock theINTERFACEregisterwhenusinga full-swingdigitalexternalclock. (1) Thereferencefrequencyaccuracy(initialtolerance)anddrift(agingandtemperaturedependency)willdeterminethefrequency accuracyofthetransmittedsignal. (2) CrystaloscillatortemperaturecompensationcanbedoneusingthefinestepPLLfrequencyprogrammabilityandtheAFCfeature.See Section5.9.13fordetails. Copyright©2006–2015,TexasInstrumentsIncorporated Specifications 13 SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 SWRS046H–NOVEMBER2006–REVISEDMARCH2015 www.ti.com 4.9 Frequency Synthesizer Allmeasurementswereperformedusingthetwo-layerPCBCC1020EMXreferencedesign.SeeFigure6-1.Theelectrical specificationsgivenfor868MHzarealsoapplicablefor902to928MHz.T =25°C,AVDD=DVDD=3.0V, A f =14.7456MHzifnothingelsestated. C PARAMETER TYP UNIT CONDITION At12.5kHzoffsetfromcarrier –90 dBc/Hz Unmodulatedcarrier. At25kHzoffsetfromcarrier –100 dBc/Hz Phasenoise, Measuredusingloopfiltercomponents 402to470MHz At50kHzoffsetfromcarrier –105 dBc/Hz giveninTable6-2.Thephasenoisewill 12.5kHzchannelspacing behigherforlargerPLLloopfilter At100kHzoffsetfromcarrier –110 dBc/Hz bandwidth. At1MHzoffsetfromcarrier –114 dBc/Hz At12.5kHzoffsetfromcarrier –85 dBc/Hz Unmodulatedcarrier. At25kHzoffsetfromcarrier –95 dBc/Hz Phasenoise, Measuredusingloopfiltercomponents 804to960MHz At50kHzoffsetfromcarrier –101 dBc/Hz giveninTable6-2.Thephasenoisewill 25kHzchannelspacing behigherforlargerPLLloopfilter At100kHzoffsetfromcarrier –109 dBc/Hz bandwidth. At1MHzoffsetfromcarrier –118 dBc/Hz 12.5kHzchannelspacing,433MHz 2.7 kHz AfterPLLandVCOcalibration.ThePLL PLLloopbandwidth 25kHzchannelspacing,868MHz 8.3 kHz loopbandwidthisprogrammable. 12.5kHzchannelspacing,433MHz 900 µs 307.2kHzfrequencysteptoRFfrequency within±10%ofchannelspacing.Depends PLLlocktime 25kHzchannelspacing,868MHz 640 µs onloopfiltercomponentvaluesand (RX/TXturntime) PLL_BWregistersetting.SeeTable5-13 500kHzchannelspacing 14 µs formoredetails. 12.5kHzchannelspacing,433MHz 3.2 ms TimefromwritingtoregisterstoRF PLLturn-ontime. frequencywithin±10%ofchannel Frompowerdownmode 25kHzchannelspacing,868MHz 2.5 ms spacing.Dependsonloopfilter withcrystaloscillator componentvaluesandPLL_BWregister running. 500kHzchannelspacing 700 µs setting.SeeTable5-12formoredetails. 14 Specifications Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 www.ti.com SWRS046H–NOVEMBER2006–REVISEDMARCH2015 4.10 Digital Inputs and Outputs Allmeasurementswereperformedusingthetwo-layerPCBCC1020EMXreferencedesign.SeeFigure6-1.Theelectrical specificationsgivenfor868MHzarealsoapplicablefor902to928MHz.T =25°C,AVDD=DVDD=3.0V, A f =14.7456MHzifnothingelsestated. C PARAMETER MIN TYP MAX UNIT CONDITION Logic"0"inputvoltage 0 0.3×VDD V Logic"1"inputvoltage 0.7×VDD VDD V Outputcurrent–2.0mA, Logic"0"outputvoltage 0 0.4 V 3.0-Vsupplyvoltage Outputcurrent2.0mA, Logic"1"outputvoltage 2.5 VDD V 3.0-Vsupplyvoltage InputsignalequalsGND. PSELhasaninternalpullup Logic“0”inputcurrent N/A –1 µA resistorandduring configurationthecurrentwill be–350µA. Logic“1”inputcurrent N/A 1 µA InputsignalequalsVDD TXmode,minimumtimeDIO mustbereadybeforethe DIOsetuptime 20 ns positiveedgeofDCLK.Data shouldbesetuponthe negativeedgeofDCLK. TXmode,minimumtimeDIO mustbeheldafterthe DIOholdtime 10 ns positiveedgeofDCLK.Data shouldbesetuponthe negativeedgeofDCLK. Serialinterface(PCLK,PDI,PDOandPSEL)timing SeeTable5-1formore specification details 0VonLNA_EN,PA_EN 0.90 mA pins 0.5VonLNA_EN, 0.87 mA PA_ENpins Sourcecurrent 1.0VonLNA_EN, 0.81 mA PA_ENpins 1.5VonLNA_EN, Pindrive, PA_ENpins 0.69 mA SeeFigure5-32formore LNA_EN, PA_EN 3.0VonLNA_EN, 0.93 mA details. PA_ENpins 2.5VonLNA_EN, 0.92 mA PA_ENpins Sinkcurrent 2.0VonLNA_EN, 0.89 mA PA_ENpins 1.5VonLNA_EN, 0.79 mA PA_ENpins Copyright©2006–2015,TexasInstrumentsIncorporated Specifications 15 SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 SWRS046H–NOVEMBER2006–REVISEDMARCH2015 www.ti.com 4.11 Current Consumption Allmeasurementswereperformedusingthetwo-layerPCBCC1020EMXreferencedesign.SeeFigure6-1.Theelectrical specificationsgivenfor868MHzarealsoapplicablefor902to928MHz.T =25°C,AVDD=DVDD=3.0V, A f =14.7456MHzifnothingelsestated. C PARAMETER MIN TYP MAX UNIT CONDITION PowerDownmode 0.2 1.8 µA Oscillatorcoreoff CurrentConsumption, 19.9 mA receivemode433and868MHz P=–20dBm 12.3/14.5 mA P=–5dBm 14.4/17.0 mA Theoutputpoweris deliveredtoa50Ωsingle- CurrentConsumption, P=0dBm 16.2/20.5 mA endedload. transmitmode433/868MHz: P=+5dBm 20.5/25.1 mA SeeSection5.10.2formore details. P=+10dBm 27.1 mA (433MHzonly) 14.7456MHz,16pFload CurrentConsumption,crystaloscillator 77 µA crystal 14.7456MHz,16pFload CurrentConsumption,crystaloscillatorandbias 500 µA crystal 14.7456MHz,16pFload CurrentConsumption,crystaloscillator,biasandsynthesizer 7.5 mA crystal 4.12 Thermal Resistance Characteristics for VQFNP Package NAME DESCRIPTION °C/W(1) (2) R Junction-to-case(top) 16.2 θJC(top) R Junction-to-board 6.9 θJB R Junction-to-freeair 30.7 θJA Psi Junction-to-packagetop 0.2 JT Psi Junction-to-board 6.9 JB R Junction-to-case(bottom) 1.0 θJC(bottom) (1) °C/W=degreesCelsiusperwatt. (2) ThesevaluesarebasedonaJEDEC-defined2S2Psystem(withtheexceptionoftheThetaJC[Rθ ]value,whichisbasedona JC JEDEC-defined1S0Psystem)andwillchangebasedonenvironmentaswellasapplication.Formoreinformation,seethese EIA/JEDECstandards: • JESD51-2,IntegratedCircuitsThermalTestMethodEnvironmentalConditions-NaturalConvection(StillAir) • JESD51-3,LowEffectiveThermalConductivityTestBoardforLeadedSurfaceMountPackages • JESD51-7,HighEffectiveThermalConductivityTestBoardforLeadedSurfaceMountPackages • JESD51-9,TestBoardsforAreaArraySurfaceMountPackageThermalMeasurements Powerdissipationof2Wandanambienttemperatureof70ºCisassumed. 16 Specifications Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 www.ti.com SWRS046H–NOVEMBER2006–REVISEDMARCH2015 5 Detailed Description 5.1 Overview AsimplifiedblockdiagramofCC1020isshowninFigure5-1.Onlysignalpinsareshown. CC1020 features a low-IF receiver. The received RF signal is amplified by the low-noise amplifier (LNA and LNA2) and down-converted in quadrature (I and Q) to the intermediate frequency (IF). At IF, the I/Q signal is complex filtered and amplified, and then digitized by the ADCs. Automatic gain control, fine channel filtering, demodulation and bit synchronization is performed digitally. CC1020 outputs the digital demodulated data on the DIO pin. A synchronized data clock is available at the DCLK pin. RSSI is availableindigitalformatandcanbereadviatheserialinterface.TheRSSIalsofeaturesaprogrammable carriersenseindicator. In transmit mode, the synthesized RF frequency is fed directly to the power amplifier (PA). The RF output is frequency shift keyed (FSK) by the digital bit stream that is fed to the DIO pin. Optionally, a Gaussian filtercanbeusedtoobtainGaussianFSK(GFSK). The frequency synthesizer includes a completely on-chip LC VCO and a 90 degrees phase splitter for generating the LO_I and LO_Q signals to the down-conversion mixers in receive mode. The VCO operates in the frequency range 1.608 to 1.880 GHz. The CHP_OUT pin is the charge pump output and VC is the control node of the on-chip VCO. The external loop filter is placed between these pins. A crystal istobeconnectedbetweenXOSC_Q1andXOSC_Q2.AlocksignalisavailablefromthePLL. The4-wireSPIserialinterfaceisusedforconfiguration. 5.2 Functional Block Diagram ADC DIGITAL DEMODULATOR -DigitalRSSI RF_IN LNA LNA2 -GainControl -ImageSuppression -ChannelFiltering ADC -Demodulation 0 er :2 x 90 e Multipl 900 :2 SFYRNETQH NTROLOGIC INDTTIEGORITFmACALCE PDO OL PDI C PCLK Power PSEL Control DIGITAL Multiplexer MODULATOR -Modulation RF_OUT PA -Datashaping BIAS XOSC -PowerControl PA_EN LNA_EN R_BIAS XOSC_Q1 XOSC_Q2 VC CHP_OUT Figure5-1.CC1020SimplifiedBlockDiagram Copyright©2006–2015,TexasInstrumentsIncorporated DetailedDescription 17 SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 SWRS046H–NOVEMBER2006–REVISEDMARCH2015 www.ti.com 5.3 Configuration Overview CC1020 can be configured to achieve optimum performance for different applications. Through the programmableconfigurationregistersthefollowingkeyparameterscanbeprogrammed: • Receiveandtransmitmode • RFoutputpower • Frequencysynthesizerkeyparameters: – RFoutputfrequency – FSKfrequencyseparation – Crystaloscillatorreferencefrequency • Power-downandpower-upmode • Power-downandpower-upmode • Datarateanddataformat(NRZ,ManchestercodedorUARTinterface) • Synthesizerlockindicatormode • DigitalRSSIandcarriersense • FSK,GFSK,andOOKmodulation 5.3.1 Configuration Software TI provides users of CC1020 with a software program, SmartRF Studio (Windows interface) that generates all necessary CC1020 configuration data based on the user’s selections of various parameters. These hexadecimal numbers will then be the necessary input to the microcontroller for the configuration of CC1020. In addition, the program will provide the user with the component values needed for the input/outputmatchingcircuit,thePLLloopfilterandtheLCfilter. Figure5-2showstheuserinterfaceoftheCC1020configurationsoftware. Figure5-2. SmartRF™Studiouserinterface 18 DetailedDescription Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 www.ti.com SWRS046H–NOVEMBER2006–REVISEDMARCH2015 5.4 Microcontroller Interface Usedinatypicalsystem,CC1020willinterfacetoamicrocontroller.Thismicrocontrollermustbeableto: • Program CC1020 into different modes via the 4-wire serial configuration interface (PDI, PDO, PCLK andPSEL). • Interfacetothebi-directionalsynchronousdatasignalinterface(DIOandDCLK). • Optionally,themicrocontrollercandodataencodinganddecoding. • Optionally, the microcontroller can monitor the LOCK pin for frequency lock status, carrier sense status orotherstatusinformation. • Optionally,themicrocontrollercanreadbackthedigitalRSSIvalueandotherstatusinformationviathe 4-wireserialinterface. 5.4.1 Configuration Interface The microcontroller interface is shown in Figure 5-3. The microcontroller uses 3 or 4 I/O pins for the configuration interface (PDI, PDO, PCLK and PSEL). PDO should be connected to a microcontroller input. PDI, PCLK and PSEL must be microcontroller outputs. One I/O pin can be saved if PDI and PDO are connectedtogetherandabi-directionalpinisusedatthemicrocontroller. The microcontroller pins connected to PDI, PDO and PCLK can be used for other purposes when the configuration interface is not used. PDI, PDO and PCLK are high impedance inputs as long as PSEL is notactivated(activelow). PSEL has an internal pullup resistor and should be left open (tri-stated by the microcontroller) or set to a highlevelduringpowerdownmodeinordertopreventatricklecurrentflowinginthepullup. 5.4.2 Signal Interface A bi-directional pin is usually used for data (DIO) to be transmitted and data received. DCLK providing the datatimingshould As an option, the data output in receive mode can be made available on a separate pin. See Section 5.6 forfurtherdetails. 5.4.3 PLL Lock Signal Optionally, one microcontroller pin can be used to monitor the LOCK signal. This signal is at low logic level when the PLL is in lock. It can also be used for carrier sense and to monitor other internal test signals. Figure5-3.MicrocontrollerInterface Copyright©2006–2015,TexasInstrumentsIncorporated DetailedDescription 19 SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 SWRS046H–NOVEMBER2006–REVISEDMARCH2015 www.ti.com 5.5 4-wire Serial Configuration Interface CC1020 is configured via a simple 4-wire SPI-compatible interface (PDI, PDO, PCLK and PSEL) where CC1020 is the slave. There are 8-bit configuration registers, each addressed by a 7-bit address. A Read/Write bit initiates a read or write operation. A full configuration of CC1020 requires sending 33 data frames of 16 bits each (7 address bits, R/W bit and 8 data bits). The time needed for a full configuration depends on the PCLK frequency. With a PCLK frequency of 10 MHz the full configuration is done in less than 53 ms. Setting the device in power down mode requires sending one frame only and will in this case takelessthan2ms.Allregistersarealsoreadable. During each write-cycle, 16 bits are sent on the PDI-line. The seven most significant bits of each data frame (A6:0) are the address-bits. A6 is the MSB (Most Significant Bit) of the address and is sent as the first bit. The next bit is the R/W bit (high for write, low for read). The 8 data-bits are then transferred (D7:0).DuringaddressanddatatransferthePSEL(ProgramSelect)mustbekeptlow.SeeFigure5-4. The timing for the programming is also shown in Figure 5-4 with reference to Table 5-1. The clocking of the data on PDI is done on the positive edge of PCLK. Data should be set up on the negative edge of PCLK by the microcontroller. When the last bit, D0, of the 8 data-bits has been loaded, the data word is loadedintotheinternalconfigurationregister. The configuration data will be retained during a programmed power down mode, but not when the power supplyisturnedoff.Theregisterscanbeprogrammedinanyorder. The configuration registers can also be read by the microcontroller via the same configuration interface. The seven address bits are sent first, then the R/W bit set low to initiate the data read-back. CC1020 then returns the data from the addressed register. PDO is used as the data output and must be configured as an input by the microcontroller. The PDO is set at the negative edge of PCLK and should be sampled at thepositiveedge.ThereadoperationisillustratedinFigure5-5. PSELmustbesethighbetweeneachread/writeoperation. T T SS HS T T T T CL,min CH,min HD SD PCLK Address Writemode Databyte PDI 6 5 4 3 2 1 0 W 7 6 5 4 3 2 1 0 PDO PSEL Figure5-4.ConfigurationRegistersWriteOperation 20 DetailedDescription Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 www.ti.com SWRS046H–NOVEMBER2006–REVISEDMARCH2015 T T SS HS T T CL,min CH,min PCLK Address Readmode PDI 6 5 4 3 2 1 0 R Databyte PDO 7 6 5 4 3 2 1 0 PSEL T SH Figure5-5.ConfigurationRegistersReadOperation Table5-1.SerialInterface,TimingSpecification(1) PARAMETER MIN MAX UNIT CONDITION F PCLK,clockfrequency 10 MHz PCLK T PCLKlowpulseduration 50 ns TheminimumtimePCLKmustbelow. CL,min T PCLKhighpulseduration 50 ns TheminimumtimePCLKmustbehigh. CH,min TheminimumtimePSELmustbelowbefore T PSELsetuptime 25 ns SS positiveedgeofPCLK. TheminimumtimePSELmustbeheldlow T PSELholdtime 25 ns HS afterthenegativeedgeofPCLK. T PSELhightime 50 ns TheminimumtimePSELmustbehigh. SH TheminimumtimedataonPDImustbeready T PDIsetuptime 25 ns SD beforethepositiveedgeofPCLK. TheminimumtimedatamustbeheldatPDI, T PDIholdtime 25 ns HD afterthepositiveedgeofPCLK. T Risetime 100 ns ThemaximumrisetimeforPCLKandPSEL rise T Falltime 100 ns ThemaximumfalltimeforPCLKandPSEL fall (1) Thesetupandholdtimesreferto50%ofVDD.Theriseandfalltimesreferto10%/90%ofVDD.Themaximumloadthatthistableis validforis20pF. 5.6 Signal Interface The CC1020 can be used with NRZ (Non-Return-to-Zero) data or Manchester (also known as bi-phase- level) encoded data. CC1020 can also synchronize the data from the demodulator and provide the data clockatDCLK.ThedataformatiscontrolledbytheDATA_FORMAT[1:0]bitsintheMODEMregister. CC1020 can be configured for three different data formats: Synchronous NRZ mode, Transparent AsynchronousUARTmode,andSynchronousManchesterencodedmode. Copyright©2006–2015,TexasInstrumentsIncorporated DetailedDescription 21 SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 SWRS046H–NOVEMBER2006–REVISEDMARCH2015 www.ti.com 5.6.1 Synchronous NRZ Mode In transmit mode CC1020 provides the data clock at DCLK and DIO is used as data input. Data is clocked intoCC1020attherisingedgeofDCLK.ThedataismodulatedatRFwithoutencoding. In receive mode CC1020 performs the synchronization and provides received data clock at DCLK and data at DIO. The data should be clocked into the interfacing circuit at the rising edge of DCLK. See Figure5-6. 5.6.2 Transparent Asynchronous UART Mode In transmit mode DIO is used as data input. The data is modulated at RF without synchronization or encoding. In receive mode the raw data signal from the demodulator is sent to the output (DIO). No synchronization ordecodingofthesignalisdoneinCC1020andshouldbedonebytheinterfacingcircuit. If SEP_DI_DO = 0 in the INTERFACE register, the DIO pin is the data output in receive mode and data input in transmit mode. The DCLK pin is not active and can be set to a high or low level by DATA_FORMAT[0]. If SEP_DI_DO = 1 in the INTERFACE register, the DCLK pin is the data output in receive mode and the DIOpinisthedatainputintransmitmode.InTXmodetheDCLKpinisnotactiveandcanbesettoahigh orlowlevelbyDATA_FORMAT[0].SeeFigure5-7. 5.6.3 Synchronous Manchester Encoded Mode In transmit mode CC1020 provides the data clock at DCLK and DIO is used as data input. Data is clocked into CC1020 at the rising edge of DCLK and should be in NRZ format. The data is modulated at RF with Manchester code. The encoding is done by CC1020. In this mode the effective bit rate is half the baud rateduetothecoding.Asanexample,4.8kBaudManchesterencodeddatacorrespondsto2.4kbps. In receive mode CC1020 performs the synchronization and provides received data clock at DCLK and data at DIO. CC1020 performs the decoding and NRZ data is presented at DIO. The data should be clockedintotheinterfacingcircuitattherisingedgeofDCLK.SeeFigure5-7. In synchronous NRZ or Manchester mode the DCLK signal runs continuously both in RX and TX unless the DCLK signal is gated with the carrier sense signal or the PLL lock signal. Refer to Section 5.18 and Section5.18.2formoredetails. If SEP_DI_DO = 0 in the INTERFACE register, the DIO pin is the data output in receive mode and data inputintransmitmode. As an option, the data output can be made available at a separate pin. This is done by setting SEP_DI_DO = 1 in the INTERFACE register. Then, the LOCK pin will be used as data output in synchronousmode,overridingotheruseoftheLOCKpin. 5.6.3.1 ManchesterEncodingandDecoding In the Synchronous Manchester encoded mode CC1020 uses Manchester coding when modulating the data. The CC1020 also performs the data decoding and synchronization. The Manchester code is based on transitions; a “0” is encoded as a low-to-high transition, a “1” is encoded as a high-to-low transition. SeeFigure5-9. The Manchester code ensures that the signal has a constant DC component, which is necessary in some FSKdemodulators.UsingthismodealsoensurescompatibilitywithCC400/CC900designs. 22 DetailedDescription Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 www.ti.com SWRS046H–NOVEMBER2006–REVISEDMARCH2015 TTrraannssmmiitttteerrssiiddee:: DDCCLLKK CClloocckkpprroovviiddeedd bbyyCCCC11002200 DDIIOO DDaattaa pprroovviiddeedd bbyymmiiccrrooccoonnttrroolllleerr FFSSKKmmoodduullaattiinnggssiiggnnaall ((NNRRZZ)),, ““RRFF”” iinntteerrnnaall iinn CCCC11002200 RReecceeiivveerrssiiddee:: DDeemmoodduullaatteedd ssiiggnnaall ((NNRRZZ)),, ““RRFF”” iinntteerrnnaall iinn CCCC11002200 DDCCLLKK CClloocckkpprroovviiddeedd bbyyCCCC11002200 DDIIOO DDaattaa pprroovviiddeedd bbyyCCCC11002200 Figure5-6.SynchronousNRZMode(SEP_DI_DO=0) TTrraannssmmiitttteerrssiiddee:: DDCCLLKK CClloocckkpprroovviiddeedd bbyyCCCC11002200 DDIIOO DDaattaa pprroovviiddeedd bbyymmiiccrrooccoonnttrroolllleerr FFSSKKmmoodduullaattiinnggssiiggnnaall ((MMaanncchheesstteerr ““RRFF”” eennccooddeedd)),, iinntteerrnnaall iinn CCCC11002200 RReecceeiivveerrssiiddee:: DDeemmoodduullaatteeddssiiggnnaall((MMaanncchheesstteerr ““RRFF”” eennccooddeedd)),, iinntteerrnnaall iinn CCCC11002200 DDCCLLKK CClloocckkpprroovviiddeedd bbyyCCCC11002200 DDIIOO DDaattaa pprroovviiddeedd bbyyCCCC11002200 Figure5-7.SynchronousManchesterEncodedMode(SEP_DI_DO=0) Copyright©2006–2015,TexasInstrumentsIncorporated DetailedDescription 23 SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 SWRS046H–NOVEMBER2006–REVISEDMARCH2015 www.ti.com TTrraannssmmiitttteerrssiiddee:: DDCCLLKKiiss nnoott uusseedd iinnttrraannssmmiittmmooddee,, aanndd iiss uusseeddaassddaattaa oouuttppuuttiinn rreecceeiivveemmooddee.. IIttccaannbbee DDCCLLKK sseett ttooddeeffaauulltt hhiigghhoorrllooww iinn ttrraannssmmiittmmooddee.. DDIIOO DDaattaa pprroovviiddeedd bbyyUUAARRTT((TTXXDD)) FFSSKKmmoodduullaattiinnggssiiggnnaall,, ““RRFF”” iinntteerrnnaall iinn CCCC11002200 RReecceeiivveerrssiiddee:: DDeemmoodduullaatteedd ssiiggnnaall ((NNRRZZ)),, ““RRFF”” iinntteerrnnaall iinn CCCC11002200 DDCCLLKKiissuusseedd aass ddaattaaoouuttppuutt DDCCLLKK pprroovviiddeedd bbyyCCCC11002200.. CCoonnnneeccttttooUUAARRTT((RRXXDD)) DDIIOO DDIIOO iissnnoottuusseeddiinn rreecceeiivveemmooddee..UUsseeddoonnllyy aass ddaattaaiinnppuutt iinn ttrraannssmmiittmmooddee Figure5-8.TransparentAsynchronousUARTMode(SEP_DI_DO=1) 11 00 11 11 00 00 00 11 11 00 11 TTxx ddaattaa TTiimmee Figure5-9.ManchesterEncoding 5.7 Data Rate Programming The data rate (baud rate) is programmable and depends on the crystal frequency and the programming of theCLOCK(CLOCK_AandCLOCK_B)registers. Thebaudrate(B.R.)isgivenbyEquation1. f B.R.= xosc 8´(REF_DIV+1)´DIV1´DIV2 (1) Where: DIV1andDIV2aregivenbythevalueofMCLK_DIV1andMCLK_DIV2. Table 5-4 shows some possible data rates as a function of crystal frequency in synchronous mode. In asynchronoustransparentUARTmodeanydatarateupto153.6kBaudcanbeused. Table5-2.DIV2forDifferentSettingsofMCLK_DIV2 MCLK_DIV2[1:0] DIV2 00 1 01 2 10 4 11 8 24 DetailedDescription Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 www.ti.com SWRS046H–NOVEMBER2006–REVISEDMARCH2015 Table5-3.DIV1forDifferentSettingsofMCLK_DIV1 MCLK_DIV1[2:0] DIV1 000 2.5 001 3 010 4 011 7.5 100 12.5 101 40 110 48 111 64 Table5-4.SomePossibleDataRatesVersusCrystalFrequency DATARATE CRYSTALFREQUENCY[MHz] [kBaud] 4.9152 7.3728 9.8304 12.288 14.7456 17.2032 19.6608 0.45 X X 0.5 X 0.6 X X X X X X X 0.9 X X 1 X 1.2 X X X X X X X 1.8 X X 2 X 2.4 X X X X X X X 3.6 X X 4 X 4.096 X X 4.8 X X X X X X X 7.2 X X 8 X 8.192 X X 9.6 X X X X X X X 14.4 X X 16 X 16.384 X X 19.2 X X X X X X X 28.8 X X 32 X 32.768 X X 38.4 X X X X X X X 57.6 X X 64 X 65.536 X 76.8 X X X X X X X 115.2 X X 128 X 153.6 X X X X X Copyright©2006–2015,TexasInstrumentsIncorporated DetailedDescription 25 SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 SWRS046H–NOVEMBER2006–REVISEDMARCH2015 www.ti.com 5.8 Frequency Programming Programming the frequency word in the configuration registers sets the operation frequency. There are two frequency words registers, termed FREQ_A and FREQ_B, which can be programmed to two different frequencies. One of the frequency words can be used for RX (local oscillator frequency) and the other for TX (transmitting carrier frequency) in order to be able to switch very fast between RX mode and TX mode. They can also be used for RX (or TX) at two different channels. The F_REG bit in the MAIN register selectsfrequencywordAorB. The frequency word is located in FREQ_2A:FREQ_1A:FREQ_0A and FREQ_2B:FREQ_1B:FREQ_0B for the FREQ_A and FREQ_B word respectively. The LSB of the FREQ_0 registers are used to enable dithering,seeSection5.8.1. ThePLLoutputfrequencyisgivenbyEquation2 inthefrequencyband402to470MHz. æ3 FREQ + 0.5´DITHERö fc = fref ´çè4 + 32768 ÷ø (2) ThePLLoutputfrequencyisgivenbyEquation3 inthefrequencyband804to960MHz. æ3 FREQ + 0.5´DITHERö fc = fref ´çè2 + 16384 ÷ø (3) The BANDSELECT bit in the ANALOG register controls the frequency band used. BANDSELECT = 0 gives402to470MHz,andBANDSELECT=1gives804to960MHz. The reference frequency is the crystal oscillator clock frequency divided by REF_DIV (3 bits in the CLOCK_AorCLOCK_Bregister),anumberbetween1and7,asshowninEquation4. f f = xosc ref REF_DIV +1 (4) FSKfrequencydeviationisprogrammedintheDEVIATIONregister.Thedeviationprogrammingisdivided intoamantissa(TXDEV_M[3:0])andanexponent(TXDEV_X[2:0]). Generally REF_DIV should be as low as possible but the requirements (shown in Equation 5 and Equation6)mustbemet. f 9.8304 ³ f > c [MHz] ref 256 (5) Equation5inthefrequencyband402to470MHz,andEquation6inthefrequencyband804to960MHz. f 9.8304 ³ f > c [MHz] ref 512 (6) The PLL output frequency Equation 2 and Equation 3 give the carrier frequency, f , in transmit mode c (centrefrequency).ThetwoFSKmodulationfrequenciesaregivenbyEquation7andEquation7. f =f –f (7) 0 c dev f =f +f (8) 1 c dev Where: f is set by the DEVIATION register shown in Equation 9 in the frequency band 402 to 470 MHz and dev inEquation10inthefrequencyband804to960MHz. f = f ´TXDEV_M´2(TXDEV_X-16) dev ref (9) f = f ´TXDEV_M´2(TXDEV_X-15) dev ref (10) OOK(On-OffKeying)isusedifTXDEV_M[3:0]=0000. TheTX_SHAPINGbitintheDEVIATIONregistercontrolsGaussianshapingofthemodulationsignal. 26 DetailedDescription Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 www.ti.com SWRS046H–NOVEMBER2006–REVISEDMARCH2015 In receive mode the frequency must be programmed to be the LO frequency. Low side LO injection is used,henceEquation8. f =f –f (11) LO c IF Where: f istheIFfrequency(ideally307.2kHz). IF 5.8.1 Dithering Spurious signals will occur at certain frequencies depending on the division ratios in the PLL. To reduce thestrengthofthesespurs,acommontechniqueistouseaditheringsignalinthecontrolofthefrequency dividers. Dithering is activated by setting the DITHER bit in the FREQ_0 registers. It is recommended to usetheditheringinordertoachievethebestpossibleperformance. 5.9 Receiver 5.9.1 IF Frequency TheIFfrequencyisderivedfromthecrystalfrequencyasshowninEquation12. f f = xoscx IF 8´(ADC_DIV[2:0]+1) (12) Where: ADC_DIV[2:0]issetintheMODEMregister. The analog filter succeeding the mixer is used for wideband and anti-alias filtering, which is important for the blocking performance at 1 MHz and larger offsets. This filter is fixed and centered on the nominal IF frequencyof307.2kHz.Thebandwidthoftheanalogfilterisabout160kHz. Using crystal frequencies which gives an IF frequency within 300 to 320 kHz means that the analog filter canbeused(assuminglowfrequencydeviationsandlowdatarates). Large offsets, however, from the nominal IF frequency will give an un-symmetric filtering (variation in group delay and different attenuation) of the signal, resulting in decreased sensitivity and selectivity. See AN022CC1020CrystalFrequencySelection (SWRA070)formoredetails. For IF frequencies other than 300 to 320 kHz and for high frequency deviation and high data rates (typically≥ 76.8kBaud)theanalogfiltermustbebypassedbysettingFILTER_BYPASS=1intheFILTER register.Inthiscasetheblockingperformanceat1MHzandlargeroffsetswillbedegraded. The IF frequency is always the ADC clock frequency divided by 4. The ADC clock frequency should thereforebeascloseto1.2288MHzaspossible. 5.9.2 Receiver Channel Filter Bandwidth In order to meet different channel spacing requirements, the receiver channel filter bandwidth is programmable.Itcanbeprogrammedfrom9.6to307.2kHz. The minimum receiver channel filter bandwidth depends on baud rate, frequency separation and crystal tolerance. The signal bandwidth must be smaller than the available receiver channel filter bandwidth. The signal bandwidth(SBW)canbeapproximatedby(Carson’srule)showninEquation13. SBW=2×f +2×frequencydeviation (13) m Where: f isthemodulatingsignal. m Copyright©2006–2015,TexasInstrumentsIncorporated DetailedDescription 27 SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 SWRS046H–NOVEMBER2006–REVISEDMARCH2015 www.ti.com In Manchester mode the maximum modulating signal occurs when transmitting a continuous sequence of 0s (or 1s). In NRZ mode the maximum modulating signal occurs when transmitting a 0-1-0 sequence. In both Manchester and NRZ mode 2 × fm is then equal to the programmed baud rate. The equation for SBWcanthenberewrittenasshowninEquation14. SBW=Baudrate+frequencyseparation (14) Furthermore, the frequency offset of the transmitter and receiver must also be considered. Assuming equal frequency error in the transmitter and receiver (same type of crystal) the total frequency error is showninEquation15. f_error=±2×XTAL_ppm×f_RF (15) Where: XTAL_ppm is the total accuracy of the crystal including initial tolerance, temperature drift, loading and ageing. F_RFistheRFoperatingfrequency. Theminimumreceiverchannelfilterbandwidth(ChBW)canthenbeestimatedasshowninEquation16. ChBW>SBW+2×f_error (16) The DEC_DIV[4:0] bits in the FILTER register control the receiver channel filter bandwidth. The 6 dB bandwidthisgivenbyEquation17. 307.2 ChBW = (DEC_DIV+1)[kHz] (17) Where: theIFfrequencyissetto307.2kHz. In SmartRF Studio the user specifies the channel spacing and the channel filter bandwidth is set accordingtoTable5-5. For narrowband systems with channel spacings of 12.5 and 25 kHz the channel filter bandwidth is 12.288 kHzand19.2kHzrespectivelytocomplywithARIBSTD-T67andEN300220. For wideband systems (channel spacing of 50 kHz and above) it is possible to use different channel filter bandwidthsthangiveninTable5-5. There is a trade-off between selectivity as well as sensitivity and accepted frequency tolerance. In applications where larger frequency drift is expected, the filter bandwidth can be increased, but with reducedadjacentchannelrejection(ACR)andsensitivity. Table5-5.ChannelFilterBandwidthsUsedfortheChannelSpacingsDefinedinSmartRFStudio FILTER.DEC_DIV CHANNELSPACING FILTERBANDWIDTH [4:0] [kHz] [kHz] [decimal(binary)] 12.5 12.288 24(11000b) 25 19.2 15(01111b) 50 25.6 11(01011b) 100 51.2 5(00101b) 150 102.4 2(00010b) 200 153.6 1(00001b) 500 307.2 0(00000b) 28 DetailedDescription Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 www.ti.com SWRS046H–NOVEMBER2006–REVISEDMARCH2015 5.9.3 Demodulator, Bit Synchronizer, and Data Decision The block diagram for the demodulator, data slicer and bit synchronizer is shown in Figure 5-10. The built- in bit synchronizer synchronizes the internal clock to the incoming data and performs data decoding. The data decision is done using over-sampling and digital filtering of the incoming signal. This improves the reliability of the data transmission. Using the synchronous modes simplifies the data-decoding task substantially. The recommended preamble is a ‘010101…’ bit pattern. The same bit pattern should also be used in Manchester mode, giving a ‘011001100110…‘chip’ pattern. This is necessary for the bit synchronizer to synchronizetothecodingcorrectly. The data slicer does the bit decision. Ideally the two received FSK frequencies are placed symmetrically around the IF frequency. However, if there is some frequency error between the transmitter and the receiver, the bit decision level should be adjusted accordingly. In CC1020, this is done automatically by measuringthetwofrequenciesandusetheaveragevalueasthedecisionlevel. The digital data slicer in CC1020 uses an average value of the minimum and maximum frequency deviation detected as the comparison level. The RXDEV_X[1:0] and RXDEV_M[3:0] in the AFC_CONTROL register are used to set the expected deviation of the incoming signal. Once a shift in the received frequency larger than the expected deviation is detected, a bit transition is recorded and the averagevaluetobeusedbythedatasliceriscalculated. The minimum number of transitions required to calculate a slicing level is 3. That is, a 010 bit pattern (NRZ). The actual number of bits used for the averaging can be increased for better data decision accuracy. This is controlled by the SETTLING[1:0] bits in the AFC_CONTROL register. If RX data is present in the channel when the RX chain is turned on, then the data slicing estimate will usually give correct results after 3 bit transitions. The data slicing accuracy will increase after this, depending on the SETTLING[1:0] bits. If the start of transmission occurs after the RX chain has turned on, the minimum number of bit transitions(orpreamblebits)beforecorrectdataslicingwilldependontheSETTLING[1:0]bits. The automatic data slicer average value function can be disabled by setting SETTLING[1:0] = 00. In this caseasymmetricalsignalaroundtheIFfrequencyisassumed. The internally calculated average FSK frequency value gives a measure for the frequency offset of the receivercomparedtothetransmitter.Thisinformationcanalsobeusedforanautomaticfrequencycontrol (AFC)asdescribedinSection5.9.13. Average filter Frequency Data Data slicer Bit synchronizer Digital filtering Decimator detector filter comparator and data decoder Figure5-10.DemodulatorBlockDiagram Copyright©2006–2015,TexasInstrumentsIncorporated DetailedDescription 29 SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 SWRS046H–NOVEMBER2006–REVISEDMARCH2015 www.ti.com 5.9.4 Receiver Sensitivity Versus Data Rate and Frequency Separation The receiver sensitivity depends on the channel filter bandwidth, data rate, data format, FSK frequency separation and the RF frequency. Typical figures for the receiver sensitivity (BER = 10–3) are shown in Table 5-6 and Table 5-7 for FSK. For best performance, the frequency deviation should be at least half thebaudrateinFSKmode. The sensitivity is measured using the matching network shown in the application circuit in Figure 6-1, whichincludesanexternalT/Rswitch. Refer to AN029 CC1020/1021 Automatic Frequency Control (AFC) (SWRA063) for plots of sensitivity versusfrequencyoffset. Table5-6.TypicalReceiverSensitivityasaFunctionofDataRateat433MHz,FSKModulation, BER=10–3,Pseudo-randomData(PN9Sequence) CHANNEL SENSITIVITY[dBm] DATARATE DEVIATION [kBaud] SP[AkHCzIN]G [kHz] FILTERBW NRZMODE MANMCOHDEESTER UARTMODE 2.4optimized sensitivity(1) 12.5 ±2.025 9.6 –115 –118 –115 2.4optimized selectivity(1) 12.5 ±2.025 12.288 –112 –114 –112 4.8 25 ±2.475 19.2 –112 –112 –112 9.6 50 ±4.95 25.6 –110 –111 –110 19.2 100 ±9.9 51.2 –107 –108 –107 38.4 150 ±19.8 102.4 –104 –104 –104 76.8 200 ±36.0 153.6 –101 –101 –101 153.6 500 ±72.0 307.2 –96 –97 –96 (1) OptimizedselectivityisrelevantforsystemstargetingcompliancewithARIBSTD-T67,12.5kHzchannelspacing. Table5-7.TypicalReceiverSensitivityasaFunctionofDataRateat868MHz,FSKModulation, BER=10–3,Pseudo-randomData(PN9Sequence) CHANNEL SENSITIVITY[dBm] DATARATE [kBaud] SP[AkHCzIN]G DEVIATION[kHz] FILTERBW NRZMODE MANMCOHDEESTER UARTMODE 2.4 12.5 ±2.025 12.288 –112 –116 –112 4.8 25 ±2.475 19.2 –111 –112 –111 9.6 50 ±4.95 25.6 –109 –110 –109 19.2 100 ±9.9 51.2 –107 –107 –107 38.4 150 ±19.8 102.4 –103 –103 –103 76.8 200 ±36.0 153.6 –99 –100 –99 153.6 500 ±72.0 307.2 –94 –94 –94 30 DetailedDescription Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 www.ti.com SWRS046H–NOVEMBER2006–REVISEDMARCH2015 5.9.5 RSSI CC1020 has a built-in RSSI (Received Signal Strength Indicator) giving a digital value that can be read form the RSSI register. The RSSI reading must be offset and adjusted for VGA gain setting (VGA_SETTING[4:0]intheVGA3register). ThedigitalRSSIvalueisrangingfrom0to106(7bits). The RSSI reading is a logarithmic measure of the average voltage amplitude after the digital filter in the digitalpartoftheIFchainasshowninEquation18. RSSI=4log (signalamplitude) (18) 2 TherelativepoweristhengivenbyRSSI× 1.5dBinalogarithmicscale. The number of samples used to calculate the average signal amplitude is controlled by AGC_AVG[1:0] in theVGA2register.TheRSSIupdaterateisgivenbyEquation19. f f = filter_clock RSSI 2AGC_AVG[1:0]+1 (19) Where: AGC_AVG[1:0]issetintheVGA2register. f =2 ×ChBW. filter_clock Maximum VGA gain is programmed by the VGA_SETTING[4:0] bits. The VGA gain is programmed in approximately 3 dB/LSB. The RSSI measurement can be referred to the power (absolute value) at the RF_INpinbyusingtheEquation20. P=1.5×RSSI–3×VGA_SETTING–RSSI_Offset[dBm] (20) The RSSI_Offset depends on the channel filter bandwidth used due to different VGA settings. Figure 5-11 and Figure 5-12 show typical plots of RSSI reading as a function of input power for different channel spacings. See Section 5.9.5 for a list of channel filter bandwidths corresponding to the various channel spacings. Refer to AN030 CC1020/1021 Received Signal Strength Indicator (SWRA062) for further details. The method shown in Equation 21 can be used to calculate the power (P) in dBm from the RSSI readout valuesinFigure5-11andFigure5-12. P=1.5×[RSSI–RSSI_ref]+P_ref (21) Where: PistheoutputpowerindBmforthecurrentRSSIreadoutvalue. RSSI_ref is the RSSI readout value taken from Figure 5-11 or Figure 5-12 for an input power level of P_ref. NOTE TheRSSIreadingindecimalvaluechangesfordifferentchannelfilterbandwidths. The analog filter has a finite dynamic range and is the reason why the RSSI reading is saturated at lower channel spacings. Higher channel spacing is typically used for high frequency deviation and data rates. The analog filter bandwidth is about 160 kHz and is bypassed for high frequency deviation and data rates and is the reason why the RSSI reading is not saturated for 200 kHz and 500 kHz channel spacing in Figure5-11andFigure5-12. Copyright©2006–2015,TexasInstrumentsIncorporated DetailedDescription 31 SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 SWRS046H–NOVEMBER2006–REVISEDMARCH2015 www.ti.com Figure5-11.TypicalRSSIValuevsInputPowerforSome Figure5-12.TypicalRSSIValuevsInputPowerforSome TypicalChannelSpacings,433MHz TypicalChannelSpacings,868MHz 5.9.6 Image Rejection Calibration For perfect image rejection, the phase and gain of the “I” and “Q” parts of the analog RX chain must be perfectly matched. To improve the image rejection, the “I” and “Q” phase and gain difference can be fine- tuned by adjusting the PHASE_COMP and GAIN_COMP registers. This allows compensation for process variationsandothernonidealities.Thecalibrationisdonebyinjectingasignalattheimagefrequency,and adjustingthephaseandgaindifferenceforminimumRSSIvalue. During image rejection calibration, an unmodulated carrier should be applied at the image frequency (614.4 kHz below the desired channel). No signal should be present in the desired channel. The signal level should be 50 to 60 dB above the sensitivity in the desired channel, but the optimum level will vary from application to application. Too large input level gives poor results due to limited linearity in the analog IFchain,whiletoolowinputlevelgivespoorresultsduetothereceivernoisefloor. For best RSSI accuracy, use AGC_AVG[1:0] = 11 during image rejection calibration (RSSI value is averaged over 16 filter output samples). The RSSI register update rate then equals the receiver channel bandwidth (set in FILTER register) divided by 8, as the filter output rate is twice the receiver channel bandwidth. This gives the minimum waiting time between RSSI register reads (0.5 ms is used below). TI recommendsthefollowingimagecalibrationprocedure: 1. Define3variables:XP=0,XG=0andDX=64.Gotostep3. 2. SetDX=DX/2. 3. WriteXGtoGAIN_COMPregister. 4. If XP + 2 × DX < 127, then write XP + 2 × DX to PHASE_COMP register else write 127 to PHASE_COMP register. 5. Waitatleast3ms.MeasuresignalstrengthY4asfilteredaverageof8readsfromRSSIregisterwith 0.5msofdelaybetweeneachRSSIread. 6. WriteXP+DXtoPHASE_COMPregister. 7. Waitatleast3ms.MeasuresignalstrengthY3asfilteredaverageof8readsfromRSSIregisterwith 0.5msofdelaybetweeneachRSSIread. 8. WriteXPtoPHASE_COMPregister. 9. Waitatleast3ms.MeasuresignalstrengthY2asfilteredaverageof8readsfromRSSIregisterwith 0.5msofdelaybetweeneachRSSIread. 10. WriteXP-DXtoPHASE_COMPregister. 11. Waitatleast3ms.MeasuresignalstrengthY1asfilteredaverageof8readsfromRSSIregisterwith 32 DetailedDescription Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 www.ti.com SWRS046H–NOVEMBER2006–REVISEDMARCH2015 0.5msofdelaybetweeneachRSSIread. 12. WriteXP– 2× DXtoPHASE_COMPregister. 13. Waitatleast3ms.MeasuresignalstrengthY0asfilteredaverageof8readsfromRSSIregisterwith 0.5msofdelaybetweeneachRSSIread. 14. SetAP=2 ×(Y0 – Y2+Y4)– (Y1+Y3). 15. If AP > 0 then set DP = ROUND ( 7 × DX × (2 × (Y0 – Y4) + Y1 – Y3) / (10 × AP)) else if Y0 + Y1 > Y3 + Y4 then set DP = DX else set DP = –DX. 16. If DP > DX then set DP = DX else if DP < –DX then set DP = –DX. 17. SetXP=XP+DP. 18. WriteXPtoPHASE_COMPregister. 19. If XG + 2 × DX < 127 then write XG + 2 × DX to GAIN_COMP register else write 127 to GAIN_COMP register. 20. Waitatleast3ms.MeasuresignalstrengthY4asfilteredaverageof8readsfromRSSIregisterwith 0.5msofdelaybetweeneachRSSIread. 21. WriteXG+DXtoGAIN_COMPregister. 22. Waitatleast3ms.MeasuresignalstrengthY3asfilteredaverageof8readsfromRSSIregisterwith 0.5msofdelaybetweeneachRSSIread. 23. WriteXGtoGAIN_COMPregister. 24. Waitatleast3ms.MeasuresignalstrengthY2asfilteredaverageof8readsfromRSSIregisterwith 0.5msofdelaybetweeneachRSSIread. 25. WriteXG– DXtoGAIN_COMPregister. 26. Waitatleast3ms.MeasuresignalstrengthY1asfilteredaverageof8readsfromRSSIregisterwith 0.5msofdelaybetweeneachRSSIread. 27. WriteXG– 2 ×DXtoGAIN_COMPregister. 28. Waitatleast3ms.MeasuresignalstrengthY0asfilteredaverageof8readsfromRSSIregisterwith 0.5msofdelaybetweeneachRSSIread. 29. SetAG=2× (Y0– Y2+Y4)– (Y1+Y3). 30. If AG > 0 then set DG = ROUND (7 × DX × (2 × (Y0 – Y4) + Y1 – Y3) / (10 × AG) else if Y0 + Y1 > Y3 + Y4 then set DG = DX else set DG = –DX. 31. If DG > DX then set DG = DX else if DG < –DX then set DG = –DX 32. SetXG=XG+DG. 33. IfDX>1thengotostep2. 34. WriteXPtoPHASE_COMPregisterandXGtoGAIN_COMPregister. If repeated calibration gives varying results, try to change the input level or increase the number of RSSI reads N. A good starting point is N = 8. As accuracy is more important in the last fine-calibration steps, it canbeworthwhiletoincreaseNforeachloopiteration. Copyright©2006–2015,TexasInstrumentsIncorporated DetailedDescription 33 SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 SWRS046H–NOVEMBER2006–REVISEDMARCH2015 www.ti.com For high frequency deviation and high data rates (typically ≥ 76.8 kBaud) the analog filter succeeding the mixer must be bypassed by setting FILTER_BYPASS = 1 in the FILTER register. In this case the image rejectionisdegraded. Theimagerejectionisreducedforlowsupplyvoltages(typically <2.5V)whenoperatinginthe402to470 MHzfrequencyrange. 5.9.7 Blocking and Selectivity Figure 5-13 shows the blocking/selectivity at 433 MHz, 12.5 kHz channel spacing. Figure 5-14 shows the blocking/selectivity at 868 MHz, 25 kHz channel spacing. The blocking rejection is the ratio between a modulatedblocker(interferer)andawantedsignal3dBabovethesensitivitylimit. Figure5-13.TypicalBlockerRejection Figure5-14.TypicalBlockerRejection CarrierFrequencySetto434.3072MHz CarrierFrequencySetto868.3072MHz (12.5kHzChannelSpacing,12.288kHzReceiverChannelFilter (25kHzChannelSpacing,19.2kHzReceiverChannelFilter Bandwidth) Bandwidth) 5.9.8 Linear IF Chain and AGC Settings CC1020 is based on a linear IF chain where the signal amplification is done in an analog VGA (Variable Gain Amplifier). The gain is controlled by the digital part of the IF chain after the ADC (Analog to Digital Converter). The AGC (Automatic Gain Control) loop ensures that the ADC operates inside its dynamic rangebyusingananalog/digitalfeedbackloop. The maximum VGA gain is programmed by the VGA_SETTING[4:0] in the VGA3 register. The VGA gain is programmed in approximately 3 dB/LSB. The VGA gain should be set so that the amplified thermal noise from the front-end balance the quantization noise from the ADC. Therefore the optimum maximum VGAgainsettingwilldependonthechannelfilterbandwidth. A digital RSSI is used to measure the signal strength after the ADC. The CS_LEVEL[4:0] in the VGA4 register is used to set the nominal operating point of the gain control (and also the carrier sense level). FurtherexplanationcanbefoundinFigure5-15. The VGA gain will be changed according to a threshold set by the VGA_DOWN[2:0] in the VGA3 register and the VGA_UP[2:0] in the VGA4 register. Together, these two values specify the signal strength limits usedbytheAGCtoadjusttheVGAgain. To avoid unnecessary tripping of the VGA, an extra hysteresis and filtering of the RSSI samples can be added.TheAGC_HYSTERESISbitintheVGA2registerenablesthis. The time dynamics of the loop can be altered by the VGA_BLANKING bit in the ANALOG register, and VGA_FREEZE[1:0]andVGA_WAIT[2:0]bitsintheVGA1register. When VGA_BLANKING is activated, the VGA recovery time from DC offset spikes after a gain step is reduced. 34 DetailedDescription Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 www.ti.com SWRS046H–NOVEMBER2006–REVISEDMARCH2015 VGA_FREEZE determines the time to hold bit synchronization, VGA and RSSI levels after one of these eventsoccur: • RXpower-up • ThePLLhasbeenoutoflock • FrequencyregistersettingisswitchedbetweenAandB This feature is useful to avoid AGC operation during start-up transients and to ensure minimum dwell time usingfrequencyhopping.Thismeansthatbitsynchronizationcanbemaintainedfromhoptohop. VGA_WAIT determines the time to hold the present bit synchronization and RSSI levels after changing VGA gain. This feature is useful to avoid AGC operation during the settling of transients after a VGA gain change.SometransientsareexpectedduetoDCoffsetsintheVGA. At the sensitivity limit, the VGA gain is set by VGA_SETTING. In order to optimize selectivity, this gain should not be set higher than necessary. The SmartRF Studio software gives the settings for VGA1 to VGA4registers.Forreference,thefollowingmethodcanbeusedtofindtheAGCsettings: 1. DisableAGCandusemaximumLNA2gainbywritingBFhtotheVGA2register.SetminimumVGA gainbywritingtotheVGA3registerwithVGA_SETTING=0. 2. ApplynoRFinputsignal,andmeasureADCnoisefloorbyreadingtheRSSIregister. 3. ApplynoRFinputsignal,andwriteVGA3registerwithincreasingVGA_SETTINGvalueuntiltheRSSI registervalueisapproximately4largerthanthevaluereadinstep2.Thisplacesthefront-endnoise flooraround6dBabovetheADCnoisefloor. 4. ApplyanRFsignalwithstrengthequalthedesiredcarriersensethreshold.TheRFsignalshould preferablybemodulatedwithcorrectBaudrateanddeviation.ReadtheRSSIregistervalue,subtract 8,andwritetoCS_LEVELintheVGA4register.VarytheRFsignallevelslightlyandcheckthatcarrier senseindication(bit3inSTATUSregister)switchesatthedesiredinputlevel. 5. Ifdesired,adjusttheVGA_UPandVGA_DOWNsettingsaccordingtotheexplanationinFigure5-15. 6. EnableAGCandselectLNA2gainchangelevel.Write55htoVGA2registeriftheresulting VGA_SETTING>10.Otherwise,write45htoVGA2.ModifyAGC_AVGintheaboveVGA2valueif fastercarriersenseandAGCsettlingisdesired. RSSI Level NotethattheAGCworkswith"raw"filteroutputsignal (signalstrength,1.5dB/step) strength,whiletheRSSIreadoutvalueiscompensatedfor VGAgainchangesbytheAGC. AGCdecreasesgainifabove thislevel(unlessatminimum). TheAGCkeepsthesignalstrengthinthisrange.Minimize VGA_DOWNforbestselectivity,butleavesomemarginto VGA_DOWN+3 avoidfrequentVGAgainchangesduringreception. AGCincreasesgainifbelowthis level(unlessatmaximum). TheAGCkeepsthesignalstrengthabovecarriersenselevel +VGA_UP.MinimizeVGA_UPforbestselectivity,but VGA_UP increaseiffirstVGAgainreductionoccurstooclosetothe noisefloor. Carriersenseisturnedonhere. TosetCS_LEVEL,subtract8fromRSSIreadoutwithRF inputsignalatdesiredcarriersenselevel. CS_LEVEL+8 Zeroleveldependsonfront-endsettingsandVGA_SETTING 0 value. Figure5-15.RelationshipBetweenRSSI,CarrierSenseLevel, andAGCSettingsCS_LEVEL,VGA_UPandVGA_DOWN Copyright©2006–2015,TexasInstrumentsIncorporated DetailedDescription 35 SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 SWRS046H–NOVEMBER2006–REVISEDMARCH2015 www.ti.com 5.9.9 AGC Settling AfterturningontheRXchain,thefollowingoccurs: A. TheAGCwaits16to128ADC_CLK(1.2288MHz)periods,dependingontheVGA_FREEZEsettingin theVGA1register,forsettlingintheanalogparts. B. TheAGCwaits16to48FILTER_CLKperiods,dependingontheVGA_WAITsettingintheVGA1 register,forsettlingintheanalogpartsandthedigitalchannelfilter. C. TheAGCcalculatestheRSSIvalueastheaveragemagnitudeoverthenext2to16FILTER_CLK periods,dependingontheAGC_AVGsettingintheVGA2register. D. IftheRSSIvalueishigherthanCS_LEVEL+8,thenthecarriersenseindicatorisset(ifCS_SET=0). IftheRSSIvalueistoohighaccordingtotheCS_LEVEL,VGA_UPandVGA_DOWNsettings,andthe VGAgainisnotalreadyatminimum,thentheVGAgainisreducedandtheAGCcontinuesfromB). E. IftheRSSIvalueistoolowaccordingtotheCS_LEVELandVGA_UPsettings,andtheVGAgainis notalreadyatmaximum(givenbyVGA_SETTING),thentheVGAgainisincreasedandtheAGC continuesfromB). Two to three VGA gain changes should be expected before the AGC has settled. Increasing AGC_AVG increasesthesettlingtime,butmaybeworthwhileifthereisthetimeintheprotocol,andforreducingfalse wake-upeventswhensettingthecarriersenseclosetothenoisefloor. The AGC settling time depends on the FILTER_CLK (= 2 × ChBW). Thus, there is a trade off between AGC settling time and receiver sensitivity because the AGC settling time can be reduced for data rates lowerthan76.8kBaudbyusingawiderreceiverchannelfilterbandwidth(thatis,largerChBW). 5.9.10 Preamble Length and Sync Word Therulesforchoosingagoodsyncwordareasfollows: 1. Thesyncwordshouldbesignificantlydifferentfromthepreamble. 2. Alargenumberoftransitionsisgoodforthebitsynchronizationorclockrecovery.Equalbitsreduce thenumberoftransitions.Therecommendedsyncwordhasatmost3equalbitsinarow. 3. Autocorrelation.Thesyncwordshouldnotrepeatitself,asthiswillincreasethelikelihoodforerrors. 4. Ingeneralthefirstbitofsyncshouldbeoppositeoflastbitinpreamble,toachieveonemoretransition. The recommended sync words for CC1020 are 2 bytes (0xD391), 3 bytes (0xD391DA) or 4 bytes (0xD391DA26)andareselectedasthebestcompromiseoftheabovecriteria. Using the register settings provided by the SmartRFM Studio software, packet error rates (PER) less than 0.5% can be achieved when using 24 bits of preamble and a 16 bit sync word (0xD391). Using a preamblelongerthan24bitswillimprovethePER. When performing the PER measurements described above the packet format consisted of 10 bytes of random data, 2 bytes CRC and 1 dummy byte in addition to the sync word and preamble at the start of eachpackage. For the test, 1000 packets were sent 10 times. The transmitter was put in power down between each packet. Any bit error in the packet, either in the sync word, in the data or in the CRC caused the packet to becountedasafailedpacket. 36 DetailedDescription Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 www.ti.com SWRS046H–NOVEMBER2006–REVISEDMARCH2015 5.9.11 Carrier Sense The carrier sense signal is based on the RSSI value and a programmable threshold. The carrier sense function can be used to simplify the implementation of a CSMA (Carrier Sense Multiple Access) medium accessprotocol. Carrier sense threshold level is programmed by CS_LEVEL[4:0] in the VGA4 register and VGA_SETTING[4:0]intheVGA3register. VGA_SETTING[4:0] sets the maximum gain in the VGA. This value must be set so that the ADC works with optimum dynamic range for a certain channel filter bandwidth. The detected signal strength (after the ADC)willthereforedependonthissetting. CS_LEVEL[4:0] sets the threshold for this specific VGA_SETTING[4:0] value. If the VGA_SETTING[4:0] is changed, the CS_LEVEL[4:0] must be changed accordingly to maintain the same absolute carrier sense threshold. See Figure 5-15 for an explanation of the relationship between RSSI, AGC and carrier sense settings. ThecarriersensesignalcanbereadastheCARRIER_SENSEbitintheSTATUSregister. The carrier sense signal can also be made available at the LOCK pin by setting LOCK_SELECT[3:0] = 0100intheLOCKregister. 5.9.12 Automatic Power-up Sequencing CC1020 has a built-in automatic power-up sequencing state machine. By setting the CC1020 into this mode, the receiver can be powered-up automatically by a wake-up signal and will then check for a carrier signal (carrier sense). If carrier sense is not detected, it returns to power-down mode. A flow chart for automaticpower-upsequencingisshowninFigure5-16. The automatic power-up sequencing mode is selected when PD_MODE[1:0] = 11 in the MAIN register. When the automatic power-up sequencing mode is selected, the functionality of the MAIN register is changedandusedtocontrolthesequencing. BysettingSEQ_PD=1intheMAINregister,CC1020issetinpowerdownmode.IfSEQ_PSEL=1inthe SEQUENCING register the automatic power-up sequence is initiated by a negative transition on the PSEL pin. If SEQ_PSEL = 0 in the SEQUENCING register, then the automatic power-up sequence is initiated by a negativetransitionontheDIOpin(aslongasSEP_DI_DO=1intheINTERFACEregister). SequencetimingiscontrolledthroughRX_WAIT[2:0]ANDCS_WAIT[3:0]intheSEQUENCINGregister. VCO and PLL calibration can also be done automatically as a part of the sequence. This is controlled through SEQ_CAL[1:0] in the MAIN register. Calibration can be done every time, every 16th sequence, every 256th sequence, or never. See Section 5.22.1 description for details. A description of when to do, andhowtheVCOandPLLself-calibrationisdone,isgiveninSection5.12.2. SeealsoApplicationNoteAN070CC1020AutomaticPower-UpSequencing(SWRA279). Copyright©2006–2015,TexasInstrumentsIncorporated DetailedDescription 37 SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 SWRS046H–NOVEMBER2006–REVISEDMARCH2015 www.ti.com Powerdown Turn on crystal oscillator/bias Sequencing wake-up event Crystaloscillator and biasoff Frequencysynthesizer off (negative transition on Frequencysynthesizer off Receive chainoff PSELpin or DIO pin) Receive chainoff Crystaloscillator and biason Turn on frequency synthesizer Receive chainoff Set Optionalcalibration Waitfor PLL PLLtimeout SEQ_ERROR Programmable:each time, lockor timeout, flaginSTATUS oncein 16,or once in256 127 filter clocks register Receive chainoff PLLin lock Optional waiting time before turning on receivechain Programmable: 32-256ADC clocks Crystaloscillator and biason Frequencysynthesizer on Turnonreceivechain Waitfor Carriersensetimeout carrier sense or timeout Programmable: 20-72 filter clocks Carriersense Receive mode Sequencing power-downevent Crystaloscillator and biason Frequencysynthesizer on (PositivetransitiononSEQ_PDinMAINregister) Receive chainon (1) Filterclock(FILTER_CLK):f =2×ChBWwhereChBWisdefinedinSection5.9.2. filter_clock f f = xoscx ADC 2´(ADC_DIV[2:0]+1) (2) ADCclock(ADC_CLK): whereADC_DIV[2:0]issetintheMODEMregister. Figure5-16.AutomaticPower-upSequencingFlowChart 5.9.13 Automatic Frequency Control CC1020 has a built-in feature called AFC (Automatic Frequency Control) that can be used to compensate forfrequencydrift. The average frequency offset of the received signal (from the nominal IF frequency) can be read in the AFC register. The signed (2’s-complement) 8-bit value AFC[7:0] can be used to compensate for frequency offsetbetweentransmitterandreceiver. ThefrequencyoffsetisgivenbyEquation22. AFC´Baudrate DF = 16 (22) The receiver can be calibrated against the transmitter by changing the operating frequency according to the measured offset. The new frequency must be calculated and written to the FREQ register by the microcontroller. The AFC can be used for an FSK/GFSK signal, but not for OOK. Application Note AN029 CC1020/1021 Automatic Frequency Control (AFC) (SWRA063) provides the procedure and equations necessarytoimplementAFC. TheAFCfeaturereducesthecrystalaccuracyrequirement. 38 DetailedDescription Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 www.ti.com SWRS046H–NOVEMBER2006–REVISEDMARCH2015 5.9.14 Digital FM It is possible to read back the instantaneous IF from the FM demodulator as a frequency offset from the nominalIFfrequency.ThisdigitalvaluecanbeusedtoperformapseudoanalogFMdemodulation. The frequency offset can be read from the GAUSS_FILTER register and is a signed 8-bit value coded as 2-complement. TheinstantaneousdeviationisgivenbyEquation23. GAUSS_FILTER´Baudrate F = 8 (23) The digital value should be read from the register and sent to a DAC and filtered in order to get an analog audiosignal.TheinternalregistervalueisupdatedattheMODEM_CLKrate.MODEM_CLKisavailableat the LOCK pin when LOCK_SELECT[3:0] = 1101 in the LOCK register, and can be used to synchronize thereading. For audio (300 to 4000 Hz) the sampling rate should be higher than or equal to 8 kHz (Nyquist) and is determined by the MODEM_CLK. The MODEM_CLK, which is the sampling rate, equals 8 times the baud rate. That is, the minimum baud rate, which can be programmed, is 1 kBaud. However, the incoming data will be filtered in the digital domain and the 3-dB cut-off frequency is 0.6 times the programmed Baud rate. Thus,foraudiotheminimumprogrammedBaudrateshouldbeapproximately7.2kBaud. The GAUSS_FILTER resolution decreases with increasing baud rate. A accumulate and dump filter can be implemented in the µC to improve the resolution. Note that each GAUSS_FILTER reading should be synchronized to the MODEM_CLK. As an example, accumulating 4 readings and dividing the total by 4 willimprovetheresolutionby2bits. Furthermore, to fully utilize the GAUSS_FILTER dynamic range the frequency deviation must be 16 times theprogrammedbaudrate. 5.10 Transmitter 5.10.1 FSK Modulation Formats The data modulator can modulate FSK, which is a two level FSK (Frequency Shift Keying), or GFSK, which is a Gaussian filtered FSK with BT = 0.5. The purpose of the GFSK is to make a more bandwidth efficient system as shown in Figure 5-17. The modulation and the Gaussian filtering are done internally in the chip. The TX_SHAPING bit in the DEVIATION register enables the GFSK. GFSK is recommended for narrowbandoperation. Figure5-18andFigure5-19showtypicaleyediagramsfor434MHzand868MHzoperation,respectively. Copyright©2006–2015,TexasInstrumentsIncorporated DetailedDescription 39 SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 SWRS046H–NOVEMBER2006–REVISEDMARCH2015 www.ti.com 2.4kBaud, NRZ, ±2.025kHz 2.4kBaud, NRZ, ±2.025kHz frequencydeviation frequencydeviation Figure5-17.FSKvsGFSKSpectrumPlot Figure5-18.FSKvsGFSKEyeDiagram 153.6kBaud, NRZ, ±79.2kHzfrequency deviation Figure5-19.GFSKEyeDiagram 5.10.2 Output Power Programming The RF output power from the device is programmable by the 8-bit PA_POWER register. Figure 5-20 and Figure 5-21 show the output power and total current consumption as a function of the PA_POWER register setting. It is more efficient in terms of current consumption to use either the lower or upper 4-bits in the register to control the power, as shown in Figure 5-20 and Figure 5-21. However, the output power canbecontrolledinfinerstepsusingalltheavailablebitsinthePA_POWERregister. 40 DetailedDescription Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 www.ti.com SWRS046H–NOVEMBER2006–REVISEDMARCH2015 35.0 30.0 m] 25.0 dB 20.0 [ er 15.0 w o p 10.0 ut p 5.0 ut O 0.0 A] / -5.0 m nt [ -10.0 e urr -15.0 C -20.0 -25.0 0 1 2 3 4 5 6 7 8 9 0A 0B 0C0D0E 0F 50 60 70 80 90 A0 B0 C0 D0 E0 F0 FF PA_POWER[hex] CurrentConsumption OutputPower Figure5-20.TypicalOutputPowerandCurrentConsumption,433MHz 35.0 30.0 m] 25.0 dB 20.0 [ er 15.0 w o p 10.0 ut p 5.0 ut O 0.0 / A] -5.0 m [ nt -10.0 e urr -15.0 C -20.0 -25.0 0 1 2 3 4 5 6 7 8 9 0A 0B 0C0D0E 0F 50 60 70 80 90 A0 B0 C0 D0 E0 F0 FF PA_POWER[hex] CurrentConsumption OutputPower Figure5-21.TypicalOutputPowerandCurrentConsumption,433MHz 5.10.3 TX Data Latency The transmitter will add a delay due to the synchronization of the data with DCLK and further clocking into the modulator. The user should therefore add a delay equivalent to at least 2 bits after the data payload hasbeentransmittedbeforeswitchingoffthePA(thatis,beforestoppingthetransmission). Copyright©2006–2015,TexasInstrumentsIncorporated DetailedDescription 41 SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 SWRS046H–NOVEMBER2006–REVISEDMARCH2015 www.ti.com 5.10.4 Reducing Spurious Emission and Modulation Bandwidth Modulation bandwidth and spurious emission are normally measured with the PA continuously on and a repeatedtestsequence. In cases where the modulation bandwidth and spurious emission are measured with the CC1020 switching from power down mode to TX mode, a PA ramping sequence could be used to minimize modulationbandwidthandspuriousemission. PA ramping should then be used both when switching the PA on and off. A linear PA ramping sequence can be used where register PA_POWER is changed from 00h to 0Fh and then from 50h to the register setting that gives the desired output power (for example, F0h for +10 dBm output power at 433 MHz operation).ThelongerthetimeperPArampingstepthebetter,butsettingthetotalPArampingtimeequal to2bitperiodsisagoodcompromisebetweenperformanceandPArampingtime. 5.11 Input and Output Matching and Filtering When designing the impedance matching network for the CC1020 the circuit must be matched correctly at the harmonic frequencies as well as at the fundamental tone. A recommended matching network is shown in Figure 5-22. Component values for various frequencies are given in Table 5-8. Component values for otherfrequenciescanbefoundusingtheSmartRFStudiosoftware. As can be seen from Figure 5-22 and Table 5-8, the 433 MHz network utilizes a T-type filter, while the 868/915MHznetworkhasaπ-typefiltertopology. It is important to remember that the physical layout and the components used contribute significantly to the reflection coefficient, especially at the higher harmonics. For this reason, the frequency response of the matching network should be measured and compared to the response of the TI reference design. RefertoFigure5-24andTable5-9aswellasFigure5-25andTable5-10. The use of an external T/R switch reduces current consumption in TX for high output power levels and improves the sensitivity in RX. A recommended application circuit is available from the TI web site (CC1020EMX). The external T/R switch can be omitted in certain applications, but performance will then bedegraded. ThematchcanalsobetunedbyashuntcapacitorarrayatthePAoutput(RF_OUT).Thecapacitancecan be set in 0.4-pF steps and used either in RX mode or TX mode. The RX_MATCH[3:0] and TX_MATCH[3:0]bitsintheMATCHregistercontrolthecapacitorarray. AVDD = 3 V R10 ANTENNA CC1021 C60 L2 L70 L71 C3 RF_OUT RF_IN C71 C72 C1 L1 T/R SWITCH Figure5-22.InputandOutputMatchingNetwork 42 DetailedDescription Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 www.ti.com SWRS046H–NOVEMBER2006–REVISEDMARCH2015 Table5-8.ComponentValuesfortheMatchingNetworkDescribedinFigure5-22 ITEM 433MHz 868MHz 915MHz C1 10pF,5%,NP0,0402 47pF,5%,NP0,0402 47pF,5%,NP0,0402 C3 5.6pF,5%,NP0,0402 10pF,5%,NP0,0402 10pF,5%,NP0,0402 C60 220pF,5%,NP0,0402 220pF,5%,NP0,0402 220pF,5%,NP0,0402 C71 DNM(1) 8.2pF5%,NP0,0402 8.2pF5%,NP0,0402 C72 4.7pF,5%,NP0,0402 8.2pF5%,NP0,0402 8.2pF5%,NP0,0402 L1 33nH,5%,0402 82nH,5%,0402 82nH,5%,0402 L2 22nH,5%,0402 3.6nH,5%,0402 3.6nH,5%,0402 L70 47nH,5%,0402 5.1nH,5%,0402 5.1nH,5%,0402 L71 39nH,5%,0402 0Ωresistor,0402 0Ωresistor,0402 R10 82Ω,5%,0402 82Ω,5%,0402 82Ω,5%,0402 (1) DNM=DoNotMount Figure5-23.TypicalLNAInputImpedance,200to1000MHz Copyright©2006–2015,TexasInstrumentsIncorporated DetailedDescription 43 SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 SWRS046H–NOVEMBER2006–REVISEDMARCH2015 www.ti.com Thefrequencyissweptfrom300MHzto2500MHz.Valuesarelistedin. Figure5-24.TypicalOptimumPALoadImpedance,433MHz Table5-9.ImpedancesattheFirst5Harmonics (433MHzMatchingNetwork) FREQUENCY REAL IMAGINARY (MHz) (Ohms) (Ohms) 433 54 44 866 20 173 1299 288 –563 1732 14 –123 2165 5 –66 44 DetailedDescription Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 www.ti.com SWRS046H–NOVEMBER2006–REVISEDMARCH2015 Thefrequencyissweptfrom300MHzto2800MHz.ValuesarelistedinTable5-10. Figure5-25.TypicaloptimumPAloadimpedance,868/915MHz Table5-10.ImpedancesattheFirstThreeHarmonics (868/915MHzMatchingNetwork) FREQUENCY REAL IMAGINARY (MHz) (Ohms) (Ohms) 868 15 24 915 20 35 1736 1.5 18 1830 1.7 22 2604 3.2 44 2745 3.6 45 5.12 Frequency Synthesizer 5.12.1 VCO, Charge Pump and PLL Loop Filter The VCO is completely integrated and operates in the 1608 to 1920 MHz range. A frequency divider is used to get a frequency in the UHF range (402 to 470 and 804 to 960 MHz). The BANDSELECT bit in the ANALOGregisterselectsthefrequencyband. Copyright©2006–2015,TexasInstrumentsIncorporated DetailedDescription 45 SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 SWRS046H–NOVEMBER2006–REVISEDMARCH2015 www.ti.com TheVCOfrequencyisgivenbyEquation24. æ FREQ + 0.5´DITHERö fVCO= fref´çè3 + 8192 ÷ø (24) TheVCOfrequencyisdividedby2andby4togeneratefrequenciesinthetwobands,respectively. The VCO sensitivity (sometimes referred to as VCO gain) varies over frequency and operating conditions. Typically the VCO sensitivity varies between 12 and 36 MHz/V. For calculations the geometrical mean at 21 MHz/V can be used. The PLL calibration (explained below) measures the actual VCO sensitivity and adjusts the charge pump current accordingly to achieve correct PLL loop gain and bandwidth (higher chargepumpcurrentwhenVCOsensitivityislower). Equation 25 through Equation 29 can be used for calculating PLL loop filter component values, see Figure6-1,foradesiredPLLloopbandwidth,BW. æ f ö C7 =3037ç ref ÷ -7[pF] èBW2ø (25) æBWö R2 = 7126ç ÷[kW] f è ref ø (26) C6 =80.75æçèBfWref2ö÷ø[nF] (27) æBWö R3 = 21823ç ÷[kW] f è ref ø (28) æ f ö C8 =839ç ref ÷ - 6 [pF] èBW2ø (29) DefineaminimumPLLloopbandwidthasshowninEquation30. f BW = 80.75´ ref min 220 (30) If BW > Baud rate/3 then set BW = BW and if BW < Baud rate/3 then set BW = Baud rate/3 in min min min Equation25throughEquation29. Therearetwospecialcaseswhenusingtherecommended14.7456MHzcrystal: 1. Ifthedatarateis4.8kBaudorbelowandthechannelspacingis12.5kHzthefollowingloopfilter componentsarerecommended: C6=220nF C7=8200pF C8=2200pF R2=1.5kΩ R3=4.7kΩ 2. Ifthedatarateis4.8kBaudorbelowandthechannelspacingisdifferentfrom12.5kHzthefollowing loopfiltercomponentsarerecommended: C6=100nF C7=3900pF C8=1000pF R2=2.2kΩ R3=6.8kΩ 46 DetailedDescription Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 www.ti.com SWRS046H–NOVEMBER2006–REVISEDMARCH2015 After calibration the PLL bandwidth is set by the PLL_BW register in combination with the external loop filtercomponentscalculatedabove.ThePLL_BWcanbefoundfromEquation31. æ f ö PLL_BW =174 +16log ç ref ÷ 2 è7.126ø (31) Where: f isthereferencefrequency(inMHz). ref The PLL loop filter bandwidth increases with increasing PLL_BW setting. Note that in SmartRF Studio PLL_BWisfixedto9Ehexwhenthechannelspacingissetupfor12.5kHz,optimizedselectivity. After calibration the applied charge pump current (CHP_CURRENT[3:0]) can be read in the STATUS1 register.ThechargepumpcurrentisapproximatelygivenbyEquation32. I =16´2CHP_CURRENT/4[mA] CHP (32) The combined charge pump and phase detector gain (in A/rad) is given by the charge pump current dividedby2π. ThePLLbandwidthwilllimitthemaximummodulationfrequencyandhence,datarate. 5.12.2 VCO and PLL Self-Calibration To compensate for supply voltage, temperature and process variations, the VCO and PLL must be calibrated. The calibration is performed automatically and sets the maximum VCO tuning range and optimum charge pump current for PLL stability. After setting up the device at the operating frequency, the self-calibration can be initiated by setting the CAL_START bit in the CALIBRATE register. The calibration result is stored internally in the chip, and is valid as long as power is not turned off. If large supply voltage drops (typically more than 0.25 V) or temperature variations (typically more than 40°C) occur after calibration,anewcalibrationshouldbeperformed. ThenominalVCOcontrolvoltageissetbytheCAL_ITERATE[2:0]bitsintheCALIBRATEregister. The CAL_COMPLETE bit in the STATUS register indicates that calibration has finished. The calibration wait time (CAL_WAIT) is programmable and is inverse proportional to the internal PLL reference frequency. The highest possible reference frequency should be used to get the minimum calibration time. ItisrecommendedtouseCAL_WAIT[1:0]=11inordertogetthemostaccurateloopbandwidth. Table5-11.TypicalCalibrationTimes CALIBRATION REFERENCEFREQUENCY[MHz] TIME[ms] CAL_WAIT 1.8432 7.3728 9.8304 00 49ms 12ms 10ms 01 60ms 15ms 11ms 10 71ms 18ms 13ms 11 109ms 27ms 20ms The CAL_COMPLETE bit can also be monitored at the LOCK pin, configured by LOCK_SELECT[3:0] = 0101,andusedasaninterruptinputtothemicrocontroller. To check that the PLL is in lock the user should monitor the LOCK_CONTINUOUS bit in the STATUS register. The LOCK_CONTINUOUS bit can also be monitored at the LOCK pin, configured by LOCK_SELECT[3:0]=0010. Copyright©2006–2015,TexasInstrumentsIncorporated DetailedDescription 47 SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 SWRS046H–NOVEMBER2006–REVISEDMARCH2015 www.ti.com Thereareseparatecalibrationvaluesforthetwofrequencyregisters.However,dualcalibrationispossible ifallofthebelowconditionsapply: • ThetwofrequenciesAandBdifferbylessthan1MHz. • Reference frequencies are equal (REF_DIV_A[2:0] = REF_DIV_B[2:0] in the CLOCK_A/CLOCK_B registers). • VCOcurrentsareequal(VCO_CURRENT_A[3:0]=VCO_CURRENT_B[3:0]intheVCOregister). TheCAL_DUALbitintheCALIBRATEregistercontrolsdualorseparatecalibration. The single calibration algorithm (CAL_DUAL=0) using separate calibration for RX and TX frequency is illustrated in Figure 5-26. The same algorithm is applicable for dual calibration if CAL_DUAL=1. Refer to Application Note AN023 CC1020 MCU Interfacing (SWRA069), which includes example source code for singlecalibration. TIrecommendsthatsinglecalibrationbeusedformorerobustoperation. There is a small, but finite, possibility that the PLL self-calibration will fail. The calibration routine in the source code should include a loop so that the PLL is re-calibrated until PLL lock is achieved if the PLL doesnotlockthefirsttime.Referto CC1020ErrataNote004,availableintheCC1020productfolder. 48 DetailedDescription Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 www.ti.com SWRS046H–NOVEMBER2006–REVISEDMARCH2015 SSStttaaarrrttt sssiiinnngggllleee cccaaallliiibbbrrraaatttiiiooonnn WWrriitteeFFRREEQQ__AA,,FFRREEQQ__BB,,VVCCOO,, ff iisstthheerreeffeerreenncceeffrreeqquueennccyy((iinn rreeff CCLLOOCCKK__AAaannddCCLLOOCCKK__BBrreeggiisstteerrss.. MMHHzz)) PPLLLL__BBWW==117744++1166lloogg ((ff //77..112266)) 22 rreeff CCaalliibbrraatteeRRXXffrreeqquueennccyyrreeggiisstteerrAA WWrriitteeMMAAIINNrreeggiisstteerr==1111hh:: ((ttooccaalliibbrraatteeTTXXffrreeqquueennccyyrreeggiisstteerr RRXXTTXX==00,,FF__RREEGG==00,,PPDD__MMOODDEE==11,, BBwwrriitteeMMAAIINNrreeggiisstteerr==DD11hh)).. FFSS__PPDD==00,,CCOORREE__PPDD==00,,BBIIAASS__PPDD==00,, RReeggiisstteerrCCAALLIIBBRRAATTEE==3344hh RREESSEETT__NN==11 WWrriitteeCCAALLIIBBRRAATTEErreeggiisstteerr==BB44hh SSttaarrttccaalliibbrraattiioonn WWaaiittffoorrTT≥≥110000uuss RReeaaddSSTTAATTUUSSrreeggiisstteerraannddwwaaiittuunnttiill CCAALL__CCOOMMPPLLEETTEE==11 RReeaaddSSTTAATTUUSSrreeggiisstteerraannddwwaaiittuunnttiill LLOOCCKK__CCOONNTTIINNUUOOUUSS==11 NNoo CCaalliibbrraattiioonnOOKK?? YYeess EEEnnndddooofff cccaaallliiibbbrrraaatttiiiooonnn Figure5-26.SingleCalibrationAlgorithmforRXandTX 5.12.3 PLL Turn-on Time Versus Loop Filter Bandwidth If calibration has been performed the PLL turn-on time is the time needed for the PLL to lock to the desired frequency when going from power down mode (with the crystal oscillator running) to TX or RX mode. The PLL turn-on time depends on the PLL loop filter bandwidth. Table 5-12 gives the PLL turn-on timefordifferentPLLloopfilterbandwidths. Copyright©2006–2015,TexasInstrumentsIncorporated DetailedDescription 49 SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 SWRS046H–NOVEMBER2006–REVISEDMARCH2015 www.ti.com Table5-12.TypicalPLLTurn-onTimetoWithin ±10%ofChannelSpacingforDifferentLoopFilter Bandwidths C6 C7 C8 R2 R3 PLLTURN-ONTIME COMMENT [nF] [pF] [pF] [kΩ] [kΩ] [µs] Upto4.8kBauddata rate, 220 8200 2200 1.5 4.7 3200 12.5kHzchannel spacing Upto4.8kBauddata 100 3900 1000 2.2 6.8 2500 rate, 25kHzchannelspacing Upto9.6kBauddata 56 2200 560 3.3 10 1400 rate, 50kHzchannelspacing Upto19.2kBauddata 15 560 150 5.6 18 1300 rate, 100kHzchannelspacing Upto38.4kBauddata 3.9 120 33 12 39 1080 rate, 150kHzchannelspacing Upto76.8kBauddata 1.0 27 3.3 27 82 950 rate, 200kHzchannelspacing Upto153.6kBauddata 0.2 1.5 — 47 150 700 rate, 500kHzchannelspacing 5.12.4 PLL Lock Time Versus Loop Filter Bandwidth If calibration has been performed the PLL lock time is the time needed for the PLL to lock to the desired frequency when going from RX to TX mode or vice versa. The PLL lock time depends on the PLL loop filterbandwidth.Table5-13givesthePLLlocktimefordifferentPLLloopfilterbandwidths. Table5-13.TypicalPLLLockTimetoWithin ±10%ofChannelSpacingforDifferentLoopFilter Bandwidths(1) C6 C7 C8 R2 R3 PLLLOCKTIME[µs] Comment [nF] [pF] [pF] [kΩ] [kΩ] 1 2 3 Upto4.8kBauddatarate,12.5kHz 220 8200 2200 1.5 4.7 900 180 1300 channelspacing Upto4.8kBauddatarate,25kHz 100 3900 1000 2.2 6.8 640 270 830 channelspacing Upto9.6kBauddatarate,50kHz 56 2200 560 3.3 10 400 140 490 channelspacing Upto19.2kBauddatarate,100kHz 15 560 150 5.6 18 140 70 230 channelspacing Upto38.4kBauddatarate,150kHz 3.9 120 33 12 39 75 50 180 channelspacing Upto76.8kBauddatarate,200kHz 1.0 27 3.3 27 82 30 15 55 channelspacing Upto153.6kBauddatarate,500 0.2 1.5 — 47 150 14 14 28 kHzchannelspacing (1) 1)307.2kHzstep, 2)1channelstep, 3)1MHzstep 50 DetailedDescription Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 www.ti.com SWRS046H–NOVEMBER2006–REVISEDMARCH2015 5.13 VCO and LNA Current Control The VCO current is programmable and should be set according to operating frequency, RX/TX mode and output power. Recommended settings for the VCO_CURRENT bits in the VCO register are shown in Table 5-16 and are also given by SmartRF Studio. The VCO current for frequency FREQ_A and FREQ_B canbeprogrammedindependently. The bias currents for the LNA, mixer and the LO and PA buffers are also programmable. The FRONTEND andtheBUFF_CURRENTregisterscontrolthesecurrents. 5.14 Power Management CC1020 offers great flexibility for power management in order to meet strict power consumption requirements in battery-operated applications. Power down mode is controlled through the MAIN register. There are separate bits to control the RX part, the TX part, the frequency synthesizer and the crystal oscillator in the MAIN register. This individual control can be used to optimize for lowest possible current consumption in each application. Figure 5-27 shows a typical power-on and initializing sequence for minimumpowerconsumption. Figure 5-28 shows a typical sequence for activating RX and TX mode from power down mode for minimumpowerconsumption. NOTE PSEL shouldbe tri-statedorset to ahighlevelduringpower downmode inorder to prevent atricklecurrentfromflowingintheinternalpullupresistor. ApplicationNoteAN023CC1020MCUInterfacing (SWRA069)includesexamplesourcecode. TIrecommendsresettingtheCC1020(byclearingtheRESET_NbitintheMAINregister)whenthechipis powered up initially. All registers that need to be configured should then be programmed (those which differ from their default values). Registers can be programmed freely in any order. The CC1020 should then be calibrated in both RX and TX mode. After this is completed, the CC1020 is ready for use. See the detailedprocedureflowchartsinFigure5-26throughFigure5-28. With reference to Application Note AN023 CC1020 MCU Interfacing (SWRA069), TI recommends the followingsequence: Afterpowerup: 1. ResetCC1020 2. Initialize 3. WakeUpCC1020ToRX 4. Calibrate 5. WakeUpCC1020ToTX 6. Calibrate After calibration is completed, enter TX mode (SetupCC1020TX), RX mode (SetupCC1020RX) or power downmode(SetupCC1020PD). Frompower-downmodetoRX: 1. WakeUpCC1020ToRX 2. SetupCC1020RX Copyright©2006–2015,TexasInstrumentsIncorporated DetailedDescription 51 SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 SWRS046H–NOVEMBER2006–REVISEDMARCH2015 www.ti.com Frompower-downmodetoTX: 1. WakeUpCC1020ToTX 2. SetupCC1020TX SwitchingfromRXtoTXmode: 1. SetupCC1020TX SwitchingfromTXtoRXmode: 1. SetupCC1020RX PPPooowwweeerrr OOOffffff TTuurrnn oonn ppoowweerr RReesseett CCCC11002200 MMAAIINN::RRXX__TTXX==00,, FF__RREEGG==00,, 2020 PPDD__MMOODDEE==11,, FFSS__PPDD==11,, 00 11 XXOOSSCC__PPDD==11,, BBIIAASS__PPDD==11 CC CC RREESSEETT__NN==00 etet ss ee RR RREESSEETT__NN==11 PPrrooggrraammaallllnneecceessssaarryyrreeggiisstteerrss eexxcceepptt MMAAIINN aanndd RREESSEETT x/x/xx RRTT ToToToTo TTuurrnnoonn ccrryyssttaalloosscciillllaattoorr,, bbiiaass 0000 2222 ggeenneerraattoorraannddssyynntthheessiizzeerr 0000 CC11C1C1 ssuucccceessssiivveellyy CCCC pppp uuuu eeee kkkk aaaa WWWW CCaalliibbrraatteeVVCCOO aanndd PPLLLL DD PP 00 22 00 MMAAIINN::PPDD__MMOODDEE==11,, FFSS__PPDD==11,, 11 CC XXOOSSCC__PPDD==11,, BBIIAASS__PPDD==11 CC pp PPAA__PPOOWWEERR==0000hh uu etet SS PPoowweerrDDoowwnnmmooddee Figure5-27.InitializingSequence 52 DetailedDescription Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 www.ti.com SWRS046H–NOVEMBER2006–REVISEDMARCH2015 **TTiimmee ttoo wwaaiitt ddeeppeennddss PPPooowwweeerrrDDDooowwwnnnmmmooodddeee oonn tthheeccrryyssttaall ffrreeqquueennccyy aanndd tthhee llooaadd ccaappaacciittaannccee TTuurrnnoonn ccrryyssttaalloosscciillllaattoorrccoorree xx xx RR MMAAIINN::PPDD__MMOODDEE==11,, FFSS__PPDD==11,, XXOOSSCC__PPDD==00,, BBIIAASS__PPDD==11 TT oo oo TT WWaaiitt11..22mmss** TT 00 00 22 22 00 00 11 11 CC CC CC CC pp TTuurrnnoonnbbiiaass ggeenneerraattoorr.. MMAAIINN::BBIIAASS__PPDD==00 pp uu uu ee WWaaiitt115500 uuss ee kk kk aa aa WW WW RRXX TTXX RRXX oorrTTXX?? TTTuuurrrnnn ooonnn fffrrreeeqqquuueeennncccyyysssyyynnnttthhheeesssiiizzzeeerrr TTTuuurrrnnn ooonnn fffrrreeeqqquuueeennncccyyysssyyynnnttthhheeesssiiizzzeeerrr MMMAAAIIINNN:::RRRXXXTTTXXX===000,,, FFF___RRREEEGGG===000,,, FFFSSS___PPPDDD===000 MMMAAAIIINNN:::RRRXXXTTTXXX===111,,, FFF___RRREEEGGG===111,,, FFFSSS___PPPDDD===000 xx xx RR TT 00 WWWaaaiiittt uuunnntttiiilllllloooccckkkdddeeettteeecccttteeedddfffrrrooommm LLLOOOCCCKKKpppiiinnn WWWaaaiiittt uuunnntttiiilllllloooccckkkdddeeettteeecccttteeedddfffrrrooommm LLLOOOCCCKKKpppiiinnn 00 22 22 00 ooorrrSSSTTTAAATTTUUUSSSrrreeegggiiisssttteeerrr ooorrrSSSTTTAAATTTUUUSSSrrreeegggiiisssttteeerrr 00 11 11 CC TTTuuurrrnnnooonnnRRRXXX:::MMMAAAIIINNN::: PPPDDD___MMMOOODDDEEE === 000 TTTuuurrrnnn ooonnnTTTXXX::: MMMAAAIIINNN::: PPPDDD___MMMOOODDDEEE ===000 CC CC CC upup SSSeeetttPPPAAA___PPPOOOWWWEEERRR upup etet etet SS SS RRRRXXXXmmmmooooddddeeee TTTTXXXXmmmmooooddddeeee TTuurrnnooffff RRXX//TTXX:: DD DD PP MMAAIINN:: PPDD__MMOODDEE ==11,,FFSS__PPDD==11,, PP 00 00 22 XXOOSSCC__PPDD==11,, BBIIAASS__PPDD==11 22 00 00 C1C1 PPAA__PPOOWWEERR==0000hh C1C1 CC CC pp pp uu uu etet etet SS SS PPPooowwweeerrrDDDooowwwnnnmmmooodddeee Figure5-28.SequenceforActivatingRXorTXMode 5.15 On-Off Keying (OOK) The data modulator can also provide OOK (On-Off Keying) modulation. OOK is an ASK (Amplitude Shift Keying) modulation using 100% modulation depth. OOK modulation is enabled in RX and in TX by setting TXDEV_M[3:0]=0000intheDEVIATIONregister.AnOOKeyediagramisshowninFigure5-29. The data demodulator can also perform OOK demodulation. The demodulation is done by comparing the signal level with the “carrier sense” level (programmed as CS_LEVEL in the VGA4 register). The signal is then decimated and filtered in the data filter. Data decision and bit synchronization are as for FSK reception. Copyright©2006–2015,TexasInstrumentsIncorporated DetailedDescription 53 SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 SWRS046H–NOVEMBER2006–REVISEDMARCH2015 www.ti.com In this mode, AGC_AVG in the VGA2 register must be set to 3. The channel bandwidth must be 4 times the Baud rate for data rates up to 9.6 kBaud. For the highest data rates the channel bandwidth must be 2 timestheBaudrate(seeTable5-14).ManchestercodingmustalwaysbeusedforOOK. NOTE Theautomaticfrequencycontrol(AFC)cannotbeusedwhenreceivingOOK,asitrequiresa frequencyshift. The AGC has a certain time-constant determined by FILTER_CLK, which depends on the IF filter bandwidth. There is a lower limit on FILTER_CLK and hence the AGC time constant. For very low data rates the minimum time constant is too fast and the AGC will increase the gain when a “0” is received and decreasethegainwhena“1” isreceived.ForthisreasontheminimumdatarateinOOKis2.4kBaud. Typicalfiguresforthereceiversensitivity(BER=10–3)areshowninTable5-14forOOK. 9.6kBaud Figure5-29.OOKEyeDiagram Table5-14.TypicalReceiverSensitivityasaFunctionofDataRateat433and868MHz,OOKModulation, BER=10–3,Pseudo-randomData(PN9Sequence) SENSITIVITY[dBm] DATARATE FILTERBW [kBaud] [kHz] 433MHz 868MHz MANCHESTERMODE MANCHESTERMODE 2.4 9.6 –116 — 4.8 19.2 –113 –107 9.6 38.4 –103 –104 19.2 51.2 –102 –101 38.4 102.4 –95 –97 76.8 153.6 –92 –94 153.6 307.2 –81 –87 54 DetailedDescription Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 www.ti.com SWRS046H–NOVEMBER2006–REVISEDMARCH2015 5.16 Crystal Oscillator The recommended crystal frequency is 14.7456 MHz, but any crystal frequency in the range 4 to 20 MHz can be used. Using a crystal frequency different from 14.7456 MHz might in some applications give degraded performance. Refer to AN022 Crystal Frequency Selection (SWRA070) for more details on the use of other crystal frequencies than 14.7456 MHz. The crystal frequency is used as reference for the data rate (as well as other internal functions) and in the 4 to 20 MHz range the frequencies 4.9152, 7.3728, 9.8304, 12.2880, 14.7456, 17.2032, 19.6608 MHz will give accurate data rates (as shown in Table 5-4) and an IF frequency of 307.2 kHz. The crystal frequency will influence the programming of the CLOCK_A,CLOCK_BandMODEMregisters. An external clock signal or the internal crystal oscillator can be used as main frequency reference. An external clock signal should be connected to XOSC_Q1, while XOSC_Q2 should be left open. The XOSC_BYPASS bit in the INTERFACE register should be set to ‘1’ when an external digital rail-to-rail clock signal is used. No DC block should be used then. A sine with smaller amplitude can also be used. A DC blocking capacitor must then be used (10 nF) and the XOSC_BYPASS bit in the INTERFACE register shouldbesetto‘0’.Forinputsignalamplitude,seeSection4.8. Using the internal crystal oscillator, the crystal must be connected between the XOSC_Q1 and XOSC_Q2 pins. The oscillator is designed for parallel mode operation of the crystal. In addition, loading capacitors (C4 and C5) for the crystal are required. The loading capacitor values depend on the total load capacitance, CL, specified for the crystal. The total load capacitance seen between the crystal terminals shouldequalCLforthecrystaltooscillateatthespecifiedfrequency. 1 C = + C L 1 1 parasitic + C C 4 5 (33) The parasitic capacitance is constituted by pin input capacitance and PCB stray capacitance. Total parasitic capacitance is typically 8 pF. A trimming capacitor may be placed across C5 for initial tuning if necessary. The crystal oscillator circuit is shown in Figure 5-30. Typical component values for different values of C L aregiveninTable5-15. The crystal oscillator is amplitude regulated. This means that a high current is required to initiate the oscillations. When the amplitude builds up, the current is reduced to what is necessary to maintain approximately 600 mVpp amplitude. This ensures a fast start-up, keeps the drive level to a minimum and makes the oscillator insensitive to ESR variations. As long as the recommended load capacitance values areused,theESRisnotcritical. Theinitialtolerance,temperaturedrift,agingandloadpullingshouldbecarefullyspecifiedinordertomeet the required frequency accuracy in a certain application. By specifying the total expected frequency accuracy in SmartRF Studio together with data rate and frequency separation, the software will estimate thetotalbandwidthandcomparetotheavailablereceiverchannelfilterbandwidth.Thesoftwarewillreport anycontradictionsandamoreaccuratecrystalwillberecommendedifrequired. XOSC_Q2 XOSC_Q1 XTAL C4 C5 Figure5-30.CrystalOscillatorCircuit Copyright©2006–2015,TexasInstrumentsIncorporated DetailedDescription 55 SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 SWRS046H–NOVEMBER2006–REVISEDMARCH2015 www.ti.com Table5-15.CrystalOscillatorComponentValues ITEM C =12pF C =16pF C =22pF L L L C4 6.8pF 15pF 27pF C5 6.8pF 15pF 27pF 5.17 Built-in Test Pattern Generator The CC1020 has a built-in test pattern generator that generates a PN9 pseudo random sequence. The PN9_ENABLE bit in the MODEM register enables the PN9 generator. A transition on the DIO pin is requiredafterenablingthePN9pseudorandomsequence. ThePN9pseudorandomsequenceisdefinedbythepolynomialx9+x5+1. The PN9 sequence is ‘XOR’ed with the DIO signal in both TX and RX mode as shown in Figure 5-31. Hence, by transmitting only zeros (DIO = 0), the BER (Bit Error Rate) can be tested by counting the number of received ones. Note that the 9 first received bits should be discarded in this case. Also note thatonebiterrorwillgenerate3receivedones. Transmittingonlyones(DIO=1),theBERcanbetestedbycountingthenumberofreceivedzeroes. The PN9 generator can also be used for transmission of ‘real-life’ data when measuring narrowband ACP (AdjacentChannelPower),modulationbandwidthoroccupiedbandwidth. Tx pseudo random sequence Tx out (modulating signal) Tx data (DIO pin) XOR 8 7 6 5 4 3 2 1 0 XOR Rx pseudo random sequence Rx in (Demodulated Rx data) 8 7 6 5 4 3 2 1 0 XOR XOR Rx out (DIO pin) Figure5-31.PN9Pseudo-randomSequenceGeneratorinTXandRXMode 5.18 Interrupt on Pin DCLK 5.18.1 Interrupt Upon PLL Lock In synchronous mode the DCLK pin on CC1020 can be used to give an interrupt signal to wake the microcontrollerwhenthePLLislocked. 56 DetailedDescription Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 www.ti.com SWRS046H–NOVEMBER2006–REVISEDMARCH2015 PD_MODE[1:0]intheMAINregistershouldbesetto01.IfDCLK_LOCKintheINTERFACEregisterisset to 1 the DCLK signal is always logic high if the PLL is not in lock. When the PLL locks to the desired frequency the DCLK signal changes to logic 0. When this interrupt has been detected write PD_MODE[1:0]=00.ThiswillenabletheDCLKsignal. ThisfunctioncanbeusedtowaitforthePLLtobelockedbeforethePAisrampedupintransmitmode.In receivemode,itcanbeusedtowaituntilthePLLislockedbeforesearchingforpreamble. 5.18.2 Interrupt Upon Received Signal Carrier Sense In synchronous mode the DCLK pin on CC1020 can also be used to give an interrupt signal to the microcontroller when the RSSI level exceeds a certain threshold (carrier sense threshold). This function canbeusedtowakeorinterruptthemicrocontrollerwhenastrongsignalisreceived. GatingtheDCLKsignalwiththecarriersensesignalmakestheinterruptsignal. This function should only be used in receive mode and is enabled by setting DCLK_CS = 1 in the INTERFACEregister. The DCLK signal is always logic high unless carrier sense is indicated. When carrier sense is indicated the DCLK starts running. When gating the DCLK signal with the carrier sense signal at least 2 dummy bits should be added after the data payload in TX mode. The reason being that the carrier sense signal is generated earlier in the receive chain (that is, before the demodulator), causing it to be updated 2 bits beforethecorrespondingdataisavailableontheDIOpin. In transmit mode DCLK_CS must be set to 0. Refer to CC1020 Errata Note 002, available in the CC1020 productfolder. 5.19 PA_EN and LNA_EN Digital Output Pins 5.19.1 Interfacing an External LNA or PA CC1020 has two digital output pins, PA_EN and LNA_EN, which can be used to control an external LNA or PA. The functionality of these pins are controlled through the INTERFACE register. The outputs can alsobeusedasgeneraldigitaloutputcontrolsignals. EXT_PA_POLandEXT_LNA_POLcontroltheactivepolarityofthesignals. EXT_PA and EXT_LNA control the function of the pins. If EXT_PA = 1, then the PA_EN pin will be activated when the internal PA is turned on. Otherwise, the EXT_PA_POL bit controls the PA_EN pin directly. If EXT_LNA = 1, then the LNA_EN pin will be activated when the internal LNA is turned on. Otherwise,theEXT_LNA_POLbitcontrolstheLNA_ENpindirectly. These two pins can therefore also be used as two general control signals, see Section 5.19.2. In the TI referencedesignLNA_ENandPA_ENareusedtocontroltheexternalT/Rswitch. 5.19.2 General Purpose Output Control Pins The two digital output pins, PA_EN and LNA_EN, can be used as two general control signals by setting EXT_PA=0andEXT_LNA=0.TheoutputvalueisthensetdirectlybythevaluewrittentoEXT_PA_POL andEXT_LNA_POL. The LOCK pin can also be used as a general-purpose output pin. The LOCK pin is controlled by LOCK_SELECT[3:0] in the LOCK register. The LOCK pin is low when LOCK_SELECT[3:0] = 0000, and highwhenLOCK_SELECT[3:0]=0001. These features can be used to save I/O pins on the microcontroller when the other functions associated withthesepinsarenotused. Copyright©2006–2015,TexasInstrumentsIncorporated DetailedDescription 57 SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 SWRS046H–NOVEMBER2006–REVISEDMARCH2015 www.ti.com 5.19.3 PA_EN and LNA_EN Pin Drive Figure 5-32 shows the PA_EN and LNA_EN pin drive currents. The sink and source currents have oppositesignsbutabsolutevaluesareusedinFigure5-32. 1400 1200 1000 A] u 800 [ nt e rr 600 u C 400 200 0 0 2 4 6 8 1 2 4 6 8 2 2 4 6 8 3 2 4 6 0. 0. 0. 0. 1. 1. 1. 1. 2. 2. 2. 2. 3. 3. 3. VoltageonPA_EN/LNA_ENpin[V] sourcecurrent,3V sinkcurrent,3V sourcecurrent,2.3V sinkcurrent,2.3V sourcecurrent,3.6V sinkcurrent,3.6V Figure5-32.TypicalPA_ENandLNA_ENPinDrive 5.20 System Considerations and Guidelines 5.20.1 SRD Regulations International regulations and national laws regulate the use of radio receivers and transmitters. SRDs (Short Range Devices) for license free operation are allowed to operate in the 433 and 868 to 870 MHz bands in most European countries. In the United States, such devices operate in the 260 to 470 and 902 to 928 MHz bands. CC1020 is also applicable for use in the 950 to 960 MHz frequency band in Japan. A summary of the most important aspects of these regulations can be found in AN001 SRD Regulations For LicenseFreeTransceiverOperation(SWRA090). 5.20.2 Narrowband Systems CC1020 is specifically designed for narrowband systems complying with ARIB STD-T67 and EN 300 220. The CC1020 meets the strict requirements to ACP (Adjacent Channel Power) and occupied bandwidth for a narrowband transmitter. To meet the ARIB STD-T67 requirements, a 3.0 V regulated voltage supply shouldbeused. For the receiver side, CC1020 gives very good ACR (Adjacent Channel Rejection), image frequency suppressionandblockingpropertiesforchannelspacingsdownto12.5kHz. Such narrowband performance normally requires the use of external ceramic filters. The CC1020 provides thisperformanceasatruesingle-chipsolutionwithintegratedIFfilters. Japan and Korea have allocated several frequency bands at 424, 426, 429, 447, 449 and 469 MHz for narrowbandlicensefreeoperation.CC1020isdesignedtomeettherequirementsforoperationinallthese bands,includingthestrictrequirementsfornarrowbandoperationdownto12.5kHzchannelspacing. Due to on-chip complex filtering, the image frequency is removed. An on-chip calibration circuit is used to get the best possible image rejection. A narrowband preselector filter is not necessary to achieve image rejection. 58 DetailedDescription Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 www.ti.com SWRS046H–NOVEMBER2006–REVISEDMARCH2015 A unique feature in CC1020 is the very fine frequency resolution. This can be used for temperature compensationofthecrystalifthetemperaturedriftcurveisknownandatemperaturesensorisincludedin the system. Even initial adjustment can be performed using the frequency programmability. This eliminates the need for an expensive TCXO and trimming in some applications. For more details refer to AN027TemperatureCompensationbyIndirectMethod(SWRA065). In less demanding applications, a crystal with low temperature drift and low aging could be used without furthercompensation.Atrimmercapacitorinthecrystaloscillatorcircuit(inparallelwithC5)couldbeused tosettheinitialfrequencyaccurately. The frequency offset between a transmitter and receiver is measured in the CC1020 and can be read back from the AFC register. The measured frequency offset can be used to calibrate the receiver frequencyusingthetransmitterasthereference.Formoredetailsreferto AN029CC1020/1021Automatic FrequencyControl(AFC) (SWRA063). CC1020 also has the possibility to use Gaussian shaped FSK (GFSK). This spectrum-shaping feature improves adjacent channel power (ACP) and occupied bandwidth. In ‘true’ FSK systems with abrupt frequency shifting, the spectrum is inherently broad. By making the frequency shift ‘softer’, the spectrum can be made significantly narrower. Thus, higher data rates can be transmitted in the same bandwidth usingGFSK. 5.20.3 Low Cost Systems As the CC1020 provides true narrowband multi-channel performance without any external filters, a very low cost high performance system can be achieved. The oscillator crystal can then be a low cost crystal with50ppmfrequencytoleranceusingtheon-chipfrequencytuningpossibilities. 5.20.4 Battery Operated Systems In low power applications, the power down mode should be used when CC1020 is not being active. Depending on the start-up time requirement, the oscillator core can be powered during power down. See Section5.14 forinformationonhoweffectivepowermanagementcanbeimplemented. 5.20.5 High Reliability Systems Using a SAW filter as a preselector will improve the communication reliability in harsh environments by reducing the probability of blocking. The receiver sensitivity and the output power will be reduced due to the filter insertion loss. By inserting the filter in the RX path only, together with an external RX/TX switch, only the receiver sensitivity is reduced and output power is remained. The PA_EN and LNA_EN pin can be configured to control an external LNA, RX/TX switch or power amplifier. This is controlled by the INTERFACEregister. Copyright©2006–2015,TexasInstrumentsIncorporated DetailedDescription 59 SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 SWRS046H–NOVEMBER2006–REVISEDMARCH2015 www.ti.com 5.20.6 Frequency Hopping Spread Spectrum Systems (FHSS) Due to the very fast locking properties of the PLL, the CC1020 is also very suitable for frequency hopping systems. Hop rates of 1to100 hops/s are commonly used depending on the bit rate and the amount of data to be sent during each transmission. The two frequency registers (FREQ_A and FREQ_B) are designed such that the ‘next’ frequency can be programmed while the ‘present’ frequency is used. The switching between the two frequencies is done through the MAIN register. Several features have been included to do the hopping without a need to re-synchronize the receiver. For more details, refer to ApplicationNoteAN014FrequencyHoppingSystems(SWRA077). InordertoimplementafrequencyhoppingsystemwithCC1020dothefollowing: Setthedesiredfrequency,calibrateandstorethefollowingregistersettingsinnon-volatilememory: STATUS1[3:0]: CHP_CURRENT[3:0] STATUS2[4:0]: VCO_ARRAY[4:0] TEST1[3:0]: CHP_CO[3:0] STATUS3[5:0]:VCO_CAL_CURRENT[5:0] Repeat the calibration for each desired frequency. VCO_CAL_CURRENT[5:0] is not dependent on the RF frequencyandthesamevaluecanbeusedforallfrequencies. When performing frequency hopping, write the stored values to the corresponding TEST1, TEST2 and TEST3registers,andenableoverride: TEST2[4:0]: VCO_AO[4:0] TEST2[5]: VCO_OVERRIDE TEST2[6]: CHP_OVERRIDE TEST3[5:0]: VCO_CO[5:0] TEST3[6]: VCO_CAL_OVERRIDE CHP_CO[3:0] is the register setting read from CHP_CURRENT[3:0], VCO_AO[4:0] is the register setting read from VCO_ARRAY[4:0] and VCO_CO[5:0] is the register setting read from VCO_CAL_CURRENT[5:0]. Assume channel 1 defined by register FREQ_A is currently being used and that CC1020 should operate on channel 2 next (to change channel simply write to register MAIN[6]). The channel 2 frequency can be set by register FREQ_B which can be written to while operating on channel 1. The calibration data must be written to the TEST1-3 registers after switching to the next frequency. That is, when hopping to a new channel write to register MAIN[6] first and the test registers next. The PA should be switched off between each hop and the PLL should be checked for lock before switching the PA back on after a hop has been performed. NOTE The override bits VCO_OVERRIDE, CHP_OVERRIDE and VCO_CAL_OVERRIDE must be disabledwhenperformingare-calibration. 60 DetailedDescription Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 www.ti.com SWRS046H–NOVEMBER2006–REVISEDMARCH2015 5.21 Antenna Considerations CC1020 can be used together with various types of antennas. The most common antennas for short- rangecommunicationaremonopole,helicalandloopantennas. Monopole antennas are resonant antennas with a length corresponding to one quarter of the electrical l wavelength ( 4 ). They are very easy to design and can be implemented simply as a “piece of wire” or evenintegratedontothePCB. l Non-resonant monopole antennas shorter than 4 can also be used, but at the expense of range. In size andcostcriticalapplicationssuchanantennamayverywellbeintegratedontothePCB. Helical antennas can be thought of as a combination of a monopole and a loop antenna. They are a good compromise in size critical applications. But helical antennas tend to be more difficult to optimize than the simplemonopole. Loop antennas are easy to integrate into the PCB, but are less effective due to difficult impedance matchingbecauseoftheirverylowradiationresistance. l For low power applications the 4 monopole antenna is recommended due to its simplicity as well as providingthebestrange. l Thelengthofthe 4 monopoleantennaisgivenbyEquation34. 7125 L = f (34) Where: fisinMHz,givingthelengthincm. Anantennafor868MHzshouldbe8.2cm,and16.4cmfor433MHz. The antenna should be connected as close as possible to the IC. If the antenna is located away from the inputpintheantennashouldbematchedtothefeedingtransmissionline(50 Ω). Foramorethoroughbackgroundonantennas,pleaserefertoAN003SRDAntennas (SWRA088). Copyright©2006–2015,TexasInstrumentsIncorporated DetailedDescription 61 SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 SWRS046H–NOVEMBER2006–REVISEDMARCH2015 www.ti.com 5.22 Configuration Registers The configuration of CC1020 is done by programming the 8-bit configuration registers. The configuration data based on selected system parameters are most easily found by using the SmartRF Studio software. Complete descriptions of the registers are given in Section 5.22.1. After a RESET is programmed, all the registers have default values. The TEST registers also get default values after a RESET, and should not bealteredbytheuser. TI recommends using the register settings found using the SmartRF Studio software. These are the register settings that TI specifies across temperature, voltage, and process. Check the TI web site for regularlyupdatestotheSmartRFStudiosoftware. Table5-16.CC1020RegisterOverview ADDRESS ACRONYM REGISTERNAME 00h MAIN Maincontrolregister 01h INTERFACE Interfacecontrolregister 02h RESET Digitalmoduleresetregister 03h SEQUENCING Automaticpower-upsequencingcontrolregister 04h FREQ_2A Frequencyregister2A 05h FREQ_1A Frequencyregister1A 06h FREQ_0A Frequencyregister0A 07h CLOCK_A ClockgenerationregisterA 08h FREQ_2B Frequencyregister2B 09h FREQ_1B Frequencyregister1B 0Ah FREQ_0B Frequencyregister0B 0Bh CLOCK_B ClockgenerationregisterB 0Ch VCO VCOcurrentcontrolregister 0Dh MODEM Modemcontrolregister 0Eh DEVIATION TXfrequencydeviationregister 0Fh AFC_CONTROL RXAFCcontrolregister 10h FILTER Channelfilter/RSSIcontrolregister 11h VGA1 VGAcontrolregister1 12h VGA2 VGAcontrolregister2 13h VGA3 VGAcontrolregister3 14h VGA4 VGAcontrolregister4 15h LOCK Lockcontrolregister 16h FRONTEND Frontendbiascurrentcontrolregister 17h ANALOG Analogmodulescontrolregister 18h BUFF_SWING LObufferandprescalerswingcontrolregister 19h BUFF_CURRENT LObufferandprescalerbiascurrentcontrolregister 1Ah PLL_BW PLLloopbandwidth/chargepumpcurrentcontrolregister 1Bh CALIBRATE PLLcalibrationcontrolregister 1Ch PA_POWER Poweramplifieroutputpowerregister Matchcapacitorarraycontrolregister,forRXandTXimpedance 1Dh MATCH matching 1Eh PHASE_COMP PhaseerrorcompensationcontrolregisterforLOI/Q 1Fh GAIN_COMP GainerrorcompensationcontrolregisterformixerI/Q 20h POWERDOWN Power-downcontrolregister 21h TEST1 TestregisterforoverridingPLLcalibration 22h TEST2 TestregisterforoverridingPLLcalibration 23h TEST3 TestregisterforoverridingPLLcalibration 24h TEST4 TestregisterforchargepumpandIFchaintesting 62 DetailedDescription Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 www.ti.com SWRS046H–NOVEMBER2006–REVISEDMARCH2015 Table5-16.CC1020RegisterOverview(continued) ADDRESS ACRONYM REGISTERNAME 25h TEST5 TestregisterforADCtesting 26h TEST6 TestregisterforVGAtesting 27h TEST7 TestregisterforVGAtesting Statusinformationregister(PLLlock,RSSI,calibrationready,and 40h STATUS soon) 41h RESET_DONE Statusregisterfordigitalmodulereset 42h RSSI Receivedsignalstrengthregister AveragereceivedfrequencydeviationfromIF(canbeusedfor 43h AFC AFC) 44h GAUSS_FILTER DigitalFMdemodulatorregister 45h STATUS1 StatusofPLLcalibrationresultsandsoon(testonly) 46h STATUS2 StatusofPLLcalibrationresultsandsoon(testonly) 47h STATUS3 StatusofPLLcalibrationresultsandsoon(testonly) 48h STATUS4 StatusofADCsignals(testonly) 49h STATUS5 Statusofchannelfilter“I”signal(testonly) 4Ah STATUS6 Statusofchannelfilter“Q”signal(testonly) 4Bh STATUS7 StatusofAGC(testonly) 5.22.1 Memory Table5-17.MAINRegister(00h) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE MAIN[7] RXTX — — RX/TXswitch,0:RX,1:TX MAIN[6] F_REG — — SelectionofFrequencyRegister,0:RegisterA,1:RegisterB MAIN[5:4] PD_MODE[1:0] — — Powerdownmode 0(00):ReceiveChaininpower-downinTX,PAinpower-downin RX 1(01):ReceiveChainandPAinpowerdowninbothTXandRX 2 (10): Individual modules can be put in power down by programmingthePOWERDOWNregister 3(11):Automaticpower-upsequencingisactivated (seeTable5-18) MAIN[3] FS_PD — H PowerDownofFrequencySynthesizer MAIN[2] XOSC_PD — H PowerDownofCrystalOscillatorCore MAIN[1] BIAS_PD — H PowerDownofBIAS(GlobalCurrentGenerator)andCrystalOscillator Buffer MAIN[0] RESET_N — L Reset,activelow.WritingRESET_Nlowwillwritedefaultvaluestoall otherregistersthanMAIN.BitsinMAINdonothaveadefaultvalue andwillbewrittendirectlythroughtheconfigurationinterface.Mustbe sethightocompletereset. Table5-18.MAINRegister(00h)WhenUsingAutomaticPower-upSequencing (RXTX=0,PD_MODE[1:0]=11) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE MAIN[7] RXTX — — Automaticpower-upsequencingonlyworksinRX(RXTX=0) MAIN[6] F_REG — — SelectionofFrequencyRegister,0:RegisterA,1:RegisterB MAIN[5:4] PD_MODE[1:0] — H SetPD_MODE[1:0]=3(11)toenablesequencing Copyright©2006–2015,TexasInstrumentsIncorporated DetailedDescription 63 SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 SWRS046H–NOVEMBER2006–REVISEDMARCH2015 www.ti.com Table5-18.MAINRegister(00h)WhenUsingAutomaticPower-upSequencing (RXTX=0,PD_MODE[1:0]=11)(continued) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE MAIN[3:2] SEQ_CAL[1:0] — — ControlsPLLcalibrationbeforere-enteringpowerdown 0:NeverperformPLLcalibrationaspartofsequence 1:AlwaysperformPLLcalibrationatendofsequence 2:PerformPLLcalibrationatendofevery16thsequence 3:PerformPLLcalibrationatendofevery256thsequence MAIN[1] SEQ_PD — ↑ ↑1:Putthechipinpowerdownandwaitforstartofnewpower-up sequence MAIN[0] RESET_N — L Reset,activelow.WritingRESET_Nlowwillwritedefaultvaluestoall otherregistersthanMAIN.BitsinMAINdonothaveadefaultvalue andwillbewrittendirectlythroughtheconfigurationinterface.Mustbe sethightocompletereset. Table5-19.INTERFACERegister(01h)(1) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE INTERFACE[7] XOSC_BYPASS 0 H Bypassinternalcrystaloscillator,useexternalclock 0: Internal crystal oscillator is used, or external sine wave fed throughacouplingcapacitor 1:Internalcrystaloscillatorinpowerdown,externalclockwithrail- to-railswingisused INTERFACE[6] SEP_DI_DO 0 H UseseparatepinforRXdataoutput 0: DIO is data output in RX and data input in TX. LOCK pin is available(Normaloperation). 1: DIO is always input, and a separate pin is used for RX data output(synchronousmode:LOCKpin,asynchronousmode:DCLK pin). If SEP_DI_DO=1 and SEQ_PSEL=0 in SEQUENCING register then negativetransitionsonDIOisusedtostartpower-upsequencingwhen PD_MODE=3(power-upsequencingisenabled). INTERFACE[5] DCLK_LOCK 0 H GateDCLKsignalwithPLLlocksignalinsynchronousmode OnlyapplieswhenPD_MODE="01" 0:DCLKisalways1 1:DCLKisalways1unlessPLLisinlock INTERFACE[4] DCLK_CS 0 H GateDCLKsignalwithcarriersenseindicatorinsynchronousmode Usewhenreceivechainisactive(inpowerup) Alwayssetto0inTXmode. 0:DCLKisindependentofcarriersenseindicator. 1:DCLKisalways1unlesscarriersenseisindicated INTERFACE[3] EXT_PA 0 H UsePA_ENpintocontrolexternalPA 0:PA_ENpinalwaysequalsEXT_PA_POLbit 1:PA_ENpinisassertedwheninternalPAisturnedon INTERFACE[2] EXT_LNA 0 H UseLNA_ENpintocontrolexternalLNA 0:LNA_ENpinalwaysequalsEXT_LNA_POLbit 1:LNA_ENpinisassertedwheninternalLNAisturnedon INTERFACE[1] EXT_PA_POL 0 H PolarityofexternalPAcontrol 0:PA_ENpinis"0"whenactivatingexternalPA 1:PA_ENpinis“1”whenactivatingexternalPA INTERFACE[0] EXT_LNA_POL 0 H PolarityofexternalLNAcontrol 0:LNA_ENpinis“0”whenactivatingexternalLNA 1:LNA_ENpinis“1”whenactivatingexternalLNA (1) IfTF_ENABLE=1orTA_ENABLE=1inTEST4register,thenINTERFACE[3:0]controlsanalogtestmodule:INTERFACE[3]=TEST_PD, INTERFACE[2:0]=TEST_MODE[2:0].Otherwise,TEST_PD=1andTEST_MODE[2:0]=001. 64 DetailedDescription Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 www.ti.com SWRS046H–NOVEMBER2006–REVISEDMARCH2015 Table5-20.RESETRegister(02h)(1)(2) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE RESET[7] ADC_RESET_N 0 L ResetADCcontrollogic RESET[6] AGC_RESET_N 0 L ResetAGC(VGAcontrol)logic RESET[5] GAUSS_RESET_N 0 L ResetGaussiandatafilter RESET[4] AFC_RESET_N 0 L ResetAFC/FSKdecisionlevellogic RESET[3] BITSYNC_RESET_N 0 L Resetmodulator,bitsynchronizationlogicandPN9PRBSgenerator RESET[2] SYNTH_RESET_N 0 L Resetdigitalpartoffrequencysynthesizer RESET[1] SEQ_RESET_N 0 L Resetpower-upsequencinglogic RESET[0] CAL_LOCK_RESET_N 0 L Resetcalibrationlogicandlockdetector (1) ForresetofCC1020writeRESET_N=0intheMAINregister.Theresetregistershouldnotbeusedduringnormaloperation. (2) BitsintheRESETregisterareself-clearing(willbesetto1whentheresetoperationstarts).Relevantdigitalclocksmustberunningfor theresettingtocomplete.AfterwritingtotheRESETregister,theusershouldverifythatallresetoperationshavebeencompleted,by readingtheRESET_DONEstatusregister(41h)untilallbitsequal1. Table5-21.SEQUENCINGRegister(03h) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE SEQUENCING[7] SEQ_PSEL 1 H UsePSELpintostartsequencing 0:PSELpindoesnotstartsequencing.Negativetransitionson DIOstartspower-upsequencingifSEP_DI_DO=1. 1: Negative transitions on the PSEL pin will start power-up sequencing SEQUENCING[6:4] RX_WAIT[2:0] 0 — WaitingtimefromPLLenterslockuntilRXpowerup 0:Waitforapprox.32ADC_CLKperiods(26μs) 1:Waitforapprox.44ADC_CLKperiods(36μs) 2:Waitforapprox.64ADC_CLKperiods(52μs) 3:Waitforapprox.88ADC_CLKperiods(72μs) 4:Waitforapprox.128ADC_CLKperiods(104μs) 5:Waitforapprox.176ADC_CLKperiods(143μs) 6:Waitforapprox.256ADC_CLKperiods(208μs) 7:NoadditionalwaitingtimebeforeRXpowerup SEQUENCING[3:0] CS_WAIT[3:0] 10 — WaitingtimeforcarriersensefromRXpowerup 0:Wait20FILTER_CLKperiodsbeforepowerdown1:Wait22 FILTER_CLKperiodsbeforepowerdown 2: Wait 24 FILTER_CLK periods before power down 3:Wait26FILTER_CLKperiodsbeforepowerdown 4:Wait28FILTER_CLKperiodsbeforepowerdown 5:Wait30FILTER_CLKperiodsbeforepowerdown 6:Wait32FILTER_CLKperiodsbeforepowerdown 7:Wait36FILTER_CLKperiodsbeforepowerdown 8:Wait40FILTER_CLKperiodsbeforepowerdown 9:Wait44FILTER_CLKperiodsbeforepowerdown 10:Wait48FILTER_CLKperiodsbeforepowerdown 11:Wait52FILTER_CLKperiodsbeforepowerdown 12:Wait56FILTER_CLKperiodsbeforepowerdown 13:Wait60FILTER_CLKperiodsbeforepowerdown 14:Wait64FILTER_CLKperiodsbeforepowerdown 15:Wait72FILTER_CLKperiodsbeforepowerdown Table5-22.FREQ_2ARegister(04h) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE FREQ_2A[7:0] FREQ_A[22:15] 131 — 8MSBoffrequencycontrolwordA Copyright©2006–2015,TexasInstrumentsIncorporated DetailedDescription 65 SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 SWRS046H–NOVEMBER2006–REVISEDMARCH2015 www.ti.com Table5-23.FREQ_1ARegister(05h) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE FREQ_1A[7:0] FREQ_1A[7:0] 177 — Bit15to8offrequencycontrolwordA Table5-24.FREQ_0ARegister(06h) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE FREQ_0A[7:1] FREQ_A[6:0] 124 — 7LSBoffrequencycontrolwordA FREQ_0A[0] DITHER_A 1 H EnableditheringforfrequencyA Table5-25.CLOCK_ARegister(07h) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE CLOCK_A[7:5] REF_DIV_A[2:0] 2 — Referencefrequencydivisor(A): 0:Notsupported 1:REF_CLKfrequency=Crystalfrequency/2 … 7:REF_CLKfrequency=Crystalfrequency/8 It is recommended to use the highest possible reference clock frequencythatallowsthedesiredBaudrate. CLOCK_A[4:2] MCLK_DIV1_A[2:0] 4 — Modemclockdivider1(A): 0:Divideby2.5 1:Divideby3 2:Divideby4 3:Divideby7.5(2.5×3) 4:Divideby12.5(2.5×5) 5:Divideby40(2.5×16) 6:Divideby48(3×16) 7:Divideby64(4×16) CLOCK_A[1:0] MCLK_DIV2_A[1:0] 0 — Modemclockdivider2(A): 0:Divideby1 1:Divideby2 2:Divideby4 3:Divideby8 MODEM_CLK frequencyis FREFfrequencydividedby theproductof divider1anddivider2. BaudrateisMODEM_CLKfrequencydividedby8. Table5-26.FREQ_2BRegister(08h) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE FREQ_2B[7:0] FREQ_B[22:15] 131 — 8MSBoffrequencycontrolwordB Table5-27.FREQ_1BRegister(09h) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE FREQ_1B[7:0] FREQ_B[14:7] 189 — 8MSBoffrequencycontrolwordB 66 DetailedDescription Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 www.ti.com SWRS046H–NOVEMBER2006–REVISEDMARCH2015 Table5-28.FREQ_0BRegister(0Ah) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE FREQ_0B[7:1] FREQ_B[6:0] 124 — 7LSBoffrequencycontrolwordB FREQ_0B[0] DITHER_B 1 H EnableditheringforfrequencyB Table5-29.CLOCK_BRegister(0Bh) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE CLOCK_B[7:5] REF_DIV_B[2:0] 2 — Referencefrequencydivisor(B): 0:Notsupported 1:REF_CLKfrequency=Crystalfrequency/2 … 7:REF_CLKfrequency=Crystalfrequency/8 CLOCK_B[4:2] MCLK_DIV1_B[2:0] 4 — Modemclockdivider1(B): 0:Divideby2.5 1:Divideby3 2:Divideby4 3:Divideby7.5(2.5×3) 4:Divideby12.5(2.5×5) 5:Divideby40(2.5×16) 6:Divideby48(3×16) 7:Divideby64(4×16) CLOCK_B[1:0] MCLK_DIV2_B[1:0] 0 — Modemclockdivider2(B): 0:Divideby1 1:Divideby2 2:Divideby4 3:Divideby8 MODEM_CLK frequencyis FREFfrequencydividedby theproductof divider1anddivider2. BaudrateisMODEM_CLKfrequencydividedby8. Table5-30.VCORegister(0Ch) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE VCO[7:4] VCO_CURRENT_A[3:0] 8 — ControlofcurrentinVCOcoreforfrequencyA 0:1.4mAcurrentinVCOcore 1:1.8mAcurrentinVCOcore 2:2.1mAcurrentinVCOcore 3:2.5mAcurrentinVCOcore 4:2.8mAcurrentinVCOcore 5:3.2mAcurrentinVCOcore 6:3.5mAcurrentinVCOcore 7:3.9mAcurrentinVCOcore 8:4.2mAcurrentinVCOcore 9:4.6mAcurrentinVCOcore 10:4.9mAcurrentinVCOcore 11:5.3mAcurrentinVCOcore 12:5.6mAcurrentinVCOcore 13:6.0mAcurrentinVCOcore 14:6.4mAcurrentinVCOcore 15:6.7mAcurrentinVCOcore Recommendedsetting:VCO_CURRENT_A=4 VCO[3:0] VCO_CURRENT_B[3:0] 8 — ControlofcurrentinVCOcoreforfrequencyB ThecurrentstepsarethesameasforVCO_CURRENT_A Recommendedsetting:VCO_CURRENT_B=4 Copyright©2006–2015,TexasInstrumentsIncorporated DetailedDescription 67 SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 SWRS046H–NOVEMBER2006–REVISEDMARCH2015 www.ti.com Table5-31.MODEMRegister(0Dh) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE MODEM[7] — 0 — Reserved,write0 MODEM[6:4] ADC_DIV[2:0] 3 — ADCclockdivisor(1) 0:Notsupported 1:ADCfrequency=XOSCfrequency/4 2:ADCfrequency=XOSCfrequency/6 3:ADCfrequency=XOSCfrequency/8 4:ADCfrequency=XOSCfrequency/10 5:ADCfrequency=XOSCfrequency/12 6:ADCfrequency=XOSCfrequency/14 7:ADCfrequency=XOSCfrequency/16 MODEM[3] — 0 — Reserved,write0 MODEM[2] PN9_ENABLE 0 H EnablescramblingofTXandRXwithPN9pseudo-randombit sequence 0:PN9scramblingisdisabled 1:PN9scramblingisenabled(x9+x5+1) ThePN9pseudo-randombitsequencecanbeusedforBERtestingby only transmitting zeros, and then counting the number of received ones. MODEM[1:0] DATA_FORMAT[1:0] 0 — Modemdataformat 0(00):NRZoperation 1(01):Manchesteroperation 2(10):TransparentasynchronousUARToperation,setDCLK=0 3(11):TransparentasynchronousUARToperation,setDCLK=1 (1) Theintermediatefrequencyshouldbeascloseto307.2kHzaspossible.ADCclockfrequencyisalways4timestheintermediate frequencyandshouldthereforebeascloseto1.2288MHzaspossible. Table5-32.DEVIATIONRegister(0Eh) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE DEVIATION[7] TX_SHAPING 1 H EnableGaussianshapingoftransmitteddata Recommendedsetting:TX_SHAPING=1 DEVIATION[6:4] TXDEV_X[2:0] 6 — Transmitfrequencydeviationexponent DEVIATION[3:0] TXDEV_M[3:0] 8 — Transmitfrequencydeviationmantissa Deviationin402to470MHzband: F ×XDEV_M×2(TXDEV_X−16) REF Deviationin804to960MHzband: F ×TXDEV_M×2(TXDEV_X−15) REF On-off-keying(OOK)isusedinRX/TXifTXDEV_M[3:0]=0 TofindTXDEV_MgiventhedeviationandTXDEV_X: TXDEV_M=deviation×2(16−TXDEV_X)/F REF in402to470MHzband, TXDEV_M=deviation×2(15−TXDEV_X)/F REF in804to960MHzband, DecreaseTXDEV_XandtryagainifTXDEV_M<8. IncreaseTXDEV_XandtryagainifTXDEV_M≥16. 68 DetailedDescription Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 www.ti.com SWRS046H–NOVEMBER2006–REVISEDMARCH2015 Table5-33.AFC_CONTROLRegister(0Fh)(1) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE AFC_CONTROL[7:6] SETTLING[1:0] 2 — ControlsAFCsettlingtimeversusaccuracy 0:AFCoff;zeroaveragefrequencyisusedindemodulator 1:Fastestsettling;frequencyaveragedover10/1bitpair 2:Mediumsettling;frequencyaveragedover20/1bitpairs 3:Slowestsettling;frequencyaveragedover40/1bitpairs Recommendedsetting: AFC_CONTROL=3 for higher accuracy unless it is essential to havethefastestsettlingtimewhentransmissionstartsafterRX isactivated. AFC_CONTROL[5:4] RXDEV_X[1:0] 1 — RXfrequencydeviationexponent AFC_CONTROL[3:0] RXDEV_M[3:0] 12 — RXfrequencydeviationmantissa ExpectedRXdeviationshouldbe: Baudrate×RXDEV_M×2(RXDEV_X−3)/3 TofindRXDEV_MgiventhedeviationandRXDEV_X: RXDEV_M=3×deviation×2(3−RXDEV_X)/Baudrate DecreaseRXDEV_XandtryagainifRXDEV_M<8. IncreaseRXDEV_XandtryagainifRXDEV_M≥16. (1) TheRXfrequencydeviationshouldbeclosetohalftheTXfrequencydeviationforGFSKat100kBauddatarateandbelow.TheRX frequencydeviationshouldbeclosetotheTXfrequencydeviationforFSKandforGFSKat100kBauddatarateandabove. Table5-34.FILTERRegister(10h) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE FILTER[7] FILTER_BYPASS 0 H Bypassanalogimagerejection/anti-aliasfilter.Setto1forincreased dynamicrangeathighBaudrates. Recommendedsetting: FILTER_BYPASS=0below76.8kBaud, FILTER_BYPASS=1for76.8kBaudandup. FILTER[6:5] DEC_SHIFT[1:0] 0 — Numberofextrabitstoshiftdecimatorinput(mayimprovefilter accuracyandlowerpowerconsumption). Recommendedsettings: DEC_SHIFT=0whenDEC_DIV≤1 (receiverchannelbandwidth≥153.6kHz), DEC_SHIFT=1whenoptimizedsensitivityand1<DEC_DIV< 24 (12.29kHz<receiverchannelbandwidth<153.6kHz), DEC_SHIFT=2whenoptimizedselectivityandDEC_DIV≥24 (receiverchannelbandwidth≤12.29kHz) FILTER[4:0] DEC_DIV[4:0] 0 — Decimationclockdivisor 0:Decimationclockdivisor=1,307.2kHzchannelfilterBW. 1:Decimationclockdivisor=2,153.6kHzchannelfilterBW. … 30:Decimationclockdivisor=31,9.91kHzchannelfilterBW. 31:Decimationclockdivisor=32,9.6kHzchannelfilterBW. Channelfilter bandwidth is 307.2 kHz dividedby thedecimationclock divisor. Copyright©2006–2015,TexasInstrumentsIncorporated DetailedDescription 69 SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 SWRS046H–NOVEMBER2006–REVISEDMARCH2015 www.ti.com Table5-35.VGA1Register(11h) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE VGA1[7:6] CS_SET[1:0] 1 — Setsthenumberofconsecutivesamplesatorabovecarriersense levelbeforecarriersenseisindicated(forexample,onLOCKpin) 0: Set carrier sense after first sample at or above carrier sense level 1:Setcarriersenseaftersecondsampleatorabovecarriersense level 2: Set carrier sense after third sample at or above carrier sense level 3: Set carrier sense after fourth sample at or above carrier sense level IncreasingCS_SETreducesthenumberof“false”carriersenseevents duetonoiseattheexpenseofincreasedcarriersenseresponsetime. VGA1[5] CS_RESET 1 — Setsthenumberofconsecutivesamplesbelowcarriersenselevel beforecarriersenseindication(forexample,onlockpin)isreset 0:Carriersenseisresetafterfirstsamplebelowcarriersenselevel 1:Carriersenseis reset aftersecondsamplebelow carriersense level Recommendedsetting:CS_RESET=1inordertoreducethechanceof losingcarriersenseduetonoise. VGA1[4:2] VGA_WAIT[2:0] 1 — ControlshowlongAGC,bitsynchronization,AFCandRSSIlevelsare frozenafterVGAgainischangedwhenfrequencyischangedbetween AandBorPLLhasbeenoutoflockorafterRXpowerup 0:Freezeoperationfor16filterclocks,8/(filterBW)seconds 1:Freezeoperationfor20filterclocks,10/(filterBW)seconds 2:Freezeoperationfor24filterclocks,12/(filterBW)seconds 3:Freezeoperationfor28filterclocks,14/(filterBW)seconds 4:Freezeoperationfor32filterclocks,16/(filterBW)seconds 5:Freezeoperationfor40filterclocks,20/(filterBW)seconds 6:Freezeoperationfor48filterclocks,24/(filterBW)seconds 7:Freezepresentlevelsunconditionally VGA1[1:0] VGA_FREEZE[1:0] 1 — ControlstheadditionaltimeAGC,bitsynchronization,AFCandRSSI levelsarefrozenwhenfrequencyischangedbetweenAandBorPLL hasbeenoutoflockorafterRXpowerup 0:Freezelevelsforapprox.16ADC_CLKperiods(13µs) 1:Freezelevelsforapprox.32ADC_CLKperiods(26µs) 2:Freezelevelsforapprox.64ADC_CLKperiods(52µs) 3:Freezelevelsforapprox.128ADC_CLKperiods(104µs) 70 DetailedDescription Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 www.ti.com SWRS046H–NOVEMBER2006–REVISEDMARCH2015 Table5-36.VGA2Register(12h) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE VGA2[7] LNA2_MIN 0 — MinimumLNA2settingusedinVGA 0:MinimumLNA2gain 1:MediumLNA2gain Recommendedsetting:LNA2_MIN=0forbestselectivity. VGA2[6] LNA2_MAX 1 — MaximumLNA2settingusedinVGA 0:MediumLNA2gain 1:MaximumLNA2gain Recommendedsetting:LNA2_MAX=1forbestsensitivity. VGA2[5:4] LNA2_SETTING[1:0] 3 — SelectsatwhatVGAsettingtheLNAgainshouldbechanged 0:ApplyLNA2changebelowmin.VGAsetting. 1: Apply LNA2 change at approx. 1/3 VGA setting (around VGA setting10). 2: Apply LNA2 change at approx. 2/3 VGA setting (around VGA setting19). 3:ApplyLNA2changeabovemax.VGAsetting. Recommendedsetting: LNA2_SETTING=0 if VGA_SETTING<10, LNA2_SETTING=1 otherwise. If LNA2_MIN=1 and LNA2_MAX=0, then the LNA2 setting is controlledbyLNA2_SETTING: 0:BetweenmediumandmaximumLNA2gain 1:MinimumLNA2gain 2:MediumLNA2gain 3:MaximumLNA2gain VGA2[3] AGC_DISABLE 0 H DisableAGC 0:AGCisenabled 1:AGCisdisabled(VGA_SETTINGdeterminesVGAgain) Recommendedsetting:AGC_DISABLE=0forgooddynamicrange. VGA2[2] AGC_HYSTERESIS 1 H EnableAGChysteresis 0: No hysteresis. Immediate gain change for smallest up/down step 1: Hysteresis enabled. Two samples in a row must indicate gain changeforsmallestupordownstep Recommendedsetting:AGC_HYSTERESIS=1. VGA2[1:0] AGC_AVG[1:0] 1 — Setshowmanysamplesthatareusedtocalculateaverageoutput magnitudeforAGC/RSSI. 0:Magnitudeisaveragedover2filteroutputsamples 1:Magnitudeisaveragedover4filteroutputsamples 2:Magnitudeisaveragedover8filteroutputsamples 3:Magnitudeisaveragedover16filteroutputsamples Recommendedsetting:AGC_AVG=1. ForbestAGC/RSSIaccuracyAGC_AVG=3. For automatic power-up sequencing, the AGC_AVG and CS_SET valuesmustbechosensothatcarriersenseisavailableintimetobe detectedbeforethechipre-enterspowerdown. Copyright©2006–2015,TexasInstrumentsIncorporated DetailedDescription 71 SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 SWRS046H–NOVEMBER2006–REVISEDMARCH2015 www.ti.com Table5-37.VGA3Register(13h) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE VGA3[7:5] VGA_DOWN[2:0] 1 — Decideshowmuchthesignalstrengthmustbeabove CS_LEVEL+VGA_UPbeforeVGAgainisdecreased.Basedonthe calculatedinternalstrengthlevel,whichhasanLSBresolutionof1.5 dB. 0: Gain is decreased when level is above CS_LEVEL+ 8 + VGA_UP+3 1: Gain is decreased when level is above CS_LEVEL+ 8 + VGA_UP+4 … 6: Gain is decreased when level is above CS_LEVEL+ 8 + VGA_UP+9 7: Gain is decreased when level is above CS_LEVEL+ 8 + VGA_UP+10 SeeFigure5-15foranexplanationoftherelationshipbetweenRSSI, AGCandcarriersensesettings. VGA3[4:0] VGA_SETTING[4:0] 24 H VGAsettingtobeusedwhenreceivechainisturnedon ThisisalsothemaximumgainthattheAGCisallowedtouse. SeeFigure5-15foranexplanationoftherelationshipbetweenRSSI, AGCandcarriersensesettings. Table5-38.VGA4Register(14h) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE VGA4[7:5] VGA_UP[2:0] 1 — DecidesthelevelwhereVGAgainisincreasedifitisnotalreadyat themaximumsetbyVGA_SETTING.Basedonthecalculatedinternal strengthlevel,whichhasanLSBresolutionof1.5dB. 0:GainisincreasedwhensignalisbelowCS_LEVEL+8 1:GainisincreasedwhensignalisbelowCS_LEVEL+8+1 … 6:GainisincreasedwhensignalisbelowCS_LEVEL+8+6 7:GainisincreasedwhensignalbelowCS_LEVEL+8+7 SeeFigure5-15foranexplanationoftherelationshipbetweenRSSI, AGCandcarriersensesettings. VGA4[4:0] CS_LEVEL[4:0] 24 H ReferencelevelforReceivedSignalStrengthIndication(carriersense level)andAGC. SeeFigure5-15foranexplanationoftherelationshipbetweenRSSI, AGCandcarriersensesettings. 72 DetailedDescription Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 www.ti.com SWRS046H–NOVEMBER2006–REVISEDMARCH2015 Table5-39.LOCKRegister(15h)(1) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE LOCK[7:4] LOCK_SELECT[3:0] 0 — SelectionofsignalstoLOCKpin 0:Setto0 1:Setto1 2:LOCK_CONTINUOUS(activelow) 3:LOCK_INSTANT(activelow) 4:CARRIER_SENSE(RSSIabovethreshold,activelow) 5:CAL_COMPLETE(activelow) 6:SEQ_ERROR(activelow) 7:FXOSC 8:REF_CLK 9:FILTER_CLK 10:DEC_CLK 11:PRE_CLK 12:DS_CLK 13:MODEM_CLK 14:VCO_CAL_COMP 15:F_COMP LOCK[3] WINDOW_WIDTH 0 — Selectslockwindowwidth 0:Lockwindowis2prescalerclockcycleswide 1:Lockwindowis4prescalerclockcycleswide Recommendedsetting:WINDOW_WIDTH=0. LOCK[2] LOCK_MODE 0 — Selectslockdetectormode 0:Counterrestartmode 1:Up/Downcountermode Recommendedsetting:LOCK_MODE=0. LOCK[1:0] LOCK_ACCURACY[1:0] 0 — Selectslockaccuracy(counterthresholdvalues) 0:Declarelockatcountervalue127,outoflockatvalue111 1:Declarelockatcountervalue255,outoflockatvalue239 2:Declarelockatcountervalue511,outoflockatvalue495 3:Declarelockatcountervalue1023,outoflockatvalue1007 (1) SetLOCK_SELECT=2tousetheLOCKpinasalockindicator. Copyright©2006–2015,TexasInstrumentsIncorporated DetailedDescription 73 SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 SWRS046H–NOVEMBER2006–REVISEDMARCH2015 www.ti.com Table5-40.FRONTENDRegister(16h) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE FRONTEND[7:6] LNAMIX_CURRENT[1:0] 2 — ControlscurrentinLNA,LNA2andmixer Recommendedsetting:LNAMIX_CURRENT=1 FRONTEND[5:4] LNA_CURRENT[1:0] 1 — ControlscurrentintheLNA Recommendedsetting:LNA_CURRENT=3. Can be lowered to save power at the expense of reduced sensitivity. FRONTEND[3] MIX_CURRENT 0 — Controlscurrentinthemixer Recommendedsetting: MIX_CURRENT=1at426to464MHz, MIX_CURRENT=0at852to928MHz. FRONTEND[2] LNA2_CURRENT 0 — ControlscurrentinLNA2 Recommendedsettings: LNA2_CURRENT=0at426to464MHz, LNA2_CURRENT=1at852to928MHz. FRONTEND[1] SDC_CURRENT 0 — Controlscurrentinthesingle-to-diff.Converter Recommendedsettings: SDC_CURRENT=0at426to464MHz, SDC_CURRENT=1at852to928MHz. FRONTEND[0] LNAMIX_BIAS 1 — Controlshowfront-endbiascurrentsaregenerated 0:Constantcurrentbiasing 1:ConstantGm×Rbiasing(reducesgainvariation) Recommendedsetting:LNAMIX_BIAS=0. 74 DetailedDescription Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 www.ti.com SWRS046H–NOVEMBER2006–REVISEDMARCH2015 Table5-41.ANALOGRegister(17h) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE ANALOG[7] BANDSELECT 1 — Frequencybandselection 0:402to470MHzband 1:804to960MHzband ANALOG[6] LO_DC 1 — LowerLODCleveltomixers 0:HighLODCleveltomixers 1:LowLODCleveltomixers Recommendedsettings: LO_DC=1for402to470MHz, LO_DC=0for804to960MHz. ANALOG[5] VGA_BLANKING 1 H EnableanalogblankingswitchesinVGAwhenchangingVGA gain. 0:Blankingswitchesaredisabled 1:Blankingswitchesareturnedonforapprox.0.8μswhen gainischanged(alwaysonifAGC_DISABLE=1) Recommendedsetting:VGA_BLANKING=0. ANALOG[4] PD_LONG 0 H Selectsshortorlongresetdelayinphasedetector 0:Shortresetdelay 1:Longresetdelay Recommendedsetting:PD_LONG=0. ANALOG[3] — 0 — Reserved,write0 ANALOG[2] PA_BOOST 0 H BoostPAbiascurrentforhigheroutputpower Recommendedsetting:PA_BOOST=1. ANALOG[1:0] DIV_BUFF_CURRENT[1:0] 3 — OverallbiascurrentadjustmentforVCOdividerandbuffers 0:4/6ofnominalVCOdividerandbuffercurrent 1:4/5ofnominalVCOdividerandbuffercurrent 2:NominalVCOdividerandbuffercurrent 3:4/3ofnominalVCOdividerandbuffercurrent Recommendedsetting:DIV_BUFF_CURRENT=3 Table5-42.BUFF_SWINGRegister(18h) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE BUFF_SWING[7:6] PRE_SWING[1:0] 3 — Prescalerswing. 0:2/3ofnominalswing 1:1/2ofnominalswing 2:4/3ofnominalswing 3:Nominalswing Recommendedsetting:PRE_SWING=0. BUFF_SWING[5:3] RX_SWING[2:0] 4 — LObufferswing,inRX(tomixers) 0:Smallestloadresistance(smallestswing) … 7:Largestloadresistance(largestswing) Recommendedsetting:RX_SWING=2. BUFF_SWING[2:0] TX_SWING[2:0] 1 — LObufferswing,inTX(topoweramplifierdriver) 0:Smallestloadresistance(smallestswing) … 7:Largestloadresistance(largestswing) Recommendedsettings: TX_SWING=4for402to470MHz, TX_SWING=0for804to960MHz. Copyright©2006–2015,TexasInstrumentsIncorporated DetailedDescription 75 SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 SWRS046H–NOVEMBER2006–REVISEDMARCH2015 www.ti.com Table5-43.BUFF_CURRENTRegister(19h) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE BUFF_CURRENT[7:6] PRE_CURRENT[1:0] 1 — Prescalercurrentscaling 0:Nominalcurrent 1:2/3ofnominalcurrent 2:1/2ofnominalcurrent 3:2/5ofnominalcurrent Recommendedsetting:PRE_CURRENT=0. BUFF_CURRENT[5:3] RX_CURRENT[2:0] 4 — LObuffercurrent,inRX(tomixers) 0:Minimumbuffercurrent … 7:Maximumbuffercurrent Recommendedsetting:RX_CURRENT=4. BUFF_CURRENT[2:0] TX_CURRENT[2:0] 5 — LObuffercurrent,inTX(toPAdriver) 0:Minimumbuffercurrent … 7:Maximumbuffercurrent Recommendedsettings: TX_CURRENT=2for402to470MHz, TX_CURRENT=5for804to960MHz. Table5-44.PLL_BWRegister(1Ah) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE PLL_BW[7:0] PLL_BW[7:0] 134 — Chargepumpcurrentscaling/roundingfactor.Usedtocalibratecharge pumpcurrentforthedesiredPLLloopbandwidth. Thevalueisgivenby: PLL_BW=174+16log (f /7.126) 2 ref wheref isthereferencefrequencyinMHz. ref Table5-45.CALIBRATERegister(1Bh) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE CALIBRATE[7] CAL_START 0 ↑ ↑1:Calibrationstarted 0:Calibrationinactive CALIBRATE[6] CAL_DUAL 0 H UsecalibrationresultsforbothfrequencyAandB 0:StoreresultsinAorBdefinedbyF_REG(MAIN[6]) 1:StorecalibrationresultsinbothAandB CALIBRATE[5:4] CAL_WAIT[1:0] 0 — Selectscalibrationwaittime(affectsaccuracy) 0(00):Calibrationtimeisapprox.90000F_REFperiods 1(01):Calibrationtimeisapprox.110000F_REFperiods 2(10):Calibrationtimeisapprox.130000F_REFperiods 3(11):Calibrationtimeisapprox.200000F_REFperiods Recommended setting: CAL_WAIT=3 for best accuracy in calibrated PLLloopfilterbandwidth. CALIBRATE[3] — 0 — Reserved,write0 76 DetailedDescription Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 www.ti.com SWRS046H–NOVEMBER2006–REVISEDMARCH2015 Table5-45.CALIBRATERegister(1Bh)(continued) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE CALIBRATE[2:0] CAL_ITERATE[2:0] 5 — IterationstartvalueforcalibrationDAC 0(000):DACstartvalue1,VC<0.49Vaftercalibration 1(001):DACstartvalue2,VC<0.66Vaftercalibration 2(010):DACstartvalue3,VC<0.82Vaftercalibration 3(011):DACstartvalue4,VC<0.99Vaftercalibration 4(100):DACstartvalue5,VC<1.15Vaftercalibration 5(101):DACstartvalue6,VC<1.32Vaftercalibration 6(110):DACstartvalue7,VC<1.48Vaftercalibration 7(111):DACstartvalue8,VC<1.65Vaftercalibration Recommendedsetting:CAL_ITERATE=4. Table5-46.PA_POWERRegister(1Ch) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE PA_POWER[7:4] PA_HIGH[3:0] 0 — Controlsoutputpowerinhigh-powerarray 0:High-powerarrayisoff 1:Minimumhigh-powerarrayoutputpower … 15:Maximumhigh-powerarrayoutputpower PA_POWER[3:0] PA_LOW[3:0] 15 — Controlsoutputpowerinlow-powerarray 0:Low-powerarrayisoff 1:Minimumlow-powerarrayoutputpower … 15:Maximumlow-powerarrayoutputpower Itismoreefficientintermsofcurrentconsumptiontouseeither thelowerorupper4-bitsinthePA_POWERregistertocontrol thepower. Table5-47.MATCHRegister(1Dh) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE MATCH[7:4] RX_MATCH[3:0] 0 — SelectsmatchingcapacitorarrayvalueforRX.Eachstepis approximately0.4pF. MATCH[3:0] TX_MATCH[3:0] 0 — SelectsmatchingcapacitorarrayvalueforTX. Eachstepisapproximately0.4pF. Table5-48.PHASE_COMPRegister(1Eh) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE PHASE_COMP[7:0] PHASE_COMP[7:0] 0 — SignedcompensationvalueforLOI/Qphaseerror.Usedforimage rejectioncalibration. –128:approx.–6.2°adjustmentbetweenIandQphase –1:approx.–0.02°adjustmentbetweenIandQphase 0:approx.+0.02°adjustmentbetweenIandQphase 127:approx.+6.2°adjustmentbetweenIandQphase Copyright©2006–2015,TexasInstrumentsIncorporated DetailedDescription 77 SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 SWRS046H–NOVEMBER2006–REVISEDMARCH2015 www.ti.com Table5-49.GAIN_COMPRegister(1Fh) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE GAIN_COMP[7:0] GAIN_COMP[7:0] 0 — SignedcompensationvalueformixerI/Qgainerror.Usedforimage rejectioncalibration. –128:approx.–1.16dBadjustmentbetweenIandQgain –1:approx.–0.004dBadjustmentbetweenIandQgain 0:approx.+0.004dBadjustmentbetweenIandQgain 127:approx.+1.16dBadjustmentbetweenIandQgain Table5-50.POWERDOWNRegister(20h) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE POWERDOWN[7] PA_PD 0 H SetsPAinpowerdownwhenPD_MODE[1:0]=2 POWERDOWN[6] VCO_PD 0 H SetsVCOinpowerdownwhenPD_MODE[1:0]=2 POWERDOWN[5] BUFF_PD 0 H SetsVCOdivider,LObuffersandprescalerinpower-downwhen PD_MODE[1:0]=2 POWERDOWN[4] CHP_PD 0 H SetschargepumpinpowerdownwhenPD_MODE[1:0]=2 POWERDOWN[3] LNAMIX_PD 0 H SetsLNA/mixerinpowerdownwhenPD_MODE[1:0]=2 POWERDOWN[2] VGA_PD 0 H SetsVGAinpowerdownwhenPD_MODE[1:0]=2 POWERDOWN[1] FILTER_PD 0 H SetsimagefilterinpowerdownwhenPD_MODE[1:0]=2 POWERDOWN[0] ADC_PD 0 H SetsADCinpowerdownwhenPD_MODE[1:0]=2 Table5-51.TEST1Register(21h,forTestOnly) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE TEST1[7:4] CAL_DAC_OPEN[3:0] 4 — CalibrationDACoverridevalue,activewhenBREAK_LOOP=1 TEST1[3:0] CHP_CO[3:0] 13 — Chargepumpcurrentoverridevalue Table5-52.TEST2Register(22h,forTestOnly) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE TEST2[7] BREAK_LOOP 0 H 0:PLLloopclosed 1:PLLloopopen TEST2[6] CHP_OVERRIDE 0 H 0:usecalibratedvalue 1:useCHP_CO[3:0]value TEST2[5] VCO_OVERRIDE 0 H 0:usecalibratedvalue 1:useVCO_AO[4:0]value TEST2[4:0] VCO_AO[4:0] 16 — VCO_ARRAYoverridevalue Table5-53.TEST3Register(23h,forTestOnly) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE TEST3[7] VCO_CAL_MANUAL 0 H Enables“manual”VCOcalibration(testonly) TEST3[6] VCO_CAL_OVERRIDE 0 H OverrideVCOcurrentcalibration 0:Usecalibratedvalue 1:UseVCO_CO[5:0]value VCO_CAL_OVERRIDEcontrolsVCO_CAL_CLK if VCO_CAL_MANUAL=1. Negative transitions are then used to sampleVCO_CAL_COMP. TEST3[5:0] VCO_CO[5:0] 6 — VCO_CAL_CURRENToverridevalue 78 DetailedDescription Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 www.ti.com SWRS046H–NOVEMBER2006–REVISEDMARCH2015 Table5-54.TEST4Register(24h,forTestOnly)(1) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE TEST4[7] CHP_DISABLE 0 H Disablenormalchargepumpoperation TEST4[6] CHP_TEST_UP 0 H Forcechargepumptooutput“up”current TEST4[5] CHP_TEST_DN 0 H Forcechargepumptooutput“down”current TEST4[4:3] TM_IQ[1:0] 0 — ValueofdifferentialIandQoutputsfrommixerwhenTM_ENABLE=1 0:Ioutputnegative,Qoutputnegative 1:Ioutputnegative,Qoutputpositive 2:Ioutputpositive,Qoutputnegative 3:Ioutputpositive,Qoutputpositive TEST4[2] TM_ENABLE 0 H EnableDCcontrolofmixeroutput(fortesting) TEST4[1] TF_ENABLE 0 H Connectanalogtestmoduletofilterinputs TEST4[0] TA_ENABLE 0 H ConnectanalogtestmoduletoADCinputs (1) IfTF_ENABLE=1orTA_ENABLE=1inTEST4register,thenINTERFACE[3:0]controlsanalogtestmodule:INTERFACE[3]=TEST_PD, INTERFACE[2:0]=TEST_MODE[2:0].Otherwise,TEST_PD=1andTEST_MODE[2]=1. Table5-55.TEST5Register(25h,forTestOnly) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE TEST5[7] F_COMP_ENABLE 0 H EnablefrequencycomparatoroutputF_COMPfromphasedetector TEST5[6] SET_DITHER_CLOCK 1 H Enableditheringofdelta-sigmaclock TEST5[5] ADC_TEST_OUT 0 H OutputsADCsamplesonLOCKandDIO,whileADC_CLKisoutput onDCLK TEST5[4] CHOP_DISABLE 0 H DisablechoppinginADCintegrators TEST5[3] SHAPING_DISABLE 0 H DisableADCfeedbackmismatchshaping TEST5[2] VCM_ROT_DISABLE 0 H DisablerotationforVCMmismatchshaping TEST5[1:0] ADC_ROTATE[1:0] 0 — ControlADCinputrotation 0:Rotatein00011011sequence 1:Rotatein00101101sequence 2:Alwaysuse00position 3:Rotatein00100010sequence Table5-56.TEST6Register(26h,forTestOnly) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE TEST6[7:4] — 0 — Reserved,write0 TEST6[3] VGA_OVERRIDE 0 — OverrideVGAsettings TEST6[2] AC1O 0 — OverridevaluetofirstACcouplerinVGA 0:Approx.0dBgain 1:Approx.–12dBgain TEST6[1:0] AC2O[1:0] 0 — OverridevaluetosecondACcouplerinVGA 0:Approx.0dBgain 1:Approx.–3dBgain 2:Approx.–12dBgain 3:Approx.–15dBgain Copyright©2006–2015,TexasInstrumentsIncorporated DetailedDescription 79 SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 SWRS046H–NOVEMBER2006–REVISEDMARCH2015 www.ti.com Table5-57.TEST7Register(27h,forTestOnly) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE TEST7[7:6] — 0 — Reserved,write0 TEST7[5:4] VGA1O[1:0] 0 — OverridevaluetoVGAstage1 TEST7[3:2] VGA2O[1:0] 0 — OverridevaluetoVGAstage2 TEST7[1:0] VGA3O[1:0] 0 — OverridevaluetoVGAstage3 Table5-58.STATUSRegister(40h,ReadOnly) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE STATUS[7] CAL_COMPLETE — H Setto0whenPLLcalibrationstarts,andsetto1whencalibrationhas finished STATUS[6] SEQ_ERROR — H Setto1whenPLLfailedtolockduringautomaticpower-up sequencing STATUS[5] LOCK_INSTANT — H InstantaneousPLLlockindicator STATUS[4] LOCK_CONTINUOUS — H PLLlockindicator,asdefinedbyLOCK_ACCURACY. Setto1whenPLLisinlock STATUS[3] CARRIER_SENSE — H CarriersensewhenRSSIisaboveCS_LEVEL STATUS[2] LOCK — H LogicallevelonLOCKpin STATUS[1] DCLK — H LogicallevelonDCLKpin STATUS[0] DIO — H LogicallevelonDIOpin Table5-59.RESET_DONERegister(41h,ReadOnly) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE RESET_DONE[7] ADC_RESET_DONE — H ResetofADCcontrollogicdone RESET_DONE[6] AGC_RESET_DONE — H ResetofAGC(VGAcontrol)logicdone RESET_DONE[5] GAUSS_RESET_DONE — H ResetofGaussiandatafilterdone RESET_DONE[4] AFC_RESET_DONE — H ResetofAFC/FSKdecisionlevellogicdone RESET_DONE[3] BITSYNC_RESET_DONE — H Resetofmodulator,bitsynchronizationlogicandPN9 PRBSgeneratordone RESET_DONE[2] SYNTH_RESET_DONE — H Resetdigitalpartoffrequencysynthesizerdone RESET_DONE[1] SEQ_RESET_DONE — H Resetofpower-upsequencinglogicdone RESET_DONE[0] CAL_LOCK_RESET_DONE — H Resetofcalibrationlogicandlockdetectordone Table5-60.RSSIRegister(42h,ReadOnly) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE RSSI[7] — — — Notinuse,willread0 RSSI[6:0] RSSI[6:0] — — Receivedsignalstrengthindicator. TherelativepowerisgivenbyRSSI×1.5dBinalogarithmicscale. TheVGAgainsetbyVGA_SETTINGmustbetakenintoaccount.See Section5.9.5formoredetails. 80 DetailedDescription Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 www.ti.com SWRS046H–NOVEMBER2006–REVISEDMARCH2015 Table5-61.AFCRegister(43h,ReadOnly) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE AFC[7:0] AFC[7:0] — — AveragereceivedfrequencydeviationfromIF.This8-bit2-complement signedvalueequalsthedemodulatordecisionlevelandcanbeused forAFC. TheaveragefrequencyoffsetfromtheIFfrequencyis ΔF=Baudrate×AFC/16 Table5-62.GAUSS_FILTERRegister(44h) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE GAUSS_FILTER[7:0] GAUSS_FILTER[7:0] — — ReadoutofinstantaneousIFfrequencyoffsetfromnominal IF.Signed8-bitvalue. ΔF=Baudrate×GAUSS_FILTER/8 Table5-63.STATUS1Register(45h,forTestOnly) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE STATUS1[7:4] CAL_DAC[3:0] — — StatusvectordefiningappliedCalibrationDACvalue STATUS1[3:0] CHP_CURRENT[3:0] — — StatusvectordefiningappliedCHP_CURRENTvalue Table5-64.STATUS2Register(46h,forTestOnly) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE STATUS2[7:5] CC1020_VERSION[2:0] — — CC1020versioncode: 0:Pre-productionversion 1:Firstproductionversion 2through7:Reservedforfutureuse STATUS2[4:0] VCO_ARRAY[4:0] — — StatusvectordefiningappliedVCO_ARRAYvalue Table5-65.STATUS3Register(47h,forTestOnly) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE STATUS3[7] F_COMP — — Frequencycomparatoroutputfromphasedetector STATUS3[6] VCO_CAL_COMP — — ReadoutofVCOcurrentcalibrationcomparator. Equals 1 if current defined by VCO_CURRENT_A/B is largerthantheVCOcorecurrent STATUS3[5:0] VCO_CAL_CURRENT[5:0] — — StatusvectordefiningappliedVCO_CAL_CURRENTvalue Table5-66.STATUS4Register(48h,forTestOnly) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE STATUS4[7:6] ADC_MIX[1:0] — — ReadoutofmixerinputtoADC STATUS4[5:3] ADC_I[2:0] — — ReadoutofADC“I”output STATUS4[2:0] ADC_Q[2:0] — — ReadoutofADC“Q”output Copyright©2006–2015,TexasInstrumentsIncorporated DetailedDescription 81 SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 SWRS046H–NOVEMBER2006–REVISEDMARCH2015 www.ti.com Table5-67.STATUS5Register(49h,forTestOnly) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE STATUS5[7:0] FILTER_I[7:0] — — Upperbitsof“I”outputfromchannelfilter Table5-68.STATUS6Register(4Ah,forTestOnly) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE STATUS6[7:0] FILTER_Q[7:0] — — Upperbitsof“Q”outputfromchannelfilter Table5-69.STATUS7Register(4Bh,forTestOnly) DEFAULT REGISTER NAME ACTIVE DESCRIPTION VALUE STATUS7[7:5] — — — Notinuse,willread0 STATUS7[4:0] VGA_GAIN_OFFSET[4:0] — — ReadoutofoffsetbetweenVGA_SETTINGandactualVGAgainset byAGC 82 DetailedDescription Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 www.ti.com SWRS046H–NOVEMBER2006–REVISEDMARCH2015 6 Applications, Implementation, and Layout NOTE Information in Section 6 is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementationtoconfirmsystemfunctionality. 6.1 Application Information Very few external components are required for the operation of CC1020. The recommended application circuitisshowninFigure6-1.TheexternalcomponentsaredescribedinTable6-1 andvaluesaregivenin Table6-2. 6.1.1 Typical Application Figure6-1.TypicalApplicationandTestCircuit(PowerSupplyDecouplingNotShown) Copyright©2006–2015,TexasInstrumentsIncorporated Applications,Implementation,andLayout 83 SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 SWRS046H–NOVEMBER2006–REVISEDMARCH2015 www.ti.com Figure6-2.AlternativeApplicationCircuit(PowerSupplyDecouplingNotShown) Table6-1.OverviewofExternalComponents (ExcludingSupplyDecouplingCapacitors) REF DESCRIPTION C1 LNAinputmatchandDCblock,seeSection5.11 C3 PAoutputmatchandDCblock,seeSection5.11 C4 Crystalloadcapacitor,seeSection5.16 C5 Crystalloadcapacitor,seeSection5.16 C6 PLLloopfiltercapacitor PLLloopfiltercapacitor(maybeomittedforhighestloop C7 bandwidth) PLLloopfiltercapacitor(maybeomittedforhighestloop C8 bandwidth) C60 Decouplingcapacitor L1 LNAmatchandDCbias(ground),seeSection5.11 L2 PAmatchandDCbias(supplyvoltage),seeSection5.11 R1 Precisionresistorforcurrentreferencegenerator R2 PLLloopfilterresistor R3 PLLloopfilterresistor R10 PAoutputmatch,seeSection5.11 XTAL Crystal,seeSection5.16 84 Applications,Implementation,andLayout Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 www.ti.com SWRS046H–NOVEMBER2006–REVISEDMARCH2015 Table6-2.BillofMaterialsfortheApplicationCircuitInFigure6-1(1)(2) ITEM 433MHz 868MHz 915MHz C1(3) 10pF,5%,NP0,0402 47pF,5%,NP0,0402 47pF,5%,NP0,0402 C3(3) 5.6pF,5%,NP0,0402 10pF,5%,NP0,0402 10pF,5%,NP0,0402 C4 22pF,5%,NP0,0402 22pF,5%,NP0,0402 22pF,5%,NP0,0402 C5 12pF,5%,NP0,0402 12pF,5%,NP0,0402 12pF,5%,NP0,0402 C6 220nF,10%,X7R,0603 100nF,10%,X7R,0603 100nF,10%,X7R,0603 C7 8.2nF,10%,X7R,0402 3.9nF,10%,X7R,0402 3.9nF,10%,X7R,0402 C8 2.2nF,10%,X7R,0402 1.0nF,10%,X7R,0402 1.0nF,10%,X7R,0402 C60 220pF,5%,NP0,0402 220pF,5%,NP0,0402 220pF,5%,NP0,0402 L1(3) 33nH,5%,0402 82nH,5%,0402 82nH,5%,0402 L2(3) 22nH,5%,0402 3.6nH,5%,0402 3.6nH,5%,0402 R1 82kΩ,1%,0402 82kΩ,1%,0402 82kΩ,1%,0402 R2 1.5kΩ,5%,0402 2.2kΩ,5%,0402 2.2kΩ,5%,0402 R3 4.7kΩ,5%,0402 6.8kΩ,5%,0402 6.8kΩ,5%,0402 R10 82Ω,5%,0402 82Ω,5%,0402 82Ω,5%,0402 14.7456MHzcrystal, 14.7456MHzcrystal, 14.7456MHzcrystal, XTAL 16pFload 16pFload 16pFload (1) ThePLLloopfiltercomponentvaluesinTable6-2(R2,R3,C6-C8)canbeusedfordataratesupto4.8kBaud. (2) TheSmartRFStudiosoftwareprovidescomponentvaluesforotherdataratesusingtheequationsinSection5.12.2. (3) Itemsshadedvaryfordifferentfrequencies.For433MHz,12.5kHzchannel,aloopfilterwithlowerbandwidthisusedtoimprove adjacentandalternatechannelrejection. In the CC1020EMX reference design (CC1020EMX), LQG15HS series inductors from Murata have been used.TheswitchisSW-456fromM/A-COM. The LC filter in Figure 6-1 is inserted in the TX path only. The filter will reduce the emission of harmonics and the spurious emissions in the TX path. An alternative is to insert the LC filter between the antenna andtheT/RswitchasshowninFigure6-2. The filter will reduce the emission of harmonics and the spurious emissions in the TX path as well as increase the receiver selectivity. The sensitivity will be slightly reduced due to the insertion loss of the LC filter. 6.2 Design Requirements 6.2.1 Input and Output Matching L1 and C1 are the input match for the receiver. L1 is also a DC choke for biasing. L2 and C3 are used to match the transmitter to 50 Ω. Internal circuitry makes it possible to connect the input and output together and match the CC1020 to 50 Ω in both RX and TX mode. However, it is recommended to use an external T/R switch for optimum performance. See Section 5.11 for details. Component values for the matching networkareeasilyfoundusingtheSmartRFStudiosoftware. 6.2.2 Bias Resistor TheprecisionbiasresistorR1isusedtosetanaccuratebiascurrent. 6.2.3 PLL Loop Filter Theloopfilterconsistsoftworesistors(R2andR3)andthreecapacitors(C6throughC8).C7andC8may be omitted in applications where high loop bandwidth is desired. The values shown in Table 6-2 can be used for data rates up to 4.8 kBaud. Component values for higher data rates are easily found using the SmartRFStudiosoftware. Copyright©2006–2015,TexasInstrumentsIncorporated Applications,Implementation,andLayout 85 SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 SWRS046H–NOVEMBER2006–REVISEDMARCH2015 www.ti.com 6.2.4 Crystal An external crystal with two loading capacitors (C4 and C5) is used for the crystal oscillator. See Section5.16 fordetails. 6.2.5 Additional Filtering Additional external components (for example, RF, LC, or SAW filter) may be used in order to improve the performanceinspecificapplications.SeeSection5.11 forfurtherinformation. 6.2.6 Power Supply Decoupling and Filtering Power supply decoupling and filtering must be used (not shown in the application circuit). The placement and size of the decoupling capacitors and the power supply filtering are very important to achieve the optimum performance for narrowband applications. TI provides a reference design that should be followed veryclosely. 6.3 PCB Layout Recommendations The top layer should be used for signal routing, and the open areas should be filled with metallization connectedtogroundusingseveralvias. The area under the chip is used for grounding and must be connected to the bottom ground plane with several vias. In the TI reference designs we have placed 9 vias inside the exposed die attached pad. These vias should be “tented” (covered with solder mask) on the component side of the PCB to avoid migrationofsolderthroughtheviasduringthesolderreflowprocess. DonotplaceaviaunderneathCC1020at“pin#1corner”asthispinisinternallyconnectedtotheexposed dieattachedpad,whichisthemaingroundconnectionforthechip. Each decoupling capacitor should be placed as close as possible to the supply pin it is supposed to decouple. Each decoupling capacitor should be connected to the power line (or power plane) by separate vias. The best routing is from the power line (or power plane) to the decoupling capacitor and then to the CC1020supplypin.Supplypowerfilteringisveryimportant,especiallyforpins23,22,20and18. Each decoupling capacitor ground pad should be connected to the ground plane using a separate via. Direct connections between neighboring power pins will increase noise coupling and should be avoided unlessabsolutelynecessary. The external components should ideally be as small as possible and surface mount devices are highly recommended. Precaution should be used when placing the microcontroller in order to avoid noise interfering with the RF circuitry. A CC1020/1070DK Development Kit with a fully assembled CC1020EMX Evaluation Module is available. It is strongly advised that this reference layout is followed very closely in order to get the best performance.ThelayoutGerberfilesareavailablefromtheCC1020EMX productfolder. 86 Applications,Implementation,andLayout Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 www.ti.com SWRS046H–NOVEMBER2006–REVISEDMARCH2015 7 Device and Documentation Support 7.1 Device Support 7.1.1 Device Nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers. Each device has one of three prefixes: X, P, or null (no prefix) (for example, CC1020 is in production; therefore, noprefixisassigned). Devicedevelopmentevolutionaryflow: X Experimental device that is not necessarily representative of the final device's electrical specificationsandmaynotuseproductionassemblyflow. P Prototype device that is not necessarily the final silicon die and may not necessarily meet finalelectricalspecifications. null Productionversionofthesilicondiethatisfullyqualified. Production devices have been characterized fully, and the quality and reliability of the device have been demonstratedfully.TI'sstandardwarrantyapplies. Predictions show that prototype devices (X or P) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the packagetype(forexample,RSS). For orderable part numbers of CC1020 devices in the RSS package types, see the Package Option Addendumofthisdocument,theTIwebsite(www.ti.com),orcontactyourTIsalesrepresentative. 7.2 Documentation Support The following documents describe the CC1020 device. Copies of these documents are available on the Internetatwww.ti.com. 1. [1]AN022CC1020CrystalFrequencySelection (SWRA070) 2. [2]AN029CC1020/1021AutomaticFrequencyControl(AFC) (SWRA063) 3. [3]AN030CC1020/1021ReceivedSignalStrengthIndicator(SWRA062) 4. [4]AN070CC1020AutomaticPower-UpSequencing(SWRA279) 5. [5]AN023CC1020MCUInterfacing (SWRA069) 6. [6]CC1020ErrataNote004,availableintheCC1020productfolder. 7. [7]CC1020ErrataNote002,availableintheCC1020productfolder. 8. [8]AN001SRDRegulationsForLicenseFreeTransceiverOperation (SWRA090). 9. [9]AN027TemperatureCompensationbyIndirectMethod(SWRA065) 10. [10]AN003SRDAntennas (SWRA088) 11. [11]SmartRFStudio 12. [12]CC1020EMXEvaluationModule 7.2.1 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; seeTI'sTermsofUse. TIE2E™OnlineCommunity TI's Engineer-to-Engineer (E2E) Community. Created to foster Copyright©2006–2015,TexasInstrumentsIncorporated DeviceandDocumentationSupport 87 SubmitDocumentationFeedback ProductFolderLinks:CC1020

CC1020 SWRS046H–NOVEMBER2006–REVISEDMARCH2015 www.ti.com collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, exploreideasandhelpsolveproblemswithfellowengineers. TIEmbeddedProcessorsWiki Texas Instruments Embedded Processors Wiki. Established to help developers get started with Embedded Processors from Texas Instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding thesedevices. 7.3 Trademarks SmartRF,E2EaretrademarksofTexasInstruments. 7.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. 7.5 Export Control Notice Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled product restricted by other applicable national regulations, received from disclosing party under nondisclosure obligations (if any), or any direct product of such technology, to any destination to which such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from U.S. Department of Commerce and other competent Government authorities to the extentrequiredbythoselaws. 7.6 Glossary SLYZ022—TIGlossary. Thisglossarylistsandexplainsterms,acronyms,anddefinitions. 8 Mechanical Packaging and Orderable Information 8.1 Packaging Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revisionofthisdocument.Forbrowser-basedversionsofthisdatasheet,refertotheleft-handnavigation. 88 MechanicalPackagingandOrderableInformation Copyright©2006–2015,TexasInstrumentsIncorporated SubmitDocumentationFeedback ProductFolderLinks:CC1020

PACKAGE OPTION ADDENDUM www.ti.com 7-Mar-2016 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) CC1020-RTB1 OBSOLETE VQFNP RUZ 32 TBD Call TI Call TI -40 to 85 CC1020 CC1020-RTR1 NRND VQFNP RUZ 32 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 CC1020 & no Sb/Br) CC1020RSS OBSOLETE VQFNP RUZ 32 TBD Call TI Call TI -40 to 85 CC1020 CC1020RSSG4 ACTIVE QFN RSS 32 TBD Call TI Call TI -40 to 85 CC1020RSSR ACTIVE QFN RSS 32 2500 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 CC1020 & no Sb/Br) CC1020RSST ACTIVE QFN RSS 32 250 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 CC1020 & no Sb/Br) CC1020RUZ OBSOLETE VQFNP RUZ 32 TBD Call TI Call TI -40 to 85 CC1020 CC1020RUZR OBSOLETE VQFNP RUZ 32 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 85 CC1020 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 7-Mar-2016 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 21-Nov-2016 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) CC1020RSSR QFN RSS 32 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 CC1020RSST QFN RSS 32 250 180.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 CC1020RUZR VQFNP RUZ 32 0 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 21-Nov-2016 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) CC1020RSSR QFN RSS 32 2500 336.6 336.6 28.6 CC1020RSST QFN RSS 32 250 213.0 191.0 55.0 CC1020RUZR VQFNP RUZ 32 0 336.6 336.6 28.6 PackMaterials-Page2

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