CC1000 CC1000 Single Chip Very Low Power RF Transceiver Applications • Very low power UHF wireless data • Home automation transmitters and receivers • Wireless alarm and security systems • 315 / 433 / 868 and 915 MHz ISM/SRD • AMR – Automatic Meter Reading band systems • Low power telemetry • RKE – Two-way Remote Keyless Entry • Game Controllers and advanced toys Product Description CC1000 is a true single-chip UHF trans- CC1000 is based on Chipcon’s SmartRF® ceiver designed for very low power and technology in 0.35 µm CMOS. very low voltage wireless applications. The circuit is mainly intended for the ISM (Industrial, Scientific and Medical) and SRD (Short Range Device) frequency bands at 315, 433, 868 and 915 MHz, but can easily be programmed for operation at other frequencies in the 300-1000 MHz range. The main operating parameters of CC1000 can be programmed via a serial bus, thus making CC1000 a very flexible and easy to use transceiver. In a typical system CC1000 will be used together with a microcontroller and a few external passive components. Features • True single chip UHF RF transceiver • RSSI output • Very low current consumption • Single port antenna connection • Frequency range 300 – 1000 MHz • FSK data rate up to 76.8 kBaud • Integrated bit synchroniser • Complies with EN 300 220 and FCC • High sensitivity (typical -110 dBm at 2.4 CFR47 part 15 kBaud) • Programmable frequency in 250 Hz • Programmable output power –20 to steps makes crystal temperature drift 10 dBm compensation possible without TCXO • Small size (TSSOP-28 or UltraCSP™ • Suitable for frequency hopping package) protocols • Low supply voltage (2.1 V to 3.6 V) • Development kit available • Very few external components required • Easy-to-use software for generating the • No external RF switch / IF filter CC1000 configuration data required SWRS048A Page 1 of 55

CC1000 Table of Contents CC1000...........................................................................................................................1 Single Chip Very Low Power RF Transceiver...........................................................1 1. Absolute Maximum Ratings...................................................................................4 2. Operating Conditions.............................................................................................4 3. Electrical Specifications.........................................................................................4 4. Pin Assignment.......................................................................................................8 5. Circuit Description..................................................................................................9 6. Application Circuit................................................................................................10 6.1 Input / output matching...............................................................................................10 6.2 VCO inductor..............................................................................................................10 6.3 Additional filtering.......................................................................................................10 6.4 Power supply decoupling...........................................................................................10 7. Configuration Overview .......................................................................................12 8. Configuration Software........................................................................................12 9. 3-wire Serial Configuration Interface..................................................................13 Note: The set-up- and hold-times refer to 50% of VDD..........................................14 10. Microcontroller Interface....................................................................................15 10.1 Connecting the microcontroller................................................................................15 11. Signal interface...................................................................................................16 11.1 Manchester encoding and decoding........................................................................16 12. Bit synchroniser and data decision ..................................................................19 13. Receiver sensitivity versus data rate and frequency separation....................22 14. Frequency programming....................................................................................23 15. Recommended RX settings for ISM frequencies.............................................24 16. VCO......................................................................................................................25 17. VCO and PLL self-calibration.............................................................................25 18. VCO and LNA current control............................................................................28 19. Power management............................................................................................28 SWRS048A Page 2 of 55

CC1000 20. Input / Output Matching......................................................................................31 21. Output power programming ..............................................................................32 22. RSSI output.........................................................................................................33 23. IF output ..............................................................................................................34 24. Crystal oscillator.................................................................................................35 25. Optional LC Filter................................................................................................36 26. System Considerations and Guidelines............................................................37 26.1 SRD regulations.......................................................................................................37 26.2 Low cost systems.....................................................................................................37 26.3 Battery operated systems.........................................................................................37 26.4 Crystal drift compensation........................................................................................37 26.5 High reliability systems.............................................................................................37 26.6 Frequency hopping spread spectrum systems.........................................................37 27. PCB Layout Recommendations.........................................................................38 28. Antenna Considerations.....................................................................................38 L = 7125 / f.................................................................................................................38 29. Configuration registers......................................................................................39 30. Package Description (TSSOP-28)......................................................................48 31. Package Description (UltraCSP™)....................................................................49 32. Plastic Tube Specification .................................................................................51 33. Waffle Pack Specification ..................................................................................51 34. Carrier Tape and Reel Specification..................................................................51 35. Ordering Information..........................................................................................52 36. General Information............................................................................................52 36.1 Document Revision History......................................................................................52 36.2 Product Status Definitions........................................................................................52 37. Address Information...........................................................................................54 38. TI Worldwide Technical Support.......................................................................54 39. Product Information Centers.............................................................................54 SWRS048A Page 3 of 55

CC1000 1. Absolute Maximum Ratings Parameter Min. Max. Units Condition Supply voltage, VDD -0.3 5.0 V Voltage on any pin -0.3 VDD+0.3, V max 5.0 Input RF level 10 dBm Storage temperature range -50 150 °C (TSSOP) Shelf life (UltraCSP™) 1 year Room temperature and oxygen free cabinet Reflow soldering temperature 260 °C IPC/JEDEC J-STD-020C (TSSOP) Peak reflow soldering temperature 255 °C IPC/JEDEC J-STD-020C (UltraCSP™) Under no circumstances the absolute the limiting values may cause permanent maximum ratings given above should be damage to the device. violated. Stress exceeding one or more of Caution! ESD sensitive device. Precaution should be used when handling the device in order to prevent permanent damage. 2. Operating Conditions Parameter Min. Typ. Max. Unit Condition / Note RF Frequency Range 300 1000 MHz Programmable in steps of 250 Hz Operating ambient temperature range -40 85 °C Supply voltage 2.1 3.0 3.6 V Note: The same supply voltage should be used for digital (DVDD) and analogue (AVDD) power. 3. Electrical Specifications Tc = 25°C, VDD = 3.0 V if nothing else stated Parameter Min. Typ. Max. Unit Condition / Note Transmit Section Transmit data rate 0.6 76.8 kBaud NRZ or Manchester encoding. 76.8 kBaud equals 76.8 kbit/s using NRZ coding. See page 16. Binary FSK frequency separation 0 65 kHz The frequency separation is programmable in 250 Hz steps. 65 kHz is the maximum guaranteed separation at 1 MHz reference frequency. Larger separations can be achieved at higher reference frequencies. SWRS048A Page 4 of 55

CC1000 Parameter Min. Typ. Max. Unit Condition / Note Output power Delivered to 50 Ω load. 433 MHz -20 10 dBm The output power is 868 MHz -20 5 dBm programmable. RF output impedance 140 / 80 Ω Transmit mode. For matching 433/868 MHz details see “Input/ output matching” p.31. Harmonics -20 dBc An external LC or SAW filter should be used to reduce harmonics emission to comply with SRD requirements. See p.36. Receive Section Receiver Sensitivity, 433 MHz 2.4 kBaud, Manchester coded Optimum sensitivity (9.3 mA) -110 dBm data, 64 kHz frequency Low current consumption (7.4 mA) -109 dBm separation, BER = 10-3 Receiver Sensitivity, 868 MHz See Table 6 and Table 7 page 22 Optimum sensitivity (11.8 mA) -107 dBm for typical sensitivity figures at Low current consumption (9.6 mA) -105 dBm other data rates. System noise bandwidth 30 kHz 2.4 kBaud, Manchester coded data Cascaded noise figure 12/13 dB 433/868 MHz Saturation 10 dBm 2.4 kBaud, Manchester coded data, BER = 10-3 Input IP3 -18 dBm From LNA to IF output Blocking 40 dBc At +/- 1 MHz LO leakage -57 dBm Input impedance Receive mode, series equivalent 88-j26 Ω at 315 MHz 70-j26 Ω at 433 MHz 52-j7 Ω at 868 MHz. 52-j4 Ω At 915 MHz For matching details see “Input/ output matching” p. 31. Turn on time 11 128 Baud The turn-on time is determined by the demodulator settling time, which is programmable. See p. 19 IF Section Intermediate frequency (IF) 150 kHz Internal IF filter 10.7 MHz External IF filter IF bandwidth 175 kHz RSSI dynamic range -105 -50 dBm RSSI accuracy ± 6 dB See p.33 for details RSSI linearity ± 2 dB SWRS048A Page 5 of 55

CC1000 Parameter Min. Typ. Max. Unit Condition / Note Frequency Synthesiser Section Crystal Oscillator Frequency 3 16 MHz Crystal frequency can be 3-4, 6-8 or 9-16 MHz. Recommended frequencies are 3.6864, 7.3728, 11.0592 and 14.7456. See page 35 for details. Crystal frequency accuracy ± 50 ppm 433 MHz requirement ± 25 868 MHz The crystal frequency accuracy and drift (ageing and temperature dependency) will determine the frequency accuracy of the transmitted signal. Crystal operation Parallel C171 and C181 are loading capacitors, see page 35 Crystal load capacitance 12 22 30 pF 3-4 MHz, 22 pF recommended 12 16 30 pF 6-8 MHz, 16 pF recommended 12 16 16 pF 9-16 MHz, 16 pF recommended Crystal oscillator start-up time 5 ms 3.6864 MHz, 16 pF load 1.5 ms 7.3728 MHz, 16 pF load 2 ms 16 MHz, 16 pF load Output signal phase noise -85 dBc/Hz At 100 kHz offset from carrier PLL lock time (RX / TX turn time) 200 µs Up to 1 MHz frequency step PLL turn-on time, crystal oscillator 250 µs Crystal oscillator running on in power down mode Digital Inputs/Outputs Logic “0” input voltage 0 0.3*VDD V Logic ”1” input voltage 0.7*VDD VDD V Logic “0” output voltage 0 0.4 V Output current -2.5 mA, 3.0 V supply voltage Logic “1” output voltage 2.5 VDD V Output current 2.5 mA, 3.0 V supply voltage Logic “0” input current NA -1 µA Input signal equals GND Logic “1” input current NA 1 µA Input signal equals VDD DIO setup time 20 ns TX mode, minimum time DIO must be ready before the positive edge of DCLK DIO hold time 10 ns TX mode, minimum time DIO must be held after the positive edge of DCLK Serial interface (PCLK, PDATA and See Table 2 page 14 PALE) timing specification Current Consumption Power Down mode 0.2 1 µA Oscillator core off SWRS048A Page 6 of 55

CC1000 Parameter Min. Typ. Max. Unit Condition / Note Current Consumption, 7.4/9.6 mA Current is programmable and can receive mode 433/868 MHz be increased for improved sensitivity Current Consumption, 74/96 µA Polling controlled by micro- average in receive mode using controller using 1:100 receive to polling 433/868 MHz power down ratio Current Consumption, transmit mode 433/868 MHz: P=0.01mW (-20 dBm) 5.3/8.6 mA The ouput power is delivered to a 50Ω load, see also p. 32 P=0.3 mW (-5 dBm) 8.9/13.8 mA P=1 mW (0 dBm) 10.4/16.5 mA P=3 mW (5 dBm) 14.8/25.4 mA P=10 mW (10 dBm) 26.7/NA mA Current Consumption, crystal osc. 30 µA 3-8 MHz, 16 pF load 80 µA 9-14 MHz, 12 pF load 105 µA 14-16 MHz, 16 pF load Current Consumption, crystal osc. 860 µA And bias Current Consumption, crystal osc., 4/5 mA < 500 MHz bias and synthesiser, RX/TX 5/6 mA > 500 MHz SWRS048A Page 7 of 55

CC1000 4. Pin Assignment Pin no. UltraCSP Pin name Pin type Description pin no. 1 G3 AVDD Power (A) Power supply (3 V) for analog modules (mixer and IF) 2 F2 AGND Ground (A) Ground connection (0 V) for analog modules (mixer and IF) 3 G2 RF_IN RF Input RF signal input from antenna 4 G1 RF_OUT RF output RF signal output to antenna 5 F1 AVDD Power (A) Power supply (3 V) for analog modules (LNA and PA) 6 E2 AGND Ground (A) Ground connection (0 V) for analog modules (LNA and PA) 7 E1 AGND Ground (A) Ground connection (0 V) for analog modules (PA) 8 D1 AGND Ground (A) Ground connection (0 V) for analog modules (VCO and prescaler) 9 C1 AVDD Power (A) Power supply (3 V) for analog modules (VCO and prescaler) 10 B1 L1 Analog input Connection no 1 for external VCO tank inductor 11 A1 L2 Analog input Connection no 2 for external VCO tank inductor 12 B2 CHP_OUT Analog output Charge pump current output (LOCK) The pin can also be used as PLL Lock indicator. Output is high when PLL is in lock. 13 C2 R_BIAS Analog output Connection for external precision bias resistor (82 kΩ, ± 1%) 14 F3 AGND Ground (A) Ground connection (0 V) for analog modules (backplane) 15 A2 AVDD Power (A) Power supply (3 V) for analog modules (general) 16 B3 AGND Ground (A) Ground connection (0 V) for analog modules (general) 17 A3 XOSC_Q2 Analog output Crystal, pin 2 18 A4 XOSC_Q1 Analog input Crystal, pin 1, or external clock input 19 B4 AGND Ground (A) Ground connection (0 V) for analog modules (guard) 20 C3 DGND Ground (D) Ground connection (0 V) for digital modules (substrate) 21 C4 DVDD Power (D) Power supply (3 V) for digital modules 22 D4 DGND Ground (D) Ground connection (0 V) for digital modules 23 E4 DIO Digital Data input/output. Data input in transmit mode. Data output in input/output receive mode 24 F4 DCLK Digital output Data clock for data in both receive and transmit mode 25 G4 PCLK Digital input Programming clock for 3-wire bus 26 D3 PDATA Digital Programming data for 3-wire bus. Programming data input for input/output write operation, programming data output for read operation 27 D2 PALE Digital input Programming address latch enable for 3-wire bus. Internal pull-up. 28 E3 RSSI/IF Analog output The pin can be used as RSSI or 10.7 MHz IF output to optional external IF and demodulator. If not used, the pin should be left open (not connected). A=Analog, D=Digital (Top View) 11 2288 AAVVDDDD RRRSSSSSSIII///IIIFFF 22 2277 AAGGNNDD PPPAAALLLEEE 33 2266 RRFF__IINN PPPDDDAAATTTAAA 44 2255 RRFF__OOUUTT PPPCCCLLLKKK 55 2244 AAVVDDDD DDDCCCLLLKKK 66 2233 AAGGNNDD DDDIIIOOO CC 77 2222 AAGGNNDD CC DDDGGGNNNDDD 88 11 2211 AAGGNNDD DDDVVVDDDDDD 00 AAVVDDDD 99 00 2200 DDDGGGNNNDDD 1100 00 1199 LL11 AAAGGGNNNDDD 1111 1188 LL22 XXXOOOSSSCCC___QQQ111 1122 1177 CCHHPP__OOUUTT XXXOOOSSSCCC___QQQ222 1133 1166 RR__BBIIAASS AAAGGGNNNDDD 1144 1155 AAGGNNDD AAAVVVDDDDDD SWRS048A Page 8 of 55

CC1000 5. Circuit Description RRSSSSII//IIFF MMIIXXEERR RRFF__IINN LLNNAA IIFF SSTTAAGGEE DDEEMMOODD CCOONNTTRROOLL DDIIOO DDCCLLKK PPDDAATTAA,, PPCCLLKK,, PPAALLEE 33 //NN RRFF__OOUUTT PPAA BBIIAASS RR__BBIIAASS ~~ XXOOSSCC__QQ22 CCHHAARRGGEE VVCCOO LLPPFF PPDD //RR OOSSCC PPUUMMPP XXOOSSCC__QQ11 LL11 LL22 CCHHPP__OOUUTT Figure 1. Simplified block diagram of the CC1000 A simplified block diagram of CC1000 is In transmit mode the voltage controlled shown in Figure 1. Only signal pins are oscillator (VCO) output signal is fed shown. directly to the power amplifier (PA). The RF output is frequency shift keyed (FSK) In receive mode CC1000 is configured as a by the digital bit stream fed to the pin DIO. traditional superheterodyne receiver. The The internal T/R switch circuitry makes the RF input signal is amplified by the low- antenna interface and matching very easy. noise amplifier (LNA) and converted down to the intermediate frequency (IF) by the The frequency synthesiser generates the mixer (MIXER). In the intermediate local oscillator signal which is fed to the frequency stage (IF STAGE) this MIXER in receive mode and to the PA in downconverted signal is amplified and transmit mode. The frequency synthesiser filtered before being fed to the consists of a crystal oscillator (XOSC), demodulator (DEMOD). As an option a phase detector (PD), charge pump RSSI signal, or the IF signal after the (CHARGE PUMP), VCO, and frequency mixer is available at the RSSI/IF pin. After dividers (/R and /N). An external crystal demodulation CC1000 outputs the digital must be connected to XOSC, and only an demodulated data on the pin DIO. external inductor is required for the VCO. Synchronisation is done on-chip providing data clock at DCLK. The 3-wire digital serial interface (CONTROL) is used for configuration. SWRS048A Page 9 of 55

CC1000 6. Application Circuit Very few external components are Component values for the matching required for the operation of CC1000. A network and VCO inductor are easily typical application circuit is shown in calculated using the SmartRF® Studio Figure 2. Component values are shown in software. Table 1. 6.3 Additional filtering 6.1 Input / output matching Additional external components (e.g. RF C31/L32 is the input match for the LC or SAW-filter) may be used in order to receiver. L32 is also a DC choke for improve the performance in specific biasing. C41, L41 and C42 are used to applications. See also “Optional LC filter” match the transmitter to 50 Ω. An internal p.36 for further information. T/R switch circuit makes it possible to connect the input and output together and 6.4 Power supply decoupling match the CC1000 to 50 Ω in both RX and Power supply decoupling and filtering TX mode. See “Input/output matching” must be used (not shown in the p.31 for details. application circuit). The placement and size of the decoupling capacitors and the 6.2 VCO inductor power supply filtering are very important to The VCO is completely integrated except achieve the optimum performance. for the inductor L101. Chipcon provides reference designs (CC1000PP and CC1000uCSP_EM) that should be followed very closely. Figure 2. Typical CC1000 application circuit (power supply decoupling not shown) SWRS048A Page 10 of 55

CC1000 CC1000 TSSOP package Item 315 MHz 433 MHz 868 MHz 915 MHz C31 8.2 pF, 5%, C0G, 0603 15 pF, 5%, C0G, 0603 10 pF, 5%, C0G, 0603 10 pF, 5%, C0G, 0603 C41 2.2 pF, 5%, C0G, 0603 8.2 pF, 5%, C0G, 0603 Not used Not used C42 5.6 pF, 5%, C0G, 0603 5.6 pF, 5%, C0G, 0603 4.7 pF, 5%, C0G, 0603 4.7 pF, 5%, C0G, 0603 C171 18 pF, 5%, C0G, 0603 18 pF, 5%, C0G, 0603 18 pF, 5%, C0G, 0603 18 pF, 5%, C0G, 0603 C181 18 pF, 5%, C0G, 0603 18 pF, 5%, C0G, 0603 18 pF, 5%, C0G, 0603 18 pF, 5%, C0G, 0603 L32 39 nH, 10%, 0805 68 nH, 10%, 0805 120 nH, 10%, 0805 120 nH, 10%, 0805 (Coilcraft 0805CS-390XKBC) (Coilcraft 0805CS-680XKBC) (Coilcraft 0805CS-121XKBC) (Coilcraft 0805CS-121XKBC) L41 20 nH, 10%, 0805 6.2 nH, 10%, 0805 2.5 nH, 10%, 0805 2.5 nH, 10%, 0805 (Coilcraft 0805HQ- (Coilcraft 0805HQ- (Coilcraft 0805HQ- (Coilcraft 0805HQ- 20NXKBC) 6N2XKBC) 2N5XKBC) 2N5XKBC) L101 56 nH, 5%, 0805 33 nH, 5%, 0805 4.7 nH, 5%, 0805 4.7 nH, 5%, 0805 (Koa KL732ATE56NJ) (Koa KL732ATE33NJ) (Koa KL732ATE4N7C) (Koa KL732ATE4N7C) R131 82 kΩ, 1%, 0603 82 kΩ, 1%, 0603 82 kΩ, 1%, 0603 82 kΩ, 1%, 0603 XTAL 14.7456 MHz crystal, 14.7456 MHz crystal, 14.7456 MHz crystal, 14.7456 MHz crystal, 16 pF load 16 pF load 16 pF load 16 pF load CC1000 UltraCSP™ package Item 315 MHz 433 MHz 868 MHz 915 MHz C31 8.2 pF, 5%, C0G, 0402 15 pF, 5%, C0G, 0402 10 pF, 5%, C0G, 0402 10 pF, 5%, C0G, 0402 C41 Not used Not used Not used Not used C42 4.7 pF, 5%, C0G, 0402 4.7 pF, 5%, C0G, 0402 6.8 pF, 5%, C0G, 0402 6.8 pF, 5%, C0G, 0402 C171 18 pF, 5%, C0G, 0402 18 pF, 5%, C0G, 0402 18 pF, 5%, C0G, 0402 18 pF, 5%, C0G, 0402 C181 18 pF, 5%, C0G, 0402 18 pF, 5%, C0G, 0402 18 pF, 5%, C0G, 0402 18 pF, 5%, C0G, 0402 L32 39 nH, 5%, 0402 68 nH, 5%, 0402 120 nH, 5%, 0402 120 nH, 5%, 0402 (Ceramic multilayer) (Ceramic multilayer) (Ceramic multilayer) (Ceramic multilayer) L41 22 nH, 5%, 0402 15 nH, 5%, 0402 2.7 nH, 5%, 0402 2.7 nH, 5%, 0402 (Ceramic multilayer) (Ceramic multilayer) (Ceramic multilayer) (Ceramic multilayer) L101 56 nH, 5%, 0402 33 nH, 5%, 0402 7.5 nH, 5%, 0402 7.5 nH, 5%, 0402 (Thin film inductor) (Thin film inductor) (Thin film inductor) (Thin film inductor) R131 82 kΩ, 1%, 0402 82 kΩ, 1%, 0402 82 kΩ, 1%, 0402 82 kΩ, 1%, 0402 XTAL 14.7456 MHz crystal, 14.7456 MHz crystal, 14.7456 MHz crystal, 14.7456 MHz crystal, 16 pF load 16 pF load 16 pF load 16 pF load Note: Items shaded are different for different frequencies Table 1. Bill of materials for the application circuit Note that the component values for Chipcon provide reference layouts that 868/915 MHz can be the same. However, should be followed very closely in order to it is important the layout is optimised for achieve the best performance. The the selected VCO inductor in order to reference design can be downloaded from centre the tuning range around the the Chipcon website. operating frequency to account for inductor tolerance. The VCO inductor must be placed very close and symmetrical with respect to the pins (L1 and L2). SWRS048A Page 11 of 55

CC1000 7. Configuration Overview CC1000 can be configured to achieve the frequency separation (deviation), best performance for different crystal oscillator reference frequency applications. Through the programmable • Power-down / power-up mode configuration registers the following key • Crystal oscillator power-up / power parameters can be programmed: down • Data rate and data format (NRZ, • Receive / transmit mode Manchester coded or UART interface) • RF output power • Synthesiser lock indicator mode • Frequency synthesiser key • Optional RSSI or external IF parameters: RF output frequency, FSK 8. Configuration Software Chipcon provides users of CC1000 with a CC1000. In addition the program will software program, SmartRF® Studio provide the user with the component (Windows interface) that generates all values needed for the input/output necessary CC1000 configuration data matching circuit and the VCO inductor. based on the user’s selections of various parameters. These hexadecimal numbers Figure 3 shows the user interface of the will then be the necessary input to the CC1000 configuration software. microcontroller for the configuration of Figure 3. SmartRF® Studio user interface SWRS048A Page 12 of 55

CC1000 9. 3-wire Serial Configuration Interface CC1000 is configured via a simple 3-wire The timing for the programming is also interface (PDATA, PCLK and PALE). shown in Figure 4 with reference to Table There are 28 8-bit configuration registers, 2. The clocking of the data on PDATA is each addressed by a 7-bit address. A done on the negative edge of PCLK. Read/Write bit initiates a read or write When the last bit, D0, of the 8 data-bits operation. A full configuration of CC1000 has been loaded, the data word is loaded requires sending 22 data frames of 16 bits in the internal configuration register. each (7 address bits, R/W bit and 8 data bits). The time needed for a full The configuration data is stored in internal configuration depend on the PCLK RAM. The data is retained during power- frequency. With a PCLK frequency of 10 down mode, but not when the power- MHz the full configuration is done in less supply is turned off. The registers can be than 46 µs. Setting the device in power programmed in any order. down mode requires sending one frame only and will in this case take less than 2 The configuration registers can also be µs. All registers are also readable. read by the microcontroller via the same configuration interface. The seven address bits are sent first, then the R/W bit set low In each write-cycle 16 bits are sent on the PDATA-line. The seven most significant to initiate the data read-back. CC1000 then bits of each data frame (A6:0) are the returns the data from the addressed address-bits. A6 is the MSB (Most register. PDATA is in this case used as an Significant Bit) of the address and is sent output and must be tri-stated (or set high n as the first bit. The next bit is the R/W bit the case of an open collector pin) by the (high for write, low for read). During microcontroller during the data read-back address and R/W bit transfer the PALE (D7:0). The read operation is illustrated in (Program Address Latch Enable) must be Figure 5. kept low. The 8 data-bits are then transferred (D7:0). See Figure 4. T T SA HA T T T SA T T CH,min CL,min HD SD PCLK Address Write mode Data byte PDATA 6 5 4 3 2 1 0 W 7 6 5 4 3 2 1 0 PALE Figure 4. Configuration registers write operation SWRS048A Page 13 of 55

CC1000 PCLK Address Read mode Data byte PDATA 6 5 4 3 2 1 0 R 7 6 5 4 3 2 1 0 PALE Figure 5. Configuration registers read operation Parameter Symbol Min Max Units Conditions PCLK, clock F - 10 MHz CLOCK frequency PCLK low T 50 ns The minimum time PCLK must be low. CL,min pulse duration PCLK high T 50 ns The minimum time PCLK must be high. CH,min pulse duration PALE setup T 10 - ns The minimum time PALE must be low before SA time negative edge of PCLK. PALE hold T 10 - ns The minimum time PALE must be held low after HA time the positive edge of PCLK. PDATA setup T 10 - ns The minimum time data on PDATA must be ready SD time before the negative edge of PCLK. PDATA hold T 10 - ns The minimum time data must be held at PDATA, HD time after the negative edge of PCLK. Rise time T 100 ns The maximum rise time for PCLK and PALE rise Fall time T 100 ns The maximum fall time for PCLK and PALE fall Note: The set-up- and hold-times refer to 50% of VDD. Table 2. Serial interface, timing specification SWRS048A Page 14 of 55

CC1000 10. Microcontroller Interface Used in a typical system, CC1000 will • Optionally the microcontroller can do interface to a microcontroller. This data encoding / decoding. microcontroller must be able to: • Optionally the microcontroller can monitor the frequency lock status from • Program CC1000 into different modes pin CHP_OUT (LOCK). via the 3-wire serial configuration • Optionally the microcontroller can interface (PDATA, PCLK and PALE). monitor the RSSI output for signal • Interface to the bi-directional strength acquisition. synchronous data signal interface (DIO and DCLK). 10.1 Connecting the microcontroller The microcontroller uses 3 output pins for The microcontroller pins connected to the configuration interface (PDATA, PCLK PDATA and PCLK can be used for other and PALE). PDATA should be a bi- purposes when the configuration interface directional pin for data read-back. A bi- is not used. PDATA and PCLK are high directional pin is used for data (DIO) to be impedance inputs as long as PALE is transmitted and data received. DCLK high. providing the data timing should be connected to a microcontroller input. PALE has an internal pull-up resistor and Optionally another pin can be used to should be left open (tri-stated by the monitor the LOCK signal (available at the microcontroller) or set to a high level CHP_OUT pin). This signal is logic level during power down mode in order to high when the PLL is in lock. See Figure prevent a trickle current flowing in the pull- 6. up. The pin state in power down mode is summarized in Table 3. Also the RSSI signal can be connected to the microcontroller if it has an analogue ADC input. Pin Pin state Note PDATA Input Should be driven high or low PCLK Input Should be driven high or low PALE Input with internal pull- Should be driven high or high-impedance to minimize up resistor power consumption DIO Input Should be driven high or low DCLK High-impedance output Table 3. CC1000 pins in power-down mode PDATA PCLK Micro- CC1000 PALE controller DIO DCLK (Optional) CHP_OUT (LOCK) (Optional) RSSI/IF ADC Figure 6. Microcontroller interface SWRS048A Page 15 of 55

CC1000 11. Signal interface The signal interface consists of DIO and is presented at DIO. The data should be DCLK and is used for the data to be clocked into the interfacing circuit at the transmitted and data received. DIO is the rising edge of DCLK. See Figure 8. bi-directional data line and DCLK provides a synchronous clock both during data Transparent Asynchronous UART mode. transmission and data reception. In transmit mode DIO is used as data input. The data is modulated at RF without The CC1000 can be used with NRZ (Non- synchronisation or encoding. In receive Return-to-Zero) data or Manchester (also mode the raw data signal from the known as bi-phase-level) encoded data. demodulator is sent to the output. No CC1000 can also synchronise the data from synchronisation or decoding of the signal the demodulator and provide the data is done in CC1000 and should be done by clock at DCLK. the interfacing circuit. The DCLK pin is used as data output in this mode. Data CC1000 can be configured for three rates in the range from 0.6 to 76.8 kBaud different data formats: can be used. For 38.4 and 76.8 kBaud a crystal frequency of 14.7456 MHz must be Synchronous NRZ mode. In transmit used. See Figure 9. mode CC1000 provides the data clock at DCLK, and DIO is used as data input. 11.1 Manchester encoding and Data is clocked into CC1000 at the rising decoding edge of DCLK. The data is modulated at In the Synchronous Manchester encoded RF without encoding. CC1000 can be mode CC1000 uses Manchester coding configured for the data rates 0.6, 1.2, 2.4, when modulating the data. The CC1000 4.8, 9.6, 19.2, 38.4 or 76.8 kbit/s. For 38.4 also performs the data decoding and and 76.8 kbit/s a crystal frequency of synchronisation. The Manchester code is 14.7456 MHz must be used. In receive based on transitions; a “0” is encoded as a mode CC1000 does the synchronisation low-to-high transition, a “1” is encoded as and provides received data clock at DCLK a high-to-low transition. See Figure 10. and data at DIO. The data should be clocked into the interfacing circuit at the The CC1000 can detect a Manchester rising edge of DCLK. See Figure 7. decoding violation and will set a Manchester Violation Flag when such a Synchronous Manchester encoded mode. violation is detected in the incoming In transmit mode CC1000 provides the data signal. The threshold limit for the clock at DCLK, and DIO is used as data Manchester Violation can be set in the MODEM1 register. The Manchester input. Data is clocked into CC1000 at the Violation Flag can be monitored at the rising edge of DCLK and should be in NRZ CHP_OUT (LOCK) pin, configured in the format. The data is modulated at RF with LOCK register. Manchester code. The encoding is done by CC1000. In this mode CC1000 can be The Manchester code ensures that the configured for the data rates 0.3, 0.6, 1.2, signal has a constant DC component, 2.4, 4.8, 9.6, 19.2 or 38.4 kbit/s. The 38.4 which is necessary in some FSK kbit/s rate corresponds to the maximum demodulators. Using this mode also 76.8 kBaud due to the Manchester ensures compatibility with CC400/CC900 encoding. For 38.4 and 76.8 kBaud a designs. crystal frequency of 14.7456 MHz must be used. In receive mode CC1000 does the synchronisation and provides received data clock at DCLK and data at DIO. CC1000 does the decoding and NRZ data SWRS048A Page 16 of 55

CC1000 TTrraannssmmiitttteerr ssiiddee:: DDIIOO DDaattaa pprroovviiddeedd bbyy mmiiccrrooccoonnttrroolllleerr DDCCLLKK CClloocckk pprroovviiddeedd bbyy CCCC11000000 ““RRFF”” FFSSKK mmoodduullaattiinngg ssiiggnnaall ((NNRRZZ)),, iinntteerrnnaall iinn CCCC11000000 RReecceeiivveerr ssiiddee:: ““RRFF”” DDeemmoodduullaatteedd ssiiggnnaall ((NNRRZZ)),, iinntteerrnnaall iinn CCCC11000000 DDCCLLKK CClloocckk pprroovviiddeedd bbyy CCCC11000000 DDIIOO DDaattaa pprroovviiddeedd bbyy CCCC11000000 Figure 7. Synchronous NRZ mode TTrraannssmmiitttteerr ssiiddee:: DDIIOO DDaattaa pprroovviiddeedd bbyy mmiiccrrooccoonnttrroolllleerr ((NNRRZZ)) DDCCLLKK CClloocckk pprroovviiddeedd bbyy CCCC11000000 ““RRFF”” FFSSKK mmoodduullaattiinngg ssiiggnnaall ((MMaanncchheesstteerr eennccooddeedd)),, iinntteerrnnaall iinn CCCC11000000 RReecceeiivveerr ssiiddee:: ““RRFF”” DDeemmoodduullaatteedd ssiiggnnaall ((MMaanncchheesstteerr eennccooddeedd)),, iinntteerrnnaall iinn CCCC11000000 DDCCLLKK CClloocckk pprroovviiddeedd bbyy CCCC11000000 DDIIOO DDaattaa pprroovviiddeedd bbyy CCCC11000000 ((NNRRZZ)) Figure 8. Synchronous Manchester encoded mode SWRS048A Page 17 of 55

CC1000 TTrraannssmmiitttteerr ssiiddee:: DDIIOO DDaattaa pprroovviiddeedd bbyy UUAARRTT ((TTXXDD)) DDCCLLKK DDCCLLKK iiss nnoott uusseedd iinn ttrraannssmmiitt mmooddee.. UUsseedd aass ddaattaa oouuttppuutt iinn rreecceeiivvee mmooddee.. ““RRFF”” FFSSKK mmoodduullaattiinngg ssiiggnnaall,, iinntteerrnnaall iinn CCCC11000000 RReecceeiivveerr ssiiddee:: ““RRFF”” DDeemmoodduullaatteedd ssiiggnnaall,, iinntteerrnnaall iinn CCCC11000000 DDIIOO DDIIOO iiss nnoott uusseedd iinn rreecceeiivvee mmooddee.. UUsseedd oonnllyy aass ddaattaa iinnppuutt iinn ttrraannssmmiitt mmooddee.. DDCCLLKK DDaattaa oouuttppuutt pprroovviiddeedd bbyy CCCC11000000.. CCoonnnneecctt ttoo UUAARRTT ((RRXXDD)).. Figure 9. Transparent Asynchronous UART mode 11 00 11 11 00 00 00 11 11 00 11 TTXX ddaattaa TTiimmee Figure 10. Manchester encoding SWRS048A Page 18 of 55

CC1000 12. Bit synchroniser and data decision Average filter Frequency Data Data slicer Sampler Decimator detector filter comparator Figure 11. Demodulator block diagram A block diagram of the digital demodulator acquired value will be kept also after is shown in Figure 11. The IF signal is Power Down or Transmit mode. After a sampled and its instantaneous frequency modem reset is detected. The result is decimated and (MODEM1.MODEM_RESET_N), or a filtered. In the data slicer the data filter main reset (using any of the standard output is compared to the average filter reset sources), the averaging filter is reset. output to generate the data output. In a polled receiver system the automatic The averaging filter is used to find the locking can be used. This is illustrated in average value of the incoming data. While Figure 12. If the receiver is operated the averaging filter is running and continuously and searching for a acquiring samples, it is important that the preamble, the averaging filter should be number of high and low bits received is locked manually as soon as the preamble equal (e.g. Manchester code or a is detected. This is shown in Figure 13. If balanced preamble). the data is Manchester coded there is no need to lock the averaging filter Therefore all modes, also synchronous (MODEM1.LOCK_AVG_IN=’0’), as shown NRZ mode, need a DC balanced in Figure 14. preamble for the internal data slicer to acquire correct comparison level from the The minimum length of the preamble averaging filter. The suggested preamble depends on the acquisition mode selected is a ‘010101…’ bit pattern. The same bit and the settling time. Table 4 gives the pattern should also be used in Manchester minimum recommended number of chips mode, giving a ‘011001100110…chip for the preamble in NRZ and UART pattern. This is necessary for the bit modes. In this context ‘chips’ refer to the synchronizer to synchronize correctly. data coding. Using Manchester coding every bit consists of two ‘chips’. For The averaging filter must be locked before Manchester mode the minimum any NRZ data can be received. If the recommended number of chips is shown averaging filter is locked in Table 5. (MODEM1.LOCK_AVG_MODE=’1’), the SWRS048A Page 19 of 55

CC1000 Settling Manual Lock Automatic Lock NRZ mode UART mode NRZ mode UART mode MODEM1. MODEM1.LOCK_ MODEM1.LOCK_ MODEM1.LOCK_ MODEM1.LOCK_ SETTLING AVG_MODE=’1’ AVG_MODE=’1’ AVG_MODE=’0’ AVG_MODE=’0’ (1:0) MODEM1.LOCK_ MODEM1.LOCK_ MODEM1.LOCK_ MODEM1.LOCK_ AVG_IN=’0’=→’1’** AVG_IN=’0’=→’1’** AVG_IN=’X’*** AVG_IN=’X’*** 00 14 11 16 16 01 25 22 32 32 10 46 43 64 64 11 89 86 128 128 Notes: ** The averaging filter is locked when MODEM1.LOCK_AVG_IN is set to 1 *** X = Do not care. The timer for the automatic lock is started when RX mode is set in the RFMAIN register Also please note that in addition to the number of bits required to lock the filter, you need to add the number of bits needed for the preamble detector. See the next section for more information. Table 4. Minimum preamble bits for locking the averaging filter, NRZ and UART mode Settling Free-running Manchester mode MODEM1. MODEM1.LOCK_ SETTLING AVG_MODE=’1’ (1:0) MODEM1.LOCK_ AVG_IN=’0’ 00 23 01 34 10 55 11 98 Table 5. Minimum number preamble chips for averaging filter, Manchester mode SWRS048A Page 20 of 55

CC1000 DDaattaa ppaacckkaaggee ttoo bbee rreecceeiivveedd NNooiissee PPrreeaammbbllee NNRRZZ ddaattaa NNooiissee RRXX PPDD RRXX AAvveerraaggiinngg ffiilltteerr lloocckkeedd AAvveerraaggiinngg ffiilltteerr ffrreeee--rruunnnniinngg // nnoott uusseedd AAuuttoommaattiiccaallllyy lloocckkeedd aafftteerr aa sshhoorrtt ppeerriioodd ddeeppeennddiinngg oonn ““SSEETTTTLLIINNGG”” Figure 12. Automatic locking of the averaging filter DDaattaa ppaacckkaaggee ttoo bbee rreecceeiivveedd NNooiissee PPrreeaammbbllee NNRRZZ ddaattaa NNooiissee PPDD RRXX AAvveerraaggiinngg ffiilltteerr ffrreeee--rruunnnniinngg AAvveerraaggiinngg ffiilltteerr lloocckkeedd MMaannuuaallllyy lloocckkeedd aafftteerr pprreeaammbbllee iiss ddeetteecctteedd Figure 13. Manual locking of the averaging filter DDaattaa ppaacckkaaggee ttoo bbee rreecceeiivveedd NNooiissee PPrreeaammbbllee MMaanncchheesstteerr eennccooddeedd ddaattaa NNooiissee PPDD RRXX AAvveerraaggiinngg ffiilltteerr aallwwaayyss ffrreeee--rruunnnniinngg Figure 14. Free-running averaging filter SWRS048A Page 21 of 55

CC1000 13. Receiver sensitivity versus data rate and frequency separation The receiver sensitivity depends on the configurations are used. For best data rate, the data format, FSK frequency performance the frequency separation separation and the RF frequency. Typical should be as high as possible especially at figures for the receiver sensitivity (BER = high data rates. Table 8 shows the 10-3) are shown in Table 6 for 64 kHz sensitivity for low current settings. See frequency separations and Table 7 for 20 page 28 for how to program different kHz separations. Optimised sensitivity current consumption. Data rate Separation 433 MHz 868 MHz [kBaud] [kHz] NRZ Manchester UART NRZ Manchester UART mode mode mode mode mode mode 0.6 64 -113 -114 -113 -110 -111 -110 1.2 64 -111 -112 -111 -108 -109 -108 2.4 64 -109 -110 -109 -106 -107 -106 4.8 64 -107 -108 -107 -104 -105 -104 9.6 64 -105 -106 -105 -102 -103 -102 19.2 64 -103 -104 -103 -100 -101 -100 38.4 64 -102 -103 -102 -98 -99 -98 76.8 64 -100 -101 -100 -97 -98 -97 Average current consumption 9.3 mA 11.8 mA Table 6. Receiver sensitivity as a function of data rate at 433 and 868 MHz, BER = 10-3, frequency separation 64 kHz, normal current settings Data rate Separation 433 MHz 868 MHz [kBaud] [kHz] NRZ Manchester UART NRZ Manchester UART mode mode mode mode mode mode 0.6 20 -109 -111 -109 -106 -108 -106 1.2 20 -108 -110 -108 -104 -106 -104 2.4 20 -106 -108 -106 -103 -105 -103 4.8 20 -104 -106 -104 -101 -103 -101 9.6 20 -103 -104 -103 -100 -101 -100 19.2 20 -102 -103 -102 -99 -100 -99 38.4 20 -98 -100 -98 -98 -99 -98 76.8 20 -94 -98 -94 -94 -96 -94 Average current consumption 9.3 mA 11.8 mA Table 7. Receiver sensitivity as a function of data rate at 433 and 868 MHz, BER = 10-3, frequency separation 20 kHz, normal current settings Data rate Separation 433 MHz 868 MHz [kBaud] [kHz] NRZ Manchester UART NRZ Manchester UART mode mode mode mode mode mode 0.6 64 -111 -113 -111 -107 -109 -107 1.2 64 -110 -111 -110 -106 -107 -106 2.4 64 -108 -109 -108 -104 -105 -104 4.8 64 -106 -107 -106 -102 -103 -102 9.6 64 -104 -105 -104 -100 -101 -100 19.2 64 -102 -103 -102 -98 -99 -98 38.4 64 -101 -102 -101 -96 -97 -96 76.8 64 -99 -100 -99 -95 -96 -95 Average current consumption 7.4 mA 9.6 mA Table 8. Receiver sensitivity as a function of data rate at 433 and 868 MHz, BER = 10-3, frequency separation 64 kHz , low current settings SWRS048A Page 22 of 55

CC1000 14. Frequency programming RX mode: f (low-side) fRF f (high-side) fvco LO (Receive frequency) LO fIF fIF TX mode: (Lowef0r FSK (Center ffRreFquency) (Uppef1r FSK fvco frequency) frequency) fsep Figure 15. Relation between f , f , and LO frequency vco if The frequency synthesiser (PLL) is number between 2 and 14 that should be controlled by the frequency word in the chosen such that: configuration registers. There are two frequency words, A and B, which can be 1.0 MHz ≤ f ≤ 2.46 MHz ref programmed to two different frequencies. One of the frequency words can be used Thus, the reference frequency f is: ref for RX (local oscillator frequency) and the other for TX (transmitting frequency, f0). f This makes it possible to switch very fast f = xosc ref REFDIV between RX mode and TX mode. They can also be used for RX (or TX) on two f is the Local Oscillator (LO) frequency different channels. The MAIN.F_REG VCO in receive mode, and the f frequency in control bit performs selection of frequency 0 transmit mode (lower FSK frequency). The word A or B. LO frequency must be f – f or f + f RF IF RF IF giving low-side or high side LO injection The frequency word, FREQ, is 24 bits (3 respectively. Note that the data on DIO will bytes) located in be inverted if high-side LO is used. FREQ_2A:FREQ_1A:FREQ_0A and FREQ_2B:FREQ_1B:FREQ_0B for the A The upper FSK transmit frequency is and B word, respectively. given by: The frequency word FREQ can be f = f + f , calculated from: 1 0 sep where the frequency separation f is set FREQ+FSEP⋅TXDATA+8192 sep f = f ⋅ , by the 11 bit separation word VCO ref 16384 (FSEP1:FSEP0): where TXDATA is 0 or 1 in transmit mode FSEP depending on the data bit to be f = f ⋅ sep ref 16384 transmitted on DIO. In receive mode Clearing PLL.ALARM_DISABLE will TXDATA is always 0. enable generation of the frequency alarm bits PLL.ALARM_H and PLL.ALARM_L. The reference frequency f is the crystal ref These bits indicate that the frequency oscillator clock divided by PLL.REFDIV, a SWRS048A Page 23 of 55

CC1000 synthesis PLL is near the limit of generate register is checked when changing the frequency requested, and the PLL frequencies and when changing between should be recalibrated. RX and TX mode. If lock is not achieved, a It is recommended that the calibration should be performed. LOCK_CONTINOUS bit in the LOCK 15. Recommended RX settings for ISM frequencies Shown in Table 9 are the recommended RX frequency synthesiser settings for a few operating frequencies in the popular ISM bands. These settings ensure optimum configuration of the synthesiser in receive mode for best sensitivity. For some settings of the synthesiser (combinations of RF frequencies and reference frequency), the receiver sensitivity is degraded. The FSK frequency separation is set to 64 kHz. The SmartRF® Studio can be used to generate optimised configuration data as well. Also an application note (AN011) and a spreadsheet are available from Chipcon generating configuration data for any frequency giving optimum sensitivity. ISM Actual Crystal Low-side / Reference Frequency word Frequency word Frequency frequency frequency high- side divider RX mode RX mode [MHz] [MHz] [MHz] LO* REFDIV FREQ FREQ (decimal) (decimal) (hex) 315 315.037200 3.6864 High-side 3 4194304 400000 7.3728 6 4194304 400000 11.0592 9 4194304 400000 14.7456 12 4194304 400000 433.3 433.302000 3.6864 Low-side 3 5775168 580000 7.3728 6 5775168 580000 11.0592 9 5775168 580000 14.7456 12 5775168 580000 433.9 433.916400 3.6864 Low-side 3 5775360 582000 7.3728 6 5775360 582000 11.0592 9 5775360 582000 14.7456 12 5775360 582000 434.5 434.530800 3.6864 Low-side 3 5783552 584000 7.3728 6 5783552 584000 11.0592 9 5783552 584000 14.7456 12 5783552 584000 868.3 868.297200 3.6864 Low-side 2 7708672 75A000 7.3728 4 7708672 75A000 11.0592 6 7708672 75A000 14.7456 8 7708672 75A000 868.95 868.918800 3.6864 High-side 2 7716864 75C000 7.3728 4 7716864 75C000 11.0592 6 7716864 75C000 14.7456 7716864 75C000 869.525 869.526000 3.6864 Low-side 3 11583488 B0C000 7.3728 6 11583488 B0C000 11.0592 9 11583488 B0C000 14.7456 12 11583488 B0C000 869.85 869.840400 3.6864 High-side 2 7725056 75E000 7.3728 4 7725056 75E000 11.0592 6 7725056 75E000 14.7456 8 7725056 75E000 915 914.998800 3.6864 High-side 2 8126464 7C0000 7.3728 4 8126464 7C0000 11.0592 6 8126464 7C0000 14.7456 8 8126464 7C0000 *Note: When using high-side LO injection the data at DIO will be inverted. Table 9. Recommended settings for ISM frequencies SWRS048A Page 24 of 55

CC1000 16. VCO Only one external inductor (L101) is Typical tuning range for the integrated required for the VCO. The inductor will varactor is 20-25%. determine the operating frequency range of the circuit. It is important to place the Component values for various frequencies inductor as close to the pins as possible in are given in Table 1. Component values order to reduce stray inductance. It is for other frequencies can be found using recommended to use a high Q, low the SmartRF® Studio software. tolerance inductor for best performance. 17. VCO and PLL self-calibration To compensate for supply voltage, There are separate calibration values for temperature and process variations the the two frequency registers. If the two VCO and PLL must be calibrated. The frequencies, A and B, differ more than 1 calibration is done automatically and sets MHz, or different VCO currents are used maximum VCO tuning range and optimum (VCO_CURRENT[3:0] in the CURRENT charge pump current for PLL stability. register) the calibration should be done After setting up the device at the operating separately. When using a 10.7 MHz frequency, the self-calibration can be external IF the LO is 10.7 MHz initiated by setting the CAL_START bit. below/above the transmit frequency, The calibration result is stored internally in hence separate calibration must be done. the chip, and is valid as long as power is The CAL_DUAL bit in the CAL register not turned off. If large supply voltage controls dual or separate calibration. variations (more than 0.5 V) or temperature variations (more than 40 The single calibration algorithm, using degrees) occur after calibration, a new separate calibration for RX and TX calibration should be performed. frequency, is illustrated in Figure 16. The self-calibration is controlled through In Figure 17 the dual calibration algorithm the CAL register (see configuration is shown for two RX frequencies. It could registers description p. 39). The also be used for two TX frequencies, or CAL_COMPLETE bit indicates complete even for one RX and one TX frequency if calibration. The user can poll this bit, or the same VCO current is used. simply wait for 34 ms (calibration wait time when CAL_WAIT = 1). The wait time is In multi-channel and frequency hopping proportional to the internal PLL reference applications the PLL calibration values frequency. The lowest permitted reference may be read and stored for later use. By frequency (1 MHz) gives 34 ms wait time, reading back calibration values and which is therefore the worst case. frequency change can be done without doing a re-calibration which could take up Reference Calibration time to 34 ms. The calibration value is stored in frequency [MHz] [ms] the TEST0 and TEST2 registers after a 2.4 14 calibration is completed. Note that when 2.0 17 using single calibration, calibration values 1.5 23 1.0 34 are stored separately for frequency registers A and B. This means that the The CAL_COMPLETE bit can also be TEST0 and TEST2 registers will contain monitored at the CHP_OUT (LOCK) pin calibration settings for the currently (configured by LOCK_SELECT[3:0]) and selected frequency register (selected by used as an interrupt input to the F_REG in the MAIN register). The microcontroller. calibration value can later be written into TEST5 and TEST 6 to bypass the The CAL_START bit must be set to 0 by calibration. Note that you must set the microcontroller after the calibration is VCO_OVERRIDE=1 in TEST5 and done. CHP_OVERRIDE=1 in the TEST6 register. SWRS048A Page 25 of 55

CC1000 SSttaarrtt ssiinnggllee ccaalliibbrraattiioonn WWrriittee FFRREEQQ__AA,, FFRREEQQ__BB IIff DDRR>>==99..66kkBBddtthheenn wwrriittee TTEESSTT44:: LL22KKIIOO==33FFhh FFrreeqquueennccyy rreeggiisstteerr AA iiss uusseedd ffoorr WWrriittee CCAALL:: CCAALL__DDUUAALL == 00 RRXX mmooddee,, rreeggiisstteerr BB ffoorr TTXX WWrriittee MMAAIINN:: RRXX ffrreeqquueennccyy rreeggiisstteerr AA iiss ccaalliibbrraatteedd ffiirrsstt RRXXTTXX == 00;; FF__RREEGG == 00 RRXX__PPDD == 00;; TTXX__PPDD == 11;; FFSS__PPDD == 00 CCOORREE__PPDD == 00;; BBIIAASS__PPDD == 00;; RREESSEETT__NN==11 UUppddaattee CCUURRRREENNTT aanndd PPLLLL ffoorr RRXX mmooddee WWrriittee CCUURRRREENNTT == RRXX ccuurrrreenntt WWrriittee PPLLLL== RRXX ppllll CCaalliibbrraattiioonn iiss ppeerrffoorrmmeedd iinn RRXX mmooddee,, WWrriittee CCAALL:: RReessuulltt iiss ssttoorreedd iinn TTEESSTT00 aanndd TTEESSTT22,, CCAALL__SSTTAARRTT==11 RRXX rreeggiisstteerr WWaaiitt ffoorr mmaaxxiimmuumm 3344 mmss,, oorr CCaalliibbrraattiioonn ttiimmee ddeeppeenndd oonn tthhee rreeffeerreennccee RReeaadd CCAALL aanndd wwaaiitt uunnttiill ffrreeqquueennccyy,, sseeee tteexxtt.. CCAALL__CCOOMMPPLLEETTEE==11 WWrriittee CCAALL:: CCAALL__SSTTAARRTT==00 WWrriittee MMAAIINN:: RRXXTTXX == 11;; FF__RREEGG == 11 TTXX ffrreeqquueennccyy rreeggiisstteerr BB iiss ccaalliibbrraatteedd sseeccoonndd RRXX__PPDD == 11;; TTXX__PPDD == 00;; FFSS__PPDD == 00 CCOORREE__PPDD == 00;; BBIIAASS__PPDD == 00;; RREESSEETT__NN==11 WWrriittee CCUURRRREENNTT == TTXX ccuurrrreenntt WWrriittee PPLLLL== TTXX ppllll UUppddaattee CCUURRRREENNTT aanndd PPLLLL ffoorr TTXX mmooddee WWrriittee PPAA__PPOOWW == 0000hh PPAA iiss ttuurrnneedd ooffff ttoo pprreevveenntt ssppuurriioouuss eemmiissssiioonn CCaalliibbrraattiioonn iiss ppeerrffoorrmmeedd iinn TTXX mmooddee,, WWrriittee CCAALL:: RReessuulltt iiss ssttoorreedd iinn TTEESSTT00 aanndd TTEESSTT22,, CCAALL__SSTTAARRTT==11 TTXX rreeggiisstteerrss WWaaiitt ffoorr 3344mmss,, oorr RReeaadd CCAALL aanndd wwaaiitt uunnttiill CCAALL__CCOOMMPPLLEETTEE==11 WWrriittee CCAALL:: CCAALL__SSTTAARRTT==00 EEnndd ooff ccaalliibbrraattiioonn Figure 16. Single calibration algorithm for RX and TX SWRS048A Page 26 of 55

CC1000 SSttaarrtt dduuaall ccaalliibbrraattiioonn WWrriittee FFRREEQQ__AA,, FFRREEQQ__BB IIff DDRR>>==3388kkBBdd tthheenn wwrriittee TTEESSTT44:: LL22KKIIOO==33FFhh FFrreeqquueennccyy rreeggiisstteerrss AA aanndd BB aarree bbootthh uusseedd WWrriittee CCAALL:: CCAALL__DDUUAALL == 11 ffoorr RRXX mmooddee WWrriittee MMAAIINN:: EEiitthheerr ffrreeqquueennccyy rreeggiisstteerr AA oorr BB iiss sseelleecctteedd RRXXTTXX == 00;; FF__RREEGG == 00 RRXX__PPDD == 00;; TTXX__PPDD == 11;; FFSS__PPDD == 00 CCOORREE__PPDD == 00;; BBIIAASS__PPDD == 00;; RREESSEETT__NN==11 UUppddaattee CCUURRRREENNTT aanndd PPLLLL ffoorr RRXX mmooddee WWrriittee CCUURRRREENNTT==RRXX ccuurrrreenntt WWrriittee PPLLLL==RRXX ppllll DDuuaall ccaalliibbrraattiioonn iiss ppeerrffoorrmmeedd.. WWrriittee CCAALL:: RReessuulltt iiss ssttoorreedd iinn TTEESSTT00 aanndd TTEESSTT22,, CCAALL__SSTTAARRTT==11 ffoorr bbootthh ffrreeqquueennccyy AA aanndd BB rreeggiisstteerrss WWaaiitt ffoorr mmaaxxiimmuumm 3344 mmss,, oorr CCaalliibbrraattiioonn ttiimmee ddeeppeenndd oonn tthhee rreeffeerreennccee RReeaadd CCAALL aanndd wwaaiitt uunnttiill ffrreeqquueennccyy,, sseeee tteexxtt.. CCAALL__CCOOMMPPLLEETTEE==11 WWrriittee CCAALL:: CCAALL__SSTTAARRTT==00 EEnndd ooff ccaalliibbrraattiioonn Figure 17. Dual calibration algorithm for RX mode SWRS048A Page 27 of 55

CC1000 18. VCO and LNA current control The VCO current is programmable and The bias current for the LNA, and the LO should be set according to operating and PA buffers are also programmable. frequency RX/TX mode and output power. Table 10 shows the current consumption Recommended settings for the and receiver sensitivity for different VCO_CURRENT bits in the CURRENT settings (2.4 kBaud Manchester encoded register are shown in the tables on page data). 41. RF freq- Current Sensitivity CURRENT register FRONT_END register uency consumption [dBm] VCO_ LO_DRIVE PA_DRIVE BUF_CUR LNA_CUR [MHz] [mA] CURRENT [1:0] [1:0] RENT RENT[1:0] [3:0] 433 9.3 -110 0100 01 00 0 10 433 7.4 -109 0100 00 00 0 00 868 11.8 -107 1000 11 00 1 10 868 9.6 -105 1000 10 00 0 00 Note: Current consumption and sensitivity are typical figures at 2.4 kBaud Manchester encoded data, BER 10-3 Table 10. Receiver sensitivity as function of current consumption 19. Power management CC1000 offers great flexibility for power A typical power-on and initialising management in order to meet strict power sequence for minimum power consumption requirements in battery consumption is shown in Figure 18 and operated applications. Power Down mode Figure 19. is controlled through the MAIN register. There are separate bits to control the RX PALE should be tri-stated or set to a high part, the TX part, the frequency level during power down mode in order to synthesiser and the crystal oscillator (see prevent a trickle current from flowing in the page 39). This individual control can be internal pull-up resistor. used to optimise for lowest possible current consumption in a certain PA_POW should be set to 00h before application. power down mode to ensure lowest possible leakage current. SWRS048A Page 28 of 55

CC1000 PPoowweerr OOffff PPoowweerr ttuurrnneedd oonn IInniittiiaalliissee aanndd rreesseett CCCC11000000 MMAAIINN:: RReesseett aanndd ttuurrnniinngg oonn tthhee RRXXTTXX == 00 ccrryyssttaall oosscciillllaattoorr ccoorree FF__RREEGG == 00 RRXX__PPDD == 11 TTXX__PPDD == 11 FFSS__PPDD == 11 CCOORREE__PPDD == 00 BBIIAASS__PPDD == 11 RREESSEETT__NN == 00 **TTiimmee ttoo wwaaiitt ddeeppeennddss oonn tthhee ccrryyssttaall ffrreeqquueennccyy MMAAIINN:: RREESSEETT__NN == 11 aanndd tthhee llooaadd ccaappaacciittaannccee WWaaiitt 22 mmss** FFrreeqquueennccyy rreeggiisstteerr AA iiss uusseedd ffoorr PPrrooggrraamm aallll rreeggiisstteerrss eexxcceepptt MMAAIINN RRXX mmooddee,, rreeggiisstteerr BB ffoorr TTXX CCaalliibbrraattiioonn iiss ppeerrffoorrmmeedd aaccccoorrddiinngg CCaalliibbrraattee VVCCOO aanndd PPLLLL ttoo ssiinnggllee ccaalliibbrraattiioonn aallggoorriitthhmm ffoorr bbootthh RRXX aanndd TTXX mmooddee MMAAIINN:: RRXX__PPDD == 11,, TTXX__PPDD == 11,, FFSS__PPDD == 11,, CCOORREE__PPDD == 11,, BBIIAASS__PPDD == 11 PPAA__PPOOWW == 0000hh PPoowweerr DDoowwnn Figure 18. Initializing sequence SWRS048A Page 29 of 55

CC1000 Power Down Turn on crystal oscillator core MAIN: CORE_PD = 0 *Time to wait depends on the crystal frequency Wait 2 ms* and the load capacitance Turn on bias generator BIAS_PD = 0 Wait 200 µs RX TX RX or TX? Turn on RX: Turn on TX: MAIN: RXTX = 0, F_REG = 0 PA_POW = 00h RX_PD = 0, FS_PD = 0 MAIN: RXTX = 1, F_REG = 1 CURRENT = ‘RX current’ TX_PD = 0, FS_PD = 0 PLL = ’RX pll’ CURRENT = ‘TX current’ Wait 250 µs PLL = ’RX pll’ Wait 250 µs RX mode PA_POW = ‘Output power’ Wait 20 µs Turn off RX: MAIN: RX_PD = 1, FS_PD = 1, TX mode CORE_PD=1, BIAS_PD=1 Turn off TX: Power Down MAIN: TX_PD = 1, FS_PD = 1, CORE_PD=1, BIAS_PD=1 PA_POW = 00h Power Down Figure 19. Sequence for activating RX or TX mode SWRS048A Page 30 of 55

CC1000 20. Input / Output Matching A few passive external components Component values for various frequencies combined with the internal T/R switch are given in Table 1. Component values circuitry ensures match in both RX and TX for other frequencies can be found using mode. The matching network is shown in the configuration software. Figure 20. CCCC33331111 RRRRFFFF____IIIINNNN TTTTOOOO AAAANNNNTTTTEEEENNNNNNNNAAAA RRRRFFFF____OOOOUUUUTTTT CCCCCCCC1111000000000000 CCCC44442222 CCCC44441111 LLLL44441111 LLLL33332222 AAAAVVVVDDDDDDDD====3333VVVV Figure 20. Input/output matching network SWRS048A Page 31 of 55

CC1000 21. Output power programming The RF output power is programmable In power down mode the PA_POW should and controlled by the PA_POW register. be set to 00h for minimum leakage Table 11 shows the closest programmable current. value for output powers in steps of 1 dB. The typical current consumption is also shown. Output power RF frequency 433 MHz RF frequency 868 MHz [dBm] PA_POW Current consumption, PA_POW Current consumption, [hex] typ. [mA] [hex] typ. [mA] -20 01 6.9 02 8.6 -19 01 6.9 02 8.8 -18 02 7.1 03 9.0 -17 02 7.1 03 9.0 -16 02 7.1 04 9.1 -15 03 7.4 05 9.3 -14 03 7.4 05 9.3 -13 03 7.4 06 9.5 -12 04 7.6 07 9.7 -11 04 7.6 08 9.9 -10 05 7.9 09 10.1 -9 05 7.9 0B 10.4 -8 06 8.2 0C 10.6 -7 07 8.4 0D 10.8 -6 08 8.7 0F 11.1 -5 09 8.9 40 13.8 -4 0A 9.6 50 14.5 -3 0B 9.4 50 14.5 -2 0C 9.7 60 15.1 -1 0E 10.2 70 15.8 0 0F 10.4 80 16.8 1 40 11.8 90 17.2 2 50 12.8 B0 18.5 3 50 12.8 C0 19.2 4 60 13.8 F0 21.3 5 70 14.8 FF 25.4 6 80 15.8 7 90 16.8 8 C0 20.0 9 E0 22.1 10 FF 26.7 Table 11. Output power settings and typical current consumption SWRS048A Page 32 of 55

CC1000 22. RSSI output CC1000 has a built-in RSSI (Received The RSSI measures the power referred to Signal Strength Indicator) giving an the RF_IN pin. The input power can be analogue output signal at the RSSI/IF pin. calculated using the following equations: The IF_RSSI bits in the FRONT_END register enable the RSSI. When the RSSI P = -51.3 V – 49.2 [dBm] at 433 MHz RSSI function is enabled, the output current of P = -50.0 V – 45.5 [dBm] at 868 MHz RSSI this pin is inversely proportional to the input signal level. The output should be The external network for RSSI operation is terminated in a resistor to convert the shown in Figure 21. R281 = 27 kΩ, C281 current output into a voltage. A capacitor = 1nF. is used in order to low-pass filter the signal. A typical plot of RSSI voltage as function of input power is shown in Figure 22. The RSSI voltage range from 0 – 1.2 V when using a 27 kΩ terminating resistor, giving approximately 50 dB/V. This RSSI voltage can be measured by an A/D converter. Note that a higher voltage means a lower input signal. 1.3 1.2 1.1 433Mhz RRSSSSII//IIFF 1 868Mhz TTOO AADDCC 0.9 CCCC11000000 e 0.8 ag 0.7 olt 0.6 V 0.5 0.4 0.3 CC228811 RR228811 0.2 0.1 0 -105 -100 -95 -90 -85 -80 -75 -70 -65 -60 -55 -50 dBm Figure 22. RSSI voltage vs. input power Figure 21. RSSI circuit SWRS048A Page 33 of 55

CC1000 23. IF output CC1000 has a built-in 10.7 MHz IF output The external network provides 330 Ω buffer. This buffer could be applied in source impedance for the 10.7 MHz narrowband applications with ceramic filter. requirements on mirror image filtering. The system is then built with CC1000, a 10.7 MHz ceramic filter and an external 10.7 MHz demodulator. The external network for IF output operation is shown in Figure 23. R281 = 470 Ω, C281 = 3.3nF. RRSSSSII//IIFF TToo 1100..77MMHHzz ffiilltteerr CCCC11000000 aanndd ddeemmoodduullaattoorr CC228811 RR228811 Figure 23. IF output circuit SWRS048A Page 34 of 55

CC1000 24. Crystal oscillator CC1000 has an advanced amplitude regulated crystal oscillator. A high current Using the internal crystal oscillator, the is used to start up the oscillations. When crystal must be connected between the amplitude builds up, the current is XOSC_Q1 and XOSC_Q2. The oscillator reduced to what is necessary to maintain is designed for parallel mode operation of a 600 mVpp amplitude. This ensures a the crystal. In addition loading capacitors fast start-up, keeps the current (C171 and C181) for the crystal are consumption as well as the drive level to a required. The loading capacitor values minimum and makes the oscillator depend on the total load capacitance, C , L insensitive to ESR variations. specified for the crystal. The total load capacitance seen between the crystal An external clock signal or the internal terminals should equal C for the crystal to L crystal oscillator can be used as main oscillate at the specified frequency. frequency reference. An external clock 1 signal should be connected to XOSC_Q1, CL = 1 1 +Cparasitic while XOSC_Q2 should be left open. The + XOSC_BYPASS bit in the FRONT_END C C 171 181 register should be set when an external The parasitic capacitance is constituted by clock signal is used. pin input capacitance and PCB stray capacitance. Typically the total parasitic The crystal frequency should be in the capacitance is 8 pF. A trimming capacitor range 3-4, 6-8 or 9-16 MHz. Because the may be placed across C171 for initial crystal frequency is used as reference for tuning if necessary. the data rate (as well as other internal functions), the following frequencies are The crystal oscillator circuit is shown in recommended: 3.6864, 7.3728, 11.0592 Figure 24. Typical component values for or 14.7456 MHz. These frequencies will different values of C are given in Table L give accurate data rates. The crystal 12. frequency range is selected by XOSC_FREQ1:0 in the MODEM0 register. The initial tolerance, temperature drift, ageing and load pulling should be carefully To operate in synchronous mode at data specified in order to meet the required rates different from the standards at 1.2, frequency accuracy in a certain 2.4, 4.8 kBaud and so on, the crystal application. By specifying the total frequency can be scaled. The data rate expected frequency accuracy in (DR) will change proportionally to the new SmartRF® Studio together with data rate crystal frequency (f). To calculate the new and frequency separation, the software crystal frequency: will calculate the total bandwidth and DR compare to the available IF bandwidth. f = f new xtal_new xtal DR XXOOSSCC__QQ11 XXOOSSCC__QQ22 XXXTTTAAALLL CC118811 CC117711 Figure 24. Crystal oscillator circuit Item C = 12 pF C = 16 pF C = 22 pF L L L C171 6.8 pF 18 pF 33 pF C181 6.8 pF 18 pF 33 pF Table 12. Crystal oscillator component values SWRS048A Page 35 of 55

CC1000 25. Optional LC Filter An optional LC filter may be added The filter topology is shown in Figure 25. between the antenna and the matching Component values are given in Table 13. network in certain applications. The filter The filter is designed for 50 Ω will reduce the emission of harmonics and terminations. The component values may increase the receiver selectivity. have to be tuned to compensate for layout parasitics. LL7711 CC7711 CC7722 Figure 25. LC filter Item 315 MHz 433 MHz 868 MHz 915 MHz C71 30 pF 20 pF 10 pF 10 pF C72 30 pF 20 pF 10 pF 10 pF L71 15 nH 12 nH 5.6 nH 4.7 nH Table 13. LC filter component values SWRS048A Page 36 of 55

CC1000 26. System Considerations and Guidelines 26.1 SRD regulations TCXO and trimming in some applications. International regulations and national laws In less demanding applications a crystal regulate the use of radio receivers and with low temperature drift and low ageing transmitters. SRDs (Short Range Devices) could be used without further for licence free operation are allowed to compensation. A trimmer capacitor in the operate in the 433 and 868-870 MHz crystal oscillator circuit (in parallel with bands in most European countries. In the C171) could be used to set the initial United States such devices operate in the frequency accurately. The fine frequency 260–470 and 902-928 MHz bands. CC1000 step programming cannot be used in RX is designed to meet the requirements for mode if optimised frequency settings are operation in all these bands. A summary required (see page 24). of the most important aspects of these regulations can be found in Application 26.5 High reliability systems Note AN001 SRD regulations for licence Using a SAW filter as a preselector will free transceiver operation, available from improve the communication reliability in Chipcon’s web site. harsh environments by reducing the probability of blocking. The receiver 26.2 Low cost systems sensitivity and the output power will be In systems where low cost is of great reduced due to the filter insertion loss. By importance the CC1000 is the ideal choice. inserting the filter in the RX path only, Very few external components keep the together with an external RX/TX switch, total cost at a minimum. The oscillator only the receiver sensitivity is reduced, crystal can then be a low cost crystal with and output power is remained. The 50 ppm frequency tolerance. CHP_OUT (LOCK) pin can be configured to control an external LNA, RX/TX switch 26.3 Battery operated systems or power amplifier. This is controlled by In low power applications the power down LOCK_SELECT in the LOCK register. mode should be used when not being active. Depending on the start-up time 26.6 Frequency hopping spread requirement, the oscillator core can be spectrum systems powered during power down. See page 28 Due to the very fast frequency shift for information on how effective power properties of the PLL, the CC1000 is also management can be implemented. suitable for frequency hopping systems. Hop rates of 1-100 hops/s are usually 26.4 Crystal drift compensation used depending on the bit rate and the A unique feature in CC1000 is the very fine amount of data to be sent during each frequency resolution of 250 Hz. This can transmission. The two frequency registers be used to do the temperature (FREQ_A and FREQ_B) are designed compensation of the crystal if the such that the ‘next’ frequency can be temperature drift curve is known and a programmed while the ‘present’ frequency temperature sensor is included in the is used. The switching between the two system. Even initial adjustment can be frequencies is done through the MAIN done using the frequency programmability. register. This eliminates the need for an expensive SWRS048A Page 37 of 55

CC1000 27. PCB Layout Recommendations Chipcon provide reference layouts that devices are required. The VCO inductor should be followed in order to achieve the must be placed as close as possible to the best performance. The Chipcon reference chip and symmetrical with respect to the design (CC1000PP and input pins. CC1000uCSP_EM) can be downloaded from the Chipcon website. Precaution should be used when placing the microcontroller in order to avoid A two layer PCB is highly recommended. interference with the RF circuitry. The bottom layer of the PCB should be the “ground-layer”. In certain applications where the ground plane for the digital circuitry is expected to The top layer should be used for signal be noisy, the ground plane may be split in routing, and the open areas should be an analogue and a digital part. All AGND filled with (cid:31)etallization connected to pins and AVDD de-coupling capacitors ground using several vias. should be connected to the analogue ground plane. All DGND pins and DVDD The ground pins should be connected to de-coupling capacitors should be ground as close as possible to the connected to the digital ground. The package pin using individual vias. The de- connection between the two ground coupling capacitors should also be placed planes should be implemented as a star as close as possible to the supply pins connection with the power supply ground. and connected to the ground plane by separate vias. A development kit with a fully assembled PCB is available, and can be used as a The external components should be as guideline for layout. small as possible and surface mount 28. Antenna Considerations CC1000 can be used together with various difficult impedance matching because of types of antennas. The most common their very low radiation resistance. antennas for short range communication are monopole, helical and loop antennas. For low power applications the λ/4- monopole antenna is recommended giving Monopole antennas are resonant the best range and because of its antennas with a length corresponding to simplicity. one quarter of the electrical wavelength (λ/4). They are very easy to design and The length of the λ/4-monopole antenna is can be implemented simply as a “piece of given by: wire” or even integrated into the PCB. L = 7125 / f Non-resonant monopole antennas shorter where f is in MHz, giving the length in cm. than λ/4 can also be used, but at the An antenna for 869 MHz should be 8.2 expense of range. In size and cost critical cm, and 16.4 cm for 434 MHz. applications such an antenna may very well be integrated into the PCB. The antenna should be connected as close as possible to the IC. If the antenna Helical antennas can be thought of as a is located away from the input pin the combination of a monopole and a loop antenna should be matched to the feeding antenna. They are a good compromise in transmission line (50 Ω). size critical applications. But helical antennas tend to be more difficult to For a more thorough primer on antennas, optimise than the simple monopole. please refer to Application Note AN003 SRD Antennas available from Chipcon’s Loop antennas are easy to integrate into web site. the PCB, but are less effective due to SWRS048A Page 38 of 55

CC1000 29. Configuration registers The configuration of CC1000 is done by Studio software. A complete description of programming 22 8-bit configuration the registers are given in the following registers. The configuration data based on tables. After a RESET is programmed all selected system parameters are most the registers have default values. easily found by using the SmartRF® REGISTER OVERVIEW ADDRESS Byte Name Description 00h MAIN MAIN Register 01h FREQ_2A Frequency Register 2A 02h FREQ_1A Frequency Register 1A 03h FREQ_0A Frequency Register 0A 04h FREQ_2B Frequency Register 2B 05h FREQ_1B Frequency Register 1B 06h FREQ_0B Frequency Register 0B 07h FSEP1 Frequency Separation Register 1 08h FSEP0 Frequency Separation Register 0 09h CURRENT Current Consumption Control Register 0Ah FRONT_END Front End Control Register 0Bh PA_POW PA Output Power Control Register 0Ch PLL PLL Control Register 0Dh LOCK LOCK Status Register and signal select to CHP_OUT (LOCK) pin 0Eh CAL VCO Calibration Control and Status Register 0Fh MODEM2 Modem Control Register 2 10h MODEM1 Modem Control Register 1 11h MODEM0 Modem Control Register 0 12h MATCH Match Capacitor Array Control Register for RX and TX impedance matching 13h FSCTRL Frequency Synthesiser Control Register 14h Reserved 15h Reserved 16h Reserved 17h Reserved 18h Reserved 19h Reserved 1Ah Reserved 1Bh Reserved 1Ch PRESCALER Prescaler and IF-strip test control register 40h TEST6 Test register for PLL LOOP 41h TEST5 Test register for PLL LOOP 42h TEST4 Test register for PLL LOOP (must be updated as specified) 43h TEST3 Test register for VCO 44h TEST2 Test register for Calibration 45h TEST1 Test register for Calibration 46h TEST0 Test register for Calibration SWRS048A Page 39 of 55

CC1000 MAIN Register (00h) REGISTER NAME Default Active Description value MAIN[7] RXTX - - RX/TX switch, 0 : RX , 1 : TX MAIN[6] F_REG - - Selection of Frequency Register, 0 : Register A, 1 : Register B MAIN[5] RX_PD - H Power Down of LNA, Mixer, IF, Demodulator, RX part of Signal Interface MAIN[4] TX_PD - H Power Down of TX part of Signal Interface, PA MAIN[3] FS_PD - H Power Down of Frequency Synthesiser MAIN[2] CORE_PD - H Power Down of Crystal Oscillator Core MAIN[1] BIAS_PD - H Power Down of BIAS (Global_Current_Generator) and Crystal Oscillator Buffer MAIN[0] RESET_N - L Reset, active low. Writing RESET_N low will write default values to all other registers than MAIN. Bits in MAIN do not have a default value, and will be written directly through the configurations interface. Must be set high to complete reset. FREQ_2A Register (01h) REGISTER NAME Default Active Description value FREQ_2A[7:0] FREQ_A[23:16] 01110101 - 8 MSB of frequency control word A FREQ_1A Register (02h) REGISTER NAME Default Active Description value FREQ_1A[7:0] FREQ_A[15:8] 10100000 - Bit 15 to 8 of frequency control word A FREQ_0A Register (03h) REGISTER NAME Default Active Description value FREQ_0A[7:0] FREQ_A[7:0] 11001011 - 8 LSB of frequency control word A FREQ_2B Register (04h) REGISTER NAME Default Active Description value FREQ_2B[7:0] FREQ_B[23:16] 01110101 - 8 MSB of frequency control word B FREQ_1B Register (05h) REGISTER NAME Default Active Description value FREQ_1B[7:0] FREQ_B[15:8] 10100101 - Bit 15 to 8 of frequency control word B FREQ_0B Register (06h) REGISTER NAME Default Active Description value FREQ_0B[7:0] FREQ_B[7:0] 01001110 - 8 LSB of frequency control word B FSEP1 Register (07h) REGISTER NAME Default Active Description value FSEP1[7:3] - - - Not used FSEP1[2:0] FSEP_MSB[2:0] 000 - 3 MSB of frequency separation control FSEP0 Register (08h) REGISTER NAME Default Active Description value FSEP0[7:0] FSEP_LSB[7:0] 01011001 - 8 LSB of frequency separation control SWRS048A Page 40 of 55

CC1000 CURRENT Register (09h) REGISTER NAME Default Active Description value CURRENT[7:4] VCO_CURRENT[3:0] 1100 - Control of current in VCO core for TX and RX 0000 : 150µA 0001 : 250µA 0010 : 350µA 0011 : 450µA 0100 : 950µA, use for RX, f= 400 – 500 MHz 0101 : 1050µA 0110 : 1150µA 0111 : 1250µA 1000 : 1450µA, use for RX, f<400 MHz and f>500 MHz; and TX, f= 400 – 500 MHz 1001 : 1550µA, use for TX, f<400 MHz 1010 : 1650µA 1011 : 1750µA 1100 : 2250µA 1101 : 2350µA 1110 : 2450µA 1111 : 2550µA, use for TX, f>500 MHz CURRENT[3:2] LO_DRIVE[1:0] 10 Control of current in VCO buffer for LO drive 00 : 0.5mA, use for TX 01 : 1.0mA , use for RX, f<500 MHz* 10 : 1.5mA, 11 : 2.0mA, use for RX, f>500 MHz * * LO_DRIVE can be reduced to save current in RX mode. See Table 10 for details CURRENT[1:0] PA_DRIVE[1:0] 10 Control of current in VCO buffer for PA 00 : 1mA, use for RX 01 : 2mA, use for TX, f<500 MHz 10 : 3mA 11 : 4mA, use for TX, f>500 MHz FRONT_END Register (0Ah) REGISTER NAME Default Active Description value FRONT_END[7:6] - 00 - Not used FRONT_END[5] BUF_CURRENT 0 - Control of current in the LNA_FOLLOWER 0 : 520uA, use for f<500 MHz 1 : 690uA, use for f>500 MHz * *BUF_CURRENT can be reduced to save current in RX mode. See Table 10 for details. FRONT_END[4:3] LNA_CURRENT 01 - Control of current in LNA [1:0] 00 : 0.8mA, use for f<500 MHz * 01 : 1.4mA 10 : 1.8mA, use for f>500 MHz * 11 : 2.2mA *LNA_CURRENT can be reduced to save current in RX mode. See Table 10 for details. FRONT_END[2:1] IF_RSSI[1:0] 00 - Control of IF_RSSI pin 00 : Internal IF and demodulator, RSSI inactive 01 : RSSI active, RSSI/IF is analog RSSI output 10 : External IF and demodulator, RSSI/IF is mixer output. Internal IF in power down mode. 11 : Not used FRONT_END[0] XOSC_BYPASS 0 - 0 : Internal XOSC enabled 1 : Power-Down of XOSC, external CLK used SWRS048A Page 41 of 55

CC1000 PA_POW Register (0Bh) REGISTER NAME Default Active Description value PA_POW[7:4] PA_HIGHPOWER[3:0] 0000 - Control of output power in high power array. Should be 0000 in PD mode . See Table 11 page 32 for details. PA_POW[3:0] PA_LOWPOWER[3:0] 1111 - Control of output power in low power array Should be 0000 in PD mode. See Table 11 page 32 for details. PLL Register (0Ch) REGISTER NAME Default Active Description value PLL[7] EXT_FILTER 0 - 1 : External loop filter 0 : Internal loop filter 1-to-0 transition samples F_COMP comparator when BREAK_LOOP=1 (TEST3) PLL[6:3] REFDIV[3:0] 0010 - Reference divider 0000 : Not allowed 0001 : Not allowed 0010 : Divide by 2 0011 : Divide by 3 …........ 1111 : Divide by 15 PLL[2] ALARM_DISABLE 0 h 0 : Alarm function enabled 1 : Alarm function disabled PLL[1] ALARM_H - - Status bit for tuning voltage out of range (too close to VDD) PLL[0] ALARM_L - - Status bit for tuning voltage out of range (too close to GND) SWRS048A Page 42 of 55

CC1000 LOCK Register (0Dh) REGISTE NAME Default Active Description R value LOCK[7:4] LOCK_SELECT[3:0] 0000 - Selection of signals to CHP_OUT (LOCK) pin 0000 : Normal, pin can be used as CHP_OUT 0001 : LOCK_CONTINUOUS (active high) 0010 : LOCK_INSTANT (active high) 0011 : ALARM_H (active high) 0100 : ALARM_L (active high) 0101 : CAL_COMPLETE (active high) 0110 : IF_OUT 0111 : REFERENCE_DIVIDER Output 1000 : TX_PDB (active high, activates external PA when TX_PD=0) 1001 : Manchester Violation (active high) 1010 : RX_PDB (active high, activates external LNA when RX_PD=0) 1011 : Not defined 1100 : Not defined 1101 : LOCK_AVG_FILTER 1110 : N_DIVIDER Output 1111 : F_COMP LOCK[3] PLL_LOCK_ 0 - 0 : Sets Lock Threshold = 127, Reset Lock ACCURACY Threshold = 111. Corresponds to a worst case accuracy of 0.7% 1 : Sets Lock Threshold = 31, Reset Lock Threshold =15. Corresponds to a worst case accuracy of 2.8% LOCK[2] PLL_LOCK_ 0 - 0 : Normal PLL lock window LENGTH 1 : Not used LOCK[1] LOCK_INSTANT - - Status bit from Lock Detector LOCK[0] LOCK_CONTINUOUS - - Status bit from Lock Detector CAL Register (0Eh) REGISTER NAME Default Active Description value CAL[7] CAL_START 0 ↑ ↑ 1 : Calibration started 0 : Calibration inactive CAL_START must be set to 0 after calibration is done CAL[6] CAL_DUAL 0 H 1 : Store calibration in both A and B 0 : Store calibration in A or B defined by MAIN[6] CAL[5] CAL_WAIT 0 H 1 : Normal Calibration Wait Time 0 : Half Calibration Wait Time The calibration time is proportional to the internal reference frequency. 2 MHz reference frequency gives 14 ms wait time. CAL[4] CAL_CURRENT 0 H 1 : Calibration Current Doubled 0 : Normal Calibration Current CAL[3] CAL_COMPLETE 0 H Status bit defining that calibration is complete CAL[2:0] CAL_ITERATE 101 H Iteration start value for calibration DAC 000 – 101: Not used 110 : Normal start value 111 : Not used SWRS048A Page 43 of 55

CC1000 MODEM2 Register (0Fh) REGISTER NAME Default Active Description value MODEM2[7] PEAKDETECT 1 H Peak Detector and Remover disabled or enabled 0 : Peak detector and remover is disabled 1 : Peak detector and remover is enabled MODEM2[6:0] PEAK_LEVEL_OFFSET[6:0] 0010110 - Threshold level for Peak Remover in Demodulator. Correlated to frequency deviation, see note. Note: PEAK_LEVEL_OFFSET[6:0] =IFFlsow−IFlowF+s∆f2⋅85 where Fs= XOSCf__FxoRsEcQ+1 and and ∆f is the separation IF =150kHz−2•f_rf•XTAL_accuracy low MODEM1 Register (10h) REGISTER NAME Default Active Description value MODEM1[7:5] MLIMIT 011 - Sets the limit for the Manchester Violation Flag. A Manchester Value = 14 is a perfect bit and a Manchester Value = 0 is a constant level (an unbalanced corrupted bit) 000 : No Violation Flag is set 001 : Violation Flag is set for Manchester Value < 1 010 : Violation Flag is set for Manchester Value < 2 011 : Violation Flag is set for Manchester Value < 3 100 : Violation Flag is set for Manchester Value < 4 101 : Violation Flag is set for Manchester Value < 5 110 : Violation Flag is set for Manchester Value < 6 111 : Violation Flag is set for Manchester Value < 7 MODEM1[4] LOCK_AVG_IN 0 H Lock control bit of Average Filter 0 : Average Filter is free-running 1 : Average Filter is locked MODEM1[3] LOCK_AVG_MODE 0 - Automatic lock of Average Filter 0 : Lock of Average Filter is controlled automatically 1 : Lock of Average Filter is controlled by LOCK_AVG_IN MODEM1[2:1] SETTLING[1:0] 11 - Settling Time of Average Filter 00 : 11 baud settling time, worst case 1.2dB loss in sensitivity 01 : 22 baud settling time, worst case 0.6dB loss in sensitivity 10 : 43 baud settling time, worst case 0.3dB loss in sensitivity 11 : 86 baud settling time, worst case 0.15dB loss in sensitivity MODEM1[0] MODEM_RESET_N 1 L Separate reset of MODEM SWRS048A Page 44 of 55

CC1000 MODEM0 Register (11h) REGISTER NAME Default Active Description value MODEM0[7] - - - Not used MODEM0[6:4] BAUDRATE[2:0] 010 - 000 : 0.6 kBaud 001 : 1.2 kBaud 010 : 2.4 kBaud 011 : 4.8 kBaud 100 : 9.6 kBaud 101 : 19.2, 38.4 and 76.8 kBaud 110 : Not used 111 : Not used MODEM0[3:2] DATA_FORMAT[1:0] 01 - 00 : NRZ operation. 01 : Manchester operation 10 : Transparent Asyncronous UART operation 11 : Not used MODEM0[1:0] XOSC_FREQ[1:0] 00 - Selection of XTAL frequency range 00 : 3MHz – 4MHz crystal, 3.6864MHz recommended Also used for 76.8 kBaud, 14.7456MHz 01 : 6MHz – 8MHz crystal, 7.3728MHz recommended Also used for 38.4 kBaud, 14.7456MHz 10 : 9MHz – 12MHz crystal, 11.0592 MHz recommended 11 : 12MHz – 16MHz crystal, 14.7456MHz recommended MATCH Register (12h) REGISTER NAME Default Active Description value MATCH[7:4] RX_MATCH[3:0] 0000 - Selects matching capacitor array value for RX, step size is 0.4 pF 0001: Use for RF frequency > 500 MHz 0111: Use for RF frequency < 500 MHz MATCH[3:0] TX_MATCH[3:0] 0000 - Selects matching capacitor array value for TX, step size is 0.4 pF FSCTRL Register (13h) REGISTER NAME Default Active Description value FSCTRL[7:4] - - - Not used FSCTRL[3:1] Reserved FSCTRL[0] FS_RESET_N 1 L Separate reset of frequency synthesizer SWRS048A Page 45 of 55

CC1000 PRESCALER Register (1Ch) REGISTER NAME Default Active Description value PRESCALER[7:6] PRE_SWING[1:0] 00 - Prescaler swing. Fractions for PRE_CURRENT[1:0] = 00 00 : 1 * Nominal Swing 01 : 2/3 * Nominal Swing 10 : 7/3 * Nominal Swing 11 : 5/3 * Nominal Swing PRESCALER[5:4] PRE_CURRENT 00 - Prescaler current scaling [1:0] 00 : 1 * Nominal Current 01 : 2/3 * Nominal Current 10 : 1/2 * Nominal Current 11 : 2/5 * Nominal Current PRESCALER[3] IF_INPUT 0 - 0 : Nominal setting 1 : RSSI/IF pin is input to IF-strips PRESCALER[2] IF_FRONT 0 - 0 : Nominal setting 1 : Output of IF_Front_amp is switched to RSSI/IF pin PRESCALER[1:0] - 00 - Not used TEST6 Register (for test only, 40h) REGISTER NAME Default Active Description value TEST6[7] LOOPFILTER_TP1 0 - 1 : Select testpoint 1 to CHP_OUT 0 : CHP_OUT tied to GND TEST6 [6] LOOPFILTER_TP2 0 - 1 : Select testpoint 2 to CHP_OUT 0 : CHP_OUT tied to GND TEST6 [5] CHP_OVERRIDE 0 - 1 : use CHP_CO[4:0] value 0 : use calibrated value TEST6[4:0] CHP_CO[4:0] 10000 - Charge_Pump Current DAC override value TEST5 Register (for test only, 41h) REGISTER NAME Default Active Description value TEST5[7:6] - - - Not used TEST5[5] CHP_DISABLE 0 - 1 : CHP up and down pulses disabled 0 : normal operation TEST5[4] VCO_OVERRIDE 0 - 1 : use VCO_AO[2:0] value 0 : use calibrated value TEST5[3:0] VCO_AO[3:0] 1000 - VCO_ARRAY override value TEST4 Register (for test only, 42h) REGISTER NAME Default Active Description value TEST4[7:6] - - - Not used TEST4[5:0] L2KIO[5:0] 100101 h Constant setting charge pump current scaling/rounding factor. Sets Bandwidth of PLL. Use 3Fh for 9.6 kBaud and higher SWRS048A Page 46 of 55

CC1000 TEST3 Register (for test only, 43h) REGISTER NAME Default Active Description value TEST3[7:5] - - - Not used TEST3[4] BREAK_LOOP 0 - 1 : PLL loop open 0 : PLL loop closed TEST3[3:0] CAL_DAC_OPEN 0100 - Calibration DAC override value, active when BREAK_LOOP =1 TEST2 Register (for test only, 44h) REGISTER NAME Default Active Description value TEST2[7:5] - - - Not used TEST2[4:0] CHP_CURRENT - - Status vector defining applied [4:0] CHP_CURRENT value TEST1 Register (for test only, 45h) REGISTER NAME Default Active Description value TEST1[7:4] - - - Not used TEST1[3:0] CAL_DAC[3:0] - - Status vector defining applied Calibration DAC value TEST0 Register (for test only, 46h) REGISTER NAME Default Active Description value TEST0[7:4] - - - Not used TEST0[3:0] VCO_ARRAY[3:0] - - Status vector defining applied VCO_ARRAY value SWRS048A Page 47 of 55

CC1000 30. Package Description (TSSOP-28) Note: The figure is an illustration only. Thin Shrink Small Outline Package (TSSOP) D E1 E A A1 e B L Copl. α TSSOP 28 Min 9.60 4.30 0.05 0.19 0.45 0° 6.40 0.65 Max 9.80 4.50 1.20 0.15 0.30 0.75 0.10 8° All dimensions in mm SWRS048A Page 48 of 55

CC1000 31. Package Description (UltraCSP™) Top view A1 A2 A3 A4 B1 B2 B3 B4 2339um +/- 20um C1 C2 C3 C4 D1 D2 D3 D4 4034um +/- 20um E1 E2 E3 E4 F1 F2 F3 F4 500um +/- 10um G1 G2 G3 G4 535um 392um +/-20um +/-20um 500um 417um 292um 250um +/- 10um +/-20um +/-20um +/- 10um Bump pitch is 500um centre to centre in both directions. SWRS048A Page 49 of 55

CC1000 Vertical cross section (UltraCSP™) Before assembly on PCB: A Die h1 Solder bumps (Pb free) After assembly on PCB: A Die h2 PCB mounting pads Die thickness Bump height Bump height Total height Total (A) before after assembly before height after assembly (h1) (h2) assembly assembly 432um 200um 140um 632um 572um +/- 20um +/- tbd um +/- 20um +/- tbd um Table 14: Height budget SWRS048A Page 50 of 55

CC1000 32. Plastic Tube Specification TSSOP 4.4mm (.173”) antistatic tube. Tube Specification Package Tube Width Tube Height Tube Units per Tube Length TSSOP 28 268 mil 80 mil 20” 50 33. Waffle Pack Specification Waffle Pack Specification Package Waffle Pack Waffle Pack Length Waffle Pack Length Units per Waffle Pack Width UltraCSP™ 50.8 mm 50.8 mm 3.96 mm 117 34. Carrier Tape and Reel Specification Carrier tape and reel is in accordance with EIA Specification 481. Tape and Reel Specification Package Tape Width Component Hole Reel Units per Reel Pitch Pitch Diameter TSSOP 28 16 mm 8 mm 4 mm 13” 2500 UltraCSP™ 12 mm 8 mm 4 mm 4 mm 2500 Note: UltraCSP™ Tape and reel illustration only SWRS048A Page 51 of 55

CC1000 35. Ordering Information Chipcon Part TI Part Number Description Minimum Order Number* Quantity (MOQ) CC1000-RTB1 CC1000PW Single Chip RF Transceiver. CC1000, 250 (5 tubes of 50 TSSOP 28 package, RoHS compliant Pb- units per tube) free assembly in tubes with 50 pcs per tube. CC1000-RTR1 CC1000PWR Single Chip RF Transceiver. CC1000, 2500 (tape and TSSOP 28 package, RoHS compliant Pb- reel) free assembly, T&R with 2500 pcs per reel. CC1000-RWP2 CC1000YZ Single Chip RF Transceiver. CC1000, 585 (5 waffle UltraCSP™ package, RoHS compliant Pb- packs with 117 free assembly with 117 pcs per waffle pack. pcs per waffle pack) CC1000-RTR2 CC1000YZR Single Chip RF Transceiver. CC1000, 2500 (tape and UltraCSP™ package, RoHS compliant Pb- reel) free assembly, T&R with 2500 pcs per reel. CC1000DK-433 CC1000DK-433 CC1000 Development Kit, 433 MHz 1 CC1000DK-868-915 CC1000DK-868-915 CC1000 Development Kit, 868/915 MHz 1 CC1000PPK-433 CC1000PPK-433 CC1000 Plug & Play Kit, 433 MHz 1 CC1000PPK-868 CC1000PPK-868 CC1000 Plug & Play Kit, 868/915 MHz 1 * Chipcon part numbers are obsolete, but included for reference. Use the TI part numbers when ordering parts. 36. General Information 36.1 Document Revision History Revision Date Description/Changes SWRS048A January 2007 Reflow soldering temperature according to IPC/JEDEC J-STD-020C. Max reflow temperature for CC1000 UltraCSP™ updated to 255 °C. Added waffle pack specification. Updated ordering information with TI part numbers. Updated address information. Updated header and footer. Updated Important Notice. Removed Chipcon specific Disclaimer, Trademarks and Life Support Policy sections. SWRS048 August 2005 UltraCSP™ package included (2.3) Minor corrections and editorial changes 2.2 April 2004 Shaping feature removed Application circuit simplified Additional information added for the demodulator Additional information added for frequency calculation Additional information added for calibration Additional information added for crystal oscillator Preliminary version removed Narrow band information removed REFDIV different in RX and TX Minor corrections and editorial changes 36.2 Product Status Definitions Data Sheet Identification Product Status Definition Advance Information Planned or Under This data sheet contains the design specifications for Development product development. Specifications may change in any manner without notice. Preliminary Engineering Samples This data sheet contains preliminary data, and and First Production supplementary data will be published at a later date. Chipcon reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. No Identification Noted Full Production This data sheet contains the final specifications. Chipcon reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. SWRS048A Page 52 of 55

CC1000 Data Sheet Identification Product Status Definition Obsolete Not In Production This data sheet contains specifications on a product that has been discontinued by Chipcon. The data sheet is printed for reference information only. SWRS048A Page 53 of 55

CC1000 37. Address Information Texas Instruments Norway AS Gaustadalléen 21 N-0349 Oslo NORWAY Tel: +47 22 95 85 44 Fax: +47 22 95 85 46 Web site: http://www.ti.com/lpw 38. TI Worldwide Technical Support Internet TI Semiconductor Product Information Center Home Page: support.ti.com TI Semiconductor KnowledgeBase Home Page: support.ti.com/sc/knowledgebase 39. Product Information Centers Americas Phone: +1(972) 644-5580 Fax: +1(972) 927-6377 Internet/Email: support.ti.com/sc/pic/americas.htm Europe, Middle East and Africa Phone: Belgium (English) +32 (0) 27 45 54 32 Finland (English) +358 (0) 9 25173948 France +33 (0) 1 30 70 11 64 Germany +49 (0) 8161 80 33 11 Israel (English) 180 949 0107 Italy 800 79 11 37 Netherlands (English) +31 (0) 546 87 95 45 Russia +7 (0) 95 363 4824 Spain +34 902 35 40 28 Sweden (English) +46 (0) 8587 555 22 United Kingdom +44 (0) 1604 66 33 99 Fax: +49 (0) 8161 80 2045 Internet: support.ti.com/sc/pic/euro.htm Japan Fax International +81-3-3344-5317 Domestic 0120-81-0036 Internet/Email International support.ti.com/sc/pic/japan.htm Domestic www.tij.co.jp/pic SWRS048A Page 54 of 55

CC1000 Asia Phone International +886-2-23786800 Domestic Toll-Free Number Australia 1-800-999-084 China 800-820-8682 Hong Kong 800-96-5941 India +91-80-51381665 (Toll) Indonesia 001-803-8861-1006 Korea 080-551-2804 Malaysia 1-800-80-3973 New Zealand 0800-446-934 Philippines 1-800-765-7404 Singapore 800-886-1028 Taiwan 0800-006800 Thailand 001-800-886-0010 Fax +886-2-2378-6808 Email tiasia@ti.com or ti-china@ti.com Internet support.ti.com/sc/pic/asia.htm Copyright © 2007, Texas Instruments Incorporated SWRS048A Page 55 of 55

PACKAGE MATERIALS INFORMATION www.ti.com 4-Feb-2009 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0(mm) B0(mm) K0(mm) P1 W Pin1 Type Drawing Diameter Width (mm) (mm) Quadrant (mm) W1(mm) CC1000PWR TSSOP PW 28 2500 330.0 16.4 6.8 10.2 1.6 8.0 16.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 4-Feb-2009 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) CC1000PWR TSSOP PW 28 2500 378.0 70.0 346.0 PackMaterials-Page2

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