CAT5114 32‐tap Digital Potentiometer (POT) Description The CAT5114 is a single digital POT designed as an electronic replacement for mechanical potentiometers and trim pots. Ideal for automated adjustments on high volume production lines, they are also http://onsemi.com well suited for applications where equipment requiring periodic adjustment is either difficult to access or located in a hazardous or remote environment. The CAT5114 contains a 32-tap series resistor array connected SOIC−8 MSOP−8 between two terminals R and R . An up/down counter and decoder H L V SUFFIX Z SUFFIX that are controlled by three input pins, determines which tap is CASE 751BD CASE 846AD connected to the wiper, R . The wiper setting, stored in nonvolatile W memory, is not lost when the device is powered down and is automatically reinstated when power is returned. The wiper can be adjusted to test new system values without affecting the stored setting. Wiper-control of the CAT5114 is accomplished with three input control pins, CS, U/D, and INC. The INC input increments the wiper PDIP−8 TSSOP−8 in the direction which is determined by the logic state of the U/D input. L SUFFIX Y SUFFIX CASE 646AA CASE 948AL The CS input is used to select the device and also store the wiper position prior to power down. The digital POT can be used as a three-terminal resistive divider or as a two-terminal variable resistor. Digital POTs bring variability and TDFN−8 programmability to a wide variety of applications including control, VP2 SUFFIX parameter adjustments, and signal processing. CASE 511AK Features PIN CONFIGURATIONS  32-position Linear Taper Potentiometer 1  Non-volatile EEPROM Wiper Storage INC VCC  Low Standby Current U/D CS  Single Supply Operation: 2.5 V − 6.0 V RH RL GND RWB  Increment Up/Down Serial Interface PDIP (L), SOIC (V), MSOP (Z)  Resistance Values: 10 k(cid:2), 50 k(cid:2) and 100 k(cid:2)  Available in PDIP, SOIC, TSSOP, MSOP and Space Saving 1 CS RL 2  3mm TDFN Packages VCC RWB  These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS INC GND Compliant U/D RH TSSOP (Y) Applications  Automated Product Calibration INC 1 VCC  Remote Control Adjustments U/D CS  Offset, Gain and Zero Control RH RL GND RWB  Tamper-proof Calibrations TDFN (VP2)  Contrast, Brightness and Volume Controls (Top Views)  Motor Controls and Feedback Systems  Programmable Analog Functions ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet.  Semiconductor Components Industries, LLC, 2013 1 Publication Order Number: June, 2013 − Rev. 23 CAT5114/D

CAT5114 DEVICE MARKING INFORMATION PDIP SOIC MSOP TSSOP A4RL RL4B ABMS 4YMXXX RL4B CAT5114VI YMP CAT5114LI YMXXXX YMXXXX A4 = Device Code R = Resistance: ABMS = CAT5114ZI−10−GT3 2 = 10 k(cid:2) ABMT = CAT5114ZI−50−GT3 4 = 50 k(cid:2) R = Resistance: ABTH = CAT5114ZI−00−GT3 5 = 100 k(cid:2) 2 = 10 k(cid:2) Y = Production Year (Last Digit) L = Assembly Location 4 = 50 k(cid:2) M = Production Month (1−9, O, N, D) 4 = Lead Finish − NiPdAu 5 = 100 k(cid:2) P = Product Revision Y = Production Year (last digit) L = Assembly Location M = Production Month (1−9, O, N, D) 4 = Lead Finish − NiPdAu XXX = Last Three Digits of Assembly B = Product Revision (Fixed as “B”) XXX = Lot Number CAT5114L = Device Code (PDIP) TDFN CAT5114V = Device Code (SOIC) EF = CAT5114VP2I10GT3 I = Temperature Range (Industrial) HF = CAT5114VP2I50GT3 Y = Production Year (Last Digit) M = Production Month (1−9, O, N, D) EFL GW = CAT5114VP2I00GT3 XXXX = Last Four Digits of Assembly Lot Number XXX L = Assembly Location YM XXX = Last Three Digits of Assembly Lot Number Y = Production Year (Last Digit) M = Production Month (1−9, O, N, D) Functional Diagram U/D 5−Bit 31 RH/VH RH/VH INC Up/Down VCC CS Counter 30 RH/VH 29 U/D 5−Bit Control Nonvolatile 28 INC Meamndory RW/VW Memory Po3s2it−ion TGraantsefser RAesrriastyor RW/VW CS Decoder Power On 2 Recall RL/VL Store and Recall 1 GND VCC Control GND Circuitry 0 RL/VL RW/VW RL/VL Figure 1. General Figure 2. Detailed Figure 3. Electronic Potentiometer Implementation http://onsemi.com 2

CAT5114 than the R terminal. Voltage applied to the R terminal Table 1. PIN DESCRIPTIONS H L cannot exceed the supply voltage, V or go below ground, CC Name Function GND. R and R are electrically interchangeable. L H INC Increment Control CS: Chip Select U/D Up/Down Control The chip select input is used to activate the control input of RH Potentiometer High Terminal the CAT5114 and is active low. When in a high state, activity GND Ground on the INC and U/D inputs will not affect or change the position of the wiper. RW Wiper Terminal RL Potentiometer Low Terminal Device Operation The CAT5114 operates like a digitally controlled CS Chip Select potentiometer with R and R equivalent to the high and low H L VCC Supply Voltage terminals and R equivalent to the mechanical W potentiometer’s wiper. There are 32 available tap positions Pin Function including the resistor end points, R and R . There are 31 H L INC: Increment Control Input resistor elements connected in series between the RH and RL terminals. The wiper terminal is connected to one of the 32 The INC input moves the wiper in the up or down direction taps and controlled by three inputs, INC, U/D and CS. These determined by the condition of the U/D input. inputs control a seven-bit up/down counter whose output is U/D: Up/Down Control Input decoded to select the wiper position. The selected wiper The U/D input controls the direction of the wiper movement. position can be stored in nonvolatile memory using the INC When in a high state and CS is low, any high-to-low and CS inputs. transition on INC will cause the wiper to move one With CS set LOW the CAT5114 is selected and will increment toward the RH terminal. When in a low state and respond to the U/D and INC inputs. HIGH to LOW CS is low, any high-to-low transition on INC will cause the transitions on INC will increment or decrement the wiper wiper to move one increment towards the RL terminal. (depending on the state of the U/D input and seven−bit R : High End Potentiometer Terminal counter). The wiper, when at either fixed terminal, acts like H its mechanical equivalent and does not move beyond the last R is the high end terminal of the potentiometer. It is not H position. The value of the counter is stored in nonvolatile required that this terminal be connected to a potential greater memory whenever CS transitions HIGH while the INC input than the R terminal. Voltage applied to the R terminal L H is also HIGH. When the CAT5114 is powered-down, the last cannot exceed the supply voltage, V or go below ground, CC stored wiper counter position is maintained in the GND. nonvolatile memory. When power is restored, the contents R : Wiper Potentiometer Terminal W of the memory are recalled and the counter is set to the value RW is the wiper terminal of the potentiometer. Its position on stored. the resistor array is controlled by the control inputs, INC, With INC set low, the CAT5114 may be de-selected and U/D and CS. Voltage applied to the RW terminal cannot powered down without storing the current wiper position in exceed the supply voltage, VCC or go below ground, GND. nonvolatile memory. This allows the system to always R : Low End Potentiometer Terminal power up to a preset value stored in nonvolatile memory. L R is the low end terminal of the potentiometer. It is not L required that this terminal be connected to a potential less http://onsemi.com 3

CAT5114 Table 2. OPERATION MODES INC CS U/D Operation High to Low Low High Wiper toward H High to Low Low Low Wiper toward L High Low to High X Store Wiper Position Low Low to High X No Store, Return to Standby X High X Standby RH CH RWI RW CW CL RL Figure 4. Potentiometer Equivalent Circuit Table 3. ABSOLUTE MAXIMUM RATINGS Parameters Ratings Units Supply Voltage V VCC to GND −0.5 to +7 Inputs V CS to GND −0.5 to VCC +0.5 INC to GND −0.5 to VCC +0.5 V U/D to GND −0.5 to VCC +0.5 V H to GND −0.5 to VCC +0.5 V L to GND −0.5 to VCC +0.5 V W to GND −0.5 to VCC +0.5 V Operating Ambient Temperature C Industrial (‘I’ suffix) −40 to +85 Junction Temperature +150 C Storage Temperature −65 to 150 C Lead Soldering (10 s max) +300 C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 4. RELIABILITY CHARACTERISTICS Symbol Parameter Test Method Min Typ Max Units VZAP (Note 1) ESD Susceptibility MIL−STD−883, Test Method 3015 2000 V ILTH (Notes 1, 2) Latch-up JEDEC Standard 17 100 mA TDR Data Retention MIL−STD−883, Test Method 1008 100 Years NEND Endurance MIL−STD−883, Test Method 1003 1,000,000 Stores 1. This parameter is tested initially and after a design or process change that affects the parameter. 2. Latch-up protection is provided for stresses up to 100 mA on address and data pins from −1 V to VCC + 1 V. http://onsemi.com 4

CAT5114 Table 5. DC ELECTRICAL CHARACTERISTICS (VCC = +2.5 V to +6 V unless otherwise specified) Symbol Parameter Conditions Min Typ Max Units POWER SUPPLY VCC Operating Voltage Range 2.5 – 6.0 V ICC1 Supply Current (Increment) VCC = 6 V, f = 1 MHz, IW = 0 – – 100 (cid:3)A VCC = 6 V, f = 250 kHz, IW = 0 – – 50 (cid:3)A ICC2 Supply Current (Write) Programming, VCC = 6 V – – 1000 (cid:3)A VCC = 3 V – – 500 (cid:3)A ISB1 (Note 4) Supply Current (Standby) CS = VCC − 0.3 V – − 1 (cid:3)A U/D, INC = VCC − 0.3 V or GND LOGIC INPUTS IIH Input Leakage Current VIN = VCC – – 10 (cid:3)A IIL Input Leakage Current VIN = 0 V – – −10 (cid:3)A VIH2 CMOS High Level Input Voltage 2.5 V  VCC  6 V VCC x 0.7 – VCC + 0.3 V VIL2 CMOS Low Level Input Voltage −0.3 – VCC x 0.2 V POTENTIOMETER CHARACTERISTICS RPOT Potentiometer Resistance −10 Device 10 k(cid:2) −50 Device 50 −00 Device 100 Pot. Resistance Tolerance 20 % VRH Voltage on RH pin 0 VCC V VRL Voltage on RL pin 0 VCC V Resolution 3.2 % INL Integral Linearity Error IW  2 (cid:3)A 0.5 1 LSB DNL Differential Linearity Error IW  2 (cid:3)A 0.25 0.5 LSB RWI Wiper Resistance VCC = 5 V, IW = 1 mA 70 200 (cid:2) VCC = 2.5 V, IW = 1 mA 150 400 (cid:2) IW Wiper Current −4.4 4.4 mA TCRPOT TC of Pot Resistance 300 ppm/C TCRATIO Ratiometric TC 20 ppm/C VN Noise 100 kHz / 1 kHz 8/24 nV/Hz CH/CL/CW Potentiometer Capacitances 8/8/25 pF fc Frequency Response Passive Attenuator, 10 k(cid:2) 1.7 MHz 3. This parameter is tested initially and after a design or process change that affects the parameter. 4. Latch−up protection is provided for stresses up to 100 mA on address and data pins from −1 V to VCC + 1 V. 5. IW = source or sink. 6. These parameters are periodically sampled and are not 100% tested. http://onsemi.com 5

CAT5114 Table 6. AC TEST CONDITIONS VCC Range 2.5 V  VCC  6 V Input Pulse Levels 0.2 x VCC to 0.7 x VCC Input Rise and Fall Times 10 ns Input Reference Levels 0.5 x VCC Table 7. AC OPERATING CHARACTERISTICS (VCC = +2.5 V to +6.0 V, VH = VCC, VL = 0 V, unless otherwise specified) Symbol Parameter Min Typ (Note 7) Max Units tCI CS to INC Setup 100 − − ns tDI U/D to INC Setup 50 − − ns tID U/D to INC Hold 100 − − ns tIL INC LOW Period 250 − − ns tIH INC HIGH Period 250 − − ns tIC INC Inactive to CS Inactive 1 − − (cid:3)s tCPH CS Deselect Time (NO STORE) 100 − − ns tCPH CS Deselect Time (STORE) 10 − − ms tIW INC to VOUT Change − 1 5 (cid:3)s tCYC INC Cycle Time 1 − − (cid:3)s tR, tF (Note 8) INC Input Rise and Fall Time − − 500 (cid:3)s tPU (Note 8) Power-up to Wiper Stable – – 1 ms tWR Store Cycle – 5 10 ms 7. Typical values are for TA = 25C and nominal supply voltage. 8. This parameter is periodically sampled and not 100% tested. 9. MI in the A.C. Timing diagram refers to the minimum incremental change in the W output due to a change in the wiper position. CS (store) tCYC tCI tIL tIH tIC tCPH 90% 90% INC 10% tDI tID tF tR U/D tIW MI(3) RW Figure 5. A.C. Timing http://onsemi.com 6

CAT5114 APPLICATIONS INFORMATION (a) resistive divider (b) variable resistance (c) two−port Figure 6. Potentiometer Configuration Applications V1 (−) 3 + A1 1 R3 R4 +5 V +5 V 2 – 8 R1 2 2+5 V8 R2 9 –+5 V4A3 71 DigitalPOT RA 6 pRPOT 74 8 71 DigitalPOT R1R2 10 + 11 8 VO 4 RB 3 5 (1−p)RPOT 555 3 CAT45113/5114 6 – A2 R3 R4 +2.5 V CAT5114 R2 6 5 V2 (+) 5 + 7 AR12 == AR23 == AR34 == 15/ 4k L(cid:2)M6064 C 00..00013 (cid:3) (cid:3)FF 2 1 0.01 (cid:3)F RPOT = 10 k(cid:2) Figure 7. Programmable Instrumentation Figure 8. Programmable Sq. Wave Oscillator (555) Amplifier +5 V 100 k(cid:2) 8 2 1 gitalOT CAT5113/5114 VOUT VO (REG) 7 DiP 4 VIN (UNREG) 2952 R1 11 k(cid:2) 0.1 (cid:3)F 6.8 (cid:3)F pR (1−p)R SHUTDOWN SD FB 1.23 V 330 (cid:2) 330 (cid:2) 1 M(cid:2) GND R2 65 3 +5 V 1 (cid:3)F 820 (cid:2) 2 +5 V +5 V 271 DigitalPOT8 CAT5113/5114 5 3R103 k(cid:2) IS 3 +– 47 6A1 10 k 32 +– 47 6A2 VO 4 6 LT1097 +2.5 V Figure 9. Programmable Voltage Regulator Figure 10. Programmable I to V Convertor http://onsemi.com 7

CAT5114 C1 0.001 (cid:3)F 1R030 k(cid:2) 1 (cid:3)F R1 C2 +5 V 2 VS – 7 +5 V 50 k(cid:2) 0.001 (cid:3)F + 6 VO 8 R2 3 4 2 10 k(cid:2) A1 1 gitalOT 7 DiP +2.5 V 4 CAT5113/5114 Figure 11. Programmable Bandpass Filter +5 V IC1 393 74HICC2132 2 VLL R1 – 1 OSC CLO + 3 R2 6 10 k(cid:2) CHI 7 – 0.1 (cid:3)F R3 + 5 VUL +5 V IC3 +5 V CAT5114 +5 V 6 8 5 2 10 k(cid:2) – 71 DigitalPOT 3 + AI 2.5  VO  5 V VO 4 IC4 VS +2.5 V 0  VS  2.5 V Figure 12. Automatic Gain Control http://onsemi.com 8

CAT5114 Table 8. ORDERING INFORMATION Orderable Part Numbers Resistance Values (k(cid:2)) Package−Pin Lead Finish Shipping† CAT5114LI−10−G 10 CAT5114LI−50−G 50 PDIP−8 NiPdAu 50 Units / Rail CAT5114LI−00−G 100 CAT5114VI−10−GT3 10 CAT5114VI−50−GT3 50 SOIC−8 NiPdAu 100 Units / Rail CAT5114VI−00−GT3 100 CAT5114VP2I10GT3 (Notes 10, 11) 10 TDFN−8 CAT5114VP2I50GT3 (Notes 10, 11) 50 NiPdAu 3000 / Tape & Reel 2 x 3 mm CAT5114VP2I00GT3 (Notes 10, 11) 100 CAT5114YI−10−GT3 10 CAT5114YI−50−GT3 50 TSSOP−8 NiPdAu 3000 / Tape & Reel CAT5114YI−00−GT3 100 CAT5114ZI−10−GT3 10 CAT5114ZI−50−GT3 50 MSOP−8 NiPdAu 96 Units / Rail CAT5114ZI−00−GT3 100 †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 10.Contact factory for package availability. 11.Part number is not exactly the same as the “Example of Ordering Information” shown above. For the indicated part numbers there are NO hyphens in the orderable part numbers. 12.All packages are RoHS-compliant (Pb-Free, Halogen-Free). 13.The standard lead finish is NiPdAu. 14.For additional package and temperature options, please contact your nearest ON Semiconductor Sales office. http://onsemi.com 9

CAT5114 PACKAGE DIMENSIONS PDIP−8, 300 mils CASE 646AA ISSUE A SYMBOL MIN NOM MAX A 5.33 A1 0.38 A2 2.92 3.30 4.95 b 0.36 0.46 0.56 E1 b2 1.14 1.52 1.78 c 0.20 0.25 0.36 D 9.02 9.27 10.16 E 7.62 7.87 8.25 E1 6.10 6.35 7.11 e 2.54 BSC eB 7.87 10.92 PIN # 1 L 2.92 3.30 3.80 IDENTIFICATION D TOP VIEW E A2 A A1 c b2 L eB e b SIDE VIEW END VIEW Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MS-001. http://onsemi.com 10

CAT5114 PACKAGE DIMENSIONS SOIC 8, 150 mils CASE 751BD ISSUE O SYMBOL MIN NOM MAX A 1.35 1.75 A1 0.10 0.25 b 0.33 0.51 c 0.19 0.25 E1 E D 4.80 5.00 E 5.80 6.20 E1 3.80 4.00 e 1.27 BSC h 0.25 0.50 L 0.40 1.27 PIN # 1 IDENTIFICATION θ 0º 8º TOP VIEW D h A1 θ A c e b L SIDE VIEW END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. http://onsemi.com 11

CAT5114 PACKAGE DIMENSIONS MSOP 8, 3x3 CASE 846AD ISSUE O SYMBOL MIN NOM MAX A 1.10 A1 0.05 0.10 0.15 A2 0.75 0.85 0.95 b 0.22 0.38 c 0.13 0.23 E E1 D 2.90 3.00 3.10 E 4.80 4.90 5.00 E1 2.90 3.00 3.10 e 0.65 BSC L 0.40 0.60 0.80 L1 0.95 REF L2 0.25 BSC θ 0º 6º TOP VIEW D A A2 DETAIL A A1 e b c SIDE VIEW END VIEW (cid:4) L2 Notes: L (1) All dimensions are in millimeters. Angles in degrees. L1 (2) Complies with JEDEC MO-187. DETAIL A http://onsemi.com 12

CAT5114 PACKAGE DIMENSIONS TSSOP8, 4.4x3 CASE 948AL ISSUE O b SYMBOL MIN NOM MAX A 1.20 A1 0.05 0.15 A2 0.80 0.90 1.05 b 0.19 0.30 E1 E c 0.09 0.20 D 2.90 3.00 3.10 E 6.30 6.40 6.50 E1 4.30 4.40 4.50 e 0.65 BSC L 1.00 REF L1 0.50 0.60 0.75 θ 0º 8º e TOP VIEW D A2 A (cid:4)1 c A1 L1 L SIDE VIEW END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153. http://onsemi.com 13

CAT5114 PACKAGE DIMENSIONS TDFN8, 2x3 CASE 511AK ISSUE A D A e b E E2 PIN#1 IDENTIFICATION A1 PIN#1 INDEX AREA D2 L TOP VIEW SIDE VIEW BOTTOM VIEW SYMBOL MIN NOM MAX A 0.70 0.75 0.80 A1 0.00 0.02 0.05 A2 A2 0.45 0.55 0.65 A3 0.20 REF A3 b 0.20 0.25 0.30 D 1.90 2.00 2.10 FRONT VIEW D2 1.30 1.40 1.50 E 2.90 3.00 3.10 E2 1.20 1.30 1.40 e 0.50 TYP L 0.20 0.30 0.40 Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MO-229. http://onsemi.com 14

CAT5114 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 5163, Denver, Colorado 80217 USA Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910 Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Japan Customer Focus Center For additional information, please contact your local Email: orderlit@onsemi.com Phone: 81−3−5817−1050 Sales Representative http://onsemi.com CAT5114/D 15