CAT34C02 EEPROM Serial 2-Kb I2C for(cid:2)DDR2 DIMM SPD Description The CAT34C02 is a EEPROM Serial 2−Kb I2C, internally organized as 16 pages of 16 bytes each, for a total of 256 bytes of 8 bits www.onsemi.com each. It features a 16−byte page write buffer and supports both the Standard (100 kHz) as well as Fast (400 kHz) I2C protocol. Write operations can be inhibited by taking the WP pin High (this protects the entire memory) or by setting an internal Write Protect flag via Software command (this protects the lower half of the memory). TSSOP−8 TDFN−8 In addition to Permanent Software Write Protection, the Y SUFFIX VP2 SUFFIX CAT34C02 also features JEDEC compatible Reversible Software CASE 948AL CASE 511AK Write Protection for DDR2 Serial Presence Detect (SPD) applications operating over the 1.7 V to 3.6 V supply voltage range. The CAT34C02 is fully backwards compatible with earlier DDR1 SPD applications operating over the 1.7 V to 5.5 V supply voltage range. UDFN−8 EP HU4 SUFFIX Features CASE 517AZ • Supports Standard and Fast I2C Protocol • 1.7 V to 5.5 V Supply Voltage Range • 16−Byte Page Write Buffer PIN CONFIGURATION • Hardware Write Protection for Entire Memory • A0 1 VCC Software Write Protection for Lower 128 Bytes • Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs A1 WP (SCL and SDA) A2 SCL • Low power CMOS Technology VSS SDA • 1,000,000 Program/Erase Cycles TSSOP (Y), TDFN (VP2), • UDFN (HU4) 100 Year Data Retention • Industrial and Extended Temperature Range For the location of Pin 1, please consult the • corresponding package drawing. This Device is Pb−Free, Halogen Free/BFR Free and RoHS Compliant* VCC PIN FUNCTION Pin Name Function SCL A0, A1, A2 Device Address Input SDA Serial Data Input/Output A2, A1, A0 CAT34C02 SDA SCL Serial Clock Input WP Write Protect Input WP VCC Power Supply VSS Ground VSS Figure 1. Functional Symbol *For additional information on our Pb−Free strategy and soldering details, please ORDERING INFORMATION download the ON Semiconductor Soldering and Mounting Techniques See detailed ordering and shipping information in the package Reference Manual, SOLDERRM/D. dimensions section on page 10 of this data sheet. © Semiconductor Components Industries, LLC, 2012 1 Publication Order Number: May, 2018 − Rev. 20 CAT34C02/D

CAT34C02 Table 1. ABSOLUTE MAXIMUM RATINGS Parameter Rating Unit Operating Temperature −45 to +130 °C Storage Temperature −65 to +150 °C Voltage on Any Pin with Respect to Ground (Note 1) −0.5 to +6.5 V Voltage on Pin A0 with Respect to Ground −0.5 to +10.5 V Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. The DC input voltage on any pin should not be lower than −0.5 V. During transitions, the voltage on any pin may undershoot to no less than −1.5 V, for periods of less than 20 ns. Table 2. RELIABILITY CHARACTERISTICS (Note 2) Symbol Parameter Min Units NEND (Note 3) Endurance 1,000,000 Program/ Erase Cycles TDR Data Retention 100 Years 2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100 and JEDEC test methods. 3. Page Mode, VCC = 5 V, 25°C Table 3. D.C. OPERATING CHARACTERISTICS (VCC = 1.7 V to 5.5 V, TA = −40°C to +85°C and VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.) Symbol Parameter Test Conditions Min Max Units ICC Supply Current VCC < 3.6 V, fSCL = 100 kHz 1 mA VCC > 3.6 V, fSCL = 400 kHz 2 ISB Standby Current All I/O Pins at GND or VCC TA = −40°C to +85°C 1 (cid:2)A VCC ≤ 3.3 V TA = −40°C to +85°C 3 VCC > 3.3 V TA = −40°C to +125°C 5 IL I/O Pin Leakage Pin at GND or VCC 2 (cid:2)A VIL Input Low Voltage −0.5 0.3 x VCC V VIH Input High Voltage 0.7 x VCC VCC + 0.5* VOL Output Low Voltage VCC > 2.5 V, IOL = 3 mA 0.4 VCC < 2.5 V, IOL = 1 mA 0.2 *VIH Max = 4 V for SDA and SCL when VCC = 0 V. Table 4. PIN IMPEDANCE CHARACTERISTICS (VCC = 1.7 V to 5.5 V, TA = −40°C to +85°C and VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.) Symbol Parameter Conditions Max Units CIN (Note 4) SDA I/O Pin Capacitance VIN = 0 V, f = 1.0 MHz, VCC = 5.0 V 8 pF Other Input Pins 6 IWP (Note 5) WP Input Current VIN < VIH, VCC = 5.5 V 130 (cid:2)A VIN < VIH, VCC = 3.6 V 120 VIN < VIH, VCC = 1.7 V 80 VIN > VIH 2 IA (Note 5) Address Input Current VIN < VIH, VCC = 5.5 V 50 (cid:2)A (A0, A1, A2) Product Rev H VIN < VIH, VCC = 3.6 V 35 VIN < VIH, VCC = 1.7 V 25 VIN > VIH 2 4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100 and JEDEC test methods. 5. When not driven, the WP, A0, A1 and A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively strong; therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power, as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull−down reverts to a weak current source. www.onsemi.com 2

CAT34C02 Table 5. A.C. CHARACTERISTICS (VCC = 1.7 V to 5.5 V, TA = −40°C to +85°C and VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C) (Note 6) Standard Fast Symbol Parameter Min Max Min Max Units FSCL Clock Frequency 100 400 kHz tHD:STA START Condition Hold Time 4 0.6 (cid:2)s tLOW Low Period of SCL Clock 4.7 1.3 (cid:2)s tHIGH High Period of SCL Clock 4 0.6 (cid:2)s tSU:STA START Condition Setup Time 4.7 0.6 (cid:2)s tHD:DAT Data Hold Time 0 0 (cid:2)s tSU:DAT Data Setup Time 250 100 ns tR (Note 7) SDA and SCL Rise Time 1000 300 ns tF (Note 7) SDA and SCL Fall Time 300 300 ns tSU:STO STOP Condition Setup Time 4 0.6 (cid:2)s tBUF Bus Free Time Between STOP and START 4.7 1.3 (cid:2)s tAA SCL Low to SDA Data Out 3.5 0.9 (cid:2)s tDH Data Out Hold Time 100 100 ns Ti (Note 7) Noise Pulse Filtered at SCL and SDA Inputs 100 100 ns tSU:WP WP Setup Time 0 0 (cid:2)s tHD:WP WP Hold Time 2.5 2.5 (cid:2)s tWR Write Cycle Time 5 5 ms tPU (Notes 7 & 8) Power−up to Ready Mode 1 1 ms 6. Test conditions according to “A.C. Test Conditions” table. 7. Tested initially and after a design or process change that affects this parameter. 8. tPU is the delay between the time VCC is stable and the device is ready to accept commands. Table 6. THERMAL CHARACTERISTICS (Air velocity = 0 m/s, 4 layers PCB) (Notes 9 and 10) Part Number Package (cid:2) (cid:2) Units JA JC CAT34C02Y TSSOP 64 37 °C/W CAT34C02VP2 TDFN 92 15 °C/W CAT34C02HU3 UDFN 101 18 °C/W CAT34C02HU4 UDFN 101 18 °C/W 9. TJ = TA + PD * (cid:3)JA, where: TJ is the Junction Temperature, TA the Ambient Temperature, PD the Power dissipation. Example: CAT34C02VP2, VCC = 3.0 V, ICCmax = 1 mA, TA = 85°C: TJ = 85°C + 3 mW * 92°C/W = 85.276°C. 10.TJ = TC + PD * (cid:3)JC, where: TC is the Case Temperature, etc. Table 7. A.C. TEST CONDITIONS Input Levels 0.2 VCC to 0.8 VCC Input Rise and Fall Times ≤ 50 ns Input Reference Levels 0.3 VCC, 0.7 VCC Output Reference Levels 0.5 VCC Output Load Current Source: IOL = 3 mA (VCC ≥ 2.5 V); IOL = 1 mA (VCC < 2.5 V); CL = 100 pF www.onsemi.com 3

CAT34C02 Power−On Reset (POR) device pulls down the SDA line to ‘transmit’ a ‘0’ and The CAT34C02 incorporates Power−On Reset (POR) releases it to ‘transmit’ a ‘1’. circuitry which protects the internal logic against powering Data transfer may be initiated only when the bus is not up in the wrong state. busy (see A.C. Characteristics). The CAT34C02 will power up into Standby mode after During data transfer, the SDA line must remain stable V exceeds the POR trigger level and will power down into while the SCL line is HIGH. An SDA transition while SCL CC Reset mode when V drops below the POR trigger level. is HIGH will be interpreted as a START or STOP condition CC This bi−directional POR feature protects the device against (Figure 2). ‘brown−out’ failure following a temporary loss of power. Start Pin Description The START condition precedes all commands. It consists of a HIGH to LOW transition on SDA while SCL is HIGH. SCL: The Serial Clock input pin accepts the Serial Clock The START acts as a ‘wake−up’ call to all receivers. Absent generated by the Master. a START, a Slave will not respond to commands. SDA: The Serial Data I/O pin receives input data and transmits data stored in EEPROM. In transmit mode, this pin Stop is open drain. Data is acquired on the positive edge, and is The STOP condition completes all commands. It consists delivered on the negative edge of SCL. of a LOW to HIGH transition on SDA while SCL is HIGH. A , A and A : The Address pins accept the device address. The STOP starts the internal Write cycle (when following a 0 1 2 These pins have on−chip pull−down resistors. Write command) or sends the Slave into standby mode (when following a Read command). WP: The Write Protect input pin inhibits all write operations, when pulled HIGH. This pin has an on−chip Device Addressing pull−down resistor. The Master initiates data transfer by creating a START condition on the bus. The Master then broadcasts an 8−bit Functional Description serial Slave address. The first 4 bits of the Slave address are The CAT34C02 supports the Inter−Integrated Circuit set to 1010, for normal Read/Write operations (Figure 3). (I2C) Bus data transmission protocol, which defines a device The next 3 bits, A , A and A , select one of 8 possible Slave that sends data to the bus as a transmitter and a device 2 1 0 devices. The last bit, R/W, specifies whether a Read (1) or receiving data as a receiver. Data flow is controlled by a Write (0) operation is to be performed. Master device, which generates the serial clock and all START and STOP conditions. The CAT34C02 acts as a Acknowledge Slave device. Master and Slave alternate as either After processing the Slave address, the Slave responds transmitter or receiver. Up to 8 devices may be connected to with an acknowledge (ACK) by pulling down the SDA line the bus as determined by the device address inputs A0, A1, during the 9th clock cycle (Figure 4). The Slave will also and A2. acknowledge the byte address and every data byte presented in Write mode. In Read mode the Slave shifts out a data byte, I2C Bus Protocol and then releases the SDA line during the 9th clock cycle. If The I2C bus consists of two ‘wires’, SCL and SDA. The the Master acknowledges the data, then the Slave continues two wires are connected to the V supply via pull−up CC transmitting. The Master terminates the session by not resistors. Master and Slave devices connect to the 2−wire acknowledging the last data byte (NoACK) and by sending bus via their respective SCL and SDA pins. The transmitting a STOP to the Slave. Bus timing is illustrated in Figure 5. SDA SCL START BIT STOP BIT Figure 2. Start/Stop Timing www.onsemi.com 4

CAT34C02 1 0 1 0 A2 A1 A0 R/W DEVICE ADDRESS Figure 3. Slave Address Bits BUS RELEASE DELAY (TRANSMITTER) BUS RELEASE DELAY (RECEIVER) SCL FROM 1 8 9 MASTER DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START ACK SETUP (≥ tSU:DAT) ACK DELAY (≤ tAA) Figure 4. Acknowledge Timing tF tHIGH tR tLOW tLOW SCL tSU:STA tHD:DAT tHD:STA tSU:DAT tSU:STO SDA IN tAA tDH tBUF SDA OUT Figure 5. Bus Timing Write Operations The internal byte address counter is automatically incremented after each data byte is loaded. If the Master Byte Write transmits more than 16 data bytes, then earlier bytes will be In Byte Write mode the Master sends a START, followed overwritten by later bytes in a ‘wrap−around’ fashion by Slave address, byte address and data to be written (within the selected page). The internal Write cycle starts (Figure 6). The Slave acknowledges all 3 bytes, and the immediately following the STOP. Master then follows up with a STOP, which in turn starts the internal Write operation (Figure 7). During internal Write, Acknowledge Polling the Slave will not acknowledge any Read or Write request Acknowledge polling can be used to determine if the from the Master. CAT34C02 is busy writing or is ready to accept commands. Polling is implemented by interrogating the device with a Page Write ‘Selective Read’ command (see READ OPERATIONS). The CAT34C02 contains 256 bytes of data, arranged in 16 The CAT34C02 will not acknowledge the Slave address, pages of 16 bytes each. A page is selected by the 4 most as long as internal Write is in progress. significant bits of the address byte following the Slave address, while the 4 least significant bits point to the byte Delivery State within the page. Up to 16 bytes can be written in one Write The CAT34C02 is shipped ‘unprotected’, i.e. neither SWP cycle (Figure 8). flag is set. The entire 2 kb memory is erased, i.e. all bytes are FFh. www.onsemi.com 5

CAT34C02 S T S BUS ACTIVITY: A SLAVE BYTE T MASTER R ADDRESS ADDRESS DATA O T P SDA LINE S P A A A C C C K K K Figure 6. Byte Write Timing SCL SDA 8th Bit ACK Byte n tWR STOP START ADDRESS CONDITION CONDITION Figure 7. Write Cycle Timing S T S BUS ACTIVITY: A SLAVE BYTE T MASTER R ADDRESS ADDRESS (n) DATA n DATA n+1 DATA n+P O T P SDA LINE S P A A A A A C C C C C K K K K K NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0 Figure 8. Page Write Timing BYTE ADDRESS DATA 1 8 9 1 8 SCL SDA A7 A0 D7 D0 tSU:WP WP tHD:WP Figure 9. WP Timing www.onsemi.com 6

CAT34C02 Read Operations The address counter can be initialized by performing a ‘dummy’ Write operation (Figure 11). Here the START is Immediate Address Read followed by the Slave address (with the R/W bit set to ‘0’) In standby mode, the CAT34C02 internal address counter and the desired byte address. Instead of following up with points to the data byte immediately following the last byte data, the Master then issues a 2nd START, followed by the accessed by a previous operation. If that ‘previous’ byte was ‘Immediate Address Read’ sequence, as described earlier. the last byte in memory, then the address counter will point to the 1st memory byte, etc. Sequential Read When, following a START, the CAT34C02 is presented If the Master acknowledges the 1st data byte transmitted with a Slave address containing a ‘1’ in the R/W bit position by the CAT34C02, then the device will continue (Figure 10), it will acknowledge (ACK) in the 9th clock cycle, transmitting as long as each data byte is acknowledged by and will then transmit data being pointed at by the internal the Master (Figure 12). If the end of memory is reached address counter. The Master can stop further transmission by during sequential Read, then the address counter will issuing a NoACK, followed by a STOP condition. ‘wrap−around’ to the beginning of memory, etc. Sequential Read works with either ‘Immediate Address Read’ or Selective Read ‘Selective Read’, the only difference being the starting byte The Read operation can also be started at an address address. different from the one stored in the internal address counter. S T S BUS ACTIVITY: A SLAVE T MASTER R ADDRESS O T P SDA LINE S P A N C DATA O K A C K SCL 8 9 SDA 8th Bit DATA OUT NO ACK STOP Figure 10. Immediate Address Read Timing S S T T S BUS ACTIVITY: A SLAVE BYTE A SLAVE T MASTER R ADDRESS ADDRESS (n) R ADDRESS O T T P SDA LINE S S P A A A N C C C DATA n O K K K A C K Figure 11. Selective Read Timing S BUS ACTIVITY: SLAVE T MASTER ADDRESS DATA n DATA n+1 DATA n+2 DATA n+x O P SDA LINE P A A A A N C C C C O K K K K A C Figure 12. Sequential Read Timing K www.onsemi.com 7

CAT34C02 Software Write Protection is set and with ACK if the flag is not set. Therefore, the The lower half of memory (first 128 bytes) can be Master can immediately follow up with a STOP, as there is protected against Write requests by setting one of two no meaningful data following the ACK interval (Figure 15). Software Write Protection (SWP) flags. Hardware Write Protection The Permanent Software Write Protection (PSWP) flag With the WP pin held HIGH, the entire memory, as well can be set or read while all address pins are at regular CMOS as the SWP flags are protected against Write operations, see levels (GND or V ), whereas the very high voltage V CC HV Memory Protection Map below. If the WP pin is left floating must be present on address pin A to set, clear or read the 0 or is grounded, it has no impact on the operation of the Reversible Software Write Protection (RSWP) flag. The CAT34C02. D.C. OPERATING CONDITIONS for RSWP operations The state of the WP pin is strobed on the last falling edge are shown in Table 8. The SWP commands are listed in Table 9. All commands of SCL immediately preceding the first data byte (Figure 9). are preceded by a START and terminated with a STOP, If the WP pin is HIGH during the strobe interval, the CAT34C02 will not acknowledge the data byte and the Write following the ACK or NoACK from the CAT34C02. All request will be rejected. SWP related Slave addresses use the pre−amble: 0110 (6h), instead of the regular 1010 (Ah) used for memory access. For PSWP commands, the three address pins can be at any FFH logic level, whereas for RSWP commands the address pins must be at pre−assigned logic levels. V is interpreted as HV logic ‘1’. The V condition must be established on pin A Hardware Write Protectable HV 0 (by connecting WP pin to before the START and maintained just beyond the STOP. VCC) Otherwise an RSWP request could be interpreted by the 7FH CAT34C02 as a PSWP request. The SWP Slave addresses follow the standard I2C Software Write Protectable convention, i.e. to read the state of the SWP flag, the LSB of (by setting the write protect flags) the Slave address must be ‘1’, and to set or clear a flag, it must be ‘0’. For Write commands a dummy byte address and 00H dummy data byte must be provided (Figure 14). In contrast Figure 13. Memory Protection Map to a regular memory Read, a SWP Read does not return Data. Instead the CAT34C02 will respond with NoACK if the flag Table 8. RSWP D.C. OPERATING CONDITIONS (Note 11) Symbol Parameter Test Conditions Min Max Units (cid:4)VHV A0 Overdrive (VHV − VCC) 1.7 V < VCC < 3.6 V 4.8 V IHVD A0 High Voltage Detector Current 0.1 mA VHV A0 Very High Voltage 7 10 V IHV A0 Input Current @ VHV 1 mA 11.To prevent damaging the CAT34C02 while applying VHV, it is strongly recommended to limit the power delivered to pin A0, by inserting a series resistor (> 1.5 k(cid:5)) between the supply and the input pin. The resistance is only limited by the combination of VHV and maximum IHVD. While the resistor can be omitted if VHV is clamped well below 10 V, it nevertheless provides simple protection against EOS events. As an example: VCC = 1.7 V, VHV = 8 V, 1.5 k(cid:5) < RS < 15 k(cid:5). www.onsemi.com 8

CAT34C02 Table 9. SWP COMMANDS Control Pin Levels Flag State (Note 12) (Note 13) Slave Address ACK Address ACK Data ACK Write Action WP A2 A1 A0 PSWP RSWP b7 to b4 b3 b2 b1 b0 ? Byte ? Byte ? Cycle X A2 A1 A0 1 X A2 A1 A0 X No Set GND A2 A1 A0 0 X A2 A1 A0 0 Yes X Yes X Yes Yes PSWP VCC A2 A1 A0 0 X A2 A1 A0 0 Yes X Yes X No No X A2 A1 A0 0 X A2 A1 A0 1 Yes X GND GND VHV 1 X 0 0 1 X No X GND GND VHV 0 1 0 0 1 X No Set RSWP GND GND GND VHV 0 0 0110 0 0 1 0 Yes X Yes X Yes Yes VCC GND GND VHV 0 0 0 0 1 0 Yes X Yes X No No X GND GND VHV 0 0 0 0 1 1 Yes X GND VCC VHV 1 X 0 1 1 X No Clear GND GND VCC VHV 0 X 0 1 1 0 Yes X Yes X Yes Yes RSWP VCC GND VCC VHV 0 X 0 1 1 0 Yes X Yes X No No X GND VCC VHV 0 X 0 1 1 1 Yes 12.Here A2, A1 and A0 are either at VCC or GND. 13.1 stands for ‘Set’, 0 stands for ‘Not Set’, X stands for ‘don’t care’. S T S BUS ACTIVITY: A SLAVE BYTE T MASTER R ADDRESS ADDRESS DATA O T P SDA LINE S XXXXXXXX XXXXXXXX P A A A N C C C or O K K K A X = Don’t Care C K Figure 14. Software Write Protect (Write) S T S BUS ACTIVITY: A SLAVE T MASTER R ADDRESS O T P SDA LINE S P A N C or O K A C K Figure 15. Software Write Protect (Read) www.onsemi.com 9

CAT34C02 Ordering Information Specific Device Lead Device Order Number Marking Package Type Temperature Range Finish Shipping† CAT34C02HU4EGT4A D1U UDFN−8 I = Industrial NiPdAu Tape & Reel, (−40°C to +85°C) 4,000 Units / Reel CAT34C02HU4I−GT4 D1U UDFN−8 I = Industrial NiPdAu Tape & Reel, (−40°C to +85°C) 4,000 Units / Reel CAT34C02HU4I−GTK D1U UDFN−8 I = Industrial NiPdAu Tape & Reel, (−40°C to +85°C) 4,000 Units / Reel CAT34C02HU4IGT4A D1U UDFN−8 I = Industrial NiPdAu Tape & Reel, (−40°C to +85°C) 4,000 Units / Reel CAT34C02VP2I−GT4 D1T TDFN−8 I = Industrial NiPdAu Tape & Reel, (−40°C to +85°C) 4,000 Units / Reel CAT34C02VP2IGT4A D1T TDFN−8 I = Industrial NiPdAu Tape & Reel, (−40°C to +85°C) 4,000 Units / Reel CAT34C02YI−GT5 34CH TSSOP−8 I = Industrial NiPdAu Tape & Reel, (−40°C to +85°C) 5,000 Units / Reel CAT34C02YI−GT5A 34CH TSSOP−8 I = Industrial NiPdAu Tape & Reel, (−40°C to +85°C) 5,000 Units / Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 14.All packages are RoHS−compliant (Lead−free, Halogen−free) 15.The standard lead finish is NiPdAu. 16.For Gresham ONLY die, please order the OPNs: CAT34C02YI−GT5A, CAT34C02VP2IGT4A, CAT34C02HU3IGT4A orCAT34C02HU4IGT4A. 17.For additional package and temperature options, please contact your nearest ON Semiconductor Sales office. ON Semiconductor is licensed by the Philips Corporation to carry the I2C bus protocol. www.onsemi.com 10

MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TDFN8, 2x3, 0.5P CASE 511AK 1 ISSUE B SCALE 2:1 DATE 18 MAR 2015 D A B L L NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. L1 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN DETAIL A 0.15 AND 0.25MM FROM THE TERMINAL TIP. ÇÇ ALTERNATE 4. COPLANARITY APPLIES TO THE EXPOSED PIN ONE E CONSTRUCTIONS PAD AS WELL AS THE TERMINALS. REFERENCE ÇÇ MILLIMETERS DIM MIN MAX 0.10 CÇÇ EXPOSED CuÇÇMOLD CMPD A 0.70 0.80 A1 0.00 0.05 ÇÉÇÉ A3 0.20 REF 0.10 C TOP VIEW b 0.20 0.30 D 2.00 BSC DETAIL B D2 1.30 1.50 DETAIL B A ALTERNATE E 3.00 BSC 0.10 C CONSTRUCTION E2 1.20 1.40 A3 e 0.50 BSC L 0.20 0.40 L1 −−− 0.15 0.08 C A1 GENERIC NOTE 4 SIDE VIEW C SPELAATNIENG MARKING DIAGRAM* 1 DETAIL A D2 L XXXXX 1 4 AWLYW(cid:2) XXXXX = Specific Device Code A = Assembly Location E2 WL = Wafer Lot Y = Year W = Work Week (cid:2) = Pb−Free Package 8 5 8X b *This information is generic. Please refer to e 0.10 M C A B device data sheet for actual part marking. BOTTOM VIEW 0.05 M C NOTE 3 Pmba−yF orre em ianyd incoatt obre, “pGre” soer nmt.icrodot “ (cid:2)”, RECOMMENDED SOLDERING FOOTPRINT* 1.56 8X 0.68 1.45 3.40 1 8X 0.30 0.50 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: 98AON34336E Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed STATUS: ON SEMICONDUCTOR STANDARD versions are uncontrolled except when stamped “CONTROLLED COPY” in red. REFERENCE: © Semiconductor Components Industries, LLC, 2002 http://onsemi.com Case Outline Number: October, D20E0S2C −R RIePvT. I0ON: TDFN8, 2X3, 0.5P 1 PAGE 1 OFX 2XX

DOCUMENT NUMBER: 98AON34336E PAGE 2 OF 2 ISSUE REVISION DATE O RELEASED FOR PRODUCTION FROM POD #TDFN8−008−01 TO ON SEMICON- 19 DEC 2008 DUCTOR. REQ. BY B. BERGMAN. A CHANGED DESCRIPTION FROM WDFN TO TDFN. 18 MAR 2009 B REDREW PACKAGE DRAWING TO ON SEMICONDUCTOR/JEDEC STANDARD. 18 MAR 2015 REQ. BY B. BECKER. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. © Semiconductor Components Industries, LLC, 2015 Case Outline Number: March, 2015 − Rev. B 511AK

MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS UDFN8, 2x3 EXTENDED PAD CASE 517AZ 1 ISSUE A SCALE 2:1 DATE 23 MAR 2015 D A B L L NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. L1 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN DETAIL A 0.15 AND 0.25MM FROM THE TERMINAL TIP. ÇÇ ALTERNATE 4. COPLANARITY APPLIES TO THE EXPOSED PIN ONE E CONSTRUCTIONS PAD AS WELL AS THE TERMINALS. REFERENCE ÇÇ MILLIMETERS DIM MIN MAX 0.10 C ÇÇ A3 A 0.45 0.55 A1 0.00 0.05 EXPOSED CuÉÉMOLD CMPD ÉÉÉ A3 0.13 REF 0.10 C TOP VIEW b 0.20 0.30 ÉÇÉÇ ÉÇÉÇÉÇ D 2.00 BSC D2 1.35 1.45 DETAIL B A1 E 3.00 BSC A E2 1.25 1.35 0.10 C A3 DETAIL B e 0.50 BSC ALTERNATE L 0.25 0.35 CONSTRUCTIONS L1 −−− 0.15 0.08 C A1 NOTE 4 SIDE VIEW C SPELAATNIENG GENERIC MARKING DIAGRAM* 1 DETAIL A D2 L XXXXX 1 4 AWLYW(cid:2) XXXXX = Specific Device Code A = Assembly Location E2 WL = Wafer Lot Y = Year W = Work Week 8 5 (cid:2) = Pb−Free Package 8X b *This information is generic. Please refer to e 0.10 M C A B device data sheet for actual part marking. BOTTOM VIEW 0.05 M C NOTE 3 Pb−Free indicator, “G” or microdot “ (cid:2)”, may or may not be present. RECOMMENDED SOLDERING FOOTPRINT* 1.56 8X 0.68 1.45 3.40 1 8X 0.30 0.50 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: 98AON42552E Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed STATUS: ON SEMICONDUCTOR STANDARD versions are uncontrolled except when stamped “CONTROLLED COPY” in red. REFERENCE: © Semiconductor Components Industries, LLC, 2002 http://onsemi.com Case Outline Number: October, D20E0S2C −R RIePvT. I0ON: UDFN8, 2X3 EXTENDED PAD 1 PAGE 1 OFX 2XX

DOCUMENT NUMBER: 98AON42552E PAGE 2 OF 2 ISSUE REVISION DATE O RELEASED FOR PRODUCTION FROM POD #UDFN8−046−01 TO ON SEMICON- 23 JUL 2009 DUCTOR. REQ. BY B. BERGMAN. A REDREW PACKAGE DRAWING TO ON SEMICONDUCTOR/JEDEC STANDARD. 23 MAR 2015 REQ. BY B. BECKER. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. © Semiconductor Components Industries, LLC, 2015 Case Outline Number: March, 2015 − Rev. A 517AZ

MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSSOP8, 4.4x3 CASE 948AL−01 ISSUE O DATE 19 DEC 2008 b SYMBOL MIN NOM MAX A 1.20 A1 0.05 0.15 A2 0.80 0.90 1.05 b 0.19 0.30 E1 E c 0.09 0.20 D 2.90 3.00 3.10 E 6.30 6.40 6.50 E1 4.30 4.40 4.50 e 0.65 BSC L 1.00 REF L1 0.50 0.60 0.75 θ 0º 8º e TOP VIEW D A2 A (cid:2)1 c A1 L1 L SIDE VIEW END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153. DOCUMENT NUMBER: 98AON34428E Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed STATUS: ON SEMICONDUCTOR STANDARD versions are uncontrolled except when stamped “CONTROLLED COPY” in red. REFERENCE: © Semiconductor Components Industries, LLC, 2002 http://onsemi.com Case Outline Number: October, D20E0S2C −R RIePvT. I0ON: TSSOP8, 4.4X3 1 PAGE 1 OFX 2XX

DOCUMENT NUMBER: 98AON34428E PAGE 2 OF 2 ISSUE REVISION DATE O RELEASED FOR PRODUCTION FROM POD #TSSOP8−004−01 TO ON 19 DEC 2008 SEMICONDUCTOR. REQ. BY B. BERGMAN. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. © Semiconductor Components Industries, LLC, 2008 Case Outline Number: December, 2008 − Rev. 01O 948AL

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com Literature Distribution Center for ON Semiconductor USA/Canada 19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910 Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada For additional information, please contact your local Email: orderlit@onsemi.com Sales Representative ◊

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