CAT25128 EEPROM Serial 128-Kb SPI Description The CAT25128 is a 128−Kb Serial CMOS EEPROM device internally organized as 16Kx8 bits. This features a 64−byte page write buffer and supports the Serial Peripheral Interface (SPI) protocol. The device is enabled through a Chip Select (CS) input. In addition, the www.onsemi.com required bus signals are clock input (SCK), data input (SI) and data output (SO) lines. The HOLD input may be used to pause any serial communication with the CAT25128 device. The device features software and hardware write protection, including partial as well as full array protection. SOIC−8 UDFN−8 On−Chip ECC (Error Correction Code) makes the device suitable V SUFFIX HU4 SUFFIX CASE 751BD CASE 517AZ for high reliability applications.* Features • 20 MHz SPI Compatible • 1.8 V to 5.5 V Supply Voltage Range • SPI Modes (0,0) & (1,1) TSSOP−8 SOIC−8 WIDE • Y SUFFIX X SUFFIX 64−byte Page Write Buffer CASE 948AL CASE 751BE • Additional Identification Page with Permanent Write Protection • Self−timed Write Cycle PIN CONFIGURATION • Hardware and Software Protection • Block Write Protection CS 1 VCC − Protect 1/4, 1/2 or Entire EEPROM Array SO HOLD • Low Power CMOS Technology WP SCK • 1,000,000 Program/Erase Cycles VSS SI • 100 Year Data Retention SOIC (X, V), TSSOP (Y), UDFN (HU4) • Industrial and Extended Temperature Range • 8−lead SOIC, TSSOP and 8−pad, UDFN Packages • This Device is Pb−Free, Halogen Free/BFR Free, and RoHS Compliant PIN FUNCTION VCC Pin Name† Function CS Chip Select SI SO Serial Data Output CS WP Write Protect WP CAT25128 SO HOLD VSS Ground SCK SI Serial Data Input SCK Serial Clock VSS HOLD Hold Transmission Input Figure 1. Functional Symbol VCC Power Supply †The exposed pad for the TDFN/UDFN packages can be left floating or connected to Ground. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 13 of this data sheet. © Semiconductor Components Industries, LLC, 2014 1 Publication Order Number: June, 2018 − Rev. 9 CAT25128/D

CAT25128 Table 1. ABSOLUTE MAXIMUM RATINGS Parameters Ratings Units Operating Temperature −45 to +130 °C Storage Temperature −65 to +150 °C Voltage on any Pin with Respect to Ground (Note 1) −0.5 to +6.5 V Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may undershoot to no less than −1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns. Table 2. RELIABILITY CHARACTERISTICS (Note 2) Symbol Parameter Min Units NEND (Notes 3, 4) Endurance 1,000,000 Program / Erase Cycles TDR Data Retention 100 Years 2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100 and JEDEC test methods. 3. Page Mode, VCC = 5 V, 25°C. 4. The new product revision (E) uses ECC (Error Correction Code) logic with 6 ECC bits to correct one bit error in 4 data bytes. Therefore, when a single byte has to be written, 4 bytes (including the ECC bits) are re−programmed. It is recommended to write by multiple of 4 bytes in order to benefit from the maximum number of write cycles. Table 3. D.C. OPERATING CHARACTERISTICS − MATURE PRODUCT (VCC = 1.8 V to 5.5 V, TA = −40°C to +85°C and VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.) Symbol Parameter Test Conditions Min Max Units ICCR Supply Current Read, VCC = 5.5 V, 10 MHz / −40°C to 85°C 2 mA (Read Mode) SO open 5 MHz / −40°C to 125°C 2 mA ICCW Supply Current Write, VCC = 5.5 V, 10 MHz / −40°C to 85°C 4 mA (Write Mode) SO open 5 MHz / −40°C to 125°C 4 mA ISB1 Standby Current VIN = GND or VCC, CS = VCC, TA = −40°C to +85°C 1 (cid:2)A WVCPC == V5C.5C ,V HOLD = VCC, TA = −40°C to +125°C 3 (cid:2)A ISB2 Standby Current VIN = GND or VCC, CS = VCC, TA = −40°C to +85°C 4 (cid:2)A WP = GND, HOLD = GND, VCC = 5.5 V TA = −40°C to +125°C 5 (cid:2)A IL Input Leakage Current VIN = GND or VCC −2 2 (cid:2)A ILO Output Leakage CS = VCC, TA = −40°C to +85°C −1 1 (cid:2)A Current VOUT = GND or VCC TA = −40°C to +125°C −1 2 (cid:2)A VIL Input Low Voltage −0.5 0.3 VCC V VIH Input High Voltage 0.7 VCC VCC + 0.5 V VOL1 Output Low Voltage VCC > 2.5 V, IOL = 3.0 mA 0.4 V VOH1 Output High Voltage VCC > 2.5 V, IOH = −1.6 mA VCC − 0.8V V VOL2 Output Low Voltage VCC > 1.8 V, IOL = 150 (cid:2)A 0.2 V VOH2 Output High Voltage VCC > 1.8 V, IOH = −100 (cid:2)A VCC − 0.2V V Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 2

CAT25128 Table 4. D.C. OPERATING CHARACTERISTICS − NEW PRODUCT (Rev E) (VCC = 1.8 V to 5.5 V, TA = −40°C to +85°C and VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.) Symbol Parameter Test Conditions Min Max Units ICCR Supply Current Read, SO open / VCC = 1.8 V, fSCK = 5 MHz 0.8 mA (Read Mode) −40°C to +85°C VCC = 2.5 V, fSCK =10 MHz 1.2 VCC = 5.5 V, fSCK = 20 MHz 3.0 Read, SO open / 2.5 V< VCC < 5.5 V, 2.0 −40°C to +125°C fSCK = 10 MHz ICCW Supply Current Write, CS = VCC/ VCC = 1.8 V 1.5 mA (Write Mode) −40°C to +85°C VCC = 2.5 V 2 VCC = 5.5 V 2 Write, CS = VCC/ 2.5 V< VCC < 5.5 V 2 −40°C to +125°C ISB1 Standby Current VIN = GND or VCC, TA = −40°C to +85°C 1 (cid:2)A CVCSC = = V 5C.C5 ,V WP = VCC, TA = −40°C to +125°C 3 ISB2 Standby Current VIN = GND or VCC, TA = −40°C to +85°C 3 (cid:2)A CVCSC = = V 5C.C5 ,V WP = GND, TA = −40°C to +125°C 5 IL Input Leakage Current VIN = GND or VCC −2 2 (cid:2)A ILO Output Leakage CS = VCC TA = −40°C to +85°C −1 1 (cid:2)A Current VOUT = GND or VCC TA = −40°C to +125°C −1 2 VIL1 Input Low Voltage VCC ≥ 2.5 V −0.5 0.3 VCC V VIH1 Input High Voltage VCC ≥ 2.5 V 0.7 VCC VCC + 0.5 V VIL2 Input Low Voltage VCC < 2.5 V −0.5 0.25 VCC V VIH2 Input High Voltage VCC < 2.5 V 0.75 VCC VCC + 0.5 V VOL1 Output Low Voltage VCC ≥ 2.5 V, IOL = 3.0 mA 0.4 V VOH1 Output High Voltage VCC ≥ 2.5 V, IOH = −1.6 mA VCC − 0.8 V V VOL2 Output Low Voltage VCC < 2.5 V, IOL = 150 (cid:2)A 0.2 V VOH2 Output High Voltage VCC < 2.5 V, IOH = −100 (cid:2)A VCC − 0.2 V V Table 5. PIN CAPACITANCE (Note 5) (TA = 25°C, f = 1.0 MHz, VCC = +5.0 V) Symbol Test Conditions Min Typ Max Units COUT Output Capacitance (SO) VOUT = 0 V 8 pF CIN Input Capacitance (CS, SCK, SI, WP, HOLD) VIN = 0 V 8 pF 5. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100 and JEDEC test methods. www.onsemi.com 3

CAT25128 Table 6. A.C. CHARACTERISTICS − MATURE PRODUCT (TA = −40°C to +85°C (Industrial) and TA = −40°C to +125°C (Extended).) (Notes 6, 9) VCC = 1.8 V − 5.5 V / −40(cid:2)C to +85(cid:2)C VCC = 2.5 V − 5.5 V VCC = 2.5 V − 5.5 V / −40(cid:2)C to +125(cid:2)C −40(cid:2)C to +85(cid:2)C Symbol Parameter Min Max Min Max Units fSCK Clock Frequency DC 5 DC 10 MHz tSU Data Setup Time 40 20 ns tH Data Hold Time 40 20 ns tWH SCK High Time 75 40 ns tWL SCK Low Time 75 40 ns tLZ HOLD to Output Low Z 50 25 ns tRI (Note 7) Input Rise Time 2 2 (cid:2)s tFI (Note 7) Input Fall Time 2 2 (cid:2)s tHD HOLD Setup Time 0 0 ns tCD HOLD Hold Time 10 10 ns tV Output Valid from Clock Low 75 40 ns tHO Output Hold Time 0 0 ns tDIS Output Disable Time 50 20 ns tHZ HOLD to Output High Z 100 25 ns tCS CS High Time 140 70 ns tCSS CS Setup Time 30 15 ns tCSH CS Hold Time 30 15 ns tCNS CS Inactive Setup Time 20 15 ns tCNH CS Inactive Hold Time 20 15 ns tWPS WP Setup Time 10 10 ns tWPH WP Hold Time 100 60 ns tWC (Note 8) Write Cycle Time 5 5 ms 6. AC Test Conditions: Input Pulse Voltages: 0.3 VCC to 0.7 VCC Input rise and fall times: ≤ 10 ns Input and output reference voltages: 0.5 VCC Output load: current source IOL max/IOH max; CL = 50 pF 7. This parameter is tested initially and after a design or process change that affects the parameter. 8. tWC is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle. 9. All Chip Select (CS) timing parameters are defined relative to the positive clock edge (Figure 2). tCSH timing specification is valid for die revision D and higher. The die revision D is identified by letter “D” or a dedicated marking code on top of the package. For previous product revision (Rev.C) the tCSH is defined relative to the negative clock edge. Table 7. POWER−UP TIMING (Notes 7, 10) Symbol Parameter Max Units tPUR Power−up to Read Operation 1 ms tPUW Power−up to Write Operation 1 ms 10.tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. www.onsemi.com 4

CAT25128 Table 8. A.C. CHARACTERISTICS – NEW PRODUCT (Rev E) (VCC = 1.8 V to 5.5 V, TA = −40°C to +85°C (Industrial) and VCC = 2.5 V to 5.5 V, TA = −40°C to +125°C, unless otherwise specified.) (Note 11) VCC = 1.8 V − 5.5 V VCC = 2.5 V − 5.5 V VCC = 4.5 V − 5.5 V −40(cid:2)C to +85(cid:2)C −40(cid:2)C to +125(cid:2)C −40(cid:2)C to +85(cid:2)C Symbol Parameter Min Max Min Max Min Max Units fSCK Clock Frequency DC 5 DC 10 DC 20 MHz tSU Data Setup Time 20 10 5 ns tH Data Hold Time 20 10 5 ns tWH SCK High Time 75 40 20 ns tWL SCK Low Time 75 40 20 ns tLZ HOLD to Output Low Z 50 25 25 ns tRI (Note 12) Input Rise Time 2 2 2 (cid:2)s tFI (Note 12) Input Fall Time 2 2 2 (cid:2)s tHD HOLD Setup Time 0 0 0 ns tCD HOLD Hold Time 10 10 5 ns tV Output Valid from Clock Low 75 40 20 ns tHO Output Hold Time 0 0 0 ns tDIS Output Disable Time 50 20 20 ns tHZ HOLD to Output High Z 100 25 25 ns tCS CS High Time 80 40 20 ns tCSS CS Setup Time 30 30 15 ns tCSH CS Hold Time 30 30 20 ns tCNS CS Inactive Setup Time 20 20 15 ns tCNH CS Inactive Hold Time 20 20 15 ns tWPS WP Setup Time 10 10 10 ns tWPH WP Hold Time 10 10 10 ns tWC (Note 13) Write Cycle Time 5 5 5 ms 11.AC Test Conditions: Input Pulse Voltages: 0.3 VCC to 0.7 VCC Input rise and fall times: ≤ 10 ns Input and output reference voltages: 0.5 VCC Output load: current source IOL max/IOH max; CL = 30 pF 12.This parameter is tested initially and after a design or process change that affects the parameter. 13.tWC is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle. Table 9. POWER−UP TIMING (Notes 12, 14) Symbol Parameter Min Max Units tPUR Power−up to Read Operation 0.1 1 ms tPUW Power−up to Write Operation 0.1 1 ms 14.tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. www.onsemi.com 5

CAT25128 Pin Description Functional Description The CAT25128 device supports the Serial Peripheral SI: The serial data input pin accepts op−codes, addresses Interface (SPI) bus protocol, modes (0,0) and (1,1). The and data. In SPI modes (0,0) and (1,1) input data is latched device contains an 8−bit instruction register. The instruction on the rising edge of the SCK clock input. set and associated op−codes are listed in Table10. SO: The serial data output pin is used to transfer data out of Reading data stored in the CAT25128 is accomplished by the device. In SPI modes (0,0) and (1,1) data is shifted out simply providing the READ command and an address. on the falling edge of the SCK clock. Writing to the CAT25128, in addition to a WRITE SCK: The serial clock input pin accepts the clock provided command, address and data, also requires enabling the by the host and used for synchronizing communication device for writing by first setting certain bits in a Status between host and CAT25128. Register, as will be explained later. CS: The chip select input pin is used to enable/disable the After a high to low transition on the CS input pin, the CAT25128. When CS is high, the SO output is tri−stated (high CAT25128 will accept any one of the six instruction impedance) and the device is in Standby Mode (unless an op−codes listed in Table 10 and will ignore all other possible internal write operation is in progress). Every communication 8−bit combinations. The communication protocol follows session between host and CAT25128 must be preceded by a the timing from Figure 2. high to low transition and concluded with a low to high The CAT25128, New Product Rev E features an transition of the CS input. additional Identification Page (64 bytes) which can be accessed for Read and Write operations when the IPL bit WP: The write protect input pin will allow all write from the Status Register is set to “1”. The user can also operations to the device when held high. When WP pin is tied low and the WPEN bit in the Status Register (refer to choose to make the Identification Page permanent write Status Register description, later in this Data Sheet) is set to protected. “1”, writing to the Status Register is disabled. Table 10. INSTRUCTION SET HOLD: The HOLD input pin is used to pause transmission Instruction Opcode Operation between host and CAT25128, without having to retransmit WREN 0000 0110 Enable Write Operations the entire sequence at a later time. To pause, HOLD must be taken low and to resume it must be taken back high, with the WRDI 0000 0100 Disable Write Operations SCK input low during both transitions. When not used for RDSR 0000 0101 Read Status Register pausing, it is recommended the HOLD input to be tied to WRSR 0000 0001 Write Status Register V , either directly or through a resistor. CC READ 0000 0011 Read Data from Memory WRITE 0000 0010 Write Data to Memory tCS CS tCSS tWH tWL tCNH tCSH tCNS SCK tSU tH ttRFII VALID SI IN tV tV tDIS tHO HI−Z VALID HI−Z SO OUT Figure 2. Synchronous Data Timing www.onsemi.com 6

CAT25128 Status Register The Status Register, as shown in Table 11, contains a protected sections of memory. While hardware write number of status and control bits. protection is active, only the non−block protected memory The RDY (Ready) bit indicates whether the device is busy can be written. Hardware write protection is disabled when with a write operation. This bit is automatically set to 1 during the WP pin is high or the WPEN bit is 0. The WPEN bit, WP an internal write cycle, and reset to 0 when the device is ready pin and WEL bit combine to either permit or inhibit Write to accept commands. For the host, this bit is read only. operations, as detailed in Table 13. The WEL (Write Enable Latch) bit is set/reset by the The IPL (Identification Page Latch) bit determines WREN/WRDI commands. When set to 1, the device is in a whether the additional Identification Page (IPL = 1) or main Write Enable state and when set to 0, the device is in a Write memory array (IPL = 0) can be accessed both for Read and Disable state. Write operations. The IPL bit is set by the user with the The BP0 and BP1 (Block Protect) bits determine which WRSR command and is volatile. The IPL bit is blocks are currently write protected. They are set by the user automatically reset after read/write operations. with the WRSR command and are non−volatile. The user is The LIP bit is set by the user with the WRSR command allowed to protect a quarter, one half or the entire memory, and is non−volatile. When set to 1, the Identification Page is by setting these bits according to Table 12. The protected permanently write protected (locked in Read−only mode). blocks then become read−only. Note: The IPL and LIP bits cannot be set to 1 using the The WPEN (Write Protect Enable) bit acts as an enable for same WRSR instruction. If the user attempts to set (“1”) the WP pin. Hardware write protection is enabled when the both the IPL and LIP bit in the same time, these bits cannot WP pin is low and the WPEN bit is 1. This condition be written and therefore they will remain unchanged. prevents writing to the status register and to the block Table 11. STATUS REGISTER 7 6 5 4 3 2 1 0 WPEN IPL* 0 LIP* BP1 BP0 WEL RDY *The IPL and LIP bits are available for the New Product only. The Status Register bit 6 and bit 4 are set to “0” for the older product revisions. Table 12. BLOCK PROTECTION BITS Status Register Bits BP1 BP0 Array Address Protected Protection 0 0 None No Protection 0 1 3000−3FFF Quarter Array Protection 1 0 2000−3FFF Half Array Protection 1 1 0000−3FFF Full Array Protection Table 13. WRITE PROTECT CONDITIONS WPEN WP WEL Protected Blocks Unprotected Blocks Status Register 0 X 0 Protected Protected Protected 0 X 1 Protected Writable Writable 1 Low 0 Protected Protected Protected 1 Low 1 Protected Writable Protected X High 0 Protected Protected Protected X High 1 Protected Writable Writable www.onsemi.com 7

CAT25128 WRITE OPERATIONS The CAT25128 device powers up into a write disable instruction to the CAT25128. Care must be taken to take the state. The device contains a Write Enable Latch (WEL) CS input high after the WREN instruction, as otherwise the which must be set before attempting to write to the memory Write Enable Latch will not be properly set. WREN timing array or to the status register. In addition, the address of the is illustrated in Figure 3. The WREN instruction must be memory location(s) to be written must be outside the sent prior to any WRITE or WRSR instruction. protected area, as defined by BP0 and BP1 bits from the The internal write enable latch is reset by sending the status register. WRDI instruction as shown in Figure 4. Disabling write operations by resetting the WEL bit, will protect the device Write Enable and Write Disable against inadvertent writes. The internal Write Enable Latch and the corresponding Status Register WEL bit are set by sending the WREN CS SCK SI 0 0 0 0 0 1 1 0 HIGH IMPEDANCE SO Dashed Line = mode (1, 1) Figure 3. WREN Timing CS SCK SI 0 0 0 0 0 1 0 0 HIGH IMPEDANCE SO Dashed Line = mode (1, 1) Figure 4. WRDI Timing www.onsemi.com 8

CAT25128 Byte Write Following completion of the write cycle, the CAT25128 is Once the WEL bit is set, the user may execute a write automatically returned to the write disable state. sequence, by sending a WRITE instruction, a 16−bit address and data as shown in Figure 5. Only 14 significant address Write Identification Page The additional 64−byte Identification Page (IP) can be bits are used by the CAT25128. The rest are don’t care bits, written with user data using the same Write commands as shown in Table 14. Internal programming will start after the low to high CS transition. During an internal write cycle, sequence as used for Page Write to the main memory array all commands, except for RDSR (Read Status Register) will (Figure6). The IPL bit from the Status Register must be set be ignored. The RDY bit will indicate if the internal write (IPL = 1) using the WRSR instruction, before attempting to write to the IP. cycle is in progress (RDY high), or the device is ready to The address bits [A15:A6] are Don’t Care and the accept commands (RDY low). [A5:A0] bits define the byte address within the Page Write Identification Page. In addition, the Byte Address must point After sending the first data byte to the CAT25128, the host to a location outside the protected area defined by the BP1, may continue sending data, up to a total of 64 bytes, BP0 bits from the Status Register. When the full memory according to timing shown in Figure 6. After each data byte, array is write protected (BP1, BP0 = 1,1), the write the lower order address bits are automatically incremented, instruction to the IP is not accepted and not executed. while the higher order address bits (page address) remain Also, the write to the IP is not accepted if the LIP bit from unchanged. If during this process the end of page is the Status Register is set to 1 (the page is locked in exceeded, then loading will “roll over” to the first byte in the Read−only mode). page, thus possibly overwriting previously loaded data. Table 14. BYTE ADDRESS Address Significant Bits Address Don’t Care Bits # Address Clock Pulses Main Memory Array A13 − A0 A15 − A14 16 Identification Page* A5 − A0 A15 − A6 16 *New Product only. CS 0 1 2 3 4 5 6 7 8 21 22 23 24 25 26 27 28 29 30 31 SCK OPCODE BYTE ADDRESS* DATA IN SI 0 0 0 0 0 0 1 0 AN A0 D7 D6 D5 D4 D3 D2 D1 D0 HIGH IMPEDANCE SO Dashed Line = mode (1, 1) * Please check the Byte Address Table (Table 14) Figure 5. Byte WRITE Timing CS 0 1 2 3 4 5 6 7 8 21 22 23 24−31 32−39 24+(N−1)x8−1 .. 24+(N−1)x8 SCK 24+Nx8−1 OPCODE BYTE ADDRESS* DATA IN Data Byte N SI 0 0 0 0 0 0 1 0 AN A0 7..1 0 Data Data Data Byte 1 Byte 2 Byte 3 HIGH IMPEDANCE SO Dashed Line = mode (1, 1) * Please check the Byte Address Table (Table 14) Figure 6. Page WRITE Timing www.onsemi.com 9

CAT25128 Write Status Register Write Protection The Status Register is written by sending a WRSR The Write Protect (WP) pin can be used to protect the instruction according to timing shown in Figure 7. Only bits Block Protect bits BP0 and BP1 against being inadvertently 2, 3, 4, 6 and 7 can be written using the WRSR command. altered. When WP is low and the WPEN bit is set to “1”, write operations to the Status Register are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the Status Register. The WP pin function is blocked when the WPEN bit is set to “0”. The WP input timing is shown in Figure 8. CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCK OPCODE DATA IN SI 0 0 0 0 0 0 0 1 7 6 5 4 3 2 1 0 MSB HIGH IMPEDANCE SO Dashed Line = mode (1, 1) Figure 7. WRSR Timing tWPS tWPH CS SCK WP WP Dashed Line = mode (1, 1) Figure 8. WP Timing www.onsemi.com 10

CAT25128 READ OPERATIONS Read from Memory Array address register defined by [A5:A0] bits is automatically To read from memory, the host sends a READ instruction incremented and the next data byte from the IP is shifted out. followed by a 16−bit address (see Table 14 for the number The byte address must not exceed the 64−byte page of significant address bits). boundary. After receiving the last address bit, the CAT25128 will respond by shifting out data on the SO pin (as shown in Read Status Register Figure9). Sequentially stored data can be read out by simply To read the status register, the host simply sends a RDSR continuing to run the clock. The internal address pointer is command. After receiving the last bit of the command, the automatically incremented to the next higher address as data CAT25128 will shift out the contents of the status register on the SO pin (Figure 10). The status register may be read at is shifted out. After reaching the highest memory address, any time, including during an internal write cycle. While the the address counter “rolls over” to the lowest memory internal write cycle is in progress, the RDSR command will address, and the read cycle can be continued indefinitely. output the full content of the status register (New product, The read operation is terminated by taking CS high. Rev. E) or the RDY (Ready) bit only (i.e., data out = FFh) for Read Identification Page previous product revisions C, D (Mature product). For easy Reading the additional 64−byte Identification Page (IP) is detection of the internal write cycle completion, both during achieved using the same Read command sequence as used writing to the memory array and to the status register, we for Read from main memory array (Figure 9). The IPL bit recommend sampling the RDY bit only through the polling from the Status Register must be set (IPL = 1) before routine. After detecting the RDY bit “0”, the next RDSR attempting to read from the IP. The [A5:A0] are the address instruction will always output the expected content of the significant bits that point to the data byte shifted out on the status register. SO pin. If the CS continues to be held low, the internal CS 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 SCK OPCODE BYTE ADDRESS* SI 0 0 0 0 0 0 1 1 AN A0 DATA OUT HIGH IMPEDANCE SO 7 6 5 4 3 2 1 0 Dashed Line = mode (1, 1) MSB * Please check the Byte Address Table (Table 14) Figure 9. READ Timing CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SCK OPCODE SI 0 0 0 0 0 1 0 1 DATA OUT HIGH IMPEDANCE SO 7 6 5 4 3 2 1 0 Dashed Line = mode (1, 1) MSB Figure 10. RDSR Timing www.onsemi.com 11

CAT25128 Hold Operation The CAT25128 device powers up in a write disable state The HOLD input can be used to pause communication and in a low power standby mode. A WREN instruction between host and CAT25128. To pause, HOLD must be must be issued prior to any writes to the device. taken low while SCK is low (Figure 11). During the hold After power up, the CS pin must be brought low to enter condition the device must remain selected (CS low). During a ready state and receive an instruction. After a successful the pause, the data output pin (SO) is tri−stated (high byte/page write or status register write, the device goes into impedance) and SI transitions are ignored. To resume a write disable mode. The CS input must be set high after the communication, HOLD must be taken high while SCK is low. proper number of clock cycles to start the internal write cycle. Access to the memory array during an internal write Design Considerations cycle is ignored and programming is continued. Any invalid The CAT25128 device incorporates Power−On Reset op−code will be ignored and the serial output pin (SO) will (POR) circuitry which protects the internal logic against remain in the high impedance state. powering up in the wrong state. The device will power up into Standby mode after V exceeds the POR trigger level Delivery State CC and will power down into Reset mode when VCC drops The CAT25128 is shipped erased, i.e., all bytes are FFh. below the POR trigger level. This bi−directional POR behavior protects the device against ‘brown−out’ failure following a temporary loss of power. CS tCD tCD SCK tHD HOLD tHD tHZ HIGH IMPEDANCE SO tLZ Dashed Line = mode (1, 1) Figure 11. HOLD Timing www.onsemi.com 12

CAT25128 Table 15. ORDERING INFORMATION (Notes 15 − 18) Specific De- vice Mark- Package Device Order Number ing* Type Temperature Range Lead Finish Shipping† CAT25128YI−GT3 S28E TSSOP−8 I = Industrial NiPdAu Tape & Reel, (−40°C to +85°C) 3,000 Units / Reel CAT25128YE−GT3 S28E TSSOP−8 E = Extended NiPdAu Tape & Reel, (−40°C to +125°C) 3,000 Units / Reel CAT25128HU4I−GT3 S7U UDFN−8 I = Industrial NiPdAu Tape & Reel, (−40°C to +85°C) 3,000 Units / Reel CAT25128HU4E−GT3 S7U UDFN−8 E = Extended NiPdAu Tape & Reel, (−40°C to +125°C) 3,000 Units / Reel CAT25128VI−GT3 25128E SOIC−8, I = Industrial NiPdAu Tape & Reel, JEDEC (−40°C to +85°C) 3,000 Units / Reel CAT25128VE−GT3 25128E SOIC−8, E = Extended NiPdAu Tape & Reel, JEDEC (−40°C to +125°C) 3,000 Units / Reel CAT25128XI−T2 25128E SOIC−8, I = Industrial Matte−Tin Tape & Reel, EIAJ (−40°C to +85°C) 2,000 Units / Reel CAT25128XE−T2 25128E SOIC−8, E = Extended Matte−Tin Tape & Reel, EIAJ (−40°C to +125°C) 2,000 Units / Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 15.All packages are RoHS−compliant (Lead-free, Halogen-free). 16.The standard lead finish is NiPdAu. 17.For additional package and temperature options, please contact your nearest ON Semiconductor Sales office. 18.For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device Nomenclature document, TND310/D, available at www.onsemi.com www.onsemi.com 13

MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS UDFN8, 2x3 EXTENDED PAD CASE 517AZ 1 ISSUE A SCALE 2:1 DATE 23 MAR 2015 D A B L L NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. L1 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN DETAIL A 0.15 AND 0.25MM FROM THE TERMINAL TIP. ÇÇ ALTERNATE 4. COPLANARITY APPLIES TO THE EXPOSED PIN ONE E CONSTRUCTIONS PAD AS WELL AS THE TERMINALS. REFERENCE ÇÇ MILLIMETERS DIM MIN MAX 0.10 C ÇÇ A3 A 0.45 0.55 A1 0.00 0.05 EXPOSED CuÉÉMOLD CMPD ÉÉÉ A3 0.13 REF 0.10 C TOP VIEW b 0.20 0.30 ÉÇÉÇ ÉÇÉÇÉÇ D 2.00 BSC D2 1.35 1.45 DETAIL B A1 E 3.00 BSC A E2 1.25 1.35 0.10 C A3 DETAIL B e 0.50 BSC ALTERNATE L 0.25 0.35 CONSTRUCTIONS L1 −−− 0.15 0.08 C A1 NOTE 4 SIDE VIEW C SPELAATNIENG GENERIC MARKING DIAGRAM* 1 DETAIL A D2 L XXXXX 1 4 AWLYW(cid:2) XXXXX = Specific Device Code A = Assembly Location E2 WL = Wafer Lot Y = Year W = Work Week 8 5 (cid:2) = Pb−Free Package 8X b *This information is generic. Please refer to e 0.10 M C A B device data sheet for actual part marking. BOTTOM VIEW 0.05 M C NOTE 3 Pb−Free indicator, “G” or microdot “ (cid:2)”, may or may not be present. RECOMMENDED SOLDERING FOOTPRINT* 1.56 8X 0.68 1.45 3.40 1 8X 0.30 0.50 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. DOCUMENT NUMBER: 98AON42552E Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed STATUS: ON SEMICONDUCTOR STANDARD versions are uncontrolled except when stamped “CONTROLLED COPY” in red. REFERENCE: © Semiconductor Components Industries, LLC, 2002 http://onsemi.com Case Outline Number: October, D20E0S2C −R RIePvT. I0ON: UDFN8, 2X3 EXTENDED PAD 1 PAGE 1 OFX 2XX

DOCUMENT NUMBER: 98AON42552E PAGE 2 OF 2 ISSUE REVISION DATE O RELEASED FOR PRODUCTION FROM POD #UDFN8−046−01 TO ON SEMICON- 23 JUL 2009 DUCTOR. REQ. BY B. BERGMAN. A REDREW PACKAGE DRAWING TO ON SEMICONDUCTOR/JEDEC STANDARD. 23 MAR 2015 REQ. BY B. BECKER. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. © Semiconductor Components Industries, LLC, 2015 Case Outline Number: March, 2015 − Rev. A 517AZ

MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC 8, 150 mils CASE 751BD−01 ISSUE O DATE 19 DEC 2008 SYMBOL MIN NOM MAX A 1.35 1.75 A1 0.10 0.25 b 0.33 0.51 c 0.19 0.25 E1 E D 4.80 5.00 E 5.80 6.20 E1 3.80 4.00 e 1.27 BSC h 0.25 0.50 L 0.40 1.27 PIN # 1 IDENTIFICATION θ 0º 8º TOP VIEW D h A1 θ A c e b L SIDE VIEW END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. DOCUMENT NUMBER: 98AON34272E Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed STATUS: ON SEMICONDUCTOR STANDARD versions are uncontrolled except when stamped “CONTROLLED COPY” in red. REFERENCE: © Semiconductor Components Industries, LLC, 2002 http://onsemi.com Case Outline Number: October, D20E0S2C −R RIePvT. I0ON: SOIC 8, 150 MILS 1 PAGE 1 OFX 2XX

DOCUMENT NUMBER: 98AON34272E PAGE 2 OF 2 ISSUE REVISION DATE O RELEASED FOR PRODUCTION FROM POD #SOIC8−002−01 TO ON 19 DEC 2008 SEMICONDUCTOR. REQ. BY B. BERGMAN. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. © Semiconductor Components Industries, LLC, 2008 Case Outline Number: December, 2008 − Rev. 01O 751BD

MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−8, 208 mils CASE 751BE−01 ISSUE O DATE 19 DEC 2008 SYMBOL MIN NOM MAX A 2.03 A1 0.05 0.25 b 0.36 0.48 c 0.19 0.25 E1 E D 5.13 5.33 E 7.75 8.26 E1 5.13 5.38 e 1.27 BSC L 0.51 0.76 θ 0º 8º PIN#1 IDENTIFICATION TOP VIEW D A (cid:2) e b L c A1 SIDE VIEW END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with EIAJ EDR-7320. DOCUMENT NUMBER: 98AON34273E Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed STATUS: ON SEMICONDUCTOR STANDARD versions are uncontrolled except when stamped “CONTROLLED COPY” in red. REFERENCE: © Semiconductor Components Industries, LLC, 2002 http://onsemi.com Case Outline Number: October, D20E0S2C −R RIePvT. I0ON: SOIC−8, 208 MILS 1 PAGE 1 OFX 2XX

DOCUMENT NUMBER: 98AON34273E PAGE 2 OF 2 ISSUE REVISION DATE O RELEASED FOR PRODUCTION FROM POD #SOIK8−031−01 TO ON 19 DEC 2008 SEMICONDUCTOR. REQ. BY B. BERGMAN. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. © Semiconductor Components Industries, LLC, 2008 Case Outline Number: December, 2008 − Rev. 01O 751BE

MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS TSSOP8, 4.4x3 CASE 948AL−01 ISSUE O DATE 19 DEC 2008 b SYMBOL MIN NOM MAX A 1.20 A1 0.05 0.15 A2 0.80 0.90 1.05 b 0.19 0.30 E1 E c 0.09 0.20 D 2.90 3.00 3.10 E 6.30 6.40 6.50 E1 4.30 4.40 4.50 e 0.65 BSC L 1.00 REF L1 0.50 0.60 0.75 θ 0º 8º e TOP VIEW D A2 A (cid:2)1 c A1 L1 L SIDE VIEW END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153. DOCUMENT NUMBER: 98AON34428E Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed STATUS: ON SEMICONDUCTOR STANDARD versions are uncontrolled except when stamped “CONTROLLED COPY” in red. REFERENCE: © Semiconductor Components Industries, LLC, 2002 http://onsemi.com Case Outline Number: October, D20E0S2C −R RIePvT. I0ON: TSSOP8, 4.4X3 1 PAGE 1 OFX 2XX

DOCUMENT NUMBER: 98AON34428E PAGE 2 OF 2 ISSUE REVISION DATE O RELEASED FOR PRODUCTION FROM POD #TSSOP8−004−01 TO ON 19 DEC 2008 SEMICONDUCTOR. REQ. BY B. BERGMAN. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. © Semiconductor Components Industries, LLC, 2008 Case Outline Number: December, 2008 − Rev. 01O 948AL

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: O N Semiconductor: CAT25128YI-G CAT25128VI-G CAT25128HU4I-GT3