DATASHEET CA3420 FN1320 0.5MHz, Low Supply Voltage, Low Input Current BiMOS Operational Amplifier Rev 9.00 Oct 4, 2005 The CA3420 is an integrated circuit operational amplifier that Features combines PMOS transistors and bipolar transistors on a • 2V Supply at 300A Supply Current single monolithic chip. The CA3420 BiMOS operational amplifier features gate protected PMOS transistors in the • 1pA Input Current (Typ) (Essentially Constant to 85°C) input circuit to provide very high input impedance, very low • Rail-to-Rail Output Swing (Drive 2mA into 1k Load) input currents (less than 1pA). The internal bootstrapping network features a unique guardbanding technique for • Pin Compatible with 741 Operational Amplifiers reducing the doubling of leakage current for every 10°C • Pb-Free Plus Anneal Available (RoHS Compliant) increase in temperature. The CA3420 operates at total supply voltages from 2V to 20V either single or dual supply. Applications This operational amplifier is internally phase compensated to • pH Probe Amplifiers achieve stable operation in the unity gain follower configuration. Additionally, it has access terminals for a • Picoammeters supplementary external capacitor if additional frequency roll- • Electrometer (High Z) Instruments off is desired. Terminals are also provided for use in applications requiring input offset voltage nulling. The use of • Portable Equipment PMOS in the input stage results in common mode input • Inaccessible Field Equipment voltage capability down to 0.45V below the negative supply terminal, an important attribute for single supply application. • Battery-Dependent Equipment (Medical and Military) The output stage uses a feedback OTA type amplifier that Functional Diagram can swing essentially from rail-to-rail. The output driving current of 1.5mA (Min) is provided by using nonlinear current mirrors. X1 Ordering Information PART PART TEMP. PKG. NUMBER MARKING RANGE (°C) PACKAGE DWG. # - CA3420E CA3420E -55 to 125 8 Ld PDIP E8.3 MOS BIPOLAR CA3420EZ CA3420EZ -55 to 125 8 Ld PDIP* E8.3 MOS (Note) (Pb-free) + BIPOLAR *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. X1 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant BUFFER AMPS; and compatible with both SnPb and Pb-free soldering operations. BOOTSTRAPPED HIGH GAIN OTA BUFFER INPUT PROTECTION (50K) (X2) Intersil Pb-free products are MSL classified at Pb-free peak reflow NETWORK temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Pinout CA3420 (PDIP) TOP VIEW OFFSET NULL 1 8 STROBE INV. INPUT 2 - 7 V+ NON-INV. 3 + 6 OUTPUT INPUT V- 4 5 OFFSET NULL FN1320 Rev 9.00 Page 1 of 5 Oct 4, 2005

CA3420 Absolute Maximum Ratings Thermal Information Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22V Thermal Resistance (Typical, Note 2) JA (°C/W) JC (°C/W) Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15V PDIP Package* . . . . . . . . . . . . . . . . . . 105 N/A DC Input Voltage . . . . . . . . . . . . . . . . . . . . . .(V+ + 8V) to (V- -0.5V) Maximum Junction Temperature (Plastic Package) . . . . . . . 150°C Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA Maximum Storage Temperature Range. . . . . . . . . . -65°C to 150°C Output Short Circuit Duration (Note 1). . . . . . . . . . . . . . . . Indefinite Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C Operating Conditions *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . -55°C to 125°C applications. CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Short circuit may be applied to ground or to either supply. 2. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications Typical Values Intended Only for Design Guidance, VSUPPLY = 10V, TA = 25°C PARAMETER SYMBOL TEST CONDITIONS TYP UNITS Input Resistance RI 150 T Input Capacitance CI 4.9 pF Output Resistance RO 300  Equivalent Input Noise Voltage eN f = 1kHz RS = 100 62 nV/Hz f = 10kHz 38 nV/Hz Short-Circuit Current Source IOM+ 2.6 mA To Opposite Supply Sink IOM- 2.4 mA Gain Bandwidth Product fT 0.5 MHz Slew Rate SR 0.5 V/s Transient Response Rise Time tR RL = 2k, CL = 100pF 0.7 s Overshoot OS 15 % Current from Terminal 8 To V- I8+ 20 A To V+ I8- 2 mA Electrical Specifications For Equipment Design, At VSUPPLY = 1V, TA = 25°C, Unless Otherwise Specified TEST PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input Offset Voltage |VIO| - 5 10 mV Input Offset Current (Note 3) |IIO| - 0.01 4 pA Input Current (Note 3) |II| - 1 5 pA Large Signal Voltage Gain AOL RL = 10k 10 100 - kV/V 80 100 - dB Common Mode Rejection Ratio CMRR - 560 1800 V/V 55 65 - dB Common Mode Input Voltage Range VlCR+ 0.2 0.5 - V VlCR- - -1.3 - V Power Supply Rejection Ratio PSRR VIO/V - 100 1000 V/V 60 80 - dB Max Output Voltage VOM+ RL =  0.90 0.95 - V VOM- -0.85 -0.91 - V Supply Current I+ - 350 650 A Device Dissipation PD - 0.7 1.1 mW Input Offset Voltage Temperature Drift VlO/T - 4 - V/°C NOTE: 3. The maximum limit represents the levels obtainable on high speed automatic test equipment. Typical values are obtained under laboratory conditions. FN1320 Rev 9.00 Page 2 of 5 Oct 4, 2005

CA3420 Electrical Specifications For Equipment Design, at VSUPPLY = 10V, TA = 25°C, Unless Otherwise Specified TEST PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input Offset Voltage |VIO| - 5 10 mV Input Offset Current (Note 4) |IIO| - 0.03 4 pA Input Current (Note 4) |II| - 0.05 5 pA Large Signal Voltage Gain AOL RL = 10k 10 100 - kV/V 80 100 - dB Common Mode Rejection Ratio CMRR - 100 320 V/V 70 80 - dB Common Mode Input Voltage Range VlCR+ 8.5 9.3 - V VlCR- -10 -10.3 - V Power Supply Rejection Ratio PSRR VIO/V - 32 320 V/V 70 90 - dB Max Output Voltage VOM+ RL =  9.7 9.9 - V VOM- -9.7 -9.85 - V Supply Current I+ - 450 1000 A Device Dissipation PD - 9 14 mW Input Offset Voltage Temperature Drift VlO/T - 4 - V/°C NOTE: 4. The maximum limit represents the levels obtainable on high speed automatic test equipment. Typical values are obtained under laboratory conditions. Typical Applications 10G 10pF Picoammeter Circuit +1.5V 500-0-500 The exceptionally low input current (typically 0.2pA) makes 2 - 7 A 1M 10M the CA3420 highly suited for use in a picoammeter circuit. CA3420 6 M With only a single 10G resistor, this circuit covers the range 3 + 4 50pA 1.5k from 1.5pA. Higher current ranges are possible with suitable 5 1 BATTERY 1.5k, 1% switching techniques and current scaling resistors. Input RETURNS 15pA 10k 1k transient protection is provided by the 1M resistor in series 430, 1% with the input. Higher current ranges require that this resistor 5pA be reduced. The 10M resistor connected to pin 2 of the -1.5V 150, 1% CA3420 decouples the potentially high input capacitance 1.5pA often associated with lower current circuits and reduces the tendency for the circuit to oscillate under these conditions. 68 11k 1% High Input Resistance Voltmeter FIGURE 1. PICOAMMETER CIRCUIT Advantage is taken of the high input impedance of the CA3420 in a high input resistance DC voltmeter. Only two 1.5V “AA” +1.5V type penlite batteries power this exceedingly high-input 500-0-500 3 + 7 A resistance (>1,000,000M) DC voltmeter. Full-scale deflection 22M 10M CA3420 6 M is 500mV, 150mV, and 15mV. Higher voltage ranges are 100pF - easily added with external input voltage attenuator networks. 2 4 500mV 1.5k 5 1 BATTERY The meter is placed in series with the gain network, thus RETURNS 1.5k, 1% 10k 150mV eliminating the meter temperature coefficient error term. 1k Supply current in the standby position with the meter 430, 1% 50mV undeflected is 300A. At full-scale deflection this current -1.5V rises to 800A. Carbon-zinc battery life should be in excess 150, 1% 15mV of 1,000 hours. 68 1.1k 1% FIGURE 2. HIGH INPUT RESISTANCE VOLTMETER FN1320 Rev 9.00 Page 3 of 5 Oct 4, 2005

CA3420 Typical Performance Curves E 10 OLTAGE EXCURSIONS FROM THEGATIVE SUPPLY VOLTAGE (V) -000010......0246802 RTAL == 2150°0Ck VVOO-+ GE TRANSISTOR SATURATIONOLTAGE, Q(mV)19 100 VTA- == 02V5°C VVVV++++ ==== 122500VVVV PUT & OUTPUT VPOSITIVE AND N ----0001....0864 VVIICCRR-+ OUTPUT STAV10000.01 0.1 1 10 N 0 1 5 10 15 I LOAD (SOURCING) CURRENT (mA) SUPPLY VOLTAGE (V) FIGURE 3. OUTPUT VOLTAGE SWING AND COMMON MODE FIGURE 4. OUTPUT VOLTAGE vs LOAD SOURCING CURRENT INPUT VOLTAGE RANGE vs SUPPLY VOLTAGE TION 1000 VTA+ == 205V°C V/Hz) 1000 VS = 10V TA = 25°C TURA GE (n VVSS == 15VV A A NSISTOR SE, Q (mV)17 100 VVV--- === ---12500VVV OISE VOLT 100 AG N T STAGE TRVOLTA V- = -2V ENT INPUT 10 U L P A T V OU UI 10 EQ 1 0.01 0.1 1 10 101 102 103 104 105 106 LOAD (SINKING) CURRENT (mA) FREQUENCY (Hz) FIGURE 5. OUTPUT VOLTAGE vs LOAD SINKING CURRENT FIGURE 6. INPUT NOISE VOLTAGE vs FREQUENCY TA = 25°C VS = 5V ES) 100 RL = 10k RE B) CL = 0pF 0 EG d D N ( 80 -45 E ( AI S G -90 A LTAGE 60 --118305 OOP PH O L P V 40 EN O P O O L N 20 E P O 0 1 101 102 103 104 105 106 FREQUENCY (Hz) FIGURE 7. OPEN LOOP GAIN AND PHASE SHIFT RESPONSE FN1320 Rev 9.00 Page 4 of 5 Oct 4, 2005

CA3420 Dual-In-Line Plastic Packages (PDIP) E8.3 (JEDEC MS-001-BA ISSUE D) N 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX INCHES MILLIMETERS AREA 1 2 3 N/2 SYMBOL MIN MAX MIN MAX NOTES -B- A - 0.210 - 5.33 4 -A- D E A1 0.015 - 0.39 - 4 BASE A2 0.115 0.195 2.93 4.95 - PLANE A2 -C- A B 0.014 0.022 0.356 0.558 - SEATING PLANE L CL B1 0.045 0.070 1.15 1.77 8, 10 D1 D1 A1 eA C 0.008 0.014 0.204 0.355 - B1 e eC C D 0.355 0.400 9.01 10.16 5 B eB D1 0.005 - 0.13 - 5 0.010 (0.25) M C A B S E 0.300 0.325 7.62 8.25 6 NOTES: E1 0.240 0.280 6.10 7.11 5 1. Controlling Dimensions: INCH. In case of conflict between e 0.100 BSC 2.54 BSC - English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. eA 0.300 BSC 7.62 BSC 6 3. Symbols are defined in the “MO Series Symbol List” in Section eB - 0.430 - 10.92 7 2.2 of Publication No. 95. L 0.115 0.150 2.93 3.81 4 4. Dimensions A, A1 and L are measured with the package seated N 8 8 9 in JEDEC seating plane gauge GS-3. Rev. 0 12/93 5. D, D1, and E1 dimensions do not include mold flash or protru- sions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be per- pendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads uncon- strained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). © Copyright Intersil Americas LLC 2000-2005. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN1320 Rev 9.00 Page 5 of 5 Oct 4, 2005