DATASHEET CA3140, CA3140A FN957 4.5MHz, BiMOS Operational Amplifier with MOSFET Input/Bipolar Output Rev.10.00 Jul 11, 2005 The CA3140A and CA3140 are integrated circuit operational Features amplifiers that combine the advantages of high voltage • MOSFET Input Stage PMOS transistors with high voltage bipolar transistors on a - Very High Input Impedance (ZIN) -1.5T (Typ) single monolithic chip. - Very Low Input Current (Il) -10pA (Typ) at 15V The CA3140A and CA3140 BiMOS operational amplifiers - Wide Common Mode Input Voltage Range (VlCR) - Can be feature gate protected MOSFET (PMOS) transistors in the Swung 0.5V Below Negative Supply Voltage Rail input circuit to provide very high input impedance, very low - Output Swing Complements Input Common Mode input current, and high speed performance. The CA3140A Range and CA3140 operate at supply voltage from 4V to 36V • Directly Replaces Industry Type 741 in Most Applications (either single or dual supply). These operational amplifiers are internally phase compensated to achieve stable • Pb-Free Plus Anneal Available (RoHS Compliant) operation in unity gain follower operation, and additionally, Applications have access terminal for a supplementary external capacitor if additional frequency roll-off is desired. Terminals are also • Ground-Referenced Single Supply Amplifiers in provided for use in applications requiring input offset voltage Automobile and Portable Instrumentation nulling. The use of PMOS field effect transistors in the input • Sample and Hold Amplifiers stage results in common mode input voltage capability down to 0.5V below the negative supply terminal, an important • Long Duration Timers/Multivibrators (seconds-Minutes-Hours) attribute for single supply applications. The output stage uses bipolar transistors and includes built-in protection • Photocurrent Instrumentation against damage from load terminal short circuiting to either • Peak Detectors supply rail or to ground. • Active Filters The CA3140A and CA3140 are intended for operation at supply voltages up to 36V (18V). • Comparators • Interface in 5V TTL Systems and Other Low Supply Voltage Systems • All Standard Operational Amplifier Applications • Function Generators • Tone Controls • Power Supplies • Portable Instruments • Intrusion Alarm Systems Pinout CA3140 (PDIP, SOIC) TOP VIEW OFFSET NULL 1 8 STROBE INV. INPUT 2 7 V+ - NON-INV. + 3 6 OUTPUT INPUT OFFSET V- 4 5 NULL FN957 Rev.10.00 Page 1 of 24 Jul 11, 2005

CA3140, CA3140A Ordering Information PART NUMBER TEMP. PKG. (BRAND) RANGE (°C) PACKAGE DWG. # CA3140AE -55 to 125 8 Ld PDIP E8.3 CA3140AEZ* -55 to 125 8 Ld PDIP E8.3 (See Note) (Pb-free) CA3140AM -55 to 125 8 Ld SOIC M8.15 (3140A) CA3140AM96 -55 to 125 8 Ld SOIC Tape and Reel (3140A) CA3140AMZ -55 to 125 8 Ld SOIC M8.15 (3140A) (See Note) (Pb-free) CA3140AMZ96 -55 to 125 8 Ld SOIC Tape and Reel (3140A) (See Note) (Pb-free) CA3140E -55 to 125 8 Ld PDIP E8.3 CA3140EZ* -55 to 125 8 Ld PDIP E8.3 (See Note) (Pb-free) CA3140M -55 to 125 8 Ld SOIC M8.15 (3140) CA3140M96 -55 to 125 8 Ld SOIC Tape and Reel (3140) CA3140MZ -55 to 125 8 Ld SOIC M8.15 (3140) (See Note) (Pb-free) CA3140MZ96 -55 to 125 8 Ld SOIC Tape and Reel (3140) (See Note) (Pb-free) *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD- 020. FN957 Rev.10.00 Page 2 of 24 Jul 11, 2005

CA3140, CA3140A Absolute Maximum Ratings Thermal Information DC Supply Voltage (Between V+ and V- Terminals) . . . . . . . . . 36V Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) Differential Mode Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 8V PDIP Package* . . . . . . . . . . . . . . . . . . 115 N/A DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . (V++8V) To (V- -0.5V) SOIC Package. . . . . . . . . . . . . . . . . . . 165 N/A Input Terminal Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC Output Short Circuit Duration (Note 2) . . . . . . . . . . . . . . Indefinite Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC Operating Conditions (SOIC - Lead Tips Only) Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC *Pb-free PDIPs can be used for through hole wave solder process- ing only. They are not intended for use in Reflow solder processing applications. CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details 2. Short circuit may be applied to ground or to either supply. Electrical Specifications VSUPPLY = 15V, TA = 25oC TYPICAL VALUES PARAMETER SYMBOL TEST CONDITIONS CA3140 CA3140A UNITS Input Offset Voltage Adjustment Resistor Typical Value of Resistor 4.7 18 k Between Terminals 4 and 5 or 4 and 1 to Adjust Max VIO Input Resistance RI 1.5 1.5 T Input Capacitance CI 4 4 pF Output Resistance RO 60 60  Equivalent Wideband Input Noise Voltage eN BW = 140kHz, RS = 1M 48 48 V (See Figure 27) Equivalent Input Noise Voltage (See Figure 35) eN RS = 100 f = 1kHz 40 40 nV/Hz f = 10kHz 12 12 nV/Hz Short Circuit Current to Opposite Supply IOM+ Source 40 40 mA IOM- Sink 18 18 mA Gain-Bandwidth Product, (See Figures 6, 30) fT 4.5 4.5 MHz Slew Rate, (See Figure 31) SR 9 9 V/s Sink Current From Terminal 8 To Terminal 4 to 220 220 A Swing Output Low Transient Response (See Figure 28) tr RL = 2k Rise Time 0.08 0.08 s CL = 100pF OS Overshoot 10 10 % Settling Time at 10VP-P, (See Figure 5) tS RL = 2k To 1mV 4.5 4.5 s CL = 100pF Voltage Follower To 10mV 1.4 1.4 s Electrical Specifications For Equipment Design, at VSUPPLY = 15V, TA = 25oC, Unless Otherwise Specified CA3140 CA3140A PARAMETER SYMBOL MIN TYP MAX MIN TYP MAX UNITS Input Offset Voltage |VIO| - 5 15 - 2 5 mV Input Offset Current |IIO| - 0.5 30 - 0.5 20 pA Input Current II - 10 50 - 10 40 pA FN957 Rev.10.00 Page 3 of 24 Jul 11, 2005

CA3140, CA3140A Electrical Specifications For Equipment Design, at VSUPPLY = 15V, TA = 25oC, Unless Otherwise Specified (Continued) CA3140 CA3140A PARAMETER SYMBOL MIN TYP MAX MIN TYP MAX UNITS Large Signal Voltage Gain (Note 3) AOL 20 100 - 20 100 - kV/V (See Figures 6, 29) 86 100 - 86 100 - dB Common Mode Rejection Ratio CMRR - 32 320 - 32 320 V/V (See Figure 34) 70 90 - 70 90 - dB Common Mode Input Voltage Range (See Figure 8) VICR -15 -15.5 to +12.5 11 -15 -15.5 to +12.5 12 V Power-Supply Rejection Ratio, PSRR - 100 150 - 100 150 V/V VIO/VS (See Figure 36) 76 80 - 76 80 - dB Max Output Voltage (Note 4) VOM+ +12 13 - +12 13 - V (See Figures 2, 8) VOM- -14 -14.4 - -14 -14.4 - V Supply Current (See Figure 32) I+ - 4 6 - 4 6 mA Device Dissipation PD - 120 180 - 120 180 mW Input Offset Voltage Temperature Drift VIO/T - 8 - - 6 - V/oC NOTES: 3. At VO = 26VP-P, +12V, -14V and RL = 2k. 4. At RL = 2k. Electrical Specifications For Design Guidance At V+ = 5V, V- = 0V, TA = 25oC TYPICAL VALUES PARAMETER SYMBOL CA3140 CA3140A UNITS Input Offset Voltage |VIO| 5 2 mV Input Offset Current |IIO| 0.1 0.1 pA Input Current II 2 2 pA Input Resistance RI 1 1 T Large Signal Voltage Gain (See Figures 6, 29) AOL 100 100 kV/V 100 100 dB Common Mode Rejection Ratio CMRR 32 32 V/V 90 90 dB Common Mode Input Voltage Range (See Figure 8) VICR -0.5 -0.5 V 2.6 2.6 V Power Supply Rejection Ratio PSRR 100 100 V/V VIO/VS 80 80 dB Maximum Output Voltage (See Figures 2, 8) VOM+ 3 3 V VOM- 0.13 0.13 V Maximum Output Current: Source IOM+ 10 10 mA Sink IOM- 1 1 mA Slew Rate (See Figure 31) SR 7 7 V/s Gain-Bandwidth Product (See Figure 30) fT 3.7 3.7 MHz Supply Current (See Figure 32) I+ 1.6 1.6 mA Device Dissipation PD 8 8 mW FN957 Rev.10.00 Page 4 of 24 Jul 11, 2005

CA3140, CA3140A Electrical Specifications For Design Guidance At V+ = 5V, V- = 0V, TA = 25oC (Continued) TYPICAL VALUES PARAMETER SYMBOL CA3140 CA3140A UNITS Sink Current from Terminal 8 to Terminal 4 to Swing Output Low 200 200 A Block Diagram 2mA 4mA 7 V+ BIAS CIRCUIT CURRENT SOURCES AND REGULATOR 200A 1.6mA 200A 2A 2mA + 3 A  INP-UT A 10 10,000 A 1 6 OUTPUT 2 C1 12pF 4 V- 5 1 8 STROBE OFFSET NULL FN957 Rev.10.00 Page 5 of 24 Jul 11, 2005

CA3140, CA3140A Schematic Diagram BIAS CIRCUIT INPUT STAGE SECOND STAGE OUTPUT STAGE DYNAMIC CURRENT SINK 7 V+ D1 D7 R13 5K Q1 Q2 Q3 50R9 Q20 D8 R10 Q6 Q5 Q4 1K R14 Q19 R11 R12 20K Q7 20 12K Q21 Q17 R1 8K Q8 R8 1K Q18 6 OUTPUT D2 D3 D4 D5 INVERTING 2 INPUT - Q9 Q10 + NON-INVERTING 3 INPUT C1 R2 R3 500 500 12pF Q14 Q15 Q16 Q13 Q11 Q12 D6 R4 R5 R6 R7 500 500 50 30 5 1 8 4 OFFSET NULL STROBE V- NOTE: All resistance values are in ohms. Application Information base current drive to the second stage bipolar transistor (Q13). Offset nulling, when desired, can be effected with a 10k Circuit Description potentiometer connected across Terminals 1 and 5 and with its As shown in the block diagram, the input terminals may be slider arm connected to Terminal 4. Cascode-connected bipolar operated down to 0.5V below the negative supply rail. Two transistors Q2, Q5 are the constant current source for the input class A amplifier stages provide the voltage gain, and a unique stage. The base biasing circuit for the constant current source is class AB amplifier stage provides the current gain necessary to described subsequently. The small diodes D3, D4, D5 provide drive low-impedance loads. gate oxide protection against high voltage transients, e.g., static A biasing circuit provides control of cascoded constant current electricity. flow circuits in the first and second stages. The CA3140 includes Second Stage an on chip phase compensating capacitor that is sufficient for Most of the voltage gain in the CA3140 is provided by the the unity gain voltage follower configuration. second amplifier stage, consisting of bipolar transistor Q13 and Input Stage its cascode connected load resistance provided by bipolar The schematic diagram consists of a differential input stage using transistors Q3, Q4. On-chip phase compensation, sufficient for PMOS field-effect transistors (Q9, Q10) working into a mirror pair a majority of the applications is provided by C1. Additional of bipolar transistors (Q11, Q12) functioning as load resistors Miller-Effect compensation (roll off) can be accomplished, together with resistors R2 through R5. The mirror pair transistors when desired, by simply connecting a small capacitor between also function as a differential-to-single-ended converter to provide Terminals 1 and 8. Terminal 8 is also used to strobe the output FN957 Rev.10.00 Page 6 of 24 Jul 11, 2005

CA3140, CA3140A stage into quiescence. When terminal 8 is tied to the negative current in diode connected transistor Q2 establishes the currents supply rail (Terminal 4) by mechanical or electrical means, the in transistors Q14 and Q15. output Terminal 6 swings low, i.e., approximately to Terminal 4 Typical Applications potential. Wide dynamic range of input and output characteristics with the Output Stage most desirable high input impedance characteristics is achieved The CA3140 Series circuits employ a broad band output stage in the CA3140 by the use of an unique design based upon the that can sink loads to the negative supply to complement the PMOS Bipolar process. Input common mode voltage range and capability of the PMOS input stage when operating near the output swing capabilities are complementary, allowing operation negative rail. Quiescent current in the emitter-follower cascade with the single supply down to 4V. circuit (Q17, Q18) is established by transistors (Q14, Q15) whose base currents are “mirrored” to current flowing through diode D2 in The wide dynamic range of these parameters also means that the bias circuit section. When the CA3140 is operating such that this device is suitable for many single supply applications, such output Terminal 6 is sourcing current, transistor Q18 functions as as, for example, where one input is driven below the potential an emitter-follower to source current from the V+ bus (Terminal 7), of Terminal 4 and the phase sense of the output signal must be via D7, R9, and R11. Under these conditions, the collector maintained – a most important consideration in comparator potential of Q13 is sufficiently high to permit the necessary flow of applications. base current to emitter follower Q17 which, in turn, drives Q18. When the CA3140 is operating such that output Terminal 6 is sinking current to the V- bus, transistor Q16 is the current sinking element. Transistor Q16 is mirror connected to D6, R7, with current fed by way of Q21, R12, and Q20. Transistor Q20, in turn, is biased by current flow through R13, zener D8, and R14. The dynamic current sink is controlled by voltage level sensing. For purposes of explanation, it is assumed that output Terminal 6 is quiescently established at the potential midpoint between the V+ and V- supply rails. When output current sinking mode operation is required, the collector potential of transistor Q13 is driven below its quiescent level, thereby causing Q17, Q18 to decrease the output voltage at Terminal 6. Thus, the gate terminal of PMOS transistor Q21 is displaced toward the V- bus, thereby reducing the channel resistance of Q21. As a consequence, there is an incremental increase in current flow through Q20, R12, Q21, D6, R7, and the base of Q16. As a result, Q16 sinks current from Terminal 6 in direct response to the incremental change in output voltage caused by Q18. This sink current flows regardless of load; any excess current is internally supplied by the emitter-follower Q18. Short circuit protection of the output circuit is provided by Q19, which is driven into conduction by the high voltage drop developed across R11 under output short circuit conditions. Under these conditions, the collector of Q19 diverts current from Q4 so as to reduce the base current drive from Q17, thereby limiting current flow in Q18 to the short circuited load terminal. Bias Circuit Quiescent current in all stages (except the dynamic current sink) of the CA3140 is dependent upon bias current flow in R1. The function of the bias circuit is to establish and maintain constant current flow through D1, Q6, Q8 and D2. D1 is a diode connected transistor mirror connected in parallel with the base emitter junctions of Q1, Q2, and Q3. D1 may be considered as a current sampling diode that senses the emitter current of Q6 and automatically adjusts the base current of Q6 (via Q1) to maintain a constant current through Q6, Q8, D2. The base currents in Q2, Q3 are also determined by constant current flow D1. Furthermore, FN957 Rev.10.00 Page 7 of 24 Jul 11, 2005

CA3140, CA3140A Output Circuit Considerations power transistors and thyristors directly without the need for level shifting circuitry usually associated with the 741 series of Excellent interfacing with TTL circuitry is easily achieved with a operational amplifiers. single 6.2V zener diode connected to Terminal 8 as shown in Figure 1. This connection assures that the maximum output Figure 4 shows some typical configurations. Note that a series signal swing will not go more positive than the zener voltage resistor, RL, is used in both cases to limit the drive available to minus two base-to-emitter voltage drops within the CA3140. the driven device. Moreover, it is recommended that a series These voltages are independent of the operating supply diode and shunt diode be used at the thyristor input to prevent voltage. large negative transient surges that can appear at the gate of thyristors, from damaging the integrated circuit. V+ 5V TO 36V Offset Voltage Nulling LOGIC 7 2 8 6.2V SUPP5LYV The input offset voltage can be nulled by connecting a 10k potentiometer between Terminals 1 and 5 and returning its CA3140 6 TYPICAL wiper arm to terminal 4, see Figure 3A. This technique, TTL GATE 3 5V however, gives more adjustment range than required and 4 therefore, a considerable portion of the potentiometer rotation is not fully utilized. Typical values of series resistors (R) that may be placed at either end of the potentiometer, see Figure 3B, to optimize its utilization range are given in the Electrical FIGURE 1. ZENER CLAMPING DIODE CONNECTED TO Specifications table. TERMINALS 8 AND 4 TO LIMIT CA3140 OUTPUT SWING TO TTL LEVELS An alternate system is shown in Figure 3C. This circuit uses only one additional resistor of approximately the value shown )16 1000 SUPPLY VOLTAGE (V-) = 0V in the table. For potentiometers, in which the resistance does SISTOR (Q, Q15LTAGE (mV) 100 STAU P=P 2L5Yo CVOLTAGE (V+) = +5V +15V +30V nL1o0ot%w d r loVowpo eltotra t0ghaen aO tth peeiet hvraealrtu ieeonsnd s ohfo rwonta itnio tnh,e a t avballeu es hoof urelds ibseta unsceed . NO Operation at total supply voltages as low as 4V is possible with AV GE TRATION 10 tthhree CshAo3ld1 4v0o.l tAag ceu rmreanint traeignus laretoars obnaasebdle ucpoonns ttahnet PoMpeOraSt ing AR UT STSATU cvuorltraegnet sa.nd hence consistent performance down to these lower P T U The low voltage limitation occurs when the upper extreme of the O 1 0.01 0.1 1.0 10 input common mode voltage range extends down to the voltage LOAD (SINKING) CURRENT (mA) at Terminal 4. This limit is reached at a total supply voltage just FIGURE 2. VOLTAGE ACROSS OUTPUT TRANSISTORS (Q15 below 4V. The output voltage range also begins to extend down to AND Q16) vs LOAD CURRENT the negative supply rail, but is slightly higher than that of the input. Figure 8 shows these characteristics and shows that with 2V dual Figure 2 shows output current sinking capabilities of the supplies, the lower extreme of the input common mode voltage CA3140 at various supply voltages. Output voltage swing to range is below ground potential. the negative supply rail permits this device to operate both V+ V+ V+ 2 7 2 7 2 7 CA3140 6 CA3140 6 CA3140 6 3 4 3 4 5 3 4 5 1 5 1 R R 1 10k 10k 10k R V- V- V- FIGURE 3A. BASIC FIGURE 3B. IMPROVED RESOLUTION FIGURE 3C. SIMPLER IMPROVED RESOLUTION FIGURE 3. THREE OFFSET VOLTAGE NULLING METHODS FN957 Rev.10.00 Page 8 of 24 Jul 11, 2005

CA3140, CA3140A RS V+ +HV LOAD 2 7 LOAD 30V NO LOAD MT2 CA3140 6 120VAC 2 7 RL 3 CA3140 6 4 3 RL MT1 4 FIGURE 4. METHODS OF UTILIZING THE VCE(SAT) SINKING CURRENT CAPABILITY OF THE CA3140 SERIES FOLLOWER +15V 7 3 0.1F SIMULATED 10k LOAD CA3140 6 2 100pF 2k 4 0.1F LOAD RESISTANCE (RL) = 2k -15V LOAD CAPACITANCE (CL) = 100pF 2k SUPPLY VOLTAGE: VS = 15V TA = 25oC 0.05F 10 1mV 1mV INVERTING 8 5k 10mV 10mV 6 E (V) 4 +15V G 2 7 TA FOLLOWER 2 0.1F SIMULATED OL 0 INVERTING 5k LOAD T V -2 200 CA3140 6 U NP -4 3 100pF 2k I 4 -6 1mV 1mV 4.99k 0.1F 5.11k -8 10mV 10mV -15V -10 SETTLING POINT 0.1 1.0 10 SETTLING TIME (s) D1 D2 1N914 1N914 FIGURE 5A. WAVEFORM FIGURE 5B. TEST CIRCUITS FIGURE 5. SETTLING TIME vs INPUT VOLTAGE Bandwidth and Slew Rate The exceptionally fast settling time characteristics are largely due to the high combination of high gain and wide bandwidth of For those cases where bandwidth reduction is desired, for the CA3140; as shown in Figure 6. example, broadband noise reduction, an external capacitor connected between Terminals 1 and 8 can reduce the open Input Circuit Considerations loop -3dB bandwidth. The slew rate will, however, also be As mentioned previously, the amplifier inputs can be driven proportionally reduced by using this additional capacitor. Thus, below the Terminal 4 potential, but a series current limiting a 20% reduction in bandwidth by this technique will also resistor is recommended to limit the maximum input terminal reduce the slew rate by about 20%. current to less than 1mA to prevent damage to the input Figure 5 shows the typical settling time required to reach 1mV protection circuitry. or 10mV of the final value for various levels of large signal Moreover, some current limiting resistance should be provided inputs for the voltage follower and inverting unity gain between the inverting input and the output when the CA3140 is amplifiers. FN957 Rev.10.00 Page 9 of 24 Jul 11, 2005

CA3140, CA3140A used as a unity gain voltage follower. This resistance prevents offset voltage) due to the application of large differential input the possibility of extremely large input signal transients from voltages that are sustained over long periods at elevated forcing a signal through the input protection network and temperatures. directly driving the internal constant current source which could Both applied voltage and temperature accelerate these result in positive feedback via the output terminal. A 3.9k changes. The process is reversible and offset voltage shifts of resistor is sufficient. the opposite polarity reverse the offset. Figure 9 shows the The typical input current is on the order of 10pA when the typical offset voltage change as a function of various stress inputs are centered at nominal device dissipation. As the voltages at the maximum rating of 125oC (for metal can); at output supplies load current, device dissipation will increase, lower temperatures (metal can and plastic), for example, at raising the chip temperature and resulting in increased input 85oC, this change in voltage is considerably less. In typical current. Figure 7 shows typical input terminal current versus linear applications, where the differential voltage is small and ambient temperature for the CA3140. symmetrical, these incremental changes are of about the same magnitude as those encountered in an operational amplifier It is well known that MOSFET devices can exhibit slight employing a bipolar transistor input stage. changes in characteristics (for example, small changes in input -75 E 10K SUPPLY VOLTAGE: VS = 15V AS SUPPLY VOLTAGE: VS = 15V AGE GAIN (dB)10800 TA = 25oC OL RCLL == 20kpF, -----91111002355050 OPEN LOOP PH(DEGREES) NT (pA) 1K T E OL 60 RR 100 V U P RL = 2k, C OO 40 CL = 100pF UT L P EN IN 10 P 20 O 0 1 101 102 103 104 105 106 107 108 -60 -40 -20 0 20 40 60 80 100 120 140 FREQUENCY (Hz) TEMPERATURE (oC) FIGURE 6. OPEN LOOP VOLTAGE GAIN AND PHASE vs FIGURE 7. INPUT CURRENT vs TEMPERATURE FREQUENCY S S ON RL =  ON RSI 0 RSI 1.5 U U TPUT VOLTAGE EXCM TERMINAL 7 (V+) ----1210....5005 +++VVVIICCICRRR AA ATTT TT ATAA == = 1- 522555oooCCC +++VVVOOOUUUTTT AAATTT TTTAAA === 1-252555ooCoCC TPUT VOLTAGE EXCM TERMINAL 4 (V-) -010...0550 -TVAO =U -T5 F5oOCR to 125oC ---VVVIIICCCRRR AAATTT TTTAAA === 1-25255o5oCoCC UO UO OR OR D F -2.5 D F -1.0 N N A A T -3.0 T -1.5 U U P P N N I 0 5 10 15 20 25 I 0 5 10 15 20 25 SUPPLY VOLTAGE (V+, V-) SUPPLY VOLTAGE (V+, V-) FIGURE 8. OUTPUT VOLTAGE SWING CAPABILITY AND COMMON MODE INPUT VOLTAGE RANGE vs SUPPLY VOLTAGE FN957 Rev.10.00 Page 10 of 24 Jul 11, 2005

CA3140, CA3140A Analog frequency readout is readily accomplished by the means 7 TA = 125oC described above because the output current of the CA3080A FOR METAL CAN PACKAGES mV) 6 DIFFERENTIAL DC VOLTAGE varies approximately one decade for each 60mV change in the HIFT ( 5 (OAUCTRPOUSTS S TTEARGMEI NTOAGLSG L2 EADND 3) = 2V CapAp3li0e8d0 vAo lotaf gthee, VfuAnBcCti o(vno glteangeer baetotwr).e Tenh eTreerfmorien,a slsix 5 d aencda d4e osf the E S 4 represent 360mV change in VABC. G A T Now, only the reference voltage must be established to set the VOL 3 lower limit on the meter. The three remaining transistors from ET 2 the CA3086 Array used in the sweep generator are used for S F DIFFERENTIAL DC VOLTAGE this reference voltage. In addition, this reference generator F O (ACROSS TERMINALS 2 AND 3) = 0V 1 arrangement tends to track ambient temperature variations, OUTPUT VOLTAGE = V+ / 2 and thus compensates for the effects of the normal negative 0 0 500 1000 1500 2000 2500 3000 3500 4000 4500 temperature coefficient of the CA3080A VABC terminal voltage. TIME (HOURS) Another output voltage from the reference generator is used to FIGURE 9. TYPICAL INCREMENTAL OFFSET VOLTAGE insure temperature tracking of the lower end of the Frequency SHIFT vs OPERATING LIFE Adjustment Potentiometer. A large series resistance simulates Super Sweep Function Generator a current source, assuring similar temperature coefficients at both ends of the Frequency Adjustment Control. A function generator having a wide tuning range is shown in Figure 10. The 1,000,000/1 adjustment range is accomplished To calibrate this circuit, set the Frequency Adjustment by a single variable potentiometer or by an auxiliary sweeping Potentiometer at its low end. Then adjust the Minimum signal. The CA3140 functions as a non-inverting readout Frequency Calibration Control for the lowest frequency. To amplifier of the triangular signal developed across the establish the upper frequency limit, set the Frequency integrating capacitor network connected to the output of the Adjustment Potentiometer to its upper end and then adjust the CA3080A current source. Maximum Frequency Calibration Control for the maximum frequency. Because there is interaction among these controls, Buffered triangular output signals are then applied to a second repetition of the adjustment procedure may be necessary. Two CA3080 functioning as a high speed hysteresis switch. Output adjustments are used for the meter. The meter sensitivity from the switch is returned directly back to the input of the control sets the meter scale width of each decade, while the CA3080A current source, thereby, completing the positive meter position control adjusts the pointer on the scale with feedback loop negligible effect on the sensitivity adjustment. Thus, the meter The triangular output level is determined by the four 1N914 sensitivity adjustment control calibrates the meter so that it level limiting diodes of the second CA3080 and the resistor deflects 1/6 of full scale for each decade change in frequency. divider network connected to Terminal No. 2 (input) of the Sine Wave Shaper CA3080. These diodes establish the input trip level to this switching stage and, therefore, indirectly determine the The circuit shown in Figure 12 uses a CA3140 as a voltage amplitude of the output triangle. follower in combination with diodes from the CA3019 Array to convert the triangular signal from the function generator to a Compensation for propagation delays around the entire loop is sine-wave output signal having typically less than 2% THD. provided by one adjustment on the input of the CA3080. This The basic zero crossing slope is established by the 10k adjustment, which provides for a constant generator amplitude potentiometer connected between Terminals 2 and 6 of the output, is most easily made while the generator is sweeping. CA3140 and the 9.1k resistor and 10k potentiometer from High frequency ramp linearity is adjusted by the single 7pF to Terminal 2 to ground. Two break points are established by 60pF capacitor in the output of the CA3080A. diodes D1 through D4. Positive feedback via D5 and D6 It must be emphasized that only the CA3080A is characterized establishes the zero slope at the maximum and minimum for maximum output linearity in the current generator function. levels of the sine wave. This technique is necessary because the voltage follower configuration approaches unity gain rather Meter Driver and Buffer Amplifier than the zero gain required to shape the sine wave at the two Figure 11 shows the CA3140 connected as a meter driver and extremes. buffer amplifier. Low driving impedance is required of the CA3080A current source to assure smooth operation of the Frequency Adjustment Control. This low-driving impedance requirement is easily met by using a CA3140 connected as a voltage follower. Moreover, a meter may be placed across the input to the CA3080A to give a logarithmic analog indication of the function generator’s frequency. FN957 Rev.10.00 Page 11 of 24 Jul 11, 2005

CA3140, CA3140A CENTERING -15V 10k +15V HIGH 7.5k +15V +15V FREQUENCY 360 0.1 LEVEL 910k 62k 10k 3 + 7 7 F 7-60pF 15k 5 EXTERNAL 360 2 C-A3080A 7-660 51 3 C+A3140 6 2 - 7 OUTPUT 4 pF pF 2 - 11k CA3080 6 2M 5 HIGH 4 10k 11k 3 + 4 2.7k SYMMETRY -15V FREQ. 0.1 -15V +15V SHAPE -15V F EXTERNAL -15V OUTPUT 2k 13k TO OUTPUT 100k AMPLIFIER FROM BUFFER METER FREQUENCY DRIVER (OPTIONAL) ADJUSTMENT 5.1k TO 39k 120 10k SINE WAVE SHAPER 1N914 -15V +15V OUTPUT AMPLIFIER THIS NETWORK IS USED WHEN THE OPTIONAL BUFFER CIRCUIT IS NOT USED FIGURE 10A. CIRCUIT FREQUENCY ADJUSTMENT Top Trace: Output at junction of 2.7 and 51 resistors; 5V/Div., 500ms/Div. +15V Center Trace: External output of triangular function generator; METER DRIVER POWER 2V/Div., 500ms/Div. AND BUFFER SUPPLY 15V AMPLIFIER M Bottom Trace: Output of “Log” generator; 10V/Div., 500ms/Div. -15V FIGURE 10B. FIGURE FUNCTION GENERATOR SWEEPING FUNCTION GENERATOR WIDEBAND LINE DRIVER SINE WAVE SHAPER 51 GATE DC LEVEL FINE SWEEP SWEEP ADJUST RATE GENERATOR OFF INT. EXTERNAL COARSE V- EXT. INPUT RATE 1V/Div., 1s/Div. SWEEP Three tone test signals, highest frequency 0.5MHz. Note the slight LENGTH asymmetry at the three second/cycle signal. This asymmetry is due to V- slightly different positive and negative integration from the CA3080A and from the PC board and component leakages at the 100pA level. FIGURE 10C. FUNCTION GENERATOR WITH FIXED FIGURE 10D. INTERCONNECTIONS FREQUENCIES FIGURE 10. FUNCTION GENERATOR FN957 Rev.10.00 Page 12 of 24 Jul 11, 2005

CA3140, CA3140A FREQUENCY 500k CALIBRATION MAXIMUM 620k FREQUENCY 7 ADJUSTM1E0NkT 51k 3 + OTFO F UCNAC30T8IO0AN CA3080A +15V 0.1F-15V CA3140 6 GENERATOR SWEEP IN 3M 2 - 4.7k (FIGURE 10) 4 3 + 7 5.6k7.5k 4 5 5.1k CA3140 6 - TO 2k 0.1F +15V SENSMITEIVTIETRY 620 2 4 SOUFB CSATR30A1T9E WOIDUETBPAUNTD 12k ADJUSTMENT 1k 0.1F 7 AMPLIFIER FREQUENCY 2.4k -15V 10k CALIBMRINAITMIOUMN 2k.5 11 M 2M0E0TEAR 1k00+15V1M D1R3 10kD4 EOXUTTEPRUNTAL 9 9.1k 510 -15V 510 R1 6 5 8 2 8 10 14 10k 2k D3 D6 D2 430 6 12 9 1 METER R2 7 POSITION 3.6k 13 1k ADJUSTMENT 3 4 3/5 OF CA3086 CA3019 D5 -15V DIODE ARRAY FIGURE 11. METER DRIVER AND BUFFER AMPLIFIER FIGURE 12. SINE WAVE SHAPER 750k “LOG” 100k SAWTOOTH 18M 1N914 1M 100k FRIANTEE 22M 1N914 SAWTOOTH 8.2k 0.47F SYMMETRY +15VSRAAWMPTO LOOTWH LAENVDEL SET (-14.5V) 0.047F COARSE 50k RATE 4700pF 470pF 75k +15V SAWTOOTH 51k 0.1 2 C-A31470 6F TR“IALNOGGL”+E15V 36k 3 - 7+15V 10k GATE 3 + 4 0.1 30k 100TkO OUTPUT 2 +CA31440 6 POUULTSPEUT F 50k AMPLIFIER -15V -15V LROATGE 10k ADJUST EXTERNAL OUTPUT 43k 10k TO FUNCTION GENERATOR “SWEEP IN” SWEEP WIDTH -15V 7 +15V 3 + CA3140 6 2 - 4 51k 6.8k 91k 10k LOGVIO 1 5 TRIANGLE 25k 5 1 3.9 TRANSISTORS SAWTOOTH 4 2 FROM CA3086 -15V ARRAY 100 “LOG” 390 3 FIGURE 13. SWEEPING GENERATOR FN957 Rev.10.00 Page 13 of 24 Jul 11, 2005

CA3140, CA3140A This circuit can be adjusted most easily with a distortion analyzer, but a good first approximation can be made by comparing the output signal with that of a sine wave generator. VOLTAGE The initial slope is adjusted with the potentiometer R1, followed REFERENCE ADJUSTMENT VOLTAGE 7 by an adjustment of R2. The final slope is established by 3 + REGULATED adjusting R3, thereby adding additional segments that are INPUT CA3140 6 OUTPUT - contributed by these diodes. Because there is some interaction 2 4 among these controls, repetition of the adjustment procedure may be necessary. Sweeping Generator Figure 13 shows a sweeping generator. Three CA3140s are FIGURE 15. BASIC SINGLE SUPPLY VOLTAGE REGULATOR SHOWING VOLTAGE FOLLOWER CONFIGURATION used in this circuit. One CA3140 is used as an integrator, a second device is used as a hysteresis switch that determines Essentially, the regulators, shown in Figures 16 and 17, are the starting and stopping points of the sweep. A third CA3140 connected as non inverting power operational amplifiers with a is used as a logarithmic shaping network for the log function. gain of 3.2. An 8V reference input yields a maximum output Rates and slopes, as well as sawtooth, triangle, and voltage slightly greater than 25V. As a voltage follower, when the logarithmic sweeps are generated by this circuit. reference input goes to 0V the output will be 0V. Because the offset voltage is also multiplied by the 3.2 gain factor, a Wideband Output Amplifier potentiometer is needed to null the offset voltage. Figure 14 shows a high slew rate, wideband amplifier suitable Series pass transistors with high ICBO levels will also prevent for use as a 50 transmission line driver. This circuit, when the output voltage from reaching zero because there is a finite used in conjunction with the function generator and sine wave voltage drop (VCESAT) across the output of the CA3140 (see shaper circuits shown in Figures 10 and 12 provides 18VP-P Figure 2). This saturation voltage level may indeed set the output open circuited, or 9VP-P output when terminated in 50. lowest voltage obtainable. The slew rate required of this amplifier is 28V/s (18VP-P x  x 0.5MHz). The high impedance presented by Terminal 8 is advantageous +15V in effecting current limiting. Thus, only a small signal transistor + 50F 2.2 is required for the current-limit sensing amplifier. Resistive SIGNAL - 25V k 2N3053 LEVEL decoupling is provided for this transistor to minimize damage to ADJUSTMENT it or the CA3140 in the event of unusual input or output 2.5k 3 + 7 1N914 2.7 51OUT transients on the supply rail. CA3140 6 200 2 - 4 1N914 2.7 2W Figures 16 and 17, show circuits in which a D2201 high speed 8 1 - 50F diode is used for the current sensor. This diode was chosen for OUTPUT + 25V 2.2 2N4037 its slightly higher forward voltage drop characteristic, thus giving DC LEVEL +15V 2.4pF k greater sensitivity. It must be emphasized that heat sinking of ADJUSTMENT 3k 2pF -15V this diode is essential to minimize variation of the current trip -15V point due to internal heating of the diode. That is, 1A at 1V 1.8k NOMINAL BANDWIDTH = 10MHz 200 tr = 35ns forward drop represents one watt which can result in significant regenerative changes in the current trip point as the diode temperature rises. Placing the small signal reference amplifier in FIGURE 14. WIDEBAND OUTPUT AMPLIFIER the proximity of the current sensing diode also helps minimize the variability in the trip level due to the negative temperature Power Supplies coefficient of the diode. In spite of those limitations, the current High input impedance, common mode capability down to the limiting point can easily be adjusted over the range from 10mA negative supply and high output drive current capability are key to 1A with a single adjustment potentiometer. If the temperature factors in the design of wide range output voltage supplies that stability of the current limiting system is a serious consideration, use a single input voltage to provide a regulated output voltage the more usual current sampling resistor type of circuitry should that can be adjusted from essentially 0V to 24V. be employed. Unlike many regulator systems using comparators having a A power Darlington transistor (in a metal can with heatsink), is bipolar transistor input stage, a high impedance reference used as the series pass element for the conventional current voltage divider from a single supply can be used in connection limiting system, Figure 16, because high power Darlington with the CA3140 (see Figure 15). dissipation will be encountered at low output voltage and high currents. FN957 Rev.10.00 Page 14 of 24 Jul 11, 2005

CA3140, CA3140A A small heat sink VERSAWATT transistor is used as the series regulation also remains constant. Line regulation is 0.1% per pass element in the fold back current system, Figure 17, since volt. Hum and noise voltage is less than 200V as read with a dissipation levels will only approach 10W. In this system, the meter having a 10MHz bandwidth. D2201 diode is used for current sampling. Foldback is Figure 18A shows the turn ON and turn OFF characteristics of provided by the 3k and 100k divider network connected to both regulators. The slow turn on rise is due to the slow rate of the base of the current sensing transistor. rise of the reference voltage. Figure 18B shows the transient Both regulators provide better than 0.02% load regulation. response of the regulator with the switching of a 20 load at Because there is constant loop gain at all voltage settings, the 20V output. 2N6385 CURRENT “FOLDBACK” CURRENT OUTPUT  0V TO 25V 25V AT 1A POWER DARLINGTON LIMITING LIMITER ADJUST 0O.1U TP 2U4TV 2N5294 D2201 “TFOO 4L0DmSA BACK” D2201 AT 1A +30V 2 3 +30V 3 2 1k 200 75 1k 1k 1 1 100k 3k 1k 3k 2 100k 2N2102 2N2102 3 1k 100 1k 8 1 8 7 56pF 180k 7 56pF 180k 2 2.7k 10F -+ 6 5CA13140 23 1k 82k 2.7k 10F -+ 61005kCA131404 3 1k 82k 100k 4 INPUT INPUT VOLTAGE + VAODLJTUASGTE + 2.2k +- 5F 50k ADJUST +- 250F 2.2k - 5F 50k - 250F 100k 100k 1011 1 2 14 1011 1 2 14 12 12 9 3 0.01F 9 3 0.01F 8 7 5 13 8 7 5 13 6 4 CA3086 6 4 CA3086 1k 1k 62k 62k HUM AND NOISE OUTPUT <200VRMS LOAD REGULATION HUM AND NOISE OUTPUT <200VRMS LOAD REGULATION (MEASUREMENT BANDWIDTH ~10MHz) (NO LOAD TO FULL LOAD) (MEASUREMENT BANDWIDTH ~10MHz) (NO LOAD TO FULL LOAD) LINE REGULATION 0.1%/V <0.02% LINE REGULATION 0.1%/V <0.02% FIGURE 16. REGULATED POWER SUPPLY FIGURE 17. REGULATED POWER SUPPLY WITH “FOLDBACK” CURRENT LIMITING Top Trace: Output Voltage; 5V/Div., 1s/Div. 200mV/Div., 5s/Div. Bottom Trace: Collector of load switching transistor, load = 1A; 5V/Div., 5s/Div. FIGURE 18A. SUPPLY TURN-ON AND TURNOFF CHARACTERISTICS FIGURE 18B. TRANSIENT RESPONSE FIGURE 18. WAVEFORMS OF DYNAMIC CHARACTERISTICS OF POWER SUPPLY CURRENTS SHOWN IN FIGURES 16 AND 17 FN957 Rev.10.00 Page 15 of 24 Jul 11, 2005

CA3140, CA3140A Tone Control Circuits Bass treble boost and cut are 15dB at 100Hz and 10kHz, respectively. Full peak-to-peak output is available up to at least High slew rate, wide bandwidth, high output voltage capability 20kHz due to the high slew rate of the CA3140. The amplifier and high input impedance are all characteristics required of gain is 3dB down from its “flat” position at 70kHz. tone control amplifiers. Two tone control circuits that exploit these characteristics of the CA3140 are shown in Figures 19 Figure 19 shows another tone control circuit with similar boost and 20. and cut specifications. The wideband gain of this circuit is equal to the ultimate boost or cut plus one, which in this case is The first circuit, shown in Figure 20, is the Baxandall tone a gain of eleven. For 20dB boost and cut, the input loading of control circuit which provides unity gain at midband and uses this circuit is essentially equal to the value of the resistance standard linear potentiometers. The high input impedance of from Terminal No. 3 to ground. A detailed analysis of this circuit the CA3140 makes possible the use of low-cost, low-value, is given in “An IC Operational Transconductance Amplifier small size capacitors, as well as reduced load of the driving (OTA) With Power Capability” by L. Kaplan and H. Wittlinger, stage. IEEE Transactions on Broadcast and Television Receivers, Vol. BTR-18, No. 3, August, 1972. FOR SINGLE SUPPLY +30V NOTES: 2.2M 5. 20dB Flat Position Gain. 7 6. 15dB Bass and Treble Boost and Cut 0.005F 0.1F at 100Hz and 10kHz, respectively. 3 + 5.1 CA3140 6 7. 25VP-P output at 20kHz. M 2 - 8. -3dB at 24kHz from 1kHz reference. 4 FOR DUAL SUPPLIES BOOST TREBLE CUT 200k +15V 0.012F (LINEAR) 0.001F 2.2M 0.1 18k 100 100pF 0.005F 7 0.1F F pF 3 + CA3140 6 5.1M - 2 4 0.1F 0.022F 0.0022F 2F -15V - + 10k 1M 100k TONE CONTROL NETWORK CCW (LOG) BOOST BASS CUT TONE CONTROL NETWORK FIGURE 19. TONE CONTROL CIRCUIT USING CA3130 SERIES (20dB MIDBAND GAIN) FOR SINGLE SUPPLY BOOST BASS CUT (LINEAR) 0.047F 240k 5M 240k FOR DUAL SUPPLIES 2.2M +32V 750 750 +15V pF pF 7 0.1 F 7 3 + 0.1F 3 + 0.1 2.2 CA3140 6 2.2M F M 2 - 0.047F TONE CONTROL 2 C-A3140 6 4 NETWORK 4 0.1F 20pF  -15V 9. 15dB Bass and Treble Boost and Cut at 100Hz and 10kHz, Respectively. 51k 5M 51k (LINEAR) 10. 25VP-P Output at 20kHz. BOOST TREBLE CUT 11. -3dB at 70kHz from 1kHz Reference. TONE CONTROL NETWORK 12. 0dB Flat Position Gain. FIGURE 20. BAXANDALL TONE CONTROL CIRCUIT USING CA3140 SERIES FN957 Rev.10.00 Page 16 of 24 Jul 11, 2005

CA3140, CA3140A Wien Bridge Oscillator OUTPUT Another application of the CA3140 that makes excellent use of +15V 1T9HVDP <-P0 .T3O% 22VP-P its high input impedance, high slew rate, and high voltage R2 qualities is the Wien Bridge sine wave oscillator. A basic Wien C2 1000pF 7 0.1F 3 + CA3109 8 9 Bridge oscillator is shown in Figure 21. When R1 = R2 = R and CA3140 6 ADRIORDAEY Cf=1 1=/ (C22 R=C C), athned ftrheeq guaeinnc rye eqquuiraetdio fno rr eodsuccilleasti oton ,t hAeO fSaCm iilsia r R1 1pC0F100 2 - 4 S0O.U1FB FCSTAR30A1T9E 6 2 1 equal to 3. Note that if C2 is increased by a factor of four and 7 3 R2 is reduced by a factor of four, the gain required for 0.1F -15V oscillation becomes 1.5, thus permitting a potentially higher 7.5k 5 4 operating frequency closer to the gain bandwidth product of the R1 = R2 = R CA3140. 50Hz, R = 3.3M C2 R2 NOTES: 1 100Hz, R = 1.6M 3.6k f = ------------------------------------------- 1kHz, R =160M 2 R C R C 500 1 1 2 2 10kHz, R =16M + 30kHz, R =5.1M OUTPUT C R - A = 1+-----1--+-----2-- FIGURE 22. WIEN BRIDGE OSCILLATOR CIRCUIT USING OSC C R RF 2 1 CA3140 Simple Sample-and-Hold System C1 R1 RS ACL = 1+R-R----F--- S Figure 23 shows a very simple sample-and-hold system using the CA3140 as the readout amplifier for the storage capacitor. The CA3080A serves as both input buffer amplifier and low FIGURE 21. BASIC WIEN BRIDGE OSCILLATOR CIRCUIT feed-through transmission switch (see Note 13). System offset USING AN OPERATIONAL AMPLIFIER nulling is accomplished with the CA3140 via its offset nulling terminals. A typical simulated load of 2k and 30pF is shown Oscillator stabilization takes on many forms. It must be in the schematic. precisely set, otherwise the amplitude will either diminish or reach some form of limiting with high levels of distortion. The element, RS, is commonly replaced with some variable STROBE 30k 0 SAMPLE resistance element. Thus, through some control means, the -15 HOLD 1N914 value of RS is adjusted to maintain constant oscillator output. A FET channel resistance, a thermistor, a lamp bulb, or other +15V device whose resistance increases as the output amplitude is 1N914 +15V increased are a few of the elements often utilized. 2k 5 7 0.1F 3.5k INPUT 3 + 7 Figure 22 shows another means of stabilizing the oscillator CA3080A 6 3 + with a zener diode shunting the feedback resistor (RF of Figure 2 - 4 2 C-A31404 06.1 21). As the output signal amplitude increases, the zener diode 1 F 0.1F 5 impedance decreases resulting in more feedback with 2k -15V 100k consequent reduction in gain; thus stabilizing the amplitude of 2k -15V the output signal. Furthermore, this combination of a monolithic 200pF C1 zener diode and bridge rectifier circuit tends to provide a zero 200pF 400 2k temperature coefficient for this regulating system. Because this bridge rectifier system has no time constant, i.e., thermal time 0.1F 30pF SIMULATED LOAD constant for the lamp bulb, and RC time constant for filters NOT REQUIRED often used in detector networks, there is no lower frequency limit. For example, with 1F polycarbonate capacitors and FIGURE 23. SAMPLE AND HOLD CIRCUIT 22M for the frequency determining network, the operating frequency is 0.007Hz. In this circuit, the storage compensation capacitance (C1) is only 200pF. Larger value capacitors provide longer “hold” As the frequency is increased, the output amplitude must be periods but with slower slew rates. The slew rate is: reduced to prevent the output signal from becoming slew-rate dv I limited. An output frequency of 180kHz will reach a slew rate of ------ = ---- = 0.5mA200pF = 2.5Vs dt C approximately 9V/s when its amplitude is 16VP-P. NOTE: 13. AN6668 “Applications of the CA3080 and CA 3080A High Performance Operational Transconductance Amplifiers”. FN957 Rev.10.00 Page 17 of 24 Jul 11, 2005

CA3140, CA3140A Pulse “droop” during the hold interval is 170pA/200pF which is Current Amplifier 0.85V/s; (i.e., 170pA/200pF). In this case, 170pA represents The low input terminal current needed to drive the CA3140 the typical leakage current of the CA3080A when strobed off. If C1 makes it ideal for use in current amplifier applications such as were increased to 2000pF, the “hold-droop” rate will decrease to the one shown in Figure 25 (see Note 14). In this circuit, low 0.085V/s, but the slew rate would decrease to 0.25V/s. The current is supplied at the input potential as the power supply to parallel diode network connected between Terminal 3 of the load resistor RL. This load current is increased by the CA3080A and Terminal 6 of the CA3140 prevents large input multiplication factor R2/R1, when the load current is monitored signal feedthrough across the input terminals of the CA3080A to by the power supply meter M. Thus, if the load current is the 200pF storage capacitor when the CA3080A is strobed off. 100nA, with values shown, the load current presented to the Figure 24 shows dynamic characteristic waveforms of this supply will be 100A; a much easier current to measure in sample-and-hold system. many systems. R1 10k +15V IL x RR21 7 0.1F 3 + R2 M CA3140 6 2 - 0.1F 10M IL 4 POWER 1 SUPPLY 5 RL 100k Top Trace: Output; 50mV/Div., 200ns/Div. Bottom Trace: Input; 50mV/Div., 200ns/Div. 4.3k -15V FIGURE 25. BASIC CURRENT AMPLIFIER FOR LOW CURRENT MEASUREMENT SYSTEMS Note that the input and output voltages are transferred at the same potential and only the output current is multiplied by the scale factor. The dotted components show a method of decoupling the circuit from the effects of high output load capacitance and the potential oscillation in this situation. Essentially, the necessary Top Trace: Output Signal; 5V/Div, 2s/Div. high frequency feedback is provided by the capacitor with the Center Trace: Difference of Input and Output Signals through dotted series resistor providing load decoupling. Tektronix Amplifier 7A13; 5mV/Div., 2s/Div. Full Wave Rectifier Bottom Trace: Input Signal; 5V/Div., 2s/Div. LARGE SIGNAL RESPONSE AND SETTLING TIME Figure 26 shows a single supply, absolute value, ideal full- wave rectifier with associated waveforms. During positive excursions, the input signal is fed through the feedback network directly to the output. Simultaneously, the positive excursion of the input signal also drives the output terminal (No. 6) of the inverting amplifier in a negative going excursion such that the 1N914 diode effectively disconnects the amplifier from the signal path. During a negative going excursion of the input signal, the CA3140 functions as a normal inverting amplifier with a gain equal to -R2/R1. When the equality of the two equations shown in Figure 26 is satisfied, the full wave output is symmetrical. SAMPLING RESPONSE NOTE: Top Trace: Output; 100mV/Div., 500ns/Div. 14. “Operational Amplifiers Design and Applications”, J. G. Graeme, Bottom Trace: Input; 20V/Div., 500ns/Div. McGraw-Hill Book Company, page 308, “Negative Immittance FIGURE 24. SAMPLE AND HOLD SYSTEM DYNAMIC Converter Circuits”. CHARACTERISTICS WAVEFORMS FN957 Rev.10.00 Page 18 of 24 Jul 11, 2005

CA3140, CA3140A R2 +15V 5k +15V 0.1F 10k 7 SIMULATED R1 0.1F INPUT 3 + LOAD 2 - 7 10k CA3140 6 CA3140 6 2 - 3 + 1N914 100pF 2k 4 4 5 10k 1 8 R3 PEAK 0.1F ADJUST -15V 100k 10k BW (-3dB) = 4.5MHz OFFSET SR = 9V/s ADJUST 2k R R 2 3 GAIN = R------- = X = R--------R---------+-----R------- 0.05F 1 1 2 3 2 FIGURE 28A. TEST CIRCUIT R = X------+-----X------R 3  1–X 1 FOR X = 0.5 --5----k--------- = R-----2-- 10k R 1 R = 10k0----.--7---5-- = 15k 3 0.5 20VP-P Input BW (-3dB) = 290kHz, DC Output (Avg) = 3.2V OUTPUT 0 Top Trace: Output; 50mV/Div., 200ns/Div. Bottom Trace: Input; 50mV/Div., 200ns/Div. INPUT FIGURE 28B. SMALL SIGNAL RESPONSE 0 FIGURE 26. SINGLE SUPPLY, ABSOLUTE VALUE, IDEAL FULL WAVE RECTIFIER WITH ASSOCIATED WAVEFORMS +15V 0.01F RS 7 3 + 1M CA3140 6 NOISE VOLTAGE OUTPUT 2 - 4 (Measurement made with Tektronix 7A13 differential amplifier.) 30.1k 0.01F -15V Top Trace: Output Signal; 5V/Div., 5s/Div. Center Trace: Difference Signal; 5mV/Div., 5s/Div. BW (-3dB) = 140kHz 1k Bottom Trace: Input Signal; 5V/Div., 5s/Div. TOTAL NOISE VOLTAGE (REFERRED TO INPUT) = 48V (TYP) FIGURE 28C. INPUT-OUTPUT DIFFERENCE SIGNAL SHOWING SETTLING TIME FIGURE 27. TEST CIRCUIT AMPLIFIER (30dB GAIN) USED FOR WIDEBAND NOISE MEASUREMENT FIGURE 28. SPLIT SUPPLY VOLTAGE FOLLOWER TEST CIRCUIT AND ASSOCIATED WAVEFORMS FN957 Rev.10.00 Page 19 of 24 Jul 11, 2005

CA3140, CA3140A Typical Performance Curves 20 RL = 2k Hz) RCLL == 21k00pF M B) TA = -55oC UCT ( 10 GAIN (d 125 12255ooCC H PROD TA = -55oC 12255ooCC E 100 T G D A WI LT 75 D O N V A OP 50 N B O AI N-L 25 G E P O 0 1 0 5 10 15 20 25 0 5 10 15 20 25 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) FIGURE 29. OPEN-LOOP VOLTAGE GAIN vs SUPPLY FIGURE 30. GAIN BANDWIDTH PRODUCT vs SUPPLY VOLTAGE AND TEMPERATURE VOLTAGE AND TEMPERATURE RL = 2k RL =  CL = 100pF 7 A) m NT ( 6 TA = -55oC 25oC RE 5 25oC 125oC R U 20 TA = -55oC Y C 4 125oC L s) 15 PP 3  U V/ S E ( 10 NT 2 W RAT 5 ESCE 1 E UI L Q S 0 0 0 5 10 15 20 25 0 5 10 15 20 25 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) FIGURE 31. SLEW RATE vs SUPPLY VOLTAGE AND FIGURE 32. QUIESCENT SUPPLY CURRENT vs SUPPLY TEMPERATURE VOLTAGE AND TEMPERATURE SUPPLY VOLTAGE: VS =15V B) 120 SUPPLY VOLTAGE: VS =15V TA = 25oC O (d TA = 25oC 25 TI 100 A )P R P- N G (V 20 CTIO 80 N E WI J S 15 RE 60 T E U D P O UT 10 M 40 O N- O M 5 M 20 O C 0 0 10K 100K 1M 4M 101 102 103 104 105 106 107 FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 33. MAXIMUM OUTPUT VOLTAGE SWING vs FIGURE 34. COMMON MODE REJECTION RATIO vs FREQUENCY FREQUENCY FN957 Rev.10.00 Page 20 of 24 Jul 11, 2005

CA3140, CA3140A Typical Performance Curves (Continued) 1000 E (nV/Hz) STAU P= P2L5Yo CVOLTAGE: VS =15V dB) 100 STAU P=P 2L5Yo CVOLTAGE: VS =15V LTAG 100 ATIO ( 80 +PSRR O R E V ON OIS CTI 60 N E UT EJ P R N 10 Y 40 -PSRR T I PL N P E U EQUIVAL 1 POWER S 200 P(POSWRRER) = S UVPIOPL/YV RSEJECTION RATIO 1 101 102 103 104 105 101 102 103 104 105 106 107 FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 35. EQUIVALENT INPUT NOISE VOLTAGE vs FIGURE 36. POWER SUPPLY REJECTION RATIO vs FREQUENCY FREQUENCY FN957 Rev.10.00 Page 21 of 24 Jul 11, 2005

CA3140, CA3140A Metallization Mask Layout 0 10 20 30 40 50 60 65 61 60 50 40 58-66 30 (1.473-1.676) 20 10 0 4-10 (0.102-0.254) 62-70 (1.575-1.778) Dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch). The photographs and dimensions represent a chip when it is part of the wafer. When the wafer is cut into chips, the cleavage angles are 57o instead of 90 with respect to the face of the chip. Therefore, the isolated chip is actually 7 mils (0.17mm) larger in both dimensions. FN957 Rev.10.00 Page 22 of 24 Jul 11, 2005

CA3140, CA3140A Dual-In-Line Plastic Packages (PDIP) E8.3 (JEDEC MS-001-BA ISSUE D) N 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX INCHES MILLIMETERS AREA 1 2 3 N/2 SYMBOL MIN MAX MIN MAX NOTES -B- A - 0.210 - 5.33 4 -A- D E A1 0.015 - 0.39 - 4 BASE A2 0.115 0.195 2.93 4.95 - PLANE A2 -C- A B 0.014 0.022 0.356 0.558 - SEATING PLANE L CL B1 0.045 0.070 1.15 1.77 8, 10 D1 D1 A1 eA C 0.008 0.014 0.204 0.355 - B1 e eC C D 0.355 0.400 9.01 10.16 5 B eB D1 0.005 - 0.13 - 5 0.010 (0.25) M C A B S E 0.300 0.325 7.62 8.25 6 NOTES: E1 0.240 0.280 6.10 7.11 5 1. Controlling Dimensions: INCH. In case of conflict between e 0.100 BSC 2.54 BSC - English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. eA 0.300 BSC 7.62 BSC 6 3. Symbols are defined in the “MO Series Symbol List” in Section eB - 0.430 - 10.92 7 2.2 of Publication No. 95. L 0.115 0.150 2.93 3.81 4 4. Dimensions A, A1 and L are measured with the package seated N 8 8 9 in JEDEC seating plane gauge GS-3. Rev. 0 12/93 5. D, D1, and E1 dimensions do not include mold flash or protru- sions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be per- pendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads uncon- strained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). FN957 Rev.10.00 Page 23 of 24 Jul 11, 2005

CA3140, CA3140A Small Outline Plastic Packages (SOIC) M8.15 (JEDEC MS-012-AA ISSUE C) N 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC INDEX AREA H 0.25(0.010) M B M PACKAGE E INCHES MILLIMETERS -B- SYMBOL MIN MAX MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - 1 2 3 L A1 0.0040 0.0098 0.10 0.25 - SEATING PLANE B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - -A- D A h x 45o D 0.1890 0.1968 4.80 5.00 3 E 0.1497 0.1574 3.80 4.00 4 -C- µ e 0.050 BSC 1.27 BSC - e A1 C H 0.2284 0.2440 5.80 6.20 - B 0.10(0.004) h 0.0099 0.0196 0.25 0.50 5 0.25(0.010) M C A M B S L 0.016 0.050 0.40 1.27 6 N 8 8 7 NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of  0o 8o 0o 8o - Publication Number 95. Rev. 0 12/93 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. © Copyright Intersil Americas LLC 2002-2005. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN957 Rev.10.00 Page 24 of 24 Jul 11, 2005