Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) KPS Series, High Voltage, X7R Dielectric, 500 – 630 VDC (Commercial Grade) Overview KEMET Power Solutions (KPS) High Voltage stacked KEMET’s KPS Series devices in X7R dielectric exhibit a capacitors utilize a proprietary lead-frame technology predictable change in capacitance with respect to time and to vertically stack one or two multilayer ceramic chip voltage, and boast a minimal change in capacitance with capacitors into a single compact surface mount package. reference to ambient temperature. Capacitance change is The attached lead-frame mechanically isolates the limited to ±15% from −55°C to +125°C. These devices are capacitor(s) from the printed circuit board, thereby capable of Pb-Free reflow profiles and provide lower ESR, ESL offering advanced mechanical and thermal stress and higher ripple current capability when compared to other performance. Isolation also addresses concerns for dielectric solutions. audible microphonic noise that may occur when a bias voltage is applied. A two-chip stack offers up to double Conventional uses include both snubbers and filters the capacitance in the same or smaller design footprint in applications such as switching power supplies and when compared to traditional surface mount MLCC lighting ballasts. Their exceptional performance at high devices. Providing up to 10 mm of board flex capability, frequencies has made high voltage ceramic capacitors the KPS Series High Voltage capacitors are environmentally preferred dielectric choice of design engineers worldwide. friendly and in compliance with RoHS legislation. In addition to their use in power supplies, these capacitors are widely used in industries related to automotive (hybrid), telecommunications, medical, military, aerospace, semiconductors, and test/diagnostic equipment. Benefits • −55°C to +125°C operating temperature range • Reliable and robust termination system • EIA 2220 case size • DC voltage ratings of 500 V and 630 V • Capacitance offerings ranging from 0.047 µF up to 1.0 µF • Available capacitance tolerances of ±10% and ±20% • Higher capacitance in the same footprint • Potential board space savings Ordering Information C 2220 C 105 M C R 2 C 7186 Rated Packaging/ Case Size Specification/ Capacitance Capacitance Failure Rate/ Ceramic Voltage Dielectric Leadframe Finish2 Grade (L"x W") Series Code (pF) Tolerance1 Design (VDC) (C-Spec) 2220 C = Two significant K = ±10% C = 500 R = X7R 1 = KPS Single C = 100% Matte Sn See “Packaging Standard digits and M = ±20% B = 630 Chip Stack C-Spec Ordering number of 2 = KPS Double Options Table” zeros. Chip Stack below 1 Double chip stacks ("2" in the 13th character position of the ordering code) are only available in M (±20%) capacitance tolerance. Single chip stacks ("1" in the 13th character position of the ordering code) are available in K (±10%) or M (±20%) tolerances. 2 Additional leadframe finish options may be available. Contact KEMET for details. One world. One KEMET © KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 • 864-963-6300 • www.kemet.com C1036_X7R_KPS_HV_SMD • 11/16/2016 1

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) KPS Series, High Voltage, X7R Dielectric, 500 VDC – 630 VDC (Commercial Grade) Packaging C-Spec Ordering Options Table Packaging/Grade Packaging Type1 Ordering Code (C-Spec)2 7" Reel (Embossed Plastic Tape)/Unmarked 7186 13" Reel (Embossed Plastic Tape)/Unmarked 7289 1 The terms "Marked" and "Unmarked" pertain to laser marking option of capacitors. All packaging options labeled as "Unmarked" will contain capacitors that have not been laser marked. The option to laser mark is not available on these devices. For more information see "Capacitor Marking". Benefits cont'd • Advanced protection against thermal and mechanical • Lead (Pb)-free, RoHS and REACH compliant stress • Capable of Pb-free reflow profiles • Provides up to 10 mm of board flex capability • Non-polar device, minimizing installation concerns • Reduces audible microphonic noise • Film alternative • Extremely low ESR and ESL Applications Typical applications include switch mode power supplies (input filters, resonators, tank circuits, snubber circuits, output filters), high voltage coupling and DC blocking, lighting ballasts, voltage multiplier circuits, DC/DC converters and coupling capacitors in Ćuk converters. Markets include power supply, LCD fluorescent backlight ballasts, HID lighting, telecom equipment, industrial and medical equipment/control, LAN/WAN interface, analog and digital modems, and automotive (electric and hybrid vehicles, charging stations and lighting applications). Application Note X7R dielectric is not recommended for AC line filtering or pulse applications. © KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 • 864-963-6300 • www.kemet.com C1036_X7R_KPS_HV_SMD • 11/16/2016 2

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) KPS Series, High Voltage, X7R Dielectric, 500 VDC – 630 VDC (Commercial Grade) Qualification/Certification Commercial Grade products are subject to internal qualification. Details regarding test methods and conditions are referenced in Table 4 , Performance and Reliability. Environmental Compliance Lead (Pb)-free, RoHS, and REACH compliant without exemptions. Dimensions – Millimeters (Inches) TOP VIEW PROFILE VIEW Single or Double Chip Stack Double Chip Stack Single Chip Stack L L W H H LW LW Number of EIA Size Metric Size L W H LW Mounting Chips Code Code Length Width Height Lead Width Technique 6.00 (0.236) 5.00 (0.197) 3.50 (0.138) 1.60 (0.063) Single 2220 5650 ±0.50 (0.020) ±0.50 (0.020) ±0.30 (0.012) ±0.30 (0.012) Solder Reflow 6.00 (0.236) 5.00 (0.197) 5.00 (0.197) 1.60 (0.063) Only Double 2220 5650 ±0.50 (0.020) ±0.50 (0.020) ±0.50 (0.020) ±0.30 (0.012) © KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 • 864-963-6300 • www.kemet.com C1036_X7R_KPS_HV_SMD • 11/16/2016 3

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) KPS Series, High Voltage, X7R Dielectric, 500 VDC – 630 VDC (Commercial Grade) Electrical Parameters/Characteristics Item Parameters/Characteristics Operating Temperature Range −55°C to +125°C Capacitance Change with Reference to ±15% +25°C and 0 Vdc Applied (TCC) 1Aging Rate (Maximum % Capacitance Loss/Decade Hour) 3.0% 150% of rated voltage for voltage rating of < 1000V 2Dielectric Withstanding Voltage (DWV) 120% of rated voltage for voltage rating of ≥ 1000V (5±1 seconds and charge/discharge not exceeding 50mA) 3Dissipation Factor (DF) Maximum Limit at 25°C 2.5% 4Insulation Resistance (IR) Minimum Limit at 25°C 1,000 megohm microfarads or 100GΩ (500 VDC applied for 120±5 seconds at 25°C) 1 Regarding Aging Rate: Capacitance measurements (including tolerance) are indexed to a referee time of 1,000 hours. 2 DWV is the voltage a capacitor can withstand (survive) for a short period of time. It exceeds the nominal and continuous working voltage of the capacitor. 3 Capacitance and dissipation factor (DF) measured under the following conditions: 1kHz ± 50Hz and 1.0 ± 0.2 Vrms if capacitance ≤ 10µF 120Hz ± 10Hz and 0.5 ± 0.1 Vrms if capacitance > 10µF 4 To obtain IR limit, divide MΩ-µF value by the capacitance and compare to GΩ limit. Select the lower of the two limits. Note: When measuring capacitance it is important to ensure the set voltage level is held constant. The HP4284 and Agilent E4980 have a feature known as Automatic Level Control (ALC). The ALC feature should be switched to "ON". Post Environmental Limits High Temperature Life, Biased Humidity, Moisture Resistance Rated DC Capacitance Dissipation Factor Capacitance Insulation Dielectric Voltage Value (Maximum %) Shift Resistance > 25 3.0 10% of Initial X7R 16/25 All 5.0 ±20% Limit < 16 7.5 © KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 • 864-963-6300 • www.kemet.com C1036_X7R_KPS_HV_SMD • 11/16/2016 4

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) KPS Series, High Voltage, X7R Dielectric, 500 VDC – 630 VDC (Commercial Grade) Table 1 – Capacitance Range/Selection Waterfall (2220 Case Sizes) Case Size/Series C2220C Voltage Code C B D Capacitance Capacitance Rated Voltage (VDC) 500 630 1000 Code Capacitance Product Availability and Chip Thickness Tolerance Codes – See Table 2 for Chip Thickness Dimensions Single Chip Stack 0.047 µF 473 K M JP JP 0.10 µF 104 K M JP JP 0.15 µF 154 K M JP JP 0.22 µF 224 K M JP JP 0.33 µF 334 K M JP 0.47 µF 474 K M JP Double Chip Stack 0.10 µF 104 M JR JR 0.22 µF 224 M JR JR 0.33 µF 334 M JR JR 0.47 µF 474 M JR JR 0.68 µF 684 M JR 1.0 µF 105 M JR Rated Voltage (VDC) 500 630 1000 Capacitance Capacitance Voltage Code C B D Code Case Size/Series C2220C These products are protected under US Patent 8,331,078 other patents pending, and any foreign counterparts. SnPb termination options available. "C"(100% Sn) & "L"(SnPb) Terminations. Table 2 – Chip Thickness/Tape & Reel Packaging Quantities Thickness Case Thickness ± Paper Quantity Plastic Quantity Code Size Range (mm) 7" Reel 13" Reel 7" Reel 13" Reel JP 2220 3.50 ± 0.30 0 0 300 1,300 JR 2220 5.00 ± 0.50 0 0 200 800 Package quantity based on finished chip thickness specifications. © KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 • 864-963-6300 • www.kemet.com C1036_X7R_KPS_HV_SMD • 11/16/2016 5

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) KPS Series, High Voltage, X7R Dielectric, 500 VDC – 630 VDC (Commercial Grade) Table 3 – KPS Land Pattern Design Recommendations (mm) V1 METRIC Median (Nominal) Land EIA SIZE SIZE Protrusion CODE CODE Y Y C Y X V1 V2 2220 5650 2.69 2.08 4.78 7.70 6.00 X X V2 C C Grid Placement Courtyard Soldering Process KEMET’s KPS Series devices are compatible with IR Profile Feature SnPb Assembly Pb-Free Assembly reflow techniques. Preheating of these components is Preheat/Soak recommended to avoid extreme thermal stress. KEMET's Temperature Minimum (T ) 100°C 150°C Smin recommended profile conditions for IR reflow reflect the Temperature Maximum (T ) 150°C 200°C Smax profile conditions of the IPC/J–STD–020D standard for Time (t) from T to T ) 60 – 120 seconds 60 – 120 seconds s smin smax moisture sensitivity testing. Ramp-up Rate (T to T) 3°C/seconds maximum 3°C/seconds maximum L P Liquidous Temperature (T) 183°C 217°C L To prevent degradation of temperature cycling capability, Time Above Liquidous (t) 60 – 150 seconds 60 – 150 seconds L care must be taken to prevent solder from flowing into Peak Temperature (T) 235°C 250°C P the inner side of the lead frames (inner side of "J" lead in Time within 5°C of Maximum 20 seconds maximum 10 seconds maximum Peak Temperature (t) contact with the circuit board). P Ramp-down Rate (T to T) 6°C/seconds maximum 6°C/seconds maximum P L Time 25°C to Peak After soldering, the capacitors should be air cooled to 6 minutes maximum 8 minutes maximum Temperature room temperature before further processing. Forced air Note: All temperatures refer to the center of the package, measured on the cooling is not recommended. package body surface that is facing up during assembly reflow. Hand soldering should be performed with care due to the difficulty in process control. If performed, care should be T taken to avoid contact of the soldering iron to the capacitor P Maximum Ramp Up Rate = 3ºC/sec tP Maximum Ramp Down Rate = 6ºC/sec body. The iron should be used to heat the solder pad, T applying solder between the pad and the lead, until reflow e L tL r u occurs. Once reflow occurs, the iron should be removed rat Tsmax e immediately. (Preheating is required when hand soldering to p m T avoid thermal shock.) e smin t T s 25 25ºC to Peak Time © KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 • 864-963-6300 • www.kemet.com C1036_X7R_KPS_HV_SMD • 11/16/2016 6

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) KPS Series, High Voltage, X7R Dielectric, 500 VDC – 630 VDC (Commercial Grade) Table 4 – Performance & Reliability: Test Methods and Conditions Stress Reference Test or Inspection Method Terminal Strength JIS–C–6429 Appendix 1, Note: Force of 1.8 kg for 60 seconds. Board Flex JIS–C–6429 Appendix 2, Note: 5.0 mm minimum Magnification 50 X. Conditions: a) Method B, 4 hours at 155°C, dry heat at 235°C Solderability J–STD–002 b) Method B at 215°C category 3 c) Method D, category 3 at 250°C Temperature Cycling JESD22 Method JA–104 1,000 cycles (−55°C to +125°C). Measurement at 24 hours +/−4 hours after test conclusion. Load Humidity: 1,000 hours 85°C/85% RH and 200 VDC maximum. Add 100 K ohm resistor. MIL–STD–202 Method Measurement at 24 hours +/−4 hours after test conclusion. Biased Humidity 103 Low Volt Humidity: 1,000 hours 85°C/85% RH and 1.5 V. Add 100 K ohm resistor. Measurement at 24 hours +/−4 hours after test conclusion. MIL–STD–202 Method t = 24 hours/cycle. Steps 7a and 7b not required. Moisture Resistance 106 Measurement at 24 hours +/−4 hours after test conclusion. MIL–STD–202 Method −55°C/+125°C. Note: Number of cycles required – 300. Maximum transfer time – 20 Thermal Shock 107 seconds. Dwell time – 15 minutes. Air-Air. MIL–STD–202 Method High Temperature Life 1,000 hours at 125°C with rated voltage applied. 108 MIL–STD–202 Method Storage Life 150°C, 0 VDC for 1,000 hours. 108 5 g's for 20 minutes, 12 cycles each of 3 orientations. Note: Use 8" X 5" PCB 0.031" thick, MIL–STD–202 Method Vibration 7 secure points on one long side and 2 secure points at corners of opposite sides. Parts 204 mounted within 2" from any secure point. Test from 10 – 2,000 Hz. MIL–STD–202 Method Mechanical Shock Figure 1 of Method 213, Condition F. 213 MIL–STD–202 Method Resistance to Solvents Add aqueous wash chemical, OKEM Clean or equivalent. 215 Storage and Handling Ceramic chip capacitors should be stored in normal working environments. While the chips themselves are quite robust in other environments, solderability will be degraded by exposure to high temperatures, high humidity, corrosive atmospheres, and long term storage. In addition, packaging materials will be degraded by high temperature–reels may soften or warp and tape peel force may increase. KEMET recommends that maximum storage temperature not exceed 40ºC and maximum storage humidity not exceed 70% relative humidity. Temperature fluctuations should be minimized to avoid condensation on the parts and atmospheres should be free of chlorine and sulfur bearing compounds. For optimized solderability chip stock should be used promptly, preferably within 1.5 years of receipt. © KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 • 864-963-6300 • www.kemet.com C1036_X7R_KPS_HV_SMD • 11/16/2016 7

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) KPS Series, High Voltage, X7R Dielectric, 500 VDC – 630 VDC (Commercial Grade) Construction Detailed Cross Section Dielectric Material (BaTiO) 3 Leadframe (Phosphor Bronze - Alloy 510) Leadframe Attach (High Melting Point Solder) Inner Electrodes (Ni) End Termination/ External Electrode (Cu) Barrier Layer (Ni) Dielectric Material (BaTiO) Termination Finish 3 (Sn) Termination Finish (Sn) Inner Electrodes Barrier Layer (Ni) (Ni) End Termination/ External Electrode (Cu) Product Marking Laser marking option is not available on: • C0G, Ultra Stable X8R and Y5V dielectric devices • EIA 0402 case size devices • EIA 0603 case size devices with Flexible Termination option. • KPS Commercial and Automotive grade stacked devices. These capacitors are supplied unmarked only. © KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 • 864-963-6300 • www.kemet.com C1036_X7R_KPS_HV_SMD • 11/16/2016 8

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) KPS Series, High Voltage, X7R Dielectric, 500 VDC – 630 VDC (Commercial Grade) Tape & Reel Packaging Information KEMET offers multilayer ceramic chip capacitors packaged in 8, 12 and 16 mm tape on 7" and 13" reels in accordance with EIA Standard 481. This packaging system is compatible with all tape-fed automatic pick and place systems. See Table 2 for details on reeling quantities for commercial chips. Table 5 – Carrier Tape Confi guration – Embossed Plastic (mm) EIA Case Size Tape Size (W)* Pitch (P )* 1 01005 – 0402 8 2 0603 – 1210 8 4 1805 – 1808 12 4 ≥ 1812 12 8 KPS 1210 12 8 KPS 1812 & 2220 16 12 Array 0508 & 0612 8 4 *Refer to Figure 1 for W and P carrier tape reference locations. 1 *Refer to Table 5 for tolerance specifi cations. © KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 • 864-963-6300 • www.kemet.com C1036_X7R_KPS_HV_SMD • 11/16/2016 9

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) KPS Series, High Voltage, X7R Dielectric, 500 VDC – 630 VDC (Commercial Grade) Figure 1 – Embossed (Plastic) Carrier Tape Dimensions T P2 T2 ØDo Po [10 pitches cumulative E1 tolerance on tape ± 0.2 mm] Ao F Ko W B1 Bo E2 S1 P1 T1 Center Lines of Cavity ØD1 FEomrb coasvsitmy esnizte, Cover Tape see Note 1 Table 4 B1 is for tape feeder reference only, including draft concentric about B o. User Direction of Unreeling Table 6 – Embossed (Plastic) Carrier Tape Dimensions Metric will govern Constant Dimensions — Millimeters (Inches) D Minimum R Reference S Minimum T T Tape Size D 1 E P P 1 1 0 Note 1 1 0 2 Note 2 Note 3 Maximum Maximim 1.0 25.0 8 mm (0.039) (0.984) 1.5+0.10/0.0−0.0 1.75±0.10 4.0±0.10 2.0±0.05 0.600 0.600 0.100 12 mm (0.059+0.004/−0.0) 1.5 (0.069±0.004) (0.157±0.004) (0.079±0.002) 30 (0.024) (0.024) (0.004) (0.059) (1.181) 16 mm Variable Dimensions — Millimeters (Inches) B Maximum T W Tape Size Pitch 1 E Minimum F P 2 A, B & K Note 4 2 1 Maximum Maximum 0 0 0 4.35 6.25 3.5±0.05 4.0±0.10 2.5 8.3 8 mm Single (4 mm) (0.171) (0.246) (0.138±0.002) (0.157±0.004) (0.098) (0.327) Single (4 mm) & 8.2 10.25 5.5±0.05 8.0±0.10 4.6 12.3 12 mm Note 5 Double (8 mm) (0.323) (0.404) (0.217±0.002) (0.315±0.004) (0.181) (0.484) 12.1 14.25 7.5±0.05 12.0±0.10 4.6 16.3 16 mm Triple (12 mm) (0.476) (0.561) (0.138±0.002) (0.157±0.004) (0.181) (0.642) 1. The embossment hole location shall be measured from the sprocket hole controlling the location of the embossment. Dimensions of embossment location and hole location shall be applied independent of each other. 2. The tape with or without components shall pass around R without damage (see Figure 5). 3. If S < 1.0 mm, there may not be enough area for cover tape to be properly applied (see EIA Standard 481 paragraph 4.3 section b). 1 4. B dimension is a reference dimension for tape feeder clearance only. 1 5. The cavity defi ned by A, B and K shall surround the component with suffi cient clearance that: 0 0 0 (a) the component does not protrude above the top surface of the carrier tape. (b) the component can be removed from the cavity in a vertical direction without mechanical restriction, after the top cover tape has been removed. (c) rotation of the component is limited to 20° maximum for 8 and 12 mm tapes and 10° maximum for 16 mm tapes (see Figure 2). (d) lateral movement of the component is restricted to 0.5 mm maximum for 8 and 12 mm wide tape and to 1.0 mm maximum for 16 mm tape (see Figure 3). (e) for KPS Series product, A and B are measured on a plane 0.3 mm above the bottom of the pocket. 0 0 (f) see Addendum in EIA Standard 481 for standards relating to more precise taping requirements. © KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 • 864-963-6300 • www.kemet.com C1036_X7R_KPS_HV_SMD • 11/16/2016 10

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) KPS Series, High Voltage, X7R Dielectric, 500 VDC – 630 VDC (Commercial Grade) Packaging Information Performance Notes 1. Cover Tape Break Force: 1.0 Kg minimum. 2. Cover Tape Peel Strength: The total peel strength of the cover tape from the carrier tape shall be: Tape Width Peel Strength 8 mm 0.1 to 1.0 Newton (10 to 100 gf) 12 and 16 mm 0.1 to 1.3 Newton (10 to 130 gf) The direction of the pull shall be opposite the direction of the carrier tape travel. The pull angle of the carrier tape shall be 165° to 180° from the plane of the carrier tape. During peeling, the carrier and/or cover tape shall be pulled at a velocity of 300 ±10 mm/minute. 3. Labeling: Bar code labeling (standard or custom) shall be on the side of the reel opposite the sprocket holes. Refer to EIA Standards 556 and 624. Figure 2 – Maximum Component Rotation ° T Maximum Component Rotation Maximum Component Rotation Top View Side View Typical Pocket Centerline Tape Maximum ° Width (mm) Rotation ( °) s T 8,12 20 Bo Tape Maximum 16 – 200 10 Width (mm) Rotation ( °) S 8,12 20 Typical Component Centerline 16 – 56 10 72 – 200 5 Ao Figure 3 – Maximum Lateral Movement Figure 4 – Bending Radius 8 mm & 12 mm Tape 16 mm Tape Embossed Punched Carrier Carrier 0.5 mm maximum 1.0 mm maximum 0.5 mm maximum 1.0 mm maximum Bending R R Radius © KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 • 864-963-6300 • www.kemet.com C1036_X7R_KPS_HV_SMD • 11/16/2016 11

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) KPS Series, High Voltage, X7R Dielectric, 500 VDC – 630 VDC (Commercial Grade) Figure 5 – Reel Dimensions W3 Full Radius, (Includes Access Hole at See Note Slot Location flange distortion (Ø 40 mm minimum) at outer edge) W2 (Measured at hub) A D (See Note) N C (Arbor hole W1 (Measured at hub) diameter) If present, tape slot in core for tape start: 2.5 mm minimum width x 10.0 mm minimum depth B (see Note) Note: Drive spokes optional; if used, dimensions B and D shall apply. Table 7 – Reel Dimensions Metric will govern Constant Dimensions — Millimeters (Inches) Tape Size A B Minimum C D Minimum 8 mm 178 ±0.20 (7.008 ±0.008) 1.5 13.0 +0.5/-0.2 20.2 12 mm or (0.059) (0.521 +0.02/-0.008) (0.795) 330 ±0.20 16 mm (13.000 ±0.008) Variable Dimensions — Millimeters (Inches) Tape Size N Minimum W W Maximum W 1 2 3 8.4 +1.5/-0.0 14.4 8 mm (0.331 +0.059/-0.0) (0.567) 50 12.4 +2.0/-0.0 18.4 Shall accommodate tape 12 mm (1.969) (0.488 +0.078/-0.0) (0.724) width without interference 16.4 +2.0/-0.0 22.4 16 mm (0.646 +0.078/-0.0) (0.882) © KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 • 864-963-6300 • www.kemet.com C1036_X7R_KPS_HV_SMD • 11/16/2016 12

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) KPS Series, High Voltage, X7R Dielectric, 500 VDC – 630 VDC (Commercial Grade) Figure 6 – Tape Leader & Trailer Dimensions Embossed Carrier Punched Carrier Carrier Tape 8 mm & 12 mm only Round Sprocket Holes END START Top Cover Tape Elongated Sprocket Holes (32 mm tape and wider) 100 mm Minimum Leader Trailer Components 400 mm Minimum 160 mm Minimum Top Cover Tape Figure 7 – Maximum Camber Elongated sprocket holes Carrier Tape (32 mm & wider tapes) Round Sprocket Holes 1 mm Maximum, either direction Straight Edge 250 mm © KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 • 864-963-6300 • www.kemet.com C1036_X7R_KPS_HV_SMD • 11/16/2016 13

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) KPS Series, High Voltage, X7R Dielectric, 500 VDC – 630 VDC (Commercial Grade) KEMET Electronic Corporation Sales Offi ces For a complete list of our global sales offi ces, please visit www.kemet.com/sales. Disclaimer All product specifi cations, statements, information and data (collectively, the “Information”) in this datasheet are subject to change. The customer is responsible for checking and verifying the extent to which the Information contained in this publication is applicable to an order at the time the order is placed. All Information given herein is believed to be accurate and reliable, but it is presented without guarantee, warranty, or responsibility of any kind, expressed or implied. Statements of suitability for certain applications are based on KEMET Electronics Corporation’s (“KEMET”) knowledge of typical operating conditions for such applications, but are not intended to constitute – and KEMET specifi cally disclaims – any warranty concerning suitability for a specifi c customer application or use. The Information is intended for use only by customers who have the requisite experience and capability to determine the correct products for their application. Any technical advice inferred from this Information or otherwise provided by KEMET with reference to the use of KEMET’s products is given gratis, and KEMET assumes no obligation or liability for the advice given or results obtained. Although KEMET designs and manufactures its products to the most stringent quality and safety standards, given the current state of the art, isolated component failures may still occur. Accordingly, customer applications which require a high degree of reliability or safety should employ suitable designs or other safeguards (such as installation of protective circuitry or redundancies) in order to ensure that the failure of an electrical component does not result in a risk of personal injury or property damage. Although all product–related warnings, cautions and notes must be observed, the customer should not assume that all safety measures are indicted or that other measures may not be required. KEMET is a registered trademark of KEMET Electronics Corporation. © KEMET Electronics Corporation • P.O. Box 5928 • Greenville, SC 29606 • 864-963-6300 • www.kemet.com C1036_X7R_KPS_HV_SMD • 11/16/2016 14