Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade) Overview KEMET’s Y5V dielectric features an 85°C maximum capacitance stability are not of major importance. Y5V operating temperature and is considered “general-purpose.” exhibits a predictable change in capacitance with respect to The Electronics Industries Alliance (EIA) characterizes time and voltage, and displays wide variations in capacitance Y5V dielectric as a Class III material. Components of this with reference to ambient temperature. Capacitance change classification are fixed, ceramic dielectric capacitors, is limited to +22%, −82% from −30°C to +85°C. suited for bypass and decoupling or other applications in which dielectric losses, high insulation resistance and Benefits Applications • −30°C to +85°C operating temperature range Typical applications include limited temperature, decoupling • Lead (Pb)-free, RoHS and REACH compliant and bypass. • EIA 0402, 0603, 0805, 1206, and 1210 case sizes • DC voltage ratings of 6.3 V, 10 V, 16 V, 25 V, and 50 V • Capacitance offerings ranging from 0.022 μF to 22 μF • Available capacitance tolerance of ±20% and +80%/−20% • Non-polar device, minimizing installation concerns • 100% pure matte tin-plated termination finish that allows for excellent solderability Ordering Information C 1210 C 226 Z 4 V A C TU Rated Case Size Specification/ Capacitance Capacitance Failure Rate/ Packaging/ Ceramic Voltage Dielectric Termination Finish1 (L" x W") Series Code (pF) Tolerance Design Grade (C-Spec) (VDC) 0402 C = Standard Two significant M = ±20% 9 = 6.3 V = Y5V A = N/A C = 100% Matte Sn See 0603 digits and Z = +80%/−20% 8 = 10 "Packaging 4 = 16 0805 number of C-Spec 3 = 25 1206 zeros Ordering 5 = 50 1210 Options Table" 1 Additional termination finish options may be available. Contact KEMET for details. One world. One KEMET © KEMET Electronics Corporation • KEMET Tower • One East Broward Boulevard C1005_Y5V_SMD • 9/27/2019 1 Fort Lauderdale, FL 33301 USA • 954-766-2800 • www.kemet.com

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade) Packaging C-Spec Ordering Options Table Packaging/Grade Packaging Type1 Ordering Code (C-Spec) Bulk Bag/Unmarked Not required (Blank) 7" Reel/Unmarked TU 7411 (EIA 0603 and smaller case sizes) 13" Reel/Unmarked 7210 (EIA 0805 and larger case sizes) 7" Reel/Marked TM 7040 (EIA 0603) 13" Reel/Marked 7215 (EIA 0805 and larger case sizes) 7" Reel/Unmarked/2mm pitch2 7081 13" Reel/Unmarked/2mm pitch2 7082 1 Default packaging is "Bulk Bag". An ordering code C-Spec is not required for "Bulk Bag" packaging. 1 The terms "Marked" and "Unmarked" pertain to laser marking option of capacitors. All packaging options labeled as "Unmarked" will contain capacitors that have not been laser marked. Please contact KEMET if you require a laser marked option. For more information see "Capacitor Marking". 2 The 2 mm pitch option allows for double the packaging quantity of capacitors on a given reel size. This option is limited to EIA 0603 (1608 metric) case size devices. For more information regarding 2 mm pitch option see "Tape & Reel Packaging Information". Dimensions – Millimeters (Inches) W L T B S S EIA Size Metric Size L W T B Mounting Separation Code Code Length Width Thickness Bandwidth Technique Minimum 1.00 (0.040) 0.50 (0.020) 0.30 (0.012) Solder Reflow 0402 1005 0.30 (0.012) ±0.05 (0.002) ±0.05 (0.002) ±0.10 (0.004) Only 1.60 (0.063) 0.80 (0.032) 0.35 (0.014) 0603 1608 0.70 (0.028) ±0.15 (0.006) ±0.15 (0.006) ±0.15 (0.006) 2.00 (0.079) 1.25 (0.049) See Table 2 for 0.50 (0.02) Solder Wave or 0805 2012 0.75 (0.030) ±0.20 (0.008) ±0.20 (0.008) Thickness ±0.25 (0.010) Solder Reflow 3.20 (0.126) 1.60 (0.063) 0.50 (0.02) 1206 3216 ±0.20 (0.008) ±0.20 (0.008) ±0.25 (0.010) N/A 3.20 (0.126) 2.50 (0.098) 0.50 (0.02) Solder Reflow 1210 3225 ±0.20 (0.008) ±0.20 (0.008) ±0.25 (0.010) Only © KEMET Electronics Corporation • KEMET Tower • One East Broward Boulevard C1005_Y5V_SMD • 9/27/2019 2 Fort Lauderdale, FL 33301 USA • 954-766-2800 • www.kemet.com

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade) Qualification/Certification Commercial Grade products are subject to internal qualification. Details regarding test methods and conditions are referenced in Table 4, Performance & Reliability. Environmental Compliance Lead (Pb)-free, RoHS, and REACH compliant without exemptions. Electrical Parameters/Characteristics Item Parameters/Characteristics Operating Temperature Range −30°C to +85°C Capacitance Change with Reference to +22%, −82% +25°C and 0 Vdc Applied (TCC) 1Aging Rate (Maximum % Capacitance Loss/Decade Hour) 7.0% 250% of rated voltage 2Dielectric Withstanding Voltage (DWV) (5±1 seconds and charge/discharge not exceeding 50mA) 3Dissipation Factor (DF) Maximum Limit at 25°C 10% (6.3 V and 10 V), 7% (16 V and 25 V) and 5% (50 V ) See Insulation Resistance Limit Table 4Insulation Resistance (IR) Minimum Limit at 25°C (Rated voltage applied for 120±5 seconds at 25°C) 1 Regarding Aging Rate: Capacitance measurements (including tolerance) are indexed to a referee time of 48 or 1,000 hours. Please refer to a part number specific datasheet for referee time details. 2 DWV is the voltage a capacitor can withstand (survive) for a short period of time. It exceeds the nominal and continuous working voltage of the capacitor. 3 See part number specification sheet for frequency and voltage for Capacitance, Dissipation Factor, and TCC measurement conditions. 4 To obtain IR limit, divide MΩ-µF value by the capacitance and compare to GΩ limit. Select the lower of the two limits. Note: When measuring capacitance it is important to ensure the set voltage level is held constant. The HP4284 & Agilent E4980 have a feature known as Automatic Level Control (ALC). The ALC feature should be switched to "ON". Post Environmental Limits High Temperature Life, Biased Humidity, Moisture Resistance Rated DC Capacitance Dissipation Factor Capacitance Insulation Dielectric Voltage Value (Maximum %) Shift Resistance > 25 7.5 10% of Initial Y5V 16/25 All 10.0 ±30% Limit < 16 15.0 © KEMET Electronics Corporation • KEMET Tower • One East Broward Boulevard C1005_Y5V_SMD • 9/27/2019 3 Fort Lauderdale, FL 33301 USA • 954-766-2800 • www.kemet.com

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade) Insulation Resistance Limit Table 100 Megohm 50 Megohm EIA Case Size Microfarads or 10 GΩ Microfarads or 10 GΩ All ≥ 16 V ≤ 10 V Table 1 – Capacitance Range/Selection Waterfall (0402 – 1210 Case Sizes) Case Size/ C0402C C0603C C0805C C1206C C1210C Series Capacitance Voltage Code 9 8 4 9 8 4 3 9 8 4 3 5 9 8 4 3 5 9 8 4 3 5 Capacitance Code Rated Voltage (VDC) 6.3 10 16 6.3 10 16 25 6.3 10 16 25 50 6.3 10 16 25 50 6.3 10 16 25 50 Product Availability and Chip Thickness Codes Capacitance Tolerance See Table 2 for Chip Thickness Dimensions 22,000 pF 223 M Z BB BB BB CF CF CF CF DN DN DN DN DN 27,000 pF 273 M Z BB BB BB CF CF CF CF DN DN DN DN DN 33,000 pF 333 M Z BB BB BB CF CF CF CF DN DN DN DN DN 39,000 pF 393 M Z BB BB BB CF CF CF CF DP DP DP DP DP 47,000 pF 473 M Z BB BB BB CF CF CF CF DO DO DO DO DO 56,000 pF 563 M Z BB BB BB CF CF CF CF DP DP DP DP DP 68,000 pF 683 M Z BB BB BB CF CF CF CF DP DP DP DP DP 82,000 pF 823 M Z BB BB BB CF CF CF CF DP DP DP DP DP 0.10 µF 104 M Z BB BB BB CG CG CG CG DN DN DN DN DN 0.12 µF 124 M Z CG CG CG CG DN DN DN DN 0.15 µF 154 M Z CG CG CG CG DN DN DN DN 0.18 µF 184 M Z CG CG CG CG DN DN DN DN 0.22 µF 224 M Z BB CG CG CG CG DN DN DN DN DG EC EC EC EC FD FD FD FD FD 0.27 µF 274 M Z CG CG CG CG DN DN DN DN EB EB EB EB FD FD FD FD FD 0.33 µF 334 M Z CG CG CG CG DG DG DG DG EB EB EB EB FD FD FD FD FD 0.39 µF 394 M Z CG CG CG DN DN DN DN EB EB EB EB FD FD FD FD FD 0.47 µF 474 M Z BB CG CG CG DG DG DG DG EC EC EC EC FD FD FD FD FD 0.56 µF 564 M Z CG CG DP DP DP DP EB EB EB EB FD FD FD FD FD 0.68 µF 684 M Z CG CG DP DP DP DG EB EB EB EB FD FD FD FD FD 0.82 µF 824 M Z CG CG DG DG DG DG EB EB EB EB FF FF FF FF FF 1.0 µF 105 M Z BB BB CG CG CG CG DP DP DP DG DG EP EP EP EP FH FH FH FH FH 1.2 µF 125 M Z DN DN DN EC EC EC FD FD FD 1.5 µF 155 M Z DN DN DN EC EC EC FD FD FD 1.8 µF 185 M Z DP DP DP ED ED ED FD FD FD 2.2 µF 225 M Z BB BB DG DG DG EC EC EC FJ FJ FJ 3.3 µF 335 M Z DL DL DG EH EH EH FE FE FE 4.7 µF 475 M Z DG DG DG EH² EH² EH² FT FT FT 5.6 µF 565 M Z DF DF EJ EJ EJ FG FG FG 6.8 µF 685 M Z DG DG EJ EJ FH FH FH 10 µF 106 M Z DG DG EH EH EH EH FT² FT² FT² 15 µF 156 M Z FH FH FH 22 µF 226 M Z EH EH FT² FT² FS FS Rated Voltage (VDC) 6.3 10 16 6.3 10 16 25 6.3 10 16 25 50 6.3 10 16 25 50 6.3 10 16 25 50 Capacitance Capacitance Voltage Code 9 8 4 9 8 4 3 9 8 4 3 5 9 8 4 3 5 9 8 4 3 5 Code Case Size/ C0402C C0603C C0805C C1206C C1210C Series xx² Only available in Z tolerance. © KEMET Electronics Corporation • KEMET Tower • One East Broward Boulevard C1005_Y5V_SMD • 9/27/2019 4 Fort Lauderdale, FL 33301 USA • 954-766-2800 • www.kemet.com

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade) Table 2A – Chip Thickness/Tape & Reel Packaging Quantities Thickness Case Thickness ± Paper Quantity1 Plastic Quantity Code Size Range (mm) 7" Reel 13" Reel 7" Reel 13" Reel BB 0402 0.50 ± 0.05 10,000 50,000 0 0 CF 0603 0.80 ± 0.07* 4,000 15,000 0 0 CG 0603 0.80 ± 0.10* 4,000 15,000 0 0 DN 0805 0.78 ± 0.10* 4,000 15,000 0 0 DO 0805 0.80 ± 0.10* 4,000 15,000 0 0 DP 0805 0.90 ± 0.10* 4,000 15,000 0 0 DL 0805 0.95 ± 0.10 0 0 4,000 10,000 DF 0805 1.10 ± 0.10 0 0 2,500 10,000 DG 0805 1.25 ± 0.15 0 0 2,500 10,000 EB 1206 0.78 ± 0.10 4,000 10,000 4,000 10,000 EC 1206 0.90 ± 0.10 0 0 4,000 10,000 ED 1206 1.00 ± 0.10 0 0 2,500 10,000 EP 1206 1.20 ± 0.20 0 0 2,500 10,000 EH 1206 1.60 ± 0.20 0 0 2,000 8,000 EJ 1206 1.70 ± 0.20 0 0 2,000 8,000 FD 1210 0.95 ± 0.10 0 0 4,000 10,000 FE 1210 1.00 ± 0.10 0 0 2,500 10,000 FF 1210 1.10 ± 0.10 0 0 2,500 10,000 FG 1210 1.25 ± 0.15 0 0 2,500 10,000 FH 1210 1.55 ± 0.15 0 0 2,000 8,000 FJ 1210 1.85 ± 0.20 0 0 2,000 8,000 FT 1210 1.90 ± 0.20 0 0 2,000 8,000 FS 1210 2.50 ± 0.30 0 0 1,000 4,000 7" Reel 13" Reel 7" Reel 13" Reel Thickness Case Thickness ± Code Size1 Range (mm) Paper Quantity1 Plastic Quantity Package quantity based on finished chip thickness specifications. 1 If ordering using the 2 mm Tape and Reel pitch option, the packaging quantity outlined in the table above will be doubled. This option is limited to EIA 0603 (1608 metric) case size devices. For more information regarding 2 mm pitch option see “Tape & Reel Packaging Information”. © KEMET Electronics Corporation • KEMET Tower • One East Broward Boulevard C1005_Y5V_SMD • 9/27/2019 5 Fort Lauderdale, FL 33301 USA • 954-766-2800 • www.kemet.com

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade) Table 2B – Bulk Packaging Quantities Loose Packaging Packaging Type Bulk Bag (default) Packaging C-Spec1 N/A2 Case Size Packaging Quantities (pieces/unit packaging) EIA (in) Metric (mm) Minimum Maximum 0402 1005 0603 1608 0805 2012 50,000 1206 3216 1210 3225 1 1808 4520 1812 4532 1825 4564 20,000 2220 5650 2225 5664 1 The "Packaging C-Spec" is a 4 to 8 digit code which identifies the packaging type and/or product grade. When ordering, the proper code must be included in the 15th through 22nd character positions of the ordering code. See "Ordering Information" section of this document for further details. Commercial Grade product ordered without a packaging C-Spec will default to our standard "Bulk Bag" packaging. Contact KEMET if you require a bulk bag packaging option for Automotive Grade products. 2 A packaging C-Spec (see note 1 above) is not required for "Bulk Bag" packaging (excluding Anti-Static Bulk Bag and Automotive Grade products). The 15th through 22nd character positions of the ordering code should be left blank. All product ordered without a packaging C-Spec will default to our standard "Bulk Bag" packaging. © KEMET Electronics Corporation • KEMET Tower • One East Broward Boulevard C1005_Y5V_SMD • 9/27/2019 6 Fort Lauderdale, FL 33301 USA • 954-766-2800 • www.kemet.com

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade) Table 3 – Chip Capacitor Land Pattern Design Recommendations per IPC-7351 Density Level A: Density Level B: Density Level C: EIA Metric Maximum (Most) Median (Nominal) Minimum (Least) Size Size Land Protrusion (mm) Land Protrusion (mm) Land Protrusion (mm) Code Code C Y X V1 V2 C Y X V1 V2 C Y X V1 V2 0402 1005 0.50 0.72 0.72 2.20 1.20 0.45 0.62 0.62 1.90 1.00 0.40 0.52 0.52 1.60 0.80 0603 1608 0.90 1.15 1.10 4.00 2.10 0.80 0.95 1.00 3.10 1.50 0.60 0.75 0.90 2.40 1.20 0805 2012 1.00 1.35 1.55 4.40 2.60 0.90 1.15 1.45 3.50 2.00 0.75 0.95 1.35 2.80 1.70 1206 3216 1.60 1.35 1.90 5.60 2.90 1.50 1.15 1.80 4.70 2.30 1.40 0.95 1.70 4.00 2.00 1210 3225 1.60 1.35 2.80 5.65 3.80 1.50 1.15 2.70 4.70 3.20 1.40 0.95 2.60 4.00 2.90 12101 3225 1.50 1.60 2.90 5.60 3.90 1.40 1.40 2.80 4.70 3.30 1.30 1.20 2.70 4.00 3.00 1 Only for capacitance values ≥ 22 µF Density Level A: For low-density product applications. Recommended for wave solder applications and provides a wider process window for reflow solder processes. KEMET only recommends wave soldering of EIA 0603, 0805, and 1206 case sizes. Density Level B: For products with a moderate level of component density. Provides a robust solder attachment condition for reflow solder processes. Density Level C: For high component density product applications. Before adapting the minimum land pattern variations the user should perform qualification testing based on the conditions outlined in IPC Standard 7351 (IPC–7351). Image below based on Density Level B for an EIA 1210 case size. V1 Y Y X X V2 C C Grid Placement Courtyard © KEMET Electronics Corporation • KEMET Tower • One East Broward Boulevard C1005_Y5V_SMD • 9/27/2019 7 Fort Lauderdale, FL 33301 USA • 954-766-2800 • www.kemet.com

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade) Soldering Process Recommended Soldering Technique: • Solder wave or solder reflow for EIA case sizes 0603, 0805 and 1206 • All other EIA case sizes are limited to solder reflow only Recommended Reflow Soldering Profile: KEMET’s families of surface mount multilayer ceramic capacitors (SMD MLCCs) are compatible with wave (single or dual), convection, IR or vapor phase reflow techniques. Preheating of these components is recommended to avoid extreme thermal stress. KEMET’s recommended profile conditions for convection and IR reflow reflect the profile conditions of the IPC/ J-STD-020 standard for moisture sensitivity testing. These devices can safely withstand a maximum of three reflow passes at these conditions. Termination Finish T Profile Feature P Maximum Ramp-up Rate = 3°C/second tP SnPb 100% Matte Sn Maximum Ramp-down Rate = 6°C/second T Preheat/Soak e L tL r Temperature Minimum (TSmin) 100°C 150°C ratu Tsmax Temperature Maximum (T ) 150°C 200°C e Smax mp T Time (t) from T to T 60 – 120 seconds 60 – 120 seconds e smin t S Smin Smax T s 3°C/second 3°C/second Ramp-Up Rate (T to T ) L P maximum maximum 25 25°C to Peak Liquidous Temperature (T) 183°C 217°C L Time Time Above Liquidous (t) 60 – 150 seconds 60 – 150 seconds L Peak Temperature (T ) 235°C 260°C P Time Within 5°C of Maximum 20 seconds 30 seconds Peak Temperature (t ) maximum maximum P 6°C/second 6°C/second Ramp-Down Rate (T to T) P L maximum maximum Time 25°C to Peak 6 minutes 8 minutes Temperature maximum maximum Note 1: All temperatures refer to the center of the package, measured on the capacitor body surface that is facing up during assembly reflow. © KEMET Electronics Corporation • KEMET Tower • One East Broward Boulevard C1005_Y5V_SMD • 9/27/2019 8 Fort Lauderdale, FL 33301 USA • 954-766-2800 • www.kemet.com

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade) Table 4 – Performance & Reliability: Test Methods and Conditions Stress Reference Test or Inspection Method Terminal Strength JIS–C–6429 Appendix 1, Note: Force of 1.8 kg for 60 seconds. Appendix 2, Note: Standard termination system – 2.0 mm (minimum) for all except 3 mm Board Flex JIS–C–6429 for C0G. Flexible termination system – 3.0 mm (minimum). Magnification 50 X. Conditions: a) Method B, 4 hours at 155°C, dry heat at 235°C Solderability J–STD–002 b) Method B at 215°C category 3 c) Method D, category 3 at 260°C JESD22 1,000 Cycles (−55°C to +125°C). Measurement at 24 hours +/− 4 hours after test Temperature Cycling Method JA–104 conclusion. Load Humidity: 1,000 hours 85°C/85% RH and rated voltage. Add 100 K ohm resistor. MIL–STD–202 Measurement at 24 hours +/− 4 hours after test conclusion. Biased Humidity Method 103 Low Volt Humidity: 1,000 hours 85°C/85% RH and 1.5 V. Add 100 K ohm resistor. Measurement at 24 hours +/− 4 hours after test conclusion. MIL–STD–202 t = 24 hours/cycle. Steps 7a and 7b not required. Moisture Resistance Method 106 Measurement at 24 hours +/− 4 hours after test conclusion. MIL–STD–202 −55°C/+125°C. Note: Number of cycles required – 300, maximum transfer time – 20 Thermal Shock Method 107 seconds, dwell time – 15 minutes. Air – Air. MIL–STD–202 High Temperature Life 1,000 hours at 125°C (85°C for X5R, Z5U and Y5V) with 2 X rated voltage applied. Method 108/EIA–198 MIL–STD–202 Storage Life 150°C, 0 VDC for 1,000 hours. Method 108 5 g's for 20 minutes, 12 cycles each of 3 orientations. Note: Use 8" X 5" PCB 0.031" thick MIL–STD–202 Vibration 7 secure points on one long side and 2 secure points at corners of opposite sides. Parts Method 204 mounted within 2" from any secure point. Test from 10 – 2,000 Hz MIL–STD–202 Mechanical Shock Figure 1 of Method 213, Condition F. Method 213 MIL–STD–202 Resistance to Solvents Add aqueous wash chemical, OKEM Clean or equivalent. Method 215 Storage and Handling Ceramic chip capacitors should be stored in normal working environments. While the chips themselves are quite robust in other environments, solderability will be degraded by exposure to high temperatures, high humidity, corrosive atmospheres, and long term storage. In addition, packaging materials will be degraded by high temperature–reels may soften or warp and tape peel force may increase. KEMET recommends that maximum storage temperature not exceed 40ºC and maximum storage humidity not exceed 70% relative humidity. Temperature fluctuations should be minimized to avoid condensation on the parts and atmospheres should be free of chlorine and sulfur bearing compounds. For optimized solderability chip stock should be used promptly, preferably within 1.5 years of receipt. © KEMET Electronics Corporation • KEMET Tower • One East Broward Boulevard C1005_Y5V_SMD • 9/27/2019 9 Fort Lauderdale, FL 33301 USA • 954-766-2800 • www.kemet.com

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade) Construction (Typical) Detailed Cross Section Dielectric Material (BaTiO) 3 Barrier Layer Dielectric (Ni) Material (BaTiO3) Termination Finish End Termination/ (100% Matte Sn) External Electrode (Cu) Inner Electrodes (Ni) End Termination/ External Electrode (Cu) Barrier Layer (Ni) Termination Finish (100% Matte Sn) Inner Electrodes (Ni) Capacitor Marking (Optional) Laser marking option is not available on: • C0G, Ultra Stable X8R and Y5V dielectric devices • EIA 0402 case size devices • EIA 0603 case size devices with Flexible Termination option. • KPS Commercial and Automotive grade stacked devices. These capacitors are supplied unmarked only. © KEMET Electronics Corporation • KEMET Tower • One East Broward Boulevard C1005_Y5V_SMD • 9/27/2019 10 Fort Lauderdale, FL 33301 USA • 954-766-2800 • www.kemet.com

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade) Tape & Reel Packaging Information KEMET offers multilayer ceramic chip capacitors packaged in 8, 12 and 16 mm tape on 7" and 13" reels in accordance with EIA Standard 481. This packaging system is compatible with all tape-fed automatic pick and place systems. See Table 2 for details on reeling quantities for commercial chips. Bar code label Anti-static reel KEMET ® Epumnbcohsesde pda pplears tciac*rr ioerr . Chip and KPS orientation in pocket (except 1825 commercial, and 1825 and 2225 Military) Sprocket holes Embossment or punched cavity 8 mm, 12 mm Anti-static cover tape or 16 mm carrier tape 180 mm (7.00") (0.10 mm (0.004") maximum thickness) or 330 mm (13.00") *EIA 01005, 0201, 0402 and 0603 case sizes available on punched paper carrier only. Table 5 – Carrier Tape Confi guration, Embossed Plastic & Punched Paper (mm) New 2 mm Pitch Reel Options* Embossed Plastic Punched Paper Tape Packaging EIA Case Size Size 7" Reel 13" Reel 7" Reel 13" Reel Ordering Code Packaging Type/Options (W)* Pitch (P)* Pitch (P)* 1 1 (C-Spec) 01005 – 0402 8 2 2 C-3190 Automotive grade 7" reel unmarked 0603 8 2/4 2/4 C-3191 Automotive grade 13" reel unmarked C-7081 Commercial grade 7" reel unmarked 0805 8 4 4 4 4 C-7082 Commercial grade 13" reel unmarked 1206 – 1210 8 4 4 4 4 * 2 mm pitch reel only available for 0603 EIA case size. 1805 – 1808 12 4 4 2 mm pitch reel for 0805 EIA case size under development. ≥ 1812 12 8 8 Benefi ts of Changing from 4 mm to 2 mm Pitching Spacing KPS 1210 12 8 8 • Lower placement costs. KPS 1812 • Double the parts on each reel results in fewer reel 16 12 12 and 2220 changes and increased effi ciency. Array 0612 8 4 4 • Fewer reels result in lower packaging, shipping and *Refer to Figures 1 and 2 for W and P carrier tape reference locations. storage costs, reducing waste. 1 *Refer to Tables 6 and 7 for tolerance specifi cations. © KEMET Electronics Corporation • KEMET Tower • One East Broward Boulevard C1005_Y5V_SMD • 9/27/2019 11 Fort Lauderdale, FL 33301 USA • 954-766-2800 • www.kemet.com

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade) Figure 1 – Embossed (Plastic) Carrier Tape Dimensions T P 2 T2 ØD0 P0 t(o1l0e rpaintcchee osn c tuampuel a±0ti.v2e mm) E1 A 0 F K 0 W B1 B0 E2 S P 1 1 T1 Center Lines of Cavity ØD Embossment 1 For cavity size, Cover Tape see Note 1 Table 4 B is for tape feeder reference only, 1 including draft concentric about B0. User Direction of Unreeling Table 6 – Embossed (Plastic) Carrier Tape Dimensions Metric will govern Constant Dimensions — Millimeters (Inches) D Minimum R Reference S Minimum T T Tape Size D 1 E P P 1 1 0 Note 1 1 0 2 Note 2 Note 3 Maximum Maximum 1.0 25.0 8 mm (0.039) (0.984) 1.5 +0.10/−0.0 1.75 ±0.10 4.0 ±0.10 2.0 ±0.05 0.600 0.600 0.100 12 mm (0.059 +0.004/−0.0) 1.5 (0.069 ±0.004) (0.157 ±0.004) (0.079 ±0.002) 30 (0.024) (0.024) (0.004) (0.059) (1.181) 16 mm Variable Dimensions — Millimeters (Inches) B Maximum E T W Tape Size Pitch 1 2 F P 2 A,B & K Note 4 Minimum 1 Maximum Maximum 0 0 0 4.35 6.25 3.5 ±0.05 4.0 ±0.10 2.5 8.3 8 mm Single (4 mm) (0.171) (0.246) (0.138 ±0.002) (0.157 ±0.004) (0.098) (0.327) Single (4 mm) 8.2 10.25 5.5 ±0.05 8.0 ±0.10 4.6 12.3 12 mm Note 5 and double (8 mm) (0.323) (0.404) (0.217 ±0.002) (0.315 ±0.004) (0.181) (0.484) 12.1 14.25 7.5 ±0.05 12.0 ±0.10 4.6 16.3 16 mm Triple (12 mm) (0.476) (0.561) (0.138 ±0.002) (0.157 ±0.004) (0.181) (0.642) 1. The embossment hole location shall be measured from the sprocket hole controlling the location of the embossment. Dimensions of the embossment location and the hole location shall be applied independently of each other. 2. The tape with or without components shall pass around R without damage (see Figure 6.) 3. If S < 1.0 mm, there may not be enough area for a cover tape to be properly applied (see EIA Standard 481, paragraph 4.3, section b.) 1 4. B dimension is a reference dimension for tape feeder clearance only. 1 5. The cavity defi ned by A, B and K shall surround the component with suffi cient clearance that: 0 0 0 (a) the component does not protrude above the top surface of the carrier tape. (b) the component can be removed from the cavity in a vertical direction without mechanical restriction, after the top cover tape has been removed. (c) rotation of the component is limited to 20° maximum for 8 and 12 mm tapes and 10° maximum for 16 mm tapes (see Figure 3.) (d) lateral movement of the component is restricted to 0.5 mm maximum for 8 and 12 mm wide tape and to 1.0 mm maximum for 16 mm tape (see Figure 4.) (e) for KPS product, A and B are measured on a plane 0.3 mm above the bottom of the pocket. 0 0 (f) see addendum in EIA Standard 481 for standards relating to more precise taping requirements. © KEMET Electronics Corporation • KEMET Tower • One East Broward Boulevard C1005_Y5V_SMD • 9/27/2019 12 Fort Lauderdale, FL 33301 USA • 954-766-2800 • www.kemet.com

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade) Figure 2 – Punched (Paper) Carrier Tape Dimensions T ØDo Po t(o1l0e rpaintcchee osn c tuampeu l±a0ti.v2e mm) E1 A 0 F W Bottom Cover Tape B0 E2 P1 G T1 Cavity Size, T1 Top Cover Tape Center Lines of Cavity SNeoete 1, Table 7 Bottom Cover Tape User Direction of Unreeling Table 7 – Punched (Paper) Carrier Tape Dimensions Metric will govern Constant Dimensions — Millimeters (Inches) R Reference Tape Size D E P P T Maximum G Minimum 0 1 0 2 1 Note 2 0.10 1.5 +0.10 -0.0 1.75 ±0.10 4.0 ±0.10 2.0 ±0.05 0.75 25 8 mm (0.004) (0.059 +0.004 -0.0) (0.069 ±0.004) (0.157 ±0.004) (0.079 ±0.002) (0.030) (0.984) maximum Variable Dimensions — Millimeters (Inches) Tape Size Pitch E2 Minimum F P T Maximum W Maximum A B 1 0 0 2.0 ±0.05 8.3 8 mm Half (2 mm) 6.25 3.5 ±0.05 (0.079 ±0.002) 1.1 (0.327) Note 1 (0.246) (0.138 ±0.002) 4.0 ±0.10 (0.098) 8.3 8 mm Single (4 mm) (0.157 ±0.004) (0.327) 1. The cavity defi ned by A, B and T shall surround the component with suffi cient clearance that: 0 0 a) the component does not protrude beyond either surface of the carrier tape. b) the component can be removed from the cavity in a vertical direction without mechanical restriction, after the top cover tape has been removed. c) rotation of the component is limited to 20° maximum (see Figure 3.) d) lateral movement of the component is restricted to 0.5 mm maximum (see Figure 4.) e) see addendum in EIA Standard 481 for standards relating to more precise taping requirements. 2. The tape with or without components shall pass around R without damage (see Figure 6.) © KEMET Electronics Corporation • KEMET Tower • One East Broward Boulevard C1005_Y5V_SMD • 9/27/2019 13 Fort Lauderdale, FL 33301 USA • 954-766-2800 • www.kemet.com

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade) Packaging Information Performance Notes 1. Cover Tape Break Force: 1.0 kg minimum. 2. Cover Tape Peel Strength: The total peel strength of the cover tape from the carrier tape shall be: Tape Width Peel Strength 8 mm 0.1 to 1.0 newton (10 to 100 gf) 12 and 16 mm 0.1 to 1.3 newton (10 to 130 gf) The direction of the pull shall be opposite the direction of the carrier tape travel. The pull angle of the carrier tape shall be 165° to 180° from the plane of the carrier tape. During peeling, the carrier and/or cover tape shall be pulled at a velocity of 300 ±10 mm/minute. 3. Labeling: Bar code labeling (standard or custom) shall be on the side of the reel opposite the sprocket holes. Refer to EIA Standards 556 and 624. Figure 3 – Maximum Component Rotation ° T Maximum Component Rotation Maximum Component Rotation Top View Side View Typical Pocket Centerline Tape Maximum ° Width (mm) Rotation ( °) s T 8,12 20 Bo Tape Maximum 16 – 200 10 Width (mm) Rotation ( °) S 8,12 20 Typical Component Centerline 16 – 56 10 72 – 200 5 Ao Figure 4 – Maximum Lateral Movement Figure 5 – Bending Radius 8 mm & 12 mm Tape 16 mm Tape Embossed Punched Carrier Carrier 0.5 mm maximum 1.0 mm maximum 0.5 mm maximum 1.0 mm maximum Bending R R Radius © KEMET Electronics Corporation • KEMET Tower • One East Broward Boulevard C1005_Y5V_SMD • 9/27/2019 14 Fort Lauderdale, FL 33301 USA • 954-766-2800 • www.kemet.com

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade) Figure 6 – Reel Dimensions W Full Radius, (Includes Access Hole at 3 See Note Slot Location flange distortion (Ø 40 mm minimum) at outer edge) W (Measured at hub) 2 A D (See Note) N C (Arbor hole W (Measured at hub) diameter) 1 If present, tape slot in core for tape start: 2.5 mm minimum width x 10.0 mm minimum depth B (see Note) Note: Drive spokes optional; if used, dimensions B and D shall apply. Table 8 – Reel Dimensions Metric will govern Constant Dimensions — Millimeters (Inches) Tape Size A B Minimum C D Minimum 8 mm 178 ±0.20 (7.008 ±0.008) 1.5 13.0 +0.5/−0.2 20.2 12 mm or (0.059) (0.521 +0.02/−0.008) (0.795) 330 ±0.20 16 mm (13.000 ±0.008) Variable Dimensions — Millimeters (Inches) Tape Size N Minimum W W Maximum W 1 2 3 8.4 +1.5/−0.0 14.4 8 mm (0.331 +0.059/−0.0) (0.567) 50 12.4 +2.0/−0.0 18.4 Shall accommodate tape 12 mm (1.969) (0.488 +0.078/−0.0) (0.724) width without interference 16.4 +2.0/−0.0 22.4 16 mm (0.646 +0.078/−0.0) (0.882) © KEMET Electronics Corporation • KEMET Tower • One East Broward Boulevard C1005_Y5V_SMD • 9/27/2019 15 Fort Lauderdale, FL 33301 USA • 954-766-2800 • www.kemet.com

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade) Figure 7 – Tape Leader & Trailer Dimensions Embossed Carrier Punched Carrier Carrier Tape 8 mm & 12 mm only Round Sprocket Holes END START Top Cover Tape Elongated Sprocket Holes (32 mm tape and wider) 100 mm minimum leader Trailer Components 400 mm minimum 160 mm minimum Top Cover Tape Figure 8 – Maximum Camber Elongated Sprocket Holes Carrier Tape (32 mm & wider tapes) Round Sprocket Holes 1 mm maximum, either direction Straight Edge 250 mm © KEMET Electronics Corporation • KEMET Tower • One East Broward Boulevard C1005_Y5V_SMD • 9/27/2019 16 Fort Lauderdale, FL 33301 USA • 954-766-2800 • www.kemet.com

Surface Mount Multilayer Ceramic Chip Capacitors (SMD MLCCs) Y5V Dielectric, 6.3 – 50 VDC (Commercial Grade) KEMET Electronics Corporation Sales Offi ces For a complete list of our global sales offi ces, please visit www.kemet.com/sales. Disclaimer All product specifi cations, statements, information and data (collectively, the “Information”) in this datasheet are subject to change. The customer is responsible for checking and verifying the extent to which the Information contained in this publication is applicable to an order at the time the order is placed. All Information given herein is believed to be accurate and reliable, but it is presented without guarantee, warranty, or responsibility of any kind, expressed or implied. Statements of suitability for certain applications are based on KEMET Electronics Corporation’s (“KEMET”) knowledge of typical operating conditions for such applications, but are not intended to constitute – and KEMET specifi cally disclaims – any warranty concerning suitability for a specifi c customer application or use. The Information is intended for use only by customers who have the requisite experience and capability to determine the correct products for their application. Any technical advice inferred from this Information or otherwise provided by KEMET with reference to the use of KEMET’s products is given gratis, and KEMET assumes no obligation or liability for the advice given or results obtained. Although KEMET designs and manufactures its products to the most stringent quality and safety standards, given the current state of the art, isolated component failures may still occur. Accordingly, customer applications which require a high degree of reliability or safety should employ suitable designs or other safeguards (such as installation of protective circuitry or redundancies) in order to ensure that the failure of an electrical component does not result in a risk of personal injury or property damage. Although all product–related warnings, cautions and notes must be observed, the customer should not assume that all safety measures are indicted or that other measures may not be required. KEMET is a registered trademark of KEMET Electronics Corporation. © KEMET Electronics Corporation • KEMET Tower • One East Broward Boulevard C1005_Y5V_SMD • 9/27/2019 17 Fort Lauderdale, FL 33301 USA • 954-766-2800 • www.kemet.com