BUK9K52-60E Dual N-channel 60 V, 55 mΩ logic level MOSFET 24 February 2015 Product data sheet 1. General description Dual logic level N-channel MOSFET in an LFPAK56D (Dual Power-SO8) package using TrenchMOS technology. This product has been designed and qualified to AEC Q101 standard for use in high performance automotive applications. 2. Features and benefits • Dual MOSFET • Q101 Compliant • Repetitive avalanche rated • Suitable for thermally demanding environments due to 175 °C rating • True logic level gate with V rating of greater than 0.5 V at 175 °C GS(th) 3. Applications • 12 V Automotive systems • Motors, lamps and solenoid control • Transmission control • Ultra high performance power switching 4. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit V drain-source voltage T ≥ 25 °C; T ≤ 175 °C - - 60 V DS j j I drain current V = 5 V; T = 25 °C; Fig. 2 - - 16 A D GS mb P total power dissipation T = 25 °C; Fig. 1 - - 32 W tot mb Static characteristics FET1 and FET2 R drain-source on-state V = 5 V; I = 5 A; T = 25 °C; Fig. 12 - 47.3 55 mΩ DSon GS D j resistance Dynamic characteristics FET1 and FET2 Q gate-drain charge I = 5 A; V = 48 V; V = 5 V; - 2.3 - nC GD D DS GS T = 25 °C; Fig. 14; Fig. 15 j

Nexperia BUK9K52-60E Dual N-channel 60 V, 55 mΩ logic level MOSFET 5. Pinning information Table 2. Pinning information Pin Symbol Description Simplified outline Graphic symbol 1 S1 source1 8 7 6 5 D1D1 D2D2 2 G1 gate1 3 S2 source2 4 G2 gate2 5 D2 drain2 S1 G1 S2 G2 6 D2 drain2 mbk725 1 2 3 4 7 D1 drain1 LFPAK56D (SOT1205) 8 D1 drain1 6. Ordering information Table 3. Ordering information Type number Package Name Description Version BUK9K52-60E LFPAK56D Plastic single ended surface mounted package (LFPAK56D); 8 SOT1205 leads 7. Marking Table 4. Marking codes Type number Marking code BUK9K52-60E 95260E 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit V drain-source voltage T ≥ 25 °C; T ≤ 175 °C - 60 V DS j j V drain-gate voltage R = 20 kΩ; T ≥ 25 °C; T ≤ 175 °C - 60 V DGR GS j j V gate-source voltage T ≤ 175 °C; DC -10 10 V GS j Tj ≤ 175 °C; Pulsed [1][2] -15 15 V P total power dissipation T = 25 °C; Fig. 1 - 32 W tot mb I drain current T = 25 °C; V = 5 V; Fig. 2 - 16 A D mb GS T = 100 °C; V = 5 V; Fig. 2 - 11 A mb GS BUK9K52-60E All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet 24 February 2015 2 / 13

Nexperia BUK9K52-60E Dual N-channel 60 V, 55 mΩ logic level MOSFET Symbol Parameter Conditions Min Max Unit I peak drain current T = 25 °C; pulsed; t ≤ 10 µs; Fig. 3 - 64 A DM mb p T storage temperature -55 175 °C stg T junction temperature -55 175 °C j T peak soldering temperature - 260 °C sld(M) Source-drain diode FET1 and FET2 I source current T = 25 °C - 16 A S mb I peak source current pulsed; t ≤ 10 µs; T = 25 °C - 64 A SM p mb Avalanche ruggedness FET1 and FET2 EDS(AL)S non-repetitive drain-source ID = 16 A; Vsup ≤ 60 V; VGS = 5 V; [3][4] - 11.9 mJ avalanche energy T = 25 °C; Fig. 4 j(init) [1] Accumulated Pulse duration up to 50 hours delivers zero defect ppm [2] Significantly longer life times are achieved by lowering Tj and or VGS [3] Refer to application note AN10273 for further information [4] Single-pulse avalanche rating limited by maximum junction temperature of 175 °C 03aa16 003aaj559 120 20 IIDD ((AA)) Pder (%) 16 80 12 8 40 4 0 0 0 50 100 150 200 0 30 60 90 120 150 180 Tmb(°C) Tj (°C) Fig. 1. Normalized total power dissipation as a Fig. 2. Continuous drain current as a function of function of mounting base temperature mounting base temperature BUK9K52-60E All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet 24 February 2015 3 / 13

Nexperia BUK9K52-60E Dual N-channel 60 V, 55 mΩ logic level MOSFET 102 003aaj558 IIDD ((AA)) LLiimmiitt RRDDSSoonn == VVDDSS // IIDD ttpp == 1100 uuss 10 110000 uuss DDCC 1 11 mmss 1100 mmss 110000 mmss 10-1 1 10 102 VDS (V) Fig. 3. Safe operating area; continuous and peak drain current as a function of drain-source voltage 102 003aaj660 IIAALL ((AA)) 10 ((11)) 1 ((22)) 10-1 ((33)) 10-2 10-3 10-2 10-1 1 10 tAL (ms) Fig. 4. Single-pulse and repetitive avalanche rating; avalanche current as a function of avalanche time, FET1 and FET2 9. Thermal characteristics Table 6. Thermal characteristics Symbol Parameter Conditions Min Typ Max Unit R thermal resistance Fig. 5 - - 4.68 K/W th(j-mb) from junction to mounting base BUK9K52-60E All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet 24 February 2015 4 / 13

Nexperia BUK9K52-60E Dual N-channel 60 V, 55 mΩ logic level MOSFET Symbol Parameter Conditions Min Typ Max Unit R thermal resistance Minimum footprint; mounted on a - 95 - K/W th(j-a) from junction to printed circuit board ambient 003aaj557 10 Z th(j-mb) δ = 0.5 (K/W) 0.2 1 0.1 0.05 0.02 10-1 P δ = Ttp single shot tp t T 10-2 10-6 10-5 10-4 10-3 10-2 10-1 t (s) 1 p Fig. 5. Transient thermal impedance from junction to mounting base as a function of pulse duration 10. Characteristics Table 7. Characteristics Symbol Parameter Conditions Min Typ Max Unit Static characteristics FET1 and FET2 V drain-source I = 250 µA; V = 0 V; T = -55 °C 54 - - V (BR)DSS D GS j breakdown voltage I = 250 µA; V = 0 V; T = 25 °C 60 - - V D GS j V gate-source threshold I = 1 mA; V = V ; T = 25 °C; 1.4 1.7 2.1 V GS(th) D DS GS j voltage Fig. 10; Fig. 11 I = 1 mA; V = V ; T = 175 °C; 0.5 - - V D DS GS j Fig. 10; Fig. 11 I = 1 mA; V = V ; T = -55 °C; - - 2.45 V D DS GS j Fig. 10; Fig. 11 I drain leakage current V = 60 V; V = 0 V; T = 25 °C - 0.02 1 µA DSS DS GS j V = 60 V; V = 0 V; T = 175 °C - - 500 µA DS GS j I gate leakage current V = -10 V; V = 0 V; T = 25 °C - 2 100 nA GSS GS DS j V = 10 V; V = 0 V; T = 25 °C - 2 100 nA GS DS j R drain-source on-state V = 5 V; I = 5 A; T = 25 °C; Fig. 12 - 47.3 55 mΩ DSon GS D j resistance V = 5 V; I = 5 A; T = 175 °C; - 106.9 124.3 mΩ GS D j Fig. 12; Fig. 13 V = 10 V; I = 5 A; T = 25 °C; Fig. 12 - 41.4 49 mΩ GS D j BUK9K52-60E All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet 24 February 2015 5 / 13

Nexperia BUK9K52-60E Dual N-channel 60 V, 55 mΩ logic level MOSFET Symbol Parameter Conditions Min Typ Max Unit Dynamic characteristics FET1 and FET2 Q total gate charge I = 5 A; V = 48 V; V = 5 V; - 5.6 - nC G(tot) D DS GS T = 25 °C; Fig. 14; Fig. 15 Q gate-source charge j - 1.1 - nC GS Q gate-drain charge - 2.3 - nC GD C input capacitance V = 0 V; V = 25 V; f = 1 MHz; - 544 725 pF iss GS DS T = 25 °C; Fig. 16 C output capacitance j - 74 89 pF oss C reverse transfer - 40 55 pF rss capacitance t turn-on delay time V = 48 V; R = 10 Ω; V = 5 V; - 6.2 - ns d(on) DS L GS R = 5 Ω; T = 25 °C; I = 5 A t rise time G(ext) j D - 10.1 - ns r t turn-off delay time - 10.7 - ns d(off) t fall time - 9 - ns f Source-drain diode FET1 and FET2 V source-drain voltage I = 5 A; V = 0 V; T = 25 °C; Fig. 17 - 0.78 1.2 V SD S GS j t reverse recovery time I = 5 A; dI /dt = -100 A/µs; V = 0 V; - 17.7 - ns rr S S GS V = 30 V; T = 25 °C Q recovered charge DS j - 11.6 - nC r 003aaj548 003aaj549 30 80 I D gfs (A) (S) 60 20 40 10 20 Tj=175°C Tj=25°C 0 0 0 4 8 12 16 20 0 2 4 6 8 ID(A) VGS(V) Fig. 6. Forward transconductance as a function of Fig. 7. Transfer characteristics: drain current as a drain current; typical values function of gate-source voltage; typical values BUK9K52-60E All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet 24 February 2015 6 / 13

Nexperia BUK9K52-60E Dual N-channel 60 V, 55 mΩ logic level MOSFET 003aaj550 003aaj551 180 20 ID 4.5 RDSon (A) 10 3.5 (mΩ) 16 120 12 V (V)=3 GS 8 60 2.8 4 2.6 2.4 0 0 0 4 8 12 16 0 2 4 6 V (V) V (V) GS DS Fig. 8. Drain-source on-state resistance as a function Fig. 9. Output characteristics: drain current as a of gate-source voltage; typical values function of drain-source voltage; typical values 3 003aah025 10-1 003aah026 VG(VS()th) ID (A) 2.5 10-2 max 2 typ 10-3 min typ max 1.5 10-4 min 1 10-5 0.5 0 10-6 -60 0 60 120 180 0 1 2 3 Tj(°C) VGS(V) Fig. 10. Gate-source threshold voltage as a function of Fig. 11. Sub-threshold drain current as a function of junction temperature gate-source voltage BUK9K52-60E All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet 24 February 2015 7 / 13

Nexperia BUK9K52-60E Dual N-channel 60 V, 55 mΩ logic level MOSFET 003aaj556 003aaj816 150 2.4 R 2.8 3 DSon (mΩ) a 120 VGS(V)=3.5 1.6 90 4.5 0.8 60 10 30 0 2 6 10 14 18 22 -60 0 60 120 180 ID(A) Tj(°C) Fig. 12. Drain-source on-state resistance as a function Fig. 13. Normalized drain-source on-state resistance of drain current; typical values factor as a function of junction temperature 003aaj553 10 VDS VGS (V) VDS=48V ID 8 VGS(pl) 6 14V VGS(th) VGS 4 QGS1 QGS2 QGS QGD 2 QG(tot) 003aaa508 0 Fig. 14. Gate charge waveform definitions 0 5 10 15 QG(nC) Fig. 15. Gate-source voltage as a function of gate charge; typical values BUK9K52-60E All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet 24 February 2015 8 / 13

Nexperia BUK9K52-60E Dual N-channel 60 V, 55 mΩ logic level MOSFET 104 003aaj554 25 003aaj555 I S C (A) (pF) 20 103 C iss 15 102 C oss 10 C rss 10 Tj=150°C Tj=25°C 5 1 0 10-1 1 10 102 0 0.3 0.6 0.9 1.2 V (V) V (V) DS SD Fig. 16. Input, output and reverse transfer capacitances Fig. 17. Source current as a function of source-drain as a function of drain-source voltage; typical voltage; typical values values BUK9K52-60E All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet 24 February 2015 9 / 13

Nexperia BUK9K52-60E Dual N-channel 60 V, 55 mΩ logic level MOSFET 11. Package outline Plastic single ended surface mounted package LFPAK56D; 8 leads SOT1205 E A A b1 c1 L1 mounting base D1 D D2 H L 1 2 3 4 b X e w A c E1 (8x) E2 A1 C θ detail X Lp y C 0 2.5 5 mm scale Dimensions Unit A A1 b b1 c c1 D(1) D1(1) (Dre2f) E(1) E1(1) E2 e H L L1 Lp w y θ max 1.05 0.1 0.50 4.4 0.25 0.30 4.70 4.55 3.5 5.30 1.8 0.85 6.2 1.3 0.55 0.85 8° mm nom 1.27 0.25 0.1 min 1.02 0.0 0.35 4.1 0.19 0.24 4.45 4.35 3.4 4.95 1.6 0.60 5.9 0.8 0.30 0.40 0° Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. sot1205_po Outline References European Issue date version IEC JEDEC JEITA projection 14-08-21 SOT1205 14-10-28 Fig. 18. Package outline LFPAK56D (SOT1205) BUK9K52-60E All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet 24 February 2015 10 / 13

Nexperia BUK9K52-60E Dual N-channel 60 V, 55 mΩ logic level MOSFET In no event shall Nexperia be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - 12. 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Nexperia BUK9K52-60E Dual N-channel 60 V, 55 mΩ logic level MOSFET No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 12.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. BUK9K52-60E All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet 24 February 2015 12 / 13

Nexperia BUK9K52-60E Dual N-channel 60 V, 55 mΩ logic level MOSFET 13. Contents 1 General description ...............................................1 2 Features and benefits ............................................1 3 Applications ...........................................................1 4 Quick reference data .............................................1 5 Pinning information ...............................................2 6 Ordering information .............................................2 7 Marking ...................................................................2 8 Limiting values .......................................................2 9 Thermal characteristics .........................................4 10 Characteristics .......................................................5 11 Package outline ...................................................10 12 Legal information .................................................11 12.1 Data sheet status ...............................................11 12.2 Definitions ...........................................................11 12.3 Disclaimers .........................................................11 12.4 Trademarks ........................................................12 © Nexperia B.V. 2017. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 24 February 2015 BUK9K52-60E All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved Product data sheet 24 February 2015 13 / 13