BUF602 www.ti.com...................................................................................................................................................... SBOS339B–OCTOBER2005–REVISEDMAY2008 High-Speed, Closed-Loop Buffer FEATURES DESCRIPTION 1 • WideBandwidth:1000MHz TheBUF602isaclosed-loopbufferrecommendedfor 2 • HighSlewRate:8000V/m s a wide range of applications. Its wide bandwidth • FlexibleSupplyRange: (1000MHz) and high slew rate (8000V/m s) make it ideal for buffering very high-frequency signals. For ±1.4Vto±6.3VDualSupplies AC-coupled applications, an optional mid-point +2.8Vto+12.6VSingleSupply reference (V ) is provided, reducing the number of REF • OutputCurrent:60mA(continuous) external components required and the necessary • PeakOutputCurrent:350mA supplycurrenttoprovidethatreference. • LowQuiescentCurrent:5.8mA The BUF602 is available in a standard SO-8 • StandardBufferPinout surface-mount package and in an SOT23-5 where a smallerfootprintisneeded. • OptionalMid-SupplyReferenceBuffer APPLICATIONS • LowImpedanceReferenceBuffers • ClockDistributionCircuits • Video/BroadcastEquipment • CommunicationsEquipment • High-SpeedDataAcquisition • TestEquipmentandInstrumentation +V CC ≈2kW InputZ Z <2W to20MHz O VIN x1 VOUT 2kW 200W x1 VCC/2 1m F Self-Referenced, AC-Coupled, Single-Supply Buffer 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsof TexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. Alltrademarksarethepropertyoftheirrespectiveowners. 2 PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2005–2008,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

BUF602 SBOS339B–OCTOBER2005–REVISEDMAY2008...................................................................................................................................................... www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. ORDERINGINFORMATION(1) SPECIFIED PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORTMEDIA, PRODUCT PACKAGE DESIGNATOR RANGE MARKING NUMBER QUANTITY BUF602ID Rails,75 BUF602 SO-8 D –45(cid:176) Cto+85(cid:176) C BUF602 BUF602IDR TapeandReel,2500 BUF602IDBVT TapeandReel,250 BUF602 SOT23-5 DBV –45(cid:176) Cto+85(cid:176) C AWO BUF602IDBVR TapeandReel,3000 (1) Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocumentorseetheTI websiteatwww.ti.com. ABSOLUTE MAXIMUM RATINGS(1) PowerSupply ±6.5V DC InternalPowerDissipation SeeThermalInformation InputCommon-ModeVoltageRange ±V S StorageTemperatureRange:D,DBV –65(cid:176) Cto+125(cid:176) C LeadTemperature(soldering,10s) +300(cid:176) C JunctionTemperature(T) +150(cid:176) C J ESDRating: HumanBodyModel(HBM) 2000V ChargeDeviceModel(CDM) 1000V MachineModel(MM) 200V (1) Stressesabovetheseratingsmaycausepermanentdamage.Exposuretoabsolutemaximumconditionsforextendedperiodsmay degradedevicereliability.Thesearestressratingsonly,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyond thosespecifiedisnotsupported. Top View Out 1 5 +V CC 50kW 50kW x1 - V 2 CC +VCC 1 8 Out 200W 50kW VREF 3 x1 4 In NC 2 7 NC NC 3 x1 x1 200W 6 V SOT23−5 REF In 4 50kW 5 - VCC 5 4 AWO SO−8 NC=NoConnection 1 2 3 PinOrientation/PackageMarking 2 SubmitDocumentationFeedback Copyright©2005–2008,TexasInstrumentsIncorporated ProductFolderLink(s):BUF602

BUF602 www.ti.com...................................................................................................................................................... SBOS339B–OCTOBER2005–REVISEDMAY2008 ELECTRICAL CHARACTERISTICS: V = ±5V S Boldfacelimitsaretestedat+25(cid:176) C. AtR =100Ω,unlessotherwisenoted. L BUF602ID,IDBV TYP MIN/MAXOVERTEMPERATURE 0(cid:176)Cto –40(cid:176)Cto MIN/ PARAMETER CONDITIONS +25(cid:176)C +25(cid:176)C(2) 70(cid:176)C(3) +85(cid:176)C(3) UNITS MAX TESTLEVEL(1) ACPERFORMANCE (Seefigure30) Bandwidth VO=500mVPP 1000 560 550 540 MHz min B VO=1VPP 920 MHz typ C FullPowerBandwidth VO=5VPP 880 MHz typ C Bandwidthfor0.1dBFlatness VO=500mVPP 240 MHz typ C SlewRate VO=5VStep 8000 7000 6000 5000 V/m s min B RiseTimeandFallTime VO=0.2VStep 350 625 640 650 ps max B SettlingTimeto0.05% VO=1VStep 6 ns typ C HarmonicDistortion VO=2VPP,5MHz 2nd-Harmonic RL=100Ω –57 –44 –44 –42 dBc max B RL=500Ω –76 –63 –62 –60 dBc max B 3rd-Harmonic RL=100Ω –68 –63 –63 –63 dBc max B RL=500Ω –98 –85 –84 –82 dBc max B InputVoltageNoise f>100kHz 4.8 5.1 5.6 6.0 nV/√Hz max B InputCurrentNoise f>100kHz 2.1 2.6 2.7 2.8 pA/√Hz max B DifferentialGain NTSC,RL=150Ωto0V 0.15 % typ C DifferentialPhase NTSC,RL=150Ωto0V 0.04 (cid:176) typ C BUFFERDCPERFORMANCE(4) MaximumGain RL=500Ω 0.99 1 1 1 V/V max A MinimumGain RL=500Ω 0.99 0.98 0.98 0.98 V/V min A InputOffsetVoltage ±16 ±30 ±36 ±38 mV max A AverageInputOffsetVoltageDrift ±125 ±125 m V/(cid:176)C max B InputBiasCurrent ±3 ±7 ±8 ±8.5 m A max A AverageInputBiasCurrentDrift ±20 ±20 nA/(cid:176)C max B BUFFERINPUT InputImpedance 1.0||2.1 MΩ||pF typ C BUFFEROUTPUT OutputVoltageSwing RL=100Ω ±3.8 ±3.7 ±3.7 ±3.7 V min B RL=500Ω ±4.0 ±3.8 ±3.8 ±3.8 V min A OutputCurrent(Continuous) VO=0V ±60 ±50 ±49 ±48 mA min A PeakOutputCurrent VO=0V ±350 mA typ C Closed-LoopOutputImpedance f≤10MHz 1.4 Ω typ C POWERSUPPLY SpecifiedOperatingVoltage ±5 V typ C MaximumOperatingVoltage ±6.3 ±6.3 ±6.3 V max A MinimumOperatingVoltage ±1.4 ±1.4 ±1.4 V min B MaximumQuiescentCurrent VS=±5V 5.8 6.3 6.9 7.2 mA max A MinimumQuiescentCurrent VS=±5V 5.8 5.3 4.9 4.3 mA min A Power-SupplyRejectionRatio(+PSRR) 54 48 46 45 dB min A THERMALCHARACTERISTICS Specification:ID –40to+85 (cid:176)C typ C ThermalResistanceq JA D SO-8 Junction-to-Ambient 125 (cid:176)C/W typ C DBV SOT23-5 Junction-to-Ambient 150 (cid:176)C/W typ C (1) Testlevels:(A)100%testedat+25(cid:176) C.Overtemperaturelimitssetbycharacterizationandsimulation.(B)Limitssetbycharacterization andsimulation.(C)Typicalvalueonlyforinformation. (2) Junctiontemperature=ambientfor+25(cid:176) Cspecifications. (3) Junctiontemperature=ambientatlowtemperaturelimit;junctiontemperature=ambient+8(cid:176) Cathightemperaturelimitforover temperaturespecifications. (4) Currentisconsideredpositiveoutofnode. Copyright©2005–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):BUF602

BUF602 SBOS339B–OCTOBER2005–REVISEDMAY2008...................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS: V = +5V S Boldfacelimitsaretestedat+25(cid:176) C. AtR =100ΩtoV /2,unlessotherwisenoted. L S BUF602ID,IDBV TYP MIN/MAXOVERTEMPERATURE 0(cid:176)Cto –40(cid:176)Cto MIN/ PARAMETER CONDITIONS +25(cid:176)C +25(cid:176)C(2) 70(cid:176)C(3) +85(cid:176)C(3) UNITS MAX TESTLEVEL(1) ACPERFORMANCE (Seefigure31) Bandwidth VO=500mVPP 780 400 400 390 MHz min B VO=1VPP 700 MHz typ C Full-PowerBandwidth VO=3VPP 420 MHz typ C Bandwidthfor0.1dBFlatness VO=500mVPP 130 MHz typ C SlewRate VO=3VStep 2500 1800 1600 1400 V/m s min B RiseTimeandFallTime VO=0.2VStep 450 875 875 900 ps max B SettlingTimeto0.05% VO=1VStep 6 ns typ C HarmonicDistortion VO=2VPP,5MHz 2nd-Harmonic RL=100Ω –50 –45 –44 –43 dBc max B RL=500Ω –73 –62 –61 –60 dBc max B 3rd-Harmonic RL=100Ω –70 –64 –64 –63 dBc max B RL=500Ω –73 –72 –72 –71 dBc max B InputVoltageNoise f>100kHz 4.9 5.2 5.7 6.1 nV/√Hz max B InputCurrentNoise f>100kHz 2.2 2.7 2.8 2.9 pA/√Hz max B DifferentialGain NTSC,RL=100ΩtoVS/2 0.16 % typ C DifferentialPhase NTSC,RL=100ΩtoVS/2 0.05 (cid:176) typ C BUFFERDCPERFORMANCE(4) MaximumGain RL=500Ω 0.99 1 1 1 V/V max A MinimumGain RL=500Ω 0.99 0.98 0.98 0.98 V/V min A InputOffsetVoltage ±16 ±30 ±36 ±38 mV max A AverageInputOffsetVoltageDrift ±125 ±125 m V/(cid:176)C max B InputBiasCurrent ±3 ±7 ±8 ±8.5 m A max A AverageInputBiasCurrentDrift ±20 ±20 nA/(cid:176)C max B BUFFERINPUT InputImpedance 1.0||2.1 MΩ||pF typ C BUFFEROUTPUT MostPositiveOutputVoltage RL=100Ω +3.9 +3.7 +3.7 +3.7 V min B RL=500Ω +4.1 +3.8 +3.8 +3.8 V min A LeastPositiveOutputVoltage RL=100Ω +1.1 +1.3 +1.3 +1.3 V max B RL=500Ω +0.9 +1.2 +1.2 +1.2 V max A OutputCurrent(Continuous) VO=0V ±60 ±50 ±49 ±48 mA min A PeakOutputCurrent VO=0V ±160 mA typ C Closed-LoopOutputImpedance f≤10MHz 1.4 Ω typ C MID-POINTREFERENCEOUTPUT MaximumMid-SupplyReferenceVoltage 2.5 2.6 2.6 2.6 V max A MinimumMid-SupplyReferenceVoltage 2.5 2.4 2.4 2.4 V min A Mid-SupplyOutputCurrent,Sourcing 800 m A typ C Mid-SupplyOutputCurrent,Sinking 70 m A typ C Mid-SupplyOutputImpedance 200 Ω typ C (1) Testlevels:(A)100%testedat+25(cid:176) C.Overtemperaturelimitssetbycharacterizationandsimulation.(B)Limitssetbycharacterization andsimulation.(C)Typicalvalueonlyforinformation. (2) Junctiontemperature=ambientfor+25(cid:176) Cspecifications. (3) Junctiontemperature=ambientatlowtemperaturelimit;junctiontemperature=ambient+4(cid:176) Cathightemperaturelimitforover temperaturespecifications. (4) Currentisconsideredpositiveoutofnode. 4 SubmitDocumentationFeedback Copyright©2005–2008,TexasInstrumentsIncorporated ProductFolderLink(s):BUF602

BUF602 www.ti.com...................................................................................................................................................... SBOS339B–OCTOBER2005–REVISEDMAY2008 ELECTRICAL CHARACTERISTICS: V = +5V (continued) S Boldfacelimitsaretestedat+25(cid:176) C. AtR =100ΩtoV /2,unlessotherwisenoted. L S BUF602ID,IDBV TYP MIN/MAXOVERTEMPERATURE 0(cid:176)Cto –40(cid:176)Cto MIN/ PARAMETER CONDITIONS +25(cid:176)C +25(cid:176)C(2) 70(cid:176)C(3) +85(cid:176)C(3) UNITS MAX TESTLEVEL(1) POWERSUPPLY SpecifiedOperatingVoltage +5 V typ C MaximumOperatingVoltage +12.6 +12.6 +12.6 V max A MinimumOperatingVoltage +2.8 +2.8 +2.8 V min B MaximumQuiescentCurrent VS=+5V 5.3 5.8 6.3 6.5 mA max A MinimumQuiescentCurrent VS=+5V 5.3 4.8 4.5 3.9 mA min A Power-SupplyRejectionRatio(+PSRR) 52 46 44 43 dB min A THERMALCHARACTERISTICS Specification:ID –40to+85 (cid:176)C typ C ThermalResistanceq JA D SO-8 Junction-to-Ambient 125 (cid:176)C/W typ C DBV SOT23-5 Junction-to-Ambient 150 (cid:176)C/W typ C Copyright©2005–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):BUF602

BUF602 SBOS339B–OCTOBER2005–REVISEDMAY2008...................................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS: V = +3.3V S Boldfacelimitsaretestedat+25(cid:176) C. AtR =100Ω,unlessotherwisenoted. L BUF602ID,IDBV TYP MIN/MAXOVERTEMPERATURE 0(cid:176)Cto –40(cid:176)Cto MIN/ PARAMETER CONDITIONS +25(cid:176)C +25(cid:176)C(2) 70(cid:176)C(3) +85(cid:176)C(3) UNITS MAX TESTLEVEL(1) ACPERFORMANCE Bandwidth VO=500mVPP 600 320 320 310 MHz min B FullPowerBandwidth VO=1VPP 520 MHz typ C Bandwidthfor0.1dBFlatness VO=500mVPP 110 MHz typ C SlewRate VO=1.4VStep 800 650 600 600 V/m s min B RiseTimeandFallTime VO=0.2VStep 580 1100 1100 1150 ps max B SettlingTimeto0.05% VO=1VStep 6.5 ns typ C HarmonicDistortion VO=1VPP,5MHz 2nd-Harmonic RL=100Ω –59 –49 –49 –48 dBc max B RL=500Ω –76 –61 –57 –53 dBc max B 3rd-Harmonic RL=100Ω –70 –51 –48 –44 dBc max B RL=500Ω –63 –51 –48 –44 dBc max B InputVoltageNoise f>100kHz 4.9 5.2 5.7 6.1 nV/√Hz max B InputCurrentNoise f>100kHz 2.2 2.7 2.8 2.9 pA/√Hz max B BUFFERDCPERFORMANCE(4) MaximumGain RL=500Ω 0.99 1 1 1 V/V max A MinimumGain RL=500Ω 0.99 0.98 0.98 0.98 V/V min A InputOffsetVoltage ±16 ±30 ±36 ±38 mV max A AverageInputOffsetVoltageDrift ±125 ±125 m V/(cid:176)C max B InputBiasCurrent ±3 ±7 ±8 ±8.5 m A max A AverageInputBiasCurrentDrift ±20 ±20 nA/(cid:176)C max B BUFFERINPUT InputImpedance 1.0||2.1 MΩ||pF typ C BUFFEROUTPUT MostPositiveOutputVoltage RL=100Ω +2.1 +2.0 +2.0 +2.0 V min B RL=500Ω +2.3 +2.2 +2.2 +2.2 V min A LeastPositiveOutputVoltage RL=100Ω +1.2 +1.3 +1.3 +1.3 V max B RL=500Ω +1.0 +1.1 +1.1 +1.1 V max A OutputCurrent(Continuous) VO=0 ±60 ±50 ±49 ±48 mA min A PeakOutputCurrent ±100 mA typ C Closed-LoopOutputImpedance f≤10MHz 1.4 Ω typ C MID-POINTREFERENCEOUTPUT MaximumMid-SupplyReferenceVoltage 1.65 1.72 1.72 1.72 V max A MinimumMid-SupplyReferenceVoltage 1.65 1.58 1.58 1.58 V min A Mid-SupplyOutputCurrent,Sourcing 500 m A typ C Mid-SupplyOutputCurrent,Sinking 60 m A typ C Mid-SupplyOutputImpedance 200 Ω typ C POWERSUPPLY SpecifiedOperatingVoltage +3.3 V typ C MaximumOperatingVoltage +12.6 +12.6 +12.6 V max A MinimumOperatingVoltage +2.8 +2.8 +2.8 V min B MaximumQuiescentCurrent VS=+3.3V 5.0 5.5 6.0 6.3 mA max A MinimumQuiescentCurrent VS=+3.3V 5.0 4.5 4.2 3.8 mA min A Power-SupplyRejectionRatio(+PSRR) 50 44 42 41 dB min A (1) Testlevels:(A)100%testedat+25(cid:176) C.Overtemperaturelimitssetbycharacterizationandsimulation.(B)Limitssetbycharacterization andsimulation.(C)Typicalvalueonlyforinformation. (2) Junctiontemperature=ambientfor+25(cid:176) Cspecifications. (3) Junctiontemperature=ambientatlowtemperaturelimit;junctiontemperature=ambient+2(cid:176) Cathightemperaturelimitforover temperaturespecifications. (4) Currentisconsideredpositiveoutofnode. 6 SubmitDocumentationFeedback Copyright©2005–2008,TexasInstrumentsIncorporated ProductFolderLink(s):BUF602

BUF602 www.ti.com...................................................................................................................................................... SBOS339B–OCTOBER2005–REVISEDMAY2008 ELECTRICAL CHARACTERISTICS: V = +3.3V (continued) S Boldfacelimitsaretestedat+25(cid:176) C. AtR =100Ω,unlessotherwisenoted. L BUF602ID,IDBV TYP MIN/MAXOVERTEMPERATURE 0(cid:176)Cto –40(cid:176)Cto MIN/ PARAMETER CONDITIONS +25(cid:176)C +25(cid:176)C(2) 70(cid:176)C(3) +85(cid:176)C(3) UNITS MAX TESTLEVEL(1) THERMALCHARACTERISTICS Specification:ID –40to+85 (cid:176)C typ C ThermalResistanceq JA D SO-8 Junction-to-Ambient 125 (cid:176)C/W typ C DBV SOT23-5 Junction-to-Ambient 150 (cid:176)C/W typ C Copyright©2005–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):BUF602

BUF602 SBOS339B–OCTOBER2005–REVISEDMAY2008...................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS: V = ±5V S AtT =+25(cid:176) CandR =100Ω,unlessotherwisenoted. A L BUFFERBANDWIDTHvsOUTPUTVOLTAGE BUFFERBANDWIDTHvsLOADRESISTANCE 3 6 R =100W V =0.2V V =0.5V 0 L O PP OUT PP RL=1kW 3 - 3 VO=5VPP RL=500W V =0.5V B) - 6 O PP B) 0 d d ( V =1V ( n O PP n Gai - 9 Gai - 3 - 12 RL=100W VO=4VPP - 6 - 15 V =2V O PP - 18 - 9 1M 10M 100M 1G 2G 1M 10M 100M 1G 2G Frequency(Hz) Frequency(Hz) Figure1. Figure2. BUFFERGAINFLATNESS INPUTVOLTAGEANDCURRENTNOISEDENSITY 0.5 100 00..43 VROL==100.50VW PP √V/Hz)√A/Hz) np (( 0.2 yy sitsit dB) 0.1 DenDen Gain( - 0.01 NoiseNoise 10 InputVoltageNoise(4.8nV/√Hz) -- 00..23 VoltageCurrent - 0.4 putput InputCurrentNoise(2.1pA/√Hz) nn - 0.5 II 1 1M 10M 100M 1G 100 1k 10k 100k 1M 10M Frequency(Hz) Frequency(Hz) Figure3. Figure4. BUFFERSMALL-SIGNALPULSERESPONSE BUFFERLARGE-SIGNALPULSERESPONSE 150 4 3 100 2 (V) 50 (V) e e 1 g g a a olt 0 olt 0 V V utput - 50 utput - 1 O O - 2 - 100 VROLU=T1=000.W2VPP - 3 VROLU=T1=050VW PP f=40MHz f=40MHz - 150 - 4 Time(2ns/div) Time(2ns/div) Figure5. Figure6. 8 SubmitDocumentationFeedback Copyright©2005–2008,TexasInstrumentsIncorporated ProductFolderLink(s):BUF602

BUF602 www.ti.com...................................................................................................................................................... SBOS339B–OCTOBER2005–REVISEDMAY2008 TYPICAL CHARACTERISTICS: V = ±5V (continued) S AtT =+25(cid:176) CandR =100Ω,unlessotherwisenoted. A L HARMONICDISTORTIONvsFREQUENCY 5MHzHARMONICDISTORTIONvsLOADRESISTANCE - 50 - 50 R =500W - 55 VL=2V O PP c) - 60 c) - 60 B B (d - 65 (d n n stortio -- 7705 2nd−Harmonic stortio - 70 2nd−Harmonic Di 3rd−Harmonic Di c - 80 c - 80 ni ni mo - 85 mo 3rd−Harmonic Har - 90 Har - 90 f=5MHz - 95 - 100 VO=2VPP - 100 1 10 100 100 1k Frequency(MHz) LoadResistance(W ) Figure7. Figure8. HARMONICDISTORTIONvsOUTPUTVOLTAGE 5MHzHARMONICDISTORTIONvsSUPPLYVOLTAGE - 60 - 40 f=5MHz R =500W L c) - 70 RL=500W c) - 50 VO=2VPP B B d d n( 2nd−Harmonic n( - 60 ortio - 80 ortio st st - 70 Di Di 2nd−Harmonic c - 90 c oni oni - 80 Harm - 100 3rd−Harmonic Harm - 90 3rd−Harmonic - 110 - 100 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 OutputVoltage(V ) ±SupplyVoltage PP Figure9. Figure10. BUFFEROUTPUTIMPEDANCE BUFFERGROUPDELAYTIMEvsFREQUENCY 100 700 600 ) s) p We( e( 500 c m an Ti mped 10 elay 400 I D Output Group 300 200 1 100 1k 10k 100k 1M 10M 100M 1G 0 100 200 300 400 500 600 700 800 900 1000 Frequency(Hz) Frequency(MHz) Figure11. Figure12. Copyright©2005–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):BUF602

BUF602 SBOS339B–OCTOBER2005–REVISEDMAY2008...................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS: V = ±5V (continued) S AtT =+25(cid:176) CandR =100Ω,unlessotherwisenoted. A L POWER-SUPPLYREJECTIONRATIOvsFREQUENCY OUTPUTSWINGVOLTAGEvsTEMPERATURE 50 4.10 45 +PSRR 40 V) ( 4.05 35 ng wi B) 30 S +V R(d 25 age 4.00 O PSR 20 Volt 15 - PSRR utput 3.95 - VO O 10 ± 5 0 3.90 10k 100k 1M 10M 100M - 40 - 20 0 20 40 60 80 100 120 Frequency(Hz) AmbientTemperature((cid:1)C) Figure13. Figure14. DCDRIFTvsTEMPERATURE BUFFEROUTPUTVOLTAGEANDCURRENTLIMITATIONS 30 6 5 1WInternal 4 PowerLimit mV) 25 5 A) 3 Lo1a0d0LWine Voltage( 2105 BufferInputOffsetVoltage(VOS) 43 mCurrent( oltage(V) 210 50W L2o5aWdLLoinaedLine utOffset 10 BufferInputBiasCurrent(IB) 2 putBias OutputV -- 12 p n In 5 1 I - 3 1WInternal - 4 PowerLimit 0 0 - 5 - 40 - 20 0 20 40 60 80 100 120 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 5 0 5 5 0 5 0 5 0 AmbientTemperature((cid:1)C) 3 2 2 1 1 - 1 1 2 2 3 - - - - - OutputCurrent(mA) Figure15. Figure16. R vsCAPACITIVELOAD FREQUENCYRESPONSEvsCAPACITIVELOAD S 114200 0.5dB Peaking Allowed d (dB) 30 CL= 10pF a o L C = 100 ve -3 22LpF citi W) 80 pa -6 R(OUT 60 n to Ca -9 CL= 47pF ai 40 zed G -12 CL= 100pF 20 ali -15 m or 0 N -18 1 10 100 1000 1 10 100 1000 Capacitive Load (pF) Frequency (MHz) Figure17. Figure18. 10 SubmitDocumentationFeedback Copyright©2005–2008,TexasInstrumentsIncorporated ProductFolderLink(s):BUF602

BUF602 www.ti.com...................................................................................................................................................... SBOS339B–OCTOBER2005–REVISEDMAY2008 TYPICAL CHARACTERISTICS: V = +5V S AtT =+25(cid:176) CandR =100ΩtoV /2,unlessotherwisenoted. A L S BUFFERBANDWIDTHvsOUTPUTVOLTAGE HARMONICDISTORTIONvsFREQUENCY 3 - 40 0 RL=100W VO=0.5VPP - 45 RVOL==520V0PWP V =2V c) - 50 - 3 O PP (dB - 55 n Gain(dB) -- 69 VVOO==03.V2PVPPP cDistortio --- 667050 ni 2nd−Harmonic - 12 mo - 75 VO=1VPP Har - 80 - 15 3rd−Harmonic - 85 - 18 - 90 1M 10M 100M 1G 2G 1 10 100 Frequency(Hz) Frequency(MHz) Figure19. Figure20. BUFFERGAINFLATNESS 5MHzHARMONICDISTORTIONvsLOADRESISTANCE 0.5 - 60 V =0.5V 0.4 ROU=T100W PP L - 65 0.3 Bc) 2nd−Harmonic 0.2 n(d - 70 dB) 0.1 ortio Gain( - 0.01 cDist - 75 - 0.2 moni - 80 3rd−Harmonic - 0.3 Har - 85 - 0.4 f=5MHz V =2V - 0.5 - 90 O PP 1 10 100 500 100 1k Frequency(MHz) LoadResistance(W ) Figure21. Figure22. BUFFERPULSERESPONSE HARMONICDISTORTIONvsOUTPUTVOLTAGE 2.8 4.3 - 40 f=5MHz R =500W 2.7 3.7 - 50 L c) Voltage(mV) 22..65 2.5S5mVLaDelCl−ft±SSi0gc.na1alVel L2a.5rVgeD−CS±ig1n.5aVl 32..15 Voltage(V) Distortion(dB -- 6700 2nd−Harmonic Output 2.4 RightScale 1.9 Output armonic - 80 3rd−Harmonic 2.3 1.3 H - 90 R =100W L f=40MHz 2.2 0.7 - 100 Time(2ns/div) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 OutputVoltage(V ) PP Figure23. Figure24. Copyright©2005–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLink(s):BUF602

BUF602 SBOS339B–OCTOBER2005–REVISEDMAY2008...................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS: V = +3.3V S AtT =+25(cid:176) CandR =100ΩtoV /2,unlessotherwisenoted. A L S BUFFERBANDWIDTHvsOUTPUTVOLTAGE HARMONICDISTORTIONvsFREQUENCY 3 - 40 0 RL=100W VO=0.5VPP - 45 RVOL==510V0PWP - 3 dBc) - 50 ain(dB) -- 69 VOV=O0=.21VVPPPP Distortion( -- 5650 3rd−Harmonic G nic - 65 o - 12 arm - 70 H 2nd−Harmonic - 15 - 75 - 18 - 80 1M 10M 100M 1G 2G 1 10 100 Frequency(Hz) Frequency(MHz) Figure25. Figure26. BUFFERGAINFLATNESS 5MHzHARMONICDISTORTIONvsLOADRESISTANCE 0.5 - 50 V =0.5V f=5MHz O PP 0.4 RL=100W - 55 VO=1VPP 0.3 c) B 0.2 n(d - 60 Gain(dB) - 000...101 cDistortio - 65 3rd−Harmonic - 0.2 moni - 70 - 0.3 Har - 75 2nd−Harmonic - 0.4 - 0.5 - 80 1 10 100 300 100 1k Frequency(MHz) LoadResistance(W ) Figure27. Figure28. BUFFERPULSERESPONSE HARMONICDISTORTIONvsOUTPUTVOLTAGE 2.0 RL=100W 2.7 - 30 f=5MHz 1.9 f=40MHz 2.4 - 40 RL=500W c) OutputVoltage(mV) 1111....8765 1.6S5mVLaDelCl−ft±SSi0gc.na1alVel L1Ra.i6gr5ghVet−DSCScai±glen0a.7lV 2111....1852 OutputVoltage(V) armonicDistortion(dB --- 567000 3rd−Harmonic2nd−Harmonic H - 80 1.4 0.9 1.3 0.6 - 90 Time(2ns/div) 0.50 0.75 1.00 1.25 1.50 OutputVoltage(V ) PP Figure29. Figure30. 12 SubmitDocumentationFeedback Copyright©2005–2008,TexasInstrumentsIncorporated ProductFolderLink(s):BUF602

BUF602 www.ti.com...................................................................................................................................................... SBOS339B–OCTOBER2005–REVISEDMAY2008 APPLICATION INFORMATION single-supply operation of the BUF602 is to maintain WIDEBAND BUFFER OPERATION outputsignalswingswithintheusablevoltageranges. The circuit of Figure 32 establishes an input midpoint The BUF602 gives the exceptional AC performance bias using the internal midpoint reference. The input of a wideband buffer. Requiring only 5.8mA quiescent signal is then AC-coupled into this midpoint voltage current, the BUF602 will swing to within 1V of either bias. Again, on a single +5V supply, the output supply rail and deliver in excess of 60mA at room voltage can swing to within 1V of either supply pin temperature. This low output headroom requirement, while delivering more than 60mA output current. A along with supply voltage independent biasing, gives demanding 100Ω load to a midpoint bias is used in remarkable single (+5V) supply operation. The thischaracterizationcircuit. BUF602 will deliver greater than 500MHz bandwidth driving a 2V output into 100Ω on a single +5V PP supply. V CC Figure 31 shows the DC-coupled, dual power-supply circuit configuration used as the basis of the ±5V Electrical and Typical Characteristics. For test 0.1m F 50W purposes, the input impedance is set to 50Ω with a V OUT resistor to ground and the output impedance is set to ToV /2 50Ω with a series output resistor. Voltage swings 50W 50W Load CC reported in the specifications are taken directly at the 2kW input and output pins while load powers (dBm) are defined at a matched 50Ω load. In addition to the 200W usual power-supply decoupling capacitors to ground, V /2 CC a 0.01m F capacitor can be included between the two power-supply pins. This optional added capacitor will 0.1m F BUF602 typically improve the 2nd-harmonic distortion performanceby3dBto6dB. Figure32.AC-Coupled,Single-Supply, +5V SpecificationandTestCircuit + 0.1m F 4.7m F LOW-IMPEDANCE TRANSMISSION LINES 50W Source 50W The most important equations and technical basics of VIN BUF602 VOUT transmission lines support the results found for the 50W 50W Load various drive circuits presented here. An ideal transmission medium with zero ohmic impedance 0.1m F 4.7m F + would have inductance and capacitance distributed over the transmission cable. Both inductance and - 5V capacitance detract from the transmission quality of a line. Each input is connected with high-impedance to the line as in a daisy-chain or loop-through Figure31.DC-Coupled,BipolarSupply, SpecificationandTestCircuit configuration, and each adds capacitance of at least a few picofarads. The typical transmission line impedance (Z ) defines the line type. In Equation 1, Figure 32 shows the AC-coupled, single-supply circuit O the impedance is calculated by the square root of line configuration used as the basis of the +5V Electrical inductance(L )dividedbylinecapacitance(C ): and Typical Characteristics. Though not a rail-to-rail T T design, the BUF602 requires minimal input and LT Z = output voltage headroom compared to other very O C T (1) wideband buffers. It will deliver a 3V output swing PP on a single +5V supply with greater than 400MHz bandwidth. The key requirement of broadband Copyright©2005–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLink(s):BUF602

BUF602 SBOS339B–OCTOBER2005–REVISEDMAY2008...................................................................................................................................................... www.ti.com In the same manner, line inductance and capacitance The figure shown in Figure 33 makes use of the determine the delay time of a transmission line as BUF602 as a line driver. The BUF602 exhibits high showninEquation2: inputimpedanceandlowoutputimpedance,makingit idealwheneverabufferisrequired. (cid:1)(cid:2)(cid:3)LT(cid:1)CT (2) Typical values for Z are 240Ω for symmetrical traces O and 75Ω or 50Ω for coaxial cables. ZO sometimes ROUT ZO decreases to 30Ω to 40Ω in high data rate bus V BUF602 V IN OUT systems for bus lines on printed circuit boards (PCBs). In general, the more complex a bus system RLOAD is, the lower Z will be. Because it increases the O capacitance of the transmission medium, a complex system lowers the typical line impedance, resulting in higher drive requirements for the line drivers used Figure33.TypicalLineDriverCircuit here. Transmission lines are almost always terminated on SELF-BIASED, LOW-IMPEDANCE the transmitter line and always terminated on the MID-SUPPLY VOLTAGE REFERENCE receiver side. Unterminated lines generate signal reflections that degrade the pulse fidelity. The driver Using the midpoint reference in conjunction with the circuit transmits the output voltage (V ) over the BUF602 allows the creation of a low-impedance OUT line. The signal appears at the end of the line and will referencefromDCto250MHz. be reflected when not properly terminated. The The 0.1m F external capacitor is used in Figure 34 to reflected portion of V , called V , returns to the OUT REFL filterthenoise. driver. The transmitted signal is the sum of the originalsignalV andthereflectedV . OUT REFL VT(cid:2)VOUT(cid:1)VREFL (3) VS The magnitude of the reflected signal depends upon BUF602 the typical line impedance (Z ) and the value of the terminationresistorZ . O 50kW 1 200W VREFL(cid:2)VOUT(cid:1)(cid:1) (4) x1 x1 V /2 S Γ denotes the reflection factor and is described by 50kW Equation5. Z -Z G= 1 O 20W Z +Z 1 O (5) 0.1m F Γcanvaryfrom–1to+1. The conditions at the corner points of Equation 5 are Figure34.Self-Biased,LowImpedance asfollows: Mid-SupplyVoltageReference Z =Z → Γ=0 V =0 O 1 REFL Z =∞ → Γ=–1 V =–V O REFL OUT SELF-REFERENCED, AC-COUPLED Z =0 → Γ=+1 V =+V O REFL OUT WIDEBAND BUFFER An unterminated driver circuit complicates the Whenever a high-speed AC-coupled buffer is situation even more. V is reflected a second time REFL required, you should consider the BUF602. One on the driver side and wanders like a ping-pong ball feature of the BUF602 is the mid-supply reference back and forth over the line. When this happens, it is voltage, saving external components and power usually impossible to recover the output signal V OUT dissipation. A capacitor on the output of the onthereceiverside. mid-supply reference is recommended to bandlimit the noise contribution of the mid-supply reference voltage generated by the two 50kΩ internal resistors. This circuit is shown on the front page of the datasheet. 14 SubmitDocumentationFeedback Copyright©2005–2008,TexasInstrumentsIncorporated ProductFolderLink(s):BUF602

BUF602 www.ti.com...................................................................................................................................................... SBOS339B–OCTOBER2005–REVISEDMAY2008 DESIGN-IN TOOLS BUF602 output drive capabilities, noting that the graph is bounded by a Safe Operating Area of 1W maximum internal power dissipation. Superimposing DEMONSTRATION FIXTURES resistor load lines onto the plot shows that the Two printed circuit boards (PCBs) are available to BUF602 can drive ±3V into 25Ω or ±3.5V into 50Ω assist in the initial evaluation of circuit performance without exceeding the output capabilities or the 1W using the BUF602 in its two package options. Both of dissipationlimit. these are offered free of charge as unpopulated The minimum specified output voltage and current PCBs, delivered with a user's guide. The summary over-temperaturearesetbyworst-case simulations at informationforthesefixturesisshowninTable1. the cold temperature extreme. Only at cold startup will the output current and voltage decrease to the Table1.DemonstrationFixturesbyPackage numbers shown in the Electrical Characteristic tables. LITERATURE As the output transistors deliver power, the junction BOARDPART REQUEST temperatures will increase, decreasing both V PRODUCT PACKAGE NUMBER NUMBER BE (increasing the available output voltage swing) and BUF602ID SO-8 DEM-BUF-SO-1A SBAU118 increasing the current gains (increasing the available BUF602IDBV SOT23-5 DEM-BUF-SOT-1A SBAU117 output current). In steady-state operation, the available output voltage and current will always be The demonstration fixtures can be requested at the greater than that shown in the over-temperature Texas Instruments web site (www.ti.com) through the specifications, since the output stage junction BUF602productfolder. temperatures will be higher than the minimum specifiedoperatingambient. MACROMODELS AND APPLICATIONS SUPPORT For a buffer, the noise model is shown in Figure 35. Equation 6 shows the general form for the output Computer simulation of circuit performance using noisevoltageusingthetermsshowninFigure35. SPICE is often useful when analyzing the performance of analog circuits and systems. This is particularly true for video and RF amplifier circuits e n where parasitic capacitance and inductance can have e a major effect on circuit performance. A SPICE model O for the BUF602 is available through the TI web site (www.ti.com). These models do a good job of R S predicting small-signal AC and transient performance i n under a wide variety of operating conditions. They do not do as well in predicting the harmonic distortion or √4kTRS dG/dP characteristics. These models do not attempt to distinguish between package types in their small-signalACperformance. Figure35.BufferNoiseAnalysisModel OUTPUT CURRENT AND VOLTAGE (cid:5) 2 nV TcahpeabBilUitiFe6s0t2haptroavreidensotouustpuuatllyvofoltuangde ianndwidceubrraenndt eO(cid:2) e2n(cid:1)(cid:3)inRS(cid:4) (cid:1)4kTRS (cid:5)Hz (6) buffers. Under no-load conditions at +25(cid:176) C, the THERMAL ANALYSIS output voltage typically swings closer than 1.2V to either supply rail; the +25(cid:176) C swing limit is within 1.2V Due to the high output power capability of the of either rail. Into a 15Ω load (the minimum tested BUF602, heatsinking or forced airflow may be load),itistestedtodelivermorethan±60mA. required under extreme operating conditions. The specifications described above, though familiar in Maximum desired junction temperature will set the the industry, consider voltage and current limits maximum allowed internal power dissipation as separately. In many applications, it is the voltage · described below. In no case should the maximum current, or V-I product, which is more relevant to junctiontemperaturebeallowedtoexceed150(cid:176) C. circuit operation. Refer to the Buffer Output Voltage Operating junction temperature (T ) is given by T + J A and Current Limitations plot (Figure 16) in the Typical P · q . The total internal power dissipation (P ) is D JA D Characteristics. The X and Y axes of this graph show the sum of quiescent power (P ) and additional DQ the zero-voltage output current limit and the power dissipated in the output stage (P ) to deliver DL zero-current output voltage limit, respectively. The load power. Quiescent power is simply the specified four quadrants give a more detailed view of the no-load supply current times the total supply voltage Copyright©2005–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLink(s):BUF602

BUF602 SBOS339B–OCTOBER2005–REVISEDMAY2008...................................................................................................................................................... www.ti.com across the part. P will depend on the required b) Minimize the distance (< 0.25") from the DL output signal and load but would, for a grounded power-supply pins to high-frequency 0.1µF resistive load, be at a maximum when the output is decoupling capacitors. At the device pins, the ground fixed at a voltage equal to 1/2 of either supply voltage and power-plane layout should not be in close (for equal bipolar supplies). Under this condition, P proximity to the signal I/O pins. Avoid narrow power DL =V 2/(4· R ). and ground traces to minimize inductance between S L the pins and the decoupling capacitors. The Note that it is the power in the output stage and not power-supply connections should always be into the load that determines internal power decoupled with these capacitors. An optional supply dissipation. decoupling capacitor (0.1µF) across the two power As a worst-case example, compute the maximum T supplies (for bipolar operation) will improve J using a BUF602IDBV in the circuit on the front page 2nd-harmonic distortion performance. Larger (2.2µF operating at the maximum specified ambient to 6.8µF) decoupling capacitors, effective at lower temperature of +85(cid:176) C and driving a grounded 20Ω frequency, should also be used on the main supply load. pins. These may be placed somewhat farther from the device and may be shared among several P =10V· 5.8mA+52/(4· 20Ω)=370.5mW D devicesinthesameareaofthePCB. MaximumT =+85(cid:176) C+(0.37W· 150(cid:176) C/W)=141(cid:176) C. J c) Careful selection and placement of external Although this is still below the specified maximum components will preserve the high-frequency junction temperature, system reliability considerations performance of the BUF602. Resistors should be a may require lower tested junction temperatures. The very low reactance type. Surface-mount resistors highest possible internal dissipation will occur if the work best and allow a tighter overall layout. Metal film load requires current to be forced into the output for or carbon composition, axially-leaded resistors can positive output voltages or sourced from the output also provide good high-frequency performance. for negative output voltages. This puts a high current Again, keep their leads and PCB traces as short as through a large internal voltage drop in the output possible. Never use wirewound type resistors in a transistors. The output V-I plot (Figure 16) shown in high-frequencyapplication. the Typical Characteristics include a boundary for 1W d) Connections to other wideband devices on the maximum internal power dissipation under these board may be made with short, direct traces or conditions. through onboard transmission lines. For short connections, consider the trace and the input to the BOARD LAYOUT GUIDELINES next device as a lumped capacitive load. Relatively Achieving optimum performance with a wide traces (50mils to 100mils) should be used, high-frequency amplifier like the BUF602 requires preferably with ground and power planes opened up careful attention to board layout parasitics and around them. If a long trace is required, and the 6dB external component types. Recommendations that signal loss intrinsic to a doubly-terminated willoptimizeperformanceinclude: transmission line is acceptable, implement a matched impedance transmission line using microstrip or a)MinimizeparasiticcapacitancetoanyACground striplinetechniques(consultanECL design handbook for all of the signal I/O pins. Parasitic capacitance on for microstrip and stripline layout techniques). A 50Ω the output pins can cause instability: on the environment is normally not necessary on board, and noninverting input, it can react with the source in fact, a higher impedance environment will improve impedance to cause unintentional bandlimiting. To distortionasshowninthedistortionversusloadplots. reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground e) Socketing a high-speed part like the BUF602 is and power planes around those pins. Otherwise, not recommended. The additional lead length and ground and power planes should be unbroken pin-to-pin capacitance introduced by the socket can elsewhereontheboard. create an extremely troublesome parasitic network that makes it almost impossible to achieve a smooth, stable frequency response. Best results are obtained bysolderingtheBUF602ontotheboard. 16 SubmitDocumentationFeedback Copyright©2005–2008,TexasInstrumentsIncorporated ProductFolderLink(s):BUF602

BUF602 www.ti.com...................................................................................................................................................... SBOS339B–OCTOBER2005–REVISEDMAY2008 INPUT AND ESD PROTECTION These diodes provide moderate protection to input overdrive voltages above the supplies as well. The The BUF602 is built using a very high-speed protection diodes can typically support 30mA complementary bipolar process. The internal junction continuous current. Where higher currents are breakdown voltages are relatively low for these very possible (for example, in systems with ±15V supply small geometry devices. These breakdowns are parts driving into the BUF602), current-limiting series reflected in the Absolute Maximum Ratings table. All resistors should be added into the two inputs. Keep devicepinsare protected with internal ESD protection these resistor values as low as possible since high diodestothepowersuppliesasshowninFigure36. values degrade both noise performance and frequencyresponse. +V CC External Internal Pin Circuitry - V CC Figure36.InternalESDProtection Copyright©2005–2008,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLink(s):BUF602

BUF602 SBOS339B–OCTOBER2005–REVISEDMAY2008...................................................................................................................................................... www.ti.com Revision History ChangesfromRevisionA(August2006)toRevisionB ................................................................................................ Page • ChangedstoragetemperaturerangeratinginAbsoluteMaximumRatingstablefrom–40(cid:176) Cto+125(cid:176) Cto–65(cid:176) Cto +125(cid:176) C................................................................................................................................................................................... 2 ChangesfromOriginal(October2005)toRevisionA .................................................................................................... Page • AddedFigure17.................................................................................................................................................................. 10 • AddedFigure18.................................................................................................................................................................. 10 • ChangedDemonstrationFixturestitleandtext.................................................................................................................... 15 18 SubmitDocumentationFeedback Copyright©2005–2008,TexasInstrumentsIncorporated ProductFolderLink(s):BUF602

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) BUF602ID ACTIVE SOIC D 8 75 Green (RoHS NIPDAU Level-2-260C-1 YEAR -45 to 85 BUF & no Sb/Br) 602 BUF602IDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -45 to 85 AWO & no Sb/Br) BUF602IDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -45 to 85 AWO & no Sb/Br) BUF602IDBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -45 to 85 AWO & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 31-Dec-2013 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) BUF602IDBVR SOT-23 DBV 5 3000 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3 BUF602IDBVT SOT-23 DBV 5 250 178.0 9.0 3.3 3.2 1.4 4.0 8.0 Q3 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 31-Dec-2013 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) BUF602IDBVR SOT-23 DBV 5 3000 565.0 140.0 75.0 BUF602IDBVT SOT-23 DBV 5 250 565.0 140.0 75.0 PackMaterials-Page2

PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 0.1 C 1.75 1.45 1.45 B A 0.90 PIN 1 INDEX AREA 1 5 2X 0.95 3.05 2.75 1.9 1.9 2 4 3 0.5 5X 0.3 0.15 0.2 C A B (1.1) TYP 0.00 0.25 GAGE PLANE 0.22 TYP 0.08 8 TYP 0.6 0 0.3 TYP SEATING PLANE 4214839/E 09/2019 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. www.ti.com

EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK SOLDER MASK METAL UNDER METAL OPENING OPENING SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MAX 0.07 MIN ARROUND ARROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER MASK DETAILS 4214839/E 09/2019 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM 2 (1.9) 2X(0.95) 3 4 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/E 09/2019 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. www.ti.com

PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1 2X .189-.197 [4.81-5.00] .150 NOTE 3 [3.81] 4X (0 -15 ) 4 5 8X .012-.020 B .150-.157 [0.31-0.51] .069 MAX [3.81-3.98] .010 [0.25] C A B [1.75] NOTE 4 .005-.010 TYP [0.13-0.25] 4X (0 -15 ) SEE DETAIL A .010 [0.25] .004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04] 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. www.ti.com

EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM SEE DETAILS 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SOLDER MASK SOLDER MASK METAL OPENING OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND NON SOLDER MASK SOLDER MASK DEFINED DEFINED SOLDER MASK DETAILS 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com

EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 ) [1.55] SYMM 1 8 8X (.024) [0.6] SYMM (R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com

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