bq24751A www.ti.com............................................................................................................................................. SLUS756C–SEPTEMBER2007–REVISEDMARCH2009 Host-controlled Multi-Chemistry Battery Charger With System Power Selector, AC Over-Power Protection, Programmable OVP and Low I q FEATURES • EnergyStarLowI 1 q • NMOS-NMOSSynchronousBuckConverter – <10-m AOff-StateBatteryDischargeCurrent with300kHzFrequencyand>95%Efficiency – <1.5-mAOff-StateInputQuiescentCurrent • 30-nsMinimumDriverDead-timeand99.5% MaximumEffectiveDutyCycle APPLICATIONS • High-AccuracyVoltageandCurrentRegulation • NotebookandUltra-MobileComputers – ±0.5%ChargeVoltageAccuracy • PortableDataCaptureTerminals – ±3%ChargeCurrentAccuracy • PortablePrinters • MedicalDiagnosticsEquipment – ±3%AdapterCurrentAccuracy • BatteryBayChargers – ±2%InputCurrentSenseAmpAccuracy • BatteryBack-upSystems • Integration – AutomaticSystemPowerSelectionFrom DESCRIPTION AC/DCAdapterorBattery The bq24751A is a high-efficiency, synchronous – InternalLoopCompensation battery charger with integrated compensation and – InternalSoftStart system power selector logic, offering low component • Safety count for space-constrained multi-chemistry battery charging applications. Ratiometric charge current and – ProgrammableInputOvervoltage voltage programming allows very high regulation Protection(OVP) accuracies,andcanbeeitherhardwiredwithresistors – DynamicPowerManagement(DPM)with or programmed by the system power-management StatusIndicator microcontrollerusingaDACorGPIOs. – ProgrammableInrushAdapterPower The bq24751A charges two, three, or four series Li+ (ACOP)andOvercurrent(ACOC)Limits cells, supporting up to 10 A of charge current, and is – Reverse-ConductionProtectionInputFET availableina28-pin,5x5-mmthinQFNpackage. • SupportsTwo,Three,orFourLi+Cells V •• 5An–a2lo4gVInApCu/tDsCw-AitdhaRpatetiroOmpeetrriactiPnrgoRgraanmgeming PVCC BTST HIDRV PH REGN LODR PGND viaResistorsorDAC/GPIOHostControl 28 27 26 25 24 23 22 – ChargeVoltage(4-4.512V/cell) CHGEN 1 21 LEARN – ChargeCurrent(upto10A,with10-mΩ ACN 2 20 CELLS senseresistor) ACP 3 bq24751A 19 SRP – AdapterCurrentLimit(DPM) ACDRV 4 28 LD QFN 18 SRN • StatusandMonitoringOutputs ACDET 5 TOPVIEW 17 BAT – AC/DCAdapterPresentwithProgrammable VoltageThreshold ACSET 6 16 SRSET – CurrentDrawnfromInputSource ACOP 7 15 IADAPT • BatteryLearnCycleControl 8 9 10 11 12 13 14 • SupportsAnyBatteryChemistry:Li+,NiCd, T D F C J D V • NCihMaHrg,eLeEandabAlecid,etc. VPSE AGN VRE VDA VAD GOO ATDR O C B • 28-pin,5x5-mmQFNpackage A 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2007–2009,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

bq24751A SLUS756C–SEPTEMBER2007–REVISEDMARCH2009............................................................................................................................................. www.ti.com Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamagetotheMOSgates. DESCRIPTION (CONTINUED) The bq24751A controls external switches to prevent battery discharge back to the input, connect the adapter to the system, and to connect the battery to the system using 6-V gate drives for better system efficiency. For maximum system safety, inrush-power limiting provides instantaneous response to high input voltage multiplied by current. This AC Over-Power protection (ACOP) feature limits the input-switch power to the programmed level ontheACOPpin,andlatchesoffifthehigh-powerconditionpersiststopreventoverheating. The bq24751A features Dynamic Power Management (DPM) and input power limiting. These features reduce batterychargecurrentwhentheinputpower limit is reached to avoid overloading the AC adapter when supplying the load and the battery charger simultaneously. A highly-accurate current-sense amplifier enables precise measurementofinputcurrentfromtheACadaptertomonitortheoverallsystempower. ADAPTER+ SYSTEM R10 RAC C6 C7 ADAPTER- 2Ω P P 0.010Ω 10µF 10µF Q1(ACFET) Q2(ACFET) C1 SI4435 SI4435 2.2µF C2 C3 0.1µF 0.1µF ACN PVCC C8 ACP 0.1µF ACDRV R1 BATDRV Q3(BATFET) ACDET SI4435 413%2kΩ 6R62.5kΩ VREF AGND HIDRV QFD4S6680A P 1% R5 bq24751A PH N L1 RSR 10kΩ 8.2µH 0.010Ω ACGOOD ACGOOD BTST PACK+ 4R232kΩ R4 OVPSET REGN BDA1T54 C0.91µF C1011µF 1C012µF PACK- 1% 71kΩ C10 1% 1µF C13 SRSET 0.1µF DAC ACSET LODRV QFD5S6680A C14 N 0.1µF VREF PGND HOST C4 1µF SRP LEARN SRN GPIO CELLS BAT CHGEN C15 ACOP 0.1µF VDAC C16 DAC 0.47µF VADJ ADC IADAPT PowerPad C5 100pF (1)Pull-uprailcouldbeeitherVREForothersystemrail. (2)SRSET/ACSETcouldcomefromeitherDACorresistordividers. V =20V,V =3-cellLi-Ion,I =3A,I =4A IN BAT charge adapter_limit Figure1.TypicalSystemSchematic,VoltageandCurrentProgrammedbyDAC 2 SubmitDocumentationFeedback Copyright©2007–2009,TexasInstrumentsIncorporated ProductFolderLink(s):bq24751A

bq24751A www.ti.com............................................................................................................................................. SLUS756C–SEPTEMBER2007–REVISEDMARCH2009 ADAPTER+ SYSTEM R10 RAC C6 C7 ADAPTER- 2Ω P P 0.010Ω 10µF 10µF Q1(ACFET) Q2(ACFET) C1 SI4435 SI4435 2.2µF C2 C3 0.1µF 0.1µF ACN PVCC C8 ACP 0.1µF ACDRV R1 BATDRV Q3(BATFET) ACDET SI4435 413%2kΩ 6R62.5kΩ VREF AGND HIDRV QFD4S6680A P 1% R5 bq24751A PH N L1 RSR 10kΩ 8.2µH 0.010Ω ACGOOD ACGOOD BTST PACK+ 4R232kΩ R4 VREF OVPSET REGN BDA1T54 C0.91µF C1011µF 1C012µF PACK- 1% 71kΩ R7 C10 VREF 1% R11 100kΩ 1µF C13 R8 SRSET 0.1µF 100kΩ 43kΩ ACSET LODRV QFD5S6680A C14 R9 N 0.1µF 66.5kΩ VREF PGND C4 HOST 1µF SRP LEARN SRN GPIO CELLS BAT CHGEN C15 VREF ACOP 0.1µF REGN VDAC C16 0.47µF VADJ ADC IADAPT PowerPad C5 100pF (1)Pull-uprailcouldbeeitherVREForothersystemrail. (2)SRSET/ACSETcouldcomefromeitherDACorresistordividers. V =20V,V =3-cellLi-Ion,I =3A,I =4A IN BAT charge adapter_limit Figure2. TypicalSystemSchematic,VoltageandCurrentProgrammedbyResistor ORDERINGINFORMATION ORDERINGNUMBER PARTNUMBER PACKAGE QUANTITY (TapeandReel) bq24751ARHDR 3000 bq24751A 28-PIN5x5mmQFN bq24751ARHDT 250 PACKAGE THERMAL DATA PACKAGE q T =70°C DERATINGFACTOR JA A POWERRATING ABOVET =25°C A QFN–RHD(1)(2) 39°C/W 2.36W 0.028W/°C (1) Forthemostcurrentpackageandorderinginformation,seethePackageOptionAddendumattheendofthisdocument,orseetheTI Websiteatwww.ti.com. (2) ThisdataisbasedonusingtheJEDECHigh-KboardandtheexposeddiepadisconnectedtoaCupadontheboard.Thisis connectedtothegroundplanebya2x3viamatrix. Copyright©2007–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):bq24751A

bq24751A SLUS756C–SEPTEMBER2007–REVISEDMARCH2009............................................................................................................................................. www.ti.com Table1. TERMINALFUNCTIONS–28-PINQFN TERMINAL DESCRIPTION NAME NO. CHGEN 1 Chargeenableactive-lowlogicinput.LOenablescharge.HIdisablescharge. Adaptercurrentsenseresistor,negativeinput.A0.1-m FceramiccapacitorisplacedfromACNtoACPtoprovide ACN 2 differential-modefiltering.Anoptional0.1-m FceramiccapacitorisplacedfromACNpintoAGNDforcommon-mode filtering. Adaptercurrentsenseresistor,positiveinput.A0.1-m FceramiccapacitorisplacedfromACNtoACPtoprovide ACP 3 differential-modefiltering.A0.1-m FceramiccapacitorisplacedfromACPpintoAGNDforcommon-modefiltering. ACadaptertosystem-switchdriveroutput.ConnectdirectlytothegateoftheACFETP-channelpowerMOSFETand thereverseconductionblockingP-channelpowerMOSFET.ConnectbothFETsascommon-source.Connectthe ACFETdraintothesystem-loadside.ThePVCCshouldbeconnectedtothecommon-sourcenodetoensurethatthe driverlogicisalwaysactivewhenneeded.Ifneeded,anoptionalcapacitorfromgatetosourceoftheACFETisused ACDRV 4 toslowdowntheONandOFFtimes.Theinternalgatedriveisasymmetrical,allowingaquickturn-offandslower turn-oninadditiontotheinternalbreak-before-makelogicwithrespecttotheBATDRV.Theoutputgoesintolinear regulationmodewhentheinputsensedcurrentexceedstheACOCthreshold.ACDRVislatchedoffafterACOP voltageexceeds2V,toprotectthechargingsystemfromanACFET-overpowercondition. Adapterdetectedvoltagesetinput.Programtheadapterdetectthresholdbyconnectingaresistordividerfromadapter ACDET 5 inputtoACDETpintoAGNDpin.AdaptervoltageisdetectedifACDET-pinvoltageisgreaterthan2.4V.TheI ADAPT currentsenseamplifierisactivewhentheACDETpinvoltageisgreaterthan0.6V. Adaptercurrentsetinput.ThevoltageratioofACSETvoltageversusVDACvoltageprogramstheinputcurrent regulationset-pointduringDynamicPowerManagement(DPM).ProgrambyconnectingaresistordividerfromVDAC ACSET 6 toACSETtoAGND;orbyconnectingtheoutputofanexternalDACtotheACSETpinandconnecttheDACsupplyto theVDACpin. Inputpowerlimitsetinput.Programtheinputover-powertimeconstantbyplacingaceramiccapacitorfromACOPto AGND.Thecapacitorsetsthetimethattheinputcurrentlimit,ACOC,canbesustainedbeforeexceedingthe ACOP 7 power-MOSFETpowerlimit.WhentheACOPvoltageexceeds2V,thentheACDRVlatchesofftoprotectthecharge systemfromanover-powercondition,ACOP.ResetlatchbytogglingACDETorPVCC_UVLO. Setinputovervoltageprotectionthreshold.ChargeisdisabledandACDRVisturnedoffifadapterinputvoltageis higherthantheOVPSETprogrammedthreshold.Inputovervoltage,ACOV,disableschargeandACDRVwhen OVPSET 8 OVPSET>3.1V.ACOVdoesnotlatch.Programtheovervoltageprotectionthresholdbyconnectingaresistordivider fromadapterinputtoOVPSETpintoAGNDpin. Analogground.Groundconnectionforlow-currentsensitiveanaloganddigitalsignals.OnPCBlayout,connecttothe AGND 9 analoggroundplane,andonlyconnecttoPGNDthroughthePowerPadunderneaththeIC. 3.3-Vregulatedvoltageoutput.Placea1-m FceramiccapacitorfromVREFtoAGNDpinclosetotheIC.Thisvoltage VREF 10 couldbeusedforratiometricprogrammingofvoltageandcurrentregulation. Chargevoltagesetreferenceinput.ConnecttheVREForexternalDACvoltagesourcetotheVDACpin.Battery voltage,chargecurrent,andinputcurrentareprogrammedasaratiooftheVDACpinvoltageversustheVADJ, VDAC 11 SRSET,andACSETpinvoltages,respectively.PlaceresistordividersfromVDACtoVADJ,SRSET,andACSETpins toAGNDforprogramming.ADACcouldbeusedbyconnectingtheDACsupplytoVDACandconnectingtheoutput toVADJ,SRSET,orACSET. Chargevoltagesetinput.ThevoltageratioofVADJvoltageversusVDACvoltageprogramsthebatteryvoltage regulationset-point.ProgrambyconnectingaresistordividerfromVDACtoVADJ,toAGND;or,byconnectingthe VADJ 12 outputofanexternalDACtoVADJ,andconnecttheDACsupplytoVDAC.VADJconnectedtoREGNprogramsthe defaultof4.2Vpercell. Validadapteractive-lowdetectlogicopen-drainoutput.PulledlowwhenInputvoltageisaboveprogrammedACDET. ACGOOD 13 Connecta10-kΩpullupresistorfromACGOODtoVREF,ortoadifferentpullup-supplyrail. Batterytosystemswitchdriveroutput.GatedriveforthebatterytosystemloadBATPMOSpowerFETtoisolatethe systemfromthebatterytopreventcurrentflowfromthesystemtothebattery,whileallowingalowimpedancepath frombatterytosystemandwhiledischargingthebatterypacktothesystemload.Connectthispindirectlytothegate BATDRV 14 oftheinputBATP-channelpowerMOSFET.ConnectthesourceoftheFETtothesystemloadvoltagenode.Connect thedrainoftheFETtothebatterypackpositivenode.Anoptionalcapacitorisplacedfromthegatetothesourceto slowdowntheswitchingtimes.Theinternalgatedriveisasymmetricaltoallowaquickturn-offandslowerturn-on,in additiontotheinternalbreak-before-makelogicwithrespecttoACDRV. Adaptercurrentsenseamplifieroutput.IADAPTvoltageis20timesthedifferentialvoltageacrossACP-ACN.Placea IADAPT 15 100-pForlessceramicdecouplingcapacitorfromIADAPTtoAGND. Chargecurrentsetinput.ThevoltageratioofSRSETvoltageversusVDACvoltageprogramsthechargecurrent SRSET 16 regulationset-point.ProgrambyconnectingaresistordividerfromVDACtoSRSETtoAGND;orbyconnectingthe outputofanexternalDACtoSRSETpinandconnecttheDACsupplytoVDACpin. Batteryvoltageremotesense.DirectlyconnectakelvinsensetracefromthebatterypackpositiveterminaltotheBAT BAT 17 pintoaccuratelysensethebatterypackvoltage.Placea0.1-m FcapacitorfromBATtoAGNDclosetotheICtofilter high-frequencynoise. 4 SubmitDocumentationFeedback Copyright©2007–2009,TexasInstrumentsIncorporated ProductFolderLink(s):bq24751A

bq24751A www.ti.com............................................................................................................................................. SLUS756C–SEPTEMBER2007–REVISEDMARCH2009 Table1. TERMINALFUNCTIONS–28-PINQFN(continued) TERMINAL DESCRIPTION NAME NO. Chargecurrentsenseresistor,negativeinput.A0.1-m FceramiccapacitorisplacedfromSRNtoSRPtoprovide SRN 18 differential-modefiltering.Anoptional0.1-m FceramiccapacitorisplacedfromSRNpintoAGNDforcommon-mode filtering. Chargecurrentsenseresistor,positiveinput.A0.1-m FceramiccapacitorisplacedfromSRNtoSRPtoprovide SRP 19 differential-modefiltering.A0.1-m FceramiccapacitorisplacedfromSRPpintoAGNDforcommon-modefiltering. CELLS 20 2,3or4cellsselectionlogicinput.Logiclowprograms3cell.Logichighprograms4cell.Floatingprograms2cell. Learnmodelogicinputcontrolpin—logichightooverridesystemselectorwhenadapterispresent,thebatteryis dischargedtorecalibratethebattery-packgasgauge.WhenadapterispresentandLEARNishigh,batterychargingis disabled,theadapterisdisconnected(ACDRVisoff),andthebatteryisconnectedtosystem(BATDRVison).Ssytem LEARN 21 selectorautomaticallyswitchestoadapterifbatteryisdischargedbelowLOWBAT(3V).Whenadapterispresentand LEARNislow,theadapterisconnectedtosysteminnormalselectorlogic(ACDRVisonandBATDRVisoff),allowing batterycharging.Ifadapterisnotpresent,thebatteryisalwaysconnectedtothesystem(ACDRVisoffandBATDRV ison). Powerground.Groundconnectionforhigh-currentpowerconverternode.OnPCBlayout,connectdirectlytosourceof PGND 22 low-sidepowerMOSFET,togroundconnectionofinputandoutputcapacitorsofthecharger.OnlyconnecttoAGND throughthePowerPadunderneaththeIC. LODRV 23 PWMlowsidedriveroutput.Connecttothegateofthelow-sidepowerMOSFETwithashorttrace. PWMlowsidedriverpositive6-Vsupplyoutput.Connecta1-m FceramiccapacitorfromREGNtoPGND,closetothe REGN 24 IC.Useforhigh-sidedriverbootstrapvoltagebyconnectingasmall-signalSchottkydiodefromREGNtoBTST. PWMhighsidedrivernegativesupply.Connecttothephaseswitchingnode(junctionofthelow-sidepowerMOSFET PH 25 drain,high-sidepowerMOSFETsource,andoutputinductor).Connectthe0.1-m FbootstrapcapacitorfromfromPHto BTST. HIDRV 26 PWMhighsidedriveroutput.Connecttothegateofthehigh-sidepowerMOSFETwithashorttrace. PWMhighsidedriverpositivesupply.Connecta0.1-m FbootstrapceramiccapacitorfromBTSTtoPH.Connecta BTST 27 smallbootstrapSchottkydiodefromREGNtoBTST. ICpowerpositivesupply.Connecttothecommon-source(diode-OR)point:sourceofhigh-sideP-channelMOSFET PVCC 28 andsourceofreverse-blockingpowerP-channelMOSFET.Placea1-m FceramiccapacitorfromPVCCtoPGNDpin closetotheIC. ExposedpadbeneaththeIC.AGNDandPGNDstar-connectedonlyatthePowerPadplane.AlwayssolderPowerPad PowerPad totheboard,andhaveviasonthePowerPadplaneconnectingtoAGNDandPGNDplanes.Italsoservesasa thermalpadtodissipatetheheat. ABSOLUTE MAXIMUM RATINGS overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) (2) VALUE UNIT PVCC,ACP,ACN,SRP,SRN,BAT,BATDRV,ACDRV –0.3to30 PH –1to30 REGN,LODRV,VREF,VDAC,VADJ,ACSET,SRSET,ACDET,ACOP, Voltagerange –0.3to7 CHGEN,CELLS,STAT,ACGOOD,LEARN,OVPSET V VREF,IADAPT –0.3to3.6 BTST,HIDRVwithrespecttoAGNDandPGND –0.3to36 Maximumdifferencevoltage ACP–ACN,SRP–SRN,AGND–PGND –0.5to0.5 Junctiontemperaturerange –40to155 °C Storagetemperaturerange –55to155 (1) Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperating conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability. (2) AllvoltagesarewithrespecttoGNDifnotspecified.Currentsarepositiveinto,negativeoutofthespecifiedterminal.ConsultPackaging Sectionofthedatabookforthermallimitationsandconsiderationsofpackages. Copyright©2007–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):bq24751A

bq24751A SLUS756C–SEPTEMBER2007–REVISEDMARCH2009............................................................................................................................................. www.ti.com RECOMMENDED OPERATING CONDITIONS overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN NOM MAX UNIT PH –1 24 PVCC,ACP,ACN,SRP,SRN,BAT,BATDRV,ACDRV 0 24 REGN,LODRV 0 6.5 VDAC,IADAPT 0 3.6 VREF 3.3 Voltagerange V ACSET,SRSET,TS,ACDET,ACOP,CHGEN,CELLS,ACGOOD,LEARN, 0 5.5 OVPSET VADJ 0 6.5 BTST,HIDRVwithrespecttoAGNDandPGND 0 30 AGND,PGND –0.3 0.3 Maximumdifferencevoltage:ACP–ACN,SRP–SRN –0.3 0.3 V Junctiontemperaturerange –40 125 Storage –55 150 °C temperature range ELECTRICAL CHARACTERISTICS 7.0V≤V ≤24V,0°C<T <+125°C,typicalvaluesareatT =25°C,withrespecttoAGND(unlessotherwisenoted) PVCC J A PARAMETER TESTCONDITIONS MIN TYP MAX UNIT OPERATINGCONDITIONS V PVCCInputvoltageoperatingrange 5.0 24.0 V PVCC_OP CHARGEVOLTAGEREGULATION V BATvoltageregulationrange 4-4.512Vpercell,times2,3,4cells 8 18.04 V BAT_REG_RNG 8 V VDACreferencevoltagerange 2.6 3.6 V VDAC_OP V VADJvoltagerange 0 REGN V ADJ_OP 8V,8.4V,9.024V –0.5 0.5 Chargevoltageregulationaccuracy 12V,12.6V,13.536V –0.5 0.5 % 16V,16.8V,18.048V –0.5 0.5 Chargevoltageregulationsetto VADJconnectedtoREGN,8.4V,12.6V, –0.5 0.5 % defaultto4.2Vpercell 16.8V CHARGECURRENTREGULATION V Chargecurrentregulationdifferential V =V –V 0 100 mV IREG_CHG IREG_CHG SRP SRN voltagerange V SRSETvoltagerange 0 VDAC V SRSET_OP V =40–100mV –3 3 IREG_CHG V =20mV –5 5 IREG_CHG Chargecurrentregulationaccuracy % V =5mV –25 25 IREG_CHG V =1.5mV(V >4V) –33 33 IREG_CHG BAT 6 SubmitDocumentationFeedback Copyright©2007–2009,TexasInstrumentsIncorporated ProductFolderLink(s):bq24751A

bq24751A www.ti.com............................................................................................................................................. SLUS756C–SEPTEMBER2007–REVISEDMARCH2009 ELECTRICAL CHARACTERISTICS (continued) 7.0V≤V ≤24V,0°C<T <+125°C,typicalvaluesareatT =25°C,withrespecttoAGND(unlessotherwisenoted) PVCC J A PARAMETER TESTCONDITIONS MIN TYP MAX UNIT INPUTCURRENTREGULATION V Adaptercurrentregulationdifferential V =V –V 0 100 mV IREG_DPM IREG_DPM ACP ACN voltagerange V ACSETvoltagerange 0 VDAC V ACSET_OP V =40–100mV –3 3 IREG_DPM V =20mV –5 5 IREG_DPM Inputcurrentregulationaccuracy % V =5mV –25 25 IREG_DPM V =1.5mV –33 33 IREG_DPM VREFREGULATOR V VREFregulatorvoltage V >0.6V,0-30mA 3.267 3.3 3.333 V VREF_REG ACDET I VREFcurrentlimit V =0V,V >0.6V 35 75 mA VREF_LIM VREF ACDET REGNREGULATOR V REGNregulatorvoltage V >0.6V,0-75mA,PVCC>10V 5.6 5.9 6.2 V REGN_REG ACDET I REGNcurrentlimit V =0V,V >0.6V 90 135 mA REGN_LIM REGN ACDET ADAPTERCURRENTSENSEAMPLIFIER V Inputcommonmoderange VoltageonACP/ACN 0 24 ACP/N_OP V V IADAPToutputvoltagerange 0 2 IADAPT I IADAPToutputcurrent 0 1 mA IADAPT A Currentsenseamplifiervoltagegain A =V /V 20 V/V IADAPT IADAPT IADAPT IREG_DPM V =40–100mV –2 2 IREG_DPM V =20mV –3 3 IREG_DPM Adaptercurrentsenseaccuracy % V =5mV –25 25 IREG_DPM V =1.5mV –33 33 IREG_DPM I Outputcurrentlimit V =0V 1 mA IADAPT_LIM IADAPT C Maximumoutputloadcapacitance Forstabilitywith0mAto1mAload 100 pF IADAPT_MAX ACDETCOMPARATOR V ACDETadapter-detectrising Minvoltagetoenablecharging,V 2.376 2.40 2.424 V ACDET_CHG ACDET threshold rising V ACDETfallinghysteresis V falling 40 mV ACDET_CHG_HYS ACDET ACDETrisingdeglitch VACDETrising 518 700 908 ms ACDETfallingdeglitch VACDETfalling 7 9 11 ms V ACDETenable-biasrisingthreshold Minvoltagetoenableallbias,V rising 0.56 0.62 0.68 V ACDET_BIAS ACDET V Adapterpresentfallinghysteresis V falling 20 mV ACDET_BIAS_HYS ACDET ACDETrisingdeglitch V rising 10 m s ACDET ACDETfallingdeglitch V falling 10 m s ACDET PVCC/BATCOMPARATOR(REVERSEDISCHARGINGPROTECTION) V DifferentialVoltagefromPVCCto –20 24 V PVCC-BAT_OP BAT V PVCCtoBATfallingthreshold V –V toturnoffACFET 140 185 240 mV PVCC-BAT_FALL PVCC BAT V PVCCtoBAThysteresis 50 mV PVCC-BAT__HYS PVCCtoBATRisingDeglitch V –V >V 7 9 11 ms PVCC BAT PVCC-BAT_RISE PVCCtoBATFallingDeglitch V –V <V 6 m s PVCC BAT PVCC-BAT_FALL INPUTUNDERVOLTAGELOCK-OUTCOMPARATOR(UVLO) V ACUnder-voltagerisingthreshold MeasuredonPVCC 3.5 4 4.5 V UVLO V ACUnder-voltagehysteresis,falling 260 mV UVLO_HYS Copyright©2007–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):bq24751A

bq24751A SLUS756C–SEPTEMBER2007–REVISEDMARCH2009............................................................................................................................................. www.ti.com ELECTRICAL CHARACTERISTICS (continued) 7.0V≤V ≤24V,0°C<T <+125°C,typicalvaluesareatT =25°C,withrespecttoAGND(unlessotherwisenoted) PVCC J A PARAMETER TESTCONDITIONS MIN TYP MAX UNIT ACN/BATCOMPARATOR V ACNtoBATfallingthreshold V –V toturnonBATDRV 175 285 340 mV ACN-BAT_FALL ACN BAT V ACNtoBAThysteresis 50 mV ACN-BAT_HYS ACNtoBATrisingdeglitch V –V >V 20 m s ACN BAT ACN-BAT_RISE ACNtoBATfallingdeglitch V –V <V 6 m s ACN BAT ACN-BAT_FALL BATOVERVOLTAGECOMPARATOR V Overvoltagerisingthreshold AspercentageofV 104 OV_RISE BAT_REG % V Overvoltagefallingthreshold AspercentageofV 102 OV_FALL BAT_REG BATSHORT(UNDERVOLTAGE)COMPARATOR V BATshortfallingthreshold 2.755 2.9 3.045 V/cell BAT_SHORT_FALL V BATshorthysteresis 250 mV/cell BAT_SHORT_HYS BATshortrisingdeglitch V >V +V BAT BAT_SHORT BAT_SHORT_HYS 1.5 Detectiondelay s BATshortfallingdeglitch V <V 1.5 BAT BAT_SHORT CHARGEOVERCURRENTCOMPARATOR V Chargeover-currentfallingthreshold AspercentageofI 145 % OC REG_CHG MinimumCurrentLimit(SRP-SRN) 50 mV CHARGEUNDERCURRENTCOMPARATOR(SYNCHRONOUSTONON-SYNCHRONOUSTRANSITION) V Chargeundercurrentfallingthreshold Changingfromsynchronousto 9.75 13 16.25 mV ISYNSET_FALL non-sysnchronous V Chargeundercurrentrising 8 mV ISYNSET_HYS hysteresis Chargeundercurrent,falling-current 20 deglitch V <V m s IREG_DPM ISYNSET Chargeundercurrent,rising-current 640 deglitch INPUTOVER-POWERCOMPARATOR(ACOP) V ACOCGainforinitialACOCcurrent Begins700msafterACDET % ACOC limitlimit(Percentageofprogrammed Inputcurrentlimitedtothisthresholdfor 150 V IREG_DPM VIREG_DPM) faultprotection V MaximumACOCinputcurrentlimit Internallylimitedceiling ACOC_CEILING 100 mV (V –V )max V =(V –V )max ACP ACN ACOC_MAX ACP ACN ACOPLatchBlankoutTimewith Begins700msafterACDET ACOCactive (doesnotallowACOPlatch-off,andno 2 ms (begins700msafterACDET) ACOPsourcecurrent) V ACOPpinlatch-offthresholdvoltage ACOP (SeeACOPinTerminalFunctions 1.95 2 2.05 V table) K GainforACOPSourceCurrentwhen CurrentsourceonwheninACOClimit. ACOP inACOC FunctionofvoltageacrosspowerFET 18 m A/V I =K ×(V -V ) ACOP_SOURCE ACOP PVCC ACP I ACOPSinkCurrentwhennotin CurrentsinkonwhennotinACOC ACOP_SINK ACOC 5 m A ACOPLatchisresetbygoingbelow ACDETorUVLO V ACNShortprotectionthreshold ACN<2.4V,ACDET>2.4V 2.4 V ACN-SHORT latching 8 SubmitDocumentationFeedback Copyright©2007–2009,TexasInstrumentsIncorporated ProductFolderLink(s):bq24751A

bq24751A www.ti.com............................................................................................................................................. SLUS756C–SEPTEMBER2007–REVISEDMARCH2009 ELECTRICAL CHARACTERISTICS (continued) 7.0V≤V ≤24V,0°C<T <+125°C,typicalvaluesareatT =25°C,withrespecttoAGND(unlessotherwisenoted) PVCC J A PARAMETER TESTCONDITIONS MIN TYP MAX UNIT INPUTOVERVOLTAGECOMPARATOR(ACOV) V ACOvervoltagerisingthresholdon ACOV OVPSET MeasuredonOVPSET 3.007 3.1 3.193 V (SeeOVPSETinTable1) V ACOver-voltagerisingdeglitch 1.3 ACOV_HYS ms ACOver-voltagefallingdeglitch 1.3 THERMALSHUTDOWNCOMPARATOR T Thermalshutdownrisingtemperature TemperatureIncreasing 155 °C SHUT T Thermalshutdownhysteresis,falling 20 °C SHUT_HYS BATTERYSWITCH(BATDRV)DRIVER R BATFETTurn-offresistance V >5V 160 Ω DS_BAT_OFF ACN R BATFETTurn-onresistance V >5V 3 kΩ DS_BAT_ON ACN V =V –V when V BATFETdrivevoltage BATDRV_REG ACN BATDRV 6.5 V BATDRV_REG V >5VandBATFETison ACN BATFETPower-updelay DelaytoturnoffBATFETafteradapteris 518 700 908 ms detected(afterACDET>2.4) ACSWITCH(ACDRV)DRIVER R ACFETturn-offresistance V >5V 80 Ω DS_AC_OFF PVCC R ACFETturn-onresistance V >5V 2.5 kΩ DS_AC_ON PVCC V ACFETdrivevoltage V =V –V when ACDRV_REG ACDRV_REG PVCC ACDRV 6.5 V V >5VandACFETison PVCC ACFETPower-upDelay DelaytoturnonACFETafteradapteris 518 700 908 ms detected(afterACDET>2.4) AC/BATMOSFETDRIVERSTIMING Driverdeadtime DeadtimewhenswitchingbetweenACDRV 10 m s andBATDRV PWMHIGHSIDEDRIVER(HIDRV) R Highsidedriverturn-onresistance V –V =5.5V,testedat100mA 3 6 Ω DS_HI_ON BTST PH R Highsidedriverturn-offresistance V –V =5.5V,testedat100mA 0.7 1.4 Ω DS_HI_OFF BTST PH V Bootstraprefreshcomparator V –V whenlowsiderefreshpulseis BTST_REFRESH BTST PH 4 V thresholdvoltage requested PWMLOWSIDEDRIVER(LODRV) R Lowsidedriverturn-onresistance REGN=6V,testedat100mA 3 6 Ω DS_LO_ON R Lowsidedriverturn-offresistance REGN=6V,testedat100mA 0.6 1.2 Ω DS_LO_OFF PWMDRIVERSTIMING DriverDeadTime—Deadtime whenswitchingbetweenLODRVand 30 ns HIDRV.NoloadatLODRVand HIDRV PWMOSCILLATOR F PWMswitchingfrequency 240 360 kHz SW V PWMrampheight AspercentageofPVCC 6.6 %PVCC RAMP_HEIGHT Copyright©2007–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):bq24751A

bq24751A SLUS756C–SEPTEMBER2007–REVISEDMARCH2009............................................................................................................................................. www.ti.com ELECTRICAL CHARACTERISTICS (continued) 7.0V≤V ≤24V,0°C<T <+125°C,typicalvaluesareatT =25°C,withrespecttoAGND(unlessotherwisenoted) PVCC J A PARAMETER TESTCONDITIONS MIN TYP MAX UNIT QUIESCENTCURRENT I Totaloff-statequiescentcurrentinto V =16.8V,V <0.6V, 7 10 OFF_STATE BAT ACDET pinsSRP,SRN,BAT,BTST,PH, V >5V,T =0to85°C m A PVCC J PVCC,ACP,ACN IBATQ_CD Totalquiescentcurrentintopins: Adapterpresent,VACDET>2.4V,charge 100 200 m A SRP,SRN,BAT,BTST,PH disabled I Adapterquiescentcurrent V =20V,chargedisabled 1 1.5 mA AC PVCC INTERNALSOFTSTART(8stepstoregulationcurrent) Softstartsteps 8 step Softstartsteptime 1.7 ms CHARGERSECTIONPOWER-UPSEQUENCING Charge-enabledelayafterpower-up Delayfromwhenadapterisdetectedto 518 700 908 ms whenthechargerisallowedtoturnon LOGICINPUTPINCHARACTERISTICS(CHGEN,LEARN) V Inputlowthresholdvoltage 0.8 IN_LO V V Inputhighthresholdvoltage 2.1 IN_HI I Inputbiascurrent V =0toV 1 m A BIAS CHGEN REGN t Chargeenabledeglitchtime,CHGEN ACDET>2.4V,CHGENrising CHGEN_DEGLITCH 2 ms falling=enablingcharge LOGICINPUTPINCHARACTERISTICS(CELLS) V Inputlowthresholdvoltage,3cells CELLSvoltagefallingedge 0.5 IN_LO V Inputmidthresholdvoltage,2cells CELLSvoltagerisingforMIN, 0.8 1.8 IN_MID V CELLSvoltagefallingforMAX V Inputhighthresholdvoltage,4cells CELLSvoltagerising 2.5 IN_HI IBIAS_FLOAT Inputbiasfloatcurrentfor2-cell VCHGEN=0toVREGN –1 1 m A selection OPEN-DRAINLOGICOUTPUTPINCHARACTERISTICS(ACGOOD) V Outputlowsaturationvoltage SinkCurrent=5mA 0.5 V OUT_LO 518 700 908 ms Delay,ACGOODrising 10 ms Delay,ACGOODfalling ms 10 SubmitDocumentationFeedback Copyright©2007–2009,TexasInstrumentsIncorporated ProductFolderLink(s):bq24751A

bq24751A www.ti.com............................................................................................................................................. SLUS756C–SEPTEMBER2007–REVISEDMARCH2009 TYPICAL CHARATERISTICS TableofGraphs(1) Y X FIgure VREFLoadandLineRegulation vsLoadCurrent Figure3 REGNLoadandLineRegulation vsLoadCurrent Figure4 BATVoltage vsVADJ/VDACRatio Figure5 ChargeCurrent vsSRSET/VDACRatio Figure6 InputCurrent vsACSET/VDACRatio Figure7 BATVoltageRegulationAccuracy vsChargeCurrent Figure8 BATVoltageRegulationAccuracy Figure9 ChargeCurrentRegulationAccuracy Figure10 InputCurrentRegulation(DPM)Accuracy Figure11 V InputCurrentSenseAmplifierAccuracy Figure12 IADAPT InputRegulationCurrent(DPM),andChargeCurrent vsSystemCurrent Figure13 TransientSystemLoad(DPM)Response Figure14 ChargeCurrentRegulation vsBATVoltage Figure15 Efficiency vsBatteryChargeCurrent Figure16 BatteryRemoval(fromConstantCurrentMode) Figure17 ACDRVandBATDRVStartup Figure18 REFandREGNStartup Figure19 SystemSelectoronAdapterInsertionwith390-m FSYS-to-PGNDSystemCapacitor Figure20 SystemSelectoronAdapterRemovalwith390-m FSYS-to-PGNDSystemCapacitor Figure21 SystemSelectorLEARNTurn-Onwith390-m FSYS-to-PGNDSystemCapacitor Figure22 SystemSelectorLEARNTurn-Offwith390-m FSYS-to-PGNDSystemCapacitor Figure23 SystemSelectoronAdapterInsertion Figure24 SelectorGateDriveVoltages,700msdelayafterACDET Figure25 Chargeron/AdapterRemoval Figure26 ChargeEnable/DisableandCurrentSoft-Start Figure27 NonsynchronoustoSynchronousTransition Figure28 SynchronoustoNonsynchronousTransition Figure29 Near100%DutyCycleBootstrapRechargePulse Figure30 BatteryShortedChargerResponse,OverCurrentProtection(OCP)andChargeCurrentRegulation Figure31 ContinuousConductionMode(CCM)SwitchingWaveforms Figure32 DiscontinuousConductionMode(DCM)SwitchingWaveforms Figure33 (1) TestresultsbasedonFigure2applicationschematic.V =20V,V =3-cellLiIon,I =3A,I =4A, IN BAT CHG ADAPTER_LIMIT T =25°C,unlessotherwisespecified. A Copyright©2007–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLink(s):bq24751A

bq24751A SLUS756C–SEPTEMBER2007–REVISEDMARCH2009............................................................................................................................................. www.ti.com VREFLOADANDLINEREGULATION REGNLOADANDLINEREGULATION vs vs LoadCurrent LOADCURRENT 0.50 0 0.40 -0.50 on Error - % 00..2300 PVCC = 10 V n Error - % -1.5-10 gulati 0.10 ulatio PVCC = 10 V Re 0 Reg -2 PVCC = 20 V -0.10 -2.50 PVCC = 20 V -0.20 -3 0 10 20 30 40 50 0 10 20 30 40 50 60 70 80 VREF - Load Current - mA REGN - Load Current - mA Figure3. Figure4. BATVOLTAGE CHARGECURRENT vs vs VADJ/VDACRATIO SRSET/VDACRATIO 18.2 10 18 VADJ = 0 -VDAC, 9 SRSETVaried, 4-Cell, 4-Cell, 17.8 No Load A 8 Vbat = 16 V ge Regulation - V 111167771....86247 urrent Regulation - 4567 a C Volt 1166..46 harge 23 C 16.2 1 16 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 VADJ/VDAC Ratio SRSET/VDAC Ratio Figure5. Figure6. INPUTCURRENT BATVOLTAGEREGULATIONACCURACY vs vs ACSET/VDACRATIO CHARGECURRENT 10 0.2 ACSETVaried, 9 4-Cell, Vreg= 16.8 V Vbat = 16 V A 8 ation - 7 or - % 0.1 gul 6 Err ut Current Re 354 Regulation -0.01 np 2 I 1 -0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 2000 4000 6000 8000 Charge Current - mA ACSET/VDAC Ratio Figure7. Figure8. 12 SubmitDocumentationFeedback Copyright©2007–2009,TexasInstrumentsIncorporated ProductFolderLink(s):bq24751A

bq24751A www.ti.com............................................................................................................................................. SLUS756C–SEPTEMBER2007–REVISEDMARCH2009 BATVOLTAGEREGULATIONACCURACY CHARGECURRENTREGULATIONACCURACY 0.10 2 4-Cell, VBAT= 16 V SRSETVaried 0.08 VADJ = 0 -VDAC 1 0 0.06 -1 Regulation Error - %--0000....000042240 4-Cell, no load Regulation Error - % ------765432 -0.06 -8 -0.08 -9 -0.10 -10 16.5 17 17.5 18 18.5 19 0 2 4 6 8 V(BAT)- Setpoint - V I(CHRG)-Setpoint -A Figure9. Figure10. INPUTCURRENTREGULATION(DPM)ACCURACY V INPUTCURRENTSENSEAMPLIFIERACCURACY IADAPT 10 5 9 ACSETVaried 8 0 7 ation Error - % 3456 4-Cell, VBAT= 16 V ercent Error-1-05 VI= 20 V, CHG = DIS VI= 20 V, CHG = EN gul 2 P-15 e R 1 0 -20 -1 IadaptAmplifier Gain -2 -25 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 8 9 10 Input Current Regulation Setpoint -A I(ACPWR)-A Figure11. Figure12. INPUTREGULATIONCURRENT(DPM),ANDCHARGE CURRENT vs SYSTEMCURRENT TRANSIENTSYSTEMLOAD(DPM)RESPONSE 5 VI= 20 V, 4-Cell, 4 Vbat= 16 V Input Current A n - 3 nd Ii System Current a hrg 2 Charge Current c I 1 0 0 1 2 3 4 System Current -A Figure13. Figure14. Copyright©2007–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLink(s):bq24751A

bq24751A SLUS756C–SEPTEMBER2007–REVISEDMARCH2009............................................................................................................................................. www.ti.com CHARGECURRENTREGULATION EFFICIENCY vs vs BATVOLTAGE BATTERYCHARGECURRENT 5 100 V(BAT)= 16.8 V Vin= 20 V, Ichrg_set = 4A, 4 TA= 20°C urrent -A 3 4 Cell cy - % 90 Vreg= 12.6 V Vreg= 8.4 V C n Charge 2 Efficie 80 1 0 0 2 4 6 8 10 12 14 16 18 70 0 2000 4000 6000 8000 Battery Voltage - V Battery Charge Current - mA Figure15. Figure16. BATTERYREMOVAL ACDRVANDBATDRVSTARTUP v Ch12V/di VACDET v Ch2V/di VBATDRV 0 2 v Ch3V/di VACDRV 5 Ch4V/div VACGOOD 5 t−Time = 100 ms/div Figure17. Figure18. SYSTEMSELECTORONADAPTERINSERTIONWITH REFANDREGNSTARTUP 390m FSYS-TO-PGNDSYSTEMCAPACITOR v Ch10V/di VBAT 2 v Ch2V/di VSYS 0 2 v Ch3V/di VACDRV 0 1 v Ch4V/di VBATDRV 0 1 t−Time = 400ms/div Figure19. Figure20. 14 SubmitDocumentationFeedback Copyright©2007–2009,TexasInstrumentsIncorporated ProductFolderLink(s):bq24751A

bq24751A www.ti.com............................................................................................................................................. SLUS756C–SEPTEMBER2007–REVISEDMARCH2009 SYSTEMSELECTORONADAPTERREMOVALWITH SYSTEMSELECTORLEARNTURN-ONWITH 390m FSYS-TO-PGNDSYSTEMCAPACITOR 390m FSYS-TO-PGNDSYSTEMCAPACITOR v Ch10V/di VBAT 2 v Ch20V/di VSYS 2 v Ch30V/di VACDRV 1 v Ch4V/di VBATDRV 0 1 t−Time = 2 ms/div Figure21. Figure22. SYSTEMSELECTORLEARNTURN-OFFWITH 390m FSYS-TO-PGNDSYSTEMCAPACITOR SYSTEMSELECTORONADAPTERINSERTION v Ch10V/di VACPWR Ch17.2V 2 v 2di Ch0V/ VACDRV 2 v Ch3V/di VACGOOD 5 v IL Ch4A/di 5 t−Time = 400 ms/div Figure23. Figure24. SELECTORGATEDRIVEVOLTAGES,700MSDELAY AFTERACDET CHARGERON/ADAPTERREMOVAL Ch1V/div VSYS Ch1V/div VIN 5 5 Ch25V/div VACDRV Ch45V/div VBAT v v Ch40mV/di VACOP Ch32A/di IL 0 5 IIN v Ch3A/di 5 t−Time = 1 ms/div t−Time = 200ms/div Figure25. Figure26. Copyright©2007–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLink(s):bq24751A

bq24751A SLUS756C–SEPTEMBER2007–REVISEDMARCH2009............................................................................................................................................. www.ti.com CHARGEENABLE/DISABLEANDCURRENTSOFT-START NONSYNCHRONOUSTOSYNCHRONOUSTRANSITION 1div 1V 1div VHIDRV Ch0V/ VCHGEN Ch1.8 Ch0V/ 1 1 Ch41V/div VBAT Ch210V/div VPH v Ch20V/di VPH Ch4V/div 2 5 VLDDRV v Ch3A/div IBAT Ch32A/di IL 2 t−Time = 4 ms/div t−Time = 4ms/div Figure27. Figure28. SYNCHRONOUSTONONSYNCHRONOUSTRANSITION NEAR100%DUTYCYCLEBOOTSTRAPRECHARGEPULSE v VPH Ch1V/di VPH 0 v 2 2di Ch10V/ Ch2V/div VHIDRV 0 VLODRV 2 v Ch4V/di 5 Ch3V/div VLODRV 5 Ch32A/div IL Ch4A/div IL 2 t−Time = 2ms/div t−Time = 4 ms/div Figure29. Figure30. BATTERYSHORTEDCHARGERRESPONSE, OVERCURRENTPROTECTION(OCP)ANDCHARGE CONTINUOUSCONDUCTIONMODE(CCM)SWITCHING CURRENTREGULATION WAVEFORMS v Ch40V/div VBAT Ch120V/di VPH 1 v Ch2V/di VHIDRV 0 2 Ch32A/div Ch35V/div VLODRV IL v Ch4A/di IL 5 t−Time = 400ms/div t−Time = 1ms/div Figure31. Figure32. 16 SubmitDocumentationFeedback Copyright©2007–2009,TexasInstrumentsIncorporated ProductFolderLink(s):bq24751A

bq24751A www.ti.com............................................................................................................................................. SLUS756C–SEPTEMBER2007–REVISEDMARCH2009 DISCONTINUOUSCONDUCTIONMODE(DCM)SWITCHING WAVEFORMS v Ch1V/di VPH 0 2 v Ch2V/di VHIDRV 0 2 v Ch35V/di VLODRV v Ch4A/di IL 2 t−Time = 1ms/div Figure33. Copyright©2007–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLink(s):bq24751A

bq24751A SLUS756C–SEPTEMBER2007–REVISEDMARCH2009............................................................................................................................................. www.ti.com FUNCTIONALBLOCKDIAGRAM 700ms 0.6 V – ENA_BIAS + 2.4 V – ADAPTERDETECTED DelayRising ACGOOD ACDET + VREF ENA_SRC Isrc=K*V(PVCC-ACP) PVCC + PVCC-6V K=18µA/V PVCC-6V PVCC ACOP BAT _+ – LDO + ACOPDET 185 mV PVCC-BAT ENA_SNK 5µA2 V +– – S Q ACOP_LATCH ENA_BIAS PVCC ACDET R Q SYSTEMPOWER ACDRV PVCC_UVLO SELLOEGCITCOR CHGEN PVCC-6V ACN ENA_BIAS VREF 3.3VLDO EAI EAO BATDRV PVCC ACN-6V ACP FBO ACFET_ON LEARN + V(ACP-ACN) 20x – IIN_ER – IIN_REG + COMP ERROR ACN AMPLIFIER CHGEN BTST + V(ACN-BAT) - _+ – + BAT 285 mV – BAT_ER 1 V BAT_OVP SLHEIFVTEELR HIDRV CHG_OCP VBAT_REG + 20µA ACOV ACOP SRP PH 3.5 mA V(ACN-BAT) CONDVCE-DRCTER + V(SRP-SRN) BAT_SHORT PWMLOGIC 20x – ICH_ER – IBAT_REG + UVLO SRN 20µA PVCC 6VLDO REGN 3.5 mA SYNCH ENA_BIAS CHGEN CHRG_ON BTST – RCEBFTRSTESH LODRV + V(SRP-SRN) + SYNCH 4 V _+ ACSET 13 mV +– – PH PGND ICTj + TSHUT 155°C – ACP + V(IADAPT) SRSET 20x IADAPT VBATSET VBAT_REG BAT + BAT_OVP ACN – IBATSET 104%XVBAT_REG – IINSET IBAT_REG RATIO VADJ PROGRAM IIN_REG V(SRP-SRN) + CHG_OCP 145%XIBAT_REG – VDAC + ACOV OVPSET 3.1 V +– – BAT –+ BAT_SHORT 2.9 V/cell +– CELLS PVCC – UVLO + AGND 4 V +– bq24751A 18 SubmitDocumentationFeedback Copyright©2007–2009,TexasInstrumentsIncorporated ProductFolderLink(s):bq24751A

bq24751A www.ti.com............................................................................................................................................. SLUS756C–SEPTEMBER2007–REVISEDMARCH2009 DETAILED DESCRIPTION Battery Voltage Regulation The bq24751A uses a high-accuracy voltage regulator for charging voltage. Internal default battery voltage setting V = 4.2 V × cell count. The regulation voltage is ratiometric with respect to VADC. The ratio of VADJ BATT and VDAC provides extra 12.5% adjust range on V regulation voltage. By limiting the adjust range to 12.5% BATT of the regulation voltage, the external resistor mismatch error is reduced from ±1% to ±0.1%. Therefore, an overall voltage accuracy as good as 0.5% is maintained, while using 1% mismatched resistors. Ratiometric conversion also allows compatibility with D/As or microcontrollers (m C). The battery voltage is programmed throughVADJandVDACusingEquation1. é æ V öù VBATT =cellcount´êêë4 V+çè0.512´VVVDAADCJ ÷øúúû (1) The input voltage range of VDAC is between 2.6 V and 3.6 V. VADJ is set between 0 and VDAC. V defaults BATT to4.2V×cellcountwhenVADJisconnectedtoREGN. The CELLS pin is the logic input for selecting the cell count. Connect CELLS to the appropriate voltage level to charge 2,3, or 4 Li+ cells, as shown in Table 2. When charging other cell chemistries, use CELLS to select an outputvoltagerangeforthecharger. Table2.Cell-CountSelection CELLS CELLCOUNT Float 2 AGND 3 VREF 4 The per-cell charge-termination voltage is a function of the battery chemistry. Consult the battery manufacturer to determinethisvoltage. The BAT pin is used to sense the battery voltage for voltage regulation and should be connected as close to the battery as possible, or directly on the output capacitor. A 0.1-m F ceramic capacitor from BAT to AGND is recommendedtobeasclosetotheBATpinaspossibletodecouplehigh-frequencynoise. Battery Current Regulation The SRSET input sets the maximum charge current. Battery current is sensed by resistor R connected SR between SRP and SRN. The full-scale differential voltage between SRP and SRN is 100 mV. Thus, for a 0.010-Ω sense resistor, the maximum charging current is 10 A. SRSET is ratiometric with respect to VDAC using Equation2: V I (cid:2) SRSET(cid:1)0.10 CHARGE V R VDAC SR (2) TheinputvoltagerangeofSRSETisbetween0andV ,upto3.6V. DAC TheSRPandSRNpinsareusedtosenseacrossR ,withadefaultvalueof10mΩ.However,resistorsof other SR values can also be used. A larger sense-resistor value yields a larger sense voltage, and a higher regulation accuracy.However,thisisattheexpenseofahigherconductionloss. Input Adapter Current Regulation The total input current from an AC adapter or other DC sources is a function of the system supply current and the battery charging current. System current normally fluctuates as portions of the systems are powered up or down. Without Dynamic Power Management (DPM), the source must be able to supply the maximum system current and the maximum charger input current simultaneously. By using DPM, the input current regulator reduces the charging current when the input current exceeds the input current limit set by ACSET. The current capacityoftheACadaptercanbelowered,reducingsystemcost. Similar to setting battery-regulation current, adapter current is sensed by resistor R connected between ACP AC andACN.ItsmaximumvalueissetbyACSET,whichisratiometricwithrespecttoVDAC,usingEquation3. Copyright©2007–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLink(s):bq24751A

bq24751A SLUS756C–SEPTEMBER2007–REVISEDMARCH2009............................................................................................................................................. www.ti.com V I (cid:2) ACSET(cid:1)0.10 ADAPTER V R VDAC AC (3) TheinputvoltagerangeofACSETisbetween0andV ,upto3.6V. DAC The ACP and ACN pins are used to sense R with a default value of 10 mΩ. However, resistors of other values AC can also be used. A larger sense-resistor value yields a larger sense voltage, and a higher regulation accuracy. However,thisisattheexpenseofahigherconductionloss. Adapter Detect and Power Up An external resistor voltage divider attenuates the adapter voltage to the ACDET pin. The adapter detect threshold should typically be programmed to a value greater than the maximum battery voltage and lower than the minimum-allowed adapter voltage. The ACDET divider should be placed before the ACFET in order to sense the true adapter input voltage whether the ACFET is on or off. Before the adapter is detected, BATFET stays on andACFETturnsoff. IfPVCCisbelow4V,thedeviceisdisable. If ACDET is below 0.6 V but PVCC is above 4 V, part of the bias is enabled, including a crude bandgap reference, ACFET drive and BATFET drive. IADAPT is disabled and pulled down to GND. The total quiescent currentislessthan10m A. When ACDET rises above 0.6 V and PVCC is above 4 V, all the bias circuits are enabled and VREF goes to 3.3V. IF CHGEN is LOW, the REGN output rises to 6 V. IADAPT becomes valid to proportionally reflect the adaptercurrent. WhenACDETkeepsrisingandpasses2.4V,avalidACadapterispresent.500mslater,thefollowingoccurs: • ACGOODispulledhighthroughtheexternalpull-upresistortothehostdigitalvoltagerail; • ACFETisallowedtoturnonandBATFETturnsoffconsequently;(refertoSystemPowerSelector) • Charging begins if all the conditions are satisfied and STAT becomes valid. (refer to Enable and Disable Charging) Enable and Disable Charging Thefollowingconditionsmustbevalidbeforethechargefunctionisenabled: • CHGENisLOW • PVCC>UVLO • Adapterisdetected • AdaptervoltageishigherthanBAT+185mV • Adapterisnotovervoltage(ACOV) • 700msdelayiscompleteaftertheadapterisdetectedplus10msACOCtime • ThermalShut(TSHUT)isnotvalid • TSiswithinthetemperaturequalificationwindow • VDAC>2.4V • LEARNislow System Power Selector The bq24751A automatically switches between connecting the adapter or battery power to the system load. By default, the battery is connected to the system during power up or when a valid adapter is not present. When the adapter is detected, the battery is first disconnected from the system, then the adapter is connected. An automaticbreak-before-makealgorithmpreventsshoot-throughcurrentswhentheselectortransistorsswitch. The ACDRV signal drives a pair of back-to-back p-channel power MOSFETs (with sources connected together and to PVCC) connected between the adapter and ACP. The FET connected to the adapter prevents reverse 20 SubmitDocumentationFeedback Copyright©2007–2009,TexasInstrumentsIncorporated ProductFolderLink(s):bq24751A

bq24751A www.ti.com............................................................................................................................................. SLUS756C–SEPTEMBER2007–REVISEDMARCH2009 discharge from the battery to the adapter when it is turned off. The p-channel FET with the drain connected to the adapter input provides reverse battery discharge protection when off; and also minimizes system power dissipation, with its low R , compared to a Schottky diode. The other p-channel FET connected to ACP dson separates the battery from the adapter, and provides both ACOC current limit and ACOP power limit to the system.TheBATDRVsignalcontrolsap-channelpowerMOSFETplacedbetweenBATandthesystem. When the adapter is not detected, the ACDRV output is pulled to PVCC to turn off the ACFET, disconnecting the adapterfromsystem.BATDRVstaysatACN–6Vtoconnectthebatterytosystem. At 700 ms after adapter is detected, the system begins to switch from the battery to the adapter. The PVCC voltage must be 185 mV above BAT to enable the switching. The break-before-make logic turns off both ACFET and BATFET for 10m s before ACFET turns on. This isolates the battery from shoot-through current or any large discharging current. The BATDRV output is pulled up to ACN and the ACDRV pin is set to PVCC – 6 V by an internalregulatortoturnonthep-channelACFET,connectingtheadaptertothesystem. When the adapter is removed, the system waits till ACN drops back to within 285 mV above BAT to switch from the adapter back to the battery. The break-before-make logic ensures a 10-m s dead time. The ACDRV output is pulled up to PVCC and the BATDRV pin is set to ACN – 6 V by an internal regulator to turn on the p-channel BATFET,connectingthebatterytothesystem. Asymmetrical gate drive for the ACDRV and BATDRV drivers provides fast turn-off and slow turn-on of the ACFET and BATFET to help the break-before-make logic and to allow a soft-start at turn-on of either FET. The soft-start time can be further increased, by putting a capacitor from gate to source of the p-channel power MOSFETs. Battery Learn Cycles A battery Learn cycle can be implemented using the LEARN pin. A logic low on LEARN keeps the system power selector logic in its default states dependant on the adapter. If adapter is not detected, then; the ACFET is kept off,andtheBATFETiskepton.Iftheadapterisdetected,theBATFETiskeptoff,andtheACFETiskepton. When the LEARN pin is at logic high, the system power selector logic is overridden, keeping the ACFET off and the BATFET on when the adapter is present. This is used to allow the battery to discharge in order to calibrate the battery gas gauge over a complete discharge/charge cycle. Charge turns off when LEARN is high. The controllerautomaticallyexitsthelearncyclewhenBAT<2.9Vpercell.BATDRVturnsoffandACDRVturnson. Automatic Internal Soft-Start Charger Current The charger automatically soft-starts the charger regulation current every time the charger is enabled to ensure there is no overshoot or stress on the output capacitors or the power converter. The soft-start consists of stepping-upthechargeregulationcurrentinto8evenly-dividedstepsuptothe programmed charge current. Each step lasts approximately 1.7 ms, for a typical rise time of 13.6ms. No external components are needed for this function. Converter Operation The synchronous-buck PWM converter uses a fixed-frequency (300 kHz) voltage mode with a feed-forward control scheme. A Type-III compensation network allows the use of ceramic capacitors at the output of the converter. The compensation input stage is internally connected between the feedback output (FBO) and the error-amplifier input (EAI). The feedback compensation stage is connected between the error amplifier input (EAI) and error amplifier output (EAO). The LC output filter is selected for a nominal resonant frequency of 8 kHz–12.5kHz. 1 fo(cid:1) 2(cid:1)(cid:2)L C Theresonantfrequency,f ,isgivenby: o owhere(fromFigure1schematic) o • C =C11+C12 O • L =L1 O An internal sawtooth ramp is compared to the internal EAO error-control signal to vary the duty cycle of the converter. The ramp height is one-fifteenth of the input adapter voltage, making it always directly proportional to the input adapter voltage. This cancels out any loop-gain variation due to a change in input voltage, and simplifies the loop compensation. The ramp is offset by 200 mV in order to allow a 0% duty cycle when the EAO signal is below the ramp. The EAO signal is also allowed to exceed the sawtooth ramp signal in order to operate Copyright©2007–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLink(s):bq24751A

bq24751A SLUS756C–SEPTEMBER2007–REVISEDMARCH2009............................................................................................................................................. www.ti.com with a 100% duty-cycle PWM request. Internal gate-drive logic allows a 99.98% duty-cycle while ensuring that theN-channelupperdevicealwayshasenoughvoltagetostayfullyon.IftheBTST-to-PHvoltagefallsbelow4 V for more than 3 cycles, the high-side N-channel power MOSFET is turned off and the low-side N-channel power MOSFET is turned on to pull the PH node down and recharge the BTST capacitor. Then the high-side driver returns to 100% duty-cycle operation until the (BTST-PH) voltage is detected falling low again due to leakage currentdischargingtheBTSTcapacitorbelow4V,andtheresetpulseisreissued. The 300-kHz fixed-frequency oscillator tightly controls the switching frequency under all conditions of input voltage, battery voltage, charge current, and temperature. This simplifies output-filter design, and keeps it out of the audible noise region. The charge-current sense resistor R should be designed with at least half or more of SR the total output capacitance placed before the sense resistor, contacting both sense resistor and the output inductor; and the other half, or remaining capacitance placed after the sense resistor. The output capacitance should be divided and placed on both sides of the charge-current sense resistor. A ratio of 50:50 percent gives the best performance; but the node in which the output inductor and sense resistor connect should have a minimum of 50% of the total capacitance. This capacitance provides sufficient filtering to remove the switching noise and give better current-sense accuracy. The Type-III compensation provides phase boost near the cross-overfrequency,givingsufficientphasemargin. Synchronous and Non-Synchronous Operation The charger operates in non-synchronous mode when the sensed charge current is below the ISYNSET value. Otherwise,thechargeroperatesinsynchronousmode. During synchronous mode, the low-side N-channel power MOSFET is on when the high-side N-channel power MOSFET is off. The internal gate-drive logic uses break-before-make switching to prevent shoot-through currents. During the 30-ns dead time where both FETs are off, the back-diode of the low-side power MOSFET conducts the inductor current. Having the low-side FET turn-on keeps the power dissipation low, and allows safe charging at high currents. During synchronous mode, the inductor current always flows, and the device operates inContinuousConductionMode(CCM),creatingafixedtwo-polesystem. During non-synchronous operation, after the high-side n-channel power MOSFET turns off, and after the break-before-make dead-time, the low-side n-channel power MOSFET turns on for approximately 80 ns, then the low-side power MOSFET turns off and stays off until the beginning of the next cycle, when the high-side power MOSFET is turned on again. The 80-ns low-side MOSFET on-time is required to ensure that the bootstrap capacitor is always recharged and able to keep the high-side power MOSFET on during the next cycle. This is important for battery chargers, where unlike regular dc-dc converters, there is a battery load that maintains a voltage and can both source and sink current. The 80-ns low-side pulse pulls the PH node (connection between high and low-side MOSFET) down, allowing the bootstrap capacitor to recharge up to the REGN LDO value. After the 80 ns, the low-side MOSFET is kept off to prevent negative inductor current from flowing. The inductor current is blocked by the turned-off low-side MOSFET, and the inductor current becomes discontinuous. This modeiscalledDiscontinuousConductionMode(DCM). During the DCM mode, the loop response automatically changes and has a single-pole system at which the pole is proportional to the load current, because the converter does not sink current, and only the load provides a current sink. This means that at very low currents, the loop response is slower, because there is less sinking current available to discharge the output voltage. At very low currents during non-synchronous operation, there may be a small amount of negative inductor current during the 80-ns recharge pulse. The charge should be low enoughtobeabsorbedbytheinputcapacitance. Whenever BTST – PH < 4 V, the 80-ns recharge pulse occurs on LODRV, the high-side MOSFET does not turn on,andthelow-sideMOSFETdoesnotturnon(only80-nsrechargepulse). In the bq24751A, V =I ×R is internally set to 13mV as the charge-current threshold at which the ISYNSET SYN SR chargerchangesfromnon-synchronousoperationtosynchronousoperation.Thelow-sidedriverturnsonfor only 80 ns to charge the boost capacitor. This is important to prevent negative inductor current, which may cause a boost effect in which the input voltage increases as power is transferred from the battery to the input capacitors. This boost effect can lead to an over-voltage on the PVCC node and potentially damage the system. The inductorripplecurrentisgivenby 22 SubmitDocumentationFeedback Copyright©2007–2009,TexasInstrumentsIncorporated ProductFolderLink(s):bq24751A

bq24751A www.ti.com............................................................................................................................................. SLUS756C–SEPTEMBER2007–REVISEDMARCH2009 I RIPPLE_MAX £I £I SYN RIPPLE_MAX 2 and V 1 1 (V -V )´ BAT ´ V ´(1-D)´D´ IN BAT IN V f f I = IN s = s RIPPLE L L (4) where: V = adaptervoltage IN V = BATvoltage BAT f switchingfrequency S= L= outputinductor D= duty-cycle I Happenswhentheduty-cycle(D)ismostlynearto0.5atgivenV ,f ,andL. RIPPLE_MAX IN s The ISYNSET comparator, or charge undercurrent comparator, compares the voltage between SRP-SRN and internal threshold. The threshold is set to 13 mV on the falling edge, with an 8-mV hysteresis on the rising edge witha10%variation. High Accuracy IADAPT Using Current Sense Amplifier (CSA) An industry-standard, high-accuracy current sense amplifier (CSA) is used by the host or some discrete logic to monitor the input current through the analog voltage output of the IADAPT pin. The CSA amplifies the sensed input voltage of ACP – ACN by 20x through the IADAPT pin. The IADAPT output is a voltage source 20 times the input differential voltage. When PVCC is above 5 V and ACDET is above 0.6 V, IADAPT no longer stays at ground, but becomes active. If the user wants to lower the voltage, they can use a resistor divider from IOUT to AGND, and still achieve accuracy over temperature as the resistors can be matched according to their thermal coefficients. A 200-pF capacitor connected on the output is recommended for decoupling high-frequency noise. An additional RC filter is optional, after the 200-pF capacitor, if additional filtering is desired. Note that adding filtering also addsadditionalresponsedelay. Input Overvoltage Protection (ACOV) ACOV provides protection to prevent system damage due to high input voltage. Once the adapter voltage is above the programmable OVPSET voltage (3.1 V), charge is disabled, the adapter is disconnected from the system by turning off ACDRV, and the battery is connected to the system by turning on BATDRV. ACOV is not latched—normaloperationresumeswhentheOVPSETvoltagereturnsbelow3.1V. Input Undervoltage Lock Out (UVLO) The system must have 5 V minimum of PVCC voltage for proper operation. This PVCC voltage can come from either the input adapter or the battery, using a diode-OR input. When the PVCC voltage is below 5 V, the bias circuits REGN, VREF, and the gate drive bias to ACFET and BATFET stay inactive, even with ACDET above 0.6 V. Note: Thebq24751AwillnotallowACDRVtoturnonintheuniqueconditionthatACP<3Vand PVCC>UVLO.Inthiscondition,thebreak-before-makeprotectionlatchgetsstuckinastatethatit thinkstheBATDRVisON,anddoesnotallowtheACDRVtoturnon. Battery Overvoltage Protection The converter stops switching when BAT voltage goes above 104% of the regulation voltage. The converter will not allow the high-side FET to turn on until the BAT voltage goes below 102% of the regulation voltage. This allows one-cycle response to an overvoltage condition, such as when the load is removed or the battery is disconnected. A 10-mA current sink from BAT to PGND is on only during charge, and allows discharging the storedoutput-inductorenergyintotheoutputcapacitors. Copyright©2007–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLink(s):bq24751A

bq24751A SLUS756C–SEPTEMBER2007–REVISEDMARCH2009............................................................................................................................................. www.ti.com Battery Shorted (Battery Undervoltage) Protection The bq24751A has a BAT SHORT comparator monitoring the output battery voltage (BAT). If the voltage falls below 2.9 V per cell (5.8 V for 2 cells, 8.7 V for 3 cells, 11.6 V for 4 cells), a battery-short status is detected. Below the BAT_SHORT threshold, the charger reduces the charge current to 1/8th of the programmed charging current (0.1×SRSET/VDAC)/8 = C/8 down to zero volts on BAT pin.. This lower current is used as a pre-charge current for over-discharged battery packs. Above the BAT_SHORT threshold (plus hysteresis, the charge current resumesattheprogrammedvalue(0.1×SRSET/VDAC). The BAT_SHORT comparator also serves as a depleted-battery alarm during a LEARN cycle. If the selector is in a LEARN cycle, and the battery voltage falls bellow the BAT_SHORT threshold, the selector disconnects the battery from the system and connects the adapter to the system in order to protect the battery pack. If battery voltage increases, and LEARN is still logic high, then the selector disconnects the adapter from the system and reconnectsthebatterytothesystem. Charge Overcurrent Protection The charger has a secondary overcurrent protection feature. It monitors the charge current, and prevents the current from exceeding 145% of regulated charge current. The high-side gate drive turns off when the overcurrentisdetected,andautomaticallyresumeswhenthecurrentfallsbelowtheovercurrentthreshold. Thermal Shutdown Protection The QFN package has low thermal impedance, which provides good thermal conduction from the silicon to the ambient, to keep junction temperatures low. As an added level of protection, the charger converter turns off and self-protects when the junction temperature exceeds the TSHUT threshold of 155°C. The charger stays off until thejunctiontemperaturefallsbelow135°C. Adapter Detected Status Register (ACGOOD Pin) One status output is available, and it requires an external pullup resistor to pull the pin to the system digital rail forahighlevel. ACGOOD goes low when ACDET is above 2.4 V and the 700-ms delay time is over. It indicates that the adapter voltageishighenoughfornormaloperation. Input Over-Power Protection (ACOP) The ACOC/ACOP circuit provides a reliable layer of safety protection that can complement other safety measues.ACOC/ACOPhelpstoprotectfrominputcurrentsurgeduetovariousconditionsincluding: • Adapterinsertionandsystemselectorconnectingadaptertosystemwheresystemcapacitorsneedtocharge • Learnmodeexitwhenadapterisreconnectedtothesystem;systemloadover-currentsurge • Systemshortedtoground • Batteryshortedtoground • Phaseshortedtoground • High-sideFETshortedfromdraintosource(SYSTEMshortedtoPH) • BATFETshortedfromdraintosource(SYSTEMshortedtoBAT) Severalexamplesofthecircuitprotectingfromthesefaultconditionsareshownbelow. For designs using the selector functions, an input overcurrent (ACOC) and input over-power protection function (ACOP) is provided. The threshold is set by an external capacitor from the ACOP pin to AGND. After the adapter is detected (ACDET pin > 2.4V), there is a 700-ms delay before ACGOOD is asserted low, and Q3 (BATFET) is turned-off. Then Q1/Q2 (ACFET) are turned on by the ACDRV pin. When Q1/Q2 (ACFET) are turned on, the ACFET allows operation in linear-regulation mode to limit the maximum input current, ACOC, to a safe level. The ACOC current limit is 1.5 times the programmed DPM input current limit set by the ratio of SRSET/VDAC. The maximumallowablecurrentlimitis100mVacrossACP–ACN(10Afora10-mΩsenseresistor). The first 2 ms after the ACDRV signal begins to turn on, ACOC may limit the current; but the controller is not allowedtolatchoffinordertoallowareasonabletimeforthesytemvoltagetorise. 24 SubmitDocumentationFeedback Copyright©2007–2009,TexasInstrumentsIncorporated ProductFolderLink(s):bq24751A

bq24751A www.ti.com............................................................................................................................................. SLUS756C–SEPTEMBER2007–REVISEDMARCH2009 After 2 ms, ACOP is enabled. ACOP allows the ACFET to latch off before the ACFET can be damaged by excessive thermal dissipation. The controller only latches if the ACOP pin voltage exceeds 2 V with respect to AGND. In ACOP, a current source begins to charge the ACOP capacitor when the input current is being limited by ACOC. This current source is proportional to the voltage across the source-drain of the ACFET (V ) by PVCC-ACP an 18-m A/V ratio. This dependency allows faster capacitor charging if the voltage is larger (more power dissipation). It allows the time to be programmed by the ACOP capacitor selected. If the controller is not limiting current,afixed5-m AsinkcurrentintotheACOPpintodischarge the ACOP capacitor. This charge and discharge effect depends on whether there is a current-limit condition, and has a memory effect that averages the power over time, protecting the system from potentially hazardous repetitive faults. Whenever the ACOP threshold is exceeded, the charge is disabled and the adapter is disconnected from the system to protect the ACFET and the wholesystem.IftheACFETislatchedoff,theBATFETisturnedontoconnectthebatterytothesystem. The capacitor provides a predictable time to limit the power dissipation of the ACFET. Since the input current is constantattheACOCcurrentlimit,thedesignercancalculatethepowerdissipationontheACFET. Power =I ×V =I ×V(PVCC-ACP) TheACOCcurrentLimitthresholdisequalto d sd ACOC_LIM . Thetimeittakestochargeto2Vcanbecalculatedfrom C ×DV C ×2V Dt = ACOP ACOP = ACOP iACOP 18mA/V×V(PVCC-ACP) (5) An ACOP fault latch off can only be cleared by bringing the ACDET pin voltage below 2.4 V, then above 2.4 V (i.e.removeadapterandreinsert),orbyreducingthePVCCvoltagebelowtheUVLOthresholdandraisingit. ConditionsforACOPLatchOff: 702msafterACDET(adapterdetected),and a. ACOP voltage > 2V. The ACOP pin charges the ceramic capacitor when in an ACOC current-limit condition. TheACOPpindischargesthecapacitorwhennotinACOCcurrent-limit. b. ACOP protects from a single-pulse ACOC condition depending on duration and source-drain voltage of ACFET. Larger voltage across ACFET creates more power dissipation so latch-off protection occurs faster, byincreasingthecurrentsourceoutofACOPpin. c. Memory effect (capacitor charging and discharging) allows protection from repititive ACOC conditions, dependingondurationandfrequency.(Figure35) d. Inshortconditionswhenthesystemisshortedtoground(ACN<2.4V)aftertheinitial2-msACDET. Copyright©2007–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLink(s):bq24751A

bq24751A SLUS756C–SEPTEMBER2007–REVISEDMARCH2009............................................................................................................................................. www.ti.com In all cases,after700ms delay,have input over- current protection, ACOC,by linearly limiting input current. Threshold is equal to the lower of Idpm*1.5,or 10A. ACOC,withACOPLatch-off, After Latch-Off,Latch can only clear by: off Latch-off time accumulates h- only when in current limit 1)bringingACDETbelow atc regulation,ACOC. The time 2.4V,then above2.4V;or L before latch-off is o N programmable with Cacop, 2)bringing PVCC below 700ms delay after COC, asonudr cise i-ndvraeirns evloyl tpargoep oorftional to UUVVLLOO,.then above ACDET,before allow A ACFET(power). Cacop ACDRV to turn-on charge/discharge per time also provides memory for power averaging over time. 700ms 2ms 8ms Allow Charge toTurn-on Vin Vadapter ACDET 0V ACGOOD BATDRV ACDRV Vadapter Vsystem Vbattery Ilim=1.5xIdpm (100 mV max Input Current AcrossACP_ACN) Allow Charge Charge Current V(ACOP) A. ACFEToverpowerprotection;initialcurrentlimitallowssafesoft-startwithoutsystemvoltagedroop. Figure34.ACOCProtectionDuringAdapterInsertion 26 SubmitDocumentationFeedback Copyright©2007–2009,TexasInstrumentsIncorporated ProductFolderLink(s):bq24751A

bq24751A www.ti.com............................................................................................................................................. SLUS756C–SEPTEMBER2007–REVISEDMARCH2009 Iin Ilim= 1.5xIdpm ACOC_REG V(PVCC-ACP) LATCH-OFF Iacop_pin LATCH-OFF 2V V(ACOP) Memory Effect Averages Power ON OFF ACDRV_ON LATCH-OFF Figure35.ACOCProtectionandACOPLatchOffwithMemoryEffectExample Copyright©2007–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLink(s):bq24751A

bq24751A SLUS756C–SEPTEMBER2007–REVISEDMARCH2009............................................................................................................................................. www.ti.com RAC 0.01W ADAPTER+ R10 2W P P ADAPTER– C1 Q1 (ACFET) Q2(ACFET) 2.2µF SI4435 SI4435 C2 C3 0.1 µF 0.1 µF ACSET ACDRV_ON ACOC ERROR AMPLIFIER and DRIVER Regulation ACDRV Reference IDPM –+ Lowest of IDPM_PRG Ratio- 1.5xIDPM_PRG metric ACOCREG = or Program REGULATING 10A(100 mV) (100 mV_max) IIN ACN DifferentialAmp CSA – V(ACP-ACN) ACP + IADAPT – + PVCC VDS DifferentialAmp C8 V(PVCC-ACP) 0.1 µF Isrc = K*V(PVCC-ACP) K = 18µA/V REF = 3.3 V ACOPAdaptor ENA_SRC Over Power ACOP Comparator ACDRVand BATDRV 0.4C7a cµoFp ENA_SNK 5µA +– ACOPDET De1g µlistch ACOPDETDG befborreea-mk-ake –+ 2V aRnids iRnge-sEedt gInep Suetst SR QQ logic ACDET ACDET 700 ms Turn-offACDRV PVCC_UVLO Delay To clear latch fault, user must remove adapter and reinsert, or PVCC brought below then above input UVLO threshold Figure36.ACOC/ACOPCircuitFunctionalBlockDiagram Table3.ComponentListforTypicalSystemCircuitofFigure1 PARTDESIGNATOR QTY DESCRIPTION Q1,Q2,Q3 3 P-channelMOSFET,–30V,–6A,SO-8,Vishay-Siliconix,Si4435 Q4,Q5 2 N-channelMOSFET,30V,12.5A,SO-8,Fairchild,FDS6680A D1 1 Diode,DualSchottky,30V,200mA,SOT23,Fairchild,BAT54C R ,R 2 SenseResistor,10mΩ,1%,1W,2010,Vishay-Dale,WSL2010R0100F AC SR L1 1 Inductor,8.2m H,8.5A,24.8mΩ,Vishay-Dale,IHLP5050CE-01 C1 1 Capacitor,Ceramic,2.2m F,25V,20%,X5R,1206,Panasonic,ECJ-3YB1E225M C6,C7,C11,C12 4 Capacitor,Ceramic,10m F,35V,20%,X5R,1206,Panasonic,ECJ-3YB1E106M C4,C10 2 Capacitor,Ceramic,1m F,25V,10%,X7R,2012,TDK,C2012X7R1E105K C2,C3,C8,C9,C13,C14,C15 7 Capacitor,Ceramic,0.1m F,50V,10%,X7R,0805,Kemet,C0805C104K5RACTU C5 1 Capacitor,Ceramic,100pF,25V,10%,X7R,0805,Kemet C16 1 Capacitor,Ceramic,0.47m F,25V,10%,X7R,0805,Kemet R1 1 Resistor,Chip,432kΩ,1/16W,1%,0402 R2 1 Resistor,Chip,66.5kΩ,1/16W,1%,0402 R3 1 Resistor,Chip,422kΩ,1/16W,1%,0402 R4 1 Resistor,Chip,71kΩ,1/16W,5%,0402 R10 1 Resistor,Chip,2Ω,1W,5%,2010 28 SubmitDocumentationFeedback Copyright©2007–2009,TexasInstrumentsIncorporated ProductFolderLink(s):bq24751A

bq24751A www.ti.com............................................................................................................................................. SLUS756C–SEPTEMBER2007–REVISEDMARCH2009 APPLICATION INFORMATION Input Capacitance Calculation During the adapter hot plug-in, the ACDRV has not been enabled. The AC switch is off and the simplified equivalentcircuitoftheinputisshowninFigure37. IIIINN VVIINN RRii LLii RRcc VVii CCii VVcc Figure37.SimplifiedEquivalentCircuitDuringAdapterInsertion Thevoltageontheinputcapacitor(s)isgivenby: R VIN(t)=IIN(t)´RC +VCi(t)=Vie2LiitéêëRwi-LRiC sinwt+coswtùúû (6) inwhich, R 2 i æ ö t R =R +R w = 1 - ç Rt ÷ I (t)= Vi e2Li sinwt t i C IN LC è2L ø wL i i i i (7) R tt æ ö V (t)=V -Ve2Li ç Rt sinwt+coswt÷ Ci i i è2wL ø i (8) Thedampingconditionsis: L R =R > 2 i C C (9) Copyright©2007–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLink(s):bq24751A

bq24751A SLUS756C–SEPTEMBER2007–REVISEDMARCH2009............................................................................................................................................. www.ti.com Figure 38 (a) demonstrates a higher Ci helps dampen the voltage spike. Figure 38 (b) demonstrates the effect of theinputstrayinductanceLi upon the input voltage spike. Figure 38(c) shows how increased resistance helps to suppresstheinputvoltagespike. 35 35 30 Ci= 20mF Ri= 0.21W 30 Li= 5mH Ri= 0.15W e - V 25 Ci= 40mF Li= 9.3mH e - V 25 Li= 12mH Ci= 40mF g g a a Volt 20 Volt 20 or or acit 15 acit 15 p p a a C C ut 10 ut 10 p p n n I I 5 5 0 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Time - ms Time - ms (a) Vcwith various Civalues (b) Vcwith various Livalues 35 30 Ri= 0.15W Li= 9.3mH e - V 25 Ri= 0.5W Ci= 40mF g a Volt 20 or acit 15 p a C ut 10 p n I 5 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Time - ms (c) Vcwith various Rivalues Figure38.ParametricStudyOfTheInputVoltage As shown in Figure 38, minimizing the input stray inductance, increasing the input capacitance, and adding resistance (including using higher ESR capacitors) helps suppress the input voltage spike. However, a user often cannot control input stray inductance and increasing capacitance can increase costs. Therefore, the most efficientandcost-effectiveapproachistoaddanexternalresistor. 30 SubmitDocumentationFeedback Copyright©2007–2009,TexasInstrumentsIncorporated ProductFolderLink(s):bq24751A

bq24751A www.ti.com............................................................................................................................................. SLUS756C–SEPTEMBER2007–REVISEDMARCH2009 Figure 39 depicts the recommended input filter design. The measured input voltage and current waveforms are shown in Figure 40. The input voltage spike has been well damped by adding a 2Ω resistor, while keeping the capacitancelow. V V IN PVCC 2W Rext (0.5 W, 1210 anti-surge) 2.2mF C1 C2 0.1mF (25 V, 1210) (50 V, 0805, very close to PVCC) Figure39.RecommendedInputFilterDesign Figure40.AdapterDCSideHotPlug-inTestWaveforms Copyright©2007–2009,TexasInstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLink(s):bq24751A

bq24751A SLUS756C–SEPTEMBER2007–REVISEDMARCH2009............................................................................................................................................. www.ti.com PCB Layout Design Guideline 1. It is critical that the exposed power pad on the backside of the IC package be soldered to the PCB ground. Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on the otherlayers. 2. The control stage and the power stage should be routed separately. At each layer, the signal ground and the powergroundareconnectedonlyatthepowerpad. 3. The AC current-sense resistor must be connected to ACP (pin 3) and ACN (pin 2) with a Kelvin contact. The area of this loop must be minimized. An additional 0.1m F decoupling capacitor for ACN is required if this loop isbig.ThedecouplingcapacitorsforthesepinsshouldbeplacedasclosetotheICaspossible. 4. The charge-current sense resistor must be connected to SRP (pin 19), SRN (pin 18) with a Kelvin contact. The area of this loop must be minimized. An additional 0.1m F decoupling capacitor for SRN is required if this loopisbig.ThedecouplingcapacitorsforthesepinsshouldbeplacedasclosetotheICaspossible. 5. DecouplingcapacitorsforPVCC(pin28),VREF(pin10), REGN (pin 24) should be placed underneath the IC (onthebottomlayer)withtheinterconnectionstotheICasshortaspossible. 6. Decoupling capacitors for BAT (pin 17), IADAPT (pin 15) must be placed close to the corresponding IC pins withtheinterconnectionstotheICasshortaspossible. 7. DecouplingcapacitorCXforthechargerinputmustbeplacedveryclosetotheQ4drainandQ5source. Figure41showstherecommendedcomponentplacementwithtraceandvialocations. FortheQFNinformation,pleaserefertothefollowinglinks:SCBA017andSLUA271 (a) Top Layer (b) Bottom Layer Figure41.LayoutExample 32 SubmitDocumentationFeedback Copyright©2007–2009,TexasInstrumentsIncorporated ProductFolderLink(s):bq24751A

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) BQ24751ARHDR ACTIVE VQFN RHD 28 3000 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 BQ & no Sb/Br) 24751A BQ24751ARHDT ACTIVE VQFN RHD 28 250 Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 BQ & no Sb/Br) 24751A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 18-Aug-2014 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) BQ24751ARHDR VQFN RHD 28 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 BQ24751ARHDR VQFN RHD 28 3000 330.0 12.4 5.3 5.3 1.1 8.0 12.0 Q2 BQ24751ARHDT VQFN RHD 28 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 BQ24751ARHDT VQFN RHD 28 250 180.0 12.4 5.3 5.3 1.1 8.0 12.0 Q2 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 18-Aug-2014 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) BQ24751ARHDR VQFN RHD 28 3000 367.0 367.0 35.0 BQ24751ARHDR VQFN RHD 28 3000 367.0 367.0 35.0 BQ24751ARHDT VQFN RHD 28 250 210.0 185.0 35.0 BQ24751ARHDT VQFN RHD 28 250 210.0 185.0 35.0 PackMaterials-Page2

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