Not Recommended For New Designs bq24150A bq24151A www.ti.com SLUS931A–APRIL2009–REVISEDJANUARY2010 Fully Integrated Switch-Mode One-Cell Li-Ion Charger With Full USB Compliance and USB-OTG Support CheckforSamples:bq24150A,bq24151A FEATURES 1 • ChargeFasterthanLinearChargers 4.5V 2 • High-AccuracyVoltageandCurrentRegulation – OutputforVBUS:5.05V/200mA – InputCurrentRegulationAccuracy: ±5% • 2x2mm20-PinWCSPPackage (100mAand500mA) APPLICATIONS – ChargeVoltageRegulationAccuracy: ±0.5%(25°C),±1%(0°Cto125°C) • MobileandSmartPhones – ChargeCurrentRegulationAccuracy: ±5% • MP3Players • High-EfficiencyMini-USB/ACBatteryCharger • HandheldDevices forSingle-CellLi-IonandLi-PolymerBattery DESCRIPTION Packs • 20-VAbsoluteMaximumInputVoltageRating The bq24150A/1A is a compact, flexible, high-efficiency, USB-friendly switch-mode charge • 6-VMaximumOperatingInputVoltage management device for single-cell Li-ion and • Built-InInputCurrentSensingandLimiting Li-polymer batteries used in a wide range of portable • IntegratedPowerFETsforUpTo1.25-A applications. The charge parameters can be ChargeRate programmed through an I2C interface. The bq24150A/1A integrates a synchronous PWM • ProgrammableChargeParametersthrough controller, power MOSFETs, input current sensing, I2C™Interface(upto3.4Mbps): high-accuracy current and voltage regulation, and – InputCurrent chargetermination,intoasmallWCSPpackage. – Fast-Charge/TerminationCurrent The bq24150A/1A charges the battery in three – ChargeVoltage(3.5Vto4.44V) phases: conditioning, constant current and constant – SafetyTimerwithResetControl voltage. The input current is automatically limited to the value set by the host. Charge is terminated based – TerminationEnable on user-selectable minimum current level. A safety • SynchronousFixed-FrequencyPWM timer with reset control provides a safety backup for ControllerOperatingat3MHzWith0%to I2C interface. During normal operation, bq24150A/1A 99.5%DutyCycle automatically restarts the charge cycle if the battery • RobustProtection voltage falls below an internal threshold and automatically enters sleep mode or high impedance – ReverseLeakageProtectionPrevents mode when the input supply is removed. The charge BatteryDrainage statusisreportedtothehostusingtheI2Cinterface. – ThermalRegulationandProtection – Input/OutputOvervoltageProtection TYPICALAPPLICATIONCIRCUIT •• SAtuattoumsaOtiuctpHuigthfoIrmCpheadragnincgeManoddeFafourltsLow VBUS1CmINF VBUSbq241U510A/1ASW C1L0OBnOF1O.0TmH RSNS 1C0mOF PowerConsumption PMID BOOT PACK+ VAUX CIN PGND 0.1mF + •• UASutBomFraietincdClyhaBrogoint-gU–pbSqe2q4u1e5n0cAe 10S CkWL 10 kW10 kW 4.7mI2FC BUS SCL CSCOSUINT PACK- •• ABuotoosmtMatoicdeHiOghpeImraptieodnafnocreUMSoBdOeT–Gb:q24151A SSOHDTTOAAGTST 10 kW SOSDTTAAGT AUXVPRWERF C1mVFREF C1AmFUXPWR – InputVoltageRange(fromBattery):2.5Vto 1 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. I2CisatrademarkofPhilipsElectronics. 2 PRODUCTIONDATAinformationiscurrentasofpublicationdate. Copyright©2009–2010,TexasInstrumentsIncorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarilyincludetestingofallparameters.

bq24150A Not Recommended For New Designs bq24151A SLUS931A–APRIL2009–REVISEDJANUARY2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriateprecautions.Failuretoobserveproperhandlingandinstallationprocedurescancausedamage. ESDdamagecanrangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmaybemore susceptibletodamagebecauseverysmallparametricchangescouldcausethedevicenottomeetitspublishedspecifications. DESCRIPTION CONTINUED During the charging process, the bq24150A/1A monitors its junction temperature (T ) and reduces the charge J current once T increases to approximately 125°C. To support USB OTG device, bq24150A/1A provides VBUS J (approximately5.05V)byboostingthebatteryvoltage.Thebq24150A/1Aisavailablein20-pinWCSPpackage. WCSPPACKAGE (TopView) A1 A2 A3 A4 VBUS VBUS BOOT SCL B1 B2 B3 B4 PMID PMID PMID SDA C1 C2 C3 C4 SW SW SW STAT D1 D2 D3 D4 PGND PGND PGND OTG E1 E2 E3 E4 AUX CSIN PWR VREF CSOUT TERMINALFUNCTIONS TERMINAL I/O DESCRIPTION NAME NO. Batteryvoltageandcurrentsenseinput.Bypassitwithaceramiccapacitor(minimum0.1mF)to CSOUT E4 I PGNDiftherearelonginductiveleadstobattery. VBUS A1,A2 I Chargerinputvoltage.Bypassitwitha1-mFceramiccapacitorfromVBUStoPGND. ConnectionpointbetweenreverseblockingMOSFETandhigh-sideswitchingMOSFET.Bypassit PMID B1,B2,B3 O withaminimumof3.3-mFcapacitorfromPMIDtoPGND. SW C1,C2,C3 O Internalswitchtooutputinductorconnection. Boot-strappedcapacitorforthehigh-sideMOSFETgatedriver.Connecta10-nFceramiccapacitor BOOT A3 O (voltageratingabove10V)fromBOOTpintoSWpin. PGND D1,D2,D3 Powerground Chargecurrent-senseinput.Batterycurrentissensedviathevoltagedropacrossanexternalsense CSIN E1 I resistor.A0.1-mFceramiccapacitortoPGNDisrequired. SCL A4 I I2Cinterfaceclock.Opendrainoutput,connecta10-kΩpullupresistorto1.8Vrail SDA B4 I/O I2Cinterfacedata.Opendrainoutput,connecta10-kΩpullupresistorto1.8Vrail Chargestatuspin.Pulllowwhenchargeinprogress.Opendrainforotherconditions.Duringfaults,a STAT C4 O 128-mSpulseissentout.STATpincanbedisabledbytheEN_STATbitincontrolregister.STATcan beusedtodriveaLEDorcommunicatewithahostprocessor. Internalbiasregulatorvoltage.Connecta1-mFceramiccapacitorfromthisoutputtoPGND.External VREF E3 O loadonVREFisnotallowed. Auxiliarypowersupply,connectedtothebatterypacktoprovidepowerinhigh-impedancemode. AUXPWR E2 I Bypassitwitha1-mFceramiccapacitorfromthispintoPGND. Boostmodeenablecontrolorinputcurrentlimitingselectionpin.WhenOTGisinactivestatus, bq24150A/1Aisforcedtooperateinboostmode.IthashigherpriorityoverI2Ccontrolandcanbe disabledthroughcontrolregister.ThelogicvoltagelevelatOTGactivestatuscanalsobecontrolled. OTG D4 I AtPOR,theOTGpinisdefaulttobeusedastheinputcurrentlimitingselectionpin.WhenOTG= High,Iin–limit=500mAandwhenOTG=Low,Iin–limit=100mA,seetheControlRegisterfor details. 2 SubmitDocumentationFeedback Copyright©2009–2010,TexasInstrumentsIncorporated ProductFolderLink(s):bq24150Abq24151A

Not Recommended For New Designs bq24150A bq24151A www.ti.com SLUS931A–APRIL2009–REVISEDJANUARY2010 PACKAGEDIMENSIONS PACKAGEDEVICES D E bq24150A,bq24151A 1.976±0.05mm 1.946±0.05mm ORDERINGINFORMATION(1) AUTOMATICCHARGING PARTNUMBERBITPN0, PARTNO. MARKING MEDIUM QUANTITY (VBUSRecycled,V <V , BAT LOWV CONTROLREGISTER03H,BIT3 32MinutesMode) bq24150AYFFR bq24150A TapeandReel 3000 Yes 1 bq24150AYFFT bq24150A TapeandReel 250 Yes 1 bq24151AYFFR bq24151A TapeandReel 3000 No 0 bq24151AYFFT bq24151A TapeandReel 250 No 0 (1) Forthemostcurrentpackageinformation,seethePackageOptionAddendumattheendofthisdocument,orseetheTIwebsiteat www.ti.com. DISSIPATION RATINGS(1) T ≤25°C DERATINGFACTOR PACKAGE R R A qJA qJC POWERRATING T >25°C A WSCP-20 (1) 185°C/W(2) 1.57°C/W 0.54W 0.0054W/°C (1) MaximumpowerdissipationisafunctionofT(max),Rq andT .Themaximumallowablepowerdissipationatanyallowableambient J JA A temperatureisP =[T(max)-T ]/Rq . D J A JA (2) ForPCBboardwithonlytoptracelayer.ForPCBboardwithfourlayers(toptracelayer,buriedgroundlayer,buriedsignallayerand bottomlayer),Rq dropsto75.96°C/W JA ABSOLUTE MAXIMUM RATINGS(1) (2) overoperatingfree-airtemperaturerange(unlessotherwisenoted) VALUE UNIT V Supplyvoltagerange(withrespecttoPGND) VBUS –0.3to20(3) V SS V Inputvoltagerange(withrespecttoandPGND) SCL,SDA,OTG,CSIN,CSOUT,AUXPWR –0.3to7 V I PMID,STAT –0.3to20 V V Outputvoltagerange(withrespecttoandPGND) VREF 6.5 V O SW,BOOT –0.7to20 V VoltagedifferencebetweenCSINandCSOUTinputs(V –V ) ±7 V (CSIN) (CSOUT) Outputsink STAT 10 mA I OutputCurrent(average) SW 1.25 A O T Operatingfree-airtemperaturerange –40to85 °C A T Junctiontemperature –40to150 °C J T Storagetemperature –65to150 °C stg (1) Stressesbeyondthoselistedunderabsolutemaximumratingsmaycausepermanentdamagetothedevice.Thesearestressratings only,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunderrecommendedoperating conditionsisnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability.Allvoltage valuesarewithrespecttothenetworkgroundterminalunlessotherwisenoted. (2) AllvoltagesarewithrespecttoGNDifnotspecified.Currentsarepositiveinto,negativeoutofthespecifiedterminal. (3) Thebq24150A/1Afamilycanwithstandupto10.6Vcontinuouslyand20Vforaminimumof432hours. Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):bq24150Abq24151A

bq24150A Not Recommended For New Designs bq24151A SLUS931A–APRIL2009–REVISEDJANUARY2010 www.ti.com RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT V Supplyvoltage,VBUS 4 6(1) V BUS T Operatingjunctiontemperaturerange 0 +125 °C J (1) TheinherentswitchingnoisevoltagespikesshouldnotexceedtheabsolutemaximumratingoneithertheBOOSTorSWpins.Atight layoutminimizesswitchingnoise. ELECTRICAL CHARACTERISTICS CircuitofFigure1,VBUS=5V,HZ_MODE=0,OPA_MODE=0(chargermodeoperation),T =0°Cto125°C,T =25°Cfor J J typicalvalues(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT INPUTCURRENTS VBUS>VBUS(min),PWMswitching 10 mA VBUS>VBUS(min),PWMNOTswitching 5 I(VBUS) VBUSsupplycurrentcontrol 0V°(ACUX<PWTJR)<>8V5(°LCO,WVV)B,USSCL=,5SDVA,H,OZ_TMGO=D0EV=o1r,1.8V 20 mA 0°C<TJ<85°C,VBUS=5V,HZ_MODE=1, V(AUXPWR)<V(LOWV),32Smode,SCL,SDA,OTG=0 35 mA Vor1.8V Ilkg LeakagecurrentfrombatterytoVBUSpin 0m°oCde<TJ<85°C,V(AUXPWR)=4.2V,HighImpedance 5 mA BatterydischargecurrentinHighImpedance 0°C<TJ<85°C,V(AUXPWR)=4.2V,HighImpedance 20 mA mode,(CSIN,CSOUT,AUXPWR,SWpins) mode,SCL,SDA,OTG=0Vor1.8V VOLTAGEREGULATION V(OREG) Outputchargevoltage Operatinginvoltageregulation,programmable 3.5 4.44 V TA=25°C –0.5% 0.5% Voltageregulationaccuracy –1% 1% CURRENTREGULATION(FASTCHARGE) IO(CHARGE) Outputchargecurrent VV(BLOUWSV)>≤VV(S(ALPU)X,PRW(RSN)S<)V=(O6R8EmG)Ω, ,Programmable 550 1250 mA Regulationaccuracyforchargecurrentacross 20mV≤V(IREG)≤40mV –5% 5% RV((ISRNESG))=IO(CHARGE)×R(SNS) 40mV<V(IREG) –3% 3% WEAKBATTERYDETECTION V(LOWV) Weakbatteryvoltagethreshold Programmable 3.4 3.7 V Weakbatteryvoltageaccuracy –5% 5% HysteresisforV(LOWV) Batteryvoltagefalling 100 mV Deglitchtimeforweakbatterythreshold Risingvoltage,2-mVoverdrive,tRISE=100ns 30 ms OTGPINLOGICLEVEL VIL Inputlowthresholdlevel 0.4 V VIH Inputhighthresholdlevel 1.3 V CHARGETERMINATIONDETECTION I(TERM) Terminationchargecurrent VV(BAUUXSPW>RV)>(SLVP()O,RRE(GSN)S–)V=(R6C8Hm),Ω,Programmable 50 400 mA Deglitchtimeforchargetermination Bothrisingandfalling,2-mVoverdrive, 30 ms tRISE,tFALL=100ns Voltageregulationaccuracyfortermination 3mV≤V(IREG_TERM)<5mV –25% 25% currentacrossR(SNS) 5mV≤V(IREG_TERM)<20mV –10% 10% V(IREG_TERM)=IO(TERM)×R(SNS) 20mV≤V(IREG_TERM)≤40mV –5% 5% INPUTPOWERSOURCEDETECTION Inputvoltagelowerlimit Inputpowersourcedetection,Inputvoltagefalling 3.6 3.8 4 V VIN(min) DeglitchtimeforVBUSrisingaboveVIN(min) Risingvoltage,2-mVoverdrive,tRISE=100ns 30 ms HysteresisforVIN(min) Inputvoltagerising 100 200 mV tINT DetectionInterval Inputpowersourcedetection 2 S 4 SubmitDocumentationFeedback Copyright©2009–2010,TexasInstrumentsIncorporated ProductFolderLink(s):bq24150Abq24151A

Not Recommended For New Designs bq24150A bq24151A www.ti.com SLUS931A–APRIL2009–REVISEDJANUARY2010 ELECTRICAL CHARACTERISTICS (continued) CircuitofFigure1,VBUS=5V,HZ_MODE=0,OPA_MODE=0(chargermodeoperation),T =0°Cto125°C,T =25°Cfor J J typicalvalues(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT INPUTCURRENTLIMITING USBcharge IIN=100mA 88 93 98 mA IIN Inputcurrentlimitingthreshold mode IIN=500mA 450 475 500 VREFBIASREGULATOR VREF Internalbiasregulatorvoltage VI(VBRUEFS)=>V1INm(mAi,nC)(oVrRVEF(A)U=XP1WmRF)>V(BAT)min, 2 6.5 V VREFoutputshortcurrentlimit 30 mA BATTERYRECHARGETHRESHOLD V(RCH) Rechargethresholdvoltage BelowV(OREG) 100 120 150 mV Deglitchtime V(AUXPWR)decreasingbelowthreshold, 130 ms tFALL=100ns,10-mVoverdrive STATOUTPUTS Low-leveloutputsaturationvoltage,STAT IO=10mA,sinkcurrent 0.4 V VOL(STAT) High-levelleakagecurrentforSTAT VoltageonSTATpinis5V 1 mA I2CBUSLOGICLEVELSANDTIMINGCHARACTERISTICS VOL Outputlowthresholdlevel IO=10mA,sinkcurrent 0.4 V VIL Inputlowthresholdlevel 0.4 V VIH Inputhighthresholdlevel 1.2 V I(BIAS) Inputbiascurrent V(pull-up)=1.8V,SDAandSCL 1 mA f(SCL) SCLclockfrequency 3.4 MHz BATTERYDETECTION Batterydetectioncurrentbeforechargedone Beginsafterterminationdetected, I(DETECT) (sinkcurrent)(1) V(AUXPWR)≤V(OREG) –0.45 mA Batterydetectiontime 262 ms SLEEPCOMPARATOR Sleep-modeentrythreshold, V(SLP) VBUS-VAUXPWR 2.3V≤V(AUXPWR)≤V(OREG),VBUSfalling 0 40 100 mV Sleep-modeexithysteresis 2.3V≤V(AUXPWR)≤V(OREG) 40 100 160 mV V(SLP_EXIT) DV(eSgLPli_tcEhXITti)meforVBUSrisingaboveV(SLP)+ Risingvoltage,2-mVoverdrive,tRISE=100ns 30 ms UNDERVOLTAGELOCKOUT UVLO ICactivethresholdvoltage VBUSrising 3.05 3.3 3.55 V UVLO(HYS) ICactivehysteresis VBUSfallingfromaboveUVLO 120 150 mV PWM VoltagefromBOOTpintoSWpin Duringchargeorboostoperation 6.5 V InternaltopreverseblockingMOSFET on-resistance IIN(LIMIT)=500mA,MeasuredfromVBUStoPMID 180 250 InternaltopN-channelSwitchingMOSFET on-resistance MeasuredfromPMIDtoSW,VBOOT-VSW=4V 120 250 mΩ InternalbottomN-channelMOSFET MeasuredfromSWtoPGND 110 200 on-resistance f(OSC) Oscillatorfrequency 3 MHz Frequencyaccuracy –10% 10% D(MAX) Maximumdutycycle 99.5% D(MIN) Minimumdutycycle 0 Synchronousmodetonon-synchronousmode transitioncurrentthreshold(2) LowsideMOSFETcyclebycyclecurrentsensing 100 mA (1) Negativechargecurrentmeansthechargecurrentflowsfromthebatterytocharger(dischargingbattery). (2) BottomN-channelMOSFETalwaysturnsonforⅩ60nsandthenturnsoffifcurrentistoolow. Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):bq24150Abq24151A

bq24150A Not Recommended For New Designs bq24151A SLUS931A–APRIL2009–REVISEDJANUARY2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) CircuitofFigure1,VBUS=5V,HZ_MODE=0,OPA_MODE=0(chargermodeoperation),T =0°Cto125°C,T =25°Cfor J J typicalvalues(unlessotherwisenoted) PARAMETER TESTCONDITIONS MIN TYP MAX UNIT CHARGEMODEPROTECTION ThresholdoverVBUStoturnoffconverterduring InputVBUSOVPthresholdvoltage 6.3 6.5 6.7 V V(OVP-IN) charge V(OVP_IN)hysteresis VBUSfallingfromaboveV(OVP_IN) 140 mV V(OVP) OutputOVPthresholdvoltage Vdu(CrSinOgUTc)htahrrgeesholdoverV(OREG)toturnoffcharger 110 117 121 %V (OREG) V(OVP)hysteresis LowerlimitforV(CSOUT)fallingfromaboveV(OVP) 11 I(LIMIT) Cycle-by-cyclecurrentlimitforcharge Chargemodeoperation 1.5 2.3 3 A Short-circuitvoltagethreshold V(AUXPWR)falling 1.9 2 2.1 V V(SHORT) V(SHORT)hysteresis V(AUXPWR)risingfrombelowV(SHORT) 100 mV I(SHORT) Short-circuitcurrent V(AUXPWR)≤V(SHORT) 5 10 15 mA BOOSTMODEOPERATIONFORVBUS(OPA_MODE=1,HZ_MODE=0) V(BUS_B) Boostoutputvoltage(toVBUSpin) 2.5V<V(AUXPWR)<4.5V,Openloop 5.05 V Boostoutputvoltageaccuracy Includinglineandloadregulation –3% 3% I(BO) Maximumoutputcurrentforboost V(BUS_B)=5.05V,2.5V<V(AUXPWR)<4.5V 200 mA I(BLIMIT) Cyclebycyclecurrentlimitforboost V(BUS_B)=5.05V,2.5V<V(AUXPWR)<4.5V 1 A Overvoltageprotectionthresholdforboost ThresholdoverVBUStoturnoffconverterduring 5.8 6 6.2 V VBUS(OVP) (VBUSpin) boost VBUS(OVP)hysteresis VBUSfallingfromaboveVBUS(OVP) 125 mV Maximumbatteryvoltageforboost(CSOUT V(BAT)MAX pin) V(CSOUT)risingedgeduringboost 4.75 4.9 5.05 V V(BAT)MAXhysteresis V(CSOUT)fallingfromaboveVBATMAX 200 mV Minimumbatteryvoltageforboost(AUXPWR Duringboosting 2.5 V V(BAT)MIN pin) Beforebooststarts 2.9 3.05 V Outputresistanceathigh-impedancemode HZ_MODE=1 165 kΩ (FromVBUStoPGND) PROTECTION T(SHTDWN) Thermaltrip 165 Thermalhysteresis 10 °C T(CF) Thermalregulationthreshold(3) Chargecurrentbeginstoreduce 120 T(32S) Timeconstantforthe32secondtimer 32Secondmode 12 32 s (3) Verifiedbydesign 6 SubmitDocumentationFeedback Copyright©2009–2010,TexasInstrumentsIncorporated ProductFolderLink(s):bq24150Abq24151A

Not Recommended For New Designs bq24150A bq24151A www.ti.com SLUS931A–APRIL2009–REVISEDJANUARY2010 TYPICAL APPLICATION CIRCUITS VBUS = 5 V, I = 1250 mA, VBAT = 3.5 V to 4.44 V (adjustable), Safety Timer = 32 minutes or 32 (CHARGE) seconds. VBUS LO 1.0mH RSNS VBAT VBUS SW CIN 68 mW CO U1 CBOOT 1mF bq24150A/1A 10mF 10nF PMID BOOT PACK+ CIN 4.7mF CCSIN PGND + VAUX 0.1mF CSIN 10 kW 2 10 kW 10 kW 10 kW I C BUS CSOUT PACK- SCL SCL SDA SDA AUXPWR STAT STAT CAUXPWR VREF OTG OTG CVREF 1mF 10 kW 1mF HOST Figure1. I2CControlled1-CellChargerApplicationCircuit VBUS=5V,I =500mA,V =3.5Vto4.44V(adjustable),SafetyTimer=32minutesor32seconds. (IN_LIMIT) OUT VBUS VBUS SW LO 1.0mH RSNS VOUT Host- CIN 68 mW CO Controlled U1 CBOOT Switch 1mF Bq24150A/1A 10mF 10nF PMID BOOT Q CIN 4.7mF CCSIN 0.1mF VAUX PGND VSYS Host CSIN Charge 10 kW 10 kW10 kW 10 kW I2C BUS CSOUT Controller +PACK+ SCL SCL SDA SDA AUXPWR STAT STAT VREF CAUXPWR CCSOUT PACK- OTG OTG CVREF 1mF 0.1mF 10 kW 1mF HOST Figure2. I2CControlled1-CellPre-RegulatorApplication Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):bq24150Abq24151A

bq24150A Not Recommended For New Designs bq24151A SLUS931A–APRIL2009–REVISEDJANUARY2010 www.ti.com TYPICAL CHARACTERISTICS UsingcircuitshowninFigure1,T =25°C,unlessotherwisespecified. A ADAPTERINSERTION BATTERYINSERTION/REMOVAL VBAT 2 V/div VBUS 2 V/div Vbus =5 V, Iin_limit = 500 mA, 32S Mode VSW VSW 5 V/div 5 V/div Vbus = 0–5 V, Vbat = 3.5 V Charge mode IBAT IBAT 0.5A/div 0.5A/div 500mS/div 1S/div Figure3. Figure4. PWMCHARGINGWAVEFORMS POORSOURCEDETECTION VBUS 2 V/div VSW 2 V/div VSW 5 V/div IL 0.5A/div Vbus = 5 V @ 10 mA, Iin_limit = 100 mA, Vbus = 5 V,Vbat = 2.6 V, Voreg = 4.2 V, Ichg = 1250 mA IBUS Vbat = 3.2 V, Ichg = 550 mA 0.1A/div 100 nS/div 2 mS/div Figure5. Figure6. BATTERYDETECTIONATPOWERUP CYCLEBYCYCLECURRENTLIMITINCHARGEMODE VBUS 5 V/div VIN= 0-5 V, No Battery, COUT= 100mF, RLOAD= 5 kW 2 VV/SdWiv V BAT 1 V/div I OTG L 5 V/div 0.5A/div I Vbus = 5 V, Vbat = 3.6 V Charge mode 50 mA/BdAivT operation 500 mS/div 2mS/div Figure7. Figure8. 8 SubmitDocumentationFeedback Copyright©2009–2010,TexasInstrumentsIncorporated ProductFolderLink(s):bq24150Abq24151A

Not Recommended For New Designs bq24150A bq24151A www.ti.com SLUS931A–APRIL2009–REVISEDJANUARY2010 TYPICAL CHARACTERISTICS (continued) INPUTCURRENTCONTROL CHARGEREFFICIENCY 92 Vbus = 5 V, Iin_limit = 100/500 mA, (OTG Control, 32 Minute Mode), VBUS= 5 V 2 Vbat = 4 V Iin_limit = 100 mA(IC Control, 32 Second Mode) 90 OTG Vbat = 3.6 V 5 V/div 88 % 32 Minute 32 Second y - Mode Mode nc 86 e ci IBUS Effi 84 0.2A/div Vbat = 3 V 82 0.5 S/div 80 0 100 200 300 400 500 600700 800 9001000110012001300 Charge Current - mA Figure9. Figure10. BOOSTWAVEFORM(PWMMODE) BOOSTWAVEFORM(PFMMODE) VBUS 10 mV/div, 5.08 V Offset VBUS 100 mV/div, 5.06 V Offset VBAT10 mV/div, 3.52 V Offset VBAT100 mV/div, 3.5 V Offset VSW VSW 2 V/div 2 V/div IL IL VBAT= 3.5 V, VBUS = 5.06 V, IBUS = 42 mA 0.2A/div 0.2A/div VBAT= 3.5 V, VBUS = 5.07 V, IBUS = 215 mA 100 nS/div 5mS/div Figure11. Figure12. VBUSOVERLOADWAVEFORMS(BOOSTMODE) LOADSTEPUPRESPONSE(BOOSTMODE) VBUS VBUS VBAT= 3.5 V, VBUS = 5.05 V, IBUS = 42 mA 100 mV/div, 5.06 V Offset 2 V/div VPMID VBAT= 3.85 V, VBUS = 5.07 V, IBUS = 0-215 mA 200 mV/div, VBAT 5.02 V Offset 0.2 V/div, 3.8 V Offset VSW 5 V/div VSW 5 V/div I BUS 0.2A/div I BAT 0.1A/div 5 mS/div 100mS/div Figure13. Figure14. Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):bq24150Abq24151A

bq24150A Not Recommended For New Designs bq24151A SLUS931A–APRIL2009–REVISEDJANUARY2010 www.ti.com TYPICAL CHARACTERISTICS (continued) LOADSTEPDOWNRESPONSE(BOOSTMODE) CYCLEBYCYCLECURRENTLIMITINGINBOOSTMODE VBUS Vbat = 3.6 V,Vbus = 4.11 V, Boost mode 100 mV/div, overload operation 5.06 V Offset V VBAT= 3.85 V, VBUS = 5.07 V, IBUS = 215 mA-0 VSW BAT 2 V/div 0.2A/div, 3.8 V Offset VSW 5 V/div IL 0.5A/div I BAT 0.1A/div 100mS/div 200 nS/div Figure15. Figure16. BOOSTTOCHARGEMODETRANSITION(OTGCONTROL) BOOSTEFFICIENCY 95 VBUS 0.5 V/div, VBAT= 4 V 4.5 V Offset OTG 90 VBAT= 3.6 V 2 V/div Vbus = 4.5 V, (Charge Mode)/5.1 V (Boost Mode), % 85 VSW Iin_limit = 500 mA, Vbat = 3.4 V, 32S Mode. cy - VBAT= 2.5 V 5 V/div en Effici 80 IL 0.5A/div 75 0.5 mS/div 70 0 50 100 150 200 Load Current at VBUS - mA Figure17. Figure18. LINEREGULATIONFORBOOST LOADREGULATIONFORBOOST 5.1 5.1 IBUS = 100 mA 5.09 5.09 5.08 IBUS = 200 mA 5.08 5.07 5.07 VBAT= 3.6 V BUS - V 55..0056 S - V 55..0056 VBAT= 4 V V 5.04 BU V 5.04 5.03 IBUS = 50 mA 5.03 5.02 5.02 5.01 VBAT= 2.5 V 5 5.01 4.99 5 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 0 50 100 150 200 VBAT - V Load Current at VBUS - mA Figure19. Figure20. 10 SubmitDocumentationFeedback Copyright©2009–2010,TexasInstrumentsIncorporated ProductFolderLink(s):bq24150Abq24151A

Not Recommended For New Designs bq24150A bq24151A www.ti.com SLUS931A–APRIL2009–REVISEDJANUARY2010 FUNCTIONALBLOCKDIAGRAM(ChargeMode) PMID bq24150A/1A PMID V PMID PMID NMOS NMOS VBUS SW V VBUS BUS SW Q2 CBC Q3 SW Q1 Current I PWM Limiting LIMIT NMOS VREF1 Charge OSC Controller Pump - VOUT + CSOUT + - - IIN_LIMIT VOREG - TCF + VCSIN + TJ - - IOCHARGE CSIN VBUS + VBUS UVLO PWM_CHG VREF VREF - V UVLO REFERNCES BOOT &BIAS VBUS + Poor Input V IN(MIN) V VBUS + VBUS OVP PMID - V OVP_IN CHARGE CONTRO,L VBAT TIMER and DISPLAY VREF TJ + Thermal LOGIC I - Shutdown SHORT T SHTDWN AUXPWR VOUT + *Battery OVP LINEAR_CHG V - OVP VBAT + * Sleep STAT - V BUS V -V OREG RCH + *Recharge VOUT - OTG Termination V OUT - PPGGNNDD VITCESRIMN +- * (I2DCe Ccoodnetrrol) SCL PGND DAC SDA VBAT + * PWM Charge - Mode V SHORT * Signal Deglitched Figure21. FunctionBlockDiagramofbq24150A/1AinChargeMode Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLink(s):bq24150Abq24151A

bq24150A Not Recommended For New Designs bq24151A SLUS931A–APRIL2009–REVISEDJANUARY2010 www.ti.com FUNCTIONALBLOCKDIAGRAM(BoostMode) PMID bq24150A/1A PMID V PMID PMID NMOS NMOS VBUS SW V VBUS BUS SW Q2 CBC SW Q1 Current I VREF1 Charge OSC PWM Limiting BLIMIT Controller Q3 Pump CSOUT NMOS - PFM Mode 75mA CSIN + + + VBUS_FB - VREF VREF - I BO V BUS_FB REFERNCES PWM_BOOST BOOT &BIAS VBUS + VBUS OVP - VREF1 V BUSOVP V PMID TJ + Thermal - Shutdown T SHTDWN VBAT AUXPWR VOUT + *Battery OVP CHARGE CONTROL, TIMER and DISPLAY - STAT VBATMAX LOGIC VBAT + * Low Battery OTG - V BATMIN PGND (I2C Control) SCL PGND * Signal Deglitched Decoder DAC SDA PGND Figure22. FunctionBlockDiagramofbq24150A/1AinBoostMode 12 SubmitDocumentationFeedback Copyright©2009–2010,TexasInstrumentsIncorporated ProductFolderLink(s):bq24150Abq24151A

Not Recommended For New Designs bq24150A bq24151A www.ti.com SLUS931A–APRIL2009–REVISEDJANUARY2010 OPERATIONALFLOWCHART Power Up VAUXPWR<VLOWV No High Impedance Modeor Host VBUS>VUVLO andbq24150A? Controlled Operation Mode POR Load I2C Registers Yes with Default Value Reset and Start 32-MinuteTimer Disable Charge /CE=LOW Charge Configure /CE=HIGH AnyChargeState Mode Disable Charge Wait Mode DelayTINT Indnicoatt eG Pooodwer Yes No Enable ISHORT 32-Minute VAUXPWR<VSHORT? Yes Indicate Short VBUS<VIN(MIN)? No TimerExpired? Circuit condition No Regulate Input Current,Charge Current or Voltage Yes Indicate Charge-In- Progress Yes VBUS<VIN(MIN)? Yes Turn Off Charge Indicate Fault Yes /CE=HIGH No Turn Off Charge 32-Minute Enable IDETECTfor No Timer Expired? tDETECT Battery Removed No VAUXPWVRRC<HV?OREG- Yes RPeasreat mCehtaerrgse WDealiat yMToIdNTe Yes VAUXPWR<VSHORT? No No Charge Complete 32-MinuteTimer No Active? Indicate DONE No Yes Yes Termination Enabled and VIATUEXRPMWdRe>tVeOcRteEGd-VRCH Charge Complete VAUXPWR<VOREG- ? VRCH? High Impedance Mode Yes Figure23. OperationalFlowChartofbq24150A/1AinChargeMode Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLink(s):bq24150Abq24151A

bq24150A Not Recommended For New Designs bq24151A SLUS931A–APRIL2009–REVISEDJANUARY2010 www.ti.com DETAILED FUNCTIONAL DESCRIPTION For a current limited power source, such as a USB host or hub, the high efficiency converter is critical in fully using the input power capacity and charging the battery. Due to the high efficiency in a wide range of the input voltage and battery voltage, the switching mode charger is a good choice for high speed charging with less powerlossandbetterthermalmanagement. The bq24150A/1A is a highly integrated synchronous switch-mode charger with bi-directional operation to achieve boost function for USB OTG support, featuring integrated MOSFETs and small external components, targetedatextremelyspace-limitedportableapplicationspoweredby1-cellLi-IonorLi-polymerbatterypack. The bq24150A/1A usually has three operation modes: charge mode, boost mode, and high impedance mode. In charge mode, the bq24150A/1A supports a precision Li-ion or Li-polymer charging system for single-cell applications. In boost mode, bq24150A/1A boosts the battery voltage to VBUS for powering attached OTG devices. In high impedance mode, the bq24150A/1A stops charging or boosting and operates in a mode with low current from VBUS or battery, to effectively reduce the power consumption when the portable device in standby mode. Through the proper control, bq24150A/1A can achieve the smooth transition among different operation modes. CHARGEMODEOPERATION ChargeProfile In charge mode, bq24150A/1A has four control loops to regulate input current, charge current, charge voltage and device junction temperature, as shown in Figure 21. During the charging process, all four loops are enabled and the one that is dominant will take over the control. The bq24150A/1A supports a precision Li-ion or Li-polymer charging system for single-cell applications. Figure 24(a) indicates a typical charge profile without input current regulation loop and it is similar to the traditional CC/CV charge curve, while Figure 24(b) shows a typical charge profile when input current limiting loop is dominant during the constant current mode, and in this case the charge current is higher than the input current so the charge process is faster than the linear chargers. For bq24150A/1A, the input current limits, the charge current, termination current, and charge voltage are all programmableusingI2Cinterface. 14 SubmitDocumentationFeedback Copyright©2009–2010,TexasInstrumentsIncorporated ProductFolderLink(s):bq24150Abq24151A

Not Recommended For New Designs bq24150A bq24151A www.ti.com SLUS931A–APRIL2009–REVISEDJANUARY2010 Precharge Current Regulation Voltage Regulation Phase Phase Phase Regulation Voltage Regulation Current Charge Voltage VSHORT Charge Current Termination ISHORT Precharge Fast Charge (Linear Charge) (PWM Charge) (a) Precharge Current Regulation Voltage Regulation Phase Phase Phase Regulation voltage Charge Voltage VSHORT Charge Current Termination ISHORT Precharge Fast Charge (Linear Charge) (PWM Charge) (b) Figure24. TypicalChargingProfileofbq24150A/1Afor(a)withoutInputCurrentLimit,and(b)withInput CurrentLimit Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLink(s):bq24150Abq24151A

bq24150A Not Recommended For New Designs bq24151A SLUS931A–APRIL2009–REVISEDJANUARY2010 www.ti.com PWMControllerinChargeMode The bq24150A/1A provides an integrated, fixed 3 MHz frequency voltage-mode controller with Feed-Forward function to regulate charge current or voltage. This type of controller is used to help improve line transient response, thereby, simplifying the compensation network used for both continuous and discontinuous current conduction operation. The voltage and current loops are internally compensated using a Type-III compensation scheme that provides enough phase margin for stable operation, allowing the use of small ceramic capacitors withlowESR.Thereisa0.5-VoffsetonthebottomofthePWMramptoallowthedevicetooperatebetween0% to99.5%dutycycles. Thebq24150A/1Ahastwobacktobackcommon-drainN-channelMOSFETsatthehighsideandoneN-channel MOSFET at low side. An input N-MOSFET (Q1) prevents battery discharge when VBUS is lower than VAUXPWR. The second high-side N-MOSFET (Q2) behaves as the switching control switch (see Figure 21). A charge pump circuit is used to provide gate drive for Q1, while a boot strap circuit with an external boot-strap capacitorisusedtoboostupthegatedrivevoltageforQ2. Cycle-by-cycle current limit is sensed through the internal sense MOSFETs for Q2 and Q3. The threshold for Q2 is set to a nominal 2.3-A peak current. The low-side MOSFET (Q3) also has a current limit that decides if the PWM Controller will operate in synchronous or non-synchronous mode. This threshold is set to 100mA and it turns off the low-side N-channel MOSFET (Q3) before the current reverses, preventing the battery from discharging. Synchronous operation is used when the current of the low-side MOSFET is greater than 100mA to minimizepowerlosses. BatteryChargingProcess At the beginning of precharge, while battery voltage is below the V threshold, the bq24150A/1A applies a (SHORT) short-circuitcurrent,I ,tothebattery. (SHORT) When the battery voltage is above V and below V , the charge current ramps up to fast charge (SHORT) (OREG) current, I , or a charge current that corresponds to the input current of I . The slew rate for fast O(CHARGE) (IN_LIMIT) charge current is controlled to minimize the current and voltage over-shoot during transient. Both the input current limit (default at 100 mA), IIN_LIMIT, and fast charge current, I , can be set by the host. Once the O(CHARGE) battery voltage is close to the regulation voltage, V , the charge current is tapered down as shown in (OREG) Figure 24. The voltage regulation feedback occurs by monitoring the battery-pack voltage between the CSOUT and PGND pins. bq24150A/1A is a fixed single-cell voltage version, with adjustable regulation voltage (3.5 V to 4.44V)programmedthroughI2Cinterface. The bq24150A/1A monitors the charging current during the voltage regulation phase. Once the termination threshold, ITERM, is detected and the battery voltage is above the recharge threshold, the bq24150A/1A terminates charge. The termination current level is programmable. To disable the charge current termination, the hostcansetthechargeterminationbit(I_Term)ofchargecontrolregisterto0,seetheI2Csectionfordetails. Anewchargecycleisinitiatedwhenoneofthefollowingconditionsisdetected: • ThebatteryvoltagefallsbelowtheV –V threshold. (OREG) (RCH) • VBUSPower-onreset(POR),ifbatteryvoltageisbelowtheV threshold(bq24150Aonly). (LOWV) • CEbittoggleorRESETbitisset(hostcontrolled) SafetyTimerinChargeMode Atthebeginningofchargingprocess,thebq24150A/1Astartsa32-minutetimer(T32min)thatcanbestoppedby anywrite-actionperformedbyhostthroughI2Cinterface.Oncethe32-minutetimerisstopped,a32-secondtimer (T32sec) is automatically started. The 32-second timer can be reset by host using I2C interface. Writing "1" to reset bit of TMR_RST in control register resets the 32-second timer and TMR_RST is automatically set to "0" after the 32-second timer is reset. If the 32-second timer expires, the charge is terminated and charge parametersareresettodefaultvalues.Thenthe32-minutetimerstartsandthechargeresumes. During normal charging process, the bq24150A/1A is normally in 32-second mode with host control, and 32-minute mode without host control using I2C interface. The process repeats until the battery is fully charged. If the 32-minute timer expires, bq24150A/1A turns off the charger and enunciates FAULT on the STATx bits of status register. This function prevents battery over charge if the host fails to reset the safety timer. The safety timer flow chart is shown in Figure 25. Fault condition is cleared by POR and fault status bits can only be updatedafterthestatusbitsarereadoutbythehost. 16 SubmitDocumentationFeedback Copyright©2009–2010,TexasInstrumentsIncorporated ProductFolderLink(s):bq24150Abq24151A

Not Recommended For New Designs bq24150A bq24151A www.ti.com SLUS931A–APRIL2009–REVISEDJANUARY2010 Charge Start StartT32min Reset Charge Yes Timer Parameters T32sec Expired? StartT32sec StopT32min No No Yes Charge T32minActive? Yes Any I2C Write- No T32min No Action? Expired? Host Should Reset T32secTimer Yes Timer Fault (a) Charge Start (From Host Control) Timer Fault T32sec Expired? Yes Stop Charge No Charge Host Should Reset T32secTimer (b) Figure25. TimerFlowChartfor(a)bq24150Aand(b)bq24151AinChargeMode USBFriendlyBoot-UpSequence At power on reset (POR) of VBUS, if the battery voltage is above the weak battery threshold, V , bq24150A (LOWV) operates in a mode dictated by the I2C control registers. If the battery voltage is below V and the host (LOWV) control through I2C interface is lost (32 minute mode), the bq24150A resets all I2C registers with default values and enable the charger with an input current limit dictated by the OTG pin voltage level until the host programs the I2C registers. During this period, the input current limit is 100 mA when the voltage level of OTG pin is low; while the input current limit is 500 mA when the voltage level of OTG pin is high. This feature can revive the deeply discharged cell. The charge process continues even the battery is charged to the regulation voltage (default at 3.54 V) since termination is disabled by default. In another case, if the battery voltage is below V ,butthehostcontrolusingI2Cinterfaceisavailable(32secondmode),thebq24150Aoperatesinamode (LOWV) dictated by control registers. However, at POR of VBUS, bq24151A goes to high impedance mode even the battery voltage is below V and no host control through I2C interface is available. That is the major (LOWV) differencebetweenbq24150Aandbq24151A. Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLink(s):bq24150Abq24151A

bq24150A Not Recommended For New Designs bq24151A SLUS931A–APRIL2009–REVISEDJANUARY2010 www.ti.com InputCurrentLimiting To maximize the charge rate of bq24150A/1A without overloading the USB port, the input current for bq24150A/1A can be limited to 100mA or 500mA which is programmed in the control register or OTG pin. Once the input current reaches the input current limiting threshold, the charge current is reduced to keep the input current from exceeding the programmed threshold. For bq24150A, the default input current limit is controlled by the OTG pin at VBUS power on reset when V is lower than V . The input current sensing resistor (AUXPWR) (LOWV) and control loop are integrated into bq24150A/1A. The input current limit can also be disabled using I2C control, seethedefinitionofcontrolregister(01H)fordetails. ThermalRegulationandProtection To prevent overheating the chip during the charging process, the bq24150A/1A monitors the junction temperature, T , of the die and begins to taper down the charge current once T reaches the thermal regulation J J threshold, T . The charge current is reduced to zero when the junction temperature increases approximately CF 10°C above T . At any state, if T exceeds T , bq24150A/1A suspends charging. At thermal shutdown CF J SHTDWN mode, PWM is turned off and all timers are frozen. Charging resumes when T falls below T by J SHTDWN approximately10°C. InputVoltageProtectioninChargeMode SleepMode The bq24150A/1A enters the low-power sleep mode if the voltage on VBUS pin falls below sleep-mode entry threshold, V + V , and VBUS is still higher than the poor source detection threshold, V (min). This AUXPWR SLP IN feature prevents draining the battery during the absence of VBUS. During sleep mode, both the reverse blocking switchQ1andPWMareturnedoff. InputSourceDetection During the charging process, bq24150A/1A continuously monitors the input voltage, VBUS. If VBUS falls to the low input voltage threshold, V (min), poor input power source is detected. Under this condition, bq24150A/1A IN terminates the charge process, waits for a delay time of T and repeats the charging process, as indicated in INT Figure 23. This unique function provides intelligence to bq24150A/1A and so prevents USB power bus collapsing andoscillationwhenconnectingtoasuspendedUSBport,oraUSB-OTGdevicewithlowcurrentcapability. InputOvervoltageProtection The bq24150A/1A provides a built-in input over-voltage protection to protect the device and other components against damages if the input voltage (Voltage from VBUS to PGND) goes too high. When an input overvoltage condition is detected, bq24150A/1A turns off the PWM converter, sets fault status bits, and sends out fault pulse in STAT pin. Once VBUS drops below the input overvoltage exit threshold, the fault is cleared and charge processresumes. BatteryProtectioninChargeMode OutputOvervoltageProtection The bq24150A/1A provides a built-in overvoltage protection to protect the device and other components against damage if the battery voltage goes too high, as when the battery is suddenly removed. When an overvoltage condition is detected, bq24150A/1A turns off the PWM converter, sets fault status bits and sends out fault pulse in STAT pin. Once V drops to the battery overvoltage exit threshold, the fault is cleared and charge (CSOUT) processbacktonormal. BatteryDetectionDuringNormalCharging For applications with removable battery packs, the bq24150A/1A provides a battery absent detection scheme to reliablydetectinsertionorremovalofbatterypacks. During normal charging process with host control, once the voltage at the AUXPWR pin is above the battery recharge threshold, V – V , and the termination charge current is detected, bq24150A/1A turns off the (OREG) (RCH) charge and enables a discharge current, I , for a period of t , then checks the battery voltage. If the (DETECT) DETECT 18 SubmitDocumentationFeedback Copyright©2009–2010,TexasInstrumentsIncorporated ProductFolderLink(s):bq24150Abq24151A

Not Recommended For New Designs bq24150A bq24151A www.ti.com SLUS931A–APRIL2009–REVISEDJANUARY2010 battery voltage is still above recharge threshold, the battery is present and the charge done is detected. However, if the battery voltage is below battery recharge threshold, the battery is absent. Under this condition, the charge parameters (such as input current limit) are reset to the default values and charge resumes after a delay of T , as shown in Figure 23. This function ensures that the charge parameters are reset whenever the INT batteryisreplaced. BatteryDetectionatPowerUp The bq24150A has a unique battery detection scheme during the start up of the charger. At VBUS power up, if the timer is in 32-minute mode, the bq24150A starts a 32ms timer when exiting from short circuit mode to PWM charge mode. If the battery voltage is charged to recharge threshold (V – V ) and the 32ms timer is not (OREG) (RCH) expiredyet,thebq2150Adeterminesthatthebatteryisnotpresent;thenstopschargingandimmediatelygoesto the high impedance mode. However, if the 32ms timer is expired when the recharge threshold is reached, the chargingprocesscontinuesasinthenormalbatterychargingprocess. BatteryShortProtection During the normal charging process, if the battery voltage is lower than the short-circuit threshold, V , the (SHORT) chargeroperatesinlinearchargemodewithalowerchargerateofI ,asshowninFigure22. (SHORT) ChargeStatusOutput,STATPin The STAT pin is used to indicate operation conditions for bq24150A/1A. STAT is pulled low during charging and EN_STAT bit in control register (00H) is set to "1". Under other conditions, the STAT pin acts as a high impedance (open-drain) output. Under fault conditions, a 128-ms pulse is sent out to notify the host. The status of STAT pin at different operation conditions is summarized in Table 1. The STAT pin can be used to drive an LED orcommunicatetothehostprocessor. Table1.STATPinSummary CHARGESTATE STAT ChargeinprogressandEN_STAT=1 Low Othernormalconditions Open-drain Chargemodefaults:Timerfault,sleepmode,VBUSorbattery 128-mspulse,thenopen-drain overvoltage,poorinputsource,VBUSUVLO,nobattery, thermalshutdown Boostmodefaults:Timerfault,overload,VBUSorbattery 128-mspulse,thenopen-drain overvoltage,lowbatteryvoltage,thermalshutdown ControlBitsinChargeMode CEBit(ChargeMode) The bit of CE in control register is used to disable or enable the charge process. A low logic level (0) on this bit enablesthechargeandahighlogiclevel(1)disablesthecharge. RESETBit ThebitofRESETincontrolregisterisusedtoresetallthechargeparameters.Writing'1"toRESETbitresetsall the charge parameters to default values and RESET bit is automatically cleared to zero once the charge parameters are reset. It is designed for charge parameter reset before charge starts, and it is not recommended tosettheRESETbitwhenchargingorboostinginprogress. OPA_ModeBit OPA_MODE is the operation mode control bit. When OPA_MODE = 0, the bq24150A/1A will go to the charge relatedoperationmodesifHZ_MODEissetto"0",refertoTable2fordetail. Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLink(s):bq24150Abq24151A

bq24150A Not Recommended For New Designs bq24151A SLUS931A–APRIL2009–REVISEDJANUARY2010 www.ti.com Table2.OperationModeSummary OPA_MODE HZ_MODE OPERATIONMODE 0 0 Charge(nofault) Chargeconfigure(fault,V >V ) bus UVLO Highimpedance(V <V ) bus UVLO 1 0 Boost(nofaults) Anyfaultgotochargeconfiguremode X 1 Highimpedance BoostModeOperation In 32 second mode, when the OTG pin is in active status or the bit of operation mode (OPA_MODE) at control register is set to 1, the bq24150A/1A operates in boost mode and delivers the power to VBUS from the battery. At normal boost mode, bq24150A/1A converts the battery voltage (2.5 V to 4.5 V) to VBUS-B (about 5.05 V) and delivers a current as much as I (approximately 200 mA) to support other USB OTG devices connected to the (BO) USBconnector. PWMControllerinBoostMode Similar to charge mode operation, in boost mode, the bq24150A/1A provides an integrated, fixed 3 MHz frequency voltage-mode controller to regulate output voltage at PMID pin (VPMID), as shown in Figure 22. The voltage control loop is internally compensated using a Type-III compensation scheme that provides enough phasemarginforstableoperationwithawideloadrangeandbatteryvoltagerange In boost mode, the input N-MOSFET (Q1) prevents battery discharge when VBUS pin is overloaded. Cycle-by-cyclecurrentlimitissensedthroughtheinternalsenseMOSFETforQ3.Thecycle-by-cyclecurrentlimit threshold for Q3 is set to a nominal 1-A peak current. Synchronous operation is used in PWM mode to minimize powerlosses. BoostStartUp To prevent the inductor saturation and limit the inrush current, a soft-start control is applied during the boost start up. PFMModeatLightLoad In boost mode, the bq2450A/1A operates in pulse skipping mode (PFM mode) to reduce the power loss and improve the converter efficiency at light load condition. During boosting, the PWM converter is turned off once theinductorcurrentislessthan75mA;andthePWMisturnedbackononlywhenthevoltageatPMIDpindrops to about 99.5% of the rated output voltage. A unique pre-set circuit is used to make the smooth transition betweenPWMandPFMmode. SafetyTimerinBoostMode At the beginning of boost operation, the bq24150A/1A starts a 32-second timer that can be reset by host through I2C interface. Writing "1" to reset bit of TMR_RST in the control register resets the 32-second timer and TMR_RST is automatically set to "0" after the 32-second timer is reset. To keep in boost mode, the host must reset the 32-second timer repeatedly. Once the 32-second timer expires, the bq24150A/1A turns off the boost converter, enunciate the fault pulse in STAT pin and set fault status bits in status register. Fault condition is clearedbyPORorhostcontrol. ProtectioninBoostMode OutputOvervoltageProtection The bq24150A/1A provides a built-in overvoltage protection to protect the device and other components against damage if the VBUS voltage goes too high. When an overvoltage condition is detected, the bq24150A/1A turns off the PWM converter, reset OPA_MODE bit to 0, sets fault status bits, and sends out fault pulse in STAT pin. Once VBUS drops to the normal level, the boost starts after host sets OPA_MODE to "1", or the OTG pin remainsinactivestatus. 20 SubmitDocumentationFeedback Copyright©2009–2010,TexasInstrumentsIncorporated ProductFolderLink(s):bq24150Abq24151A

Not Recommended For New Designs bq24150A bq24151A www.ti.com SLUS931A–APRIL2009–REVISEDJANUARY2010 OutputOverloadProtection The bq24150A/1A provides a built-in overload protection to prevent the device and battery from damage when VBUSisoverloaded.Onceoverloadconditionisdetected,Q1operatesinlinearmodetolimittheoutputcurrent whileVPMIDkeepsinvoltageregulation.Iftheoverloadconditionlastsformorethan30ms,theoverloadfaultis detected. When an overload condition is detected, the bq24150A/1A turns off the PWM converter, reset OPA_MODEbitto0,setsfaultstatusbits,andsendsoutfaultpulseinSTATpin.Theboostwillnotstartuntilthe hostclearsthefaultregister. BatteryVoltageProtection Duringboosting,whenbatteryvoltageisabovethebatteryovervoltagethreshold,V ,orbelowtheminimum (BATMX) battery voltage threshold, V min, the bq24150A/1A turns off the PWM converter, reset OPA_MODE bit to 0, (BAT) sets fault status bits, and sends out fault pulse in STAT pin. Once battery voltage goes back to the normal level, thebooststartsafterhostsetsOPA_MODEto"1",ortheOTGpinremainsinactivestatus. STATPinBoostMode During normal boosting process, the STAT pin behaves as a high impedance (open-drain) output. Under fault conditions,a128-mspulseissentouttonotifythehost. HighImpedanceMode When control bit of HZ-MODE is set to "1" and the OTG pin is not in active status, the bq24150A/1A operates in high impedance mode, with the impedance in VBUS pin higher than 165 kΩ. In high impedance mode, a crude 32-second timer is enabled when the battery voltage is below V to monitor the host control is available or (LOWV) not. If the crude 32 second timer expires, the bq24150A/1A operates in 32 minute mode and the crude 32 second timer is disabled. In 32 minute mode, when VBUS is below UVLO, the bq24150A/1A operates in high impedancemoderegardlessofthesettingoftheHZ_MODEbit. OutputInductorandCapacitanceSelectionGuidelines The bq24150A/1A provides internal loop compensation. With this scheme, the best stability occurs when the LC resonant frequency, ƒ , is approximately 40 kHz (20 kHz to 80 kHz). Equation 1 is used to calculate the value of o theoutputinductor,L ,andoutputcapacitor,C . OUT OUT 1 fo = 2p ´ LOUT ´ COUT (1) To reduce the output voltage ripple, a ceramic capacitor with the capacitance between 4.7 mF and 47 mF is recommendedforC ,seetheapplicationsectionforcomponentsselection. OUT Pre-RegulatorApplication Figure2showsatypicalpre-regulatorapplicationthatthebq24150A/1AoperatesasaDC/DCconverter,withthe termination disabled. In this application, the host charge controller controls switch Q to achieve pulse-charging function, and bq24150A/1A converts the input voltage to the lower output voltage (V ). The robust internal OREG compensation design ensures the stable operation when the host-controlled switch Q is turned off. With the input overvoltage protection, output current regulation and high efficiency power conversion, the bq24150A/1A is an idealchoiceforpre-regulatorusedinpulsechargingapplications. StateMachineTableandStateDiagram Based on the previously-described operation modes, the definitions of all operation states are shown in Table 3 andTable4,whereastherelationshipamongdifferentstatesisshowninFigure26. Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLink(s):bq24150Abq24151A

bq24150A Not Recommended For New Designs bq24151A SLUS931A–APRIL2009–REVISEDJANUARY2010 www.ti.com Table3.StateMachineTable1ofbq24150A/1A MODE POWERDOWN CHARGECONFIGURE SHORTCIRCUIT PWMCHARGE OPA_MODE=0 HZ_MODE=0 OPA_MODE=0 OPA_MODE=0 OTGInactive HZ_MODE=0 HZ_MODE=0 V >V OTGInactive OTGInactive V <V BUS UVLO INCondition BUS UVLO V <V V >V V >V V <V BUS BUS(MIN) BUS BUS(MIN) BUS BUS(MIN) (AUXPWR) (SHORT) or V <V V >V (AUXPWR) (SHORT) (AUXPWR) (SHORT) CE=HIGH CE=Low CE=Low or NoFaults NoFaults FaultsDuringCharge OPA_MODE=1 OPA_MODE=1 orHZ_MODE=1 orHZ_MODE=1 OPA_MODE=1 orV <V orV <V V >V orHZ_MODE=1 BUS BUS(MIN) BUS BUS(MIN) OUTCondition BUS UVLO orV >V orV <V orV >V orV <V (AUXPWR) (SHORT) (AUXPWR) (SHORT) (AUXPWR) (SHORT) BUS UVLO orCE=HIGH orCE=HIGH orOTGActive orFaults orFaults orOTGActive orOTGActive I2C Off On On On Buck Off Off Off On I Off Off On Off (SHORT) Boost Off Off Off Off Q1 Off On/Off On On Note PORwhenout Table4.StateMachineTable2ofbq24150A/1A MODE HIGHIMPEDANCE BOOSTCONFIGURE BOOST HZ_MODE=0 HZ_MODE=0 HZ_MODE=1 (OPA_MODE=1 (OPA_MODE=1orOTGactive) or INCondition orOTGactive) V >V V <V and (AUXPWR) (BATMIN) BUS UVLO V >V StartUpFinished V >V (AUXPWR) (BATMIN) (AUXPWR) (SHORT) ReadyToStartUp NoFaults HZ_MODE=1orOPA_MODE=0 (OPA_MODE=0andOTGInactive) OUTCondition HZ_MODE=0orOTGActive orV >V or(HZ_MODE=1andOTGInactive) (AUXPWR) (BATMIN) orBoostStartUpFinished orV <V orFaults (AUXPWR) (BATMIN) I2C On On On Buck Off Off Off I Off Off Off (SHORT) Boost Off Off On Q1 Off On/Off(1) On (1) Q1isOFFwhenVBUSisshortedtoground. 22 SubmitDocumentationFeedback Copyright©2009–2010,TexasInstrumentsIncorporated ProductFolderLink(s):bq24150Abq24151A

Not Recommended For New Designs bq24150A bq24151A www.ti.com SLUS931A–APRIL2009–REVISEDJANUARY2010 VBUS<VUVLO VBUS>VUVLO ANYSTATE VAUXPWR<VSHORT POWER DOWN VAUXPWR<VLOWV (bq24150A) VAUXPWR>VSHORT VBUS<VUVLO HZ_MODE=1 or VBUS<VUVLO,VAUXPWR>VSHORT HIGH VBUS>VUVLO CHARGE IMPEDANCE HZ_MODE=0,OPA_MODE=0 CONFIGURE HZ_MODE=1 OPA_MODE=1 HZ_MODE=1 HZ_MODE=0 Or OHPZA__MMOODDEE==01 VAUXPWR<VLOWV oVrA VUXBPUWS<R>VVBUSSH(OMRINT) VAUXPWR>VLOWV or FAULTS OPA_MODE=0 VAUXPWR<VSHORT HZ_MODE=1 BOOST VNBUOS >FVABUUSL(TMISN) or CONFIGURE VAUXPWR<VSHORT SHORT VAUXPWR<VBATMIN OPA_MODE=1 or VBUS<VBUS(MIN) CIRCUIT HZ_MODE=0 or FAULTS STARTUP No FAULTS VAUXPWR>VSHORT,VBUS>VBUS(MIN) PWM CHARGE NO FAULTS BOOST OPA_MODE=0 or FAULTS Figure26. StateDiagramforbq24150A/1A SERIAL INTERFACE DESCRIPTION I2C™ is a 2-wire serial interface developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1, January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I2C compatible devices connect to the I2C bus through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A slave device receivesand/ortransmitsdataonthebusundercontrolofthemasterdevice. The bq24150A/1A device works as a slave and supports the following data transfer modes, as defined in the I2C-Bus™Specification:standardmode(100kbps),fastmode(400kbps),andhigh-speedmode(upto3.4Mbps in write mode). The interface adds flexibility to the battery charge solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements. Register contents remain intact as long as supply voltage remains above 2.2 V (typical). I2C is asynchronous, which means that it runs off of SCL. The device has no noise or glitch filtering on SCL, so SCL input needs to be clean. Therefore, it is recommendedthatSDAchangeswhileSCLisLOW. The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as the F/S-modeinthisdocument.Theprotocolforhigh-speedmodeisdifferentfromtheF/S-mode,anditisreferredto astheHS-mode.Thebq24150A/1Adeviceonlysupports7-bitaddressing.Thedevice7-bitaddressisdefinedas ‘1101011’(6BH). F/SModeProtocol The master initiates data transfer by generating a start condition. The start condition is when a high-to-low transition occurs on the SDA line while SCL is high, as shown in Figure 27. All I2C-compatible devices should recognizeastartcondition. Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLink(s):bq24150Abq24151A

bq24150A Not Recommended For New Designs bq24151A SLUS931A–APRIL2009–REVISEDJANUARY2010 www.ti.com DATA CLK S P START Condition STOPCondition Figure27. STARTandSTOPCondition The master then generates the SCL pulses, and transmits the 8-bit address and the read/write direction bit R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 28). All devices recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a matching address generates an acknowledge (see Figure 28) by pulling the SDA line low during the entire high periodoftheninthSCLcycle.Upondetectingthisacknowledge,themasterknowsthatcommunicationlinkwitha slavehasbeenestablished. DATA CLK Data Line Change Stable; of Data Data Valid Allowed Figure28. BitTransferontheSerialInterface The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an acknowledge signal can either be generated by the master or by the slave, depending on which one is the receiver. the 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to high while the SCL line is high (see Figure 30). This releases the bus and stops the communication linkwiththeaddressedslave.AllI2Ccompatibledevicesmustrecognizethestopcondition.Uponthereceiptofa stop condition, all devices know that the bus is released, and wait for a start condition followed by a matching address. If a transaction is terminated prematurely, the master needs sending a STOP condition to prevent the slave I2C logic from remaining in a bad state. Attempting to read data from register addresses not listed in this sectionwillresultinFFhbeingreadout. 24 SubmitDocumentationFeedback Copyright©2009–2010,TexasInstrumentsIncorporated ProductFolderLink(s):bq24150Abq24151A

Not Recommended For New Designs bq24150A bq24151A www.ti.com SLUS931A–APRIL2009–REVISEDJANUARY2010 Data Output by Transmitter NotAcknowledge Data Output by Receiver Acknowledge SCLFrom 1 2 8 9 Master Clock Pulse for START Acknowledgement Condition Figure29. AcknowledgeontheI2CBus™ Recognize START or Recognize STOPor REPRATED START REPRATED START Condition Condition GenerateACKNOWLEDGE Signal P SDA MSB Acknowledgement Sr Signal From Slave Address R/W SCL S Sr or ACK ACK or Sr P Clock Line Held Low While Interrupts are Serviced Figure30. BusProtocol H/SModeProtocol Whenthebusisidle,bothSDAandSCLlinesarepulledhighbythepull-updevices. The master generates a start condition followed by a valid serial byte containing HS master code '00001XXX'. This transmission is made in F/S mode at no more than 400 Kbps. No device is allowed to acknowledge the HS mastercode,butalldevicesmustrecognizeitandswitchtheirinternalsettingtosupport3.4-Mbpsoperation Themasterthengeneratesarepeatedstartcondition(arepeatedstartconditionhasthesametimingasthestart condition). After this repeated start condition, the protocol is the same as F/S mode, except that transmission speeds up to 3.4 Mbps are allowed. A stop condition ends the HS mode and switches all the internal settings of the slave devices to support the F/S mode. Instead of using a stop condition, repeated start conditions should be used to secure the bus in HS mode. If a transaction is terminated prematurely, the master needs sending a STOPconditiontopreventtheslaveI2Clogicfromremaininginabadstate. AttemptingtoreaddatafromregisteraddressesnotlistedinthissectionresultsinFFhbeingreadout. Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLink(s):bq24150Abq24151A

bq24150A Not Recommended For New Designs bq24151A SLUS931A–APRIL2009–REVISEDJANUARY2010 www.ti.com bq24150A/1AI2CUpdateSequence The bq24150A/1A requires a start condition, a valid I2C address, a register address byte, and a data byte for a single update. After the receipt of each byte, bq24150A/1A device acknowledges by pulling the SDA line low during the high period of a single clock pulse. A valid I2C address selects the bq24150A/1A. The bq24150A/1A performsanupdateonthefallingedgeoftheacknowledgesignalthatfollowstheLSBbyte. For the first update, bq24150A/1A requires a start condition, a valid I2C address, a register address byte, a data byte. For all consecutive updates, bq24150A/1A needs a register address byte, and a data byte. Once a stop conditionisreceived,thebq24150A/1AreleasestheI2Cbus,andawaitsanewstartconditions. S SLAVEADDRESS R/W A REGISTERADDRESS A DATA P A/A DataTransferred ‘0’(Write) (nBytes +Acknowledge) From master tobq24150 A =Acknowledge (SDALOW) A =Not acknowledge (SDA HIGH) Frombq24150/1 to master S = START condition Sr = Repeated START condition P = STOPcondition (a) F/S-Mode F/S-Mode HS-Mode F/S-Mode S HS-MASTER CODE Sr SLAVEADDRESS R/W A REGISTERADDRESS A DATA P A A/A DataTransferred ‘0’(write) (nBytes +Acknowledge) HS-Mode Continues Sr SlaveA. (b) HS-Mode Figure31. DataTransferFormatinF/SModeandH/SMode SlaveAddressByte MSB LSB X 1 1 0 1 0 1 1 The slave address byte is the first byte received following the START condition from the master device. The addressbitsarefactorypresetto‘1101011’. RegisterAddressByte MSB LSB 0 0 0 0 0 D2 D1 D0 Following the successful acknowledgment of the slave address, the bus master will send a byte to the bq24150A/1A, which contains the address of the register to be accessed. The bq24150A/1A contains five 8-bit registers accessible via a bidirectional I2C-bus interface. Among them, four internal registers have read and write access;andonehasonlyreadaccess. 26 SubmitDocumentationFeedback Copyright©2009–2010,TexasInstrumentsIncorporated ProductFolderLink(s):bq24150Abq24151A

Not Recommended For New Designs bq24150A bq24151A www.ti.com SLUS931A–APRIL2009–REVISEDJANUARY2010 I2C INTERFACE TIMING CHARACTERISTICS SYMBOL PARAMETER TESTCONDITIONS MIN TYP MAX UNIT Standardmode 100 kHz Fastmode 400 kHz High-speedmode(writeoperation) 3.4 CB-100pFmax fSCL SCLclockfrequency High-speedmode(readoperation) 2 CB-100pFmax MHz High-speedmode(writeoperation) 1.7 CB-400pFmax High-speedmode(readoperation) 2 CB-400pFmax BusfreetimebetweenaSTOPand Standardmode 4.7 t ms BUF STARTcondition Fastmode 1.3 Standardmode 4 ms Holdtime(repeated)START t ;t Fastmode 600 HD STA condition ns High-speedmode 160 Standardmode 4.7 ms Fastmode 1.3 t LOWperiodoftheSCLclock LOW High-speedmode,C –100pFmax 160 B ns High-speedmode,C –400pFmax 320 B Standardmode 4 ms Fastmode 600 t HIGHperiodoftheSCLclock HIGH High-speedmode,C –100pFmax 60 ns B High-speedmode,C –400pFmax 120 B Standardmode 4.7 ms SetuptimeforarepeatedSTART t ;t Fastmode 600 SU STA condition ns High-speedmode 160 Standardmode 250 t ;t Datasetuptime Fastmode 100 ns SU DAT High-speedmode 10 Standardmode 3.45 ms Fastmode 0.9 t ;t Dataholdtime HD DAT High-speedmode,C –100pFmax 70 B ns High-speedmode,C –400pFmax 150 B Standardmode 20+0.1C 1000 B Fastmode 20+0.1C 300 B t RisetimeofSCLsignal ns RCL High-speedmode,C –100pFmax 10 40 B High-speedmode,C –400pFmax 20 80 B Standardmode 20+0.1C 1000 B RisetimeofSCLsignalaftera Fastmode 20+0.1C 300 B t repeatedSTARTconditionandafter ns RCL1 anacknowledgebit High-speedmode,CB–100pFmax 10 80 High-speedmode,C –400pFmax 20 160 B Standardmode 20+0.1C 300 B Fastmode 20+0.1C 300 B t FalltimeofSCLsignal ns FCL High-speedmode,C –100pFmax 10 40 B High-speedmode,C –400pFmax 20 80 B Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLink(s):bq24150Abq24151A

bq24150A Not Recommended For New Designs bq24151A SLUS931A–APRIL2009–REVISEDJANUARY2010 www.ti.com SYMBOL PARAMETER TESTCONDITIONS MIN TYP MAX UNIT Standardmode 20+0.1C 1000 B Fastmode 20+0.1C 300 B t RisetimeofSDAsignal ns RDA High-speedmode,C –100pFmax 10 80 B High-speedmode,C –400pFmax 20 160 B Standardmode 20+0.1C 300 B Fastmode 20+0.1C 300 B t FalltimeofSDAsignal ns FDA High-speedmode,C –100pFmax 10 80 B High-speedmode,C –400pFmax 20 160 B Standardmode 4 ms t ;t SetuptimeforSTOPcondition Fastmode 600 SU STO ns High-speedmode 160 C CapacitiveloadforSDAandSCL 400 pF B I2C Timing Diagrams SDA tf tLOW tr tSU;DAT tf tHD;STA tSP tr tBUF SCL S tHD;STA tHD;DAT tHIGH tSU;STA Sr tSU;STO P S Figure32. SerialInterfaceTimingforF/SMode Sr Sr P t t rDA fDA SDAH t t HD;DAT SU;STO t SU;STA t t HD;STA SU;DAT SCLH t fCL1 (1) t t t rCL1 rCL1 rCL1 (1) tHIGH tLOW tLOW tHIGH = MCS current source pull-up = R resister pull-up P Figure33. SerialInterfaceTimingforH/SMode 28 SubmitDocumentationFeedback Copyright©2009–2010,TexasInstrumentsIncorporated ProductFolderLink(s):bq24150Abq24151A

Not Recommended For New Designs bq24150A bq24151A www.ti.com SLUS931A–APRIL2009–REVISEDJANUARY2010 REGISTER DESCRIPTION Table5.Status/ControlRegister(Read/Write) MemoryLocation:00,ResetState:x1xx0xxx BIT NAME READ/WRITE FUNCTION Write:TMR_RSTfunction,write"1"toresetthesafetytimer(autoclear) B7(MSB) TMR_RST/OTG Read/Write Read:OTGpinstatus,0-OTGpinatLowlevel,1-OTGpinatHighlevel B6 EN_STAT Read/Write 0-DisableSTATpinfunction,1-EnableSTATpinfunction(default1) B5 STAT2 ReadOnly 00-Ready,01-Chargeinprogress,10-Chargedone,11-Fault B4 STAT1 ReadOnly B3 BOOST ReadOnly 1-Boostmode,0-Notinboostmode B2 FAULT_3 ReadOnly Chargemode:000-Normal,001-VBUSOVP,010-Sleepmode,011-Poorinputsourceor VBUS<UVLO,100-OutputOVP,101-Thermalshutdown,110-Timerfault,111-No B1 FAULT_2 ReadOnly battery Boostmode:000-Normal,001-VBUSOVP,010-Overload,011-Batteryvoltageistoo B0(LSB) FAULT_1 ReadOnly low,100-BatteryOVP,101-Thermalshutdown,110-Timerfault,111-NA Table6.ControlRegister(Read/Write) MemoryLocation:01,ResetState:00110000(30H) BIT NAME READ/WRITE FUNCTION B7(MSB) Iin_Limit_2 Read/Write 00-USBhostwith100-mAcurrentlimit,01-USBhostwith500-mAcurrentlimit, B6 Iin_Limit_1 Read/Write 10-USBhost/chargerwith800-mAcurrentlimit,11-Noinputcurrentlimit(default00) B5 V (1) Read/Write 200mVweakbatteryvoltagethreshold(default1) (LOWV_2) B4 VLOWV_1(1) Read/Write 100mVweakbatteryvoltagethreshold(default1) B3 TE Read/Write 1-Enablechargecurrenttermination,0-Disablechargecurrenttermination(default0) B2 CE Read/Write 1-Chargerisdisabled,0-Chargerenabled(default0) B1 HZ_MODE Read/Write 1-Highimpedancemode,0-Nothighimpedancemode(default0) B0(LSB) OPA_MODE Read/Write 1-Boostmode,0-Chargermode(default0) (1) Therangeoftheweakbatteryvoltagethreshold(V )is3.4Vto3.7Vwithanoffsetof3.4Vandstepof100mV(default3.7V). (LOWV) Table7.Control/BatteryVoltageRegister(Read/Write) MemoryLocation:02,ResetState:00001010(0AH) BIT NAME READ/WRITE FUNCTION B7(MSB) V Read/Write BatteryRegulationVoltage:640mV(default0) O(REG5) B6 V Read/Write BatteryRegulationVoltage:320mV(default0) O(REG4) B5 V Read/Write BatteryRegulationVoltage:160mV(default0) O(REG3) B4 V Read/Write BatteryRegulationVoltage:80mV(default0) O(REG2) B3 V Read/Write BatteryRegulationVoltage:40mV(default1) O(REG1) B2 V Read/Write BatteryRegulationVoltage:20mV(default0) O(REG0) B1 OTG_PL Read/Write 1-ActiveatHighlevel,0-ActiveatLowlevel(default1) B0(LSB) OTG_EN Read/Write 1-EnableOTGPin,0-DisableOTGpin(default0) Chargevoltagerangeis3.5Vto4.44Vwiththeoffsetof3.5Vandstepof20mV(default3.54V). Table8.Vender/Part/RevisionRegister(Readonly) MemoryLocation:03,ResetState:0100x001 BIT NAME READ/WRITE FUNCTION B7(MSB) Vender2 ReadOnly VenderCode:bit2(default0) B6 Vender1 ReadOnly VenderCode:bit1(default1) B5 Vender0 ReadOnly VenderCode:bit0(default0) B4 PN1 ReadOnly PartNumberCode:bit1(default0) B3 PN0 ReadOnly PartNumberCode:bit0(default0forbq24151A,default1forbq24150A) Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLink(s):bq24150Abq24151A

bq24150A Not Recommended For New Designs bq24151A SLUS931A–APRIL2009–REVISEDJANUARY2010 www.ti.com Table8.Vender/Part/RevisionRegister(Readonly) MemoryLocation:03,ResetState:0100x001 (continued) BIT NAME READ/WRITE FUNCTION B2 Revision2 ReadOnly 011:Revision1.3; B1 Revision1 ReadOnly 100-111:FutureRevisions B0(LSB) Revision0 ReadOnly Table9.BatteryTermination/FastChargeCurrentRegister(Read/Write) MemoryLocation:04,ResetState:10001001(89H) BIT NAME READ/WRITE FUNCTION B7(MSB) Reset Read/Write Write:1-Chargerinresetmode,0-Noeffect,Read:alwaysget"1" B6 V Read/Write Chargecurrentsensevoltage:27.2mV(default0) I(CHRG2) B5 V Read/Write Chargecurrentsensevoltage:13.6mV(default0) I(CHRG1) B4 V Read/Write Chargecurrentsensevoltage:6.8mV(default0) I(CHRG0) B3 NA Read/Write NA B2 V Read/Write Terminationcurrentsensevoltage:13.6mV(default0) I(TERM2) B1 V Read/Write Terminationcurrentsensevoltage:6.8mV(default0) I(TERM1) B0(LSB) V Read/Write Terminationcurrentsensevoltage:3.4mV(default1) I(TERM0) Defaultchargecurrentis550mAanddefaultterminationcurrentis100mA,ifa68-mΩ sensingresistorisused. Both the termination current range and charge current range are depending on the sensing resistor R ). The (SNS) terminationcurrentstep(I )iscalculatedusingEquation2: O(TERM_STEP) V I(TERM0) I = O(TERM_STEP) R (SNS) (2) Table10showstheterminationcurrentsettingswithtwosensingresistors. Table10.TerminationCurrentSettingsfor68-mΩ and100-mΩ SenseResistors I (mA) I (mA) BIT V (mV) (TERM) (TERM) I(TERM) R =68mΩ R =100mΩ (SNS) (SNS) V 13.6 200 136 I(TERM2) V 6.8 100 68 I(TERM1) V 3.4 50 34 I(TERM0) Offset 3.4 50 34 Thechargecurrentstep(I )iscalculatedusingEquation3: O(CHARGE_STEP) V I(CHRG0) I = O(CHARGE_STEP) R (SNS) (3) Table11showsthechargecurrentsettingswithtwosensingresistors. Table11.ChargeCurrentSettingsfor68-mΩand100-mΩ SenseResistors I (mA) I (mA) BIT V (mV) O(CHARGE) O(CHARGE) I(REG) R =68mΩ R =100mΩ (SNS) (SNS) V 27.2 400 272 I(CHRG2) V 13.6 200 136 I(CHRG1) V 6.8 100 68 I(CHRG0) Offset 37.4 550 374 30 SubmitDocumentationFeedback Copyright©2009–2010,TexasInstrumentsIncorporated ProductFolderLink(s):bq24150Abq24151A

Not Recommended For New Designs bq24150A bq24151A www.ti.com SLUS931A–APRIL2009–REVISEDJANUARY2010 POWER TOPOLOGIES System Load After Sensing Resistor One of the simple high-efficiency topologies connects the system load directly across the battery pack, as shown in Figure 34. The input voltage has been converted to a usable system voltage with good efficiency from the input. When the input power is on, it supplies the system load and charges the battery pack at the same time. Whentheinputpowerisoff,thebatterypackpowersthesystemdirectly. SW VBUS Isns Isys L1 Rsns Ichg V IN + bq2415xA + System - Load C3 C4 BAT C1 PMID PGND C2 Figure34. SystemLoadAfterSensingResistor Theadvantages: • When the AC adapter is disconnected, the battery pack powers the system load with minimum power dissipations.Consequently,thetimethatthesystemrunsonthebatterypackcanbemaximized. • Itsavestheexternalpathselectioncomponentsandoffersalow-costsolution. • Dynamic power management (DPM) can be achieved. The total of the charge current and the system current can be limited to a desired value by adjusting charge current. When the system current increases, the charge current drops by the same amount. As a result, no potential over-current or over-heating issues are caused byexcessivesystemloaddemand. • The total of the input current can be limited to a desired value by setting input current limit value. So USB specificationscanbemeteasily. • Thesupplyvoltagevariationrangeforthesystemcanbeminimized. • Theinputcurrentsoft-startcanbeachievedbythegenericsoft-startfeatureoftheIC. Designconsiderationsandpotentialissues: • If the system always demands a high current (but lower than the regulation current), the charging never terminates.Thus,thebatteryisalwayscharged,andthelifetimemaybereduced. • Because the total current regulation threshold is fixed and the system always demands some current, the batterymaynotbechargedwithafull-chargerateandthusmayleadtoalongerchargetime. • If the system load current is large after the charger has been terminated, the voltage drop across the battery impedance may cause the battery voltage to drop below the refresh threshold and start a new charge. The charger would then terminate due to low charge current. Therefore, the charger would cycle between charging and terminating. If the load is smaller, the battery has to discharge down to the refresh threshold, resultinginamuchslowercycling. • In a charger system, the charge current is typically limited to about 10mA, if the sensed battery voltage is below 2V short circuit protection threshold. This results in low power availability at the system bus. If an externalsupplyisconnectedandthebatteryisdeeplydischarged,belowtheshortcircuitprotectionthreshold, the charge current is clamped to the short circuit current limit. This then is the current available to the system during the power-up phase. Most systems cannot function with such limited supply current, and the battery supplements the additional power required by the system. Note that the battery pack is already at the depletedcondition,anditdischargesfurtheruntilthebatteryprotectoropens,resultinginasystemshutdown. • If the battery is below the short circuit threshold and the system requires a bias current budget lower than the short circuit current limit, the end-equipment will be operational, but the charging process can be affected depending on the current left to charge the battery pack. Under extreme conditions, the system current is Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLink(s):bq24150Abq24151A

bq24150A Not Recommended For New Designs bq24151A SLUS931A–APRIL2009–REVISEDJANUARY2010 www.ti.com close to the short circuit current levels and the battery may not reach the fast-charge region in a timely manner. As a result, the safety timers flag the battery pack as defective, terminating the charging process. Because the safety timer cannot be disabled, the inserted battery pack must not be depleted to make the applicationpossible. • For instance, if the battery pack voltage is too low, highly depleted, or totally dead or even shorted, the systemvoltageisclampedbythebatteryanditcannotoperateeveniftheinputpowerison. System Load Before Sensing Resistor Thesecondcircuitisverysimilartofirstone;thedifferenceisthatthesystemloadisconnectedbeforethesense resistor,asshowninFigure35. Isys SW VBUS Isns L1 Rsns Ichg V IN + bq2415xA + System - Load C3 C4 BAT C1 PMID PGND C2 Figure35. SystemLoadBeforeSensingResistor Theadvantagesofsystemloadbeforesensingresistortosystemloadaftersensingresistor: • The charger controller is based only on the current goes through the current-sense resistor. So, the constant current fast charge and termination functions work well, and are not affected by the system load. This is the majoradvantageofit. • Adepletedbatterypackcanbeconnectedtothechargerwithouttheriskofthesafetytimerexpirationcaused byhighsystemload. • The charger can disable termination and keep the converter running to keep battery fully charged, or let the switcherterminatewhenthebatteryisfullandthenrunoffofthebatteryviathesenseresistor. Designconsiderationsandpotentialissues: • The total current is limited by the IC input current limit, or peak current protection, or the thermal regulation but not the charge current setting. The charge current does not drop when the system current load increases untiltheinputcurrentlimitisreached.Thissolutionisnotapplicableifthesystemrequiresahighcurrent. • Efficiencydeclineswhendischargingthroughthesenseresistortothesystem. DESIGN EXAMPLE FOR TYPICAL APPLICATION CIRCUITS SystemsDesignSpecifications: • VBUS=5V • V =4.2V(1-Cell) (BAT) • I =1.25A (charge) • Inductorripplecurrent=30%offastchargecurrent 1. Determinetheinductorvalue(L )forthespecifiedchargecurrentripple: OUT VBAT ´ (VBUS -VBAT) L = OUT VBUS ´ f ´ DI L , the worst case is when battery voltage is as close as to half of the input voltage. 32 SubmitDocumentationFeedback Copyright©2009–2010,TexasInstrumentsIncorporated ProductFolderLink(s):bq24150Abq24151A

Not Recommended For New Designs bq24150A bq24151A www.ti.com SLUS931A–APRIL2009–REVISEDJANUARY2010 2.5 ´ (5-2.5) L = OUT 6 5 ´ (3 ´ 10 ) ´ 1.25 ´ 0.3 (4) L =1.11mH OUT Selecttheoutputinductortostandard1mH.Calculatethetotalripplecurrentwithusingthe1-mHinductor: VBAT ´ (VBUS - VBAT) DI = L VBUS ´ f ´ L OUT (5) 2.5 ´ (5 - 2.5) DI = L 6 -6 5 ´ (3 ´ 10 ) ´ (1 ´ 10 ) (6) ΔI =0.42A L Calculatethemaximumoutputcurrent: DI L I = I + LPK OUT 2 (7) 0.42 I = 1.25 + LPK 2 (8) I =1.46A LPK Select 2.5mm by 2.0mm 1-mH 1.5-A surface mount multi-layer inductor. The suggested inductor part numbersareshownasfollowing. Table12.InductorPartNumbers PARTNUMBER INDUCTANCE SIZE MANUFACTURER LQM2HPN1R0MJ0 1mH 2.5x2.0mm muRata MIPS2520D1R0 1mH 2.5x2.0mm FDK MDT2520-CN1R0M 1mH 2.5x2.0mm TOKO CP1008 1mH 2.5x2.0mm Inter-Technical 2. DeterminetheoutputcapacitorvalueC using40kHzastheresonantfrequency: OUT 1 fo = 2p ´ LOUT ´ COUT (9) 1 COUT = 4p2 ´ f02 ´ LOUT (10) 1 COUT = 4p2 ´ (40 ´ 103)2 ´ (1 ´ 10-6) (11) C =15.8mF OUT Selecttwo0603X5R6.3V10-mFceramiccapacitorsinparalleli.e.,muRataGRM188R60J106M. 3. Determinethesenseresistorusingthefollowingequation: V (RSNS) R = (SNS) I (CHARGE) (12) The maximum sense voltage across sense resistor is 85 mV. In order to get a better current regulation accuracy,V shouldequal85mV,andcalculatethevalueforthesenseresistor. (RSNS) 85mV R(SNS) = 1.25A (13) R =68mΩ (SNS) Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLink(s):bq24150Abq24151A

bq24150A Not Recommended For New Designs bq24151A SLUS931A–APRIL2009–REVISEDJANUARY2010 www.ti.com This is a standard value. If it is not a standard value, then choose the next close value and calculate the real chargecurrent.Calculatethepowerdissipationonthesenseresistor: P =I 2×R (RSNS) (CHARGE) (SNS) P =1252×0.068 (RSNS) P =0.106W (RSNS) Select04020.125-W68-mΩ2%senseresistor,i.e.PanasonicERJ2BWGR068. 4. MeasuredefficiencyandtotalpowerlossfordifferentinductorsareshowninFigure36. Battery Charge Efficiency Battery Charge Loss 90 800 T =25°C, T =25°C, A A 89 TOKO VBUS = 5 V, 700 VBUS = 5 V, VBAT = 3 V VBAT = 3 V 88 FDK 600 % y - 87 muRata mW500 Inter-Technical TOKO cienc86 Inter-Technical oss - 400 muRata FDK Effi85 L 300 84 200 83 82 100 500 600 700 800 900 1000 1100 1200 1300 500 600 700 800 900 1000 1100 1200 1300 Charge Current - mA Charge Current - mA Figure36. MeasuredEfficiencyandPowerLoss PCB LAYOUT CONSIDERATION ItisimportanttopayspecialattentiontothePCBlayout.Thefollowingprovidessomeguidelines: • To obtain optimal performance, the power input capacitors, connected from input to PGND, should be placed ascloseaspossibletothebq24150A/1A.TheoutputinductorshouldbeplacedclosetotheICandtheoutput capacitorconnectedbetweentheinductorandPGNDoftheIC.Theintentistominimizethecurrentpathloop area from the SW pin through the LC filter and back to the PGND pin. To prevent high frequency oscillation problems, proper layout to minimize high frequency current path loop is critical (see Figure 37). The sense resistor should be adjacent to the junction of the inductor and output capacitor. Route the sense leads connected across the RSNS back to the IC, close to each other (minimize loop area) or on top of each other onadjacentlayers(donotroutethesenseleadsthroughahigh-currentpath,seeFigure38). • Place all decoupling capacitor close to their respective IC pin and as close as to PGND (do not place components such that routing interrupts power stage currents). All small control signals should be routed awayfromthehighcurrentpaths. • The PCB should have a ground plane (return) connected directly to the return of all components through vias (two vias per capacitor for power-stage capacitors, two vias for the IC PGND, one via per capacitor for small-signal components). A star ground design approach is typically used to keep circuit block currents isolated (high-power/low-power small-signal) which reduces noise-coupling and ground-bounce issues. A single ground plane for this design gives good results. With this small layout and a single ground plane, there isnoground-bounceissue,andhavingthecomponentssegregatedminimizescouplingbetweensignals. • The high-current charge paths into VBUS, PMID and from the SW pins must be sized appropriately for the maximum charge current in order to avoid voltage drops in these traces. The PGND pins should be connectedtothegroundplanetoreturncurrentthroughtheinternallow-sideFET. • Place 4.7mF input capacitor as close to PMID pin and PGND pin as possible to make high frequency current loop area as small as possible. Place 1mF input capacitor as close to VBUS pin and PGND pin as possible to makehighfrequencycurrentloopareaassmallaspossible(seeFigure39). 34 SubmitDocumentationFeedback Copyright©2009–2010,TexasInstrumentsIncorporated ProductFolderLink(s):bq24150Abq24151A

Not Recommended For New Designs bq24150A bq24151A www.ti.com SLUS931A–APRIL2009–REVISEDJANUARY2010 VBUS SW L1 R1 VBAT High Frequency V BAT IN PMID Current PGND Path C1 C2 C3 Figure37. HighFrequencyCurrentPath Charge Current Direction R SNS To Inductor To Capacitor and battery Current Sensing Direction To CSIN and CSOUT pin Figure38. SensingResistorPCBLayout VVBBUUSS VViinn++ PPMMIIDD 11uuFF SSWW VViinn-- 44..77uuFF PPGGNNDD Figure39. InputCapacitorPositionandPCBLayoutExample Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 35 ProductFolderLink(s):bq24150Abq24151A

bq24150A Not Recommended For New Designs bq24151A SLUS931A–APRIL2009–REVISEDJANUARY2010 www.ti.com PACKAGE SUMMARY WCSPPACKAGE CHIPSCALE PACKAGE CHIPSCALE PACKAGE (Top View) (Top Side Symbol For bq24150A) (Top Side Symbol For bq24151A) A1 A2 A3 A4 TIYMLLLLS TIYMLLLLS B1 B2 B3 B4 bq24150A bq24151A C1 C2 C3 C4 D D1 D2 D3 D4 E1 E2 E3 E4 0-PinA1 Marker, TI-TI Letters,YM-Year Month Date Code, LLLL-Lot Trace Code, S-Assembly Site Code E CHIPSCALE PACKAGING DIMENSIONS The bq24150A/1Adevices are available in a 20-bump chip scale package (YFF, NanoFreeTM).The package dimensions are: ·D = 1.976±0.05 mm ·E= 1.946±0.05 mm 36 SubmitDocumentationFeedback Copyright©2009–2010,TexasInstrumentsIncorporated ProductFolderLink(s):bq24150Abq24151A

Not Recommended For New Designs bq24150A bq24151A www.ti.com SLUS931A–APRIL2009–REVISEDJANUARY2010 REVISION HISTORY ChangesfromOriginal(April2009)toRevisionA Page • Addednotetoabsolutemaximumratings ............................................................................................................................ 3 Copyright©2009–2010,TexasInstrumentsIncorporated SubmitDocumentationFeedback 37 ProductFolderLink(s):bq24150Abq24151A

PACKAGE OPTION ADDENDUM www.ti.com 28-May-2015 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) (6) (3) (4/5) BQ24150AYFFR NRND DSBGA YFF 20 3000 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 BQ24150A & no Sb/Br) BQ24150AYFFT NRND DSBGA YFF 20 250 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 BQ24150A & no Sb/Br) BQ24151AYFFR NRND DSBGA YFF 20 3000 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 BQ24151A & no Sb/Br) BQ24151AYFFT NRND DSBGA YFF 20 250 Green (RoHS SNAGCU Level-1-260C-UNLIM -40 to 85 BQ24151A & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1

PACKAGE OPTION ADDENDUM www.ti.com 28-May-2015 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 17-Jun-2015 TAPE AND REEL INFORMATION *Alldimensionsarenominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1(mm) BQ24150AYFFR DSBGA YFF 20 3000 180.0 8.4 2.18 2.18 0.81 4.0 8.0 Q1 BQ24150AYFFT DSBGA YFF 20 250 180.0 8.4 2.18 2.18 0.81 4.0 8.0 Q1 BQ24151AYFFR DSBGA YFF 20 3000 180.0 8.4 2.18 2.18 0.81 4.0 8.0 Q1 BQ24151AYFFT DSBGA YFF 20 250 180.0 8.4 2.18 2.18 0.81 4.0 8.0 Q1 PackMaterials-Page1

PACKAGE MATERIALS INFORMATION www.ti.com 17-Jun-2015 *Alldimensionsarenominal Device PackageType PackageDrawing Pins SPQ Length(mm) Width(mm) Height(mm) BQ24150AYFFR DSBGA YFF 20 3000 182.0 182.0 20.0 BQ24150AYFFT DSBGA YFF 20 250 182.0 182.0 20.0 BQ24151AYFFR DSBGA YFF 20 3000 182.0 182.0 20.0 BQ24151AYFFT DSBGA YFF 20 250 182.0 182.0 20.0 PackMaterials-Page2

D: Max = 2.006 mm, Min =1 .946 mm E: Max = 1.976 mm, Min =1 .916 mm

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TI’sprovisionoftechnical,applicationorotherdesignadvice,qualitycharacterization,reliabilitydataorotherservicesorinformation, including,butnotlimitedto,referencedesignsandmaterialsrelatingtoevaluationmodules,(collectively,“TIResources”)areintendedto assistdesignerswhoaredevelopingapplicationsthatincorporateTIproducts;bydownloading,accessingorusingTIResourcesinany way,Designer(individuallyor,ifDesignerisactingonbehalfofacompany,Designer’scompany)agreestouseanyparticularTIResource solelyforthispurposeandsubjecttothetermsofthisNotice. TI’sprovisionofTIResourcesdoesnotexpandorotherwisealterTI’sapplicablepublishedwarrantiesorwarrantydisclaimersforTI products,andnoadditionalobligationsorliabilitiesarisefromTIprovidingsuchTIResources.TIreservestherighttomakecorrections, enhancements,improvementsandotherchangestoitsTIResources.TIhasnotconductedanytestingotherthanthatspecifically describedinthepublisheddocumentationforaparticularTIResource. Designerisauthorizedtouse,copyandmodifyanyindividualTIResourceonlyinconnectionwiththedevelopmentofapplicationsthat includetheTIproduct(s)identifiedinsuchTIResource.NOOTHERLICENSE,EXPRESSORIMPLIED,BYESTOPPELOROTHERWISE TOANYOTHERTIINTELLECTUALPROPERTYRIGHT,ANDNOLICENSETOANYTECHNOLOGYORINTELLECTUALPROPERTY RIGHTOFTIORANYTHIRDPARTYISGRANTEDHEREIN,includingbutnotlimitedtoanypatentright,copyright,maskworkright,or otherintellectualpropertyrightrelatingtoanycombination,machine,orprocessinwhichTIproductsorservicesareused.Information regardingorreferencingthird-partyproductsorservicesdoesnotconstitutealicensetousesuchproductsorservices,orawarrantyor endorsementthereof.UseofTIResourcesmayrequirealicensefromathirdpartyunderthepatentsorotherintellectualpropertyofthe thirdparty,oralicensefromTIunderthepatentsorotherintellectualpropertyofTI. TIRESOURCESAREPROVIDED“ASIS”ANDWITHALLFAULTS.TIDISCLAIMSALLOTHERWARRANTIESOR REPRESENTATIONS,EXPRESSORIMPLIED,REGARDINGRESOURCESORUSETHEREOF,INCLUDINGBUTNOTLIMITEDTO ACCURACYORCOMPLETENESS,TITLE,ANYEPIDEMICFAILUREWARRANTYANDANYIMPLIEDWARRANTIESOF MERCHANTABILITY,FITNESSFORAPARTICULARPURPOSE,ANDNON-INFRINGEMENTOFANYTHIRDPARTYINTELLECTUAL PROPERTYRIGHTS.TISHALLNOTBELIABLEFORANDSHALLNOTDEFENDORINDEMNIFYDESIGNERAGAINSTANYCLAIM, INCLUDINGBUTNOTLIMITEDTOANYINFRINGEMENTCLAIMTHATRELATESTOORISBASEDONANYCOMBINATIONOF PRODUCTSEVENIFDESCRIBEDINTIRESOURCESOROTHERWISE.INNOEVENTSHALLTIBELIABLEFORANYACTUAL, DIRECT,SPECIAL,COLLATERAL,INDIRECT,PUNITIVE,INCIDENTAL,CONSEQUENTIALOREXEMPLARYDAMAGESIN CONNECTIONWITHORARISINGOUTOFTIRESOURCESORUSETHEREOF,ANDREGARDLESSOFWHETHERTIHASBEEN ADVISEDOFTHEPOSSIBILITYOFSUCHDAMAGES. UnlessTIhasexplicitlydesignatedanindividualproductasmeetingtherequirementsofaparticularindustrystandard(e.g.,ISO/TS16949 andISO26262),TIisnotresponsibleforanyfailuretomeetsuchindustrystandardrequirements. WhereTIspecificallypromotesproductsasfacilitatingfunctionalsafetyorascompliantwithindustryfunctionalsafetystandards,such productsareintendedtohelpenablecustomerstodesignandcreatetheirownapplicationsthatmeetapplicablefunctionalsafetystandards andrequirements.Usingproductsinanapplicationdoesnotbyitselfestablishanysafetyfeaturesintheapplication.Designersmust ensurecompliancewithsafety-relatedrequirementsandstandardsapplicabletotheirapplications.DesignermaynotuseanyTIproductsin life-criticalmedicalequipmentunlessauthorizedofficersofthepartieshaveexecutedaspecialcontractspecificallygoverningsuchuse. Life-criticalmedicalequipmentismedicalequipmentwherefailureofsuchequipmentwouldcauseseriousbodilyinjuryordeath(e.g.,life support,pacemakers,defibrillators,heartpumps,neurostimulators,andimplantables).Suchequipmentincludes,withoutlimitation,all medicaldevicesidentifiedbytheU.S.FoodandDrugAdministrationasClassIIIdevicesandequivalentclassificationsoutsidetheU.S. TImayexpresslydesignatecertainproductsascompletingaparticularqualification(e.g.,Q100,MilitaryGrade,orEnhancedProduct). Designersagreethatithasthenecessaryexpertisetoselecttheproductwiththeappropriatequalificationdesignationfortheirapplications andthatproperproductselectionisatDesigners’ownrisk.Designersaresolelyresponsibleforcompliancewithalllegalandregulatory requirementsinconnectionwithsuchselection. DesignerwillfullyindemnifyTIanditsrepresentativesagainstanydamages,costs,losses,and/orliabilitiesarisingoutofDesigner’snon- compliancewiththetermsandprovisionsofthisNotice. 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