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ICGOO电子元器件商城为您提供BD91501MUV-GE2由ROHM Semiconductor设计生产,在icgoo商城现货销售,并且可以通过原厂、代理商等渠道进行代购。 提供BD91501MUV-GE2价格参考¥5.24-¥10.43以及ROHM SemiconductorBD91501MUV-GE2封装/规格参数等产品信息。 你可以下载BD91501MUV-GE2参考资料、Datasheet数据手册功能说明书, 资料中有BD91501MUV-GE2详细功能的应用电路图电压和使用方法及教程。
参数 | 数值 |
产品目录 | 集成电路 (IC) |
描述 | IC REG BCK SYNC 0.3A/0.4A 16VQFN |
产品分类 | |
品牌 | Rohm Semiconductor |
数据手册 | |
产品图片 | |
产品型号 | BD91501MUV-GE2 |
PWM类型 | 电流模式 |
rohs | 无铅 / 符合限制有害物质指令(RoHS)规范要求 |
产品系列 | - |
供应商器件封装 | VQFN016V3030 |
其它名称 | BD91501MUV-GE2TR |
包装 | 带卷 (TR) |
同步整流器 | 是 |
安装类型 | 表面贴装 |
封装/外壳 | 16-VFQFN 裸露焊盘 |
工作温度 | -30°C ~ 105°C |
标准包装 | 3,000 |
电压-输入 | 2.55 V ~ 5.5 V |
电压-输出 | 1.8V, 2.55V |
电流-输出 | 300mA, 400mA |
类型 | 降压(降压) |
输出数 | 2 |
输出类型 | 固定 |
频率-开关 | 1.65MHz |
Datasheet 2.55V/0.4A 1.8V/0.3A Output 2ch Synchronous Buck Converter Integrated FET BD91501MUV ●Description ●Key Specifications Input voltage range: 2.55V to 5.5V ROHM’s buck converter BD91501MUV is a 2ch output Output volatage: 1.8V,2.55V power supply designed to produce a low voltage Output voltage accuracy ±1.5% including 2.55V/0.4A and 1.8V/0.3A from 3.3V power Switching frequency: 1.65MHz±20% supply line. Offers high efficiency with our original Low Voltage Detection: 50%(Typ.) pulse skip control technology and synchronous rectifier. Maximum on duty: 100% Employs a current mode control system to provide Operating temperature range: -30℃ to +105℃ faster transient response to sudden change in load. ●Package (Typ.) (Typ.) (Max.) VQFN016V3030: 3.00mm × 3.00 × 1.00mm ●Features Offers fast transient response with current mode PWM control system. Offers highly efficiency for all load range with synchronous rectifier (Pch/Nch FET) and SLLMTM (Simple Light Load Mode) Incorporates soft start function Incorporates thermal protection and UVLO function Incorporates short-current protection with timer latch Incorporates shutdown function Icc=0µA (Typ.) Full 100% Duty function 2ch output power supply (2.55V, 1.8V) VQFN016V3030 2ch output ON/OFF individual control Employs small surface mount package: VQFN016V3030 ●Typical Application Circuit ●Usage Power supply for LSI including DSP, DDR(RAM), Micro computer and ASIC L1 VIN AVCC SW1 VOUT1 PVCC1 FB1 PV CC2 L2 BD91501MUV SW2 VOUT2 FB2 Enable1 EN1 Enable2 EN2 Figure.1 Typical Application Circuit ○Product structure:Silicon monolithic integrated circuit ○This product is not designed protection against radioactive rays. www.rohm.com TSZ02201-0J3J0A900260-1-2 ©2012 ROHM Co., Ltd. All rights reserved. 1/22 31.Aug.2012 Rev.001 TSZ22111・14・001
BD91501MUV Datasheet ●Pin ConFigureuration(TOP VIEW) AGND N.C. N.C. AVCC 12 11 10 9 ITH2 13 8 ITH1 FB2 14 7 FB1 EN2 15 6 EN1 SW2 16 5 SW1 1 2 3 4 PGND2 PVCC2 PVCC1 PGND1 Figure.2 Pin ConFigureuration ●Pin Description Pin Pin Pin Pin Pin Function Pin Function No. name No. name 1 PGND2 Ch2 Low side source pin 9 AVCC Analog VCC pin 2 PVcc2 Ch2 High side source pin 10 N.C. Non connection (Please connect to AGND) 3 PVcc1 Ch1 High side source pin 11 N.C. Non connection (Please connect to AGND) 4 PGND1 Ch1 Low side source pin 12 AGND Analog GND pin Ch2 gm amplifier output pin 5 SW1 Ch1 Pch/Nch FET drain output pin 13 ITH2 /Connected phase compensation capacitor 6 EN1 Ch1 Enable pin (High Active) 14 FB2 Ch2 Output voltage detect pin 7 FB1 Ch1 Output voltage detect pin 15 EN2 Ch2 Enable pin (High Active) Ch1 gm amplifier output pin 8 ITH1 16 SW2 Ch2 Pch/Nch FET drain output pin /Connected phase compensation capacitor ●Block Diagram gm Amp gm Amp AGND Figure.3 Block Diagram www.rohm.com TSZ02201-0J3J0A900260-1-2 ©2012 ROHM Co., Ltd. All rights reserved. 2/22 31.Aug.2012 Rev.001 TSZ22111・15・001
BD91501MUV Datasheet ●Absolute Maximum Ratings (Ta=25℃) Parameter Symbol Rating Unit Power Supply Voltage VCC -0.3 to +7 *1 V VEN1 -0.3 to +7 V EN Voltage VEN2 -0.3 to +7 V Vsw1 -0.3 to +7 V SW Voltage Vsw2 -0.3 to +7 V Pd1 0.27 *2 W Pd2 0.62 *3 W Power Dissipation Pd3 1.77 *4 W Pd4 2.66 *5 W Operating temperature range Topr -30 to +105 ℃ Storage temperature range Tstg -55 to +150 ℃ Maximum junction temperature Tj +150 ℃ *1 Pd, ASO and Tj=150℃ should not be exceeded. *2 IC only *3 1-layer. mounted on a 74.2mm×74.2mm×1.6mm Glass-epoxy PCB,( Copper foil area:Surface 6.28mm2 *4 4-layer. mounted on a 74.2mm×74.2mm×1.6mm Glass-epoxy PCB,( Copper foil area:Surface and bottom layer 6.28mm2,2nd and 3rd layer 5505mm2) *5 4-layer. mounted on a 74.2mm×74.2mm×1.6mm Glass-epoxy PCB,(Copper foil area:all layers 5505mm2) ●Recommended Operating Ratings (Ta=-30 to +105℃) Limits Parameter Symbol Unit Min. Typ. Max. AVCC 2.55 3.3 5.5 V Power Supply Voltage PVcc 2.55 3.3 5.5 V VEN1 0 - AVCC V EN Voltage VEN2 0 - AVCC V ISW1 - - 400*6 mA SW average output current ISW2 - - 300*6 mA *6 Pd and ASO should not be exceeded. ●Electrical Characteristics (Ta=25℃ AVCC=PVCC=3.3V, EN1=EN2=AVCC, unless otherwise specified. ) Limits Parameter Symbol Unit Conditions Min. Typ. Max. Standby Current ISTB - 0 10 µA EN1=EN2=0V Bias Current ICC - 500 800 µA EN Low Voltage VENL - GND 0.8 V In stand-by mode EN High Voltage VENH 2.0 Vcc - V In active mode EN Input Current IEN - 1 10 µA VEN1=VEN2=2V Oscillation Frequency FOSC 1.32 1.65 1.98 MHz RONP1 - 0.85 1.56 Ω VCC=3.3V Pch FET ON Resistor RONP2 - 0.85 1.56 Ω VCC=3.3V RONN1 - 0.65 1.3 Ω VCC=3.3V Nch FET ON Resistor RONN2 - 0.65 1.3 Ω VCC=3.3V FB1 2.512 2.55 2.588 V ±1.5% Output Voltage FB2 1.773 1.8 1.827 V ±1.5% UVLO Threshold Voltage VUVLO1 2.20 2.30 2.40 V VCC=5V→0V UVLO Release Voltage VUVLO2 2.22 2.35 2.50 V VCC=0V→5V Soft Start Time TSS 0.45 0.9 1.8 ms Timer Latch Time TLATCH 0.62 1.24 2.48 ms SCP/TSD ON Output Short circuit VSCP1 - 1.275 1.77 V FB1=2.55→0V Threshold Voltage VSCP2 - 0.9 1.26 V FB2=1.8→0V www.rohm.com TSZ02201-0J3J0A900260-1-2 ©2012 ROHM Co., Ltd. All rights reserved. 3/22 31.Aug.2012 Rev.001 TSZ22111・15・001
BD91501MUV Datasheet ●Characteristics data(Reference data) (Ta=25℃,VCC=3.3V,VEN=3.3V,Unless Otherwise specified) 33 33 22.5.5 22..55 TAGE[V] TAGE[V] 22 TIoa==02.53℃A TAGE[V] TAGE[V] 22 VTIoaC==C02A=5 3℃.3 V LL LL UT VOT VO11.5.5 UT VOT VO11..55 PU PU OUTUTP 11 [[VVOOUUTT21==12..85V5V s]e tting] OUTUTP 11 O O [VOUT1=2.55V] 00.5.5 00..55 [VOUT2=1.8V setting] 00 00 0 1 2 3 4 0 0.5 1 1.5 2 2.5 3 3.5 0 1 2 3 4 0 0.5 1 1.5 2 2.5 3 3.5 VCVCCC[V[V]] ENE[VN][V ] Figure.4 VCC-VOUT Figure.5 VEN-VOUT 33..55 2.26.56 33 V22.5.65 [VOUT1=2.55V] [ E UT VOLTAGE[V] PUT VOLTAGE[V]1212....552552 UT VOLTAGE[V] TVOLTAG222..254..5555 VIoC=C0A= 3.3V TPUT [VOUT1=2.55V] TPU2.24.54 OUO 11 [VOUT2=1.8V setting] OUP T U 2.35 00..55 O2.4 00 2.23.53 00 220000 440000 660000 880000 11000000 -40 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100 IIoO[m[mA]A] Ta[℃] Ta[℃] Figure.6 IOUT-VOUT Figure.7 Ta-VOUT1 www.rohm.com TSZ02201-0J3J0A900260-1-2 ©2012 ROHM Co., Ltd. All rights reserved. 4/22 31.Aug.2012 Rev.001 TSZ22111・15・001
BD91501MUV Datasheet 11.8.865 110000 9900 [VOUT2=1.8V setting] [V11.8.832 8800 V] E E[G 7700 [VOUT1=2.55V] GA TALT 11..789 %] 6600 [VOUT2=1.8V setting] TPUT VOLPUT VO11.7.776 VIoC=C0A= 3.3V Efficiency[効率[%] 45450000 VTaC=C2=53℃.3 V OUUT 3300 O11.7.743 2200 1100 1.711.7 -40 -20 0 20 40 60 80 100 00 -40 -20 0 20 40 60 80 100 1100 110000 11000000 Ta[℃] Io[mA] Ta[℃] Io[mA] Figure.8 Ta-VOUT2 Figure.9 Efficiency 2 2 1.8 1.8 1.91 .9 11..77 1.81 .8 Hz] 1z].71 .7 z] 11..66 M MH MH Ta=25℃ f[ 1f[.61 .6 VCC=3.3V f[ 11..55 1.51 .5 11..44 1.41 .4 1.31 .3 11..33 -4-400 -2-200 00 2200 4400 6600 8800 110000 2.25.555 3.30.055 33.5.555 44.0.055 44..5555 55..0055 5.50 TTa「a℃[]℃] Vcc[V] Figure.10 Ta-Fosc Figure.11 VCC-Fosc www.rohm.com TSZ02201-0J3J0A900260-1-2 ©2012 ROHM Co., Ltd. All rights reserved. 5/22 31.Aug.2012 Rev.001 TSZ22111・15・001
BD91501MUV Datasheet 11.2.2 22 PMOS Io=0.3A 11.8.8 11 11..66 11.4.4 00.8.8 11..22 ] on[Ω] on[Ω00.6.6 NMOS Io=0.3A N[V] N[V]11 RR E E00..88 00.4.4 00.6.6 VCC=3.3V VCC=3.3V 00.4.4 00.2.2 00..22 00 00 -40 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100 -40 -20 0 20 40 60 80 100 Ta[℃] Ta[℃] Ta [℃] T a[℃] Figure.12 Ta-RONN, RONP Figure.13 Ta-VEN1, VEN2 606000 505000 VCC=3.3V, Ta=25℃ EN1=EN2 A]404000 [2V/div] A] [u µc act[vc303000 ca Icc VOUT1 c [1V/div] v202000 Ip Vout1=2.55V 101000 Vout2=1.8V VOUT2 [1V/div] 0 -4-400 --2200 00 2200 4400 6600 8800 110000 time [400µsec/div] Ta[℃] Ta[℃] Figure.14 Ta-ICC Figure.15 Soft start waveform (Io=0mA) www.rohm.com TSZ02201-0J3J0A900260-1-2 ©2012 ROHM Co., Ltd. All rights reserved. 6/22 31.Aug.2012 Rev.001 TSZ22111・15・001
BD91501MUV Datasheet SW1 [2V/div] EN1=EN2 VCC=3.3V, Ta=25℃ [2V/div] VCC=3.3V, Ta=25℃ VOUT1 [1V/div] VOUT1 Vout1=2.55V [50mV/div] Vout2=1.8V VOUT2 [1V/div] time [400µsec/div] time [400nsec/div] Figure.16 Soft start waveform Figure.17 SW waveform 1 (Io=0.3A) (Io=0mA) SW1 SW2 [2V/div] [2V/div] VCC=3.3V, Ta=25℃ VCC=3.3V, Ta=25℃ VOUT2 VOUT1 [50mV/div] [50mV/div] time [400nsec/div] time [400nsec/div] Figure.18 SW waveform 1 Figure.19 SW waveform 2 (Io=0.25A) (Io=0mA) www.rohm.com TSZ02201-0J3J0A900260-1-2 ©2012 ROHM Co., Ltd. All rights reserved. 7/22 31.Aug.2012 Rev.001 TSZ22111・15・001
BD91501MUV Datasheet SW2 [2V/div] VOUT1 [50mV/div] VCC=3.3V, Ta=25℃ VCC=3.3V, Ta=25℃ VOUT2 [50mV/div] Io [100mA/div] time [400nsec/div] time [10µsec/div] Figure.20 SW waveform 2 Figure.21 VOUT1 Transient response (Io=0.25A) (Io=10mA→0.25A) VOUT1 [50mV/div] VOUT2 [50mV/div] VCC=3.3V, Ta=25℃ VCC=3.3V, Ta=25℃ Io [1 00mA/div] Io [100mA/div] time [10µsec/div] time [10µsec/div] Figure.22 VOUT1 Transient response Figure.23 VOUT2 Transient response (Io=0.25A→10mA) (Io=10mA→0.25A) www.rohm.com TSZ02201-0J3J0A900260-1-2 ©2012 ROHM Co., Ltd. All rights reserved. 8/22 31.Aug.2012 Rev.001 TSZ22111・15・001
BD91501MUV Datasheet VOUT2 [50mV/div] VCC=3.3V, Ta=25℃ Io [1 00mA/div] time [10µsec/div] Figure.24 VOUT2 Transient response (Io=0.25A→10mA) www.rohm.com TSZ02201-0J3J0A900260-1-2 ©2012 ROHM Co., Ltd. All rights reserved. 9/22 31.Aug.2012 Rev.001 TSZ22111・15・001
BD91501MUV Datasheet ●Operation BD91501MUV is a synchronous Buck Converter that achieves faster transient response by employing current mode PWM control system. It utilizes switching operation in PWM (Pulse Width Modulation) mode for heavier load, while it utilizes SLLMTM (Simple Light Load Mode) operation for lighter load to improve efficiency. ○Synchronous rectifier It does not require the power to be dissipated by a rectifier externally connected to a conventional DC/DC converter IC, and its P.N junction shoot-through protection circuit limits the shoot-through current during operation, by which the power dissipation of the set is reduced. ○Current mode PWM control Synthesizes a PWM control signal with the inductor current feedback loop added to the voltage feedback. Offers fast transient response with current mode control system. Improves output voltage drop of load rapid change. Load response IO=10mA→250mA Transient response IO=250mA→10mA Vo Vo 0.5[V/DIV] 0.5[V/DIV] Io Io 100[mA/DIV] 100[mA/DIV] Figure.25 Transient response ・PWM (Pulse Width Modulation) control The oscillation frequency for PWM is 1.65 MHz. SET signal form OSC turns ON a highside MOS FET (while a lowside MOS FET is turned OFF), and an inductor current I increases. The current comparator (Current Comp) receives two L signals, a current feedback control signal (SENSE: Voltage converted from I ) and a voltage feedback control signal (FB), L and issues a RESET signal if both input signals are identical to each other, and turns OFF the highside MOS FET (while a lowside MOS FET is turned ON) for the rest of the fixed period. The PWM control repeat this operation. ・SLLMTM (Simple Light Load Mode) control When the control mode is shifted from PWM for heavier load to the one for lighter load or vise versa, the switching pulse is designed to turn OFF with the device held operated in normal PWM control loop, which allows linear operation without voltage drop or deterioration in transient response during the mode switching from light load to heavy load or vise versa. Although the PWM control loop continues to operate with a SET signal from OSC and a RESET signal from Current Comp, it is so designed that the RESET signal is held issued if shifted to the light load mode, with which the switching is tuned OFF and the switching pulses are thinned out under control. Activating the switching intermittently reduces the switching dissipation and improves the efficiency. %] 100 SLLM η[ y c n e 50 ① PWM ci ①Improvements by Effi SLLM control 0 0.001 0.01 0.1 1 Output current Io[A] Figure.26 Efficiency characteristics www.rohm.com TSZ02201-0J3J0A900260-1-2 ©2012 ROHM Co., Ltd. All rights reserved. 10/22 31.Aug.2012 Rev.001 TSZ22111・15・001
BD91501MUV Datasheet ・100% Duty control Maximum Duty is 100% (Pch MOSFET is always ON). If output voltage cannot keep steady because of input voltage drop for normal PWM control, oscillation frequency gets low, and becomes 100% Duty finally. Output voltage value is the dropped value of Pch MOSFET’s ON voltage so that even low input voltage can keep output voltage. SENSE Current Comparator VOUT RESET Level R Q IL Shift FB SET S Driver VOUT gm Amp. Logic SW Load ITH OSC Figure.27 Current mode PWM control block diagram PVCC PVCC Com Cpuarrraetonrt SENSEComCpuarrraetonrt SENSE FB FB SET GND SET GND RESET GND RESET GND SW GND SW IL IL(AVE) GND IL 0A VOUT VOUT(AVE) VOUT VOUT(AVE) No switching Figure.28 PWM Switching timing chart Figure.29 SLLMTM Switching timing chart www.rohm.com TSZ02201-0J3J0A900260-1-2 ©2012 ROHM Co., Ltd. All rights reserved. 11/22 31.Aug.2012 Rev.001 TSZ22111・15・001
BD91501MUV Datasheet ・Soft-start function EN terminal shifted to “High” activates a soft-starter to gradually establish the output voltage with the current limited during startup, by which it is possible to prevent an overshoot of output voltage and an inrush current. ・Shutdown function With EN terminal shifted to “Low”, the device turns to Standby Mode, and all the function blocks including reference voltage circuit, internal oscillator and drivers are turned to OFF. Circuit current during standby is 0μA (Typ.). ・UVLO function Detects whether the input voltage sufficient to secure the output voltage of this IC is supplied. And the hysteresis width of 50mV (Typ.) is provided to prevent output chattering. Hysteresis 50mV VCC EN1,2 VOUT1, VOUT2 Tss Tss Tss Soft start Standby Standby Standby mode Operating mode mode Operating mode mode Operating mode Standby mode UVLO UVLO EN UVLO Figure.30 Soft start, Shut down, UVLO Timing chart ・Short-current protection circuit with time delay function Turns OFF the output to protect the IC from breakdown when the incorporated current limiter is activated continuously for the fixed time(TLATCH) or more. The output thus held tuned OFF may be recovered by restarting EN or by re-unlocking UVLO. EN1=EN2 Output Short circuit VOUT1 Threshold Voltage Output OFF Latch VOUT2 IL1 IL Limit IL2 Smtaonddeb y Opt1e<raTtLinATgC mH ode t2=TLATCH Standby Operating mode mode EN Timer latch EN Figure.31 Soft start, Shut down, UVLO Timing chart www.rohm.com TSZ02201-0J3J0A900260-1-2 ©2012 ROHM Co., Ltd. All rights reserved. 12/22 31.Aug.2012 Rev.001 TSZ22111・15・001
BD91501MUV Datasheet ●Switching regulator efficiency Efficiency ŋ may be expressed by the equation shown below: η= VOUT×IOUT ×100[%]= POUT ×100[%]= POUT ×100[%] Vin×Iin Pin POUT+PDα Efficiency may be improved by reducing the switching regulator power dissipation factors P α as follows: D Dissipation factors: 1) ON resistance dissipation of inductor and FET:PD(I2R) 2) Gate charge/discharge dissipation:PD (Gate) 3) Switching dissipation:PD (SW) 4) ESR dissipation of capacitor:PD (ESR) 5) Operating current dissipation of IC:PD (IC) 1)PD (I2R)=IOUT2×(RCOIL+RON) (RCOIL[Ω]:DC resistance of inductor, RON[Ω]:ON resistance of FET, IOUT[A]:Output current.) 2)PD (Gate)=Cgs×f×V (Cgs[F]:Gate capacitance of FET, f[H]:Switching frequency, V[V]:Gate driving voltage of FET) Vin2×CRSS×IOUT×f 3)PD (SW)= (CRSS[F]:Reverse transfer capacitance of FET, IDRIVE[A]:Peak current of gate.) IDRIVE 4)PD (ESR)=IRMS2×ESR (IRMS[A]:Ripple current of capacitor, ESR[Ω]:Equivalent series resistance.) 5)PD (IC)=Vin×ICC (ICC[A]:Circuit current.) www.rohm.com TSZ02201-0J3J0A900260-1-2 ©2012 ROHM Co., Ltd. All rights reserved. 13/22 31.Aug.2012 Rev.001 TSZ22111・15・001
BD91501MUV Datasheet ●Consideration on permissible dissipation and heat generation As this IC functions with high efficiency without significant heat generation in most applications, no special consideration is needed on permissible dissipation or heat generation. In case of extreme conditions, however, including lower input voltage, higher output voltage, heavier load, and/or higher temperature, the permissible dissipation and/or heat generation must be carefully considered. For dissipation, only conduction losses due to DC resistance of inductor and ON resistance of FET are considered. Because the conduction losses are considered to play the leading role among other dissipation mentioned above including gate charge/discharge dissipation and switching dissipation. 3.0 ①2.66W ① θ (c4oj -lpaap=yee4rr7 sf.o 0(ic℃l oin/pW peea rc hfo lial ayerersa) : 5505mm2) P=IOUT2×RON W] ②6 .θ2 (284j,m- 3al am=lay72ye)0e r.sr6 c℃(o1p,/4Wp e lar yfoeirl acroepap :e5r5 0fo5ilm amre2)a : RDO:NO=DN× DRutOyN(=HV+O(1U-TD/V)RCOCN) L Pd [ 2.0 ②1.77W ③ θ 1j- laa=y2e0r 1(c.6op℃p/eWr foil area : 6.28mm2) RONH:Highside MOS FET impedance n: ④IC only atio θj-a=463.0℃/W RONL:Lowside MOS FET impedance sip IOUT:Output current Power dis 1.0 ③④00..6227WW 0 0 25 50 75 100 105 125 150 Ambient temperature:Ta [℃] Figure.32 Thermal derating curve (VQFN016-V3030) Example) If VCC=3.3V, VOUT1=2.55V, VOUT2=1.8V, RONH=850mΩ, RONL=650mΩ, IOUT=300mA D1=VOUT1/VCC=2.55/3.3=0.77 D2=VOUT2/VCC=1.8/3.3=0.55 RON1=0.77×0.85+(1-0.77)×0.65 =0.804 [Ω] RON2=0.55×0.85+(1-0.55)×0.65 =0.760 [Ω] P=0.32×0.804+0.32×0.760=0.141 [W] As RONH is greater than RONL in this IC, the dissipation increases as the ON duty becomes greater. With the consideration on the dissipation as above, thermal design must be carried out with sufficient margin allowed. www.rohm.com TSZ02201-0J3J0A900260-1-2 ©2012 ROHM Co., Ltd. All rights reserved. 14/22 31.Aug.2012 Rev.001 TSZ22111・15・001
BD91501MUV Datasheet ●Selection of components externally connected 1. Selection of inductor (L) Ripple current value at output is greatly influenced by inductor value. IL Refer to equation of (1),Ripple current value is more decrease at ΔIL switching frequency is higher and at inductor value is larger. VCC (VCCVOUT)VOUT ΔIL [A]・・・(1) LVCCf IL Appropriate ripple current at output should be 60% more or less of VOUT the maximum output current L Co ΔIL=0.6×IOUTmax. [A]・・・(2) (VCC-VOUT)×VOUT L= [H]・・・(3) ΔIL×VCC×f Figure.33 Output ripple current (ΔIL: Output ripple current、f: Switching frequency) Output ripple current turns to be cramped at about 0.9A peak by considering the stable start-up. ※Current exceeding the current rating of the inductor results in magnetic saturation of the inductor, which decreases efficiency. The inductor must be selected allowing sufficient margin with which the peak current may not exceed its current rating. Example) for BD91501MUV, if VCC=3.3V, VOUT=2.55V, f=1.65MHz, ΔIL=0.6×0.3A=0.18A (3.3-2.55)×2.55 L= 0.18×3.3×1650K =1.95µH →1.5µH~4.7µH ※Select the inductor of low resistance component (such as DCR and ACR) to minimize dissipation in the inductor for better efficiency. 2. Selection of output capacitor (CO) Output capacitor should be selected with the consideration on the stability VCC region and the equivalent series resistance required to smooth ripple voltage. Output ripple voltage is determined by the equation (4): VOUT L ESR ΔVOUT=ΔIL×ESR [V]・・・(4) Co (ΔIL: Output ripple current、ESR: Equivalent series resistance of output capacitor) ※Rating of the capacitor should be determined allowing sufficient margin against output voltage. 22µF to 100µF ceramic capacitor is recommended. Figure.34 Output capacitor Less ESR allows reduction in output ripple voltage. www.rohm.com TSZ02201-0J3J0A900260-1-2 ©2012 ROHM Co., Ltd. All rights reserved. 15/22 31.Aug.2012 Rev.001 TSZ22111・15・001
BD91501MUV Datasheet 3. Selection of input capacitor (Cin) Input capacitor to select must be a low ESR capacitor of the capacitance VCC sufficient to cope with high ripple current to prevent high transient voltage. The Cin ripple current IRMS is given by the equation (5): √ VOUT VOUT(VCC-VOUT) L Co IRMS=IOUT× VCC [A]・・・(5) < Worst case > IRMS(max.) IOUT When VCC=2×VOUTIRMS= 2 Figure.35 Input capacitor Example) for BD91501MUV, if VCC=3.3V, VOUT=2.55V, IOUTmax.=0.3A, 2.55(3.3-2.55) 0.3 0.126(ARMS) 3.3 A low ESR 22µF/10V ceramic capacitor is recommended to reduce ESR dissipation of input capacitor for better efficiency. 4. Determination of RITH, CITH that works as a phase compensator As the Current Mode Control is designed to limit a inductor current, a pole (phase lag) appears in the low frequency area due to a CR filter consisting of a output capacitor and a load resistance, while a zero (phase lead) appears in the high frequency area due to the output capacitor and its ESR. So, the phases are easily compensated by adding a zero to the power amplifier output with C and R as described below to cancel a pole at the power amplifier. fp(Min.) A fp= 1 fp(Max.) 2π×RO×CO Gain 0 1 [dB] fz(ESR) fz(ESR)= 2π×ESR×CO IOUTMin. IOUTMax. Pole at power amplifier 0 When the output current decreases, the load resistance Ro Phase [deg] increases and the pole frequency lowers. -90 1 fp(Min.)= 2π×ROMax.×CO [Hz]←with lighter load Figure.36 Open loop gain characteristics 1 fp(Max.)= [Hz] ←with heavier load 2π×ROMin.×CO A fz(Amp.) Zero at power amplifier Gain [dB] Increasing capacitance of the output capacitor lowers the 0 pole frequency while the zero frequency does not change. (This is because when the capacitance is 0 doubled, the capacitor ESR reduces to half.) Phase [deg] 1 -90 fz(Amp.)= 2π×RITH×CITH Figure.37 Error Amp phase compensation characteristics Stable feedback loop may be achieved by canceling the pole fp (Min.) produced by the output capacitor and the load resistance with CR zero correction by the error amplifier. fz(Amp.)= fp(Min.) 1 1 = 2π×RITH×CITH 2π×ROMax.×CO www.rohm.com TSZ02201-0J3J0A900260-1-2 ©2012 ROHM Co., Ltd. All rights reserved. 16/22 31.Aug.2012 Rev.001 TSZ22111・15・001
BD91501MUV Datasheet ●Application Example Vcc CITH1 RITH1 L1 VOUT1 ITH1 FB1 EN1 SW1 COUT1 AVcc PGND1 CIN1 N.C. PVcc1 N.C. PVcc2 CIN2 AGND PGND2 COUT2 ITH2 FB2 EN2 SW2 VOUT2 RITH2 CITH2 L2 Figure.38 Application Example www.rohm.com TSZ02201-0J3J0A900260-1-2 ©2012 ROHM Co., Ltd. All rights reserved. 17/22 31.Aug.2012 Rev.001 TSZ22111・15・001
BD91501MUV Datasheet ●Evaluation Top Silk Top layer Bottom Silk Bottom Layer Figure.39 Layout Diagram ① Layout the input ceramic capacitor CIN closer to the pins PVCC and PGND, and the output capacitor Co closer to the pin PGND. ② Layout CITH and RITH between the pins ITH and GND as neat as possible with least necessary wiring. ※VQFN016V3030 (BD91501MUV) has thermal PAD on the reverse of the package. The package thermal performance may be enhanced by bonding the PAD to GND plane which take a large area of PCB. ●Recommended components Lists on above application Symbol Type Value Manufacturer Part Number L1,2 Inductor 2.2µH TOKO DE2818C 1072AS-2R2M CIN1,CIN2 Ceramic capacitor 22µF Murata GRM32EB11A226KE20 Cout1,Cout2 Ceramic capacitor 22µF Murata GRM31CB30J226KE18 CITH1 Ceramic capacitor 330pF Murata CRM18 Series RITH1 Resistor 91kΩ Rohm MCR03 Series CITH2 Ceramic capacitor 330pF Murata GRM18 Series RITH2 Resistor 75kΩ Rohm MCR03 Series ※The parts list presented above is an example of recommended parts. Although the parts are sound, actual circuit characteristics should be checked on your application carefully before use. Be sure to allow sufficient margins to accommodate variations between external devices and this IC when employing the depicted circuit with other circuit constants modified. Both static and transient characteristics should be considered in establishing these margins. When switching noise is substantial and may impact the system, a low pass filter should be inserted between the VCC and PVCC pins, and a schottky barrier diode or snubber established between the SW and PGND pins. www.rohm.com TSZ02201-0J3J0A900260-1-2 ©2012 ROHM Co., Ltd. All rights reserved. 18/22 31.Aug.2012 Rev.001 TSZ22111・15・001
BD91501MUV Datasheet ●I/O equivalence circuit ・EN1,EN2 pin ・SW1,SW2 pin PVCC PVCC PVCC EN1,EN2 88K 10K SW1/SW2 1120K 300K/250K ・FB1,FB2 pin ・ITH1,ITH2 pin AVCC 850K/500K FB1/FB2 43.75 ITH1,ITH2 400K/400K 10K Figure.40 I/O equivalence circuit ●Operational Notes 1. Absolute Maximum Ratings While utmost care is taken to quality control of this product, any application that may exceed some of the absolute maximum ratings including the voltage applied and the operating temperature range may result in breakage. If broken, short-mode or open-mode may not be identified. So if it is expected to encounter with special mode that may exceed the absolute maximum ratings, it is requested to take necessary safety measures physically including insertion of fuses. 2. Electrical potential at GND GND must be designed to have the lowest electrical potential In any operating conditions. 3. Short-circuiting between terminals, and mismounting When mounting to pc board, care must be taken to avoid mistake in its orientation and alignment. Failure to do so may result in IC breakdown. Short-circuiting due to foreign matters entered between output terminals, or between output and power supply or GND may also cause breakdown. 4. Thermal shutdown protection circuit Thermal shutdown protection circuit is the circuit designed to isolate the IC from thermal runaway, and not intended to protect and guarantee the IC. So, the IC the thermal shutdown protection circuit of which is once activated should not be used thereafter for any operation originally intended. 5. Inspection with the IC set to a pc board If a capacitor must be connected to the pin of lower impedance during inspection with the IC set to a pc board, the capacitor must be discharged after each process to avoid stress to the IC. For electrostatic protection, provide proper grounding to assembling processes with special care taken in handling and storage. When connecting to jigs in the inspection process, be sure to turn OFF the power supply before it is connected and removed. www.rohm.com TSZ02201-0J3J0A900260-1-2 ©2012 ROHM Co., Ltd. All rights reserved. 19/22 31.Aug.2012 Rev.001 TSZ22111・15・001
BD91501MUV Datasheet 6. Input to IC terminals This is a monolithic IC with P+ isolation between P-substrate and each element as illustrated below. This P-layer and the N-layer of each element form a P-N junction, and various parasitic element are formed. If a resistor is joined to a transistor terminal as shown in Figure 41. ○P-N junction works as a parasitic diode if the following relationship is satisfied; GND>Terminal A (at resistor side), or GND>Terminal B (at transistor side); and ○if GND>Terminal B (at NPN transistor side), a parasitic NPN transistor is activated by N-layer of other element adjacent to the above-mentioned parasitic diode. The structure of the IC inevitably forms parasitic elements, the activation of which may cause interference among circuits, and/or malfunctions contributing to breakdown. It is therefore requested to take care not to use the device in such manner that the voltage lower than GND (at P-substrate) may be applied to the input terminal, which may result in activation of parasitic elements. Resistor Transistor (NPN) Pin A Pin B C B Pin B E Pin A B C N N P+ N P+ P P+ P P+ N N Parasitic N E element P substrate P substrate Parasitic GND element GND GND GND Parasitic element Parasitic element Other adjacent elements Figure.41 Simplified structure of monoclinic IC 7. Ground wiring pattern If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND pattern from the small-signal GND pattern and establish a single ground at the reference point of the set PCB so that resistance to the wiring pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of the small-signal GND. Pay attention not to cause fluctuations in the GND wiring pattern of external parts as well. 8 . Selection of inductor It is recommended to use an inductor with a series resistance element (DCR) 0.1Ω or less. Especially, note that use of a high DCR inductor will cause an inductor loss, resulting in decreased output voltage. Should this condition continue for a specified period (soft start time + timer latch time), output short circuit protection will be activated and output will be latched OFF. When using an inductor over 0.1Ω, be careful to ensure adequate margins for variation between external devices and this IC, including transient as well as static characteristics. Furthermore, in any case, it is recommended to start up the output with EN after supply voltage is within operation range. ●Ordering Information B D 9 1 5 0 1 M U V ― E 2 Part Number Package Packaging and forming specification MUV : VQFN016V3030 E2 : Embossed taping and reel www.rohm.com TSZ02201-0J3J0A900260-1-2 ©2012 ROHM Co., Ltd. All rights reserved. 20/22 31.Aug.2012 Rev.001 TSZ22111・15・001
BD91501MUV Datasheet ●Physical Dimension Tape and Reel Information VQFN016V3030 <Tape and Reel information> 3.0±0.1 Tape Embossed carrier tape ±3.00.1 Quantity 3E0200pcs Direction X 1PIN MARK S of feed (Treheel odnir ethcteio lne fits h tahned 1 apnind oyfo pur opduull cot uist tahte t htaep uep opne rt hleef tr iwghhte hna ynodu hold ) MA 1.00.0C80.2S 1.4±0.1 0.5 +0.03 0.02−0.02 (0.22) ±0.40.1 1163 1 4 85 ±1.40.1 12 9 +0.05 Direction of feed 0.75 0.25−0.04 1pin (Unit : mm) Reel ∗ Order quantity needs to be multiple of the minimum quantity. ●Marking Diagram (TOP VIEW) VQFN016V3030 Product Name D 9 1 LOT Number 5 0 1 1PIN MARK www.rohm.com TSZ02201-0J3J0A900260-1-2 ©2012 ROHM Co., Ltd. All rights reserved. 21/22 31.Aug.2012 Rev.001 TSZ22111・15・001
BD91501MUV Datasheet ●Revision History Date Revision Changes 31.Aug.2012 001 New Release www.rohm.com TSZ02201-0J3J0A900260-1-2 ©2012 ROHM Co., Ltd. All rights reserved. 22/22 31.Aug.2012 Rev.001 TSZ22111・15・001
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