8/16-bit Atmel AVR XMEGA D3 Microcontroller ATxmega32D3 / ATxmega64D3 / ATxmega128D3 / ATxmega192D3 / ATxmega256D3 / ATxmega384D3 Features  High-performance, low-power Atmel® AVR® XMEGA® 8/16-bit Microcontroller  Nonvolatile program and data memories  32K - 384KBytes of in-system self-programmable flash  4K - 8KBytes boot section  1K - 4KBytes EEPROM  4K - 32KBytes internal SRAM  Peripheral features  Four-channel event system  Five 16-bit timer/counters  Four timer/counters with four output compare or input capture channels  One timer/counter with two output compare or input capture channels  High resolution extension on two timer/counters  Advanced waveform extension (AWeX) on one timer/counter  Three USARTs with IrDA support for one USART  Two two-wire interfaces with dual address match (I2C and SMBus compatible)  Two serial peripheral interfaces (SPIs)  CRC-16 (CRC-CCITT) and CRC-32 (IEEE®802.3) generator  16-bit real time counter (RTC) with separate oscillator  One sixteen-channel, 12-bit, 300ksps Analog to Digital Converter  Two Analog Comparators with window compare function, and current sources  External interrupts on all general purpose I/O pins  Programmable watchdog timer with separate on-chip ultra low power oscillator  Atmel QTouch® library support  Capacitive touch buttons, sliders and wheels  Special microcontroller features  Power-on reset and programmable brown-out detection  Internal and external clock options with PLL and prescaler  Programmable multilevel interrupt controller  Five sleep modes  Programming and debug interface  PDI (program and debug interface)  I/O and packages  50 programmable I/O pins  64-lead TQFP  64-pad QFN  Operating voltage  1.6 – 3.6V  Operating frequency  0 – 12MHz from 1.6V  0 – 32MHz from 2.7V Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

1. Ordering Information EEPROM SRAM Power Package Ordering code Flash [bytes] [bytes] [bytes] Speed [MHz] supply (1)(2)(3) Temp. ATxmega32D3-AU 32K + 4K 1K 4K ATxmega32D3-AUR (4) 32K + 4K 1K 4K ATxmega64D3-AU 64K + 4K 2K 4K ATxmega64D3-AUR (4) 64K + 4K 2K 4K ATxmega128D3-AU 128K + 8K 2K 8K ATxmega128D3-AUR (4) 128K + 8K 2K 8K 64A ATxmega192D3-AU 192K + 8K 2K 16K ATxmega192D3-AUR (4) 192K + 8K 2K 16K ATxmega256D3-AU 256K + 8K 4K 16K ATxmega256D3-AUR (4) 256K + 8K 4K 16K ATxmega384D3-AU 384K + 8K 4K 32K ATxmega384D3-AUR (4) 384K + 8K 4K 32K 32 1.6 - 3.6V -40C - 85C ATxmega32D3-MH 32K + 4K 1K 4K ATxmega32D3-MHR (4) 32K + 4K 1K 4K ATxmega64D3-MH 64K + 4K 2K 4K ATxmega64D3-MHR (4) 64K + 4K 2K 4K ATxmega128D3-MH 128K + 8K 2K 8K ATxmega128D3-MHR (4) 128K + 8K 2K 8K 64M ATxmega192D3-MH 192K + 8K 2K 16K ATxmega192D3-MHR (4) 192K + 8K 2K 16K ATxmega256D3-MH 256K + 8K 4K 16K ATxmega256D3-MHR (4) 256K + 8K 4K 16K ATxmega384D3-MH 384K + 8K 4K 32K ATxmega384D3-MHR (4) 384K + 8K 4K 32K XMEGA D3 [DATASHEET] 2 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

EEPROM SRAM Power Package Ordering code Flash [bytes] [bytes] [bytes] Speed [MHz] supply (1)(2)(3) Temp. ATxmega32D3-AN 32K + 4K 1K 4K ATxmega32D3-ANR (4) 32K + 4K 1K 4K ATxmega64D3-AN 64K + 4K 2K 4K ATxmega64D3-ANR (4) 64K + 4K 2K 4K ATxmega128D3-AN 128K + 8K 2K 8K ATxmega128D3-ANR (4) 128K + 8K 2K 8K 64A ATxmega192D3-AN 192K + 8K 2K 16K ATxmega192D3-ANR (4) 192K + 8K 2K 16K ATxmega256D3-AN 256K + 8K 4K 16K ATxmega256D3-ANR (4) 256K + 8K 4K 16K ATxmega384D3-AN 384K + 8K 4K 32K ATxmega384D3-ANR (4) 384K + 8K 4K 32K 32 1.6 - 3.6V -40C - 105C ATxmega32D3-MN 32K + 4K 1K 4K ATxmega32D3-MNR (4) 32K + 4K 1K 4K ATxmega64D3-MN 64K + 4K 2K 4K ATxmega64D3-MNR (4) 64K + 4K 2K 4K ATxmega128D3-MN 128K + 8K 2K 8K ATxmega128D3-MNR (4) 128K + 8K 2K 8K 64M ATxmega192D3-MN 192K + 8K 2K 16K ATxmega192D3-MNR (4) 192K + 8K 2K 16K ATxmega256D3-MN 256K + 8K 4K 16K ATxmega256D3-MNR (4) 256K + 8K 4K 16K ATxmega384D3-MN 384K + 8K 4K 32K ATxmega384D3-MNR (4) 384K + 8K 4K 32K Notes: 1. This device can also be supplied in wafer form. Contact your local Atmel sales office for detailed ordering information. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For packaging information, see “Packaging Information” on page 61. 4. Tape and Reel. XMEGA D3 [DATASHEET] 3 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Package type 64A 64-lead, 14 * 14mm body size, 1.0mm body thickness, 0.8mm lead pitch, thin profile plastic quad flat package (TQFP) 64M 64-pad, 9 * 9 * 1.0mm body, lead pitch 0.50mm, 7.65mm exposed pad, quad flat no-lead package (QFN) Typical applications Industrial control Climate control Low power battery applications Factory automation RF and ZigBee® Power tools Building control Motor control HVAC Board control Sensor control Utility metering White goods Optical Medical applications XMEGA D3 [DATASHEET] 4 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

2. Pinout/block Diagram Figure 2-1. Block Diagram and Pinout Power Programming, debug, test Ground External clock /C rystal pins I D Digital function General Purpose I/O P Analog function /O scillators T/ C E A2 A1 A0 VC ND R1 R0 RES DI F7 F6 CC ND F5 F4 F3 P P P A G P P _ P P P V G P P P 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 Port R PA3 1 48 PF2 XOSC PA4 2 47 PF1 DATA BUS PA5 3 46 PF0 OSC/CLK Internal Watchdog Power Control oscillators oscillator Supervision PA6 4 AREF 45 VCC A PA7 5 ort ADC CoSnltereopll er RCeoaul Tnitmere WaTticmhedrog CoRnetsroeltler 44 GND P AC0:1 PB0 6 Event System Prog/Debug 43 PE7 CRC OCD Controller Interface PB1 7 42 PE6 Interrupt BUS PB2 8 B Controller matrix 41 PE5 rt AREF PB3 9 Po Internal CPU 40 PE4 references PB4 10 SRAM 39 PE3 FLASH EEPROM PB5 11 38 PE2 PB6 12 37 PE1 DATA BUS PB7 13 EVENT ROUTING NETWORK 36 PE0 GND 14 35 VCC M 1 T0 T0 T0 C VCC 15 RCO TC0: SAR SPI TWI TC0 SAR SPI TC0 SAR TWI TOS TC0 34 GND I U U U PC0 16 33 PD7 Port C Port D Port E Port F 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 1 2 3 4 5 6 7 D C 0 1 2 3 4 5 6 C C C C C C C N C D D D D D D D P P P P P P P G V P P P P P P P Notes: 1. For full details on pinout and alternate pin functions refer to “Pinout and Pin Functions” on page 50. 2. The large center pad underneath the QFN/MLF package should be soldered to ground on the board to ensure good mechanical stability. XMEGA D3 [DATASHEET] 5 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

3. Overview The Atmel AVR XMEGA is a family of low power, high performance, and peripheral rich 8/16-bit microcontrollers based on the AVR enhanced RISC architecture. By executing instructions in a single clock cycle, the AVR XMEGA devices achieve CPU throughput approaching one million instructions per second (MIPS) per megahertz, allowing the system designer to optimize power consumption versus processing speed. The AVR CPU combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly connected to the arithmetic logic unit (ALU), allowing two independent registers to be accessed in a single instruction, executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs many times faster than conventional single-accumulator or CISC based microcontrollers. The XMEGA D3 devices provide the following features: in-system programmable flash with read-while-write capabilities; internal EEPROM and SRAM; four-channel event system and programmable multilevel interrupt controller, 50 general purpose I/O lines, 16-bit real-time counter (RTC); five, 16-bit timer/counters with compare and PWM channels; three USARTs; two two-wire serial interfaces (TWIs); two serial peripheral interfaces (SPIs); one sixteen-channel, 12-bit ADC with programmable gain; two analog comparators (ACs) with window mode; programmable watchdog timer with separate internal oscillator; accurate internal oscillators with PLL and prescaler; and programmable brown-out detection. The program and debug interface (PDI), a fast, two-pin interface for programming and debugging, is available. The AVR XMEGA devices have five software selectable power saving modes. The idle mode stops the CPU while allowing the SRAM, event system, interrupt controller, and all peripherals to continue functioning. The power-down mode saves the SRAM and register contents, but stops the oscillators, disabling all other functions until the next TWI, or pin- change interrupt, or reset. In power-save mode, the asynchronous real-time counter continues to run, allowing the application to maintain a timer base while the rest of the device is sleeping. In standby mode, the external crystal oscillator keeps running while the rest of the device is sleeping. This allows very fast startup from the external crystal, combined with low power consumption. In extended standby mode, both the main oscillator and the asynchronous timer continue to run. To further reduce power consumption, the peripheral clock to each individual peripheral can optionally be stopped in active mode and idle sleep mode. Atmel offers a free QTouch library for embedding capacitive touch buttons, sliders and wheels functionality into AVR microcontrollers. The devices are manufactured using Atmel high-density, nonvolatile memory technology. The program flash memory can be reprogrammed in-system through the PDI. A boot loader running in the device can use any interface to download the application program to the flash memory. The boot loader software in the boot flash section will continue to run while the application flash section is updated, providing true read-while-write operation. By combining an 8/16-bit RISC CPU with in-system, self-programmable flash, the AVR XMEGA is a powerful microcontroller family that provides a highly flexible and cost effective solution for many embedded applications. All AVR XMEGA devices are supported with a full suite of program and system development tools, including: C compilers, macro assemblers, program debugger/simulators, programmers, and evaluation kits. XMEGA D3 [DATASHEET] 6 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

3.1 Block Diagram Figure 3-1. XMEGA D3 Block Diagram PR[0..1] Power Programming, debug, XTAL1 Ground External clock /C rystal pins Digital function General Purpose I/O Analog function /O scillators XTAL2 Oscillator Circuits/ Clock Real Time PORT R (2) Generation Counter Watchdog Oscillator DATA BUS Watchdog Timer ACA Event System Oscillator Sleep Controller Control Controller PA[0..7] PORT A (8) Power VCC Supervision POR/BOD & ADCA SRAM BUS Matrix RESET GND AREFA RESET/ Interrupt Prog/Debug PDI_CLK VCC/10 PDI Controller Controller PDI_DATA Int. Refs. CPU Tempref CRC OCD AREFB NVM Controller PB[0..7] PORT B (8) F (8) Flash EEPROM TCF0 RT PF[0..7] O P DATA BUS EVENT ROUTING NETWORK 0 0 0 IRCOM TCC0:1 USARTC SPIC TWIC TCD0 USARTD SPID TCE0 USARTE TWIE To Clock Generator PORT C (8) PORT D (8) PORT E (8) TOSC1 TOSC2 PC[0..7] PD[0..7] PE[0..7] XMEGA D3 [DATASHEET] 7 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

4. Resources A comprehensive set of development tools, application notes and datasheets are available for download on www.atmel.com/avr. 4.1 Recommended Reading  Atmel AVR XMEGA D manual  XMEGA application notes This device data sheet only contains part specific information with a short description of each peripheral and module. The XMEGA D manual describes the modules and peripherals in depth. The XMEGA application notes contain example code and show applied use of the modules and peripherals. All documentation are available from www.atmel.com/avr. 5. Capacitive Touch Sensing The Atmel QTouch library provides a simple to use solution to realize touch sensitive interfaces on most Atmel AVR microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and includes fully debounced reporting of touch keys and includes Adjacent Key Suppression™ (AKS™) technology for unambiguous detection of key events. The QTouch library includes support for the QTouch and Atmel QMatrix acquisition methods. Touch sensing can be added to any application by linking the appropriate Atmel QTouch library for the AVR microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors, and then calling the touch sensing API’s to retrieve the channel information and determine the touch sensor states. The QTouch library is FREE and downloadable from the Atmel website at the following location: http://www.atmel.com/tools/qtouchlibrary.aspx. For implementation details and other information, refer to the QTouch library user guide - also available for download from the Atmel website. XMEGA D3 [DATASHEET] 8 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

6. AVR CPU 6.1 Features  8/16-bit, high-performance Atmel AVR RISC CPU  137 instructions  Hardware multiplier  32x8-bit registers directly connected to the ALU  Stack in RAM  Stack pointer accessible in I/O memory space  Direct addressing of up to 16MB of program memory and 16MB of data memory  True 16/24-bit access to 16/24-bit I/O registers  Efficient support for 8-, 16-, and 32-bit arithmetic  Configuration change protection of system-critical features 6.2 Overview All Atmel AVR XMEGA devices use the 8/16-bit AVR CPU. The main function of the CPU is to execute the code and perform all calculations. The CPU is able to access memories, perform calculations, control peripherals, and execute the program in the flash memory. Interrupt handling is described in a separate section, refer to “Interrupts and Programmable Multilevel Interrupt Controller” on page 28. 6.3 Architectural Overview In order to maximize performance and parallelism, the AVR CPU uses a Harvard architecture with separate memories and buses for program and data. Instructions in the program memory are executed with single-level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This enables instructions to be executed on every clock cycle. For details of all AVR instructions, refer to www.atmel.com/avr. XMEGA D3 [DATASHEET] 9 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 6-1. Block Diagram of the AVR CPU Architecture The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a register. Single-register operations can also be executed in the ALU. After an arithmetic operation, the status register is updated to reflect information about the result of the operation. The ALU is directly connected to the fast-access register file. The 32 * 8-bit general purpose working registers all have single clock cycle access time allowing single-cycle arithmetic logic unit (ALU) operation between registers or between a register and an immediate. Six of the 32 registers can be used as three 16-bit address pointers for program and data space addressing, enabling efficient address calculations. The memory spaces are linear. The data memory space and the program memory space are two different memory spaces. The data memory space is divided into I/O registers, SRAM, and external RAM. In addition, the EEPROM can be memory mapped in the data memory. All I/O status and control registers reside in the lowest 4KB addresses of the data memory. This is referred to as the I/O memory space. The lowest 64 addresses can be accessed directly, or as the data space locations from 0x00 to 0x3F. The rest is the extended I/O memory space, ranging from 0x0040 to 0x0FFF. I/O registers here must be accessed as data space locations using load (LD/LDS/LDD) and store (ST/STS/STD) instructions. The SRAM holds data. Code execution from SRAM is not supported. It can easily be accessed through the five different addressing modes supported in the AVR architecture. The first SRAM address is 0x2000. Data addresses 0x1000 to 0x1FFF are reserved for memory mapping of EEPROM. The program memory is divided in two sections, the application program section and the boot program section. Both sections have dedicated lock bits for write and read/write protection. The SPM instruction that is used for self- programming of the application flash memory must reside in the boot program section. The application section contains an application table section with separate lock bits for write and read/write protection. The application table section can be used for safe storing of nonvolatile data in the program memory. XMEGA D3 [DATASHEET] 10 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

6.4 ALU - Arithmetic Logic Unit The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a register. Single-register operations can also be executed. The ALU operates in direct connection with all 32 general purpose registers. In a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed and the result is stored in the register file. After an arithmetic or logic operation, the status register is updated to reflect information about the result of the operation. ALU operations are divided into three main categories – arithmetic, logical, and bit functions. Both 8- and 16-bit arithmetic is supported, and the instruction set allows for efficient implementation of 32-bit aritmetic. The hardware multiplier supports signed and unsigned multiplication and fractional format. 6.4.1 Hardware Multiplier The multiplier is capable of multiplying two 8-bit numbers into a 16-bit result. The hardware multiplier supports different variations of signed and unsigned integer and fractional numbers:  Multiplication of unsigned integers  Multiplication of signed integers  Multiplication of a signed integer with an unsigned integer  Multiplication of unsigned fractional numbers  Multiplication of signed fractional numbers  Multiplication of a signed fractional number with an unsigned one A multiplication takes two CPU clock cycles. 6.5 Program Flow After reset, the CPU starts to execute instructions from the lowest address in the flash programmemory ‘0.’ The program counter (PC) addresses the next instruction to be fetched. Program flow is provided by conditional and unconditional jump and call instructions capable of addressing the whole address space directly. Most AVR instructions use a 16-bit word format, while a limited number use a 32-bit format. During interrupts and subroutine calls, the return address PC is stored on the stack. The stack is allocated in the general data SRAM, and consequently the stack size is only limited by the total SRAM size and the usage of the SRAM. After reset, the stack pointer (SP) points to the highest address in the internal SRAM. The SP is read/write accessible in the I/O memory space, enabling easy implementation of multiple stacks or stack areas. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR CPU. 6.6 Status Register The status register (SREG) contains information about the result of the most recently executed arithmetic or logic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the status register is updated after all ALU operations, as specified in the instruction set reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The status register is not automatically stored when entering an interrupt routine nor restored when returning from an interrupt. This must be handled by software. The status register is accessible in the I/O memory space. 6.7 Stack and Stack Pointer The stack is used for storing return addresses after interrupts and subroutine calls. It can also be used for storing temporary data. The Stack Pointer (SP) register always points to the top of the stack. It is implemented as two 8-bit registers that are accessible in the I/O memory space. Data are pushed and popped from the stack using the PUSH and POP instructions. The stack grows from a higher memory location to a lower memory location. This implies that pushing data onto the stack decreases the SP, and popping data off the stack increases the SP. The SP is automatically loaded XMEGA D3 [DATASHEET] 11 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

after reset, and the initial value is the highest address of the internal SRAM. If the SP is changed, it must be set to point above address 0x2000, and it must be defined before any subroutine calls are executed or before interrupts are enabled. During interrupts or subroutine calls, the return address is automatically pushed on the stack. The return address can be two or three bytes, depending on program memory size of the device. For devices with 128KB or less of program memory, the return address is two bytes, and hence the stack pointer is decremented/incremented by two. For devices with more than 128KB of program memory, the return address is three bytes, and hence the SP is decremented/incremented by three. The return address is popped off the stack when returning from interrupts using the RETI instruction, and from subroutine calls using the RET instruction. The SP is decremented by one when data are pushed on the stack with the PUSH instruction, and incremented by one when data is popped off the stack using the POP instruction. To prevent corruption when updating the stack pointer from software, a write to SPL will automatically disable interrupts for up to four instructions or until the next I/O memory write. After reset the stack pointer is initialized to the highest address of the SRAM. See Figure 7-2 on page 16. 6.8 Register File The register file consists of 32 * 8-bit general purpose working registers with single clock cycle access time. The register file supports the following input/output schemes:  One 8-bit output operand and one 8-bit result input  Two 8-bit output operands and one 8-bit result input  Two 8-bit output operands and one 16-bit result input  One 16-bit output operand and one 16-bit result input Six of the 32 registers can be used as three 16-bit address register pointers for data space addressing, enabling efficient address calculations. One of these address pointers can also be used as an address pointer for lookup tables in flash program memory. XMEGA D3 [DATASHEET] 12 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

7. Memories 7.1 Features  Flash program memory  One linear address space  In-system programmable  Self-programming and boot loader support  Application section for application code  Application table section for application code or data storage  Boot section for application code or boot loader code  Separate read/write protection lock bits for all sections  Built in fast CRC check of a selectable flash program memory section  Data memory  One linear address space  Single-cycle access from CPU  SRAM  EEPROM  Byte and page accessible  Optional memory mapping for direct load and store  I/O memory  Configuration and status registers for all peripherals and modules  Four bit-accessible general purpose registers for global variables or flags  Production signature row memory for factory programmed data  ID for each microcontroller device type  Serial number for each device  Calibration bytes for factory calibrated peripherals  User signature row  One flash page in size  Can be read and written from software  Content is kept after chip erase 7.2 Overview The Atmel AVR architecture has two main memory spaces, the program memory and the data memory. Executable code can reside only in the program memory, while data can be stored in the program memory and the data memory. The data memory includes the internal SRAM, and EEPROM for nonvolatile data storage. All memory spaces are linear and require no memory bank switching. Nonvolatile memory (NVM) spaces can be locked for further write and read/write operations. This prevents unrestricted access to the application software. A separate memory section contains the fuse bytes. These are used for configuring important system functions, and can only be written by an external programmer. The available memory size configurations are shown in “Ordering Information” on page 2. In addition, each device has a Flash memory signature row for calibration data, device identification, serial number etc. 7.3 Flash Program Memory The Atmel AVR XMEGA devices contain on-chip, in-system reprogrammable flash memory for program storage. The flash memory can be accessed for read and write from an external programmer through the PDI or from application software running in the device. All AVR CPU instructions are 16 or 32 bits wide, and each flash location is 16 bits wide. The flash memory is organized in two main sections, the application section and the boot loader section. The sizes of the different sections are fixed, but XMEGA D3 [DATASHEET] 13 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

device-dependent. These two sections have separate lock bits, and can have different levels of protection. The store program memory (SPM) instruction, which is used to write to the flash from the application software, will only operate when executed from the boot loader section. The application section contains an application table section with separate lock settings. This enables safe storage of nonvolatile data in the program memory. Figure 7-1. Flash Program Memory (hexadecimal address) Word address ATxmega 32D3 64D3 128D3 192D3 256D3 384D3 Application section 0 0 0 0 0 0 (32K/64K/128K/192K/256K/384K) ... 37FF 77FF EFFF 16FFF 1EFFF 2EFFF Application table section 3800 7800 F000 17000 1F000 2F000 (4K/4K/8K/8K/8K/8K) 3FFF 7FFF FFFF 17FFF 1FFFF 2FFFF 4000 8000 10000 18000 20000 30000 Boot section (4K/4K/8K/8K/8K/8K) 47FF 87FF 10FFF 18FFF 20FFF 30FFF 7.3.1 Application Section The application section is the section of the flash that is used for storing the executable application code. The protection level for the application section can be selected by the boot lock bits for this section. The application section can not store any boot loader code since the SPM instruction cannot be executed from the application section. 7.3.2 Application Table Section The application table section is a part of the application section of the flashmemory that can be used for storing data. The size is identical to the boot loader section. The protection level for the application table section can be selected by the boot lock bits for this section. The possibilities for different protection levels on the application section and the application table section enable safe parameter storage in the program memory. If this section is not used for data, application code can reside here. 7.3.3 Boot Loader Section While the application section is used for storing the application code, the boot loader software must be located in the boot loader section because the SPM instruction can only initiate programming when executing from this section. The SPM instruction can access the entire flash, including the boot loader section itself. The protection level for the boot loader section can be selected by the boot loader lock bits. If this section is not used for boot loader software, the application code can be stored here. 7.3.4 Production Signature Row The production signature row is a separate memory section for factory programmed data. It contains calibration data for functions such as oscillators and analog modules. Some of the calibration values will be automatically loaded to the corresponding module or peripheral unit during reset. Other values must be loaded from the signature row and written to the corresponding peripheral registers from software. For details on calibration conditions, refer to “Electrical Characteristics” on page 63. The production signature row also contains an ID that identifies each microcontroller device type and a serial number for each manufactured device. The serial number consists of the production lot number, wafer number, and wafer coordinates for the device. The device ID for the available devices is shown in Table 7-1 on page 15. XMEGA D3 [DATASHEET] 14 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

The production signature row cannot be written or erased, but it can be read from application software and external programmers. Table 7-1. Device ID Bytes Device Device ID bytes Byte 2 Byte 1 Byte 0 ATxmega32D3 4A 95 1E ATxmega64D3 4A 96 1E ATxmega128D3 48 97 1E ATxmega192D3 49 97 1E ATxmega256D3 44 98 1E ATxmega384D3 47 98 1E 7.3.5 User Signature Row The user signature row is a separate memory section that is fully accessible (read and write) from application software and external programmers. It is one flash page in size, and is meant for static user parameter storage, such as calibration data, custom serial number, identification numbers, random number seeds, etc. This section is not erased by chip erase commands that erase the flash, and requires a dedicated erase command. This ensures parameter storage during multiple program/erase operations and on-chip debug sessions. 7.4 Fuses and Lock Bits The fuses are used to configure important system functions, and can only be written from an external programmer. The application software can read the fuses. The fuses are used to configure reset sources such as brownout detector and watchdog, and startup configuration. The lock bits are used to set protection levels for the different flash sections (that is, if read and/or write access should be blocked). Lock bits can be written by external programmers and application software, but only to stricter protection levels. Chip erase is the only way to erase the lock bits. To ensure that flash contents are protected even during chip erase, the lock bits are erased after the rest of the flash memory has been erased. An unprogrammed fuse or lock bit will have the value one, while a programmed fuse or lock bit will have the value zero. Both fuses and lock bits are reprogrammable like the flash program memory. 7.5 Data Memory The data memory contains the I/O memory, internal SRAM, optionally memory mapped EEPROM, and external memory if available. The data memory is organized as one continuous memory section, see Figure 7-2 on page 16. To simplify development, I/O Memory, EEPROM and SRAM will always have the same start addresses for all Atmel AVR XMEGA devices. XMEGA D3 [DATASHEET] 15 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 7-2. Data Memory Map (hexadecimal address) Byte address ATxmega32D3 Byte address ATxmega64D3 0 0 I/O registers(4K) I/O registers(4K) FFF FFF 1000 1000 EEPROM(1K) EEPROM(2K) 17FF 17FF RESERVED RESERVED 2000 2000 Internal SRAM(4K) Internal SRAM(4K) 2FFF 2FFF Byte address ATxmega128D3 Byte address ATxmega192D3 0 0 I/O registers(4K) I/O registers(4K) FFF FFF 1000 1000 EEPROM(2K) EEPROM(2K) 17FF 17FF RESERVED RESERVED 2000 2000 Internal SRAM(8K) Internal SRAM(16K) 3FFF 5FFF Byte address ATxmega256D3 Byte address ATxmega384D3 0 0 I/O registers(4K) I/O registers(4K) FFF FFF 1000 1000 EEPROM(4K) EEPROM(4K) 1FFF 1FFF 2000 2000 Internal SRAM(16K) Internal SRAM(32K) 5FFF 9FFF 7.6 EEPROM All devices have EEPROM for nonvolatile data storage. It is either addressable in a separate data space (default) or memory mapped and accessed in normal data space. The EEPROM supports both byte and page access. Memory mapped EEPROM allows highly efficient EEPROM reading and EEPROM buffer loading. When doing this, EEPROM is accessible using load and store instructions. Memory mapped EEPROM will always start at hexadecimal address 0x1000. XMEGA D3 [DATASHEET] 16 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

7.7 I/O Memory The status and configuration registers for peripherals and modules, including the CPU, are addressable through I/O memory locations. All I/O locations can be accessed by the load (LD/LDS/LDD) and store (ST/STS/STD) instructions, which are used to transfer data between the 32 registers in the register file and the I/O memory. The IN and OUT instructions can address I/O memory locations in the range of 0x00 to 0x3F directly. In the address range 0x00 - 0x1F, single-cycle instructions for manipulation and checking of individual bits are available. The I/O memory address for all peripherals and modules is shown in the “Peripheral Module Address Map” on page 55. 7.7.1 General Purpose I/O Registers The lowest 16 I/O memory addresses are reserved as general purpose I/O registers. These registers can be used for storing global variables and flags, as they are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions. 7.8 Memory Timing Read and write access to the I/O memory takes one CPU clock cycle. A write to SRAM takes one cycle, and a read from SRAM takes two cycles. EEPROM page load (write) takes one cycle, and three cycles are required for read. For burst read, new data are available every second cycle. Refer to the instruction summary for more details on instructions and instruction timing. 7.9 Device ID and Revision Each device has a three-byte device ID. This ID identifies Atmel as the manufacturer of the device and the device type. A separate register contains the revision number of the device. 7.10 I/O Memory Protection Some features in the device are regarded as critical for safety in some applications. Due to this, it is possible to lock the I/O register related to the clock system, the event system, and the advanced waveform extensions. As long as the lock is enabled, all related I/O registers are locked and they can not be written from the application software. The lock registers themselves are protected by the configuration change protection mechanism. 7.11 Flash and EEPROM Page Size The flash program memory and EEPROM data memory are organized in pages. The pages are word accessible for the flash and byte accessible for the EEPROM. Table 7-2 on page 18 shows the Flash Program Memory organization and Program Counter (PC) size. Flash write and erase operations are performed on one page at a time, while reading the Flash is done one byte at a time. For Flash access the Z-pointer (Z[m:n]) is used for addressing. The most significant bits in the address (FPAGE) give the page number and the least significant address bits (FWORD) give the word in the page. XMEGA D3 [DATASHEET] 17 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Table 7-2. Number of Words and Pages in the Flash Devices PC size Flash size Page size FWORD FPAGE Application Boot No. of No. of [bits] [bytes] [words] Size Size pages pages ATxmega32D3 15 32K + 4K 128 Z[7:1] Z[15:7] 32K 128 4K 16 ATxmega64D3 16 64K + 4K 128 Z[7:1] Z[16:9] 64K 256 4K 16 ATxmega128D3 17 128K + 8K 256 Z[8:1] Z[17:9] 128K 256 8K 16 ATxmega192D3 17 192K + 8K 256 Z[8:1] Z[17:9] 192K 384 8K 16 ATxmega256D3 18 256K + 8K 256 Z[8:1] Z[18:9] 256K 512 8K 16 ATxmega384D3 18 384K + 8K 256 Z[8:1] Z[19:9] 384K 768 8K 16 Table 7-3 shows EEPROM memory organization. EEEPROM write and erase operations can be performed one page or one byte at a time, while reading the EEPROM is done one byte at a time. For EEPROM access the NVM address register (ADDR[m:n]) is used for addressing. The most significant bits in the address (E2PAGE) give the page number and the least significant address bits (E2BYTE) give the byte in the page. Table 7-3. Number of Bytes and Pages in the EEPROM Devices EEPROM Page size E2BYTE E2PAGE No. of pages size [bytes] ATxmega32D3 1K 32 ADDR[4:0] ADDR[10:5] 64 ATxmega64D3 2K 32 ADDR[4:0] ADDR[10:5] 64 ATxmega128D3 2K 32 ADDR[4:0] ADDR[10:5] 64 ATxmega192D3 2K 32 ADDR[4:0] ADDR[10:5] 64 ATxmega256D3 4K 32 ADDR[4:0] ADDR[11:5] 128 ATxmega384D3 4K 32 ADDR[4:0] ADDR[11:5] 128 XMEGA D3 [DATASHEET] 18 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

8. Event System 8.1 Features  System for direct peripheral-to-peripheral communication and signaling  Peripherals can directly send, receive, and react to peripheral events  CPU independent operation  100% predictable signal timing  Short and guaranteed response time  Four event channels for up to four different and parallel signal routing configurations  Events can be sent and/or used by most peripherals, clock system, and software  Additional functions include  Quadrature decoders  Digital filtering of I/O pin state  Works in active mode and idle sleep mode 8.2 Overview The event system enables direct peripheral-to-peripheral communication and signaling. It allows a change in one peripheral’s state to automatically trigger actions in other peripherals. It is designed to provide a predictable system for short and predictable response times between peripherals. It allows for autonomous peripheral control and interaction without the use of interrupts or CPU resources, and is thus a powerful tool for reducing the complexity, size and execution time of application code. It also allows for synchronized timing of actions in several peripheral modules. A change in a peripheral’s state is referred to as an event, and usually corresponds to the peripheral’s interrupt conditions. Events can be directly passed to other peripherals using a dedicated routing network called the event routing network. How events are routed and used by the peripherals is configured in software. Figure 8-1 shows a basic diagram of all connected peripherals. The event system can directly connect together analog to digital converter, analog comparators, I/O port pins, the real-time counter, timer/counters, and IR communication module (IRCOM). Events can also be generated from software and the peripheral clock. Figure 8-1. Event System Overview and Connected Peripherals CPU / Software Event Routing Network clk PER Prescaler ADC Event System Real Time Controller Counter AC Timer / Counters Port pins IRCOM The event routing network consists of four software-configurable multiplexers that control how events are routed and used. These are called event channels, and allow for up to four parallel event routing configurations. The maximum routing latency is two peripheral clock cycles. The event system works in both active mode and idle sleep mode. XMEGA D3 [DATASHEET] 19 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

9. System Clock and Clock Options 9.1 Features  Fast start-up time  Safe run-time clock switching  Internal oscillators:  32MHz run-time calibrated and tuneable oscillator  2MHz run-time calibrated oscillator  32.768kHz calibrated oscillator  32kHz ultra low power (ULP) oscillator with 1kHz output  External clock options  0.4MHz - 16MHz crystal oscillator  32.768kHz crystal oscillator  External clock  PLL with 20MHz - 128MHz output frequency  Internal and external clock options and 1× to 31× multiplication  Lock detector  Clock prescalers with 1× to 2048× division  Fast peripheral clocks running at two and four times the CPU clock  Automatic run-time calibration of internal oscillators  External oscillator and PLL lock failure detection with optional non-maskable interrupt 9.2 Overview Atmel AVR XMEGA D3 devices have a flexible clock system supporting a large number of clock sources. It incorporates both accurate internal oscillators and external crystal oscillator and resonator support. A high-frequency phase locked loop (PLL) and clock prescalers can be used to generate a wide range of clock frequencies. A calibration feature (DFLL) is available, and can be used for automatic run-time calibration of the internal oscillators to remove frequency drift over voltage and temperature. An oscillator failure monitor can be enabled to issue a non-maskable interrupt and switch to the internal oscillator if the external oscillator or PLL fails. When a reset occurs, all clock sources except the 32kHz ultra low power oscillator are disabled. After reset, the device will always start up running from the 2MHz internal oscillator. During normal operation, the system clock source and prescalers can be changed from software at any time. Figure 9-1 on page 21 presents the principal clock system. Not all of the clocks need to be active at a given time. The clocks for the CPU and peripherals can be stopped using sleep modes and power reduction registers, as described in “Power Management and Sleep Modes” on page 23. XMEGA D3 [DATASHEET] 20 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 9-1. The Clock System, Clock Sources, and Clock Distribution Real Time Non-Volatile Peripherals RAM AVR CPU Counter Memory clk PER clk clk PER2 CPU clk PER4 System Clock Prescalers Brown-out Watchdog Detector Timer clk clk SYS RTC System Clock Multiplexer RTCSRC (SCLKSEL) PLL D D D IV IV IV 3 3 3 2 2 2 PLLSRC XOSCSEL D IV 4 32kHz 32.768kHz 32.768kHz 0.4 –16MHz 32MHz 2MHz Int. ULP Int. OSC TOSC XTAL Int. Osc Int. Osc T T X X O O T T S S A A C C L L 1 2 1 2 9.3 Clock Sources The clock sources are divided in two main groups: internal oscillators and external clock sources. Most of the clock sources can be directly enabled and disabled from software, while others are automatically enabled or disabled, depending on peripheral settings. After reset, the device starts up running from the 2MHz internal oscillator. The other clock sources, DFLLs and PLL, are turned off by default. The internal oscillators do not require any external components to run. For details on characteristics and accuracy of the internal oscillators, refer to the device datasheet. XMEGA D3 [DATASHEET] 21 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

9.3.1 32kHz Ultra Low Power Internal Oscillator This oscillator provides an approximate 32kHz clock. The 32kHz ultra low power (ULP) internal oscillator is a very low power clock source, and it is not designed for high accuracy. The oscillator employs a built-in prescaler that provides a 1kHz output. The oscillator is automatically enabled/disabled when it is used as clock source for any part of the device. This oscillator can be selected as the clock source for the RTC. 9.3.2 32.768kHz Calibrated Internal Oscillator This oscillator provides an approximate 32.768kHz clock. It is calibrated during production to provide a default frequency close to its nominal frequency. The calibration register can also be written from software for run-time calibration of the oscillator frequency. The oscillator employs a built-in prescaler, which provides both a 32.768kHz output and a 1.024kHz output. 9.3.3 32.768kHz Crystal Oscillator A 32.768kHz crystal oscillator can be connected between the TOSC1 and TOSC2 pins and enables a dedicated low frequency oscillator input circuit. A low power mode with reduced voltage swing on TOSC2 is available. This oscillator can be used as a clock source for the system clock and RTC, and as the DFLL reference clock. 9.3.4 0.4 - 16MHz Crystal Oscillator This oscillator can operate in four different modes optimized for different frequency ranges, all within 0.4 - 16MHz. 9.3.5 2MHz Run-time Calibrated Internal Oscillator The 2MHz run-time calibrated internal oscillator is the default system clock source after reset. It is calibrated during production to provide a default frequency close to its nominal frequency. A DFLL can be enabled for automatic run-time calibration of the oscillator to compensate for temperature and voltage drift and optimize the oscillator accuracy. 9.3.6 32MHz Run-time Calibrated Internal Oscillator The 32MHz run-time calibrated internal oscillator is a high-frequency oscillator. It is calibrated during production to provide a default frequency close to its nominal frequency. A digital frequency looked loop (DFLL) can be enabled for automatic run-time calibration of the oscillator to compensate for temperature and voltage drift and optimize the oscillator accuracy. This oscillator can also be adjusted and calibrated to any frequency between 30MHz and 55MHz. 9.3.7 External Clock Sources The XTAL1 and XTAL2 pins can be used to drive an external oscillator, either a quartz crystal or a ceramic resonator. XTAL1 can be used as input for an external clock signal. The TOSC1 and TOSC2 pins is dedicated to driving a 32.768kHz crystal oscillator. 9.3.8 PLL with 1x-31x Multiplication Factor The built-in phase locked loop (PLL) can be used to generate a high-frequency system clock. The PLL has a user- selectable multiplication factor of from 1 to 31. In combination with the prescalers, this gives a wide range of output frequencies from all clock sources. XMEGA D3 [DATASHEET] 22 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

10. Power Management and Sleep Modes 10.1 Features  Power management for adjusting power consumption and functions  Five sleep modes  Idle  Power down  Power save  Standby  Extended standby  Power reduction register to disable clock and turn off unused peripherals in active and idle modes 10.2 Overview Various sleep modes and clock gating are provided in order to tailor power consumption to application requirements. This enables the Atmel AVR XMEGA microcontroller to stop unused modules to save power. All sleep modes are available and can be entered from active mode. In active mode, the CPU is executing application code. When the device enters sleep mode, program execution is stopped and interrupts or a reset is used to wake the device again. The application code decides which sleep mode to enter and when. Interrupts from enabled peripherals and all enabled reset sources can restore the microcontroller from sleep to active mode. In addition, power reduction registers provide a method to stop the clock to individual peripherals from software. When this is done, the current state of the peripheral is frozen, and there is no power consumption from that peripheral. This reduces the power consumption in active mode and idle sleep modes and enables much more fine-tuned power management than sleep modes alone. 10.3 Sleep Modes Sleep modes are used to shut down modules and clock domains in the microcontroller in order to save power. XMEGA microcontrollers have five different sleep modes tuned to match the typical functional stages during application execution. A dedicated sleep instruction (SLEEP) is available to enter sleep mode. Interrupts are used to wake the device from sleep, and the available interrupt wake-up sources are dependent on the configured sleep mode. When an enabled interrupt occurs, the device will wake up and execute the interrupt service routine before continuing normal program execution from the first instruction after the SLEEP instruction. If other, higher priority interrupts are pending when the wake-up occurs, their interrupt service routines will be executed according to their priority before the interrupt service routine for the wake-up interrupt is executed. After wake-up, the CPU is halted for four cycles before execution starts. The content of the register file, SRAM and registers are kept during sleep. If a reset occurs during sleep, the device will reset, start up, and execute from the reset vector. 10.3.1 Idle Mode In idle mode the CPU and nonvolatile memory are stopped (note that any ongoing programming will be completed), but all peripherals, including the interrupt controller and event system are kept running. Any enabled interrupt will wake the device. 10.3.2 Power-down Mode In power-down mode, all clocks, including the real-time counter clock source, are stopped. This allows operation only of asynchronous modules that do not require a running clock. The only interrupts that can wake up the MCU are the two- wire interface address match interrupt and asynchronous port interrupts. XMEGA D3 [DATASHEET] 23 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

10.3.3 Power-save Mode Power-save mode is identical to power down, with one exception. If the real-time counter (RTC) is enabled, it will keep running during sleep, and the device can also wake up from either an RTC overflow or compare match interrupt. 10.3.4 Standby Mode Standby mode is identical to power down, with the exception that the enabled system clock sources are kept running while the CPU, peripheral, and RTC clocks are stopped. This reduces the wake-up time. 10.3.5 Extended Standby Mode Extended standby mode is identical to power-save mode, with the exception that the enabled system clock sources are kept running while the CPU and peripheral clocks are stopped. This reduces the wake-up time. XMEGA D3 [DATASHEET] 24 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

11. System Control and Reset 11.1 Features  Reset the microcontroller and set it to initial state when a reset source goes active  Multiple reset sources that cover different situations  Power-on reset  External reset  Watchdog reset  Brownout reset  PDI reset  Software reset  Asynchronous operation  No running system clock in the device is required for reset  Reset status register for reading the reset source from the application code 11.2 Overview The reset system issues a microcontroller reset and sets the device to its initial state. This is for situations where operation should not start or continue, such as when the microcontroller operates below its power supply rating. If a reset source goes active, the device enters and is kept in reset until all reset sources have released their reset. The I/O pins are immediately tri-stated. The program counter is set to the reset vector location, and all I/O registers are set to their initial values. The SRAM content is kept. However, if the device accesses the SRAM when a reset occurs, the content of the accessed location can not be guaranteed. After reset is released from all reset sources, the default oscillator is started and calibrated before the device starts running from the reset vector address. By default, this is the lowest program memory address, 0, but it is possible to move the reset vector to the lowest address in the boot section. The reset functionality is asynchronous, and so no running system clock is required to reset the device. The software reset feature makes it possible to issue a controlled system reset from the user software. The reset status register has individual status flags for each reset source. It is cleared at power-on reset, and shows which sources have issued a reset since the last power-on. 11.3 Reset Sequence A reset request from any reset source will immediately reset the device and keep it in reset as long as the request is active. When all reset requests are released, the device will go through three stages before the device starts running again:  Reset counter delay  Oscillator startup  Oscillator calibration If another reset requests occurs during this process, the reset sequence will start over again. XMEGA D3 [DATASHEET] 25 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

11.4 Reset Sources 11.4.1 Power-on Reset A power-on reset (POR) is generated by an on-chip detection circuit. The POR is activated when the V rises and CC reaches the POR threshold voltage (V ), and this will start the reset sequence. POT The POR is also activated to power down the device properly when the V falls and drops below the V level. CC POT The V level is higher for falling V than for rising V . Consult the datasheet for POR characteristics data. POT CC CC 11.4.2 Brownout Detection The on-chip brownout detection (BOD) circuit monitors the V level during operation by comparing it to a fixed, CC programmable level that is selected by the BODLEVEL fuses. If disabled, BOD is forced on at the lowest level during chip erase and when the PDI is enabled. 11.4.3 External Reset The external reset circuit is connected to the external RESET pin. The external reset will trigger when the RESET pin is driven below the RESET pin threshold voltage, V , for longer than the minimum pulse period, t . The reset will be RST EXT held as long as the pin is kept low. The RESET pin includes an internal pull-up resistor. 11.4.4 Watchdog Reset The watchdog timer (WDT) is a system function for monitoring correct program operation. If the WDT is not reset from the software within a programmable timeout period, a watchdog reset will be given. The watchdog reset is active for one to two clock cycles of the 2MHz internal oscillator. For more details see “WDT – Watchdog Timer” on page 27. 11.4.5 Software Reset The software reset makes it possible to issue a system reset from software by writing to the software reset bit in the reset control register. The reset will be issued within two CPU clock cycles after writing the bit. It is not possible to execute any instruction from when a software reset is requested until it is issued. 11.4.6 Program and Debug Interface Reset The program and debug interface reset contains a separate reset source that is used to reset the device during external programming and debugging. This reset source is accessible only from external debuggers and programmers. XMEGA D3 [DATASHEET] 26 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

12. WDT – Watchdog Timer 12.1 Features  Issues a device reset if the timer is not reset before its timeout period  Asynchronous operation from dedicated oscillator  1kHz output of the 32kHz ultra low power oscillator  11 selectable timeout periods, from 8ms to 8s  Two operation modes:  Normal mode  Window mode  Configuration lock to prevent unwanted changes 12.2 Overview The watchdog timer (WDT) is a system function for monitoring correct program operation. It makes it possible to recover from error situations such as runaway or deadlocked code. The WDT is a timer, configured to a predefined timeout period, and is constantly running when enabled. If the WDT is not reset within the timeout period, it will issue a microcontroller reset. The WDT is reset by executing the WDR (watchdog timer reset) instruction from the application code. The window mode makes it possible to define a time slot or window inside the total timeout period duringwhich WDT must be reset. If the WDT is reset outside this window, either too early or too late, a system reset will be issued. Compared to the normal mode, this can also catch situations where a code error causes constant WDR execution. The WDT will run in active mode and all sleep modes, if enabled. It is asynchronous, runs from a CPU-independent clock source, and will continue to operate to issue a system reset even if the main clocks fail. The configuration change protection mechanism ensures that the WDT settings cannot be changed by accident. For increased safety, a fuse for locking the WDT settings is also available. XMEGA D3 [DATASHEET] 27 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

13. Interrupts and Programmable Multilevel Interrupt Controller 13.1 Features  Short and predictable interrupt response time  Separate interrupt configuration and vector address for each interrupt  Programmable multilevel interrupt controller  Interrupt prioritizing according to level and vector address  Three selectable interrupt levels for all interrupts: low, medium, and high  Selectable, round-robin priority scheme within low-level interrupts  Non-maskable interrupts for critical functions  Interrupt vectors optionally placed in the application section or the boot loader section 13.2 Overview Interrupts signal a change of state in peripherals, and this can be used to alter program execution. Peripherals can have one or more interrupts, and all are individually enabled and configured. When an interrupt is enabled and configured, it will generate an interrupt request when the interrupt condition is present. The programmable multilevel interrupt controller (PMIC) controls the handling and prioritizing of interrupt requests. When an interrupt request is acknowledged by the PMIC, the program counter is set to point to the interrupt vector, and the interrupt handler can be executed. All peripherals can select between three different priority levels for their interrupts: low, medium, and high. Interrupts are prioritized according to their level and their interrupt vector address. Medium-level interrupts will interrupt low-level interrupt handlers. High-level interrupts will interrupt both medium- and low-level interrupt handlers. Within each level, the interrupt priority is decided from the interrupt vector address, where the lowest interrupt vector address has the highest interrupt priority. Low-level interrupts have an optional round-robin scheduling scheme to ensure that all interrupts are serviced within a certain amount of time. Non-maskable interrupts (NMI) are also supported, and can be used for system critical functions. 13.3 Interrupt Vectors The interrupt vector is the sum of the peripheral’s base interrupt address and the offset address for specific interrupts in each peripheral. The base addresses for the Atmel AVR XMEGA D3 devices are shown in Table 13-1 on page 29. Offset addresses for each interrupt available in the peripheral are described for each peripheral in the XMEGA D manual. For peripherals or modules that have only one interrupt, the interrupt vector is shown in Table 13-1 on page 29. The program address is the word address. XMEGA D3 [DATASHEET] 28 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Table 13-1. Reset and Interrupt Vectors Program address (base address) Source Interrupt description 0x000 RESET 0x002 OSCF_INT_vect Crystal oscillator failure interrupt vector (NMI) 0x004 PORTC_INT_base Port C interrupt base 0x008 PORTR_INT_base Port R interrupt base 0x014 RTC_INT_base Real Time Counter Interrupt base 0x018 TWIC_INT_base Two-Wire Interface on Port C Interrupt base 0x01C TCC0_INT_base Timer/Counter 0 on port C Interrupt base 0x028 TCC1_INT_base Timer/Counter 1 on port C Interrupt base 0x030 SPIC_INT_vect SPI on port C Interrupt vector 0x032 USARTC0_INT_base USART 0 on port C Interrupt base 0x040 NVM_INT_base Non-Volatile Memory Interrupt base 0x044 PORTB_INT_base Port B Interrupt base 0x056 PORTE_INT_base Port E INT base 0x05A TWIE_INT_base Two-Wire Interface on Port E Interrupt base 0x05E TCE0_INT_base Timer/Counter 0 on port E Interrupt base 0x074 USARTE0_INT_base USART 0 on port E Interrupt base 0x080 PORTD_INT_base Port D Interrupt base 0x084 PORTA_INT_base Port A Interrupt base 0x088 ACA_INT_base Analog Comparator on Port A Interrupt base 0x08E ADCA_INT_base Analog to Digital Converter on Port A Interrupt base 0x09A TCD0_INT_base Timer/Counter 0 on port D Interrupt base 0x0AE SPID_INT_vector SPI D Interrupt vector 0x0B0 USARTD0_INT_base USART 0 on port D Interrupt base 0x0B6 USARTD1_INT_base USART 1 on port D Interrupt base 0x0D0 PORTF_INT_base Port F Interrupt base 0x0D8 TCF0_INT_base Timer/Counter 0 on port F Interrupt base XMEGA D3 [DATASHEET] 29 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

14. I/O Ports 14.1 Features  50 general purpose input and output pins with individual configuration  Output driver with configurable driver and pull settings:  Totem-pole  Wired-AND  Wired-OR  Bus-keeper  Inverted I/O  Input with synchronous and/or asynchronous sensing with interrupts and events  Sense both edges  Sense rising edges  Sense falling edges  Sense low level  Optional pull-up and pull-down resistor on input and Wired-OR/AND configuration  Asynchronous pin change sensing that can wake the device from all sleep modes  Two port interrupts with pin masking per I/O port  Efficient and safe access to port pins  Hardware read-modify-write through dedicated toggle/clear/set registers  Configuration of multiple pins in a single operation  Mapping of port registers into bit-accessible I/O memory space  Peripheral clocks output on port pin  Real-time counter clock output to port pin  Event channels can be output on port pin  Remapping of digital peripheral pin functions  Selectable USART, SPI, and timer/counter input/output pin locations 14.2 Overview One port consists of up to eight port pins: pin 0 to 7. Each port pin can be configured as input or output with configurable driver and pull settings. They also implement synchronous and asynchronous input sensing with interrupts and events for selectable pin change conditions. Asynchronous pin-change sensing means that a pin change can wake the device from all sleep modes, included the modes where no clocks are running. All functions are individual and configurable per pin, but several pins can be configured in a single operation. The pins have hardware read-modify-write (RMW) functionality for safe and correct change of drive value and/or pull resistor configuration. The direction of one port pin can be changed without unintentionally changing the direction of any other pin. The port pin configuration also controls input and output selection of other device functions. It is possible to have both the peripheral clock and the real-time clock output to a port pin, and available for external use. The same applies to events from the event system that can be used to synchronize and control external functions. Other digital peripherals, such as USART, SPI, and timer/counters, can be remapped to selectable pin locations in order to optimize pin-out versus application needs. The notation of the ports are PORTA, PORTB, PORTC, PORTD, PORTE, PORTF, and PORTR. XMEGA D3 [DATASHEET] 30 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

14.3 Output Driver All port pins (Pn) have programmable output configuration. 14.3.1 Push-pull Figure 14-1. I/O Configuration - Totem-pole DIRn OUTn Pn INn 14.3.2 Pull-down Figure 14-2. I/O Configuration - Totem-pole with Pull-down (on input) DIRn OUTn Pn INn 14.3.3 Pull-up Figure 14-3. I/O Configuration - Totem-pole with Pull-up (on input) DIRn OUTn Pn INn XMEGA D3 [DATASHEET] 31 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

14.3.4 Bus-keeper The bus-keeper’s weak output produces the same logical level as the last output level. It acts as a pull-up if the last level was ‘1’, and pull-down if the last level was ‘0’. Figure 14-4. I/O Configuration - Totem-pole with Bus-keeper DIRn OUTn Pn INn 14.3.5 Others Figure 14-5. Output Configuration - Wired-OR with Optional Pull-down OUTn Pn INn Figure 14-6. I/O Configuration - Wired-AND with Optional Pull-up INn Pn OUTn XMEGA D3 [DATASHEET] 32 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

14.4 Input Sensing Input sensing is synchronous or asynchronous depending on the enabled clock for the ports, and the configuration is shown in Figure 14-7. Figure 14-7. Input Sensing System Overview Asynchronous sensing EDGE DETECT Interrupt IRQ Control Synchronous sensing Pxn Synchronizer INn EDGE Synchronous D Q D Q DETECT Events R R INVERTED I/O Asynchronous Events When a pin is configured with inverted I/O, the pin value is inverted before the input sensing. 14.5 Alternate Port Functions Most port pins have alternate pin functions in addition to being a general purpose I/O pin. When an alternate function is enabled, it might override the normal port pin function or pin value. This happens when other peripherals that require pins are enabled or configured to use pins. If and how a peripheral will override and use pins is described in the section for that peripheral. “Pinout and Pin Functions” on page 50 shows which modules on peripherals that enable alternate functions on a pin, and which alternate functions that are available on a pin. XMEGA D3 [DATASHEET] 33 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

15. TC0/1 – 16-bit Timer/Counter Type 0 and 1 15.1 Features  Five 16-bit timer/counters  Four timer/counters of type 0  One timer/counter of type 1  Split-mode enabling two 8-bit timer/counter from each timer/counter type 0  32-bit timer/counter support by cascading two timer/counters  Up to four compare or capture (CC) channels  Four CC channels for timer/counters of type 0  Two CC channels for timer/counters of type 1  Double buffered timer period setting  Double buffered capture or compare channels  Waveform generation:  Frequency generation  Single-slope pulse width modulation  Dual-slope pulse width modulation  Input capture:  Input capture with noise cancelling  Frequency capture  Pulse width capture  32-bit input capture  Timer overflow and error interrupts/events  One compare match or input capture interrupt/event per CC channel  Can be used with event system for:  Quadrature decoding  Count and direction control  Capture  High-resolution extension  Increases frequency and waveform resolution by 4× (2-bit) or 8× (3-bit)  Advanced waveform extension:  Low- and high-side output with programmable dead-time insertion (DTI)  Event controlled fault protection for safe disabling of drivers 15.2 Overview Atmel AVR XMEGA D3 devices have a set of five flexible 16-bit timer/counters (TC). Their capabilities include accurate program execution timing, frequency and waveform generation, and input capture with time and frequency measurement of digital signals. Two timer/counters can be cascaded to create a 32-bit timer/counter with optional 32-bit capture. A timer/counter consists of a base counter and a set of compare or capture (CC) channels. The base counter can be used to count clock cycles or events. It has direction control and period setting that can be used for timing. The CC channels can be used together with the base counter to do compare match control, frequency generation, and pulse width waveform modulation, as well as various input capture operations. A timer/counter can be configured for either capture or compare functions, but cannot perform both at the same time. A timer/counter can be clocked and timed from the peripheral clock with optional prescaling or from the event system. The event system can also be used for direction control and capture trigger or to synchronize operations. XMEGA D3 [DATASHEET] 34 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

There are two differences between timer/counter type 0 and type 1. Timer/counter 0 has four CC channels, and timer/counter 1 has two CC channels. All information related to CC channels 3 and 4 is valid only for timer/counter 0. Only Timer/Counter 0 has the split mode feature that split it into two 8-bit Timer/Counters with four compare channels each. Some timer/counters have extensions to enable more specialized waveform and frequency generation. The advanced waveform extension (AWeX) is intended for motor control and other power control applications. It enables low- and high- side output with dead-time insertion, as well as fault protection for disabling and shutting down external drivers. It can also generate a synchronized bit pattern across the port pins. The advanced waveform extension can be enabled to provide extra and more advanced features for the Timer/Counter. This are only available for Timer/Counter 0. See “AWeX – Advanced Waveform Extension” on page 37 for more details. The high-resolution (hi-res) extension can be used to increase the waveform output resolution by four or eight times by using an internal clock source running up to four times faster than the peripheral clock. See “Hi-Res – High Resolution Extension” on page 38 for more details. Figure 15-1. Overview of a Timer/Counter and Closely Related Peripherals Timer/Counter Base Counter Prescaler clk PER Timer Period Control Logic Event Counter System clk PER4 Compare/Capture Channel D Compare/Capture Channel C AWeX Compare/Capture Channel B Compare/Capture Channel A Pattern es RT Dead-Time Generation R O - Comparator Capture Insertion Fault Hi P Control Protection Waveform Buffer Generation PORTC has one Timer/Counter 0 and one Timer/Counter1. PORTD, PORTE and PORTF each has one Timer/Counter 0. Notation of these are TCC0 (Time/Counter C0), TCC1, TCD0, TCE0, and TCF0, respectively. XMEGA D3 [DATASHEET] 35 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

16. TC2 – Timer/Counter Type 2 16.1 Features  Eight 8-bit timer/counters  Four Low-byte timer/counter  Four High-byte timer/counter  Up to eight compare channels in each Timer/Counter 2  Four compare channels for the low-byte timer/counter  Four compare channels for the high-byte timer/counter  Waveform generation  Single slope pulse width modulation  Timer underflow interrupts/events  One compare match interrupt/event per compare channel for the low-byte timer/counter  Can be used with the event system for count control 16.2 Overview There are four Timer/Counter 2. These are realized when a Timer/Counter 0 is set in split mode. It is then a system of two eight-bit timer/counters, each with four compare channels. This results in eight configurable pulse width modulation (PWM) channels with individually controlled duty cycles, and is intended for applications that require a high number of PWM channels. The two eight-bit timer/counters in this system are referred to as the low-byte timer/counter and high-byte timer/counter, respectively. The difference between them is that only the low-byte timer/counter can be used to generate compare match interrupts and events. The two eight-bit timer/counters have a shared clock source and separate period and compare settings. They can be clocked and timed from the peripheral clock, with optional prescaling, or from the event system. The counters are always counting down. PORTC, PORTD, PORTE, and PORTF each has one Timer/Counter 2. Notation of these are TCC2 (Timer/Counter C2), TCD2, TCE2, and TCF2, respectively. XMEGA D3 [DATASHEET] 36 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

17. AWeX – Advanced Waveform Extension 17.1 Features  Waveform output with complementary output from each compare channel  Four dead-time insertion (DTI) units  8-bit resolution  Separate high and low side dead-time setting  Double buffered dead time  Optionally halts timer during dead-time insertion  Pattern generation unit creating synchronised bit pattern across the port pins  Double buffered pattern generation  Optional distribution of one compare channel output across the port pins  Event controlled fault protection for instant and predictable fault triggering 17.2 Overview The advanced waveform extension (AWeX) provides extra functions to the timer/counter in waveform generation (WG) modes. It is primarily intended for use with different types of motor control and other power control applications. It enables low- and high side output with dead-time insertion and fault protection for disabling and shutting down external drivers. It can also generate a synchronized bit pattern across the port pins. Each of the waveform generator outputs from the timer/counter 0 are split into a complimentary pair of outputs when any AWeX features are enabled. These output pairs go through a dead-time insertion (DTI) unit that generates the non- inverted low side (LS) and inverted high side (HS) of the WG output with dead-time insertion between LS and HS switching. The DTI output will override the normal port value according to the port override setting. The pattern generation unit can be used to generate a synchronized bit pattern on the port it is connected to. In addition, the WG output from compare channel A can be distributed to and override all the port pins. When the pattern generator unit is enabled, the DTI unit is bypassed. The fault protection unit is connected to the event system, enabling any event to trigger a fault condition that will disable the AWeX output. The event system ensures predictable and instant fault reaction, and gives flexibility in the selection of fault triggers. The AWeX is available for TCC0. The notation of this is AWEXC. XMEGA D3 [DATASHEET] 37 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

18. Hi-Res – High Resolution Extension 18.1 Features  Increases waveform generator resolution up to 8× (three bits)  Supports frequency, single-slope PWM, and dual-slope PWM generation  Supports the AWeX when this is used for the same timer/counter 18.2 Overview The high-resolution (hi-res) extension can be used to increase the resolution of the waveform generation output from a timer/counter by four or eight. It can be used for a timer/counter doing frequency, single-slope PWM, or dual-slope PWM generation. It can also be used with the AWeX if this is used for the same timer/counter. The hi-res extension uses the peripheral 4× clock (Clk ). The system clock prescalers must be configured so the PER4 peripheral 4× clock frequency is four times higher than the peripheral and CPU clock frequency when the hi-res extension is enabled. There is one hi-res extensions that can be enabled for timer/counters pair on PORTC. The notation of this is HIRESC. XMEGA D3 [DATASHEET] 38 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

19. RTC – 16-bit Real-Time Counter 19.1 Features  16-bit resolution  Selectable clock source  32.768kHz external crystal  External clock  32.768kHz internal oscillator  32kHz internal ULP oscillator  Programmable 10-bit clock prescaling  One compare register  One period register  Clear counter on period overflow  Optional interrupt/event on overflow and compare match 19.2 Overview The 16-bit real-time counter (RTC) is a counter that typically runs continuously, including in low-power sleep modes, to keep track of time. It can wake up the device from sleep modes and/or interrupt the device at regular intervals. The reference clock is typically the 1.024kHz output from a high-accuracy crystal of 32.768kHz, and this is the configuration most optimized for low power consumption. The faster 32.768kHz output can be selected if the RTC needs a resolution higher than 1ms. The RTC can also be clocked from an external clock signal, the 32.768kHz internal oscillator or the 32kHz internal ULP oscillator. The RTC includes a 10-bit programmable prescaler that can scale down the reference clock before it reaches the counter. A wide range of resolutions and time-out periods can be configured. With a 32.768kHz clock source, the maximum resolution is 30.5µs, and time-out periods can range up to 2000 seconds. With a resolution of 1s, the maximum timeout period is more than18 hours (65536 seconds). The RTC can give a compare interrupt and/or event when the counter equals the compare register value, and an overflow interrupt and/or event when it equals the period register value. Figure 19-1. Real-time Counter Overview External Clock TOSC1 32.768kHz Crystal Osc TOSC2 32.768kHz Int. Osc 32kHz int ULP (DIV32) D D IV IV 3 3 2 2 PER RTCSRC TOP/ clk = RTC Overflow 10-bit CNT prescaler ”match”/ = Compare COMP XMEGA D3 [DATASHEET] 39 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

20. TWI – Two-Wire Interface 20.1 Features  Two Identical two-wire interface peripherals  Bidirectional, two-wire communication interface  Phillips I2C compatible  System Management Bus (SMBus) compatible  Bus master and slave operation supported  Slave operation  Single bus master operation  Bus master in multi-master bus environment  Multi-master arbitration  Flexible slave address match functions  7-bit and general call address recognition in hardware  10-bit addressing supported  Address mask register for dual address match or address range masking  Optional software address recognition for unlimited number of addresses  Slave can operate in all sleep modes, including power-down  Slave address match can wake device from all sleep modes  100kHz and 400kHz bus frequency support  Slew-rate limited output drivers  Input filter for bus noise and spike suppression  Support arbitration between start/repeated start and data bit (SMBus)  Slave arbitration allows support for address resolve protocol (ARP) (SMBus) 20.2 Overview The two-wire interface (TWI) is a bidirectional, two-wire communication interface. It is I2C and System Management Bus (SMBus) compatible. The only external hardware needed to implement the bus is one pull-up resistor on each bus line. A device connected to the bus must act as a master or a slave. The master initiates a data transaction by addressing a slave on the bus and telling whether it wants to transmit or receive data. One bus can have many slaves and one or several masters that can take control of the bus. An arbitration process handles priority if more than one master tries to transmit data at the same time. Mechanisms for resolving bus contention are inherent in the protocol. The TWI module supports master and slave functionality. The master and slave functionality are separated from each other, and can be enabled and configured separately. The master module supports multi-master bus operation and arbitration. It contains the baud rate generator. Both 100kHz and 400kHz bus frequency is supported. Quick command and smart mode can be enabled to auto-trigger operations and reduce software complexity. The slave module implements 7-bit address match and general address call recognition in hardware. 10-bit addressing is also supported. A dedicated address mask register can act as a second address match register or as a register for address range masking. The slave continues to operate in all sleep modes, including power-down mode. This enables the slave to wake up the device from all sleep modes on TWI address match. It is possible to disable the address matching to let this be handled in software instead. The TWI module will detect START and STOP conditions, bus collisions, and bus errors. Arbitration lost, errors, collision, and clock hold on the bus are also detected and indicated in separate status flags available in both master and slave modes. It is possible to disable the TWI drivers in the device, and enable a four-wire digital interface for connecting to an external TWI bus driver. This can be used for applications where the device operates from a different V voltage than used by CC the TWI bus. PORTC and PORTE each has one TWI. Notation of these peripherals are TWIC and TWIE. XMEGA D3 [DATASHEET] 40 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

21. SPI – Serial Peripheral Interface 21.1 Features  Two identical SPI peripherals  Full-duplex, three-wire synchronous data transfer  Master or slave operation  Lsb first or msb first data transfer  Eight programmable bit rates  Interrupt flag at the end of transmission  Write collision flag to indicate data collision  Wake up from idle sleep mode  Double speed master mode 21.2 Overview The Serial Peripheral Interface (SPI) is a high-speed synchronous data transfer interface using three or four pins. It allows fast communication between an Atmel AVR XMEGA device and peripheral devices or between several microcontrollers. The SPI supports full-duplex communication. A device connected to the bus must act as a master or slave. The master initiates and controls all data transactions. PORTC and PORTD each has one SPI. Notation of these peripherals are SPIC and SPID, respectively. XMEGA D3 [DATASHEET] 41 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

22. USART 22.1 Features  Three identical USART peripherals  Full-duplex operation  Asynchronous or synchronous operation  Synchronous clock rates up to 1/2 of the device clock frequency  Asynchronous clock rates up to 1/8 of the device clock frequency  Supports serial frames with 5, 6, 7, 8, or 9 data bits and 1 or 2 stop bits  Fractional baud rate generator  Can generate desired baud rate from any system clock frequency  No need for external oscillator with certain frequencies  Built-in error detection and correction schemes  Odd or even parity generation and parity check  Data overrun and framing error detection  Noise filtering includes false start bit detection and digital low-pass filter  Separate interrupts for  Transmit complete  Transmit data register empty  Receive complete  Multiprocessor communication mode  Addressing scheme to address a specific devices on a multidevice bus  Enable unaddressed devices to automatically ignore all frames  Master SPI mode  Double buffered operation  Operation up to 1/2 of the peripheral clock frequency  IRCOM module for IrDA compliant pulse modulation/demodulation 22.2 Overview The universal synchronous and asynchronous serial receiver and transmitter (USART) is a fast and flexible serial communication module. The USART supports full-duplex communication and asynchronous and synchronous operation. The USART can be configured to operate in SPI master mode and used for SPI communication. Communication is frame based, and the frame format can be customized to support a wide range of standards. The USART is buffered in both directions, enabling continued data transmission without any delay between frames. Separate interrupts for receive and transmit complete enable fully interrupt driven communication. Frame error and buffer overflow are detected in hardware and indicated with separate status flags. Even or odd parity generation and parity check can also be enabled. The clock generator includes a fractional baud rate generator that is able to generate a wide range of USART baud rates from any system clock frequencies. This removes the need to use an external crystal oscillator with a specific frequency to achieve a required baud rate. It also supports external clock input in synchronous slave operation. When the USART is set in master SPI mode, all USART-specific logic is disabled, leaving the transmit and receive buffers, shift registers, and baud rate generator enabled. Pin control and interrupt generation are identical in both modes. The registers are used in both modes, but their functionality differs for some control settings. An IRCOM module can be enabled for one USART to support IrDA 1.4 physical compliant pulse modulation and demodulation for baud rates up to 115.2kbps. PORTC, PORTD, and PORTE each has one USART. Notation of these peripherals are USARTC0, USARTD0, and USARTE0, respectively. XMEGA D3 [DATASHEET] 42 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

23. IRCOM – IR Communication Module 23.1 Features  Pulse modulation/demodulation for infrared communication  IrDA compatible for baud rates up to 115.2kbps  Selectable pulse modulation scheme  3/16 of the baud rate period  Fixed pulse period, 8-bit programmable  Pulse modulation disabled  Built-in filtering  Can be connected to and used by any USART 23.2 Overview Atmel AVR XMEGA devices contain an infrared communication module (IRCOM) that is IrDA compatible for baud rates up to 115.2kbps. It can be connected to any USART to enable infrared pulse encoding/decoding for that USART. XMEGA D3 [DATASHEET] 43 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

24. CRC – Cyclic Redundancy Check generator 24.1 Features  Cyclic redundancy check (CRC) generation and checking for  Communication data  Program or data in flash memory  Data in SRAM and I/O memory space  Integrated with flash memory and CPU  Automatic CRC of the complete or a selectable range of the flash memory  CPU can load data to the CRC generator through the I/O interface  CRC polynomial software selectable to  CRC-16 (CRC-CCITT)  CRC-32 (IEEE 802.3)  Zero remainder detection 24.2 Overview A cyclic redundancy check (CRC) is an error detection technique test algorithm used to find accidental errors in data, and it is commonly used to determine the correctness of a data transmission, and data present in the data and program memories. A CRC takes a data stream or a block of data as input and generates a 16- or 32-bit output that can be appended to the data and used as a checksum. When the same data are later received or read, the device or application repeats the calculation. If the new CRC result does not match the one calculated earlier, the block contains a data error. The application will then detect this and may take a corrective action, such as requesting the data to be sent again or simply not using the incorrect data. Typically, an n-bit CRC applied to a data block of arbitrary length will detect any single error burst not longer than n bits (any single alteration that spans no more than n bits of the data), and will detect the fraction 1-2-n of all longer error bursts. The CRC module in Atmel AVR XMEGA devices supports two commonly used CRC polynomials; CRC-16 (CRC- CCITT) and CRC-32 (IEEE802.3). CRC-16: Polynominal: x16+x12+x5+1 Hex value: 0x1021 CRC-32: Polynominal: x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x+1 Hex value: 0x04C11DB7 XMEGA D3 [DATASHEET] 44 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

25. ADC – 12-bit Analog to Digital Converter 25.1 Features  One Analog to Digital Converter (ADC)  12-bit resolution  Up to 300 thousand samples per second  Down to 2.3µs conversion time with 8-bit resolution  Down to 3.35µs conversion time with 12-bit resolution  Differential and single-ended input  16 single-ended inputs  16 * 4 differential inputs without gain  8 * 4 differential input with gain  Built-in differential gain stage  1/2×, 1×, 2×, 4×, 8×, 16×, 32×, and 64× gain options  Single, continuous and scan conversion options  Three internal inputs  Internal temperature sensor  AV voltage divided by 10 CC  1.1V bandgap voltage  Internal and external reference options  Compare function for accurate monitoring of user defined thresholds  Optional event triggered conversion for accurate timing  Optional interrupt/event on compare result 25.2 Overview The ADC converts analog signals to digital values. The ADC has 12-bit resolution and is capable of converting up to 300 thousand samples per second (ksps). The input selection is flexible, and both single-ended and differential measurements can be done. For differential measurements, an optional gain stage is available to increase the dynamic range. In addition, several internal signal inputs are available. The ADC can provide both signed and unsigned results. The ADC measurements can either be started by application software or an incoming event from another peripheral in the device. The ADC measurements can be started with predictable timing, and without software intervention. Both internal and external reference voltages can be used. An integrated temperature sensor is available for use with the ADC. The AV /10 and the bandgap voltage can also be measured by the ADC. CC The ADC has a compare function for accurate monitoring of user defined thresholds with minimum software intervention required. XMEGA D3 [DATASHEET] 45 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 25-1. ADC Overview Compare ADC0 (cid:129) Register (cid:129) (cid:129) V < INP ADC15 > Threshold (IntReq) Internal ADC CH0Result signals ADC0 (cid:129) V (cid:129) INN (cid:129) ADC7 Internal1.00V InternalAVCC/1.6V InternalAVCC/2 Reference AREFA Voltage AREFB The ADC may be configured for 8- or 12-bit result, reducing the minimum conversion time (propagation delay) from 3.35µs for 12-bit to 2.3µs for 8-bit result. ADC conversion results are provided left- or right adjusted with optional ‘1’ or ‘0’ padding. This eases calculation when the result is represented as a signed integer (signed 16-bit number). PORTA has one ADC. Notation of this peripheral is ADCA. XMEGA D3 [DATASHEET] 46 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

26. AC – Analog Comparator 26.1 Features  Two analog comparators (AC)  Selectable hysteresis  No  Small  Large  Analog comparator output available on pin  Flexible input selection  All pins on the port  Bandgap reference voltage  A 64-level programmable voltage scaler of the internal AV voltage CC  Interrupt and event generation on:  Rising edge  Falling edge  Toggle  Window function interrupt and event generation on:  Signal above window  Signal inside window  Signal below window  Constant current source with configurable output pin selection 26.2 Overview The analog comparator (AC) compares the voltage levels on two inputs and gives a digital output based on this comparison. The analog comparator may be configured to generate interrupt requests and/or events upon several different combinations of input change. The analog comparator hysteresis can be adjusted in order to achieve the optimal operation for each application. The input selection includes analog port pins, several internal signals, and a 64-level programmable voltage scaler. The analog comparator output state can also be output on a pin for use by external devices. A constant current source can be enabled and output on a selectable pin. This can be used to replace, for example, external resistors used to charge capacitors in capacitive touch sensing applications. The analog comparators are always grouped in pairs on each port. These are called analog comparator 0 (AC0) and analog comparator 1 (AC1). They have identical behavior, but separate control registers. Used as pair, they can be set in window mode to compare a signal to a voltage range instead of a voltage level. PORTA has one AC pair. Notation is ACA. XMEGA D3 [DATASHEET] 47 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 26-1. Analog Comparator Overview Pin Input + AC0OUT Pin Input - Hysteresis Enable Interrupt Interrupts Interrupt Sensititivity Voltage Mode Control ACnMUXCTRL ACnCTRL WINCTRL Scaler & Window Events Function Enable Bandgap Hysteresis + Pin Input AC1OUT - Pin Input The window function is realized by connecting the external inputs of the two analog comparators in a pair as shown in Figure 26-2. Figure 26-2. Analog Comparator Window Function + AC0 Upper limit of window - Interrupts Interrupt Input signal sensitivity Events control + AC1 Lower limit of window - XMEGA D3 [DATASHEET] 48 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

27. Programming and Debugging 27.1 Features  Programming  External programming through PDI interface  Minimal protocol overhead for fast operation  Built-in error detection and handling for reliable operation  Boot loader support for programming through any communication interface  Debugging  Nonintrusive, real-time, on-chip debug system  No software or hardware resources required from device except pin connection  Program flow control  Go, Stop, Reset, Step Into, Step Over, Step Out, Run-to-Cursor  Unlimited number of user program breakpoints  Unlimited number of user data breakpoints, break on:  Data location read, write, or both read and write  Data location content equal or not equal to a value  Data location content is greater or smaller than a value  Data location content is within or outside a range  No limitation on device clock frequency  Program and Debug Interface (PDI)  Two-pin interface for external programming and debugging  Uses the Reset pin and a dedicated pin  No I/O pins required during programming or debugging 27.2 Overview The Program and Debug Interface (PDI) is an Atmel proprietary interface for external programming and on-chip debugging of a device. The PDI supports fast programming of nonvolatile memory (NVM) spaces; flash, EEPOM, fuses, lock bits, and the user signature row. Debug is supported through an on-chip debug system that offers nonintrusive, real-time debug. It does not require any software or hardware resources except for the device pin connection. Using the Atmel tool chain, it offers complete program flow control and support for an unlimited number of program and complex data breakpoints. Application debug can be done from a C or other high-level language source code level, as well as from an assembler and disassembler level. Programming and debugging can be done through the PDI physical layer. This is a two-pin interface that uses the Reset pin for the clock input (PDI_CLK) and one other dedicated pin for data input and output (PDI_DATA). Any external programmer or on-chip debugger/emulator can be directly connected to this interface. XMEGA D3 [DATASHEET] 49 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

28. Pinout and Pin Functions The device pinout is shown in “Pinout/block Diagram” on page 5. In addition to general purpose I/O functionality, each pin can have several alternate functions. This will depend on which peripheral is enabled and connected to the actual pin. Only one of the pin functions can be used at time. 28.1 Alternate Pin Function Description The tables below show the notation for all pin functions available and describe its function. 28.1.1 Operation/power Supply V Digital supply voltage CC AV Analog supply voltage CC GND Ground 28.1.2 Port Interrupt Functions SYNC Port pin with full synchronous and limited asynchronous interrupt function ASYNC Port pin with full synchronous and full asynchronous interrupt function 28.1.3 Analog Functions ACn Analog comparator input pin n ACnOUT Analog comparator n output ADCn Analog to digital converter input pin n A Analog reference input pin REF 28.1.4 Timer/counter and AWEX Functions OCnxLS Output compare channel x low side for Timer/Counter n OCnxHS Output compare channel x high side for Timer/Counter n XMEGA D3 [DATASHEET] 50 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

28.1.5 Communication Functions SCL Serial Clock for TWI SDA Serial Data for TWI SCLIN Serial Clock In for TWI when external driver interface is enabled SCLOUT Serial Clock Out for TWI when external driver interface is enabled SDAIN Serial Data In for TWI when external driver interface is enabled SDAOUT Serial Data Out for TWI when external driver interface is enabled XCKn Transfer Clock for USART n RXDn Receiver Data for USART n TXDn Transmitter Data for USART n SS Slave Select for SPI MOSI Master Out Slave In for SPI MISO Master In Slave Out for SPI SCK Serial Clock for SPI 28.1.6 Oscillators, Clock, and Event TOSCn Timer Oscillator pin n XTALn Input/Output for Oscillator pin n CLKOUT Peripheral Clock Output EVOUT Event Channel Output RTCOUT RTC Clock Source Output 28.1.7 Debug/system Functions RESET Reset pin PDI_CLK Program and Debug Interface Clock pin PDI_DATA Program and Debug Interface Data pin 28.2 Alternate Pin Functions The tables below show the primary/default function for each pin on a port in the first column, the pin number in the second column, and then all alternate pin functions in the remaining columns. The head row shows what peripheral that enable and use the alternate pin functions. For better flexibility, some alternate functions also have selectable pin locations for their functions, this is noted under the first table where this apply. XMEGA D3 [DATASHEET] 51 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Table 28-1. Port A - Alternate Functions ADCA POS/ ADCA PORT A PIN # INTERRUPT GAINPOS ADCA NEG GAINNEG ACA POS ACA NEG ACA OUT REFA GND 60 AVCC 61 PA0 62 SYNC ADC0 ADC0 AC0 AC0 AREFA PA1 63 SYNC ADC1 ADC1 AC1 AC1 PA2 64 SYNC/ASYNC ADC2 ADC2 AC2 PA3 1 SYNC ADC3 ADC3 AC3 AC3 PA4 2 SYNC ADC4 ADC4 AC4 PA5 3 SYNC ADC5 ADC5 AC5 AC5 PA6 4 SYNC ADC6 ADC6 AC6 AC1OUT PA7 5 SYNC ADC7 ADC7 AC7 AC0OUT Table 28-2. Port B - Alternate Functions PORT B PIN # INTERRUPT ADCA POS REFB PB0 6 SYNC ADC8 AREFB PB1 7 SYNC ADC91 PB2 8 SYNC/ASYNC ADC10 PB3 9 SYNC ADC11 PB4 10 SYNC ADC12 PB5 11 SYNC ADC13 PB6 12 SYNC ADC14 PB7 13 SYNC ADC15 GND 14 VCC 15 Table 28-3. Port C - Alternate Functions PORT C PIN # INTERRUPT TCC0 (1)(2) AWEXC TCC1 USARTC0 (3) SPIC (4) TWIC CLOCKOUT (5) EVENTOUT (6) PC0 16 SYNC OC0A OC0ALS SDA PC1 17 SYNC OC0B OC0AHS XCK0 SCL PC2 18 SYNC/ASYNC OC0C OC0BLS RXD0 PC3 19 SYNC OC0D OC0BHS TXD0 PC4 20 SYNC OC0CLS OC1A SS PC5 21 SYNC OC0CHS OC1B MOSI XMEGA D3 [DATASHEET] 52 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

PORT C PIN # INTERRUPT TCC0 (1)(2) AWEXC TCC1 USARTC0 (3) SPIC (4) TWIC CLOCKOUT (5) EVENTOUT (6) PC6 22 SYNC OC0DLS MISO RTCOUT PC7 23 SYNC OC0DHS SCK clk EVOUT PER GND 24 VCC 25 Notes: 1. Pin mapping of all TC0 can optionally be moved to high nibble of port. 2. If TC0 is configured as TC2 all eight pins can be used for PWM output. 3. Pin mapping of all USART0 can optionally be moved to high nibble of port. 4. Pins MOSI and SCK for all SPI can optionally be swapped. 5. CLKOUT can optionally be moved between port C, D, and E and between pin 4 and 7. 6. EVOUT can optionally be moved between port C, D, and E and between pin 4 and 7. Table 28-4. Port D - Alternate Functions PORT D PIN # INTERRUPT TCD0 USARTD0 SPID CLOCKOUT EVENTOUT PD0 26 SYNC OC0A PD1 27 SYNC OC0B XCK0 PD2 28 SYNC/ASYNC OC0C RXD0 PD3 29 SYNC OC0D TXD0 PD4 30 SYNC SS PD5 31 SYNC MOSI PD6 32 SYNC MISO PD7 33 SYNC SCK Clk EVOUT PER GND 34 VCC 35 Table 28-5. Port E - Alternate Functions PORT E PIN # INTERRUPT TCE0 USARTE0 TOSC TWIE CLOCKOUT EVENTOUT PE0 36 SYNC OC0A SDA PE1 37 SYNC OC0B XCK0 SCL PE2 38 SYNC/ASYNC OC0C RXD0 PE3 39 SYNC OC0D TXD0 PE4 40 SYNC PE5 41 SYNC PE6 42 SYNC TOSC2 PE7 43 SYNC TOSC1 Clk EVOUT PER GND 44 VCC 45 XMEGA D3 [DATASHEET] 53 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Table 28-6. Port F - Alternate Functions PORT F PIN # INTERRUPT TCF0 PF0 46 SYNC OC0A PF1 47 SYNC OC0B PF2 48 SYNC/ASYNC OC0C PF3 49 SYNC OC0D PF4 50 SYNC PF5 51 SYNC PF6 54 SYNC PF7 55 SYNC GND 52 VCC 53 Table 28-7. Port R - Alternate Functions PORT R PIN # INTERRUPT PDI XTAL PDI 56 PDI_DATA RESET 57 PDI_CLOCK PRO 58 SYNC XTAL2 PR1 59 SYNC XTAL1 XMEGA D3 [DATASHEET] 54 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

29. Peripheral Module Address Map The address maps show the base address for each peripheral and module in Atmel AVR XMEGA D3. For complete register description and summary for each peripheral module, refer to the XMEGA D manual. Table 29-1. Peripheral Module Address Map Base address Name Description 0x0000 GPIO General Purpose IO Registers 0x0010 VPORT0 Virtual Port 0 0x0014 VPORT1 Virtual Port 1 0x0018 VPORT2 Virtual Port 2 0x001C VPORT3 Virtual Port 2 0x0030 CPU CPU 0x0040 CLK Clock Control 0x0048 SLEEP Sleep Controller 0x0050 OSC Oscillator Control 0x0060 DFLLRC32M DFLL for the 32MHz Internal Oscillator 0x0068 DFLLRC2M DFLL for the 2MHz Internal Oscillator 0x0070 PR Power Reduction 0x0078 RST Reset Controller 0x0080 WDT Watchdog Timer 0x0090 MCU MCU Control 0x00A0 PMIC Programmable Multilevel Interrupt Controller 0x00B0 PORTCFG Port Configuration 0x0180 EVSYS Event System 0x00D0 CRC CRC Module 0x01C0 NVM Non Volatile Memory (NVM) Controller 0x0200 ADCA Analog to Digital Converter on port A 0x0380 ACA Analog Comparator pair on port A 0x0400 RTC Real-Time Counter 0x0480 TWIC Two-Wire Interface on port C 0x04A0 TWIE Two-Wire Interface on port E 0x0600 PORTA Port A 0x0620 PORTB Port B 0x0640 PORTC Port C XMEGA D3 [DATASHEET] 55 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Base address Name Description 0x0660 PORTD Port D 0x0680 PORTE Port E 0x06A0 PORTF Port F 0x07E0 PORTR Port R 0x0800 TCC0 Timer/Counter 0 on port C 0x0840 TCC1 Timer/Counter 1 on port C 0x0880 AWEXC Advanced Waveform Extension on port C 0x0890 HIRESC High Resolution Extension on port C 0x08A0 USARTC0 USART 0 on port C 0x08C0 SPIC Serial Peripheral Interface on port C 0x08F8 IRCOM Infrared Communication Module 0x0900 TCD0 Timer/Counter 0 on port D 0x09A0 USARTD0 USART 0 on port D 0x09C0 SPID Serial Peripheral Interface on port D 0x0A00 TCE0 Timer/Counter 0 on port E 0x0A80 AWEXE Advanced Waveform Extension on port E 0x0AA0 USARTE0 USART 0 on port E 0x0AC0 SPIE Serial Peripheral Interface on port E 0x0B00 TCF0 Timer/Counter 0 on port F XMEGA D3 [DATASHEET] 56 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

30. Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks Arithmetic and logic instructions ADD Rd, Rr Add without Carry Rd  Rd + Rr Z,C,N,V,S,H 1 ADC Rd, Rr Add with Carry Rd  Rd + Rr + C Z,C,N,V,S,H 1 ADIW Rd, K Add Immediate to Word Rd  Rd + 1:Rd + K Z,C,N,V,S 2 SUB Rd, Rr Subtract without Carry Rd  Rd - Rr Z,C,N,V,S,H 1 SUBI Rd, K Subtract Immediate Rd  Rd - K Z,C,N,V,S,H 1 SBC Rd, Rr Subtract with Carry Rd  Rd - Rr - C Z,C,N,V,S,H 1 SBCI Rd, K Subtract Immediate with Carry Rd  Rd - K - C Z,C,N,V,S,H 1 SBIW Rd, K Subtract Immediate from Word Rd + 1:Rd  Rd + 1:Rd - K Z,C,N,V,S 2 AND Rd, Rr Logical AND Rd  Rd  Rr Z,N,V,S 1 ANDI Rd, K Logical AND with Immediate Rd  Rd  K Z,N,V,S 1 OR Rd, Rr Logical OR Rd  Rd v Rr Z,N,V,S 1 ORI Rd, K Logical OR with Immediate Rd  Rd v K Z,N,V,S 1 EOR Rd, Rr Exclusive OR Rd  Rd  Rr Z,N,V,S 1 COM Rd One’s Complement Rd  $FF - Rd Z,C,N,V,S 1 NEG Rd Two’s Complement Rd  $00 - Rd Z,C,N,V,S,H 1 SBR Rd, K Set Bit(s) in Register Rd  Rd v K Z,N,V,S 1 CBR Rd, K Clear Bit(s) in Register Rd  Rd  ($FFh - K) Z,N,V,S 1 INC Rd Increment Rd  Rd + 1 Z,N,V,S 1 DEC Rd Decrement Rd  Rd - 1 Z,N,V,S 1 TST Rd Test for Zero or Minus Rd  Rd  Rd Z,N,V,S 1 CLR Rd Clear Register Rd  Rd  Rd Z,N,V,S 1 SER Rd Set Register Rd  $FF None 1 MUL Rd, Rr Multiply Unsigned R1:R0  Rd x Rr (UU) Z,C 2 MULS Rd, Rr Multiply Signed R1:R0  Rd x Rr (SS) Z,C 2 MULSU Rd, Rr Multiply Signed with Unsigned R1:R0  Rd x Rr (SU) Z,C 2 FMUL Rd, Rr Fractional Multiply Unsigned R1:R0  Rd x Rr<<1 (UU) Z,C 2 FMULS Rd, Rr Fractional Multiply Signed R1:R0  Rd x Rr<<1 (SS) Z,C 2 FMULSU Rd, Rr Fractional Multiply Signed with Unsigned R1:R0  Rd x Rr<<1 (SU) Z,C 2 Branch instructions RJMP k Relative Jump PC  PC + k + 1 None 2 IJMP Indirect Jump to (Z) PC(15:0)  Z, None 2 PC(21:16)  0 EIJMP Extended Indirect Jump to (Z) PC(15:0)  Z, None 2 PC(21:16)  EIND JMP k Jump PC  k None 3 RCALL k Relative Call Subroutine PC  PC + k + 1 None 2 / 3 (1) ICALL Indirect Call to (Z) PC(15:0)  Z, None 2 / 3 (1) PC(21:16)  0 XMEGA D3 [DATASHEET] 57 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Mnemonics Operands Description Operation Flags #Clocks EICALL Extended Indirect Call to (Z) PC(15:0)  Z, None 3 (1) PC(21:16)  EIND CALL k call Subroutine PC  k None 3 / 4 (1) RET Subroutine Return PC  STACK None 4 / 5 (1) RETI Interrupt Return PC  STACK I 4 / 5 (1) CPSE Rd, Rr Compare, Skip if Equal if (Rd = Rr) PC  PC + 2 or 3 None 1 / 2 / 3 CP Rd, Rr Compare Rd - Rr Z,C,N,V,S,H 1 CPC Rd, Rr Compare with Carry Rd - Rr - C Z,C,N,V,S,H 1 CPI Rd, K Compare with Immediate Rd - K Z,C,N,V,S,H 1 SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b) = 0) PC  PC + 2 or 3 None 1 / 2 / 3 SBRS Rr, b Skip if Bit in Register Set if (Rr(b) = 1) PC  PC + 2 or 3 None 1 / 2 / 3 SBIC A, b Skip if Bit in I/O Register Cleared if (I/O(A,b) = 0) PC  PC + 2 or 3 None 2 / 3 / 4 SBIS A, b Skip if Bit in I/O Register Set If (I/O(A,b) =1) PC  PC + 2 or 3 None 2 / 3 / 4 BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC  PC + k + 1 None 1 / 2 BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC  PC + k + 1 None 1 / 2 BREQ k Branch if Equal if (Z = 1) then PC  PC + k + 1 None 1 / 2 BRNE k Branch if Not Equal if (Z = 0) then PC  PC + k + 1 None 1 / 2 BRCS k Branch if Carry Set if (C = 1) then PC  PC + k + 1 None 1 / 2 BRCC k Branch if Carry Cleared if (C = 0) then PC  PC + k + 1 None 1 / 2 BRSH k Branch if Same or Higher if (C = 0) then PC  PC + k + 1 None 1 / 2 BRLO k Branch if Lower if (C = 1) then PC  PC + k + 1 None 1 / 2 BRMI k Branch if Minus if (N = 1) then PC  PC + k + 1 None 1 / 2 BRPL k Branch if Plus if (N = 0) then PC  PC + k + 1 None 1 / 2 BRGE k Branch if Greater or Equal, Signed if (N  V= 0) then PC  PC + k + 1 None 1 / 2 BRLT k Branch if Less Than, Signed if (N  V= 1) then PC  PC + k + 1 None 1 / 2 BRHS k Branch if Half Carry Flag Set if (H = 1) then PC  PC + k + 1 None 1 / 2 BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC  PC + k + 1 None 1 / 2 BRTS k Branch if T Flag Set if (T = 1) then PC  PC + k + 1 None 1 / 2 BRTC k Branch if T Flag Cleared if (T = 0) then PC  PC + k + 1 None 1 / 2 BRVS k Branch if Overflow Flag is Set if (V = 1) then PC  PC + k + 1 None 1 / 2 BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC  PC + k + 1 None 1 / 2 BRIE k Branch if Interrupt Enabled if (I = 1) then PC  PC + k + 1 None 1 / 2 BRID k Branch if Interrupt Disabled if (I = 0) then PC  PC + k + 1 None 1 / 2 Data transfer instructions MOV Rd, Rr Copy Register Rd  Rr None 1 MOVW Rd, Rr Copy Register Pair Rd+1:Rd  Rr+1:Rr None 1 LDI Rd, K Load Immediate Rd  K None 1 LDS Rd, k Load Direct from data space Rd  (k) None 2 (1)(2) LD Rd, X Load Indirect Rd  (X) None 1 (1)(2) XMEGA D3 [DATASHEET] 58 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Mnemonics Operands Description Operation Flags #Clocks LD Rd, X+ Load Indirect and Post-Increment Rd  (X) None 1 (1)(2) X  X + 1 LD Rd, -X Load Indirect and Pre-Decrement X  X - 1,  X - 1 None 2 (1)(2) Rd  (X)  (X) LD Rd, Y Load Indirect Rd  (Y)  (Y) None 1 (1)(2) LD Rd, Y+ Load Indirect and Post-Increment Rd  (Y) None 1 (1)(2) Y  Y + 1 LD Rd, -Y Load Indirect and Pre-Decrement Y  Y - 1 None 2 (1)(2) Rd  (Y) LDD Rd, Y+q Load Indirect with Displacement Rd  (Y + q) None 2 (1)(2) LD Rd, Z Load Indirect Rd  (Z) None 1 (1)(2) LD Rd, Z+ Load Indirect and Post-Increment Rd  (Z), None 1 (1)(2) Z  Z+1 LD Rd, -Z Load Indirect and Pre-Decrement Z  Z - 1, None 2 (1)(2) Rd  (Z) LDD Rd, Z+q Load Indirect with Displacement Rd  (Z + q) None 2 (1)(2) STS k, Rr Store Direct to Data Space (k)  Rd None 2 (1) ST X, Rr Store Indirect (X)  Rr None 1 (1) ST X+, Rr Store Indirect and Post-Increment (X)  Rr, None 1 (1) X  X + 1 ST -X, Rr Store Indirect and Pre-Decrement X  X - 1, None 2 (1) (X)  Rr ST Y, Rr Store Indirect (Y)  Rr None 1 (1) ST Y+, Rr Store Indirect and Post-Increment (Y)  Rr, None 1 (1) Y  Y + 1 ST -Y, Rr Store Indirect and Pre-Decrement Y  Y - 1, None 2 (1) (Y)  Rr STD Y+q, Rr Store Indirect with Displacement (Y + q)  Rr None 2 (1) ST Z, Rr Store Indirect (Z)  Rr None 1 (1) ST Z+, Rr Store Indirect and Post-Increment (Z)  Rr None 1 (1) Z  Z + 1 ST -Z, Rr Store Indirect and Pre-Decrement Z  Z - 1 None 2 (1) STD Z+q, Rr Store Indirect with Displacement (Z + q)  Rr None 2 (1) LPM Load Program Memory R0  (Z) None 3 LPM Rd, Z Load Program Memory Rd  (Z) None 3 LPM Rd, Z+ Load Program Memory and Post-Increment Rd  (Z), None 3 Z  Z + 1 ELPM Extended Load Program Memory R0  (RAMPZ:Z) None 3 ELPM Rd, Z Extended Load Program Memory Rd  (RAMPZ:Z) None 3 ELPM Rd, Z+ Extended Load Program Memory and Post- Rd  (RAMPZ:Z), None 3 Increment Z  Z + 1 SPM Store Program Memory (RAMPZ:Z)  R1:R0 None - SPM Z+ Store Program Memory and Post-Increment by 2 (RAMPZ:Z)  R1:R0, None - Z  Z + 2 IN Rd, A In From I/O Location Rd  I/O(A) None 1 OUT A, Rr Out To I/O Location I/O(A)  Rr None 1 PUSH Rr Push Register on Stack STACK  Rr None 1 (1) POP Rd Pop Register from Stack Rd  STACK None 2 (1) XMEGA D3 [DATASHEET] 59 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Mnemonics Operands Description Operation Flags #Clocks Bit and bit-test instructions LSL Rd Logical Shift Left Rd(n+1)  Rd(n), Z,C,N,V,H 1 Rd(0)  0, LSR Rd Logical Shift Right Rd(n)  Rd(n+1), Z,C,N,V 1 Rd(7)  0, ROL Rd Rotate Left Through Carry Rd(0)  C, Z,C,N,V,H 1 Rd(n+1)  Rd(n), ROR Rd Rotate Right Through Carry Rd(7)  C, Z,C,N,V 1 Rd(n)  Rd(n+1), ASR Rd Arithmetic Shift Right Rd(n)  Rd(n+1), n=0..6 Z,C,N,V 1 SWAP Rd Swap Nibbles Rd(3..0)  Rd(7..4) None 1 BSET s Flag Set SREG(s)  1 SREG(s) 1 BCLR s Flag Clear SREG(s)  0 SREG(s) 1 SBI A, b Set Bit in I/O Register I/O(A, b)  1 None 1 CBI A, b Clear Bit in I/O Register I/O(A, b)  0 None 1 BST Rr, b Bit Store from Register to T T  Rr(b) T 1 BLD Rd, b Bit load from T to Register Rd(b)  T None 1 SEC Set Carry C  1 C 1 CLC Clear Carry C  0 C 1 SEN Set Negative Flag N  1 N 1 CLN Clear Negative Flag N  0 N 1 SEZ Set Zero Flag Z  1 Z 1 CLZ Clear Zero Flag Z  0 Z 1 SEI Global Interrupt Enable I  1 I 1 CLI Global Interrupt Disable I  0 I 1 SES Set Signed Test Flag S  1 S 1 CLS Clear Signed Test Flag S  0 S 1 SEV Set Two’s Complement Overflow V  1 V 1 CLV Clear Two’s Complement Overflow V  0 V 1 SET Set T in SREG T  1 T 1 CLT Clear T in SREG T  0 T 1 SEH Set Half Carry Flag in SREG H  1 H 1 CLH Clear Half Carry Flag in SREG H  0 H 1 MCU control instructions BREAK Break (See specific descr. for BREAK) None 1 NOP No Operation None 1 SLEEP Sleep (See specific descr. for Sleep) None 1 WDR Watchdog Reset (See specific descr. for WDR) None 1 Notes: 1. Cycle times for data memory accesses assume internal memory accesses, and are not valid for accesses via the external RAM interface. 2. One extra cycle must be added when accessing internal SRAM. XMEGA D3 [DATASHEET] 60 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

31. Packaging Information 31.1 64A PIN 1 B e PIN 1 IDENTIFIER E1 E D1 D C 0°~7° A1 A2 A L COMMON DIMENSIONS (Unit of measure = mm) SYMBOL MIN NOM MAX NOTE A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 15.75 16.00 16.25 D1 13.90 14.00 14.10 Note 2 E 15.75 16.00 16.25 Notes: E1 13.90 14.00 14.10 Note 2 1.This package conforms to JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable B 0.30 – 0.45 protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum C 0.09 – 0.20 plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10mm maximum. L 0.45 – 0.75 e 0.80 TYP 2010-10-20 TITLE DRAWING NO. REV. 2325 Orchard Parkway 64A, 64-lead, 14 x 14mm Body Size, 1.0mm Body Thickness, San Jose, CA 95131 64A C 0.8mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) XMEGA D3 [DATASHEET] 61 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

31.2 64M XMEGA D3 [DATASHEET] 62 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32. Electrical Characteristics All typical values are measured at T = 25C unless other temperature condition is given. All minimum and maximum values are valid across operating temperature and voltage unless other conditions are given. 32.1 Atmel ATxmega32D3 32.1.1 Absolute Maximum Ratings Stresses beyond those listed in Table 32-1 may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 32-1. Absolute Maximum Ratings Symbol Parameter Condition Min. Typ. Max. Units V Power supply voltage -0.3 4 V CC I Current into a V pin 200 VCC CC mA I Current out of a Gnd pin 200 GND V Pin voltage with respect to Gnd and V -0.5 V + 0.5 V PIN CC CC I I/O pin sink/source current -25 25 mA PIN T Storage temperature -65 150 A °C T Junction temperature 150 j 32.1.2 General Operating Ratings The device must operate within the ratings listed in Table 32-31 on page 82 in order for all other electrical characteristics and typical characteristics of the device to be valid. Table 32-2. General Operating Conditions Symbol Parameter Condition Min. Typ. Max. Units V Power supply voltage 1.60 3.6 CC V AV Analog supply voltage 1.60 3.6 CC T Temperature range -40 85 A °C T Junction temperature -40 105 j XMEGA D3 [DATASHEET] 63 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Table 32-3. Operating Voltage and Frequency Symbol Parameter Condition Min. Typ. Max. Units V = 1.6V 0 12 CC V = 1.8V 0 12 CC Clk CPU clock frequency MHz CPU V = 2.7V 0 32 CC V = 3.6V 0 32 CC The maximum CPU clock frequency depends on V . As shown in Figure 32-8 on page 83 the frequency vs. V curve is CC CC linear between 1.8V<V <2.7V. CC Figure 32-1. Maximum Frequency vs. V CC MHz 32 Safe operating area 12 1.6 1.8 2.7 3.6 V XMEGA D3 [DATASHEET] 64 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.1.3 Current Consumption Table 32-4. Current Consumption for Active Mode and Sleep Modes Symbol Parameter Condition Min. Typ. Max. Units V = 1.8V 50 CC 32kHz, Ext. Clk V = 3.0V 130 CC V = 1.8V 215 µA CC 1MHz, Ext. Clk Active power V = 3.0V 475 consumption (1) CC V = 1.8V 445 600 CC 2MHz, Ext. Clk 0.95 1.5 V = 3.0V mA CC 32MHz, Ext. Clk 7.8 12.0 V = 1.8V 2.8 CC 32kHz, Ext. Clk V = 3.0V 3 CC V = 1.8V 46 CC 1MHz, Ext. Clk µA Idle power V = 3.0V 92 consumption (1) CC V = 1.8V 93 225 CC 2MHz, Ext. Clk 184 350 V = 3.0V CC I 32MHz, Ext. Clk 2.9 5.0 mA CC T=25°C 0.07 1.0 T=85°C V = 3.0V 1.3 5.0 CC T=105°C 4.0 8.0 Power-down power consumption WDT and sampled BOD enabled, T=25°C 1.3 2.0 WDT and sampled BOD enabled, T = 85°C V = 3.0V 2.6 6.0 CC WDT and sampled BOD enabled, T= 105°C 5.0 10 V = 1.8V 1.7 µA RTC from ULP clock, WDT and sampled CC BOD enabled, T=25°C V = 3.0V 1.8 CC V = 1.8V 0.5 2.0 Power-save power RTC from 1.024kHz low power 32.768kHz CC consumption (2) TOSC, T=25°C V = 3.0V 0.7 2.0 CC V = 1.8V 0.9 3.0 RTC from low power 32.768kHz TOSC, CC T=25°C V = 3.0V 1.2 3.0 CC Reset power consumption Current through RESET pin substracted V = 3.0V 120 CC Notes: 1. All Power Reduction Registers set. 2. Maximum limits are based on characterization, and not tested in production. XMEGA D3 [DATASHEET] 65 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Table 32-5. Current Consumption for Modules and Peripherals Symbol Parameter Condition (1) Min. Typ. Max. Units ULP oscillator 0.9 32.768kHz int. oscillator 29 82 2MHz int. oscillator DFLL enabled with 32.768kHz int. osc. as reference 114 250 32MHz int. oscillator DFLL enabled with 32.768kHz int. osc. as reference 400 µA 20× multiplication factor, PLL 300 32MHz int. osc. DIV4 as reference Watchdog timer 1.0 Continuous mode 140 BOD Sampled mode, includes ULP oscillator 1.4 I CC Internal 1.0V reference 180 Temperature sensor 175 1.23 CURRLIMIT = LOW 1.1 16ksps V = Ext. ref. REF CURRLIMIT = MEDIUM 0.98 ADC CURRLIMIT = HIGH 0.87 mA 75ksps CURRLIMIT = LOW 1.7 V = Ext. ref. REF 300ksps 3.1 V = Ext. ref. REF USART Rx and Tx enabled, 9600 BAUD 9.7 µA Flash memory and EEPROM programming 5 mA Note: 1. All parameters measured as the difference in current consumption between module enabled and disabled. All data at V = 3.0V, Clk = 1MHz external clock CC SYS without prescaling, T = 25°C unless other conditions are given. XMEGA D3 [DATASHEET] 66 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.1.4 Wake-up Time from Sleep Modes Table 32-6. Device Wake-up Time from Sleep Modes with Various System Clock Sources Symbol Parameter Condition Min. Typ. (1) Max. Units External 2MHz clock 2.0 Wake-up time from idle, 32.768kHz internal oscillator 125 standby, and extended standby mode 2MHz internal oscillator 2.0 32MHz internal oscillator 0.2 t µs wakeup External 2MHz clock 4.6 32.768kHz internal oscillator 330 Wake-up time from power-save and power-down mode 2MHz internal oscillator 9.5 32MHz internal oscillator 5.6 Note: 1. The wake-up time is the time from the wake-up request is given until the peripheral clock is available on pin, see Figure 32-2. All peripherals and modules start execution from the first clock cycle, expect the CPU that is halted for four clock cycles before program execution starts. Figure 32-2. Wake-up Time Definition Wakeup time Wakeup request Clock output XMEGA D3 [DATASHEET] 67 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.1.5 I/O Pin Characteristics The I/O pins complies with the JEDEC LVTTL and LVCMOS specification and the high- and low-level input and output voltage limits reflect or exceed this specification. Table 32-7. I/O Pin Characteristics Symbol Parameter Condition Min. Typ. Max. Units I (1)/ I (2) I/O pin source/sink current -15 15 mA OH OL V = 2.4 - 3.6V 0.7 * V V + 0.5 CC CC CC V High level input voltage IH V = 1.6 - 2.4V 0.8 * V V + 0.5 CC CC CC V = 2.4 - 3.6V -0.5 0.3 * V CC CC V Low level input voltage IL V = 1.6 - 2.4V -0.5 0.2 * V CC CC V = 3.3V I = -4mA 2.6 2.9 CC OH V V High level output voltage V = 3.0V I = -3mA 2.1 2.6 OH CC OH V = 1.8V I = -1mA 1.4 1.6 CC OH V = 3.3V I = 8mA 0.4 0.76 CC OL V Low level output voltage V = 3.0V I = 5mA 0.3 0.64 OL CC OL V = 1.8V I = 3mA 0.2 0.46 CC OL I Input leakage current I/O pin T = 25°C <0.01 1 µA IN R Pull/buss keeper resistor 25 k P Notes: 1. The sum of all I for PORTA and PORTB must not exceed 100mA. OH The sum of all I for PORTC, PORTD, and PORTE must for each port not exceed 200mA. OH The sum of all I for pins PF[0-5] on PORTF must not exceed 200mA. OH The sum of all I for pins PF[6-7] on PORTF, PORTR, and PDI must not exceed 100mA. OL 2. The sum of all I for PORTA and PORTB must not exceed 100mA. OL The sum of all I for PORTC, PORTD, and PORTE must for each port not exceed 200mA. OL The sum of all I for pins PF[0-5] on PORTF must not exceed 200mA. OL The sum of all I for pins PF[6-7] on PORTF, PORTR, and PDI must not exceed 100mA. OL XMEGA D3 [DATASHEET] 68 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.1.6 ADC Characteristics Table 32-8. Power Supply, Reference, and Input Range Symbol Parameter Condition Min. Typ. Max. Units AV Analog supply voltage V - 0.3 V + 0.3 CC CC CC V V Reference voltage 1 AV - 0.6 REF CC R Input resistance Switched 4.5 k in C Input capacitance Switched 5 pF in R Reference input resistance (leakage only) >10 M AREF C Reference input capacitance Static load 7 pF AREF V Input range 0 V in REF Conversion range Differential mode, Vinp - Vinn -V V V REF REF Conversion range Single ended unsigned mode, Vinp -V V - V REF V Fixed offset voltage 200 lsb Table 32-9. Clock and Timing Symbol Parameter Condition Min. Typ. Max. Units Maximum is 1/4 of peripheral clock frequency 100 1800 Clk ADC clock frequency kHz ADC Measuring internal signals 100 125 f Sample rate 16 300 ClkADC Current limitation (CURRLIMIT) off 16 300 CURRLIMIT = LOW 16 250 ksps f Sample rate ADC CURRLIMIT = MEDIUM 16 150 CURRLIMIT = HIGH 16 50 Configurable in steps of 1/2 Clk cycle up Sampling time ADC 0.28 320 µs to 32 Clk cycles ADC (RES+2)/2 + 1 + GAIN Conversion time (latency) 5.5 10 RES (Resolution) = 8 or 12, GAIN = 0 to 3 Clk ADC Start-up time ADC clock cycles 12 24 cycles ADC settling time After changing reference or input mode 7 7 XMEGA D3 [DATASHEET] 69 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Table 32-10. Accuracy Characteristics Symbol Parameter Condition (2) Min. Typ. Max. Units Differential 8 12 12 RES Resolution 12-bit resolution Single ended signed 7 11 11 Bits Single ended unsigned 8 12 12 16ksps, V = 3V 0.5 1 REF 16ksps, all V 0.8 2 REF Differential mode 300ksps, V = 3V 0.6 1 REF INL (1) Integral non-linearity 300ksps, all V 1 2 REF 16ksps, V = 3.0V 0.5 1 Single ended REF unsigned mode 16ksps, all V 1.3 2 REF lsb 16ksps, V = 3V 0.3 1 REF 16ksps, all V 0.5 1 REF Differential mode 300ksps, V = 3V 0.3 1 REF DNL (1) Differential non-linearity 300ksps, all V 0.5 1 REF 16ksps, V = 3V 0.6 1 Single ended REF unsigned mode 16ksps, all V 0.6 1 REF 300ksps, V = 3V -7 mV REF Offset error Differential mode Temperature drift, V = 3V 0.01 mV/K REF Operating voltage drift 0.16 mV/V External reference -5 AV /1.6 -5 CC mV AV /2.0 -6 CC Gain error Differential mode Bandgap ±10 Temperature drift 0.02 mV/K Operating voltage drift 2 mV/V External reference -8 AV /1.6 -8 CC mV AV /2.0 -8 Single ended CC Gain error unsigned mode Bandgap ±10 Temperature drift 0.03 mV/K Operating voltage drift 2 mV/V Notes: 1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range. 2. Unless otherwise noted all linearity, offset and gain error numbers are valid under the condition that external VREF is used. XMEGA D3 [DATASHEET] 70 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Table 32-11. Gain Stage Characteristics Symbol Parameter Condition Min. Typ. Max. Units R Input resistance Switched in normal mode 4.0 k in C Input capacitance Switched in normal mode 4.4 pF sample Signal range Gain stage output 0 AV - 0.6 V CC Propagation delay ADC conversion rate 1/2 1 3 Clk cycles ADC Clock frequency Same as ADC 100 1800 kHz 0.5× gain, normal mode -1 1× gain, normal mode -1 Gain error % 8× gain, normal mode -1 64× gain, normal mode 5 0.5× gain, normal mode 10 1× gain, normal mode 5 Offset error, input mV referred 8× gain, normal mode -20 64× gain, normal mode -126 32.1.7 Analog Comparator Characteristics Table 32-12. Analog Comparator Characteristics Symbol Parameter Condition Min. Typ. Max. Units V Input offset voltage 10 mV off I Input leakage current <10 50 nA lk Input voltage range -0.1 AV V CC AC startup time 50 µs V Hysteresis, none V = 1.6V - 3.6V 0 hys1 CC V Hysteresis, small V = 1.6V - 3.6V 15 mV hys2 CC V Hysteresis, large V = 1.6V - 3.6V 30 hys3 CC V = 3.0V, T = 85°C 20 40 CC t Propagation delay ns delay V = 3.0V 17 CC 64-level voltage scaler Integral non-linearity (INL) 0.3 0.5 lsb Current source accuracy after calibration 5 % Current source calibration range Single mode 4 6 µA XMEGA D3 [DATASHEET] 71 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.1.8 Bandgap and Internal 1.0V Reference Characteristics Table 32-13. Bandgp and Internal 1.0V Reference Characteristics Symbol Parameter Condition Min. Typ. Max. Units As reference for ADC 1 Clk + 2.5µs PER Startup time µs As input voltage to ADC and AC 1.5 Bandgap voltage 1.1 V INT1V Internal 1.00V reference T = 85°C, after calibration 0.99 1 1.01 Variation over voltage and temperature Calibrated at T = 85°C 1 % 32.1.9 Brownout Detection Characteristics Table 32-14. Brownout Detection Characteristics (1) Symbol Parameter (BOD level 0 at 85°C) Condition Min. Typ. Max. Units BOD level 0 falling V 1.40 1.60 1.70 CC BOD level 1 falling V 1.8 CC BOD level 2 falling V 2.0 CC BOD level 3 falling V 2.2 CC V V BOT BOD level 4 falling V 2.4 CC BOD level 5 falling V 2.6 CC BOD level 6 falling V 2.8 CC BOD level 7 falling V 3.0 CC Continuous mode 0.4 t Detection time µs BOD Sampled mode 1000 V Hysteresis 1.0 % HYST Note: 1. BOD is calibrated at 85°C within BOD level 0 values, and BOD level 0 is the default level. 32.1.10External Reset Characteristics Table 32-15. External Reset Characteristics Symbol Parameter Condition Min. Typ. Max. Units t Minimum reset pulse width 1000 90 ns EXT V = 2.7 - 3.6V 0.45 * V CC CC V Reset threshold voltage V RST V = 1.6 - 2.7V 0.42 * V CC CC R Reset pin pull-up resistor 25 k RST XMEGA D3 [DATASHEET] 72 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.1.11 Power-on Reset Characteristics Table 32-16. Power-on Reset Characteristics Symbol Parameter Condition Min. Typ. Max. Units V falls faster than 1V/ms 0.4 1.0 CC V (1) POR threshold voltage falling V POT- CC V falls at 1V/ms or slower 0.8 1.3 V CC V POR threshold voltage rising V 1.3 1.59 POT+ CC Note: 1. V values are only valid when BOD is disabled. When BOD is enabled V = V . POT- POT- POT+ 32.1.12Flash and EEPROM Memory Characteristics Table 32-17. Endurance and Data Retention Symbol Parameter Condition Min. Typ. Max. Units 25°C 10K Write/Erase cycles 85°C 10K Cycle 105°C 2K Flash 25°C 100 Data retention 85°C 25 Year 105°C 10 25°C 100K Write/Erase cycles 85°C 100K Cycle 105°C 30K EEPROM 25°C 100 Data retention 85°C 25 Year 105°C 10 Table 32-18. Programming Time Symbol Parameter Condition Min. Typ. (1) Max. Units Chip erase (2) 32KB Flash, EEPROM 50 Application erase Section erase 6 Page erase 4 Flash Page write 4 ms Atomic page erase and write 8 Page erase 4 EEPROM Page write 4 Atomic page erase and write 8 Notes: 1. Programming is timed from the 2MHz internal oscillator. 2. EEPROM is not erased if the EESAVE fuse is programmed. XMEGA D3 [DATASHEET] 73 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.1.13 Clock and Oscillator Characteristics 32.1.13.1 Calibrated 32.768kHz Internal Oscillator Characteristics Table 32-19. 32.768kHz Internal Oscillator Characteristics Symbol Parameter Condition Min. Typ. Max. Units Frequency 32.768 kHz Factory calibration accuracy T = 85C, V = 3.0V -0.5 0.5 CC % User calibration accuracy -0.5 0.5 32.1.13.2 Calibrated 2MHz RC Internal Oscillator Characteristics Table 32-20. 2MHz Internal Oscillator Characteristics Symbol Parameter Condition Min. Typ. Max. Units DFLL can tune to this frequency over Frequency range 1.8 2.0 2.2 voltage and temperature MHz Factory calibrated frequency 2.0 Factory calibration accuracy T = 85C, V = 3.0V -1.5 1.5 CC User calibration accuracy -0.2 0.2 % DFLL calibration stepsize 0.18 32.1.13.3 Calibrated 32MHz Internal Oscillator Characteristics Table 32-21. 32MHz Internal Oscillator Characteristics Symbol Parameter Condition Min. Typ. Max. Units DFLL can tune to this frequency over Frequency range 30 32 55 voltage and temperature MHz Factory calibrated frequency 32 Factory calibration accuracy T = 85C, V = 3.0V -1.5 1.5 CC User calibration accuracy -0.2 0.2 % DFLL calibration step size 0.19 32.1.13.4 32kHz Internal ULP Oscillator Characteristics Table 32-22. 32kHz Internal ULP Oscillator Characteristics Symbol Parameter Condition Min. Typ. Max. Units Factory calibrated frequency 32 kHz Factory calibration accuracy T = 85°C, V = 3.0V -12 12 CC % Accuracy -30 30 XMEGA D3 [DATASHEET] 74 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.1.13.5 Internal Phase Locked Loop (PLL) Characteristics Table 32-23. Internal PLL Characteristics Symbol Parameter Condition Min. Typ. Max. Units f Input frequency Output frequency must be within f 0.4 64 IN OUT V = 1.6 - 1.8V 20 48 MHz CC f Output frequency (1) OUT V = 2.7 - 3.6V 20 128 CC Start-up time 25 µs Re-lock time 25 Note: 1. The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than four times the maximum CPU frequency. 32.1.13.6 External Clock Characteristics Figure 32-3. External Clock Drive Waveform t t CH CH t t CR CF V IH1 V IL1 t CL t CK Table 32-24. External Clock used as System Clock without Prescaling Symbol Parameter Condition Min. Typ. Max. Units V = 1.6 - 1.8V 0 12 CC 1/t Clock Frequency (1) MHz CK V = 2.7 - 3.6V 0 32 CC V = 1.6 - 1.8V 83.3 CC t Clock Period CK V = 2.7 - 3.6V 31.5 CC V = 1.6 - 1.8V 30.0 CC t Clock High Time CH V = 2.7 - 3.6V 12.5 CC V = 1.6 - 1.8V 30.0 CC t Clock Low Time ns CL V = 2.7 - 3.6V 12.5 CC V = 1.6 - 1.8V 10 CC t Rise Time (for maximum frequency) CR V = 2.7 - 3.6V 3 CC V = 1.6 - 1.8V 10 CC t Fall Time (for maximum frequency) CF V = 2.7 - 3.6V 3 CC t Change in period from one clock cycle to the next 10 % CK Note: 1. The maximum frequency vs. supply voltage is linear between 1.6V and 2.7V, and the same applies for all other parameters with supply voltage conditions. XMEGA D3 [DATASHEET] 75 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Table 32-25. External Clock with Prescaler (1) for System Clock Symbol Parameter Condition Min. Typ. Max. Units V = 1.6 - 1.8V 0 90 CC 1/t Clock Frequency (2) MHz CK V = 2.7 - 3.6V 0 142 CC V = 1.6 - 1.8V 11 CC t Clock Period CK V = 2.7 - 3.6V 7 CC V = 1.6 - 1.8V 4.5 CC t Clock High Time CH V = 2.7 - 3.6V 2.4 CC V = 1.6 - 1.8V 4.5 CC t Clock Low Time ns CL V = 2.7 - 3.6V 2.4 CC V = 1.6 - 1.8V 1.5 CC t Rise Time (for maximum frequency) CR V = 2.7 - 3.6V 1.0 CC V = 1.6 - 1.8V 1.5 CC t Fall Time (for maximum frequency) CF V = 2.7 - 3.6V 1.0 CC t Change in period from one clock cycle to the next 10 % CK Notes: 1. System Clock Prescalers must be set so that maximum CPU clock frequency for device is not exceeded. 2. The maximum frequency vs. supply voltage is linear between 1.6V and 2.7V, and the same applies for all other parameters with supply voltage conditions. 32.1.13.7 External 16MHz Crystal Oscillator and XOSC Characteristics Table 32-26. External 16MHz Crystal Oscillator and XOSC Characteristics Symbol Parameter Condition Min. Typ. Max. Units FRQRANGE=0 0 XOSCPWR=0 Cycle to cycle jitter FRQRANGE=1, 2, or 3 0 XOSCPWR=1 0 ns FRQRANGE=0 0 XOSCPWR=0 Long term jitter FRQRANGE=1, 2, or 3 0 XOSCPWR=1 0 FRQRANGE=0 0.03 XOSCPWR=0 FRQRANGE=1 0.03 Frequency error FRQRANGE=2 or 3 0.03 XOSCPWR=1 0.003 % FRQRANGE=0 50 XOSCPWR=0 FRQRANGE=1 50 Duty cycle FRQRANGE=2 or 3 50 XOSCPWR=1 50 XMEGA D3 [DATASHEET] 76 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Symbol Parameter Condition Min. Typ. Max. Units 0.4MHz resonator, 44k CL=100pF XOSCPWR=0, FRQRANGE=0 1MHz crystal, CL=20pF 67k 2MHz crystal, CL=20pF 67k 2MHz crystal 82k XOSCPWR=0, FRQRANGE=1, 8MHz crystal 1500 CL=20pF 9MHz crystal 1500 8MHz crystal 2700 XOSCPWR=0, R Negative impedance (1) Q FRQRANGE=2, 9MHz crystal 2700 CL=20pF 12MHz crystal 1000 9MHz crystal 3600 XOSCPWR=0, FRQRANGE=3, 12MHz crystal 1300  CL=20pF 16MHz crystal 590 9MHz crystal 390 XOSCPWR=1, FRQRANGE=0, 12MHz crystal 50 CL=20pF 16MHz crystal 10 9MHz crystal 1500 XOSCPWR=1, FRQRANGE=1, 12MHz crystal 650 CL=20pF 16MHz crystal 270 R Negative impedance (1) XOSCPWR=1, 12MHz crystal 1000 Q FRQRANGE=2, CL=20pF 16MHz crystal 440 XOSCPWR=1, 12MHz crystal 1300 FRQRANGE=3, CL=20pF 16MHz crystal 590 ESR SF = safety factor min(R )/SF k Q XOSCPWR=0, 0.4MHz resonator, 1.0 FRQRANGE=0 CL=100pF XOSCPWR=0, 2MHz crystal, CL=20pF 2.6 FRQRANGE=1 XOSCPWR=0, Start-up time 8MHz crystal, CL=20pF 0.8 ms FRQRANGE=2 XOSCPWR=0, 12MHz crystal, CL=20pF 1.0 FRQRANGE=3 XOSCPWR=1, 16MHz crystal, CL=20pF 1.4 FRQRANGE=3 XMEGA D3 [DATASHEET] 77 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Symbol Parameter Condition Min. Typ. Max. Units Parasitic capacitance C 5.9 XTAL1 XTAL1 pin Parasitic capacitance pF C 8.3 XTAL2 XTAL2 pin C Parasitic capacitance load 3.5 LOAD Note: 1. Numbers for negative impedance are not tested in production but guaranteed from design and characterization. 32.1.13.8 External 32.768kHz Crystal Oscillator and TOSC Characteristics Table 32-27. External 32.768kHz Crystal Oscillator and TOSC Characteristics Symbol Parameter Condition Min. Typ. Max. Units Crystal load capacitance 6.5pF 60 Recommended crystal equivalent ESR/R1 Crystal load capacitance 9.0pF 35 k series resistance (ESR) Crystal load capacitance 12pF 28 C Parasitic capacitance TOSC1 pin 3.5 TOSC1 pF C Parasitic capacitance TOSC2 pin 3.5 TOSC2 Capacitance load matched to crystal Recommended safety factor 3 specification Note: See Figure 32-11 on page 97 for definition. Figure 32-4. TOSC Input Capacitance C C L1 L2 Device internal TOSC1 TOSC2 External 32.768 kHz crystal The parasitic capacitance between the TOSC pins is C + C in series as seen from the crystal when oscillating without L1 L2 external capacitors. XMEGA D3 [DATASHEET] 78 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.1.14SPI Characteristics Figure 32-5. SPI Timing Requirements in Master Mode SS tMOS tSCKR tSCKF SCK (CPOL = 0) tSCKW SCK (CPOL = 1) tSCKW tMIS tMIH tSCK MISO MSB LSB (Data Input) tMOH tMOH MOSI MSB LSB (Data Output) Figure 32-6. SPI Timing Requirements in Slave Mode SS tSSS tSCKR tSCKF tSSH SCK (CPOL = 0) tSSCKW SCK (CPOL = 1) tSSCKW tSIS tSIH tSSCK MOSI MSB LSB (Data Input) tSOSSS tSOS tSOSSH MISO MSB LSB (Data Output) XMEGA D3 [DATASHEET] 79 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Table 32-28. SPI Timing Characteristics and Requirements Symbol Parameter Condition Min. Typ. Max. Units (See Table 20-3 in t SCK period Master SCK XMEGA D manual) t SCK high/low width Master 0.5 * SCK SCKW t SCK rise time Master 2.7 SCKR t SCK fall time Master 2.7 SCKF t MISO setup to SCK Master 10 MIS t MISO hold after SCK Master 10 MIH t MOSI setup SCK Master 0.5 * SCK MOS t MOSI hold after SCK Master 1 MOH t Slave SCK Period Slave 4 * tClk SSCK PER t SCK high/low width Slave 2 * tClk SSCKW PER ns t SCK rise time Slave 1600 SSCKR t SCK fall time Slave 1600 SSCKF t MOSI setup to SCK Slave 3 SIS t MOSI hold after SCK Slave tClk SIH PER t SS setup to SCK Slave 21 SSS t SS hold after SCK Slave 20 SSH t MISO setup SCK Slave 8 SOS t MISO hold after SCK Slave 13 SOH t MISO setup after SS low Slave 11 SOSS t MISO hold after SS high Slave 8 SOSH 32.1.15Two-wire Interface Characteristics Table 32-29 on page 81 describes the requirements for devices connected to the two-wire interface bus. The Atmel AVR XMEGA two-wire interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 32-7. Figure 32-7. Two-wire Interface Bus Timing t t of HIGH t t LOW r SCL t tSU;STA t HD;DAT tSU;DAT tSU;STO HD;STA SDA t BUF XMEGA D3 [DATASHEET] 80 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Table 32-29. Two-wire Interface Characteristics Symbol Parameter Condition Min. Typ. Max. Units V Input high voltage 0.7V V + 0.5 IH CC CC V Input low voltage -0.5 0.3V IL CC V V Hysteresis of Schmitt trigger inputs 0.05V (1) hys CC V Output low voltage 3mA, sink current 0 0.4 OL t Rise time for both SDA and SCL 20 + 0.1C (1)(2) 300 r b t Output fall time from V to V 10pF < C < 400pF (2) 20 + 0.1C (1)(2) 250 ns of IHmin ILmax b b t Spikes suppressed by input filter 0 50 SP I Input current for each I/O pin 0.1V < V < 0.9V -10 10 µA I CC I CC C Capacitance for each I/O pin 10 pF I f SCL clock frequency f (3)> max(10f , 250kHz) 0 400 kHz SCL PER SCL 100ns f  100kHz --------------- SCL C V –0.4V b R Value of pull-up resistor ----C----C--------------------  P fSCL > 100kHz 3mA 3----0--0----n---s-- C b f  100kHz 4.0 SCL t Hold time (repeated) START condition HD;STA f > 100kHz 0.6 SCL f  100kHz 4.7 SCL t Low period of SCL clock LOW f > 100kHz 1.3 SCL f  100kHz 4.0 SCL t High period of SCL clock HIGH f > 100kHz 0.6 SCL f  100kHz 4.7 Set-up time for a repeated START SCL t SU;STA condition f > 100kHz 0.6 SCL µs f  100kHz 0 3.45 SCL t Data hold time HD;DAT f > 100kHz 0 0.9 SCL f  100kHz 250 SCL t Data setup time SU;DAT f > 100kHz 100 SCL f  100kHz 4.0 SCL t Setup time for STOP condition SU;STO f > 100kHz 0.6 SCL f  100kHz 4.7 Bus free time between a STOP and SCL t BUF START condition f > 100kHz 1.3 SCL Notes: 1. Required only for f > 100kHz. SCL 2. C = Capacitance of one bus line in pF. b 3. f = Peripheral clock frequency. PER XMEGA D3 [DATASHEET] 81 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.2 Atmel ATxmega64D3 32.2.1 Absolute Maximum Ratings Stresses beyond those listed in Table 32-30 may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 32-30. Absolute Maximum Ratings Symbol Parameter Condition Min. Typ. Max. Units V Power supply voltage -0.3 4 V CC I Current into a V pin 200 VCC CC mA I Current out of a Gnd pin 200 GND V Pin voltage with respect to Gnd and V -0.5 V + 0.5 V PIN CC CC I I/O pin sink/source current -25 25 mA PIN T Storage temperature -65 150 A °C T Junction temperature 150 j 32.2.2 General Operating Ratings The device must operate within the ratings listed in Table 32-31 in order for all other electrical characteristics and typical characteristics of the device to be valid. Table 32-31. General Operating Conditions Symbol Parameter Condition Min. Typ. Max. Units V Power supply voltage 1.60 3.6 CC V AV Analog supply voltage 1.60 3.6 CC T Temperature range -40 85 A °C T Junction temperature -40 105 j Table 32-32. Operating Voltage and Frequency Symbol Parameter Condition Min. Typ. Max. Units V = 1.6V 0 12 CC V = 1.8V 0 12 CC Clk CPU clock frequency MHz CPU V = 2.7V 0 32 CC V = 3.6V 0 32 CC The maximum CPU clock frequency depends on V . As shown in Figure 32-8 on page 83 the frequency vs. V curve is CC CC linear between 1.8V<V <2.7V. CC XMEGA D3 [DATASHEET] 82 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 32-8. Maximum Frequency vs. V CC MHz 32 Safe operating area 12 1.6 1.8 2.7 3.6 V XMEGA D3 [DATASHEET] 83 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.2.3 Current Consumption Table 32-33. Current Consumption for Active Mode and Sleep Modes Symbol Parameter Condition Min. Typ. Max. Units V = 1.8V 50 CC 32kHz, Ext. Clk V = 3.0V 130 CC V = 1.8V 215 µA CC 1MHz, Ext. Clk Active power V = 3.0V 475 consumption (1) CC V = 1.8V 445 600 CC 2MHz, Ext. Clk 0.95 1.5 V = 3.0V mA CC 32MHz, Ext. Clk 7.8 12.0 V = 1.8V 2.8 CC 32kHz, Ext. Clk V = 3.0V 3 CC V = 1.8V 46 CC 1MHz, Ext. Clk µA Idle power V = 3.0V 92 consumption (1) CC V = 1.8V 93 225 CC 2MHz, Ext. Clk 184 350 V = 3.0V CC I 32MHz, Ext. Clk 2.9 5.0 mA CC T=25°C 0.07 1.0 T=85°C V = 3.0V 1.3 5.0 CC T=105°C 4.0 8.0 Power-down power consumption WDT and sampled BOD enabled, T=25°C 1.3 2.0 WDT and sampled BOD enabled, T = 85°C V = 3.0V 2.6 6.0 CC WDT and sampled BOD enabled, T= 105°C 5.0 10 V = 1.8V 1.7 µA RTC from ULP clock, WDT and sampled CC BOD enabled, T=25°C V = 3.0V 1.8 CC V = 1.8V 0.5 2.0 Power-save power RTC from 1.024kHz low power 32.768kHz CC consumption (2) TOSC, T=25°C V = 3.0V 0.7 2.0 CC V = 1.8V 0.9 3.0 RTC from low power 32.768kHz TOSC, CC T=25°C V = 3.0V 1.2 3.0 CC Reset power consumption Current through RESET pin substracted V = 3.0V 120 CC Notes: 1. All Power Reduction Registers set. 2. Maximum limits are based on characterization, and not tested in production. XMEGA D3 [DATASHEET] 84 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Table 32-34. Current Consumption for Modules and Peripherals Symbol Parameter Condition (1) Min. Typ. Max. Units ULP oscillator 0.9 32.768kHz int. oscillator 29 82 2MHz int. oscillator DFLL enabled with 32.768kHz int. osc. as reference 114 250 32MHz int. oscillator DFLL enabled with 32.768kHz int. osc. as reference 400 µA 20× multiplication factor, PLL 300 32MHz int. osc. DIV4 as reference Watchdog timer 1.0 Continuous mode 140 BOD Sampled mode, includes ULP oscillator 1.4 I CC Internal 1.0V reference 180 Temperature sensor 175 1.23 CURRLIMIT = LOW 1.1 16ksps V = Ext. ref. REF CURRLIMIT = MEDIUM 0.98 ADC CURRLIMIT = HIGH 0.87 mA 75ksps CURRLIMIT = LOW 1.7 V = Ext. ref. REF 300ksps 3.1 V = Ext. ref. REF USART Rx and Tx enabled, 9600 BAUD 9.7 µA Flash memory and EEPROM programming 5 mA Note: 1. All parameters measured as the difference in current consumption between module enabled and disabled. All data at V = 3.0V, Clk = 1MHz external clock CC SYS without prescaling, T = 25°C unless other conditions are given. XMEGA D3 [DATASHEET] 85 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.2.4 Wake-up Time from Sleep Modes Table 32-35. Device Wake-up Time from Sleep Modes with Various System Clock Sources Symbol Parameter Condition Min. Typ. (1) Max. Units External 2MHz clock 2.0 Wake-up time from idle, 32.768kHz internal oscillator 125 standby, and extended standby mode 2MHz internal oscillator 2.0 32MHz internal oscillator 0.2 t µs wakeup External 2MHz clock 4.6 32.768kHz internal oscillator 330 Wake-up time from power-save and power-down mode 2MHz internal oscillator 9.5 32MHz internal oscillator 5.6 Note: 1. The wake-up time is the time from the wake-up request is given until the peripheral clock is available on pin, see Figure 32-9. All peripherals and modules start execution from the first clock cycle, expect the CPU that is halted for four clock cycles before program execution starts. Figure 32-9. Wake-up Time Definition Wakeup time Wakeup request Clock output XMEGA D3 [DATASHEET] 86 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.2.5 I/O Pin Characteristics The I/O pins complies with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output voltage limits reflect or exceed this specification. Table 32-36. I/O Pin Characteristics Symbol Parameter Condition Min. Typ. Max. Units I (1)/ I (2) I/O pin source/sink current -15 15 mA OH OL V = 2.4 - 3.6V 0.7 * V V + 0.5 CC CC CC V High level input voltage IH V = 1.6 - 2.4V 0.8 * V V + 0.5 CC CC CC V = 2.4 - 3.6V -0.5 0.3 * V CC CC V Low level input voltage IL V = 1.6 - 2.4V -0.5 0.2 * V CC CC V = 3.3V I = -4mA 2.6 2.9 CC OH V V High level output voltage V = 3.0V I = -3mA 2.1 2.6 OH CC OH V = 1.8V I = -1mA 1.4 1.6 CC OH V = 3.3V I = 8mA 0.4 0.76 CC OL V Low level output voltage V = 3.0V I = 5mA 0.3 0.64 OL CC OL V = 1.8V I = 3mA 0.2 0.46 CC OL I Input leakage current I/O pin T = 25°C <0.01 1 µA IN R Pull/buss keeper resistor 25 k P Notes: 1. The sum of all I for PORTA and PORTB must not exceed 100mA. OH The sum of all I for PORTC, PORTD, and PORTE must for each port not exceed 200mA. OH The sum of all I for pins PF[0-5] on PORTF must not exceed 200mA. OH The sum of all I for pins PF[6-7] on PORTF, PORTR, and PDI must not exceed 100mA. OL 2. The sum of all I for PORTA and PORTB must not exceed 100mA. OL The sum of all I for PORTC, PORTD, and PORTE must for each port not exceed 200mA. OL The sum of all I for pins PF[0-5] on PORTF must not exceed 200mA. OL The sum of all I for pins PF[6-7] on PORTF, PORTR, and PDI must not exceed 100mA. OL XMEGA D3 [DATASHEET] 87 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.2.6 ADC Characteristics Table 32-37. Power Supply, Reference, and Input Range Symbol Parameter Condition Min. Typ. Max. Units AV Analog supply voltage V - 0.3 V + 0.3 CC CC CC V V Reference voltage 1 AV - 0.6 REF CC R Input resistance Switched 4.5 k in C Input capacitance Switched 5 pF in R Reference input resistance (leakage only) >10 M AREF C Reference input capacitance Static load 7 pF AREF V Input range 0 V in REF Conversion range Differential mode, Vinp - Vinn -V V V REF REF Conversion range Single ended unsigned mode, Vinp -V V - V REF V Fixed offset voltage 200 lsb Table 32-38. Clock and Timing Symbol Parameter Condition Min. Typ. Max. Units Maximum is 1/4 of peripheral clock frequency 100 1800 Clk ADC clock frequency kHz ADC Measuring internal signals 100 125 f Sample rate 16 300 ClkADC Current limitation (CURRLIMIT) off 16 300 CURRLIMIT = LOW 16 250 ksps f Sample rate ADC CURRLIMIT = MEDIUM 16 150 CURRLIMIT = HIGH 16 50 Configurable in steps of 1/2 Clk cycle up Sampling time ADC 0.28 320 µs to 32 Clk cycles ADC (RES+2)/2 + 1 + GAIN Conversion time (latency) 5.5 10 RES (Resolution) = 8 or 12, GAIN = 0 to 3 Clk ADC Start-up time ADC clock cycles 12 24 cycles ADC settling time After changing reference or input mode 7 7 XMEGA D3 [DATASHEET] 88 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Table 32-39. Accuracy Characteristics Symbol Parameter Condition (2) Min. Typ. Max. Units Differential 8 12 12 RES Resolution 12-bit resolution Single ended signed 7 11 11 Bits Single ended unsigned 8 12 12 16ksps, V = 3V 0.5 1 REF 16ksps, all V 0.8 2 REF Differential mode 300ksps, V = 3V 0.6 1 REF INL (1) Integral non-linearity 300ksps, all V 1 2 REF 16ksps, V = 3.0V 0.5 1 Single ended REF unsigned mode 16ksps, all V 1.3 2 REF lsb 16ksps, V = 3V 0.3 1 REF 16ksps, all V 0.5 1 REF Differential mode 300ksps, V = 3V 0.3 1 REF DNL (1) Differential non-linearity 300ksps, all V 0.5 1 REF 16ksps, V = 3V 0.6 1 Single ended REF unsigned mode 16ksps, all V 0.6 1 REF 300ksps, V = 3V -7 mV REF Offset error Differential mode Temperature drift, V = 3V 0.01 mV/K REF Operating voltage drift 0.16 mV/V External reference -5 AV /1.6 -5 CC mV AV /2.0 -6 CC Gain error Differential mode Bandgap ±10 Temperature drift 0.02 mV/K Operating voltage drift 2 mV/V External reference -8 AV /1.6 -8 CC mV AV /2.0 -8 Single ended CC Gain error unsigned mode Bandgap ±10 Temperature drift 0.03 mV/K Operating voltage drift 2 mV/V Notes: 1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range. 2. Unless otherwise noted all linearity, offset and gain error numbers are valid under the condition that external V is used. REF XMEGA D3 [DATASHEET] 89 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Table 32-40. Gain Stage Characteristics Symbol Parameter Condition Min. Typ. Max. Units R Input resistance Switched in normal mode 4.0 k in C Input capacitance Switched in normal mode 4.4 pF sample Signal range Gain stage output 0 AV - 0.6 V CC Propagation delay ADC conversion rate 1/2 1 3 Clk cycles ADC Clock frequency Same as ADC 100 1800 kHz 0.5× gain, normal mode -1 1× gain, normal mode -1 Gain error % 8× gain, normal mode -1 64× gain, normal mode 5 0.5× gain, normal mode 10 1× gain, normal mode 5 Offset error, input referred mV 8× gain, normal mode -20 64× gain, normal mode -126 32.2.7 Analog Comparator Characteristics Table 32-41. Analog Comparator Characteristics Symbol Parameter Condition Min. Typ. Max. Units V Input offset voltage 10 mV off I Input leakage current <10 50 nA lk Input voltage range -0.1 AV V CC AC startup time 50 µs V Hysteresis, none V = 1.6V - 3.6V 0 hys1 CC V Hysteresis, small V = 1.6V - 3.6V 15 mV hys2 CC V Hysteresis, large V = 1.6V - 3.6V 30 hys3 CC V = 3.0V, T = 85°C 20 40 CC t Propagation delay ns delay V = 3.0V 17 CC 64-level voltage scaler Integral non-linearity (INL) 0.3 0.5 lsb Current source accuracy after calibration 5 % Current source calibration range Single mode 4 6 µA XMEGA D3 [DATASHEET] 90 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.2.8 Bandgap and Internal 1.0V Reference Characteristics Table 32-42. Bandgap and Internal 1.0V Reference Characteristics Symbol Parameter Condition Min. Typ. Max. Units As reference for ADC 1 Clk + 2.5µs PER Startup time µs As input voltage to ADC and AC 1.5 Bandgap voltage 1.1 V INT1V Internal 1.00V reference T = 85°C, after calibration 0.99 1 1.01 Variation over voltage and temperature Calibrated at T = 85°C 1 % 32.2.9 Brownout Detection Characteristics Table 32-43. Brownout Detection Characteristics (1) Symbol Parameter (BOD level 0 at 85°C) Condition Min. Typ. Max. Units BOD level 0 falling V 1.40 1.60 1.70 CC BOD level 1 falling V 1.8 CC BOD level 2 falling V 2.0 CC BOD level 3 falling V 2.2 CC V V BOT BOD level 4 falling V 2.4 CC BOD level 5 falling V 2.6 CC BOD level 6 falling V 2.8 CC BOD level 7 falling V 3.0 CC Continuous mode 0.4 t Detection time µs BOD Sampled mode 1000 V Hysteresis 1.0 % HYST Note: 1. BOD is calibrated at 85°C within BOD level 0 values, and BOD level 0 is the default level. 32.2.10External Reset Characteristics Table 32-44. External Reset Characteristics Symbol Parameter Condition Min. Typ. Max. Units t Minimum reset pulse width 1000 90 ns EXT V = 2.7 - 3.6V 0.45 * V CC CC V Reset threshold voltage V RST V = 1.6 - 2.7V 0.42 * V CC CC R Reset pin pull-up resistor 25 k RST XMEGA D3 [DATASHEET] 91 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.2.11 Power-on Reset Characteristics Table 32-45. Power-on Reset Characteristics Symbol Parameter Condition Min. Typ. Max. Units V falls faster than 1V/ms 0.4 1.0 V (1) POR threshold voltage falling V CC POT- CC V falls at 1V/ms or slower 0.8 1.3 V CC V POR threshold voltage rising V 1.3 1.59 POT+ CC Note: 1. V values are only valid when BOD is disabled. When BOD is enabled V = V . POT- POT- POT+ 32.2.12Flash and EEPROM Memory Characteristics Table 32-46. Endurance and Data Retention Symbol Parameter Condition Min. Typ. Max. Units 25°C 10K Write/Erase cycles 85°C 10K Cycle 105°C 2K Flash 25°C 100 Data retention 85°C 25 Year 105°C 10 25°C 100K Write/Erase cycles 85°C 100K Cycle 105°C 30K EEPROM 25°C 100 Data retention 85°C 25 Year 105°C 10 Table 32-47. Programming Time Symbol Parameter Condition Min. Typ. (1) Max. Units Chip erase (2) 64KB Flash, EEPROM 55 Application erase Section erase 6 Page erase 4 Flash Page write 4 ms Atomic page erase and write 8 Page erase 4 EEPROM Page write 4 Atomic page erase and write 8 Notes: 1. Programming is timed from the 2MHz internal oscillator. 2. EEPROM is not erased if the EESAVE fuse is programmed. XMEGA D3 [DATASHEET] 92 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.2.13 Clock and Oscillator Characteristics 32.2.13.1 Calibrated 32.768kHz Internal Oscillator Characteristics Table 32-48. 32.768kHz Internal Oscillator Characteristics Symbol Parameter Condition Min. Typ. Max. Units Frequency 32.768 kHz Factory calibration accuracy T = 85C, V = 3.0V -0.5 0.5 CC % User calibration accuracy -0.5 0.5 32.2.13.2 Calibrated 2MHz RC Internal Oscillator Characteristics Table 32-49. 2MHz Internal Oscillator Characteristics Symbol Parameter Condition Min. Typ. Max. Units DFLL can tune to this frequency over Frequency range 1.8 2.0 2.2 voltage and temperature MHz Factory calibrated frequency 2.0 Factory calibration accuracy T = 85C, V = 3.0V -1.5 1.5 CC User calibration accuracy -0.2 0.2 % DFLL calibration stepsize 0.18 32.2.13.3 Calibrated 32MHz Internal Oscillator Characteristics Table 32-50. 32MHz Internal Oscillator Characteristics Symbol Parameter Condition Min. Typ. Max. Units DFLL can tune to this frequency over Frequency range 30 32 55 voltage and temperature MHz Factory calibrated frequency 32 Factory calibration accuracy T = 85C, V = 3.0V -1.5 1.5 CC User calibration accuracy -0.2 0.2 % DFLL calibration step size 0.19 32.2.13.4 32kHz Internal ULP Oscillator Characteristics Table 32-51. 32kHz Internal ULP Oscillator Characteristics Symbol Parameter Condition Min. Typ. Max. Units Factory calibrated frequency 32 kHz Factory calibration accuracy T = 85°C, V = 3.0V -12 12 CC % Accuracy -30 30 XMEGA D3 [DATASHEET] 93 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.2.13.5 Internal Phase Locked Loop (PLL) Characteristics Table 32-52. Internal PLL Characteristics Symbol Parameter Condition Min. Typ. Max. Units f Input frequency Output frequency must be within f 0.4 64 IN OUT V = 1.6 - 1.8V 20 48 MHz CC f Output frequency (1) OUT V = 2.7 - 3.6V 20 128 CC Start-up time 25 µs Re-lock time 25 Note: 1. The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than four times the maximum CPU frequency. 32.2.13.6 External Clock Characteristics Figure 32-10.External Clock Drive Waveform t t CH CH t t CR CF V IH1 V IL1 t CL t CK Table 32-53. External Clock used as System Clock without Prescaling Symbol Parameter Condition Min. Typ. Max. Units V = 1.6 - 1.8V 0 12 CC 1/t Clock Frequency (1) MHz CK V = 2.7 - 3.6V 0 32 CC V = 1.6 - 1.8V 83.3 CC t Clock Period CK V = 2.7 - 3.6V 31.5 CC V = 1.6 - 1.8V 30.0 CC t Clock High Time CH V = 2.7 - 3.6V 12.5 CC V = 1.6 - 1.8V 30.0 CC t Clock Low Time ns CL V = 2.7 - 3.6V 12.5 CC V = 1.6 - 1.8V 10 CC t Rise Time (for maximum frequency) CR V = 2.7 - 3.6V 3 CC V = 1.6 - 1.8V 10 CC t Fall Time (for maximum frequency) CF V = 2.7 - 3.6V 3 CC t Change in period from one clock cycle to the next 10 % CK Note: 1. The maximum frequency vs. supply voltage is linear between 1.6V and 2.7V, and the same applies for all other parameters with supply voltage conditions. XMEGA D3 [DATASHEET] 94 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Table 32-54. External Clock with Prescaler (1) for System Clock Symbol Parameter Condition Min. Typ. Max. Units V = 1.6 - 1.8V 0 90 CC 1/t Clock Frequency (2) MHz CK V = 2.7 - 3.6V 0 142 CC V = 1.6 - 1.8V 11 CC t Clock Period CK V = 2.7 - 3.6V 7 CC V = 1.6 - 1.8V 4.5 CC t Clock High Time CH V = 2.7 - 3.6V 2.4 CC V = 1.6 - 1.8V 4.5 CC t Clock Low Time ns CL V = 2.7 - 3.6V 2.4 CC V = 1.6 - 1.8V 1.5 CC t Rise Time (for maximum frequency) CR V = 2.7 - 3.6V 1.0 CC V = 1.6 - 1.8V 1.5 CC t Fall Time (for maximum frequency) CF V = 2.7 - 3.6V 1.0 CC t Change in period from one clock cycle to the next 10 % CK Notes: 1. System Clock Prescalers must be set so that maximum CPU clock frequency for device is not exceeded. 2. The maximum frequency vs. supply voltage is linear between 1.6V and 2.7V, and the same applies for all other parameters with supply voltage conditions. 32.2.13.7 External 16MHz Crystal Oscillator and XOSC Characteristics Table 32-55. External 16MHz Crystal Oscillator and XOSC Characteristics Symbol Parameter Condition Min. Typ. Max. Units FRQRANGE=0 0 XOSCPWR=0 Cycle to cycle jitter FRQRANGE=1, 2, or 3 0 XOSCPWR=1 0 ns FRQRANGE=0 0 XOSCPWR=0 Long term jitter FRQRANGE=1, 2, or 3 0 XOSCPWR=1 0 FRQRANGE=0 0.03 XOSCPWR=0 FRQRANGE=1 0.03 Frequency error FRQRANGE=2 or 3 0.03 XOSCPWR=1 0.003 % FRQRANGE=0 50 XOSCPWR=0 FRQRANGE=1 50 Duty cycle FRQRANGE=2 or 3 50 XOSCPWR=1 50 XMEGA D3 [DATASHEET] 95 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Symbol Parameter Condition Min. Typ. Max. Units 0.4MHz resonator, CL=100pF 44k XOSCPWR=0, 1MHz crystal, CL=20pF 67k FRQRANGE=0 2MHz crystal, CL=20pF 67k 2MHz crystal 82k XOSCPWR=0, FRQRANGE=1, 8MHz crystal 1500 CL=20pF 9MHz crystal 1500 8MHz crystal 2700 XOSCPWR=0, FRQRANGE=2, 9MHz crystal 2700 CL=20pF 12MHz crystal 1000 9MHz crystal 3600 XOSCPWR=0, FRQRANGE=3, 12MHz crystal 1300 R Negative impedance (1) CL=20pF  Q 16MHz crystal 590 9MHz crystal 390 XOSCPWR=1, FRQRANGE=0, 12MHz crystal 50 CL=20pF 16MHz crystal 10 9MHz crystal 1500 XOSCPWR=1, FRQRANGE=1, 12MHz crystal 650 CL=20pF 16MHz crystal 270 XOSCPWR=1, 12MHz crystal 1000 FRQRANGE=2, CL=20pF 16MHz crystal 440 XOSCPWR=1, 12MHz crystal 1300 FRQRANGE=3, CL=20pF 16MHz crystal 590 ESR SF = safety factor min(R )/SF k Q XOSCPWR=0, 0.4MHz resonator, CL=100pF 1.0 FRQRANGE=0 XOSCPWR=0, 2MHz crystal, CL=20pF 2.6 FRQRANGE=1 XOSCPWR=0, Start-up time 8MHz crystal, CL=20pF 0.8 ms FRQRANGE=2 XOSCPWR=0, 12MHz crystal, CL=20pF 1.0 FRQRANGE=3 XOSCPWR=1, 16MHz crystal, CL=20pF 1.4 FRQRANGE=3 XMEGA D3 [DATASHEET] 96 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Symbol Parameter Condition Min. Typ. Max. Units Parasitic capacitance C 5.9 XTAL1 XTAL1 pin Parasitic capacitance pF C 8.3 XTAL2 XTAL2 pin C Parasitic capacitance load 3.5 LOAD Note: 1. Numbers for negative impedance are not tested in production but guaranteed from design and characterization. 32.2.13.8 External 32.768kHz Crystal Oscillator and TOSC Characteristics Table 32-56. External 32.768kHz Crystal Oscillator and TOSC Characteristics Symbo l Parameter Condition Min. Typ. Max. Units Crystal load capacitance 6.5pF 60 ESR/ Recommended crystal equivalent Crystal load capacitance 9.0pF 35 k R1 series resistance (ESR) Crystal load capacitance 12pF 28 C Parasitic capacitance TOSC1 pin 3.5 TOSC1 pF C Parasitic capacitance TOSC2 pin 3.5 TOSC2 Capacitance load matched to crystal Recommended safety factor 3 specification Note: See Figure 32-11 for definition. Figure 32-11.TOSC Input Capacitance C C L1 L2 Device internal TOSC1 TOSC2 External 32.768 kHz crystal The parasitic capacitance between the TOSC pins is C + C in series as seen from the crystal when oscillating without L1 L2 external capacitors. XMEGA D3 [DATASHEET] 97 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.2.14 SPI Characteristics Figure 32-12.SPI Timing Requirements in Master Mode SS tMOS tSCKR tSCKF SCK (CPOL = 0) tSCKW SCK (CPOL = 1) tSCKW tMIS tMIH tSCK MISO MSB LSB (Data Input) tMOH tMOH MOSI MSB LSB (Data Output) Figure 32-13.SPI Timing Requirements in Slave Mode SS tSSS tSCKR tSCKF tSSH SCK (CPOL = 0) tSSCKW SCK (CPOL = 1) tSSCKW tSIS tSIH tSSCK MOSI MSB LSB (Data Input) tSOSSS tSOS tSOSSH MISO MSB LSB (Data Output) XMEGA D3 [DATASHEET] 98 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Table 32-57. SPI Timing Characteristics and Requirements Symbol Parameter Condition Min. Typ. Max. Units (See Table 20-3 in t SCK period Master SCK XMEGA D manual) t SCK high/low width Master 0.5 * SCK SCKW t SCK rise time Master 2.7 SCKR t SCK fall time Master 2.7 SCKF t MISO setup to SCK Master 10 MIS t MISO hold after SCK Master 10 MIH t MOSI setup SCK Master 0.5 * SCK MOS t MOSI hold after SCK Master 1 MOH t Slave SCK Period Slave 4 * tClk SSCK PER t SCK high/low width Slave 2 * tClk SSCKW PER ns t SCK rise time Slave 1600 SSCKR t SCK fall time Slave 1600 SSCKF t MOSI setup to SCK Slave 3 SIS t MOSI hold after SCK Slave tClk SIH PER t SS setup to SCK Slave 21 SSS t SS hold after SCK Slave 20 SSH t MISO setup SCK Slave 8 SOS t MISO hold after SCK Slave 13 SOH t MISO setup after SS low Slave 11 SOSS t MISO hold after SS high Slave 8 SOSH 32.2.15Two-wire Interface Characteristics Table 32-58 on page 100 describes the requirements for devices connected to the two-wire interface bus. The Atmel AVR XMEGA two-wire interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 32-14. Figure 32-14.Two-wire Interface Bus Timing t t of HIGH t t LOW r SCL t tSU;STA t HD;DAT tSU;DAT tSU;STO HD;STA SDA t BUF XMEGA D3 [DATASHEET] 99 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Table 32-58. Two-wire Interface Characteristics Symbol Parameter Condition Min. Typ. Max. Units V Input high voltage 0.7V V + 0.5 IH CC CC V Input low voltage -0.5 0.3V IL CC V V Hysteresis of Schmitt trigger inputs 0.05V (1) hys CC V Output low voltage 3mA, sink current 0 0.4 OL t Rise time for both SDA and SCL 20 + 0.1C (1)(2) 300 r b t Output fall time from V to V 10pF < C < 400pF (2) 20 + 0.1C (1)(2) 250 ns of IHmin ILmax b b t Spikes suppressed by input filter 0 50 SP I Input current for each I/O pin 0.1V < V < 0.9V -10 10 µA I CC I CC C Capacitance for each I/O pin 10 pF I f SCL clock frequency f (3)> max(10f , 250kHz) 0 400 kHz SCL PER SCL 100ns f  100kHz --------------- SCL C V –0.4V b R Value of pull-up resistor ----C----C--------------------  P fSCL > 100kHz 3mA 3----0--0----n---s-- C b f  100kHz 4.0 SCL t Hold time (repeated) START condition HD;STA f > 100kHz 0.6 SCL f  100kHz 4.7 SCL t Low period of SCL clock LOW f > 100kHz 1.3 SCL µs f  100kHz 4.0 SCL t High period of SCL clock HIGH f > 100kHz 0.6 SCL f  100kHz 4.7 Set-up time for a repeated START SCL t SU;STA condition f > 100kHz 0.6 SCL f  100kHz 0 3.45 SCL t Data hold time HD;DAT f > 100kHz 0 0.9 SCL f  100kHz 250 SCL t Data setup time SU;DAT f > 100kHz 100 SCL µs f  100kHz 4.0 SCL t Setup time for STOP condition SU;STO f > 100kHz 0.6 SCL f  100kHz 4.7 Bus free time between a STOP and SCL t BUF START condition f > 100kHz 1.3 SCL Notes: 1. Required only for f > 100kHz. SCL 2. C = Capacitance of one bus line in pF. b 3. f = Peripheral clock frequency. PER XMEGA D3 [DATASHEET] 100 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.3 Atmel ATxmega128D3 32.3.1 Absolute Maximum Ratings Stresses beyond those listed in Table 32-59 may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 32-59. Absolute Maximum Ratings Symbol Parameter Condition Min. Typ. Max. Units V Power supply voltage -0.3 4 V CC I Current into a V pin 200 VCC CC mA I Current out of a Gnd pin 200 GND V Pin voltage with respect to Gnd and V -0.5 V + 0.5 V PIN CC CC I I/O pin sink/source current -25 25 mA PIN T Storage temperature -65 150 A °C T Junction temperature 150 j 32.3.2 General Operating Ratings The device must operate within the ratings listed in Table 32-60 in order for all other electrical characteristics and typical characteristics of the device to be valid. Table 32-60. General Operating Conditions Symbol Parameter Condition Min. Typ. Max. Units V Power supply voltage 1.60 3.6 CC V AV Analog supply voltage 1.60 3.6 CC T Temperature range -40 85 A °C T Junction temperature -40 105 j Table 32-61. Operating Voltage and Frequency Symbol Parameter Condition Min. Typ. Max. Units V = 1.6V 0 12 CC V = 1.8V 0 12 CC Clk CPU clock frequency MHz CPU V = 2.7V 0 32 CC V = 3.6V 0 32 CC The maximum CPU clock frequency depends on V . As shown in Figure 32-15 on page 102 the frequency vs. V CC CC curve is linear between 1.8V<V <2.7V. CC XMEGA D3 [DATASHEET] 101 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 32-15.Maximum Frequency vs. V CC MHz 32 Safe operating area 12 1.6 1.8 2.7 3.6 V XMEGA D3 [DATASHEET] 102 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.3.3 Current Consumption Table 32-62. Current Consumption for Active Mode and Sleep Modes Symbol Parameter Condition Min. Typ. Max. Units V = 1.8V 55 CC 32kHz, Ext. Clk V = 3.0V 135 CC V = 1.8V 237 µA CC 1MHz, Ext. Clk Active power V = 3.0V 515 consumption (1) CC V = 1.8V 425 700 CC 2MHz, Ext. Clk 0.9 1.5 V = 3.0V mA CC 32MHz, Ext. Clk 8.3 12 V = 1.8V 2.8 CC 32kHz, Ext. Clk V = 3.0V 3.1 CC V = 1.8V 47 CC 1MHz, Ext. Clk µA Idle power V = 3.0V 95 consumption (1) CC V = 1.8V 94 200 CC 2MHz, Ext. Clk 190 400 V = 3.0V CC I 32MHz, Ext. Clk 3.0 7.0 mA CC T=25°C 0.1 1.0 T=85°C V = 3.0V 1.9 4.0 CC T=105°C 4.0 8.0 Power-down power consumption WDT and sampled BOD enabled, T=25°C 1.5 2.0 WDT and sampled BOD enabled, T = 85°C V = 3.0V 3.0 8.0 CC WDT and sampled BOD enabled, T= 105°C 5.0 10 V = 1.8V 1.3 µA RTC from ULP clock, WDT and sampled CC BOD enabled, T=25°C V = 3.0V 1.4 CC V = 1.8V 0.7 2.0 Power-save power RTC from 1.024kHz low power 32.768kHz CC consumption (2) TOSC, T=25°C V = 3.0V 0.8 2.0 CC V = 1.8V 0.9 3.0 RTC from low power 32.768kHz TOSC, CC T=25°C V = 3.0V 1.1 3.0 CC Reset power consumption Current through RESET pin substracted V = 3.0V 145 CC Notes: 1. All Power Reduction Registers set. 2. Maximum limits are based on characterization, and not tested in production. XMEGA D3 [DATASHEET] 103 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Table 32-63. Current Consumption for Modules and Peripherals Symbol Parameter Condition (1) Min. Typ. Max. Units ULP oscillator 0.9 32.768kHz int. oscillator 26 79 2MHz int. oscillator DFLL enabled with 32.768kHz int. osc. as reference 110 245 32MHz int. oscillator DFLL enabled with 32.768kHz int. osc. as reference 415 µA 20× multiplication factor, PLL 305 32MHz int. osc. DIV4 as reference Watchdog timer 1.0 Continuous mode 138 BOD Sampled mode, includes ULP oscillator 1.4 I CC Internal 1.0V reference 185 Temperature sensor 173 1.3 CURRLIMIT = LOW 1.15 16ksps V = Ext. ref. REF CURRLIMIT = MEDIUM 1.0 ADC CURRLIMIT = HIGH 0.9 mA 75ksps CURRLIMIT = LOW 1.7 V = Ext. ref. REF 300ksps 3.1 V = Ext. ref. REF USART Rx and Tx enabled, 9600 BAUD 7.5 µA Flash memory and EEPROM programming 4 mA Note: 1. All parameters measured as the difference in current consumption between module enabled and disabled. All data at V = 3.0V, Clk = 1MHz external clock CC SYS without prescaling, T = 25°C unless other conditions are given. XMEGA D3 [DATASHEET] 104 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.3.4 Wake-up Time from Sleep Modes Table 32-64. Device Wake-up Time from Sleep Modes with Various System Clock Sources Symbol Parameter Condition Min. Typ. (1) Max. Units External 2MHz clock 2.0 Wake-up time from idle, 32.768kHz internal oscillator 130 standby, and extended standby mode 2MHz internal oscillator 2.0 32MHz internal oscillator 0.2 t µs wakeup External 2MHz clock 4.5 32.768kHz internal oscillator 320 Wake-up time from power-save and power-down mode 2MHz internal oscillator 9.0 32MHz internal oscillator 5.0 Note: 1. The wake-up time is the time from the wake-up request is given until the peripheral clock is available on pin, see Figure 32-16. All peripherals and modules start execution from the first clock cycle, expect the CPU that is halted for four clock cycles before program execution starts. Figure 32-16.Wake-up Time Definition Wakeup time Wakeup request Clock output XMEGA D3 [DATASHEET] 105 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.3.5 I/O Pin Characteristics The I/O pins compiles with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output voltage limits or exceeds this specification. Table 32-65. I/O Pin Characteristics Symbol Parameter Condition Min. Typ. Max. Units I (1)/ I (2) I/O pin source/sink current -15 15 mA OH OL V = 2.4 - 3.6V 0.7 * V V + 0.5 CC CC CC V High level input voltage IH V = 1.6 - 2.4V 0.8 * V V + 0.5 CC CC CC V = 2.4 - 3.6V -0.5 0.3 * V CC CC V Low level input voltage IL V = 1.6 - 2.4V -0.5 0.2 * V CC CC V = 3.3V I = -4mA 2.6 2.9 CC OH V V High level output voltage V = 3.0V I = -3mA 2.1 2.6 OH CC OH V = 1.8V I = -1mA 1.4 1.6 CC OH V = 3.3V I = 8mA 0.4 0.76 CC OL V Low level output voltage V = 3.0V I = 5mA 0.3 0.64 OL CC OL V = 1.8V I = 3mA 0.2 0.46 CC OL I Input leakage current I/O pin T = 25°C <0.01 1.0 µA IN R Pull/buss keeper resistor 25 k P Notes: 1. The sum of all I for PORTA and PORTB must not exceed 100mA. OH The sum of all I for PORTC, PORTD, and PORTE must for each port not exceed 200mA. OH The sum of all I for pins PF[0-5] on PORTF must not exceed 200mA. OH The sum of all I for pins PF[6-7] on PORTF, PORTR, and PDI must not exceed 100mA. OL 2. The sum of all I for PORTA and PORTB must not exceed 100mA. OL The sum of all I for PORTC, PORTD, and PORTE must for each port not exceed 200mA. OL The sum of all I for pins PF[0-5] on PORTF must not exceed 200mA. OL The sum of all I for pins PF[6-7] on PORTF, PORTR, and PDI must not exceed 100mA. OL XMEGA D3 [DATASHEET] 106 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.3.6 ADC Characteristics Table 32-66. Power Supply, Reference, and Input Range Symbol Parameter Condition Min. Typ. Max. Units AV Analog supply voltage V - 0.3 V + 0.3 CC CC CC V V Reference voltage 1 AV - 0.6 REF CC R Input resistance Switched 4.5 k in C Input capacitance Switched 5 pF in R Reference input resistance (leakage only) >10 M AREF C Reference input capacitance Static load 7 pF AREF V Input range 0 V in REF Conversion range Differential mode, Vinp - Vinn -V V V REF REF Conversion range Single ended unsigned mode, Vinp -V V - V REF V Fixed offset voltage 200 lsb Table 32-67. Clock and Timing Symbol Parameter Condition Min. Typ. Max. Units Maximum is 1/4 of peripheral clock frequency 100 1800 Clk ADC clock frequency kHz ADC Measuring internal signals 100 125 f Sample rate 16 300 ksps ClkADC Current limitation (CURRLIMIT) off 16 300 CURRLIMIT = LOW 16 250 f Sample rate ksps ADC CURRLIMIT = MEDIUM 16 150 CURRLIMIT = HIGH 16 50 Sampling time 1/2 Clk cycle 0.28 320 µs ADC (RES+2)/2 + GAIN Conversion time (latency) 5.5 10 RES (Resolution) = 8 or 12, GAIN = 0 to 3 Clk ADC Start-up time ADC clock cycles 12 24 cycles ADC settling time After changing reference or input mode 7 7 XMEGA D3 [DATASHEET] 107 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Table 32-68. Accuracy Characteristics Symbol Parameter Condition (2) Min. Typ. Max. Units Differential 8 12 12 RES Resolution 12-bit resolution Single ended signed 7 11 11 Bits Single ended unsigned 8 12 12 16ksps, V = 3V 0.5 1 REF 16ksps, all V 0.8 2 REF Differential mode 300ksps, V = 3V 0.6 1 REF INL (1) Integral non-linearity lsb 300ksps, all V 1.0 2 REF 16ksps, V = 3.0V 0.5 1 Single ended REF unsigned mode 16ksps, all V 1.3 2 REF 16ksps, V = 3V 0.3 1 REF 16ksps, all V 0.5 1 REF Differential mode 300ksps, V = 3V 0.3 1 REF DNL (1) Differential non-linearity lsb 300ksps, all V 0.5 1 REF 16ksps, V = 3.0V 0.6 1 Single ended REF unsigned mode 16ksps, all V 0.6 1 REF 300ksps, V = 3V -7 mV REF Offset error Differential mode Temperature drift, V = 3V 0.01 mV/K REF Operating voltage drift 0.16 mV/V External reference -5 AV /1.6 -5 CC mV AV /2.0 -6 CC Gain error Differential mode Bandgap ±10 Temperature drift 0.02 mV/K Operating voltage drift 2 mV/V External reference -8 AV /1.6 -8 CC mV AV /2.0 -8 Single ended CC Gain error unsigned mode Bandgap ±10 Temperature drift 0.03 mV/K Operating voltage drift 2 mV/V Notes: 1. Maximum numbers are based on characterization and not tested in production and valid for 5% to 95% input voltage range. 2. Unless otherwise noted all linearity, offset and gain error numbers are valid under the condition that external V is used. REF XMEGA D3 [DATASHEET] 108 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Table 32-69. Gain Stage Characteristics Symbol Parameter Condition Min. Typ. Max. Units R Input resistance Switched in normal mode 4.0 k in C Input capacitance Switched in normal mode 4.4 pF sample Signal range Gain stage output 0 AV - 0.6 V CC Propagation delay ADC conversion rate 1/2 1 3 Clk cycles ADC Clock frequency Same as ADC 100 1800 kHz 0.5x gain, normal mode -1 1x gain, normal mode -1 Gain error % 8x gain, normal mode -1 64x gain, normal mode 5 0.5x gain, normal mode 10 1x gain, normal mode 5 Offset error, input referred mV 8x gain, normal mode -20 64x gain, normal mode -126 32.3.7 Analog Comparator Characteristics Table 32-70. Analog Comparator Characteristics Symbol Parameter Condition Min. Typ. Max. Units V Input offset voltage 10 mV off I Input leakage current <10 50 nA lk Input voltage range -0.1 AV V CC AC startup time 50 µs V Hysteresis, none V = 1.6V - 3.6V 0 hys1 CC V Hysteresis, small V = 1.6V - 3.6V 15 mV hys2 CC V Hysteresis, large V = 1.6V - 3.6V 30 hys3 CC V = 3.0V, T = 85°C 20 90 CC t Propagation delay ns delay V = 3.0V 17 CC 64-level voltage scaler Integral non-linearity (INL) 0.3 0.5 lsb Current source accuracy after calibration 5 % Current source calibration range Single mode 4 6 µA XMEGA D3 [DATASHEET] 109 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.3.8 Bandgap and Internal 1.0V Reference Characteristics Table 32-71. Bandgap and Internal 1.0V Reference Characteristics Symbol Parameter Condition Min. Typ. Max. Units As reference for ADC 1 Clk + 2.5µs PER Startup time µs As input voltage to ADC and AC 1.5 Bandgap voltage 1.1 V INT1V Internal 1.00V reference T = 85°C, after calibration 0.99 1.0 1.01 Variation over voltage and temperature Calibrated at T = 85°C 1 % 32.3.9 Brownout Detection Characteristics Table 32-72. Brownout Detection Characteristics (1) Symbol Parameter Condition Min. Typ. Max. Units BOD level 0 falling V 1.40 1.60 1.70 CC BOD level 1 falling V 1.8 CC BOD level 2 falling V 2.0 CC BOD level 3 falling V 2.2 CC V V BOT BOD level 4 falling V 2.4 CC BOD level 5 falling V 2.6 CC BOD level 6 falling V 2.8 CC BOD level 7 falling V 3.0 CC Continuous mode 0.4 t Detection time µs BOD Sampled mode 1000 V Hysteresis 1.0 % HYST Note: 1. BOD is calibrated at 85°C within BOD level 0 values, and BOD level 0 is the default level. 32.3.10External Reset Characteristics Table 32-73. External Reset Characteristics Symbol Parameter Condition Min. Typ. Max. Units t Minimum reset pulse width 1000 100 ns EXT V = 2.7 - 3.6V 0.45 * V CC CC V Reset threshold voltage V RST V = 1.6 - 2.7V 0.45 * V CC CC R Reset pin pull-up resistor 27 k RST XMEGA D3 [DATASHEET] 110 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.3.11 Power-on Reset Characteristics Table 32-74. Power-on Reset Characteristics Symbol Parameter Condition Min. Typ. Max. Units V falls faster than 1V/ms 0.4 1.0 CC V (1) POR threshold voltage falling V POT- CC V falls at 1V/ms or slower 0.8 1.3 V CC V POR threshold voltage rising V 1.3 1.59 POT+ CC Note: 1. V values are only valid when BOD is disabled. When BOD is enabled V = V . POT- POT- POT+ 32.3.12Flash and EEPROM Memory Characteristics Table 32-75. Endurance and Data Retention Symbol Parameter Condition Min. Typ. Max. Units 25°C 10K Write/Erase cycles 85°C 10K Cycle 105°C 2K Flash 25°C 100 Data retention 85°C 25 Year 105°C 10 25°C 100K Write/Erase cycles 85°C 100K Cycle 105°C 30K EEPROM 25°C 100 Data retention 85°C 25 Year 105°C 10 Table 32-76. Programming Time Symbol Parameter Condition Min. Typ. (1) Max. Units Chip erase (2) 128KB Flash, EEPROM 75 Application erase Section erase 6 Page erase 4 Flash Page write 4 ms Atomic page erase and write 8 Page erase 4 EEPROM Page write 4 Atomic page erase and write 8 Notes: 1. Programming is timed from the 2MHz internal oscillator. 2. EEPROM is not erased if the EESAVE fuse is programmed. XMEGA D3 [DATASHEET] 111 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.3.13 Clock and Oscillator Characteristics 32.3.13.1 Calibrated 32.768kHz Internal Oscillator Characteristics Table 32-77. 32.768kHz Internal Oscillator Characteristics Symbol Parameter Condition Min. Typ. Max. Units Frequency 32.768 kHz Factory calibration accuracy T = 85C, V = 3.0V -0.5 0.5 CC % User calibration accuracy -0.5 0.5 32.3.13.2 Calibrated 2MHz RC Internal Oscillator Characteristics Table 32-78. 2MHz Internal Oscillator Characteristics Symbol Parameter Condition Min. Typ. Max. Units DFLL can tune to this frequency over Frequency range 1.8 2.0 2.2 voltage and temperature MHz Factory calibrated frequency 2.0 Factory calibration accuracy T = 85C, V = 3.0V -1.5 1.5 CC User calibration accuracy -0.2 0.2 % DFLL calibration stepsize 0.18 32.3.13.3 Calibrated 32MHz Internal Oscillator Characteristics Table 32-79. 32MHz Internal Oscillator Characteristics Symbol Parameter Condition Min. Typ. Max. Units DFLL can tune to this frequency over Frequency range 30 32 55 voltage and temperature MHz Factory calibrated frequency 32 Factory calibration accuracy T = 85C, V = 3.0V -1.5 1.5 CC User calibration accuracy -0.2 0.2 % DFLL calibration step size 0.2 32.3.13.4 32kHz Internal ULP Oscillator Characteristics Table 32-80. 32kHz Internal ULP Oscillator Characteristics Symbol Parameter Condition Min. Typ. Max. Units Factory calibrated frequency 32 kHz Factory calibration accuracy T = 85°C, V = 3.0V -12 12 CC % Accuracy -30 30 XMEGA D3 [DATASHEET] 112 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.3.13.5 Internal Phase Locked Loop (PLL) Characteristics Table 32-81. Internal PLL Characteristics Symbol Parameter Condition Min. Typ. Max. Units f Input frequency Output frequency must be within f 0.4 64 IN OUT V = 1.6 - 1.8V 20 48 MHz CC f Output frequency (1) OUT V = 2.7 - 3.6V 20 128 CC Start-up time 25 µs Re-lock time 25 Note: 1. The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than four times the maximum CPU frequency. 32.3.13.6 External Clock Characteristics Figure 32-17.External Clock Drive Waveform t t CH CH t t CR CF V IH1 V IL1 t CL t CK Table 32-82. External Clock used as System Clock without Prescaling Symbol Parameter Condition Min. Typ. Max. Units V = 1.6 - 1.8V 0 12 CC 1/t Clock Frequency (1) MHz CK V = 2.7 - 3.6V 0 32 CC V = 1.6 - 1.8V 83.3 CC t Clock Period CK V = 2.7 - 3.6V 31.5 CC V = 1.6 - 1.8V 30.0 CC t Clock High Time CH V = 2.7 - 3.6V 12.5 CC V = 1.6 - 1.8V 30.0 CC t Clock Low Time ns CL V = 2.7 - 3.6V 12.5 CC V = 1.6 - 1.8V 10 CC t Rise Time (for maximum frequency) CR V = 2.7 - 3.6V 3 CC V = 1.6 - 1.8V 10 CC t Fall Time (for maximum frequency) CF V = 2.7 - 3.6V 3 CC t Change in period from one clock cycle to the next 10 % CK Note: 1. The maximum frequency vs. supply voltage is linear between 1.6V and 2.7V, and the same applies for all other parameters with supply voltage conditions. XMEGA D3 [DATASHEET] 113 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Table 32-83. External Clock with Prescaler (1) for System Clock Symbol Parameter Condition Min. Typ. Max. Units V = 1.6 - 1.8V 0 90 CC 1/t Clock Frequency (2) MHz CK V = 2.7 - 3.6V 0 142 CC V = 1.6 - 1.8V 11 CC t Clock Period CK V = 2.7 - 3.6V 7 CC V = 1.6 - 1.8V 4.5 CC t Clock High Time CH V = 2.7 - 3.6V 2.4 CC V = 1.6 - 1.8V 4.5 CC t Clock Low Time ns CL V = 2.7 - 3.6V 2.4 CC V = 1.6 - 1.8V 1.5 CC t Rise Time (for maximum frequency) CR V = 2.7 - 3.6V 1.0 CC V = 1.6 - 1.8V 1.5 CC t Fall Time (for maximum frequency) CF V = 2.7 - 3.6V 1.0 CC t Change in period from one clock cycle to the next 10 % CK Notes: 1. System Clock Prescalers must be set so that maximum CPU clock frequency for device is not exceeded. 2. The maximum frequency vs. supply voltage is linear between 1.6V and 2.7V, and the same applies for all other parameters with supply voltage conditions. 32.3.13.7 External 16MHz Crystal Oscillator and XOSC Characteristics Table 32-84. External 16MHz Crystal Oscillator and XOSC Characteristics Symbol Parameter Condition Min. Typ. Max. Units FRQRANGE=0 0 XOSCPWR=0 Cycle to cycle jitter FRQRANGE=0 0 XOSCPWR=1 0 ns FRQRANGE=0 0 XOSCPWR=0 Long term jitter FRQRANGE=0 0 XOSCPWR=1 0 FRQRANGE=0 0.03 XOSCPWR=0 FRQRANGE=0 0.03 Frequency error FRQRANGE=0 0.03 XOSCPWR=1 0.003 % FRQRANGE=0 50 XOSCPWR=0 FRQRANGE=0 50 Duty cycle FRQRANGE=0 50 XOSCPWR=1 50 XMEGA D3 [DATASHEET] 114 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Symbol Parameter Condition Min. Typ. Max. Units 0.4MHz resonator, CL=100pF 44k XOSCPWR=0, 1MHz resonator, CL=20pF 67k FRQRANGE=0 2MHz resonator, CL=20pF 67k 2MHz crystal 82k XOSCPWR=0, FRQRANGE=1, 8MHz crystal 1500 CL=20pF 9MHz crystal 1500 8MHz crystal 2700 XOSCPWR=0, FRQRANGE=2, 9MHz crystal 2700 CL=20pF 12MHz crystal 1000 9MHz crystal 3600 XOSCPWR=0, FRQRANGE=3, 12MHz crystal 1300 R Negative impedance (1) CL=20pF  Q 16MHz crystal 590 9MHz crystal 390 XOSCPWR=1, FRQRANGE=0, 12MHz crystal 50 CL=20pF 16MHz crystal 10 9MHz crystal 1500 XOSCPWR=1, FRQRANGE=1, 12MHz crystal 650 CL=20pF 16MHz crystal 270 XOSCPWR=1, 12MHz crystal 1000 FRQRANGE=2, CL=20pF 16MHz crystal 440 XOSCPWR=1, 12MHz crystal 1300 FRQRANGE=3, CL=20pF 16MHz crystal 590 ESR SF = safety factor min(R )/SF k Q XOSCPWR=0, 0.4MHz resonator, CL=100pF 1.0 FRQRANGE=0 XOSCPWR=0, 2MHz crystal, CL=20pF 2.6 FRQRANGE=1 XOSCPWR=0, Start-up time 8MHz crystal, CL=20pF 0.8 ms FRQRANGE=2 XOSCPWR=0, 12MHz crystal, CL=20pF 1.0 FRQRANGE=3 XOSCPWR=1, 16MHz crystal, CL=20pF 1.4 FRQRANGE=3 XMEGA D3 [DATASHEET] 115 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Symbol Parameter Condition Min. Typ. Max. Units Parasitic capacitance C 5.9 XTAL1 XTAL1 pin Parasitic capacitance pF C 8.3 XTAL2 XTAL1 pin C Parasitic capacitance load 3.5 LOAD Note: 1. Numbers for negative impedance are not tested in production but guaranteed from design and characterization. 32.3.13.8 External 32.768kHz Crystal Oscillator and TOSC Characteristics Table 32-85. External 32.768kHz Crystal Oscillator and TOSC Characteristics Symbol Parameter Condition Min. Typ. Max. Units Crystal load capacitance 6.5pF 60 Recommended crystal ESR/R1 equivalent series Crystal load capacitance 9.0pF 35 k resistance (ESR) Crystal load capacitance 12pF 28 Parasitic capacitance C 3.5 TOSC1 TOSC1 pin pF Parasitic capacitance C 3.5 TOSC2 TOSC2 pin Recommended safety Capacitance load matched to crystal specification 3 factor Note: See Figure 32-18 for definition. Figure 32-18.TOSC Input Capacitance C C L1 L2 Device internal TOSC1 TOSC2 External 32.768 kHz crystal The parasitic capacitance between the TOSC pins is C + C in series as seen from the crystal when oscillating without L1 L2 external capacitors. XMEGA D3 [DATASHEET] 116 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.3.14SPI Characteristics Figure 32-19.SPI Timing Requirements in Master Mode SS tMOS tSCKR tSCKF SCK (CPOL = 0) tSCKW SCK (CPOL = 1) tSCKW tMIS tMIH tSCK MISO MSB LSB (Data Input) tMOH tMOH MOSI MSB LSB (Data Output) Figure 32-20.SPI Timing Requirements in Slave Mode SS tSSS tSCKR tSCKF tSSH SCK (CPOL = 0) tSSCKW SCK (CPOL = 1) tSSCKW tSIS tSIH tSSCK MOSI MSB LSB (Data Input) tSOSSS tSOS tSOSSH MISO MSB LSB (Data Output) XMEGA D3 [DATASHEET] 117 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Table 32-86. SPI Timing Characteristics and Requirements Symbol Parameter Condition Min. Typ. Max. Units (See Table 20-3 in t SCK period Master SCK XMEGA D manual) t SCK high/low width Master 0.5 * SCK SCKW t SCK rise time Master 2.7 SCKR t SCK fall time Master 2.7 SCKF t MISO setup to SCK Master 10 MIS t MISO hold after SCK Master 10 MIH t MOSI setup SCK Master 0.5 * SCK MOS t MOSI hold after SCK Master 1 MOH t Slave SCK Period Slave 4 * tClk SSCK PER t SCK high/low width Slave 2 * tClk SSCKW PER ns t SCK rise time Slave 1600 SSCKR t SCK fall time Slave 1600 SSCKF t MOSI setup to SCK Slave 3 SIS t MOSI hold after SCK Slave tClk SIH PER t SS setup to SCK Slave 21 SSS t SS hold after SCK Slave 20 SSH t MISO setup SCK Slave 8 SOS t MISO hold after SCK Slave 13 SOH t MISO setup after SS low Slave 11 SOSS t MISO hold after SS high Slave 8 SOSH 32.3.15Two-wire Interface Characteristics Table 32-87 on page 119 describes the requirements for devices connected to the Two-Wire Interface Bus. The Atmel AVR XMEGA Two-Wire Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 32-21. Figure 32-21.Two-wire Interface Bus Timing t t of HIGH t t LOW r SCL t tSU;STA t HD;DAT tSU;DAT tSU;STO HD;STA SDA t BUF XMEGA D3 [DATASHEET] 118 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Table 32-87. Two-wire Interface Characteristics Symbol Parameter Condition Min. Typ. Max. Units V Input high voltage 0.7V V + 0.5 IH CC CC V Input low voltage -0.5 0.3V IL CC V V Hysteresis of Schmitt trigger inputs 0.05V (1) hys CC V Output low voltage 3mA, sink current 0 0.4 OL t Rise time for both SDA and SCL 20 + 0.1C (1)(2) 300 r b t Output fall time from V to V 10pF < C < 400pF (2) 20 + 0.1C (1)(2) 250 ns of IHmin ILmax b b t Spikes suppressed by input filter 0 50 SP I Input current for each I/O pin 0.1V < V < 0.9V -10 10 µA I CC I CC C Capacitance for each I/O pin 10 pF I f SCL clock frequency f (3)> max(10f , 250kHz) 0 400 kHz SCL PER SCL 100ns f  100kHz --------------- SCL C V –0.4V b R Value of pull-up resistor ----C----C--------------------  P fSCL > 100kHz 3mA 3----0--0----n---s-- C b f  100kHz 4.0 SCL t Hold time (repeated) START condition HD;STA f > 100kHz 0.6 SCL f  100kHz 4.7 SCL t Low period of SCL clock LOW f > 100kHz 1.3 SCL µs f  100kHz 4.0 SCL t High period of SCL clock HIGH f > 100kHz 0.6 SCL f  100kHz 4.7 Set-up time for a repeated START SCL t SU;STA condition f > 100kHz 0.6 SCL f  100kHz 0 3.45 SCL t Data hold time HD;DAT f > 100kHz 0 0.9 SCL f  100kHz 250 SCL t Data setup time SU;DAT f > 100kHz 100 SCL µs f  100kHz 4.0 SCL t Setup time for STOP condition SU;STO f > 100kHz 0.6 SCL f  100kHz 4.7 Bus free time between a STOP and SCL t BUF START condition f > 100kHz 1.3 SCL Notes: 1. Required only for f > 100kHz. SCL 2. C = Capacitance of one bus line in pF. b 3. f = Peripheral clock frequency. PER XMEGA D3 [DATASHEET] 119 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.4 Atmel ATxmega192D3 32.4.1 Absolute Maximum Ratings Stresses beyond those listed in Table 32-88 may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 32-88. Absolute Maximum Ratings Symbol Parameter Condition Min. Typ. Max. Units V Power supply voltage -0.3 4 V CC I Current into a V pin 200 VCC CC mA I Current out of a Gnd pin 200 GND V Pin voltage with respect to Gnd and V -0.5 V + 0.5 V PIN CC CC I I/O pin sink/source current -25 25 mA PIN T Storage temperature -65 150 A °C T Junction temperature 150 j 32.4.2 General Operating Ratings The device must operate within the ratings listed in Table 32-89 in order for all other electrical characteristics and typical characteristics of the device to be valid. Table 32-89. General Operating Conditions Symbol Parameter Condition Min. Typ. Max. Units V Power supply voltage 1.60 3.6 CC V AV Analog supply voltage 1.60 3.6 CC T Temperature range -40 85 A °C T Junction temperature -40 105 j Table 32-90. Operating Voltage and Frequency Symbol Parameter Condition Min. Typ. Max. Units V = 1.6V 0 12 CC V = 1.8V 0 12 CC Clk CPU clock frequency MHz CPU V = 2.7V 0 32 CC V = 3.6V 0 32 CC The maximum CPU clock frequency depends on V . As shown in Figure 32-22 on page 121 the frequency vs. V CC CC curve is linear between 1.8V<V <2.7V. CC XMEGA D3 [DATASHEET] 120 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 32-22.Maximum Frequency vs. V CC MHz 32 Safe operating area 12 1.6 1.8 2.7 3.6 V XMEGA D3 [DATASHEET] 121 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.4.3 Current Consumption Table 32-91. Current Consumption for Active Mode and Sleep Modes Symbol Parameter Condition Min. Typ. Max. Units V = 1.8V 60 CC 32kHz, Ext. Clk V = 3.0V 140 CC V = 1.8V 245 µA CC 1MHz, Ext. Clk Active power V = 3.0V 550 consumption (1) CC V = 1.8V 440 700 CC 2MHz, Ext. Clk 0.9 1.5 V = 3.0V mA CC 32MHz, Ext. Clk 9.0 15 V = 1.8V 3.0 CC 32kHz, Ext. Clk V = 3.0V 3.5 CC V = 1.8V 55 CC 1MHz, Ext. Clk µA Idle power V = 3.0V 110 consumption (2) CC V = 1.8V 105 350 CC 2MHz, Ext. Clk 215 650 V = 3.0V CC I 32MHz, Ext. Clk 3.4 8.0 mA CC T=25°C 0.1 1.0 T=85°C V = 3.0V 3.5 6.0 CC T=105°C 10 15 Power-down power consumption WDT and sampled BOD enabled, T=25°C 1.5 2.0 WDT and sampled BOD enabled, T = 85°C V = 3.0V 5.8 10 CC WDT and sampled BOD enabled, T= 105°C 12 20 V = 1.8V 1.3 µA RTC from ULP clock, WDT and sampled CC BOD enabled, T=25°C V = 3.0V 1.4 CC V = 1.8V 0.7 2.0 Power-save power RTC from 1.024kHz low power 32.768kHz CC consumption (3) TOSC, T=25°C V = 3.0V 0.8 2.0 CC V = 1.8V 0.9 3.0 RTC from low power 32.768kHz TOSC, CC T=25°C V = 3.0V 1.1 3.0 CC Reset power consumption Current through RESET pin substracted V = 3.0V 170 CC Notes: 1. All power reduction registers set including FPRM and EPRM. 2. All power reduction registers set without FPRM and EPRM. 3. Maximum limits are based on characterization, and not tested in production. XMEGA D3 [DATASHEET] 122 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Table 32-92. Current Consumption for Modules and Peripherals Symbol Parameter Condition (1) Min. Typ. Max. Units ULP oscillator 0.9 32.768kHz int. oscillator 25 78 2MHz int. oscillator DFLL enabled with 32.768kHz int. osc. as reference 110 250 32MHz int. oscillator DFLL enabled with 32.768kHz int. osc. as reference 440 µA 20× multiplication factor, PLL 310 32MHz int. osc. DIV4 as reference Watchdog timer 1.0 Continuous mode 132 BOD Sampled mode, includes ULP oscillator 1.4 I CC Internal 1.0V reference 185 Temperature sensor 182 1.12 CURRLIMIT = LOW 1.01 16ksps V = Ext. ref. REF CURRLIMIT = MEDIUM 0.9 ADC mA CURRLIMIT = HIGH 0.8 75ksps CURRLIMIT = LOW 1.7 V = Ext. ref. REF 300ksps, V = Ext. ref. 3.1 REF USART Rx and Tx enabled, 9600 BAUD 9.5 µA Flash memory and EEPROM programming 10 mA Note: 1. All parameters measured as the difference in current consumption between module enabled and disabled. All data at V = 3.0V, Clk = 1MHz external clock CC SYS without prescaling, T = 25°C unless other conditions are given. XMEGA D3 [DATASHEET] 123 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.4.4 Wake-up Time from Sleep Modes Table 32-93. Device Wake-up Time from Sleep Modes with Various System Clock Sources Symbol Parameter Condition Min. Typ. (1) Max. Units External 2MHz clock 2.0 Wake-up time from idle, 32.768kHz internal oscillator 125 standby, and extended standby mode 2MHz internal oscillator 2.0 32MHz internal oscillator 0.2 t µs wakeup External 2MHz clock 4.6 32.768kHz internal oscillator 330 Wake-up time from power-save and power-down mode 2MHz internal oscillator 9.5 32MHz internal oscillator 5.6 Note: 1. The wake-up time is the time from the wake-up request is given until the peripheral clock is available on pin, see Figure 32-23. All peripherals and modules start execution from the first clock cycle, expect the CPU that is halted for four clock cycles before program execution starts. Figure 32-23.Wake-up Time Definition Wakeup time Wakeup request Clock output XMEGA D3 [DATASHEET] 124 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.4.5 I/O Pin Characteristics The I/O pins complies with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output voltage limits reflect or exceed this specification. Table 32-94. I/O Pin Characteristics Symbol Parameter Condition Min. Typ. Max. Units I (1)/ I (2) I/O pin source/sink current -15 15 mA OH OL V = 2.4 - 3.6V 0.7 * V V + 0.5 CC CC CC V High level input voltage IH V = 1.6 - 2.4V 0.8 * V V + 0.5 CC CC CC V = 2.4 - 3.6V -0.5 0.3 * V CC CC V Low level input voltage IL V = 1.6 - 2.4V -0.5 0.2 * V CC CC V = 3.3V I = -4mA 2.6 2.9 CC OH V V High level output voltage V = 3.0V I = -3mA 2.1 2.6 OH CC OH V = 1.8V I = -1mA 1.4 1.6 CC OH V = 3.3V I = 8mA 0.4 0.76 CC OL V Low level output voltage V = 3.0V I = 5mA 0.3 0.64 OL CC OL V = 1.8V I = 3mA 0.2 0.46 CC OL I Input leakage current I/O pin T = 25°C <0.01 1.0 µA IN R Pull/buss keeper resistor 25 k P Notes: 1. The sum of all I for PORTA and PORTB must not exceed 100mA. OH The sum of all I for PORTC, PORTD, and PORTE must for each port not exceed 200mA. OH The sum of all I for pins PF[0-5] on PORTF must not exceed 200mA. OH The sum of all I for pins PF[6-7] on PORTF, PORTR, and PDI must not exceed 100mA. OL 2. The sum of all I for PORTA and PORTB must not exceed 100mA. OL The sum of all I for PORTC, PORTD, and PORTE must for each port not exceed 200mA. OL The sum of all I for pins PF[0-5] on PORTF must not exceed 200mA. OL The sum of all I for pins PF[6-7] on PORTF, PORTR, and PDI must not exceed 100mA. OL XMEGA D3 [DATASHEET] 125 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.4.6 ADC Characteristics Table 32-95. Power Supply, Reference, and Input Range Symbol Parameter Condition Min. Typ. Max. Units AV Analog supply voltage V - 0.3 V + 0.3 CC CC CC V V Reference voltage 1 AV - 0.6 REF CC R Input resistance Switched 4.5 k in C Input capacitance Switched 5 pF in R Reference input resistance (leakage only) >10 M AREF C Reference input capacitance Static load 7 pF AREF Input range 0 V REF V Conversion range Differential mode, Vinp - Vinn -V V V in REF REF Conversion range Single ended unsigned mode, Vinp -V V - V REF V Fixed offset voltage 200 lsb Table 32-96. Clock and Timing Symbol Parameter Condition Min. Typ. Max. Units Maximum is 1/4 of peripheral clock frequency 100 1800 Clk ADC clock frequency kHz ADC Measuring internal signals 100 125 f Sample rate 16 300 ClkADC Current limitation (CURRLIMIT) off 16 300 CURRLIMIT = LOW 16 250 ksps f Sample rate ADC CURRLIMIT = MEDIUM 16 150 CURRLIMIT = HIGH 16 50 Configurable in steps of 1/2 Clk cycles up Sampling time ADC 0.28 320 µs to 32 Clk cycles ADC (RES+2)/2 + 1 + GAIN Conversion time (latency) 5.5 10 RES (Resolution) = 8 or 12, GAIN = 0 to 3 Clk ADC Start-up time ADC clock cycles 12 24 cycles ADC settling time After changing reference or input mode 7 7 XMEGA D3 [DATASHEET] 126 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Table 32-97. Accuracy Characteristics Symbol Parameter Condition (2) Min. Typ. Max. Units Differential 8 12 12 RES Resolution 12-bit resolution Single ended signed 7 11 11 Bits Single ended unsigned 8 12 12 16ksps, V = 3V 0.5 1 REF 16ksps, all V 0.8 2 REF Differential mode 300ksps, V = 3V 0.6 1 REF INL (1) Integral non-linearity 300ksps, all V 1 2 REF 16ksps, V = 3.0V 0.5 1 Single ended REF unsigned mode 16ksps, all V 1.3 2 REF lsb 16ksps, V = 3V 0.3 1 REF 16ksps, all V 0.5 1 REF Differential mode 300ksps, V = 3V 0.3 1 REF DNL (1) Differential non-linearity 300ksps, all V 0.5 1 REF 16ksps, V = 3.0V 0.6 1 Single ended REF unsigned mode 16ksps, All V 0.6 1 REF 300ksps, V = 3V -7 mV REF Offset error Differential mode Temperature drift, V = 3V 0.01 mV/K REF Operating voltage drift 0.16 mV/V External reference -5 AV /1.6 -5 CC mV AV /2.0 -6 CC Gain error Differential mode Bandgap ±10 Temperature drift 0.02 mV/K Operating voltage drift 2 mV/V External reference -8 AV /1.6 -8 CC mV AV /2.0 -8 Single ended CC Gain error unsigned mode Bandgap ±10 Temperature drift 0.03 mV/K Operating voltage drift 2 mV/V Notes: 1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range. 2. Unless otherwise noted all linearity, offset, and gain error numbers are valid under the condition that external V is used. REF XMEGA D3 [DATASHEET] 127 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Table 32-98. Gain Stage Characteristics Symbol Parameter Condition Min. Typ. Max. Units R Input resistance Switched in normal mode 4.0 k in C Input capacitance Switched in normal mode 4.4 pF sample Signal range Gain stage output 0 AV - 0.6 V CC Propagation delay ADC conversion rate 1/2 1 3 Clk cycles ADC Clock frequency Same as ADC 100 1800 kHz 0.5× gain, normal mode -1 1× gain, normal mode -1 Gain error % 8× gain, normal mode -1 64× gain, normal mode 5 0.5× gain, normal mode 10 1× gain, normal mode 5 Offset error, input referred mV 8× gain, normal mode -20 64× gain, normal mode -126 32.4.7 Analog Comparator Characteristics Table 32-99. Analog Comparator Characteristics Symbol Parameter Condition Min. Typ. Max. Units V Input offset voltage 10 mV off I Input leakage current <10 50 nA lk Input voltage range -0.1 AV V CC AC startup time 50 µs V Hysteresis, none V = 1.6V - 3.6V 0 hys1 CC V Hysteresis, small V = 1.6V - 3.6V 15 mV hys2 CC V Hysteresis, large V = 1.6V - 3.6V 30 hys3 CC V = 3.0V, T = 85°C 20 40 CC t Propagation delay ns delay V = 3.0V 17 CC 64-level voltage scaler Integral non-linearity (INL) 0.3 0.5 lsb Current source accuracy after calibration 5 % Current source calibration range Single mode 4 6 µA XMEGA D3 [DATASHEET] 128 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.4.8 Bandgap and Internal 1.0V Reference Characteristics Table 32-100. Bandgap and Internal 1.0V Reference Characteristics Symbol Parameter Condition Min. Typ. Max. Units As reference for ADC 1 Clk + 2.5µs PER Startup time µs As input voltage to ADC and AC 1.5 Bandgap voltage 1.1 V INT1V Internal 1.00V reference T = 85°C, after calibration 0.99 1.0 1.01 Variation over voltage and temperature Calibrated at T = 85°C 1 % 32.4.9 Brownout Detection Characteristics Table 32-101.Brownout Detection Characteristics (1) Symbol Parameter (BOD level 0 at 85°C) Condition Min. Typ. Max. Units BOD level 0 falling V 1.40 1.60 1.70 CC BOD level 1 falling V 1.8 CC BOD level 2 falling V 2.0 CC BOD level 3 falling V 2.2 CC V V BOT BOD level 4 falling V 2.4 CC BOD level 5 falling V 2.6 CC BOD level 6 falling V 2.8 CC BOD level 7 falling V 3.0 CC Continuous mode 0.4 t Detection time µs BOD Sampled mode 1000 V Hysteresis 1.0 % HYST Note: 1. BOD is calibrated at 85°C within BOD level 0 values, and BOD level 0 is the default level. 32.4.10External Reset Characteristics Table 32-102.External Reset Characteristics Symbol Parameter Condition Min. Typ. Max. Units t Minimum reset pulse width 1000 90 ns EXT V = 2.7 - 3.6V 0.45 * V CC CC V Reset threshold voltage V RST V = 1.6 - 2.7V 0.45 * V CC CC R Reset pin pull-up resistor 25 k RST XMEGA D3 [DATASHEET] 129 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.4.11 Power-on Reset Characteristics Table 32-103.Power-on Reset Characteristics Symbol Parameter Condition Min. Typ. Max. Units V falls faster than 1V/ms 0.4 1.0 CC V (1) POR threshold voltage falling V POT- CC V falls at 1V/ms or slower 0.8 1.3 V CC V POR threshold voltage rising V 1.3 1.59 POT+ CC Note: 1. V values are only valid when BOD is disabled. When BOD is enabled V = V . POT- POT- POT+ 32.4.12Flash and EEPROM Memory Characteristics Table 32-104.Endurance and Data Retention Symbol Parameter Condition Min. Typ. Max. Units 25°C 10K Write/Erase cycles 85°C 10K Cycle 105°C 2K Flash 25°C 100 Data retention 85°C 25 Year 105°C 10 25°C 100K Write/Erase cycles 85°C 100K Cycle 105°C 30K EEPROM 25°C 100 Data retention 85°C 25 Year 105°C 10 Table 32-105. Programming Time Symbol Parameter Condition Min. Typ. (1) Max. Units Chip erase (2) 192KB flash, EEPROM 90 Application erase Section erase 6 Page erase 4 Flash Page write 4 ms Atomic page erase and write 8 Page erase 4 EEPROM Page write 4 Atomic page erase and write 8 Notes: 1. Programming is timed from the 2MHz internal oscillator. 2. EEPROM is not erased if the EESAVE fuse is programmed. XMEGA D3 [DATASHEET] 130 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.4.13 Clock and Oscillator Characteristics 32.4.13.1 Calibrated 32.768kHz Internal Oscillator Characteristics Table 32-106. 32.768kHz Internal Oscillator Characteristics Symbol Parameter Condition Min. Typ. Max. Units Frequency 32.768 kHz Factory calibration accuracy T = 85C, V = 3.0V -0.5 0.5 CC % User calibration accuracy -0.5 0.5 32.4.13.2 Calibrated 2MHz RC Internal Oscillator Characteristics Table 32-107. 2MHz Internal Oscillator Characteristics Symbol Parameter Condition Min. Typ. Max. Units DFLL can tune to this frequency over Frequency range 1.8 2.0 2.2 voltage and temperature MHz Factory calibrated frequency 2.0 Factory calibration accuracy T = 85C, V = 3.0V -1.5 1.5 CC User calibration accuracy -0.2 0.2 % DFLL calibration stepsize 0.18 32.4.13.3 Calibrated 32MHz Internal Oscillator Characteristics Table 32-108. 32MHz Internal Oscillator Characteristics Symbol Parameter Condition Min. Typ. Max. Units DFLL can tune to this frequency over Frequency range 30 32 55 voltage and temperature MHz Factory calibrated frequency 32 Factory calibration accuracy T = 85C, V = 3.0V -1.5 1.5 CC User calibration accuracy -0.2 0.2 % DFLL calibration step size 0.19 32.4.13.4 32kHz Internal ULP Oscillator Characteristics Table 32-109. 32kHz Internal ULP Oscillator Characteristics Symbol Parameter Condition Min. Typ. Max. Units Factory calibrated frequency 32 kHz Factory calibration accuracy T = 85C, V = 3.0V -12 12 CC % Accuracy -30 30 XMEGA D3 [DATASHEET] 131 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.4.13.5 Internal Phase Locked Loop (PLL) Characteristics Table 32-110. Internal PLL Characteristics Symbol Parameter Condition Min. Typ. Max. Units f Input frequency Output frequency must be within f 0.4 64 IN OUT V = 1.6 - 1.8V 20 48 MHz CC f Output frequency (1) OUT V = 2.7 - 3.6V 20 128 CC Start-up time 25 µs Re-lock time 25 Note: 1. The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than four times the maximum CPU frequency. 32.4.13.6 External Clock Characteristics Figure 32-24. External Clock Drive Waveform t t CH CH t t CR CF V IH1 V IL1 t CL t CK Table 32-111.External Clock used as System Clock without Prescaling Symbol Parameter Condition Min. Typ. Max. Units V = 1.6 - 1.8V 0 12 CC 1/t Clock Frequency (1) MHz CK V = 2.7 - 3.6V 0 32 CC V = 1.6 - 1.8V 83.3 CC t Clock Period CK V = 2.7 - 3.6V 31.5 CC V = 1.6 - 1.8V 30.0 CC t Clock High Time CH V = 2.7 - 3.6V 12.5 CC V = 1.6 - 1.8V 30.0 CC t Clock Low Time ns CL V = 2.7 - 3.6V 12.5 CC V = 1.6 - 1.8V 10 CC t Rise Time (for maximum frequency) CR V = 2.7 - 3.6V 3 CC V = 1.6 - 1.8V 10 CC t Fall Time (for maximum frequency) CF V = 2.7 - 3.6V 3 CC t Change in period from one clock cycle to the next 10 % CK Note: 1. The maximum frequency vs. supply voltage is linear between 1.6V and 2.7V, and the same applies for all other parameters with supply voltage conditions. XMEGA D3 [DATASHEET] 132 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Table 32-112.External Clock with Prescaler (1) for System Clock Symbol Parameter Condition Min. Typ. Max. Units V = 1.6 - 1.8V 0 90 CC 1/t Clock Frequency (2) MHz CK V = 2.7 - 3.6V 0 142 CC V = 1.6 - 1.8V 11 CC t Clock Period CK V = 2.7 - 3.6V 7 CC V = 1.6 - 1.8V 4.5 CC t Clock High Time CH V = 2.7 - 3.6V 2.4 CC V = 1.6 - 1.8V 4.5 CC t Clock Low Time ns CL V = 2.7 - 3.6V 2.4 CC V = 1.6 - 1.8V 1.5 CC t Rise Time (for maximum frequency) CR V = 2.7 - 3.6V 1.0 CC V = 1.6 - 1.8V 1.5 CC t Fall Time (for maximum frequency) CF V = 2.7 - 3.6V 1.0 CC t Change in period from one clock cycle to the next 10 % CK Notes: 1. System Clock Prescalers must be set so that maximum CPU clock frequency for device is not exceeded. 2. The maximum frequency vs. supply voltage is linear between 1.6V and 2.7V, and the same applies for all other parameters with supply voltage conditions. 32.4.13.7 External 16MHz Crystal Oscillator and XOSC Characteristics Table 32-113. External 16MHz Crystal Oscillator and XOSC Characteristics Symbol Parameter Condition Min. Typ. Max. Units FRQRANGE=0 0 XOSCPWR=0 Cycle to cycle jitter FRQRANGE=1, 2, or 3 0 XOSCPWR=1 0 ns FRQRANGE=0 0 XOSCPWR=0 Long term jitter FRQRANGE=1, 2, or 3 0 XOSCPWR=1 0 FRQRANGE=0 0.03 XOSCPWR=0 FRQRANGE=1 0.03 Frequency error FRQRANGE=2 or 3 0.03 XOSCPWR=1 0.003 % FRQRANGE=0 50 XOSCPWR=0 FRQRANGE=1 50 Duty cycle FRQRANGE=2 or 3 50 XOSCPWR=1 50 XMEGA D3 [DATASHEET] 133 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Symbol Parameter Condition Min. Typ. Max. Units 0.4MHz resonator, CL=100pF 44k XOSCPWR=0, 1MHz crystal, CL=20pF 67k FRQRANGE=0 2MHz crystal, CL=20pF 67k 2MHz crystal 82k XOSCPWR=0, FRQRANGE=1, 8MHz crystal 1500 CL=20pF 9MHz crystal 1500 8MHz crystal 2700 XOSCPWR=0, FRQRANGE=2, 9MHz crystal 2700 CL=20pF 12MHz crystal 1000 9MHz crystal 3600 XOSCPWR=0, FRQRANGE=3, 12MHz crystal 1300 R Negative impedance (1) CL=20pF  Q 16MHz crystal 590 9MHz crystal 390 XOSCPWR=1, FRQRANGE=0, 12MHz crystal 50 CL=20pF 16MHz crystal 10 9MHz crystal 1500 XOSCPWR=1, FRQRANGE=1, 12MHz crystal 650 CL=20pF 16MHz crystal 270 XOSCPWR=1, 12MHz crystal 1000 FRQRANGE=2, CL=20pF 16MHz crystal 440 XOSCPWR=1, 12MHz crystal 1300 FRQRANGE=3, CL=20pF 16MHz crystal 590 min ESR SF = safety factor (R )/ k Q SF XOSCPWR=0, 0.4MHz resonator, CL=100pF 1.0 FRQRANGE=0 XOSCPWR=0, 2MHz resonator, CL=20pF 2.6 FRQRANGE=1 XOSCPWR=0, Start-up time 8MHz resonator, CL=20pF 0.8 ms FRQRANGE=2 XOSCPWR=0, 12MHz resonator, CL=20pF 1.0 FRQRANGE=3 XOSCPWR=1, 16MHz resonator, CL=20pF 1.4 FRQRANGE=3 XMEGA D3 [DATASHEET] 134 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Symbol Parameter Condition Min. Typ. Max. Units Parasitic capacitance C 5.9 XTAL1 XTAL1 pin Parasitic capacitance pF C 8.3 XTAL2 XTAL2 pin C Parasitic capacitance load 3.5 LOAD Notes: 1. Numbers for negative impedance are not tested in production but guaranteed from design and characterization. 32.4.13.8 External 32.768kHz Crystal Oscillator and TOSC Characteristics Table 32-114. External 32.768kHz Crystal Oscillator and TOSC Characteristics Symbol Parameter Condition Min. Typ. Max. Units Crystal load capacitance 6.5pF 60 Recommended crystal equivalent ESR/R1 Crystal load capacitance 9.0pF 35 k series resistance (ESR) Crystal load capacitance 12pF 28 C Parasitic capacitance TOSC1 pin 3.5 TOSC1 pF C Parasitic capacitance TOSC2 pin 3.5 TOSC2 Recommended safety factor Capacitance load matched to crystal specification 3 Note: See Figure 32-25 for definition. Figure 32-25. TOSC Input Capacitance C C L1 L2 Device internal TOSC1 TOSC2 External 32.768 kHz crystal The parasitic capacitance between the TOSC pins is C + C in series as seen from the crystal when oscillating without L1 L2 external capacitors. XMEGA D3 [DATASHEET] 135 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.4.14 SPI Characteristics Figure 32-26. SPI Timing Requirements in Master Mode SS tMOS tSCKR tSCKF SCK (CPOL = 0) tSCKW SCK (CPOL = 1) tSCKW tMIS tMIH tSCK MISO MSB LSB (Data Input) tMOH tMOH MOSI MSB LSB (Data Output) Figure 32-27.SPI Timing Requirements in Slave Mode SS tSSS tSCKR tSCKF tSSH SCK (CPOL = 0) tSSCKW SCK (CPOL = 1) tSSCKW tSIS tSIH tSSCK MOSI MSB LSB (Data Input) tSOSSS tSOS tSOSSH MISO MSB LSB (Data Output) XMEGA D3 [DATASHEET] 136 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Table 32-115. SPI Timing Characteristics and Requirements Symbol Parameter Condition Min. Typ. Max. Units (See Table 20-3 in t SCK period Master SCK XMEGA D manual) t SCK high/low width Master 0.5 * SCK SCKW t SCK rise time Master 2.7 SCKR t SCK fall time Master 2.7 SCKF t MISO setup to SCK Master 10 MIS t MISO hold after SCK Master 10 MIH t MOSI setup SCK Master 0.5 * SCK MOS t MOSI hold after SCK Master 1 MOH t Slave SCK Period Slave 4 * tClk SSCK PER t SCK high/low width Slave 2 * tClk SSCKW PER ns t SCK rise time Slave 1600 SSCKR t SCK fall time Slave 1600 SSCKF t MOSI setup to SCK Slave 3 SIS t MOSI hold after SCK Slave tClk SIH PER t SS setup to SCK Slave 21 SSS t SS hold after SCK Slave 20 SSH t MISO setup SCK Slave 8 SOS t MISO hold after SCK Slave 13 SOH t MISO setup after SS low Slave 11 SOSS t MISO hold after SS high Slave 8 SOSH 32.4.15Two-wire Interface Characteristics Table 32-116 on page 138 describes the requirements for devices connected to the Two-Wire Interface Bus. The Atmel AVR XMEGA Two-Wire Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 32-28. Figure 32-28. Two-wire Interface Bus Timing t t of HIGH t t LOW r SCL t tSU;STA t HD;DAT tSU;DAT tSU;STO HD;STA SDA t BUF XMEGA D3 [DATASHEET] 137 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Table 32-116. Two-wire Interface Characteristics Symbol Parameter Condition Min. Typ. Max. Units V Input high voltage 0.7V V + 0.5 IH CC CC V Input low voltage -0.5 0.3V IL CC V V Hysteresis of Schmitt trigger inputs 0.05V (1) hys CC V Output low voltage 3mA, sink current 0 0.4 OL t Rise time for both SDA and SCL 20 + 0.1C (1)(2) 300 r b t Output fall time from V to V 10pF < C < 400pF (2) 20 + 0.1C (1)(2) 250 ns of IHmin ILmax b b t Spikes suppressed by input filter 0 50 SP I Input current for each I/O pin 0.1V < V < 0.9V -10 10 µA I CC I CC C Capacitance for each I/O pin 10 pF I f SCL clock frequency f (3)> max(10f , 250kHz) 0 400 kHz SCL PER SCL 100ns f  100kHz --------------- SCL C V –0.4V b R Value of pull-up resistor ----C----C--------------------  P fSCL > 100kHz 3mA 3----0--0----n---s-- C b f  100kHz 4.0 SCL t Hold time (repeated) START condition HD;STA f > 100kHz 0.6 SCL f  100kHz 4.7 SCL t Low period of SCL clock LOW f > 100kHz 1.3 SCL µs f  100kHz 4.0 SCL t High period of SCL clock HIGH f > 100kHz 0.6 SCL f  100kHz 4.7 Set-up time for a repeated START SCL t SU;STA condition f > 100kHz 0.6 SCL f  100kHz 0 3.45 SCL t Data hold time HD;DAT f > 100kHz 0 0.9 SCL f  100kHz 250 SCL t Data setup time SU;DAT f > 100kHz 100 SCL µs f  100kHz 4.0 SCL t Setup time for STOP condition SU;STO f > 100kHz 0.6 SCL f  100kHz 4.7 Bus free time between a STOP and SCL t BUF START condition f > 100kHz 1.3 SCL Notes: 1. Required only for f > 100kHz. SCL 2. C = Capacitance of one bus line in pF. b 3. f = Peripheral clock frequency. PER XMEGA D3 [DATASHEET] 138 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.5 Atmel ATxmega256D3 32.5.1 Absolute Maximum Ratings Stresses beyond those listed in Table 32-117 may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 32-117. Absolute Maximum Ratings Symbol Parameter Condition Min. Typ. Max. Units V Power supply voltage -0.3 4 V CC I Current into a V pin 200 VCC CC mA I Current out of a Gnd pin 200 GND V Pin voltage with respect to Gnd and V -0.5 V + 0.5 V PIN CC CC I I/O pin sink/source current -25 25 mA PIN T Storage temperature -65 150 A °C T Junction temperature 150 j 32.5.2 General Operating Ratings The device must operate within the ratings listed in Table 32-118 in order for all other electrical characteristics and typical characteristics of the device to be valid. Table 32-118. General Operating Conditions Symbol Parameter Condition Min. Typ. Max. Units V Power supply voltage 1.60 3.6 CC V AV Analog supply voltage 1.60 3.6 CC T Temperature range -40 85 A °C T Junction temperature -40 105 j Table 32-119. Operating Voltage and Frequency Symbol Parameter Condition Min. Typ. Max. Units V = 1.6V 0 12 CC V = 1.8V 0 12 CC Clk CPU clock frequency MHz CPU V = 2.7V 0 32 CC V = 3.6V 0 32 CC The maximum CPU clock frequency depends on V . As shown in Figure 32-29 on page 140 the frequency vs. V CC CC curve is linear between 1.8V<V <2.7V. CC XMEGA D3 [DATASHEET] 139 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 32-29. Maximum Frequency vs. V CC MHz 32 Safe operating area 12 1.6 1.8 2.7 3.6 V XMEGA D3 [DATASHEET] 140 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.5.3 Current Consumption Table 32-120. Current Consumption for Active Mode and Sleep Modes Symbol Parameter Condition Min. Typ. Max. Units V = 1.8V 60 CC 32kHz, Ext. Clk V = 3.0V 140 CC V = 1.8V 245 µA CC 1MHz, Ext. Clk Active power V = 3.0V 550 consumption (1) CC V = 1.8V 440 700 CC 2MHz, Ext. Clk 0.9 1.5 V = 3.0V mA CC 32MHz, Ext. Clk 9.0 15 V = 1.8V 3.0 CC 32kHz, Ext. Clk V = 3.0V 3.5 CC V = 1.8V 55 CC 1MHz, Ext. Clk µA Idle power V = 3.0V 110 consumption (2) CC V = 1.8V 105 350 CC 2MHz, Ext. Clk 215 650 V = 3.0V CC I 32MHz, Ext. Clk 3.4 8.0 mA CC T=25°C 0.1 1.0 T=85°C V = 3.0V 3.5 6.0 CC T=105°C 10 15 Power-down power consumption WDT and sampled BOD enabled, T=25°C 1.5 2.0 WDT and sampled BOD enabled, T = 85°C V = 3.0V 5.8 10 CC WDT and sampled BOD enabled, T= 105°C 12 20 V = 1.8V 1.3 µA RTC from ULP clock, WDT and sampled CC BOD enabled, T=25°C V = 3.0V 1.4 CC V = 1.8V 0.7 2.0 Power-save power RTC from 1.024kHz low power 32.768kHz CC consumption (3) TOSC, T=25°C V = 3.0V 0.8 2.0 CC V = 1.8V 0.9 3.0 RTC from low power 32.768kHz TOSC, CC T=25°C V = 3.0V 1.1 3.0 CC Reset power consumption Current through RESET pin substracted V = 3.0V 170 CC Notes: 1. All power reduction registers set including FPRM and EPRM. 2. All power reduction registers set without FPRM and EPRM. 3. Maximum limits are based on characterization, and not tested in production. XMEGA D3 [DATASHEET] 141 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Table 32-121. Current Consumption for Modules and Peripherals Symbol Parameter Condition (1) Min. Typ. Max. Units ULP oscillator 0.9 32.768kHz int. oscillator 25 78 2MHz int. oscillator DFLL enabled with 32.768kHz int. osc. as reference 110 250 32MHz int. oscillator DFLL enabled with 32.768kHz int. osc. as reference 440 µA 20× multiplication factor, PLL 310 32MHz int. osc. DIV4 as reference Watchdog timer 1.0 Continuous mode 132 BOD Sampled mode, includes ULP oscillator 1.4 I CC Internal 1.0V reference 185 Temperature sensor 182 1.12 CURRLIMIT = LOW 1.01 16ksps V = Ext. ref. REF CURRLIMIT = MEDIUM 0.9 ADC CURRLIMIT = HIGH 0.8 mA 75ksps CURRLIMIT = LOW 1.7 V = Ext. ref. REF 300ksps 3.1 V = Ext. ref. REF USART Rx and Tx enabled, 9600 BAUD 9.5 µA Flash memory and EEPROM programming 10 mA Note: 1. All parameters measured as the difference in current consumption between module enabled and disabled. All data at V = 3.0V, Clk = 1MHz external clock CC SYS without prescaling, T = 25°C unless other conditions are given. XMEGA D3 [DATASHEET] 142 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.5.4 Wake-up Time from Sleep Modes Table 32-122. Device Wake-up Time from Sleep Modes with Various System Clock Sources Symbol Parameter Condition Min. Typ. (1) Max. Units External 2MHz clock 2.0 Wake-up time from idle, 32.768kHz internal oscillator 125 standby, and extended standby mode 2MHz internal oscillator 2.0 32MHz internal oscillator 0.2 t µs wakeup External 2MHz clock 4.6 32.768kHz internal oscillator 330 Wake-up time from power-save and power-down mode 2MHz internal oscillator 9.5 32MHz internal oscillator 5.6 Note: 1. The wake-up time is the time from the wake-up request is given until the peripheral clock is available on pin, see Figure 32-30. All peripherals and modules start execution from the first clock cycle, expect the CPU that is halted for four clock cycles before program execution starts. Figure 32-30. Wake-up Time Definition Wakeup time Wakeup request Clock output XMEGA D3 [DATASHEET] 143 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.5.5 I/O Pin Characteristics The I/O pins complies with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output voltage limits reflect or exceed this specification. Table 32-123. I/O Pin Characteristics Symbol Parameter Condition Min. Typ. Max. Units I (1)/ I (2) I/O pin source/sink current -15 15 mA OH OL V = 2.4 - 3.6V 0.7 * V V + 0.5 CC CC CC V High level input voltage IH V = 1.6 - 2.4V 0.8 * V V + 0.5 CC CC CC V = 2.4 - 3.6V -0.5 0.3 * V CC CC V Low level input voltage IL V = 1.6 - 2.4V -0.5 0.2 * V CC CC V = 3.3V I = -4mA 2.6 2.9 CC OH V V High level output voltage V = 3.0V I = -3mA 2.1 2.6 OH CC OH V = 1.8V I = -1mA 1.4 1.6 CC OH V = 3.3V I = 8mA 0.4 0.76 CC OL V Low level output voltage V = 3.0V I = 5mA 0.3 0.64 OL CC OL V = 1.8V I = 3mA 0.2 0.46 CC OL I Input leakage current I/O pin T = 25°C <0.01 1.0 µA IN R Pull/buss keeper resistor 25 k P Notes: 1. The sum of all I for PORTA and PORTB must not exceed 100mA. OH The sum of all I for PORTC, PORTD, and PORTE must for each port not exceed 200mA. OH The sum of all I for pins PF[0-5] on PORTF must not exceed 200mA. OH The sum of all I for pins PF[6-7] on PORTF, PORTR, and PDI must not exceed 100mA. OL 2. The sum of all I for PORTA and PORTB must not exceed 100mA. OL The sum of all I for PORTC, PORTD, and PORTE must for each port not exceed 200mA. OL The sum of all I for pins PF[0-5] on PORTF must not exceed 200mA. OL The sum of all I for pins PF[6-7] on PORTF, PORTR, and PDI must not exceed 100mA. OL XMEGA D3 [DATASHEET] 144 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.5.6 ADC Characteristics Table 32-124. Power Supply, Reference, and Input Range Symbol Parameter Condition Min. Typ. Max. Units AV Analog supply voltage V - 0.3 V + 0.3 CC CC CC V V Reference voltage 1 AV - 0.6 REF CC R Input resistance Switched 4.5 k in C Input capacitance Switched 5 pF in R Reference input resistance (leakage only) >10 M AREF C Reference input capacitance Static load 7 pF AREF Input range 0 V REF V Conversion range Differential mode, Vinp - Vinn -V V V in REF REF Conversion range Single ended unsigned mode, Vinp -V V - V REF V Fixed offset voltage 200 lsb Table 32-125. Clock and Timing Symbol Parameter Condition Min. Typ. Max. Units Maximum is 1/4 of peripheral clock frequency 100 1800 Clk ADC clock frequency kHz ADC Measuring internal signals 100 125 f Sample rate 16 300 ClkADC Current limitation (CURRLIMIT) off 16 300 CURRLIMIT = LOW 16 250 ksps f Sample rate ADC CURRLIMIT = MEDIUM 16 150 CURRLIMIT = HIGH 16 50 Configurable in steps of 1/2 Clk cycles up Sampling time ADC 0.28 320 µs to 32 Clk cycles ADC (RES+2)/2 + 1 + GAIN Conversion time (latency) 5.5 10 RES (Resolution) = 8 or 12, GAIN = 0 to 3 Clk ADC Start-up time ADC clock cycles 12 24 cycles ADC settling time After changing reference or input mode 7 7 XMEGA D3 [DATASHEET] 145 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Table 32-126. Accuracy Characteristics Symbol Parameter Condition (2) Min. Typ. Max. Units Differential 8 12 12 RES Resolution 12-bit resolution Single ended signed 7 11 11 Bits Single ended unsigned 8 12 12 16ksps, V = 3V 0.5 1 REF 16ksps, all V 0.8 2 REF Differential mode 300ksps, V = 3V 0.6 1 REF INL (1) Integral non-linearity 300ksps, all V 1 2 REF 16ksps, V = 3.0V 0.5 1 Single ended REF unsigned mode 16ksps, all V 1.3 2 REF lsb 16ksps, V = 3V 0.3 1 REF 16ksps, all V 0.5 1 REF Differential mode 300ksps, V = 3V 0.3 1 REF DNL (1) Differential non-linearity 300ksps, all V 0.5 1 REF 16ksps, V = 3.0V 0.6 1 Single ended REF unsigned mode 16ksps, All V 0.6 1 REF 300ksps, V = 3V -7 mV REF Offset error Differential mode Temperature drift, V = 3V 0.01 mV/K REF Operating voltage drift 0.16 mV/V External reference -5 AV /1.6 -5 CC mV AV /2.0 -6 CC Gain error Differential mode Bandgap ±10 Temperature drift 0.02 mV/K Operating voltage drift 2 mV/V External reference -8 AV /1.6 -8 CC mV AV /2.0 -8 Single ended CC Gain error unsigned mode Bandgap ±10 Temperature drift 0.03 mV/K Operating voltage drift 2 mV/V Notes: 1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range. 2. Unless otherwise noted all linearity, offset, and gain error numbers are valid under the condition that external V is used. REF XMEGA D3 [DATASHEET] 146 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Table 32-127. Gain Stage Characteristics Symbol Parameter Condition Min. Typ. Max. Units R Input resistance Switched in normal mode 4.0 k in C Input capacitance Switched in normal mode 4.4 pF sample Signal range Gain stage output 0 AV - 0.6 V CC Propagation delay ADC conversion rate 1/2 1 3 Clk cycles ADC Clock frequency Same as ADC 100 1800 kHz 0.5× gain, normal mode -1 1× gain, normal mode -1 Gain error % 8× gain, normal mode -1 64× gain, normal mode 5 0.5× gain, normal mode 10 1× gain, normal mode 5 Offset error, input referred mV 8× gain, normal mode -20 64× gain, normal mode -126 32.5.7 Analog Comparator Characteristics Table 32-128. Analog Comparator Characteristics Symbol Parameter Condition Min. Typ. Max. Units V Input offset voltage 10 mV off I Input leakage current <10 50 nA lk Input voltage range -0.1 AV V CC AC startup time 50 µs V Hysteresis, none V = 1.6V - 3.6V 0 hys1 CC V Hysteresis, small V = 1.6V - 3.6V 15 mV hys2 CC V Hysteresis, large V = 1.6V - 3.6V 30 hys3 CC V = 3.0V, T = 85°C 20 40 CC t Propagation delay ns delay V = 3.0V 17 CC 64-level voltage scaler Integral non-linearity (INL) 0.3 0.5 lsb Current source accuracy after calibration 5 % Current source calibration range Single mode 4 6 µA XMEGA D3 [DATASHEET] 147 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.5.8 Bandgap and Internal 1.0V Reference Characteristics Table 32-129. Bandgap and Internal 1.0V Reference Characteristics Symbol Parameter Condition Min. Typ. Max. Units As reference for ADC 1 Clk + 2.5µs PER Startup time µs As input voltage to ADC and AC 1.5 Bandgap voltage 1.1 V INT1V Internal 1.00V reference T = 85°C, after calibration 0.99 1.0 1.01 Variation over voltage and temperature Calibrated at T = 85°C 1 % 32.5.9 Brownout Detection Characteristics Table 32-130. Brownout Detection Characteristics (1) Symbol Parameter Condition Min. Typ. Max. Units BOD level 0 falling V 1.40 1.60 1.70 CC BOD level 1 falling V 1.8 CC BOD level 2 falling V 2.0 CC BOD level 3 falling V 2.2 CC V V BOT BOD level 4 falling V 2.4 CC BOD level 5 falling V 2.6 CC BOD level 6 falling V 2.8 CC BOD level 7 falling V 3.0 CC Continuous mode 0.4 t Detection time µs BOD Sampled mode 1000 V Hysteresis 1.0 % HYST Note: 1. BOD is calibrated at 85°C within BOD level 0 values, and BOD level 0 is the default level. 32.5.10 External Reset Characteristics Table 32-131. External Reset Characteristics Symbol Parameter Condition Min. Typ. Max. Units t Minimum reset pulse width 1000 90 ns EXT V = 2.7 - 3.6V 0.45 * V CC CC V Reset threshold voltage V RST V = 1.6 - 2.7V 0.45 * V CC CC R Reset pin pull-up resistor 25 k RST XMEGA D3 [DATASHEET] 148 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.5.11 Power-on Reset Characteristics Table 32-132. Power-on Reset Characteristics Symbol Parameter Condition Min. Typ. Max. Units V falls faster than 1V/ms 0.4 1.0 CC V (1) POR threshold voltage falling V POT- CC V falls at 1V/ms or slower 0.8 1.3 V CC V POR threshold voltage rising V 1.3 1.59 POT+ CC Note: 1. V values are only valid when BOD is disabled. When BOD is enabled V = V . POT- POT- POT+ 32.5.12 Flash and EEPROM Memory Characteristics Table 32-133. Endurance and Data Retention Symbol Parameter Condition Min. Typ. Max. Units 25°C 10K Write/Erase cycles 85°C 10K Cycle 105°C 2K Flash 25°C 100 Data retention 85°C 25 Year 105°C 10 25°C 100K Write/Erase cycles 85°C 100K Cycle 105°C 30K EEPROM 25°C 100 Data retention 85°C 25 Year 105°C 10 Table 32-134. Programming Time Symbol Parameter Condition Min. Typ. (1) Max. Units Chip erase (2) 256KB flash, EEPROM 105 Application erase Section erase 6 Page erase 4 Flash Page write 4 ms Atomic page erase and write 8 Page erase 4 EEPROM Page write 4 Atomic page erase and write 8 Notes: 1. Programming is timed from the 2MHz internal oscillator. 2. EEPROM is not erased if the EESAVE fuse is programmed. XMEGA D3 [DATASHEET] 149 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.5.13 Clock and Oscillator Characteristics 32.5.13.1 Calibrated 32.768kHz Internal Oscillator Characteristics Table 32-135. 32.768kHz Internal Oscillator Characteristics Symbol Parameter Condition Min. Typ. Max. Units Frequency 32.768 kHz Factory calibration accuracy T = 85C, V = 3.0V -0.5 0.5 CC % User calibration accuracy -0.5 0.5 32.5.13.2 Calibrated 2MHz RC Internal Oscillator Characteristics Table 32-136. 2MHz Internal Oscillator Characteristics Symbol Parameter Condition Min. Typ. Max. Units DFLL can tune to this frequency over Frequency range 1.8 2.0 2.2 voltage and temperature MHz Factory calibrated frequency 2.0 Factory calibration accuracy T = 85C, V = 3.0V -1.5 1.5 CC User calibration accuracy -0.2 0.2 % DFLL calibration stepsize 0.18 32.5.13.3 Calibrated 32MHz Internal Oscillator Characteristics Table 32-137. 32MHz Internal Oscillator Characteristics Symbol Parameter Condition Min. Typ. Max. Units DFLL can tune to this frequency over Frequency range 30 32 55 voltage and temperature MHz Factory calibrated frequency 32 Factory calibration accuracy T = 85C, V = 3.0V -1.5 1.5 CC User calibration accuracy -0.2 0.2 % DFLL calibration step size 0.19 32.5.13.4 32kHz Internal ULP Oscillator Characteristics Table 32-138. 32kHz Internal ULP Oscillator Characteristics Symbol Parameter Condition Min. Typ. Max. Units Factory calibrated frequency 32 kHz Factory calibration accuracy T = 85C, V = 3.0V -12 12 % CC XMEGA D3 [DATASHEET] 150 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.5.13.5 Internal Phase Locked Loop (PLL) Characteristics Table 32-139. Internal PLL Characteristics Symbol Parameter Condition Min. Typ. Max. Units f Input frequency Output frequency must be within f 0.4 64 IN OUT V = 1.6 - 1.8V 20 48 MHz CC f Output frequency (1) OUT V = 2.7 - 3.6V 20 128 CC Start-up time 25 µs Re-lock time 25 Note: 1. The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than four times the maximum CPU frequency. 32.5.13.6 External Clock Characteristics Figure 32-31.External Clock Drive Waveform t t CH CH t t CR CF V IH1 V IL1 t CL t CK Table 32-140.External Clock used as System Clock without Prescaling Symbol Parameter Condition Min. Typ. Max. Units V = 1.6 - 1.8V 0 12 CC 1/t Clock Frequency (1) MHz CK V = 2.7 - 3.6V 0 32 CC V = 1.6 - 1.8V 83.3 CC t Clock Period CK V = 2.7 - 3.6V 31.5 CC V = 1.6 - 1.8V 30.0 CC t Clock High Time CH V = 2.7 - 3.6V 12.5 CC V = 1.6 - 1.8V 30.0 CC t Clock Low Time ns CL V = 2.7 - 3.6V 12.5 CC V = 1.6 - 1.8V 10 CC t Rise Time (for maximum frequency) CR V = 2.7 - 3.6V 3 CC V = 1.6 - 1.8V 10 CC t Fall Time (for maximum frequency) CF V = 2.7 - 3.6V 3 CC t Change in period from one clock cycle to the next 10 % CK Note: 1. The maximum frequency vs. supply voltage is linear between 1.6V and 2.7V, and the same applies for all other parameters with supply voltage conditions. XMEGA D3 [DATASHEET] 151 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Table 32-141.External Clock with Prescaler (1) for System Clock Symbol Parameter Condition Min. Typ. Max. Units V = 1.6 - 1.8V 0 90 CC 1/t Clock Frequency (2) MHz CK V = 2.7 - 3.6V 0 142 CC V = 1.6 - 1.8V 11 CC t Clock Period CK V = 2.7 - 3.6V 7 CC V = 1.6 - 1.8V 4.5 CC t Clock High Time CH V = 2.7 - 3.6V 2.4 CC V = 1.6 - 1.8V 4.5 CC t Clock Low Time ns CL V = 2.7 - 3.6V 2.4 CC V = 1.6 - 1.8V 1.5 CC t Rise Time (for maximum frequency) CR V = 2.7 - 3.6V 1.0 CC V = 1.6 - 1.8V 1.5 CC t Fall Time (for maximum frequency) CF V = 2.7 - 3.6V 1.0 CC t Change in period from one clock cycle to the next 10 % CK Notes: 1. System Clock Prescalers must be set so that maximum CPU clock frequency for device is not exceeded. 2. The maximum frequency vs. supply voltage is linear between 1.6V and 2.7V, and the same applies for all other parameters with supply voltage conditions. 32.5.13.7 External 16MHz Crystal Oscillator and XOSC Characteristics Table 32-142. External 16MHz Crystal Oscillator and XOSC Characteristics Symbol Parameter Condition Min. Typ. Max. Units FRQRANGE=0 0 XOSCPWR=0 Cycle to cycle jitter FRQRANGE=1, 2, or 3 0 XOSCPWR=1 0 ns FRQRANGE=0 0 XOSCPWR=0 Long term jitter FRQRANGE=1, 2, or 3 0 XOSCPWR=1 0 FRQRANGE=0 0.03 XOSCPWR=0 FRQRANGE=1 0.03 Frequency error FRQRANGE=2 or 3 0.03 XOSCPWR=1 0.003 % FRQRANGE=0 50 XOSCPWR=0 FRQRANGE=1 50 Duty cycle FRQRANGE=2 or 3 50 XOSCPWR=1 50 XMEGA D3 [DATASHEET] 152 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Symbol Parameter Condition Min. Typ. Max. Units 0.4MHz resonator, CL=100pF 44k XOSCPWR=0, 1MHz crystal, CL=20pF 67k FRQRANGE=0 2MHz crystal, CL=20pF 67k 2MHz crystal 82k XOSCPWR=0, FRQRANGE=1, 8MHz crystal 1500 CL=20pF 9MHz crystal 1500 8MHz crystal 2700 XOSCPWR=0, FRQRANGE=2, 9MHz crystal 2700 CL=20pF 12MHz crystal 1000 9MHz crystal 3600 XOSCPWR=0, FRQRANGE=3, 12MHz crystal 1300 R Negative impedance (1) CL=20pF  Q 16MHz crystal 590 9MHz crystal 390 XOSCPWR=1, FRQRANGE=0, 12MHz crystal 50 CL=20pF 16MHz crystal 10 9MHz crystal 1500 XOSCPWR=1, FRQRANGE=1, 12MHz crystal 650 CL=20pF 16MHz crystal 270 XOSCPWR=1, 12MHz crystal 1000 FRQRANGE=2, CL=20pF 16MHz crystal 440 XOSCPWR=1, 12MHz crystal 1300 FRQRANGE=3, CL=20pF 16MHz crystal 590 ESR SF = safety factor min(R )/SF k Q XOSCPWR=0, 0.4MHz resonator, CL=100pF 1.0 FRQRANGE=0 XOSCPWR=0, 2MHz resonator, CL=20pF 2.6 FRQRANGE=1 XOSCPWR=0, Start-up time 8MHz resonator, CL=20pF 0.8 ms FRQRANGE=2 XOSCPWR=0, 12MHz resonator, CL=20pF 1.0 FRQRANGE=3 XOSCPWR=1, 16MHz resonator, CL=20pF 1.4 FRQRANGE=3 XMEGA D3 [DATASHEET] 153 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Symbol Parameter Condition Min. Typ. Max. Units Parasitic capacitance C 5.9 XTAL1 XTAL1 pin Parasitic capacitance pF C 8.3 XTAL2 XTAL2 pin C Parasitic capacitance load 3.5 LOAD Notes: 1. Numbers for negative impedance are not tested in production but guaranteed from design and characterization. 32.5.13.8 External 32.768kHz Crystal Oscillator and TOSC Characteristics Table 32-143. External 32.768kHz Crystal Oscillator and TOSC Characteristics Symbol Parameter Condition Min. Typ. Max. Units Crystal load capacitance 6.5pF 60 Recommended crystal equivalent ESR/R1 Crystal load capacitance 9.0pF 35 k series resistance (ESR) Crystal load capacitance 12pF 28 C Parasitic capacitance TOSC1 pin 3.5 TOSC1 pF C Parasitic capacitance TOSC2 pin 3.5 TOSC2 Capacitance load matched to crystal Recommended safety factor 3 specification Note: See Figure 32-32 for definition. Figure 32-32. TOSC Input Capacitance C C L1 L2 Device internal TOSC1 TOSC2 External 32.768 kHz crystal The parasitic capacitance between the TOSC pins is C + C in series as seen from the crystal when oscillating without L1 L2 external capacitors. XMEGA D3 [DATASHEET] 154 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.5.14 SPI Characteristics Figure 32-33. SPI Timing Requirements in Master Mode SS tMOS tSCKR tSCKF SCK (CPOL = 0) tSCKW SCK (CPOL = 1) tSCKW tMIS tMIH tSCK MISO MSB LSB (Data Input) tMOH tMOH MOSI MSB LSB (Data Output) Figure 32-34.SPI Timing Requirements in Slave Mode SS tSSS tSCKR tSCKF tSSH SCK (CPOL = 0) tSSCKW SCK (CPOL = 1) tSSCKW tSIS tSIH tSSCK MOSI MSB LSB (Data Input) tSOSSS tSOS tSOSSH MISO MSB LSB (Data Output) XMEGA D3 [DATASHEET] 155 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Table 32-144. SPI Timing Characteristics and Requirements Symbol Parameter Condition Min. Typ. Max. Units (See Table 20-3 in t SCK period Master SCK XMEGA D manual) t SCK high/low width Master 0.5 * SCK SCKW t SCK rise time Master 2.7 SCKR t SCK fall time Master 2.7 SCKF t MISO setup to SCK Master 10 MIS t MISO hold after SCK Master 10 MIH t MOSI setup SCK Master 0.5 * SCK MOS t MOSI hold after SCK Master 1 MOH t Slave SCK Period Slave 4 * tClk SSCK PER t SCK high/low width Slave 2 * tClk SSCKW PER ns t SCK rise time Slave 1600 SSCKR t SCK fall time Slave 1600 SSCKF t MOSI setup to SCK Slave 3 SIS t MOSI hold after SCK Slave tClk SIH PER t SS setup to SCK Slave 21 SSS t SS hold after SCK Slave 20 SSH t MISO setup SCK Slave 8 SOS t MISO hold after SCK Slave 13 SOH t MISO setup after SS low Slave 11 SOSS t MISO hold after SS high Slave 8 SOSH 32.5.15 Two-wire Interface Characteristics Table 32-145 on page 157 describes the requirements for devices connected to the Two-Wire Interface Bus. The Atmel AVR XMEGA Two-Wire Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 32-35. Figure 32-35. Two-wire Interface Bus Timing t t of HIGH t t LOW r SCL t tSU;STA t HD;DAT tSU;DAT tSU;STO HD;STA SDA t BUF XMEGA D3 [DATASHEET] 156 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Table 32-145. Two-wire Interface Characteristics Symbol Parameter Condition Min. Typ. Max. Units V Input high voltage 0.7V V + 0.5 IH CC CC V Input low voltage -0.5 0.3V IL CC V V Hysteresis of Schmitt trigger inputs 0.05V (1) hys CC V Output low voltage 3mA, sink current 0 0.4 OL t Rise time for both SDA and SCL 20 + 0.1C (1)(2) 300 r b t Output fall time from V to V 10pF < C < 400pF (2) 20 + 0.1C (1)(2) 250 ns of IHmin ILmax b b t Spikes suppressed by input filter 0 50 SP I Input current for each I/O pin 0.1V < V < 0.9V -10 10 µA I CC I CC C Capacitance for each I/O pin 10 pF I f SCL clock frequency f (3)> max(10f , 250kHz) 0 400 kHz SCL PER SCL 100ns f  100kHz --------------- SCL C V –0.4V b R Value of pull-up resistor ----C----C--------------------  P fSCL > 100kHz 3mA 3----0--0----n---s-- C b f  100kHz 4.0 SCL t Hold time (repeated) START condition HD;STA f > 100kHz 0.6 SCL f  100kHz 4.7 SCL t Low period of SCL clock LOW f > 100kHz 1.3 SCL µs f  100kHz 4.0 SCL t High period of SCL clock HIGH f > 100kHz 0.6 SCL f  100kHz 4.7 Set-up time for a repeated START SCL t SU;STA condition f > 100kHz 0.6 SCL f  100kHz 0 3.45 SCL t Data hold time HD;DAT f > 100kHz 0 0.9 SCL f  100kHz 250 SCL t Data setup time SU;DAT f > 100kHz 100 SCL µs f  100kHz 4.0 SCL t Setup time for STOP condition SU;STO f > 100kHz 0.6 SCL f  100kHz 4.7 Bus free time between a STOP and SCL t BUF START condition f > 100kHz 1.3 SCL Notes: 1. Required only for f > 100kHz. SCL 2. C = Capacitance of one bus line in pF. b 3. f = Peripheral clock frequency.69 PER XMEGA D3 [DATASHEET] 157 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.6 Atmel ATxmega384D3 32.6.1 Absolute Maximum Ratings Stresses beyond those listed in Table 32-146 may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 32-146. Absolute Maximum Ratings Symbol Parameter Condition Min. Typ. Max. Units V Power supply voltage -0.3 4 V CC I Current into a V pin 200 VCC CC mA I Current out of a Gnd pin 200 GND V Pin voltage with respect to Gnd and V -0.5 V + 0.5 V PIN CC CC I I/O pin sink/source current -25 25 mA PIN T Storage temperature -65 150 A °C T Junction temperature 150 j 32.6.2 General Operating Ratings The device must operate within the ratings listed in Table 32-147 in order for all other electrical characteristics and typical characteristics of the device to be valid. Table 32-147. General Operating Conditions Symbol Parameter Condition Min. Typ. Max. Units V Power supply voltage 1.60 3.6 CC V AV Analog supply voltage 1.60 3.6 CC T Temperature range -40 85 A °C T Junction temperature -40 105 j Table 32-148. Operating Voltage and Frequency Symbol Parameter Condition Min. Typ. Max. Units V = 1.6V 0 12 CC V = 1.8V 0 12 CC Clk CPU clock frequency MHz CPU V = 2.7V 0 32 CC V = 3.6V 0 32 CC The maximum CPU clock frequency depends on V . As shown in Figure 32-36 on page 159 the frequency vs. V CC CC curve is linear between 1.8V<V <2.7V. CC XMEGA D3 [DATASHEET] 158 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 32-36. Maximum Frequency vs. V CC MHz 32 Safe operating area 12 1.6 1.8 2.7 3.6 V XMEGA D3 [DATASHEET] 159 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.6.3 Current Consumption Table 32-149. Current Consumption for Active Mode and Sleep Modes Symbol Parameter Condition Min. Typ. Max. Units V = 1.8V 150 CC 32kHz, Ext. Clk V = 3.0V 320 CC V = 1.8V 410 µA CC 1MHz, Ext. Clk Active power V = 3.0V 830 consumption (1) CC V = 1.8V 660 800 CC 2MHz, Ext. Clk 1.3 1.8 V = 3.0V mA CC 32MHz, Ext. Clk 10 15 V = 1.8V 4 CC 32kHz, Ext. Clk V = 3.0V 5 CC V = 1.8V 50 CC 1MHz, Ext. Clk µA Idle power V = 3.0V 100 consumption (1) CC V = 1.8V 100 350 CC 2MHz, Ext. Clk 200 600 V = 3.0V CC I 32MHz, Ext. Clk 3.3 7 mA CC T=25°C 0.2 1.0 T=85°C V = 3.0V 3.5 6.0 CC T=105°C 15 20 Power-down power consumption WDT and sampled BOD enabled, T=25°C 1.5 2.0 WDT and sampled BOD enabled, T = 85°C V = 3.0V 6.0 10 CC WDT and sampled BOD enabled, T= 105°C 16 27 V = 1.8V 1.4 µA RTC from ULP clock, WDT and sampled CC BOD enabled, T=25°C V = 3.0V 1.5 CC V = 1.8V 0.7 2 Power-save power RTC from 1.024kHz low power 32.768kHz CC consumption (2) TOSC, T=25°C V = 3.0V 0.8 2 CC V = 1.8V 0.9 3 RTC from low power 32.768kHz TOSC, CC T=25°C V = 3.0V 1.1 3 CC Reset power consumption Current through RESET pin substracted V = 3.0V 300 CC Notes: 1. All Power Reduction Registers set. 2. Maximum limits are based on characterization, and not tested in production. XMEGA D3 [DATASHEET] 160 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Table 32-150. Current Consumption for Modules and Peripherals Symbol Parameter Condition (1) Min. Typ. Max. Units ULP oscillator 0.93 32.768kHz int. oscillator 27 85 2MHz int. oscillator DFLL enabled with 32.768kHz int. osc. as reference 115 240 32MHz int. oscillator DFLL enabled with 32.768kHz int. osc. as reference 430 µA PLL 20× multiplication factor, 32MHz int. osc. DIV4 as reference 300 Watchdog timer 1.0 Continuous mode 140 BOD Sampled mode, includes ULP oscillator 1.3 I CC Internal 1.0V reference 220 Temperature sensor 215 1.12 CURRLIMIT = LOW 1.01 16ksps, V = Ext. ref. REF CURRLIMIT = MEDIUM 0.9 ADC mA CURRLIMIT = HIGH 0.8 75ksps, V = Ext. ref. CURRLIMIT = LOW 1.7 REF 300ksps, V = Ext. ref. 3.1 REF USART Rx and Tx enabled, 9600 BAUD 9.5 µA Flash memory and EEPROM programming 4.0 mA Note: 1. All parameters measured as the difference in current consumption between module enabled and disabled. All data at V = 3.0V, Clk = 1MHz external clock CC SYS without prescaling, T = 25°C unless other conditions are given. XMEGA D3 [DATASHEET] 161 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.6.4 Wake-up Time from Sleep Modes Table 32-151. Device Wake-up Time from Sleep Modes with Various System Clock Sources Symbol Parameter Condition Min. Typ. (1) Max. Units External 2MHz clock 2.0 Wake-up time from idle, 32.768kHz internal oscillator 130 standby, and extended standby mode 2MHz internal oscillator 2.0 32MHz internal oscillator 0.2 t µs wakeup External 2MHz clock 4.5 Wake-up time from 32.768kHz internal oscillator 320 power-save and power- down mode 2MHz internal oscillator 9.0 32MHz internal oscillator 5.0 Note: 1. The wake-up time is the time from the wake-up request is given until the peripheral clock is available on pin, see Figure 32-37. All peripherals and modules start execution from the first clock cycle, expect the CPU that is halted for four clock cycles before program execution starts. Figure 32-37. Wake-up Time Definition Wakeup time Wakeup request Clock output XMEGA D3 [DATASHEET] 162 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.6.5 I/O Pin Characteristics The I/O pins complies with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output voltage limits reflect or exceed this specification. Table 32-152. I/O Pin Characteristics Symbol Parameter Condition Min. Typ. Max. Units I (1)/ I (2) I/O pin source/sink current -15 15 mA OH OL V = 2.4 - 3.6V 0.7 * V V + 0.5 CC CC CC V High level input voltage IH V = 1.6 - 2.4V 0.8 * V V + 0.5 CC CC CC V = 2.4 - 3.6V -0.5 0.3 * V CC CC V Low level input voltage IL V = 1.6 - 2.4V -0.5 0.2 * V CC CC V = 3.3V I = -4mA 2.6 2.9 CC OH V V High level output voltage V = 3.0V I = -3mA 2.1 2.6 OH CC OH V = 1.8V I = -1mA 1.4 1.6 CC OH V = 3.3V I = 8mA 0.4 0.76 CC OL V Low level output voltage V = 3.0V I = 5mA 0.3 0.64 OL CC OL V = 1.8V I = 3mA 0.2 0.46 CC OL I Input leakage current I/O pin T = 25°C <0.01 1 µA IN R Pull/buss keeper resistor 25 k P Notes: 1. The sum of all I for PORTA and PORTB must not exceed 100mA. OH The sum of all I for PORTC, PORTD, and PORTE must for each port not exceed 200mA. OH The sum of all I for pins PF[0-5] on PORTF must not exceed 200mA. OH The sum of all I for pins PF[6-7] on PORTF, PORTR, and PDI must not exceed 100mA. OL 2. The sum of all I for PORTA and PORTB must not exceed 100mA. OL The sum of all I for PORTC, PORTD, and PORTE must for each port not exceed 200mA. OL The sum of all I for pins PF[0-5] on PORTF must not exceed 200mA. OL The sum of all I for pins PF[6-7] on PORTF, PORTR, and PDI must not exceed 100mA. OL 32.6.6 ADC Characteristics Table 32-153. Power Supply, Reference, and Input Range Symbol Parameter Condition Min. Typ. Max. Units AV Analog supply voltage V - 0.3 V + 0.3 CC CC CC V V Reference voltage 1 AV - 0.6 REF CC R Input resistance Switched 4.5 k in C Input capacitance Switched 5 pF in R Reference input resistance (leakage only) >10 M AREF C Reference input capacitance Static load 7 pF AREF XMEGA D3 [DATASHEET] 163 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Symbol Parameter Condition Min. Typ. Max. Units V Input range 0 V in REF Conversion range Differential mode, Vinp - Vinn -V V V REF REF Conversion range Single ended unsigned mode, Vinp -V V - V REF V Fixed offset voltage 200 lsb Table 32-154. Clock and Timing Symbol Parameter Condition Min. Typ. Max. Units Maximum is 1/4 of peripheral clock frequency 100 1800 Clk ADC clock frequency kHz ADC Measuring internal signals 100 125 f Sample rate 16 300 ClkADC Current limitation (CURRLIMIT) off 16 300 CURRLIMIT = LOW 16 250 ksps f Sample rate ADC CURRLIMIT = MEDIUM 16 150 CURRLIMIT = HIGH 16 50 Configurable in steps of 1/2 Clk cycles up Sampling time ADC 0.28 320 µs to 32 Clk cycles ADC (RES+1)/2 + GAIN Conversion time (latency) 5.5 10 RES (Resolution) = 8 or 12, GAIN = 0 to 3 Clk ADC Start-up time ADC clock cycles 12 24 cycles ADC settling time After changing reference or input mode 7 7 XMEGA D3 [DATASHEET] 164 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Table 32-155. Accuracy Characteristics Symbol Parameter Condition (1) Min. Typ. Max. Units Differential 8 12 12 RES Resolution 12-bit resolution Single ended signed 7 11 11 Bits Single ended unsigned 8 12 12 16ksps, V = 3V 0.5 1 REF 16ksps, all V 0.8 2 REF Differential mode 300ksps, V = 3V 0.6 1 REF INL (2) Integral non-linearity 300ksps, all V 1 2 REF 16ksps, V = 3.0V 0.5 1 Single ended REF unsigned mode 16ksps, all V 1.3 2 REF lsb 16ksps, V = 3V 0.3 1 REF 16ksps, all V 0.5 1 REF Differential mode 300ksps, V = 3V 0.35 1 REF DNL (2) Differential non-linearity 300ksps, all V 0.5 1 REF 16ksps, V = 3.0V 0.6 1 Single ended REF unsigned mode 16ksps, all V 0.6 1 REF 300ksps, V = 3V -7 mV REF Offset error Differential mode Temperature drift, V = 3V 0.01 mV/K REF Operating voltage drift 0.16 mV/V External reference -5 AV /1.6 -5 CC mV AV /2.0 -6 CC Gain error Differential mode Bandgap ±10 Temperature drift 0.02 mV/K Operating voltage drift 2 mV/V External reference -8 AV /1.6 -8 CC mV AV /2.0 -8 Single ended CC Gain error unsigned mode Bandgap ±10 Temperature drift 0.03 mV/K Operating voltage drift 2 mV/V Notes: 1. Unless otherwise noted all linearity, offset and gain error numbers are valid under the condition that external V is used. REF 2. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range. XMEGA D3 [DATASHEET] 165 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Table 32-156. Gain Stage Characteristics Symbol Parameter Condition Min. Typ. Max. Units R Input resistance Switched in normal mode 4.0 k in C Input capacitance Switched in normal mode 4.4 pF sample Signal range Gain stage output 0 AV - 0.6 V CC Propagation delay ADC conversion rate 1/2 1 3 Clk cycles ADC Clock rate Same as ADC 100 1800 kHz 0.5x gain, normal mode -1 1x gain, normal mode -1 Gain error % 8x gain, normal mode -1 64x gain, normal mode 5 0.5x gain, normal mode 10 1x gain, normal mode 5 Offset error, input referred mV 8x gain, normal mode -20 64x gain, normal mode -126 32.6.7 Analog Comparator Characteristics Table 32-157. Analog Comparator Characteristics Symbol Parameter Condition Min. Typ. Max. Units V Input offset voltage 10 mV off I Input leakage current <10 50 nA lk Input voltage range -0.1 AV V CC AC startup time 50 µs V Hysteresis, none V = 1.6V - 3.6V 0 hys1 CC V Hysteresis, small V = 1.6V - 3.6V 15 mV hys2 CC V Hysteresis, large V = 1.6V - 3.6V 30 hys3 CC V = 3.0V, T = 85°C 20 90 CC t Propagation delay ns delay V = 3.0V, T = 85°C 17 CC 64-level voltage scaler Integral non-linearity (INL) 0.3 0.5 lsb Current source accuracy after calibration 5 % Current source calibration range 4 6 µA XMEGA D3 [DATASHEET] 166 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.6.8 Bandgap and Internal 1.0V Reference Characteristics Table 32-158. Bandgap and Internal 1.0V Reference Characteristics Symbol Parameter Condition Min. Typ. Max. Units As reference for ADC 1 Clk + 2.5µs PER Startup time µs As input voltage to ADC and AC 1.5 Bandgap voltage 1.1 V INT1V Internal 1.00V reference T = 85°C, after calibration 0.99 1 1.01 Variation over voltage and temperature Calibrated at T = 85°C 2 % 32.6.9 Brownout Detection Characteristics Table 32-159. Brownout Detection Characteristics (1) Symbol Parameter Condition Min. Typ. Max. Units BOD level 0 falling V 1.60 1.62 1.72 CC BOD level 1 falling V 1.9 CC BOD level 2 falling V 2.0 CC BOD level 3 falling V 2.2 CC V V BOT BOD level 4 falling V 2.4 CC BOD level 5 falling V 2.6 CC BOD level 6 falling V 2.8 CC BOD level 7 falling V 3.0 CC Continuous mode 0.4 t Detection time µs BOD Sampled mode 1000 V Hysteresis 1.0 % HYST Note: 1. BOD is calibrated at 85°C within BOD level 0 values, and BOD level 0 is the default level. 32.6.10 External Reset Characteristics Table 32-160. External Reset Characteristics Symbol Parameter Condition Min. Typ. Max. Units t Minimum reset pulse width 1000 90 ns EXT V = 2.7 - 3.6V 0.45 * V CC CC V Reset threshold voltage V RST V = 1.6 - 2.7V 0.42 * V CC CC R Reset pin pull-up resistor 25 k RST XMEGA D3 [DATASHEET] 167 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.6.11 Power-on Reset Characteristics Table 32-161. Power-on Reset Characteristics Symbol Parameter Condition Min. Typ. Max. Units V falls faster than 1V/ms 0.4 1.0 CC V (1) POR threshold voltage falling V POT- CC V falls at 1V/ms or slower 0.8 1.3 V CC V POR threshold voltage rising V 1.3 1.59 POT+ CC Note: 1. V values are only valid when BOD is disabled. When BOD is enabled V = V . POT- POT- POT+ 32.6.12 Flash and EEPROM Memory Characteristics Table 32-162. Endurance and Data Retention Symbol Parameter Condition Min. Typ. Max. Units 25°C 10K Write/Erase cycles 85°C 10K Cycle 105°C 2K Flash 25°C 100 Data retention 85°C 25 Year 105°C 10 25°C 100K Write/Erase cycles 85°C 100K Cycle 105°C 30K EEPROM 25°C 100 Data retention 85°C 25 Year 105°C 10 Table 32-163. Programming Time Symbol Parameter Condition Min. Typ. (1) Max. Units Chip erase (2) 384KB Flash, EEPROM 130 Application erase Section erase 6 Page erase 6 Flash Page write 6 ms Atomic page erase and write 12 Page erase 6 EEPROM Page write 6 Atomic page erase and write 12 Notes: 1. Programming is timed from the 2MHz internal oscillator. 2. EEPROM is not erased if the EESAVE fuse is programmed. XMEGA D3 [DATASHEET] 168 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.6.13 Clock and Oscillator Characteristics 32.6.13.1 Calibrated 32.768kHz Internal Oscillator Characteristics Table 32-164. 32.768kHz Internal Oscillator Characteristics Symbol Parameter Condition Min. Typ. Max. Units Frequency 32.768 kHz Factory calibration accuracy T = 85C, V = 3.0V -0.5 0.5 CC % User calibration accuracy -0.5 0.5 32.6.13.2 Calibrated 2MHz RC Internal Oscillator Characteristics Table 32-165. 2MHz Internal Oscillator Characteristics Symbol Parameter Condition Min. Typ. Max. Units DFLL can tune to this frequency over Frequency range 1.8 2.2 voltage and temperature MHz Factory calibrated frequency 2.0 Factory calibration accuracy T = 85C, V = 3.0V -1.5 1.5 CC User calibration accuracy -0.2 0.2 % DFLL calibration stepsize 0.23 32.6.13.3 Calibrated 32MHz Internal Oscillator Characteristics Table 32-166. 32MHz Internal Oscillator Characteristics Symbol Parameter Condition Min. Typ. Max. Units DFLL can tune to this frequency over Frequency range 30 32 35 voltage and temperature MHz Factory calibrated frequency 32 Factory calibration accuracy T = 85C, V = 3.0V -1.5 1.5 CC User calibration accuracy -0.2 0.2 % DFLL calibration step size 0.24 32.6.13.4 32kHz Internal ULP Oscillator Characteristics Table 32-167. 32kHz Internal ULP Oscillator Characteristics Symbol Parameter Condition Min. Typ. Max. Units Factory calibrated frequency 26 kHz Factory calibration accuracy T = 85°C, V = 3.0V -12 12 CC % Accuracy -30 30 XMEGA D3 [DATASHEET] 169 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.6.13.5 Internal Phase Locked Loop (PLL) Characteristics Table 32-168. Internal PLL Characteristics Symbol Parameter Condition Min. Typ. Max. Units f Input frequency Output frequency must be within f 0.4 64 IN OUT V = 1.6 - 1.8V 20 48 MHz CC f Output frequency (1) OUT V = 2.7 - 3.6V 20 128 CC Start-up time 25 µs Re-lock time 25 Note: 1. The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than four times the maximum CPU frequency. 32.6.13.6 External Clock Characteristics Figure 32-38. External Clock Drive Waveform t t CH CH t t CR CF V IH1 V IL1 t CL t CK Table 32-169.External Clock used as System Clock without Prescaling Symbol Parameter Condition Min. Typ. Max. Units V = 1.6 - 0 12 1/t Clock Frequency (1) CC MHz CK V = 2.7 - 0 32 CC V = 1.6 - 83.3 t Clock Period CC CK V = 2.7 - 31.5 CC V = 1.6 - 30.0 t Clock High Time CC CH V = 2.7 - 12.5 CC V = 1.6 - 30.0 t Clock Low Time CC ns CL V = 2.7 - 12.5 CC V = 1.6 - 10 t Rise Time (for maximum frequency) CC CR V = 2.7 - 3 CC V = 1.6 - 10 t Fall Time (for maximum frequency) CC CF V = 2.7 - 3 CC t Change in period from one clock cycle to the next 10 % CK Note: 1. The maximum frequency vs. supply voltage is linear between 1.6V and 2.7V, and the same applies for all other parameters with supply voltage conditions. XMEGA D3 [DATASHEET] 170 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Table 32-170.External Clock with Prescaler (1) for System Clock Symbol Parameter Condition Min. Typ. Max. Units V = 1.6 - 1.8V 0 90 CC 1/t Clock Frequency (2) MHz CK V = 2.7 - 3.6V 0 142 CC V = 1.6 - 1.8V 11 CC t Clock Period CK V = 2.7 - 3.6V 7 CC V = 1.6 - 1.8V 4.5 CC t Clock High Time CH V = 2.7 - 3.6V 2.4 CC V = 1.6 - 1.8V 4.5 CC t Clock Low Time ns CL V = 2.7 - 3.6V 2.4 CC V = 1.6 - 1.8V 1.5 CC t Rise Time (for maximum frequency) CR V = 2.7 - 3.6V 1.0 CC V = 1.6 - 1.8V 1.5 CC t Fall Time (for maximum frequency) CF V = 2.7 - 3.6V 1.0 CC t Change in period from one clock cycle to the next 10 % CK Notes: 1. System Clock Prescalers must be set so that maximum CPU clock frequency for device is not exceeded. 2. The maximum frequency vs. supply voltage is linear between 1.6V and 2.7V, and the same applies for all other parameters with supply voltage conditions. 32.6.13.7 External 16MHz Crystal Oscillator and XOSC Characteristics Table 32-171.External 16MHz Crystal Oscillator and XOSC Characteristics Symbol Parameter Condition Min. Typ. Max. Units FRQRANGE=0 0 XOSCPWR=0 Cycle to cycle jitter FRQRANGE=1, 2, or 3 0 XOSCPWR=1 0 ns FRQRANGE=0 0 XOSCPWR=0 Long term jitter FRQRANGE=1, 2, or 3 0 XOSCPWR=1 0 FRQRANGE=0 0.03 XOSCPWR=0 FRQRANGE=1 0.03 Frequency error % FRQRANGE=2 or 3 0.03 XOSCPWR=1 0.003 FRQRANGE=0 50 XOSCPWR=0 FRQRANGE=1 50 Duty cycle % FRQRANGE=2 or 3 50 XOSCPWR=1 50 XMEGA D3 [DATASHEET] 171 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Symbol Parameter Condition Min. Typ. Max. Units 0.4MHz resonator, 44k CL=100pF XOSCPWR=0, FRQRANGE=0 1MHz crystal, CL=20pF 67k 2MHz crystal, CL=20pF 67k 2MHz crystal 82k XOSCPWR=0, FRQRANGE=1, 8MHz crystal 1500 CL=20pF 9MHz crystal 1500 8MHz crystal 2700 XOSCPWR=0, FRQRANGE=2, 9MHz crystal 2700 CL=20pF 12MHz crystal 1000 9MHz crystal 3600 XOSCPWR=0, FRQRANGE=3, 12MHz crystal 1300 R Negative impedance (1)  Q CL=20pF 16MHz crystal 590 9MHz crystal 390 XOSCPWR=1, FRQRANGE=0, 12MHz crystal 50 CL=20pF 16MHz crystal 10 9MHz crystal 1500 XOSCPWR=1, FRQRANGE=1, 12MHz crystal 650 CL=20pF 16MHz crystal 270 XOSCPWR=1, 12MHz crystal 1000 FRQRANGE=2, CL=20pF 16MHz crystal 440 XOSCPWR=1, 12MHz crystal 1300 FRQRANGE=3, CL=20pF 16MHz crystal 590 ESR SF = safety factor min(R )/SF k Q XOSCPWR=0, 0.4MHz resonator, 1.0 FRQRANGE=0 CL=100pF XOSCPWR=0, 2MHz crystal, CL=20pF 2.6 FRQRANGE=1 XOSCPWR=0, Start-up time 8MHz crystal, CL=20pF 0.8 ms FRQRANGE=2 XOSCPWR=0, 12MHz crystal, CL=20pF 1.0 FRQRANGE=3 XOSCPWR=1, 16MHz crystal, CL=20pF 1.4 FRQRANGE=3 XMEGA D3 [DATASHEET] 172 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Symbol Parameter Condition Min. Typ. Max. Units Parasitic capacitance C 5.9 XTAL1 XTAL1 pin Parasitic capacitance pF C 8.3 XTAL2 XTAL2 pin C Parasitic capacitance load 3.5 LOAD Note: 1. Numbers for negative impedance are not tested in production but guaranteed from design and characterization. 32.6.13.8 External 32.768kHz Crystal Oscillator and TOSC Characteristics Table 32-172. External 32.768kHz Crystal Oscillator and TOSC Characteristics Symbol Parameter Condition Min. Typ. Max. Units Crystal load capacitance 6.5pF 60 Recommended crystal equivalent ESR/R1 Crystal load capacitance 9.0pF 35 k series resistance (ESR) Crystal load capacitance 12pF 28 C Parasitic capacitance TOSC1 pin 3.5 TOSC1 pF C Parasitic capacitance TOSC2 pin 3.5 TOSC2 Capacitance load matched to crystal Recommended safety factor 3 specification Note: See Figure 32-39 on page 173 for definition. Figure 32-39. TOSC Input Capacitance C C L1 L2 Device internal TOSC1 TOSC2 External 32.768 kHz crystal The parasitic capacitance between the TOSC pins is C + C in series as seen from the crystal when oscillating without L1 L2 external capacitors. XMEGA D3 [DATASHEET] 173 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

32.6.14 SPI Characteristics Figure 32-40. SPI Timing Requirements in Master Mode SS tMOS tSCKR tSCKF SCK (CPOL = 0) tSCKW SCK (CPOL = 1) tSCKW tMIS tMIH tSCK MISO MSB LSB (Data Input) tMOH tMOH MOSI MSB LSB (Data Output) Figure 32-41.SPI Timing Requirements in Slave Mode SS tSSS tSCKR tSCKF tSSH SCK (CPOL = 0) tSSCKW SCK (CPOL = 1) tSSCKW tSIS tSIH tSSCK MOSI MSB LSB (Data Input) tSOSSS tSOS tSOSSH MISO MSB LSB (Data Output) XMEGA D3 [DATASHEET] 174 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Table 32-173. SPI Timing Characteristics and Requirements Symbol Parameter Condition Min. Typ. Max. Units (See Table 20-3 in t SCK period Master SCK XMEGA D manual) t SCK high/low width Master 0.5 * SCK SCKW t SCK rise time Master 2.7 SCKR t SCK fall time Master 2.7 SCKF t MISO setup to SCK Master 10 MIS t MISO hold after SCK Master 10 MIH t MOSI setup SCK Master 0.5 * SCK MOS t MOSI hold after SCK Master 1 MOH t Slave SCK Period Slave 4 * tClk SSCK PER t SCK high/low width Slave 2 * tClk SSCKW PER ns t SCK rise time Slave 1600 SSCKR t SCK fall time Slave 1600 SSCKF t MOSI setup to SCK Slave 3 SIS t MOSI hold after SCK Slave tClk SIH PER t SS setup to SCK Slave 21 SSS t SS hold after SCK Slave 20 SSH t MISO setup SCK Slave 8 SOS t MISO hold after SCK Slave 13 SOH t MISO setup after SS low Slave 11 SOSS t MISO hold after SS high Slave 8 SOSH 32.6.15 Two-wire Interface Characteristics Table 32-174 on page 176 describes the requirements for devices connected to the Two-Wire Interface Bus. The Atmel AVR XMEGA Two-Wire Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 32-42. Figure 32-42. Two-wire Interface Bus Timing t t of HIGH t t LOW r SCL t tSU;STA t HD;DAT tSU;DAT tSU;STO HD;STA SDA t BUF XMEGA D3 [DATASHEET] 175 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Table 32-174. Two-wire Interface Characteristics Symbol Parameter Condition Min. Typ. Max. Units V Input high voltage 0.7V V + 0.5 IH CC CC V Input low voltage -0.5 0.3V IL CC V V Hysteresis of Schmitt trigger inputs 0.05V (1) hys CC V Output low voltage 3mA, sink current 0 0.4 OL t Rise time for both SDA and SCL 20 + 0.1C (1)(2) 300 r b t Output fall time from V to V 10pF < C < 400pF (2) 20 + 0.1C (1)(2) 250 ns of IHmin ILmax b b t Spikes suppressed by input filter 0 50 SP I Input current for each I/O pin 0.1V < V < 0.9V -10 10 µA I CC I CC C Capacitance for each I/O pin 10 pF I f SCL clock frequency f (3)> max(10f , 250kHz) 0 400 kHz SCL PER SCL 100ns f  100kHz --------------- SCL C V –0.4V b R Value of pull-up resistor ----C----C--------------------  P fSCL > 100kHz 3mA 3----0--0----n---s-- C b f  100kHz 4.0 SCL t Hold time (repeated) START condition HD;STA f > 100kHz 0.6 SCL f  100kHz 4.7 SCL t Low period of SCL clock LOW f > 100kHz 1.3 SCL µs f  100kHz 4.0 SCL t High period of SCL clock HIGH f > 100kHz 0.6 SCL f  100kHz 4.7 Set-up time for a repeated START SCL t SU;STA condition f > 100kHz 0.6 SCL f  100kHz 0 3.45 SCL t Data hold time HD;DAT f > 100kHz 0 0.9 SCL f  100kHz 250 SCL t Data setup time SU;DAT f > 100kHz 100 SCL µs f  100kHz 4.0 SCL t Setup time for STOP condition SU;STO f > 100kHz 0.6 SCL f  100kHz 4.7 Bus free time between a STOP and SCL t BUF START condition f > 100kHz 1.3 SCL Notes: 1. Required only for f > 100kHz. SCL 2. C = Capacitance of one bus line in pF. b 3. f = Peripheral clock frequency. PER XMEGA D3 [DATASHEET] 176 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33. Typical Characteristics 33.1 Atmel ATxmega32D3 33.1.1 Current Consumption 33.1.1.1 Active Mode Supply Current Figure 33-1. Active Supply Current vs. Frequency f =0 - 1MHz external clock, T = 25°C SYS 800 3.6 V 700 3.3 V 600 3.0 V 500 2.7 V A] µ V [ 400 2.2 V c c I 300 1.8 V 1.6 V 200 100 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz] Figure 33-2. Active Supply Current vs. Frequency f =1 - 32MHz external clock, T = 25°C SYS 12 3.6 V 10 3.3 V 8 3.0 V A ] 2.7 V m 6 c [ c I 4 2.2 V 2 1.8 V 1.6 V 0 0 4 8 12 16 20 24 28 32 Frequency [MHz] XMEGA D3 [DATASHEET] 177 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-3. Active Mode Supply Current vs. V CC f =32.768kHz internal oscillator SYS 250 -40 °C 225 25 °C 200 85 °C 175 105 °C A] µ 150 [ c Ic 125 100 75 50 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V [V] CC Figure 33-4. Active Mode Supply Current vs. V CC f =1MHz external clock SYS 900 -40°C 800 25 °C 85 °C 700 105 °C 600 A] µ c [ 500 c I 400 300 200 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V [V] CC XMEGA D3 [DATASHEET] 178 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-5. Active Mode Supply Current vs. V CC f =2MHz internal oscillator SYS 1300 -40 °C 1200 25 °C 85 °C 1100 105 °C 1000 A] 900 µ [ c 800 c I 700 600 500 400 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V [V] CC Figure 33-6. Active Mode Supply Current vs. V CC f =32MHz internal oscillator prescaled to 8MHz SYS 5.0 -40 °C 4.5 25 °C 85 °C 4.0 105 °C 3.5 A] m [ 3.0 c c I 2.5 2.0 1.5 1.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V [V] CC XMEGA D3 [DATASHEET] 179 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-7. Active Mode Supply Current vs. V CC f =32MHz internal oscillator SYS 12.0 11.0 -40 °C 25 °C 10.0 85 °C A] 105 °C m 9.0 [ c c I 8.0 7.0 6.0 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 V [V] CC 33.1.1.2 Idle Mode Supply Current Figure 33-8. Idle Mode Supply Current vs. Frequency f =0 - 1MHz external clock, T = 25°C SYS 140 120 3.6 V 3.3 V 100 3.0 V A] 80 2.7 V µ c [ c 60 2.2 V I 1.8 V 40 1.6 V 20 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency[MHz] XMEGA D3 [DATASHEET] 180 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-9. Idle Mode Supply Current vs. Frequency f =1 - 32MHz external clock, T = 25°C SYS 4.5 4.0 3.6 V 3.5 3.3 V 3.0 3.0 V A] m 2.5 2.7 V c [ c I 2.0 1.5 2.2 V 1.0 1.8 V 0.5 1.6 V 0 0 4 8 12 16 20 24 28 32 Frequency [MHz] Figure 33-10.Idle Mode Supply Current vs. V CC f =32.768kHz internal oscillator SYS 46 105°C 44 42 40 A] 38 µ c [ 36 85 °C c I 34 -40 °C 32 25 °C 30 28 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V [V] CC XMEGA D3 [DATASHEET] 181 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-11.Idle Mode Supply Current vs. V CC f =1MHz external clock SYS 135 105 °C 125 85 °C 25° C 115 -40 °C 105 95 A] [µ 85 c c I 75 65 55 45 35 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V [V] CC Figure 33-12.Idle Mode Supply Current vs. V CC f =2MHz internal oscillator SYS 365 -40 °C 340 25 °C 85 °C 315 105 °C 290 A] 265 µ [ c 240 c I 215 190 165 140 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V [V] CC XMEGA D3 [DATASHEET] 182 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-13.Idle Mode Supply Current vs. V CC f =32MHz internal oscillator prescaled to 8MHz SYS 1600 -40 °C 25 °C 1500 85 °C 1400 105 °C 1300 1200 A] 1100 µ c [ 1000 c I 900 800 700 600 500 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V [V] CC Figure 33-14.Idle Mode Current vs. V CC f =32MHz internal oscillator SYS 4.5 -40 °C 4.3 25 °C 85 °C 4.1 105 °C 3.9 A] 3.7 m [ c 3.5 c I 3.3 3.1 2.9 2.7 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 VCC [V] XMEGA D3 [DATASHEET] 183 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33.1.1.3Power-down Mode Supply Current Figure 33-15.Power-down Mode Supply Current vs. V CC All functions disabled 5.0 105 °C 4.5 4.0 3.5 3.0 A] µ [ 2.5 c c I 2.0 1.5 85 °C 1.0 0.5 25 °C 0.0 -40 °C 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V [V] CC Figure 33-16.Power-down Mode Supply Current vs. V CC Watchdog and sampled BOD enabled 6.0 5.5 105 °C 5.0 4.5 4.0 A] µ 3.5 [ c Ic 3.0 85 °C 2.5 2.0 1.5 25 °C -40 °C 1.0 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V [V] CC XMEGA D3 [DATASHEET] 184 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-17.Power-down Mode Supply Current vs. Temperature All functions disabled 4.8 3.6 V 4.3 3.3 V 3.0 V 3.8 2.7 V 3.3 2.2 V 1.8 V 2.8 1.6 V A] µ c [ 2.3 c I 1.8 1.3 0.8 0.3 -0.2 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] Figure 33-18.Power-down Mode Supply Current vs. Temperature Watchdog and sampled BOD enabled and running from internal ULP oscillator 6.0 5.5 3.6 V 3.3 V 5.0 3.0 V 2.7 V 4.5 2.2 V 4.0 1.8 V A] c [µ 3.5 c I 3.0 2.5 2.0 1.5 1.0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] XMEGA D3 [DATASHEET] 185 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33.1.2 I/O Pin Characteristics 33.1.2.1 Pull-up Figure 33-19.I/O Pin Pull-up Resistor Current vs. Input Voltage V = 1.8V CC 70 60 50 40 A] µ I [ 30 20 -40 °C 25 °C 10 85 °C 105 °C 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VPIN [V] Figure 33-20.I/O Pin Pull-up Resistor Current vs. Input Voltage V = 3.0V CC 120 108 96 84 72 A] µ 60 I [ 48 36 -40 °C 24 25 °C 85 °C 12 105 °C 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 VPIN [V] XMEGA D3 [DATASHEET] 186 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-21.I/O Pin Pull-up Resistor Current vs. Input Voltage V = 3.3V CC 140 120 100 80 A] µ I [ 60 40 -40 °C 25 °C 20 85 °C 105 °C 0 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 VPIN [V] 33.1.2.2 Output Voltage vs. Sink/Source Current Figure 33-22.I/O Pin Output Voltage vs. Source Current V = 1.8V CC 2.0 1.8 1.6 1.4 1.2 ] V 25 °C [ -40 °C 105 °C N 1.0 PI V 0.8 0.6 85 °C 0.4 0.2 0.0 -5.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 I [mA] PIN XMEGA D3 [DATASHEET] 187 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-23.I/O Pin Output Voltage vs. Source Current V = 3.0V CC 3.5 3.0 2.5 V] 2.0 [ N PI 1.5 V -40 °C 1.0 85 °C 25 °C 0.5 105 °C 0.0 -16 -14 -12 -10 -8 -6 -4 -2 0 I [mA] PIN Figure 33-24.I/O Pin Output Voltage vs. Source Current V = 3.3V CC 3.5 3.0 2.5 2.0 V] [ -40 °C N PI V 1.5 25 °C 1.0 85 °C 0.5 105 °C 0.0 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 I [mA] PIN XMEGA D3 [DATASHEET] 188 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-25.I/O Pin Output Voltage vs. Sink Current V = 1.8V CC 1.8 105 °C 85 °C 1.6 1.4 1.2 V] 1.0 [N VPI 0.8 25 °C 0.6 -40 °C 0.4 0.2 0.0 0 1 2 3 4 5 6 7 8 9 IPIN [mA] Figure 33-26.I/O Pin Output Voltage vs. Sink Current V = 3.0V CC 1.1 1.0 105 °C 85 °C 0.9 0.8 25 °C -40 °C 0.7 V] [N 0.6 PI 0.5 V 0.4 0.3 0.2 0.1 0.0 0 2 4 6 8 10 12 14 16 IPIN [mA] XMEGA D3 [DATASHEET] 189 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-27.I/O Pin Output Voltage vs. Sink Current V = 3.3V CC 1.4 105 °C 1.2 85 °C 1.0 25 °C -40 °C V] 0.8 [N PI V 0.6 0.4 0.2 0.0 0 2 4 6 8 10 12 14 16 18 20 IPIN [mA] 33.1.2.3Thresholds and Hysteresis Figure 33-28.I/O Pin Input Threshold Voltage vs. V CC V I/O pin read as “1” IH 1.8 -40 °C 1.7 25 °C 1.6 85 °C 105 °C 1.5 V] 1.4 [ d ol 1.3 h s e hr 1.2 Vt 1.1 1.0 0.9 0.8 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V [V] CC XMEGA D3 [DATASHEET] 190 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-29.I/O Pin Input Threshold Voltage vs. V CC V I/O pin read as “0” IL 1.6 105 °C 1.5 85 °C 1.4 25 °C 1.3 -40 °C 1.2 ] V [ 1.1 d ol sh 1.0 e hr Vt 0.9 0.8 0.7 0.6 0.5 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V [V] CC Figure 33-30.I/O Pin Input Hysteresis vs. V CC 0.39 0.36 0.33 V] 0.30 [ d ol 0.27 h s e Vthr 0.24 - 40 °C 25 °C 0.21 85 °C 0.18 105° C 0.15 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V [V] CC XMEGA D3 [DATASHEET] 191 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33.1.3 ADC Characteristics Figure 33-31.INL Error vs. External V REF T = 25C, V = 3.6V, external reference CC 1.6 1.4 1.2 Single-ended unsigned mode B] 1.0 S L L[ 0.8 N I 0.6 Differential mode 0.4 Single -ended signed mode 0.2 0.0 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 VREF [V] Figure 33-32.INL Error vs. Sample Rate T = 25C, V = 3.6V, V = 3.0V external CC REF 0.70 0.65 Single-ended unsigned mode 0.60 0.55 B] S 0.50 Differential mode L L[ N 0.45 I 0.40 0.35 Single-ended signed mode 0.30 0.25 50 100 150 200 250 300 ADC sample rate [ksps] XMEGA D3 [DATASHEET] 192 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-33.INL Error vs. Input Code 1.25 1.00 0.75 0.50 B] S 0.25 L L[ 0.00 N I -0.25 -0.50 -0.75 -1.00 -1.25 0 512 1024 1536 2048 2560 3072 3584 4096 ADC input code Figure 33-34.DNL Error vs. External V REF T = 25C, V = 3.6V, external reference CC 0.70 0.65 0.60 Single-ended unsigned mode 0.55 B] S 0.50 L L [ 0.45 N D 0.40 Differential mode 0.35 0.30 Single-ended signed mode 0.25 0.20 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 VREF [V] XMEGA D3 [DATASHEET] 193 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-35.DNL Error vs. Sample Rate T = 25C, V = 3.6V, V = 3.0V external CC REF 0.60 0.55 Single-ended unsigned mode 0.50 B] 0.45 S L L [ 0.40 N D Differential mode 0.35 0.30 Single-ended signed mode 0.25 0.20 50 100 150 200 250 300 ADC sample rate [ksps] Figure 33-36.DNL Error vs. Input Code 1 0.8 ] 0.6 B S L 0.4 [ L N 0.2 D 0 -0.2 -0.4 -0.6 0 512 1024 1536 2048 2560 3072 3584 4096 ADC input code XMEGA D3 [DATASHEET] 194 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-37.Gain Error vs. V REF T = 25C, V = 3.6V, ADC sample rate = 300ksps CC -5 -6 ] -7 V Differential mode m -8 [ r o -9 r er Single-ended signed mode n -10 ai G -11 -12 -13 Single-ended unsigned mode -14 -15 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 VREF [V] Figure 33-38.Gain Error vs. V CC T = 25C, V = external 1.0V, ADC sample rate = 300ksps REF -2 -3 ] V -4 m [ Differential mode r -5 o r Single-ended signed r e mode n -6 ai G Single-ended unsigned mode -7 -8 -9 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] XMEGA D3 [DATASHEET] 195 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-39.Offset error vs. V . REF T = 25C, V = 3.6V, ADC sample rate = 300ksps. CC 9.4 9.2 9.0 V] 8.8 m r [ 8.6 Differential mode rro 8.4 e et 8.2 Offs 8.0 7.8 7.6 7.4 7.2 7.0 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 VREF [V] Figure 33-40.Gain Error vs. Temperature V = 3.0V, V = external 2.0V CC REF 0 -2 Single-ended signed mode V] -4 m [ or -6 r r e Differential mode n -8 ai G -10 Single-ended unsigned mode -12 -14 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] XMEGA D3 [DATASHEET] 196 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-41.Offset Error vs. V CC T = 25C, V = external 1.0V, ADC sample rate = 300ksps REF 8.00 7.00 ] V m 6.00 [ r 5.00 o r Differential mode r e 4.00 et s Off 3.00 2.00 1.00 0.00 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] 33.1.4 Analog Comparator Characteristics Figure 33-42.Analog Comparator Hysteresis vs. V CC Small hysteresis 19 105°C 18 85°C 17 16 V] 25°C m 15 [T S VHY 14 -40°C 13 12 11 10 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC[V] XMEGA D3 [DATASHEET] 197 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-43.Analog Comparator Hysteresis vs. V CC Large hysteresis 38 105 °C 36 85°C 34 V] 32 m 25°C [T 30 S Y VH 28 -40°C 26 24 22 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC[V] Figure 33-44.Analog Comparator Current Source vs. Calibration Value V = 3.0V CC 7.0 6.5 A] µ [E 6.0 C R U O 5.5 S T N E R R 5.0 U C I 4.5 -40 °C 25 °C 4.0 85 °C 105 °C 3.5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CURRCALIBA[3..0] XMEGA D3 [DATASHEET] 198 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-45.Voltage Scaler INL vs. SCALEFAC T = 25C, V = 3.0V CC 0.425 0.4 0.375 25°C B] 0.35 S L L [ 0.325 N I 0.3 0.275 0.25 0 5 10 15 20 25 30 35 40 45 50 55 60 65 SCALEFAC 33.1.5 Internal 1.0V Reference Characteristics Figure 33-46.ADC Internal 1.0V Reference vs. Temperature 1.010 1.005 1.8 V 2.7 V ] V 1.000 3.0 V e [ g a olt 0.995 V p 0.990 a g d n a 0.985 B 0.980 0.975 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] XMEGA D3 [DATASHEET] 199 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33.1.6 BOD Characteristics Figure 33-47.BOD Thresholds vs. Temperature BOD level = 1.6V 1.623 1.622 1.621 1.620 V] [T 1.619 O B V 1.618 1.617 1.616 1.615 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] Figure 33-48.BOD Thresholds vs. Temperature BOD level = 3.0V 3.066 3.063 3.060 3.057 V] 3.054 [ T O 3.051 B V 3.048 3.045 3.042 3.039 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] XMEGA D3 [DATASHEET] 200 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33.1.7 External Reset Characteristics Figure 33-49.Minimum Reset Pin Pulse Width vs. V CC 144 136 128 120 ] s n 112 [T S R t 104 105 °C 85 °C 96 25 °C 88 -40 °C 80 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 33-50.Reset Pin Pull-up Resistor Current vs. Reset Pin Voltage V = 1.8V CC 80 70 60 50 A] µ [ET 40 S E IR 30 20 -40 °C 25 °C 10 85 °C 105° C 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VRESET [V] XMEGA D3 [DATASHEET] 201 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-51.Reset Pin Pull-up Resistor Current vs. Reset Pin Voltage V = 3.0V CC 120 108 96 84 A] 72 µ [ET 60 S E R 48 I 36 -40 °C 24 25 °C 12 85 °C 105 °C 0 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 VRESET [V] Figure 33-52.Reset Pin Pull-up Resistor Current vs. Reset Pin Voltage V = 3.3V CC 140 120 100 A] µ 80 [T E S E 60 R I 40 -40 °C 25 °C 20 85 °C 105 °C 0 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 VRESET [V] XMEGA D3 [DATASHEET] 202 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-53.Reset Pin Input Threshold Voltage vs. V CC V - Reset pin read as “1” IH 1.8 105 °C 1.6 85 °C 25 °C 1.4 - 40 °C V] 1.2 D [ L 1.0 O H S E 0.8 R H T V 0.6 0.4 0.2 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] 33.1.8 Oscillator Characteristics 33.1.8.1 Ultra Low-power Internal Oscillator Figure 33-54. Ultra Low-power Internal Oscillator Frequency vs. Temperature 34.0 33.5 z] 33.0 H k y [ 32.5 c n e 32.0 u q e r 31.5 F 31.0 3.3 V 3.0 V 30.5 2.7 V 1.8 V 30.0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] XMEGA D3 [DATASHEET] 203 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33.1.8.2 32.768kHz Internal Oscillator Figure 33-55. 32.768kHz Internal Oscillator Frequency vs. Temperature 32.9 1.6 V 32.9 1.8 V 2.2 V 32.8 2.7 V z] 3.0 V H k 32.8 3.6 V [ y c 32.7 n e u q 32.7 e r F 32.6 32.6 32.5 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] Figure 33-56. 32.768kHz Internal Oscillator Frequency vs. Calibration Value V = 3.0V, T = 25°C CC 50 3.0 V 47 44 41 z] H k 38 [ y c 35 n e qu 32 e r F 29 26 23 20 -4 16 36 56 76 96 116 136 156 176 196 216 236 256 RC32KCAL[7..0] XMEGA D3 [DATASHEET] 204 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33.1.8.3 2MHz Internal Oscillator Figure 33-57. 2MHz Internal Oscillator Frequency vs. Temperature DFLL disabled 2.14 2.12 2.10 Hz] 2.08 M y [ 2.06 c n e 2.04 u q 3.6 V e 2.02 r F 3.0 V 2.00 2.7 V 2.2 V 1.98 1.8 V 1.6 V 1.96 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] Figure 33-58. 2MHz Internal Oscillator Frequency vs. Temperature DFLL enabled, from the 32.768kHz internal oscillator 2.009 2.006 2.7 V 3.6 V 2.003 3.0 V Hz] 1.8 V 1.6 V 2.000 M [ 2.2 V y c 1.997 n e u q 1.994 e r F 1.991 1.988 1.985 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] XMEGA D3 [DATASHEET] 205 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-59. 2MHz Internal Oscillator Frequency vs. CALA Calibration Value V = 3V CC 2.4 -40 °C 2.3 25 °C 85 °C z] 2.2 105 °°C H M [ 2.1 y c n e 2.0 u q e r F 1.9 1.8 1.7 0 16 32 48 64 80 96 112 128 CALA 33.1.8.4 32MHz Internal Oscillator Figure 33-60. 32MHz Internal Oscillator Frequency vs. Temperature DFLL disabled 36.0 35.5 35.0 z] 34.5 H M 34.0 [ y c 33.5 n e u 33.0 q 3.6 V e Fr 32.5 3.0 V 2.7 V 32.0 2.2 V 31.5 1.8 V 1.6 V 31.0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperatuire [°C] XMEGA D3 [DATASHEET] 206 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-61. 32MHz Internal Oscillator Frequency vs. Temperature DFLL enabled, from the 32.768kHz internal oscillator 32.10 2.2 V 32.07 2.7 V 1.6 V 3.0 V 32.04 3.6 V Hz] 32.01 M [ 31.98 y c n e 31.95 u 1.8 V q e 31.92 r F 31.89 31.86 31.83 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] Figure 33-62. 32MHz Internal Oscillator CALA Calibration Step Size T = -40°C, V = 3.0V CC 0.31 % 0.29 % %] 0.27 % e [ 0.26 % z si 0.24 % p e St 0.22 % y c 0.20 % n e u 0.18 % q e Fr 0.17 % 0.15 % -40 °C 0.13 % 0 16 32 48 64 80 96 112 128 CALA XMEGA D3 [DATASHEET] 207 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-63. 32MHz Internal Oscillator CALA Calibration Step Size T = 25°C, V = 3.0V CC 0.26 % 0.24 % %] e [ 0.22 % z si p 0.20 % e 25 °C St y 0.18 % c n e u q 0.16 % e r F 0.14 % 0.12 % 0 16 32 48 64 80 96 112 128 CALA Figure 33-64. 32MHz Internal Oscillator CALA Calibration Step Size T = 85°C, V = 3.0V CC 0.24 % 0.23 % %] 0.21 % e [ z 0.20 % si p e 0.19 % St y 0.18 % c n ue 0.17 % q e 85 °C r 0.15 % F 0.14 % 0.13 % 0 16 32 48 64 80 96 112 128 CALA XMEGA D3 [DATASHEET] 208 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-65. 32MHz Internal Oscillator CALA Calibration Step Size T = 105°C, V = 3.0V CC 0.22 % 0.21 % %] 0.20 % e [ z si 0.19 % p e St 0.18 % y c n 0.17 % e u q e 0.16 % r F 105 °C 0.15 % 0.14 % 0 16 32 48 64 80 96 112 128 CALA Figure 33-66. 32MHz Internal Oscillator Frequency vs. CALB Calibration Value V = 3.0V CC 75 70 -40 °C 25 °C 65 85 °C 60 105 °C z] H 55 M [ 50 y c n 45 e u q 40 e r F 35 30 25 20 0 7 14 21 28 35 42 49 56 63 CALB XMEGA D3 [DATASHEET] 209 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33.1.8.5 32MHz Internal Oscillator Calibrated to 48MHz Figure 33-67. 48MHz Internal Oscillator Frequency vs. Temperature DFLL disabled 55 54 53 Hz] 52 M [ 51 y c n e 50 u q e 49 3.6 V r F 3.0 V 48 2.7 V 2.2 V 47 1.8 V 1.6 V 46 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] Figure 33-68. 48MHz Internal Oscillator Frequency vs. Temperature DFLL enabled, from the 32.768kHz internal oscillator 48.20 48.15 1.6 V 1.8 V 2.2 V 48.10 3.6 V z] 2.7 V H 48.05 3.0 V M [ 48.00 y c n e 47.95 u q e 47.90 r F 47.85 47.80 47.75 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] XMEGA D3 [DATASHEET] 210 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33.1.9 Two-Wire Interface Characteristics Figure 33-69.SDA Hold Time vs. Temperature 500 450 3 400 350 s] 2 e [n 300 m 250 d ti ol 200 H 150 100 50 1 0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 33-70.SDA Hold Time vs. Supply Voltage 500 450 3 400 350 s] 2 n e [ 300 m 250 d ti ol 200 H 150 100 50 1 0 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 V [V] CC XMEGA D3 [DATASHEET] 211 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33.1.10 PDI Characteristics Figure 33-71.Maximum PDI Frequency vs. V CC 24 -40 °C 22 20 25 °C 18 z] 85 °C H 105 °C M 16 [X A 14 M f 12 10 8 6 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] XMEGA D3 [DATASHEET] 212 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33.2 Atmel ATxmega64D3 33.2.1 Current Consumption 33.2.1.1 Active Mode Supply Current Figure 33-72.Active Supply Current vs. Frequency f =0 - 1MHz external clock, T = 25°C SYS 800 3.6 V 700 3.3 V 600 3.0 V 500 2.7 V A] µ V [ 400 2.2 V c c I 300 1.8 V 1.6 V 200 100 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz] Figure 33-73.Active Supply Current vs. Frequency f =1 - 32MHz external clock, T = 25°C SYS 12 3.6 V 10 3.3 V 8 3.0 V A ] 2.7 V m 6 c [ c I 4 2.2 V 2 1.8 V 1.6 V 0 0 4 8 12 16 20 24 28 32 Frequency [MHz] XMEGA D3 [DATASHEET] 213 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-74.Active Mode Supply Current vs. V CC f =32.768kHz internal oscillator SYS 250 -40 °C 225 25 °C 200 85 °C 175 105 °C A] µ 150 [ c Ic 125 100 75 50 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V [V] CC Figure 33-75.Active Mode Supply Current vs. V CC f =1MHz external clock SYS 900 -40°C 800 25 °C 85 °C 700 105 °C 600 A] µ c [ 500 c I 400 300 200 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V [V] CC XMEGA D3 [DATASHEET] 214 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-76.Active Mode Supply Current vs. V CC f =2MHz internal oscillator SYS 1300 -40 °C 1200 25 °C 85 °C 1100 105 °C 1000 A] 900 µ [ c 800 c I 700 600 500 400 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V [V] CC Figure 33-77.Active Mode Supply Current vs. V CC f =32MHz internal oscillator prescaled to 8MHz SYS 5.0 -40 °C 4.5 25 °C 85 °C 4.0 105 °C 3.5 A] m [ 3.0 c c I 2.5 2.0 1.5 1.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V [V] CC XMEGA D3 [DATASHEET] 215 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-78.Active Mode Supply Current vs. V CC f =32MHz internal oscillator SYS 12.0 11.0 -40 °C 25 °C 10.0 85 °C ] A 105 °C m 9.0 [ c c I 8.0 7.0 6.0 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 V [V] CC 33.2.1.2 Idle Mode Supply Current Figure 33-79.Idle Mode Supply Current vs. Frequency f =0 - 1MHz external clock, T = 25°C SYS 140 120 3.6 V 3.3 V 100 3.0 V A] 80 2.7 V µ [ c c 60 2.2 V I 1.8 V 40 1.6 V 20 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency[MHz] XMEGA D3 [DATASHEET] 216 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-80.Idle Mode Supply Current vs. Frequency f =1 - 32MHz external clock, T = 25°C SYS 4.5 4.0 3.6 V 3.5 3.3 V 3.0 3.0 V A] m 2.5 2.7 V [ c c I 2.0 1.5 2.2 V 1.0 1.8 V 0.5 1.6 V 0 0 4 8 12 16 20 24 28 32 Frequency [MHz] Figure 33-81.Idle Mode Supply Current vs. V CC f =32.768kHz internal oscillator SYS 46 105°C 44 42 40 A] 38 µ c [ 36 85 °C c I 34 -40 °C 32 25 °C 30 28 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V [V] CC XMEGA D3 [DATASHEET] 217 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-82.Idle Mode Supply Current vs. V CC f =1MHz external clock SYS 135 105 °C 125 85 °C 25° C 115 -40 °C 105 95 A] [µ 85 c c I 75 65 55 45 35 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V [V] CC Figure 33-83.Idle Mode Supply Current vs. V CC f =2MHz internal oscillator SYS 365 -40 °C 340 25 °C 85 °C 315 105 °C 290 A] 265 µ [ c 240 c I 215 190 165 140 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V [V] CC XMEGA D3 [DATASHEET] 218 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-84.Idle Mode Supply Current vs. V CC f =32MHz internal oscillator prescaled to 8MHz SYS 1600 -40 °C 25 °C 1500 85 °C 1400 105 °C 1300 1200 A] 1100 µ c [ 1000 c I 900 800 700 600 500 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V [V] CC Figure 33-85.Idle Mode Current vs. V CC f =32MHz internal oscillator SYS 4.5 -40 °C 4.3 25 °C 85 °C 4.1 105 °C 3.9 A] 3.7 m [ c 3.5 c I 3.3 3.1 2.9 2.7 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 VCC [V] XMEGA D3 [DATASHEET] 219 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33.2.1.3Power-down Mode Supply Current Figure 33-86.Power-down Mode Supply Current vs. V CC All functions disabled 5.0 105 °C 4.5 4.0 3.5 3.0 A] µ [ 2.5 c c I 2.0 1.5 85 °C 1.0 0.5 25 °C 0.0 -40 °C 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V [V] CC Figure 33-87.Power-down Mode Supply Current vs. V CC Watchdog and sampled BOD enabled 6.0 5.5 105 °C 5.0 4.5 4.0 A] µ 3.5 [ c Ic 3.0 85 °C 2.5 2.0 1.5 25 °C -40 °C 1.0 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V [V] CC XMEGA D3 [DATASHEET] 220 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-88.Power-down Mode Supply Current vs. Temperature All functions disabled 4.8 3.6 V 4.3 3.3 V 3.0 V 3.8 2.7 V 3.3 2.2 V 1.8 V 2.8 1.6 V A] µ c [ 2.3 c I 1.8 1.3 0.8 0.3 -0.2 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] Figure 33-89.Power-down Mode Supply Current vs. Temperature Watchdog and sampled BOD enabled and running from internal ULP oscillator 6.0 5.5 3.6 V 3.3 V 5.0 3.0 V 2.7 V 4.5 2.2 V 4.0 1.8 V A] c [µ 3.5 c I 3.0 2.5 2.0 1.5 1.0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] XMEGA D3 [DATASHEET] 221 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33.2.2 I/O Pin Characteristics 33.2.2.1 Pull-up Figure 33-90.I/O Pin Pull-up Resistor Current vs. Input Voltage V = 1.8V CC 70 60 50 40 A] µ I [ 30 20 -40 °C 25 °C 10 85 °C 105 °C 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VPIN [V] Figure 33-91.I/O Pin Pull-up Resistor Current vs. Input Voltage V = 3.0V CC 120 108 96 84 72 A] µ 60 I [ 48 36 -40 °C 24 25 °C 85 °C 12 105 °C 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 VPIN [V] XMEGA D3 [DATASHEET] 222 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-92.I/O Pin Pull-up Resistor Current vs. Input Voltage V = 3.3V CC 140 120 100 80 A] µ I [ 60 40 -40 °C 25 °C 20 85 °C 105 °C 0 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 VPIN [V] 33.2.2.2 Output Voltage vs. Sink/Source Current Figure 33-93.I/O Pin Output Voltage vs. Source Current V = 1.8V CC 2.0 1.8 1.6 1.4 1.2 ] V 25 °C [ -40 °C 105 °C N 1.0 PI V 0.8 0.6 85 °C 0.4 0.2 0.0 -5.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 I [mA] PIN XMEGA D3 [DATASHEET] 223 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-94.I/O Pin Output Voltage vs. Source Current V = 3.0V CC 3.5 3.0 2.5 V] 2.0 [ N PI 1.5 V -40 °C 1.0 85 °C 25 °C 0.5 105 °C 0.0 -16 -14 -12 -10 -8 -6 -4 -2 0 I [mA] PIN Figure 33-95.I/O Pin Output Voltage vs. Source Current V = 3.3V CC 3.5 3.0 2.5 2.0 V] [ -40 °C N PI V 1.5 25 °C 1.0 85 °C 0.5 105 °C 0.0 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 I [mA] PIN XMEGA D3 [DATASHEET] 224 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-96.I/O Pin Output Voltage vs. Sink Current V = 1.8V CC 1.8 105 °C 85 °C 1.6 1.4 1.2 V] 1.0 [N VPI 0.8 25 °C 0.6 -40 °C 0.4 0.2 0.0 0 1 2 3 4 5 6 7 8 9 IPIN [mA] Figure 33-97.I/O Pin Output Voltage vs. Sink Current V = 3.0V CC 1.1 1.0 105 °C 85 °C 0.9 0.8 25 °C -40 °C 0.7 V] [N 0.6 PI 0.5 V 0.4 0.3 0.2 0.1 0.0 0 2 4 6 8 10 12 14 16 IPIN [mA] XMEGA D3 [DATASHEET] 225 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-98.I/O Pin Output Voltage vs. Sink Current V = 3.3V CC 1.4 105 °C 1.2 85 °C 1.0 25 °C -40 °C V] 0.8 [N PI V 0.6 0.4 0.2 0.0 0 2 4 6 8 10 12 14 16 18 20 IPIN [mA] 33.2.2.3Thresholds and Hysteresis Figure 33-99.I/O Pin Input Threshold Voltage vs. V CC V I/O pin read as “1” IH 1.8 -40 °C 1.7 25 °C 1.6 85 °C 105 °C 1.5 V] 1.4 [ d ol 1.3 h s e hr 1.2 Vt 1.1 1.0 0.9 0.8 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V [V] CC XMEGA D3 [DATASHEET] 226 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-100.I/O Pin Input Threshold Voltage vs. V CC V I/O pin read as “0” IL 1.6 105 °C 1.5 85 °C 1.4 25 °C 1.3 -40 °C 1.2 ] V [ 1.1 d ol sh 1.0 e hr Vt 0.9 0.8 0.7 0.6 0.5 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V [V] CC Figure 33-101.I/O Pin Input Hysteresis vs. V CC 0.39 0.36 0.33 V] 0.30 [ d ol 0.27 h s e Vthr 0.24 - 40 °C 25 °C 0.21 85 °C 0.18 105° C 0.15 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V [V] CC XMEGA D3 [DATASHEET] 227 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33.2.3 ADC Characteristics Figure 33-102.INL Error vs. External V REF T = 25C, V = 3.6V, external reference CC 1.6 1.4 1.2 Single-ended unsigned mode B] 1.0 S L L[ 0.8 N I 0.6 Differential mode 0.4 Single -ended signed mode 0.2 0.0 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 VREF [V] Figure 33-103.INL Error vs. Sample Rate T = 25C, V = 3.6V, V = 3.0V external CC REF 0.70 0.65 Single-ended unsigned mode 0.60 0.55 B] S 0.50 Differential mode L L[ N 0.45 I 0.40 0.35 Single-ended signed mode 0.30 0.25 50 100 150 200 250 300 ADC sample rate [ksps] XMEGA D3 [DATASHEET] 228 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-104.INL Error vs. Input Code 1.25 1.00 0.75 0.50 B] S 0.25 L L[ 0.00 N I -0.25 -0.50 -0.75 -1.00 -1.25 0 512 1024 1536 2048 2560 3072 3584 4096 ADC input code Figure 33-105.DNL Error vs. External V REF T = 25C, V = 3.6V, external reference CC 0.70 0.65 0.60 Single-ended unsigned mode 0.55 B] S 0.50 L L [ 0.45 N D 0.40 Differential mode 0.35 0.30 Single-ended signed mode 0.25 0.20 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 VREF [V] XMEGA D3 [DATASHEET] 229 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-106.DNL Error vs. Sample Rate T = 25C, V = 3.6V, V = 3.0V external CC REF 0.60 0.55 Single-ended unsigned mode 0.50 B] 0.45 S L L [ 0.40 N D Differential mode 0.35 0.30 Single-ended signed mode 0.25 0.20 50 100 150 200 250 300 ADC sample rate [ksps] Figure 33-107.DNL Error vs. Input Code 1 0.8 B] 0.6 S L 0.4 [ L N 0.2 D 0 -0.2 -0.4 -0.6 0 512 1024 1536 2048 2560 3072 3584 4096 ADC input code XMEGA D3 [DATASHEET] 230 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-108.Gain Error vs. V REF T = 25C, V = 3.6V, ADC sample rate = 300ksps CC -5 -6 ] -7 V Differential mode m -8 [ r o -9 r er Single-ended signed mode n -10 ai G -11 -12 -13 Single-ended unsigned mode -14 -15 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 VREF [V] Figure 33-109.Gain Error vs. V CC T = 25C, V = external 1.0V, ADC sample rate = 300ksps REF -2 -3 ] V -4 m [ Differential mode r -5 o r Single-ended signed r e mode n -6 ai G Single-ended unsigned mode -7 -8 -9 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] XMEGA D3 [DATASHEET] 231 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-110.Offset Error vs. V REF T = 25C, V = 3.6V, ADC sample rate = 300ksps CC 9.4 9.2 9.0 V] 8.8 m r [ 8.6 Differential mode rro 8.4 e et 8.2 Offs 8.0 7.8 7.6 7.4 7.2 7.0 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 VREF [V] Figure 33-111.Gain Error vs. Temperature V = 3.0V, V = external 2.0V CC REF 0 -2 Single-ended signed mode V] -4 m [ or -6 r r e Differential mode n -8 ai G -10 Single-ended unsigned mode -12 -14 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] XMEGA D3 [DATASHEET] 232 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-112.Offset Error vs. V CC T = 25C, V = external 1.0V, ADC sample rate = 300ksps REF 8.00 7.00 ] V m 6.00 [ r 5.00 o r Differential mode r e 4.00 et s Off 3.00 2.00 1.00 0.00 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] 33.2.4 Analog Comparator Characteristics Figure 33-113.Analog Comparator Hysteresis vs. V CC Small hysteresis 19 105°C 18 85°C 17 16 V] 25°C m 15 [T S VHY 14 -40°C 13 12 11 10 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC[V] XMEGA D3 [DATASHEET] 233 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-114.Analog Comparator Hysteresis vs. V CC Large hysteresis 38 105 °C 36 85°C 34 V] 32 m 25°C [T 30 S Y VH 28 -40°C 26 24 22 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC[V] Figure 33-115.Analog Comparator Current Source vs. Calibration Value V = 3.0V CC 7.0 6.5 A] µ [E 6.0 C R U O 5.5 S T N E R R 5.0 U C I 4.5 -40 °C 25 °C 4.0 85 °C 105 °C 3.5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CURRCALIBA[3..0] XMEGA D3 [DATASHEET] 234 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-116.Voltage Scaler INL vs. SCALEFAC T = 25C, V = 3.0V CC 0.425 0.4 0.375 25°C B] 0.35 S L L [ 0.325 N I 0.3 0.275 0.25 0 5 10 15 20 25 30 35 40 45 50 55 60 65 SCALEFAC 33.2.5 Internal 1.0V Reference Characteristics Figure 33-117.ADC Internal 1.0V Reference vs. Temperature 1.010 1.005 1.8 V 2.7 V ] V 1.000 3.0 V e [ g a olt 0.995 V p 0.990 a g d n a 0.985 B 0.980 0.975 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] XMEGA D3 [DATASHEET] 235 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33.2.6 BOD Characteristics Figure 33-118.BOD Thresholds vs. Temperature BOD level = 1.6V 1.623 1.622 1.621 1.620 V] [T 1.619 O B V 1.618 1.617 1.616 1.615 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] Figure 33-119.BOD Thresholds vs. Temperature BOD level = 3.0V 3.066 3.063 3.060 3.057 V] 3.054 [ T O 3.051 B V 3.048 3.045 3.042 3.039 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] XMEGA D3 [DATASHEET] 236 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33.2.7 External Reset Characteristics Figure 33-120.Minimum Reset Pin Pulse Width vs. V CC 144 136 128 120 ] s n 112 [T S R t 104 105 °C 85 °C 96 25 °C 88 -40 °C 80 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] Figure 33-121.Reset Pin Pull-up Resistor Current vs. Reset Pin Voltage V = 1.8V CC 80 70 60 50 A] µ [ET 40 S E IR 30 20 -40 °C 25 °C 10 85 °C 105° C 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VRESET [V] XMEGA D3 [DATASHEET] 237 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-122.Reset Pin Pull-up Resistor Current vs. Reset Pin Voltage V = 3.0V CC 120 108 96 84 A] 72 µ [ET 60 S E R 48 I 36 -40 °C 24 25 °C 12 85 °C 105 °C 0 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 VRESET [V] Figure 33-123.Reset Pin Pull-up Resistor Current vs. Reset Pin Voltage V = 3.3V CC 140 120 100 A] µ 80 [T E S E 60 R I 40 -40 °C 25 °C 20 85 °C 105 °C 0 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 VRESET [V] XMEGA D3 [DATASHEET] 238 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-124.Reset Pin Input Threshold Voltage vs. V CC V - Reset pin read as “1” IH 1.8 105 °C 1.6 85 °C 25 °C 1.4 - 40 °C V] 1.2 D [ L 1.0 O H S E 0.8 R H T V 0.6 0.4 0.2 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] 33.2.8 Oscillator Characteristics 33.2.8.1 Ultra Low-Power Internal Oscillator Figure 33-125. Ultra Low-Power Internal Oscillator Frequency vs. Temperature 34.0 33.5 z] 33.0 H k y [ 32.5 c n e 32.0 u q e r 31.5 F 31.0 3.3 V 3.0 V 30.5 2.7 V 1.8 V 30.0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] XMEGA D3 [DATASHEET] 239 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33.2.8.2 32.768kHz Internal Oscillator Figure 33-126. 32.768kHz Internal Oscillator Frequency vs. Temperature 32.9 1.6 V 32.9 1.8 V 2.2 V 32.8 2.7 V z] 3.0 V H k 32.8 3.6 V [ y c 32.7 n e u q 32.7 e r F 32.6 32.6 32.5 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] Figure 33-127. 32.768kHz Internal Oscillator Frequency vs. Calibration Value V = 3.0V, T = 25°C CC 50 3.0 V 47 44 41 z] H k 38 [ y c 35 n e qu 32 e r F 29 26 23 20 -4 16 36 56 76 96 116 136 156 176 196 216 236 256 RC32KCAL[7..0] XMEGA D3 [DATASHEET] 240 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33.2.8.3 2MHz Internal Oscillator Figure 33-128. 2MHz Internal Oscillator Frequency vs. Temperature DFLL disabled 2.14 2.12 2.10 Hz] 2.08 M y [ 2.06 c n e 2.04 u q 3.6 V e 2.02 r F 3.0 V 2.00 2.7 V 2.2 V 1.98 1.8 V 1.6 V 1.96 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] Figure 33-129. 2MHz Internal Oscillator Frequency vs. Temperature DFLL enabled, from the 32.768kHz internal oscillator 2.009 2.006 2.7 V 3.6 V 2.003 3.0 V Hz] 1.8 V 1.6 V 2.000 M [ 2.2 V y c 1.997 n e u q 1.994 e r F 1.991 1.988 1.985 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] XMEGA D3 [DATASHEET] 241 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-130. 2MHz Internal Oscillator Frequency vs. CALA Calibration Value V = 3V CC 2.4 -40 °C 2.3 25 °C 85 °C z] 2.2 105 °°C H M [ 2.1 y c n e 2.0 u q e r F 1.9 1.8 1.7 0 16 32 48 64 80 96 112 128 CALA 33.2.8.4 32MHz Internal Oscillator Figure 33-131. 32MHz Internal Oscillator Frequency vs. Temperature DFLL disabled 36.0 35.5 35.0 z] 34.5 H M 34.0 [ y c 33.5 n e u 33.0 q 3.6 V e Fr 32.5 3.0 V 2.7 V 32.0 2.2 V 31.5 1.8 V 1.6 V 31.0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperatuire [°C] XMEGA D3 [DATASHEET] 242 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-132. 32MHz Internal Oscillator Frequency vs. Temperature DFLL enabled, from the 32.768kHz internal oscillator 32.10 2.2 V 32.07 2.7 V 1.6 V 3.0 V 32.04 3.6 V Hz] 32.01 M [ 31.98 y c n e 31.95 u 1.8 V q e 31.92 r F 31.89 31.86 31.83 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] Figure 33-133. 32MHz Internal Oscillator CALA Calibration Step Size T = -40°C, V = 3.0V CC 0.31 % 0.29 % %] 0.27 % e [ 0.26 % z si 0.24 % p e St 0.22 % y c 0.20 % n e u 0.18 % q e Fr 0.17 % 0.15 % -40 °C 0.13 % 0 16 32 48 64 80 96 112 128 CALA XMEGA D3 [DATASHEET] 243 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-134. 32MHz Internal Oscillator CALA Calibration Step Size T = 25°C, V = 3.0V CC 0.26 % 0.24 % %] e [ 0.22 % z si p 0.20 % e 25 °C St y 0.18 % c n e u q 0.16 % e r F 0.14 % 0.12 % 0 16 32 48 64 80 96 112 128 CALA Figure 33-135. 32MHz Internal Oscillator CALA Calibration Step Size T = 85°C, V = 3.0V CC 0.24 % 0.23 % %] 0.21 % e [ z 0.20 % si p e 0.19 % St y 0.18 % c n ue 0.17 % q e 85 °C r 0.15 % F 0.14 % 0.13 % 0 16 32 48 64 80 96 112 128 CALA XMEGA D3 [DATASHEET] 244 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-136. 32MHz Internal Oscillator CALA Calibration Step Size T = 105°C, V = 3.0V CC 0.22 % 0.21 % %] 0.20 % e [ z si 0.19 % p e St 0.18 % y c n 0.17 % e u q e 0.16 % r F 105 °C 0.15 % 0.14 % 0 16 32 48 64 80 96 112 128 CALA Figure 33-137. 32MHz Internal Oscillator Frequency vs. CALB Calibration Value V = 3.0V CC 75 70 -40 °C 25 °C 65 85 °C 60 105 °C z] H 55 M [ 50 y c n 45 e u q 40 e r F 35 30 25 20 0 7 14 21 28 35 42 49 56 63 CALB XMEGA D3 [DATASHEET] 245 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33.2.8.5 32MHz Internal Oscillator Calibrated to 48MHz Figure 33-138. 48MHz Internal Oscillator Frequency vs. Temperature DFLL disabled 55 54 53 Hz] 52 M [ 51 y c n e 50 u q e 49 3.6 V r F 3.0 V 48 2.7 V 2.2 V 47 1.8 V 1.6 V 46 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] Figure 33-139. 48MHz Internal Oscillator Frequency vs. Temperature DFLL enabled, from the 32.768kHz internal oscillator 48.20 48.15 1.6 V 1.8 V 2.2 V 48.10 3.6 V z] 2.7 V H 48.05 3.0 V M [ 48.00 y c n e 47.95 u q e 47.90 r F 47.85 47.80 47.75 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] XMEGA D3 [DATASHEET] 246 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33.2.9 Two-Wire Interface Characteristics Figure 33-140.SDA Hold Time vs. Temperature 500 450 3 400 350 s] 2 e [n 300 m 250 d ti ol 200 H 150 100 50 1 0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 33-141.SDA Hold Time vs. Supply Voltage 500 450 3 400 350 s] 2 n e [ 300 m 250 d ti ol 200 H 150 100 50 1 0 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 V [V] CC XMEGA D3 [DATASHEET] 247 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33.2.10 PDI Characteristics Figure 33-142.Maximum PDI Frequency vs. V CC 24 -40 °C 22 20 25 °C 18 z] 85 °C H 105 °C M 16 [X A 14 M f 12 10 8 6 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] XMEGA D3 [DATASHEET] 248 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33.3 Atmel ATxmega128D3 33.3.1 Current Consumption 33.3.1.1 Active Mode Supply Current Figure 33-143.Active Supply Current vs. Frequency f =0 - 1MHz external clock, T = 25°C SYS 800 700 3.6V 600 3.3V 3.0V 500 A] 2.7V [µ 400 c c I 2.2V 300 1.8V 200 100 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz] Figure 33-144.Active Supply Current vs. Frequency f =1 - 32MHz external clock, T = 25°C SYS 12 3.6V 10 3.3V 3.0V 8 2.7V A] m 6 [ c c I 4 2.2V 1.8V 2 0 0 4 8 12 16 20 24 28 32 Frequency [MHz] XMEGA D3 [DATASHEET] 249 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-145.Active Mode Supply Current vs. V CC f =32.768kHz internal oscillator SYS 300 250 -40 °C 25 °C 200 85 °C A] 105 °C c [u 150 c I 100 50 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-146.Active Mode Supply Current vs. V CC f =1MHz external clock SYS 800 700 -40 °C 25 °C 85 °C 600 105 °C A] 500 µ cl [ Ic 400 300 200 100 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] XMEGA D3 [DATASHEET] 250 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-147.Active Mode Supply Current vs. V CC f =2MHz internal oscillator SYS 1600 1400 -40 °C 25 °C 1200 85 °C 105 °C 1000 A] c [µ 800 c I 600 400 200 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-148.Active Mode Supply Current vs. V CC f =32MHz internal oscillator prescaled to 8MHz SYS 6.0 -40 °C 5.0 25 °C 85 °C 105 °C 4.0 A] m c [ 3.0 c I 2.0 1.0 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] XMEGA D3 [DATASHEET] 251 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-149.Active Mode Supply Current vs. V CC f =32MHz internal oscillator SYS 13.0 -40 °C 12.0 25 °C 11.0 85 °C 10.0 105 °C A] 9.0 m c [ 8.0 c I 7.0 6.0 5.0 4.0 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 VCC [V] 33.3.1.2 Idle Mode Supply Current Figure 33-150.Idle Mode Supply Current vs. Frequency f =0 - 1MHz external clock, T = 25°C SYS 140 3.6V 120 3.3V 100 3.0V A] 80 2.7V µ [ c c 60 2.2V I 1.8V 40 20 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz] XMEGA D3 [DATASHEET] 252 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-151.Idle Mode Supply Current vs. Frequency f =1 - 32MHz external clock, T = 25°C SYS 4.5 4.0 3.6V 3.5 3.3V 3.0 3.0V A] 2.5 2.7V m [ c 2.0 c I 1.5 2.2V 1.0 1.8V 0.5 0 0 4 8 12 16 20 24 28 32 Frequency [MHz] Figure 33-152.Idle Mode Supply Current vs. V CC f =32.768kHz internal oscillator SYS 36 105 °C 34 32 85 °C A] -40 °C c [µ 30 25 °C c I 28 26 24 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] XMEGA D3 [DATASHEET] 253 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-153.Idle Mode Supply Current vs. V CC f =1MHz external clock SYS 140 105 °C 85 °C 25 °C 120 -40 °C 100 A] 80 µ c [ c I 60 40 20 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-154.Idle Mode Supply Current vs. V CC f =2MHz internal oscillator SYS 400 105 °C 85 °C 350 25 °C -40 °C 300 A] c [µ 250 c I 200 150 100 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] XMEGA D3 [DATASHEET] 254 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-155.Idle Mode Supply Current vs. V CC f =32MHz internal oscillator prescaled to 8MHz SYS 1800 -40 °C 25 °C 1600 85 °C 1400 105 °C A] 1200 µ c [ c 1000 I 800 600 400 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-156.Idle Mode Current vs. V CC f =32MHz internal oscillator SYS 5000 -40 °C 4500 25 °C 85 °C 105 °C 4000 A] µ c [ c I 3500 3000 2500 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 VCC [V] XMEGA D3 [DATASHEET] 255 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33.3.1.3 Power-down Mode Supply Current Figure 33-157.Power-down Mode Supply Current vs. V CC All functions disabled 6 105 °C 5 4 A] 3 µ c [ c I 2 85 °C 1 25 °C -40 °C 0 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-158.Power-down Mode Supply Current vs. V CC Watchdog and sampled BOD enabled 7 105 °C 6 5 A] 4 µ cc [ 85 °C I 3 2 25 °C -40 °C 1 0 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] XMEGA D3 [DATASHEET] 256 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-159.Power-down Mode Supply Current vs. Temperature Watchdog and sampled BOD enabled and running from internal ULP oscillator 7 3.6 V 6 3.0 V 2.7 V 5 2.2 V 1.8 V A] c [µ 4 c I 3 2 1 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] 33.3.2 I/O Pin Characteristics 33.3.2.1 Pull-up Figure 33-160.I/O Pin Pull-up Resistor Current vs. Input Voltage V = 1.8V CC 70 60 50 40 A] µ C [ IC 30 20 -40 °C 25 °C 10 85 °C 105 °C 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VPIN [V] XMEGA D3 [DATASHEET] 257 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-161.I/O Pin Pull-up Resistor Current vs. Input Voltage V = 3.0V CC 120 100 80 A] C [µ 60 C I 40 -40 °C 25 °C 20 85 °C 105 °C 0 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 VPIN [V] Figure 33-162.I/O Pin Pull-up Resistor Current vs. Input Voltage V = 3.3V CC 140 120 100 A] 80 µ C [ IC 60 40 -40 °C 25 °C 20 85 °C 105 °C 0 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 VPIN [V] XMEGA D3 [DATASHEET] 258 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33.3.2.2Output Voltage vs. Sink/Source Current Figure 33-163.I/O Pin Output Voltage vs. Source Current V = 1.8V CC 2.0 1.8 1.6 1.4 1.2 V] -40 °C N [ 1.0 PI V 0.8 25 °C 0.6 85 °C 0.4 105 °C 0.2 0.0 -5.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 IPIN [mA] Figure 33-164.I/O Pin Output Voltage vs. Source Current V = 3.0V CC 3.5 3.0 2.5 V] 2.0 N [ -40 °C PI V 1.5 25 °C 1.0 85 °C 0.5 105 °C 0.0 -16 -14 -12 -10 -8 -6 -4 -2 0 IPIN [mA] XMEGA D3 [DATASHEET] 259 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-165.I/O Pin Output Voltage vs. Source Current V = 3.3V CC 3.5 3.0 2.5 V] 2.0 PIN [ -40 °C V 1.5 25 °C 1.0 85 °C 0.5 105 °C 0.0 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 IPIN [mA] Figure 33-166.I/O Pin Output Voltage vs. Sink Current V = 1.8V CC 2.5 105 °C 2.0 85 °C 1.5 V] N [ PI V 1.0 25 °C -40 °C 0.5 0.0 0 1 2 3 4 5 6 7 8 9 IPIN [mA] XMEGA D3 [DATASHEET] 260 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-167.I/O Pin Output Voltage vs. Sink Current V = 3.0V CC 1.2 1.0 105 °C 85 °C 0.8 25 °C -40 °C V] N [ 0.6 PI V 0.4 0.2 0.0 0 2 4 6 8 10 12 14 16 IPIN [mA] Figure 33-168.I/O Pin Output Voltage vs. Sink Current V = 3.3V CC 1.4 105 °C 1.2 85 °C 1.0 25 °C -40 °C V] 0.8 N [ PI V 0.6 0.4 0.2 0.0 0 2 4 6 8 10 12 14 16 18 20 IPIN [mA] XMEGA D3 [DATASHEET] 261 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33.3.2.3Thresholds and Hysteresis Figure 33-169.I/O Pin Input Threshold Voltage vs. V CC V I/O pin read as “1” IH 2.0 -40 °C 1.8 25 °C 85 °C 1.6 105 °C V] d [ hol 1.4 s e hr Vt 1.2 1.0 0.8 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-170.I/O Pin Input Threshold Voltage vs. V CC V I/O pin read as “0” IL 1.7 -40 °C 25 °C 1.5 85 °C 105 °C 1.3 V] d [ hol 1.1 s e hr Vt 0.9 0.7 0.5 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] XMEGA D3 [DATASHEET] 262 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-171.I/O Pin Input Hysteresis vs. V CC 0.40 0.35 V] 0.30 d [ ol h s e Vthr 0.25 -40 °C 25 °C 0.20 85 °C 105 °C 0.15 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] 33.3.3 ADC Characteristics Figure 33-172.INL Error vs. External V REF T = 25C, V = 3.6V, external reference CC 1.6 1.4 1.2 Single-ended unsigned mode B] 1.0 S L L[ 0.8 N I 0.6 Differential mode 0.4 Single -ended signed mode 0.2 0.0 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 VREF [V] XMEGA D3 [DATASHEET] 263 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-173.INL Error vs. Sample Rate T = 25C, V = 3.6V, V = 3.0V external CC REF 0.70 0.65 Single-ended unsigned mode 0.60 0.55 B] S 0.50 Differential mode L L[ N 0.45 I 0.40 0.35 Single-ended signed mode 0.30 0.25 50 100 150 200 250 300 ADC sample rate [ksps] Figure 33-174.INL Error vs. Input Code 1.25 1.00 0.75 0.50 B] S 0.25 L L[ 0.00 N I -0.25 -0.50 -0.75 -1.00 -1.25 0 512 1024 1536 2048 2560 3072 3584 4096 ADC input code XMEGA D3 [DATASHEET] 264 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-175.DNL Error vs. External V REF T = 25C, V = 3.6V, external reference CC 0.70 0.65 0.60 Single-ended unsigned mode 0.55 B] S 0.50 L L [ 0.45 N D 0.40 Differential mode 0.35 0.30 Single-ended signed mode 0.25 0.20 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 VREF [V] Figure 33-176.DNL Error vs. Sample Rate T = 25C, V = 3.6V, V = 3.0V external CC REF 0.60 0.55 Single-ended unsigned mode 0.50 B] 0.45 S L L [ 0.40 N D Differential mode 0.35 0.30 Single-ended signed mode 0.25 0.20 50 100 150 200 250 300 ADC sample rate [ksps] XMEGA D3 [DATASHEET] 265 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-177.DNL Error vs. Input Code 1 0.8 ] 0.6 B S L 0.4 [ L N 0.2 D 0 -0.2 -0.4 -0.6 0 512 1024 1536 2048 2560 3072 3584 4096 ADC input code Figure 33-178.Gain Error vs. V REF T = 25C, V = 3.6V, ADC sample rate = 300ksps CC -5 -6 ] -7 V Differential mode m -8 [ r o -9 r er Single-ended signed mode n -10 ai G -11 -12 -13 Single-ended unsigned mode -14 -15 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 VREF [V] XMEGA D3 [DATASHEET] 266 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-179.Gain Error vs. V CC T = 25C, V = external 1.0V, ADC sample rate = 300ksps REF -2 -3 ] V -4 m [ Differential mode r -5 o r Single-ended signed r e mode n -6 ai G Single-ended unsigned mode -7 -8 -9 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-180.Offset Error vs. V REF T = 25C, V = 3.6V, ADC sample rate = 300ksps CC 9.4 9.2 9.0 V] 8.8 m r [ 8.6 Differential mode rro 8.4 e et 8.2 Offs 8.0 7.8 7.6 7.4 7.2 7.0 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 VREF [V] XMEGA D3 [DATASHEET] 267 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-181.Gain Error vs. Temperature V = 3.0V, V = external 2.0V CC REF 0 -2 Single-ended signed mode V] -4 m [ or -6 r r e Differential mode n -8 ai G -10 Single-ended unsigned mode -12 -14 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] Figure 33-182.Offset Error vs. V CC T = 25C, V = external 1.0V, ADC sample rate = 300ksps REF 8.00 7.00 ] V m 6.00 [ r 5.00 o r Differential mode r e 4.00 et s Off 3.00 2.00 1.00 0.00 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] XMEGA D3 [DATASHEET] 268 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33.3.4 Analog Comparator Characteristics Figure 33-183.Analog Comparator Hysteresis vs. V CC Small hysteresis 19 105°C 18 85°C 17 16 V] 25°C m 15 [T S VHY 14 -40°C 13 12 11 10 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC[V] Figure 33-184.Analog Comparator Hysteresis vs. V CC Large hysteresis 38 105 °C 36 85°C 34 V] 32 m 25°C [T 30 S Y VH 28 -40°C 26 24 22 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC[V] XMEGA D3 [DATASHEET] 269 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-185.Analog Comparator Current Source vs. Calibration Value V = 3.0V CC 7.0 6.5 A] µ [E 6.0 C R U O 5.5 S T N E R R 5.0 U C I 4.5 -40 °C 25 °C 4.0 85 °C 105 °C 3.5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CURRCALIBA[3..0] Figure 33-186.Voltage Scaler INL vs. SCALEFAC T = 25C, V = 3.0V CC 0.425 0.4 0.375 25°C B] 0.35 S L L [ 0.325 N I 0.3 0.275 0.25 0 5 10 15 20 25 30 35 40 45 50 55 60 65 SCALEFAC XMEGA D3 [DATASHEET] 270 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33.3.5 Internal 1.0V Reference Characteristics Figure 33-187.ADC Internal 1.0V Reference vs. Temperature 1.007 1.006 1.005 V] e [ 1.004 g a 1.003 olt V 1.002 p 1.6 V a 1.001 g d n 1.000 2.7 V a B 3.6 V 0.999 0.998 0.997 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 T [°C] 33.3.6 BOD Characteristics Figure 33-188.BOD Thresholds vs. Temperature BOD level = 1.6V 1.598 1.596 1.594 1.592 V] Rising Vcc [T1.590 O B V 1.588 1.586 Falling Vcc 1.584 1.582 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] XMEGA D3 [DATASHEET] 271 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-189.BOD Thresholds vs. Temperature BOD level = 3.0V 3.05 3.04 Rising Vcc 3.03 V] 3.02 [T O VB 3.01 3.00 Falling Vcc 2.99 2.98 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 T emperature[°C] 33.3.7 External Reset Characteristics Figure 33-190.Minimum Reset Pin Pulse Width vs. V CC 160 140 120 105 °C 85 °C 100 s] 25 °C [nT 80 -40 °C S R t 60 40 20 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] XMEGA D3 [DATASHEET] 272 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-191.Reset Pin Pull-up Resistor Current vs. Reset Pin Voltage V = 1.8V CC 80 60 A] µ [ET40 S E R I -40 °C 25 °C 20 85 °C 105 °C 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VRESET [V] Figure 33-192.Reset Pin Pull-up Resistor Current vs. Reset Pin Voltage V = 3.0V CC 140 120 100 µA] 80 [T E S E 60 R I 40 -40 °C 20 25 °C 85 °C 0 105 °C 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 VRESET [V] XMEGA D3 [DATASHEET] 273 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-193.Reset Pin Pull-up Resistor Current vs. Reset Pin Voltage V = 3.3V CC 140 120 100 µA] 80 [T E S E 60 R I 40 -40 °C 20 25 °C 85 °C 0 105 °C 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 VRESET [V] Figure 33-194.Reset Pin Input Threshold Voltage vs. V CC V - Reset pin read as “1” IH 1.8 105 °C 1.6 85 °C 25 °C 1.4 - 40 °C V] 1.2 D [ L 1.0 O H S E 0.8 R H T V 0.6 0.4 0.2 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] XMEGA D3 [DATASHEET] 274 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33.3.8 Oscillator Characteristics 33.3.8.1 Ultra Low-Power Internal Oscillator Figure 33-195.Ultra Low-Power Internal Oscillator Frequency vs. Temperature 36.0 35.5 35.0 34.5 z] H 34.0 k y [ 33.5 c n ue 33.0 Freq 32.5 33..63 VV 32.0 3.0 V 2.7 V 31.5 1.8 V 31.0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] 33.3.8.2 32.768kHz Internal Oscillator Figure 33-196.32.768kHz Internal Oscillator Frequency vs. Temperature 32.89 1.8 V 32.83 2.2 V 2.7 V 3.0 V 32.77 3.3 V z] H 32.71 3.6 V k y [ 32.65 c n e 32.59 u q e 32.53 Fr 32.47 32.41 32.35 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] XMEGA D3 [DATASHEET] 275 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-197.32.768kHz Internal Oscillator Frequency vs. Calibration Value V = 3.0V, T = 25°C CC 50 3.0V 47 44 ] 41 z H k 38 [ y c 35 n e u 32 q e r 29 F 26 23 20 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 RC32KCAL[7..0] 33.3.8.3 2MHz Internal Oscillator Figure 33-198.2MHz Internal Oscillator Frequency vs. Temperature DFLL disabled 2.16 2.14 2.12 2.10 z] H 2.08 M y [ 2.06 c n ue 2.04 q Fre 2.02 3.3 V 2.00 3.0 V 1.98 2.7 V 2.2 V 1.96 1.8 V 1.94 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] XMEGA D3 [DATASHEET] 276 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-199.2MHz Internal Oscillator Frequency vs. Temperature DFLL enabled, from the 32.768kHz internal oscillator 2.010 1.8 V 2.2 V 2.005 2.7 V 3.3 V 2.000 3.0 V z] H M 1.995 y [ c 1.990 n e u q 1.985 e Fr 1.980 1.975 1.970 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] Figure 33-200.2MHz Internal Oscillator Frequency vs. CALA Calibration Value V = 3V CC 2.5 -40 °C 2.4 2.3 25 °C z] MH 2.2 85 °C y [ 105 °C c 2.1 n e u q 2.0 e Fr 1.9 1.8 1.7 0 16 32 48 64 80 96 112 128 CALA XMEGA D3 [DATASHEET] 277 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33.3.8.4 32MHz Internal Oscillator Figure 33-201.32MHz Internal Oscillator Frequency vs. Temperature DFLL disabled 35.5 35.0 34.5 Hz] 34.0 M y [ 33.5 c en 33.0 u q e 32.5 Fr 3.3 V 32.0 3.0 V 2.7 V 31.5 2.2 V 1.8 V 31.0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] Figure 33-202.32MHz Internal Oscillator Frequency vs. Temperature DFLL enabled, from the 32.768kHz internal oscillator 32.2 1.8 V 32.1 2.2 V 3.3 V z] 32.0 2.7 V H 3.0 V M cy [ 31.9 n e u q e 31.8 Fr 31.7 31.6 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] XMEGA D3 [DATASHEET] 278 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-203. 32MHz Internal Oscillator CALA Calibration Step Size T = -40°C, V = 3.0V CC 0.33 % 0.30 % %] 0.28 % ze [ 0.25 % si p 0.23 % e St y 0.20 % -40 °C c n e 0.18 % u q e r 0.15 % F 0.13 % 0.10 % 0 16 32 48 64 80 96 112 128 CALA Figure 33-204. 32MHz Internal Oscillator CALA Calibration Step Size T = 25°C, V = 3.0V CC 0.25 % 0.24 % %] 0.22 % e [ z 0.21 % si p e 0.20 % St y 0.19 % c n ue 0.18 % q e 25 °C r 0.16 % F 0.15 % 0.14 % 0 16 32 48 64 80 96 112 128 CALA XMEGA D3 [DATASHEET] 279 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-205. 32MHz Internal Oscillator CALA Calibration Step Size T = 85°C, V = 3.0V CC 0.23 % 0.22 % %] 0.21 % e [ 0.20 % z si 0.19 % p e St 0.18 % y 85 °C c 0.17 % n e u 0.16 % q e Fr 0.15 % 0.14 % 0.13 % 0 16 32 48 64 80 96 112 128 CALA Figure 33-206. 32MHz Internal Oscillator CALA Calibration Step Size T = 105°C, V = 3.0V CC 0.24 % 0.23 % %] 0.22 % e [ 0.21 % z si 0.20 % p e St 0.19 % y c 0.17 % n e u 0.16 % q e Fr 0.15 % 0.14 % 105 °C 0.13 % 0 16 32 48 64 80 96 112 128 CALA XMEGA D3 [DATASHEET] 280 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-207.32MHz Internal Oscillator Frequency vs. CALB Calibration Value V = 3.0V CC 70 -40 °C 65 25 °C 60 85 °C 105 °C 55 z] MH 50 ncy [ 45 e u q 40 e Fr 35 30 25 20 0 7 14 21 28 35 42 49 56 63 DFLLRC32MCALB 33.3.8.5 32MHz Internal Oscillator Calibrated to 48MHz Figure 33-208.48MHz Internal Oscillator Frequency vs. Temperature DFLL disabled 54 53 52 z] H M 51 y [ c 50 n e qu 49 e 3.6 V Fr 48 3.3 V 3.0 V 47 2.7 V 1.8 V 46 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] XMEGA D3 [DATASHEET] 281 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-209.48MHz Internal Oscillator Frequency vs. Temperature DFLL enabled, from the 32.768kHz internal oscillator 48.2 1.8 V 48.1 3.6 V 48.0 3.0 V 2.7 V z] 47.9 3.3 V H M 47.8 y [ c 47.7 n e u q 47.6 e Fr 47.5 47.4 47.3 47.2 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] 33.3.9 Two-Wire Interface Characteristics Figure 33-210.SDA Hold Time vs. Temperature 500 450 3 400 350 s] 2 e [n 300 m 250 d ti ol 200 H 150 100 50 1 0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] XMEGA D3 [DATASHEET] 282 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-211.SDA Hold Time vs. Supply Voltage 500 450 3 400 350 s] 2 n e [ 300 m 250 d ti ol 200 H 150 100 50 1 0 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 V [V] CC 33.3.10 PDI Characteristics Figure 33-212.Maximum PDI Frequency vs. V CC 22 20 -40 °C 18 25 °C 85 °C z] 16 105 °C H M [X 14 A M 12 f 10 8 6 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] XMEGA D3 [DATASHEET] 283 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33.4 Atmel ATxmega192D3 33.4.1 Current Consumption 33.4.1.1Active Mode Supply Current Figure 33-213.Active Supply Current vs. Frequency f =0 - 1MHz external clock, T = 25°C SYS 650 3.3V 600 550 3.0V 500 450 2.7V A] 400 µ 350 [C 2.2V C 300 I 250 1.8V 200 150 100 50 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz] Figure 33-214.Active Supply Current vs. Frequency f =1 - 32MHz external clock, T = 25°C SYS 11 3.3V 10 9 3.0V 8 2.7V 7 A] m 6 [C IC 5 4 2.2V 3 2 1.8V 1 0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Frequency [MHz] XMEGA D3 [DATASHEET] 284 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-215.Active Mode Supply Current vs. V CC f =32.768kHz internal oscillator SYS 270 -40 °C 250 230 25 °C 210 85 °C 190 105 °C A] 170 µ c [ 150 c I 130 110 90 70 50 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-216.Active Mode Supply Current vs. V CC f =1MHz external clock SYS 750 -40 °C 700 25 °C 650 85 °C 105 °C 600 550 A] 500 µ c [ 450 c I 400 350 300 250 200 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] XMEGA D3 [DATASHEET] 285 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-217.Active Mode Supply Current vs. V CC f =2MHz internal oscillator SYS 1450 -40 °C 25 °C 1300 85 °C 105 °C 1150 A] 1000 µ c [ c 850 I 700 550 400 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-218.Active Mode Supply Current vs. V CC f =32MHz internal oscillator prescaled to 8MHz SYS 5.5 -40 °C 5.0 25 °C 85 °C 4.5 105 °C 4.0 A] 3.5 m c [ 3.0 c I 2.5 2.0 1.5 1.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] XMEGA D3 [DATASHEET] 286 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-219.Active Mode Supply Current vs. V CC f =32MHz internal oscillator SYS 14.0 -40 °C 13.0 25 °C 12.0 85 °C A] 11.0 105 °C m c [ c 10.0 I 9.0 8.0 7.0 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 VCC [V] 33.4.1.2Idle Mode Supply Current Figure 33-220.Idle Mode Supply Current vs. Frequency f =0 - 1MHz external clock, T = 25°C SYS 130 3.3V 117 104 3.0V 91 2.7V A] 78 µ [C 65 2.2V C I 52 1.8V 39 26 13 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz] XMEGA D3 [DATASHEET] 287 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-221.Idle Mode Supply Current vs. Frequency f =1 - 32MHz external clock, T = 25°C SYS 4.0 3.3V 3.5 3.0V 3.0 2.7V A] 2.5 m [C 2.0 C I 1.5 2.2V 1.0 1.8V 0.5 0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Frequency [MHz] Figure 33-222.Idle Mode Supply Current vs. V CC f =32.768kHz internal oscillator SYS 41 39 105 °C 37 35 A] c [µ 33 85 °C c I 31 -40 °C 25 °C 29 27 25 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] XMEGA D3 [DATASHEET] 288 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-223.Idle Mode Supply Current vs. V CC f =1MHz external clock SYS 160 105 °C 85 °C 145 25 °C -40 °C 130 115 A] µ100 c [ c I 85 70 55 40 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-224.Idle Mode Supply Current vs. V CC f =2MHz internal oscillator SYS 215 -40 °C 25 °C 195 105 °C 85 °C 175 A] 155 µ c [ c 135 I 115 95 75 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] XMEGA D3 [DATASHEET] 289 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-225.Idle Mode Supply Current vs. V CC f =32MHz internal oscillator prescaled to 8MHz SYS 1000 900 -40 °C 25 °C 85 °C 800 105 °C A] 700 µ c [ c 600 I 500 400 300 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-226.Idle Mode Current vs. V CC f =32MHz internal oscillator SYS 5.4 -40 °C 5.1 25 °C 4.8 85 °C 105 °C 4.5 A] m c [ 4.2 c I 3.9 3.6 3.3 3.0 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 VCC [V] XMEGA D3 [DATASHEET] 290 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33.4.1.3Power-down Mode Supply Current Figure 33-227.Power-down Mode Supply Current vs. V CC All functions disabled 12.0 105 °C 10.5 9.0 7.5 A] c [µ 6.0 c I 4.5 85 °C 3.0 1.5 25 °C -40 °C 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-228.Power-down Mode Supply Current vs. V CC Watchdog and sampled BOD enabled 12.0 105 °C 10.5 9.0 7.5 A] c [µ 6.0 c I 4.5 85 °C 3.0 1.5 25 °C -40 °C 0.0 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] XMEGA D3 [DATASHEET] 291 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-229.Power-down Mode Supply Current vs. Temperature Watchdog and sampled BOD enabled and running from internal ULP oscillator 10.5 3.0 V 2.7 V 9.0 2.2 V 1.8 V 7.5 A] 6.0 µ c [ c 4.5 I 3.0 1.5 0.0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] 33.4.2 I/O Pin Characteristics 33.4.2.1Pull-up Figure 33-230.I/O Pin Pull-up Resistor Current vs. Input Voltage V = 1.8V CC 72 64 56 48 A] 40 µ I [ 32 24 -40 °C 16 25 °C 8 85 °C 105 °C 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VPIN [V] XMEGA D3 [DATASHEET] 292 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-231.I/O Pin Pull-up Resistor Current vs. Input Voltage V = 3.0V CC 120 100 80 A] µ 60 I [ 40 -40 °C 20 25 °C 85 °C 105 °C 0 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 VPIN [V] Figure 33-232.I/O Pin Pull-up Resistor Current vs. Input Voltage V = 3.3V CC 140 120 100 80 A] µ I [ 60 40 -40 °C 25 °C 20 85 °C 105 °C 0 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 VPIN [V] XMEGA D3 [DATASHEET] 293 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33.4.2.2Output Voltage vs. Sink/Source Current Figure 33-233.I/O Pin Output Voltage vs. Source Current V = 1.8V CC 2.0 1.8 1.6 1.4 V] 1.2 N [ 1.0 PI 105 °C V 0.8 25 °C 0.6 -40 °C 0.4 0.2 85 °C 0.0 -5.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 IPIN [mA] Figure 33-234.I/O Pin Output Voltage vs. Source Current V = 3.0V CC 3.0 2.7 2.4 2.1 1.8 V] N [ 1.5 -40 °C PI 1.2 V 85 °C 105 °C 0.9 25 °C 0.6 0.3 0.0 -16 -14 -12 -10 -8 -6 -4 -2 0 IPIN [mA] XMEGA D3 [DATASHEET] 294 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-235.I/O Pin Output Voltage vs. Source Current V = 3.3V CC 3.3 3.0 2.7 2.4 2.1 N [V] 1.8 PI 1.5 105 °C V 1.2 0.9 85 °C 0.6 -40 °C 25 °C 0.3 0.0 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 IPIN [mA] Figure 33-236.I/O Pin Output Voltage vs. Sink Current V = 1.8V CC 1.0 105 °C 0.9 85 °C 0.8 0.7 25 °C V] 0.6 N [ 0.5 -40 °C PI V 0.4 0.3 0.2 0.1 0.0 0 1 2 3 4 5 6 7 8 IPIN [mA] XMEGA D3 [DATASHEET] 295 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-237.I/O Pin Output Voltage vs. Sink Current V = 3.0V CC 1.0 105 °C 0.9 85 °C 0.8 25 °C -40 °C 0.7 V] 0.6 N [ 0.5 PI V 0.4 0.3 0.2 0.1 0.0 0 2 4 6 8 10 12 14 16 IPIN [mA] Figure 33-238.I/O Pin Output Voltage vs. Sink Current V = 3.3V CC 1.0 105 °C 85 °C 0.9 25 °C 0.8 0.7 -40 °C V] 0.6 N [ 0.5 PI V 0.4 0.3 0.2 0.1 0.0 0 2 4 6 8 10 12 14 16 18 20 IPIN [mA] XMEGA D3 [DATASHEET] 296 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33.4.2.3Thresholds and Hysteresis Figure 33-239.I/O Pin Input Threshold Voltage vs. V CC V I/O pin read as “1” IH 1.8 -40 °C 1.7 25 °C 85 °C 1.6 105 °C 1.5 V] d [ 1.4 hol 1.3 s e hr 1.2 Vt 1.1 1.0 0.9 0.8 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-240.I/O Pin Input Threshold Voltage vs. V CC VIL I/O pin read as “0” p 1.65 105 °C 1.50 85 °C 25 °C 1.35 -40 °C 1.20 V] old [ 1.05 h s e 0.90 hr Vt 0.75 0.60 0.45 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] XMEGA D3 [DATASHEET] 297 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-241.I/O Pin Input Hysteresis vs. V CC 0.40 0.37 0.34 V] 0.31 [ hold 0.28 es hr Vt 0.25 -40 °C 0.22 25 °C 0.19 85 °C 105 °C 0.16 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V [V] CC 33.4.3 ADC Characteristics Figure 33-242.INL Error vs. External V REF T = 25C, V = 3.6V, external reference CC 1.6 1.4 1.2 Single-ended unsigned mode B] 1.0 S L L[ 0.8 N I 0.6 Differential mode 0.4 Single -ended signed mode 0.2 0.0 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 VREF [V] XMEGA D3 [DATASHEET] 298 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-243.INL Error vs. Sample Rate T = 25C, V = 3.6V, V = 3.0V external CC REF 0.70 0.65 Single-ended unsigned mode 0.60 0.55 B] S 0.50 Differential mode L L[ N 0.45 I 0.40 0.35 Single-ended signed mode 0.30 0.25 50 100 150 200 250 300 ADC sample rate [ksps] Figure 33-244.INL Error vs. Input Code 1.25 1.00 0.75 0.50 ] B 0.25 S L L[ 0.00 N I -0.25 -0.50 -0.75 -1.00 -1.25 0 512 1024 1536 2048 2560 3072 3584 4096 ADC input code XMEGA D3 [DATASHEET] 299 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-245.DNL Error vs. External V REF T = 25C, V = 3.6V, external reference CC 0.70 0.65 0.60 Single-ended unsigned mode 0.55 B] S 0.50 L L [ 0.45 N D 0.40 Differential mode 0.35 0.30 Single-ended signed mode 0.25 0.20 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 VREF [V] Figure 33-246.DNL Error vs. Sample Rate T = 25C, V = 3.6V, V = 3.0V external CC REF 0.60 0.55 Single-ended unsigned mode 0.50 B] 0.45 S L L [ 0.40 N D Differential mode 0.35 0.30 Single-ended signed mode 0.25 0.20 50 100 150 200 250 300 ADC sample rate [ksps] XMEGA D3 [DATASHEET] 300 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-247.DNL Error vs. Input Code 1 0.8 ] 0.6 B S L 0.4 [ L N 0.2 D 0 -0.2 -0.4 -0.6 0 512 1024 1536 2048 2560 3072 3584 4096 ADC input code Figure 33-248.Gain Error vs. V REF T = 25C, V = 3.6V, ADC sample rate = 300ksps CC -5 -6 ] -7 V Differential mode m -8 [ r o -9 r er Single-ended signed mode n -10 ai G -11 -12 -13 Single-ended unsigned mode -14 -15 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 VREF [V] XMEGA D3 [DATASHEET] 301 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-249.Gain Error vs. V CC T = 25C, V = external 1.0V, ADC sample rate = 300ksps REF -2 -3 ] V -4 m [ Differential mode r -5 o r Single-ended signed r e mode n -6 ai G Single-ended unsigned mode -7 -8 -9 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-250.Offset Error vs. V REF T = 25C, V = 3.6V, ADC sample rate = 300ksps CC 9.4 9.2 9.0 V] 8.8 m r [ 8.6 Differential mode rro 8.4 e et 8.2 Offs 8.0 7.8 7.6 7.4 7.2 7.0 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 VREF [V] XMEGA D3 [DATASHEET] 302 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-251.Gain Error vs. Temperature V = 3.0V, V = external 2.0V CC REF 0 -2 Single-ended signed mode -4 V] m or [ -6 err Differential mode n -8 ai G -10 Single-ended unsigned mode -12 -14 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] Figure 33-252.Offset Error vs. V CC T = 25C, V = external 1.0V, ADC sample rate = 300ksps REF 8.00 7.00 ] V m 6.00 [ r 5.00 o r Differential mode r e 4.00 et s Off 3.00 2.00 1.00 0.00 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] XMEGA D3 [DATASHEET] 303 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33.4.4 Analog Comparator Characteristics Figure 33-253.Analog Comparator Hysteresis vs. V CC Small hysteresis 19 105°C 18 85°C 17 16 25°C mV]15 V[HYST14 -40°C 13 12 11 10 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC[V] Figure 33-254.Analog Comparator Hysteresis vs. V CC Large hysteresis 36 105°C 34 85°C 32 30 25°C mV]28 V[HYST26 -40°C 24 22 20 18 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC[V] XMEGA D3 [DATASHEET] 304 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-255.Analog Comparator Current Source vs. Calibration Value V = 3.0V CC 7.0 6.5 A] 6.0 µ [E C UR 5.5 O S T N E RR 5.0 U C I 4.5 -40 °C 25 °C 4.0 85 °C 105 °C 3.5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CURRCALIBA[3..0] Figure 33-256.Voltage Scaler INL vs. SCALEFAC T = 25C, V = 3.0V CC 0.39 0.36 0.33 B] 0.3 S L 25°C L [ 0.27 N I 0.24 0.21 0.18 0.15 0 5 10 15 20 25 30 35 40 45 50 55 60 65 SCALEFAC XMEGA D3 [DATASHEET] 305 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33.4.5 Internal 1.0V Reference Characteristics Figure 33-257.ADC Internal 1.0V Reference vs. Temperature 1.007 1.006 1.005 V] e [ 1.004 g a 1.003 olt V 1.002 p 1.6 V a 1.001 g d n 1.000 2.7 V a B 3.6 V 0.999 0.998 0.997 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 T [°C] 33.4.6 BOD Characteristics Figure 33-258.BOD Thresholds vs. Temperature BOD level = 1.6V 1.68 1.67 1.66 1.65 T [V] 1.64 O B 1.63 V 1.62 1.61 1.60 1.59 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] XMEGA D3 [DATASHEET] 306 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-259.BOD Thresholds vs. Temperature BOD level = 3.0V 3.16 3.14 3.12 3.10 V] T [ 3.08 O B V 3.06 3.04 3.02 3.00 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] 33.4.7 External Reset Characteristics Figure 33-260.Minimum Reset Pin Pulse Width vs. V CC 136 128 120 s] 112 n [ T RS 104 t 105 °C 96 85 °C 88 25 °C -40 °C 80 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V [V] CC XMEGA D3 [DATASHEET] 307 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-261.Reset Pin Pull-up Resistor Current vs. Reset Pin Voltage V = 1.8V CC 72 64 56 48 A] 40 µ I [ 32 24 -40 °C 16 25 °C 8 85 °C 105 °C 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VPIN [V] Figure 33-262.Reset Pin Pull-up Resistor Current vs. Reset Pin Voltage V = 3.0V CC 140 120 100 A] 80 µ [ T E ES 60 R I 40 -40 °C 25 °C 20 85 °C 105°C 0 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 V [V] RESET XMEGA D3 [DATASHEET] 308 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-263.Reset Pin Pull-up Resistor Current vs. Reset Pin Voltage V = 3.3V CC 144 126 108 90 A] µ [T 72 E S E IR 54 36 -40 °C 25 °C 18 85 °C 105°C 0 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 V [V] RESET Figure 33-264.Reset Pin Input Threshold Voltage vs. V CC V - Reset pin read as “1” IH 1.8 105 °C 85 °C 1.6 25 °C -40 °C 1.4 V] [ D 1.2 OL H S E 1.0 R H T V 0.8 0.6 0.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V [V] CC XMEGA D3 [DATASHEET] 309 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33.4.8 Oscillator Characteristics 33.4.8.1 Ultra Low-Power Internal Oscillator Figure 33-265.Ultra Low-Power Internal Oscillator Frequency vs. Temperature 35.5 35.0 34.5 z] 34.0 H y [k 33.5 nc 33.0 e u eq 32.5 3.6 V Fr 32.0 3.3 V 3.0 V 31.5 2.7 V 2.0 V 31.0 1.8 V 1.6 V 30.5 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] 33.4.8.2 32.768kHz Internal Oscillator Figure 33-266.32.768kHz Internal Oscillator Frequency vs. Temperature 32.768kHz internal oscillator frequency vs. temperature 32.90 1.6 V 32.85 1.8 V 2.2 V 32.80 2.7 V z] 3.0 V kH 32.75 3.3 V y [ 3.6 V c 32.70 n e u q 32.65 e Fr 32.60 32.55 32.50 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] XMEGA D3 [DATASHEET] 310 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-267.32.768kHz Internal Oscillator Frequency vs. Calibration Value V = 3.0V, T = 25°C CC 53 3.0 V 50 47 ] z H 44 k [ y 41 c n e 38 u q e 35 r F 32 29 26 23 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 RC32KCAL[7..0] 33.4.8.3 2MHz Internal Oscillator Figure 33-268.2MHz Internal Oscillator Frequency vs. Temperature DFLL disabled 2.16 2.14 2.12 z] 2.10 H M 2.08 y [ c 2.06 n e u 2.04 eq 3.6 V Fr 2.02 3.3 V 3.0 V 2.00 2.7 V 1.98 2.2 V 1.8 V 1.96 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] XMEGA D3 [DATASHEET] 311 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-269.2MHz Internal Oscillator Frequency vs. Temperature DFLL enabled, from the 32.768kHz internal oscillator 2.010 1.8 V 2.005 2.2 V 2.000 2.7 V z] 3.0 V H M 1.995 3.3 V y [ 3.6 V c 1.990 n e u q 1.985 e Fr 1.980 1.975 1.970 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] Figure 33-270.2MHz Internal Oscillator Frequency vs. CALA Calibration Value V = 3V CC 2.6 -40 °C 2.5 2.4 25 °C Hz] 2.3 M 85 °C y [ 2.2 105 °C c n e 2.1 u q e 2.0 Fr 1.9 1.8 1.7 0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 CALA XMEGA D3 [DATASHEET] 312 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33.4.8.4 32MHz Internal Oscillator Figure 33-271.32MHz Internal Oscillator Frequency vs. Temperature DFLL disabled 36.5 36.0 35.5 35.0 Hz] 34.5 M cy [ 34.0 n e 33.5 u q Fre 33.0 3.3V 32.5 3.0V 2.7V 32.0 2.2V 31.5 1.8V 31.0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] Figure 33-272.32MHz Internal Oscillator Frequency vs. Temperature DFLL enabled, from the 32.768kHz internal oscillator 32.15 1.8V 32.10 2.2V 32.05 2.7V Hz] 32.00 3.0V M 3.3V ncy [ 31.95 e u q e 31.90 Fr 31.85 31.80 31.75 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] XMEGA D3 [DATASHEET] 313 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-273. 32MHz Internal Oscillator CALA Calibration Step Size T = -40°C, V = 3.0V CC 0.4 0.35 %] 0.3 e [ z Si 0.25 p e St 0.2 -40 °C y c n 0.15 e u q e 0.1 r F 0.05 0 0 16 32 48 64 80 96 112 128 CALA Figure 33-274. 32MHz Internal Oscillator CALA Calibration Step Size T = 25°C, V = 3.0V CC 0.28 0.26 %] 0.24 e [ z 0.22 Si p 0.2 e St y 0.18 c n 25 °C e 0.16 u q e r 0.14 F 0.12 0.1 0 16 32 48 64 80 96 112 128 CALA XMEGA D3 [DATASHEET] 314 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-275. 32MHz Internal Oscillator CALA Calibration Step Size T = 85°C, V = 3.0V CC 0.26 0.24 %] 0.22 e [ z Si 0.2 p e St 0.18 y 85 °C c n 0.16 e u q e 0.14 r F 0.12 0.1 0 16 32 48 64 80 96 112 128 CALA Figure 33-276. 32MHz Internal Oscillator CALA Calibration Step Size T = 105°C, V = 3.0V CC 0.24 0.22 %] e [ 0.2 z Si p 0.18 e St y 0.16 105 °C c n e u q 0.14 e r F 0.12 0.1 0 16 32 48 64 80 96 112 128 CALA XMEGA D3 [DATASHEET] 315 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-277.32MHz Internal Oscillator Frequency vs. CALB Calibration Value V = 3.0V CC 70 65 -40 °C 25 °C 60 85 °C z] 55 105 °C H M 50 y [ c 45 n e u 40 q e Fr 35 30 25 20 0 7 14 21 28 35 42 49 56 63 CALB 33.4.8.5 32MHz Internal Oscillator Calibrated to 48MHz Figure 33-278.48MHz Internal Oscillator Frequency vs. Temperature DFLL disabled 32MHz internal oscillator frequency vs. temperature Using 48MHz calibration value from signature row. DFLL disabled 55 54 53 z] 52 H M h [ 51 c n e 50 u q Fre 49 3.3V 3.0V 48 2.7V 47 2.2V 1.8V 46 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] XMEGA D3 [DATASHEET] 316 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-279.48MHz Internal Oscillator Frequency vs. Temperature DFLL enabled, from the 32.768kHz internal oscillator 48.3 48.2 Hz] 48.1 1.8V 2.2V 23..70VV M 3.3V y [ 48.0 c n ue 47.9 q e Fr 47.8 47.7 47.6 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] 33.4.9 Two-Wire Interface Characteristics Figure 33-280.SDA Hold Time vs. Temperature 500 450 3 400 350 s] 2 n 300 e [ m 250 d ti 200 ol H 150 100 50 1 0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] XMEGA D3 [DATASHEET] 317 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-281.SDA Hold Time vs. Supply Voltage 500 450 3 400 350 s] 2 n 300 e [ m 250 old ti 200 H 150 100 50 1 0 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 V [V] CC 33.4.10PDI Characteristics Figure 33-282.Maximum PDI Frequency vs. V CC 36 -40°C 31 25°C 85°C z] 26 H M [X MA 21 f 16 11 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 V [V] CC XMEGA D3 [DATASHEET] 318 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33.5 Atmel ATxmega256D3 33.5.1 Current Consumption 33.5.1.1Active Mode Supply Current Figure 33-283.Active Supply Current vs. Frequency f =0 - 1MHz external clock, T = 25°C SYS 650 3.3V 600 550 3.0V 500 450 2.7V A] 400 µ 350 [C 2.2V C 300 I 250 1.8V 200 150 100 50 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz] Figure 33-284.Active Supply Current vs. Frequency f =1 - 32MHz external clock, T = 25°C SYS 11 3.3V 10 9 3.0V 8 2.7V 7 A] m 6 [C IC 5 4 2.2V 3 2 1.8V 1 0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Frequency [MHz] XMEGA D3 [DATASHEET] 319 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-285.Active Mode Supply Current vs. V CC f =32.768kHz internal oscillator SYS 270 -40 °C 250 230 25 °C 210 85 °C 190 105 °C A] 170 µ c [ 150 c I 130 110 90 70 50 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-286.Active Mode Supply Current vs. V CC f =1MHz external clock SYS 750 -40 °C 700 25 °C 650 85 °C 105 °C 600 550 A] 500 µ c [ 450 c I 400 350 300 250 200 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] XMEGA D3 [DATASHEET] 320 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-287.Active Mode Supply Current vs. V CC f =2MHz internal oscillator SYS 1450 -40 °C 25 °C 1300 85 °C 105 °C 1150 A] 1000 µ c [ c 850 I 700 550 400 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-288.Active Mode Supply Current vs. V CC f =32MHz internal oscillator prescaled to 8MHz SYS 5.5 -40 °C 5.0 25 °C 85 °C 4.5 105 °C 4.0 A] 3.5 m c [ 3.0 c I 2.5 2.0 1.5 1.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] XMEGA D3 [DATASHEET] 321 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-289.Active Mode Supply Current vs. V CC f =32MHz internal oscillator SYS 14.0 -40 °C 13.0 25 °C 12.0 85 °C A] 11.0 105 °C m c [ c 10.0 I 9.0 8.0 7.0 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 VCC [V] 33.5.1.2Idle Mode Supply Current Figure 33-290.Idle Mode Supply Current vs. Frequency f =0 - 1MHz external clock, T = 25°C SYS 130 3.3V 117 104 3.0V 91 2.7V A] 78 µ [C 65 2.2V C I 52 1.8V 39 26 13 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz] XMEGA D3 [DATASHEET] 322 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-291.Idle Mode Supply Current vs. Frequency f =1 - 32MHz external clock, T = 25°C SYS 4.0 3.3V 3.5 3.0V 3.0 2.7V A] 2.5 m [C 2.0 C I 1.5 2.2V 1.0 1.8V 0.5 0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Frequency [MHz] Figure 33-292.Idle Mode Supply Current vs. V CC f =32.768kHz internal oscillator SYS 41 39 105 °C 37 35 A] c [µ 33 85 °C c I 31 -40 °C 25 °C 29 27 25 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] XMEGA D3 [DATASHEET] 323 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-293.Idle Mode Supply Current vs. V CC f =1MHz external clock SYS 160 105 °C 85 °C 145 25 °C -40 °C 130 115 A] µ100 c [ c I 85 70 55 40 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-294.Idle Mode Supply Current vs. V CC f =2MHz internal oscillator SYS 215 -40 °C 25 °C 195 105 °C 85 °C 175 A] 155 µ c [ c 135 I 115 95 75 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] XMEGA D3 [DATASHEET] 324 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-295.Idle Mode Supply Current vs. V CC f =32MHz internal oscillator prescaled to 8MHz SYS 1000 900 -40 °C 25 °C 85 °C 800 105 °C A] 700 µ c [ c 600 I 500 400 300 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-296.Idle Mode Current vs. V CC f =32MHz internal oscillator SYS 5.4 -40 °C 5.1 25 °C 4.8 85 °C 105 °C 4.5 A] m c [ 4.2 c I 3.9 3.6 3.3 3.0 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 VCC [V] XMEGA D3 [DATASHEET] 325 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33.5.1.3Power-down Mode Supply Current Figure 33-297.Power-down Mode Supply Current vs. V CC All functions disabled 12.0 105 °C 10.5 9.0 7.5 A] c [µ 6.0 c I 4.5 85 °C 3.0 1.5 25 °C -40 °C 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-298.Power-down Mode Supply Current vs. V CC Watchdog and sampled BOD enabled 12.0 105 °C 10.5 9.0 7.5 A] c [µ 6.0 c I 4.5 85 °C 3.0 1.5 25 °C -40 °C 0.0 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] XMEGA D3 [DATASHEET] 326 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-299.Power-down Mode Supply Current vs. Temperature Watchdog and sampled BOD enabled and running from internal ULP oscillator 10.5 3.0 V 2.7 V 9.0 2.2 V 1.8 V 7.5 A] 6.0 µ c [ c 4.5 I 3.0 1.5 0.0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] 33.5.2 I/O Pin Characteristics 33.5.2.1Pull-up Figure 33-300.I/O Pin Pull-up Resistor Current vs. Input Voltage V = 1.8V CC 72 64 56 48 A] 40 µ I [ 32 24 -40 °C 16 25 °C 8 85 °C 105 °C 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VPIN [V] XMEGA D3 [DATASHEET] 327 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-301.I/O Pin Pull-up Resistor Current vs. Input Voltage V = 3.0V CC 120 100 80 A] µ 60 I [ 40 -40 °C 20 25 °C 85 °C 105 °C 0 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 VPIN [V] Figure 33-302.I/O Pin Pull-up Resistor Current vs. Input Voltage V = 3.3V CC 140 120 100 80 A] µ I [ 60 40 -40 °C 25 °C 20 85 °C 105 °C 0 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 VPIN [V] XMEGA D3 [DATASHEET] 328 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33.5.2.2Output Voltage vs. Sink/Source Current Figure 33-303.I/O Pin Output Voltage vs. Source Current V = 1.8V CC 2.0 1.8 1.6 1.4 V] 1.2 N [ 1.0 PI 105 °C V 0.8 25 °C 0.6 -40 °C 0.4 0.2 85 °C 0.0 -5.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 IPIN [mA] Figure 33-304.I/O Pin Output Voltage vs. Source Current V = 3.0V CC 3.0 2.7 2.4 2.1 1.8 V] N [ 1.5 -40 °C PI 1.2 V 85 °C 105 °C 0.9 25 °C 0.6 0.3 0.0 -16 -14 -12 -10 -8 -6 -4 -2 0 IPIN [mA] XMEGA D3 [DATASHEET] 329 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-305.I/O Pin Output Voltage vs. Source Current V = 3.3V CC 3.3 3.0 2.7 2.4 2.1 N [V] 1.8 PI 1.5 105 °C V 1.2 0.9 85 °C 0.6 -40 °C 25 °C 0.3 0.0 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 IPIN [mA] Figure 33-306.I/O Pin Output Voltage vs. Sink Current V = 1.8V CC 1.0 105 °C 0.9 85 °C 0.8 0.7 25 °C V] 0.6 N [ 0.5 -40 °C PI V 0.4 0.3 0.2 0.1 0.0 0 1 2 3 4 5 6 7 8 IPIN [mA] XMEGA D3 [DATASHEET] 330 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-307.I/O Pin Output Voltage vs. Sink Current V = 3.0V CC 1.0 105 °C 0.9 85 °C 0.8 25 °C -40 °C 0.7 V] 0.6 N [ 0.5 PI V 0.4 0.3 0.2 0.1 0.0 0 2 4 6 8 10 12 14 16 IPIN [mA] Figure 33-308.I/O Pin Output Voltage vs. Sink Current V = 3.3V CC 1.0 105 °C 85 °C 0.9 25 °C 0.8 0.7 -40 °C V] 0.6 N [ 0.5 PI V 0.4 0.3 0.2 0.1 0.0 0 2 4 6 8 10 12 14 16 18 20 IPIN [mA] XMEGA D3 [DATASHEET] 331 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33.5.2.3Thresholds and Hysteresis Figure 33-309.I/O Pin Input Threshold Voltage vs. V CC V I/O pin read as “1” IH 1.8 -40 °C 1.7 25 °C 85 °C 1.6 105 °C 1.5 V] d [ 1.4 hol 1.3 s e hr 1.2 Vt 1.1 1.0 0.9 0.8 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-310.I/O Pin Input Threshold Voltage vs. V CC V I/O pin read as “0” IL 1.65 105 °C 1.50 85 °C 25 °C 1.35 -40 °C 1.20 V] old [ 1.05 h s e 0.90 hr Vt 0.75 0.60 0.45 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] XMEGA D3 [DATASHEET] 332 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-311.I/O Pin Input Hysteresis vs. V CC 0.40 0.37 0.34 V] 0.31 [ d hol 0.28 es hr Vt 0.25 -40 °C 0.22 25 °C 0.19 85 °C 105 °C 0.16 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V [V] CC 33.5.3 ADC Characteristics Figure 33-312.INL Error vs. External V REF T = 25C, V = 3.6V, external reference CC 1.6 1.4 1.2 Single-ended unsigned mode B] 1.0 S L L[ 0.8 N I 0.6 Differential mode 0.4 Single -ended signed mode 0.2 0.0 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 VREF [V] XMEGA D3 [DATASHEET] 333 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-313.INL Error vs. Sample Rate T = 25C, V = 3.6V, V = 3.0V external CC REF , , 0.70 0.65 Single-ended unsigned mode 0.60 0.55 B] S 0.50 Differential mode L L[ N 0.45 I 0.40 0.35 Single-ended signed mode 0.30 0.25 50 100 150 200 250 300 ADCsamplerate[ksps] Figure 33-314.INL Error vs. Input Code 1.25 1.00 0.75 0.50 B] S 0.25 L L[ 0.00 N I -0.25 -0.50 -0.75 -1.00 -1.25 0 512 1024 1536 2048 2560 3072 3584 4096 ADC input code XMEGA D3 [DATASHEET] 334 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-315.DNL Error vs. External V REF T = 25C, V = 3.6V, external reference CC 0.70 0.65 0.60 Single-ended unsigned mode 0.55 B] S 0.50 L L [ 0.45 N D 0.40 Differential mode 0.35 0.30 Single-ended signed mode 0.25 0.20 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 VREF [V] Figure 33-316.DNL Error vs. Sample Rate T = 25C, V = 3.6V, V = 3.0V external CC REF 0.60 0.55 Single-ended unsigned mode 0.50 B] 0.45 S L L [ 0.40 N D Differential mode 0.35 0.30 Single-ended signed mode 0.25 0.20 50 100 150 200 250 300 ADC sample rate [ksps] XMEGA D3 [DATASHEET] 335 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-317.DNL Error vs. Input Code 1 0.8 ] 0.6 B S L 0.4 [ L N 0.2 D 0 -0.2 -0.4 -0.6 0 512 1024 1536 2048 2560 3072 3584 4096 Figure 33-318.Gain Error vs. V REF T = 25C, V = 3.6V, ADC sample rate = 300ksps CC -5 -6 ] -7 V Differential mode m -8 [ r o -9 r er Single-ended signed mode n -10 ai G -11 -12 -13 Single-ended unsigned mode -14 -15 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 VREF [V] XMEGA D3 [DATASHEET] 336 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-319.Gain Error vs. V CC T = 25C, V = external 1.0V, ADC sample rate = 300ksps REF 4 2 Single-ended signed mode V] 0 m error [ -2 n Single-ended unsigned mode ai -4 G -6 Differential mode -8 -10 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 V [V] REF Figure 33-320.Offset Error vs. V REF T = 25C, V = 3.6V, ADC sample rate = 300ksps CC 9.4 9.2 9.0 V] 8.8 m [ 8.6 Differential mode r ro 8.4 r e 8.2 et fs 8.0 Of 7.8 7.6 7.4 7.2 7.0 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 VREF [V] XMEGA D3 [DATASHEET] 337 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-321.Gain Error vs. Temperature V = 3.0V, V = external 2.0V CC REF 0 -2 Single-ended signed mode -4 V] m or [ -6 err Differential mode n -8 ai G -10 Single-ended unsigned mode -12 -14 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] Figure 33-322.Offset Error vs. V CC T = 25C, V = external 1.0V, ADC sample rate = 300ksps REF 8.00 7.00 ] V m 6.00 [ r 5.00 o r Differential mode r e 4.00 et s Off 3.00 2.00 1.00 0.00 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] XMEGA D3 [DATASHEET] 338 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33.5.4 Analog Comparator Characteristics Figure 33-323.Analog Comparator Hysteresis vs. V CC Small hysteresis Highspeed mode, small hysteresis 19 105°C 18 85°C 17 16 25°C mV]15 V[HYST14 -40°C 13 12 11 10 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC[V] Figure 33-324.Analog Comparator Hysteresis vs. V CC Large hysteresis Highspeed mode, large hysteresis 36 105°C 34 85°C 32 30 25°C mV]28 V[HYST26 -40°C 24 22 20 18 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC[V] XMEGA D3 [DATASHEET] 339 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-325.Analog Comparator Current Source vs. Calibration Value V = 3.0V CC 7.0 6.5 A] 6.0 µ [E C UR 5.5 O S T N E RR 5.0 U C I 4.5 -40 °C 25 °C 4.0 85 °C 105 °C 3.5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CURRCALIBA[3..0] Figure 33-326.Voltage Scaler INL vs. SCALEFAC T = 25C, V = 3.0V CC 0.39 0.36 0.33 B] 0.3 S L 25°C L [ 0.27 N I 0.24 0.21 0.18 0.15 0 5 10 15 20 25 30 35 40 45 50 55 60 65 SCALEFAC XMEGA D3 [DATASHEET] 340 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33.5.5 Internal 1.0V Reference Characteristics Figure 33-327.ADC Internal 1.0V Reference vs. Temperature 1.007 1.006 1.005 V] e [ 1.004 g a 1.003 olt V 1.002 p 1.6 V a 1.001 g d n 1.000 2.7 V a B 3.6 V 0.999 0.998 0.997 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 T [°C] 33.5.6 BOD Characteristics Figure 33-328.BOD Thresholds vs. Temperature BOD level = 1.6V 1.68 1.67 1.66 1.65 T [V] 1.64 O B 1.63 V 1.62 1.61 1.60 1.59 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] XMEGA D3 [DATASHEET] 341 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-329.BOD Thresholds vs. Temperature BOD level = 3.0V 3.16 3.14 3.12 3.10 V] T [ 3.08 O B V 3.06 3.04 3.02 3.00 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] 33.5.7 External Reset Characteristics Figure 33-330.Minimum Reset Pin Pulse Width vs. V CC 136 128 120 s] 112 n [ T RS 104 t 105 °C 96 85 °C 88 25 °C -40 °C 80 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V [V] CC XMEGA D3 [DATASHEET] 342 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-331.Reset Pin Pull-up Resistor Current vs. Reset Pin Voltage V = 1.8V CC 80 70 60 50 A] µ [T 40 E S E IR 30 20 -40 °C 25 °C 10 85 °C 105°C 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 V [V] RESET Figure 33-332.Reset Pin Pull-up Resistor Current vs. Reset Pin Voltage V = 3.0V CC 140 120 100 A] 80 µ [ T E ES 60 R I 40 -40 °C 25 °C 20 85 °C 105°C 0 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 V [V] RESET XMEGA D3 [DATASHEET] 343 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-333.Reset Pin Pull-up Resistor Current vs. Reset Pin Voltage V = 3.3V CC V 3.3 V CC 144 126 108 90 A] µ [T 72 E S E IR 54 36 -40 °C 25 °C 18 85 °C 105°C 0 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 V [V] RESET Figure 33-334.Reset Pin Input Threshold Voltage vs. V CC V - Reset pin read as “1” IH 1.8 105 °C 85 °C 1.6 25 °C -40 °C 1.4 V] [ D 1.2 OL H S E 1.0 R H T V 0.8 0.6 0.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V [V] CC XMEGA D3 [DATASHEET] 344 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33.5.8 Oscillator Characteristics 33.5.8.1Ultra Low-Power Internal Oscillator Figure 33-335.Ultra Low-Power Internal Oscillator Frequency vs. Temperature 35.5 35.0 34.5 z] 34.0 H y [k 33.5 nc 33.0 e u eq 32.5 3.6 V Fr 32.0 3.3 V 3.0 V 31.5 2.7 V 2.0 V 31.0 1.8 V 1.6 V 30.5 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] 33.5.8.2 32.768kHz Internal Oscillator Figure 33-336.32.768kHz Internal Oscillator Frequency vs. Temperature 32.90 1.6 V 32.85 1.8 V 2.2 V 32.80 2.7 V z] 3.0 V kH 32.75 3.3 V y [ 3.6 V c 32.70 n e u q 32.65 e Fr 32.60 32.55 32.50 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] XMEGA D3 [DATASHEET] 345 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-337.32.768kHz Internal Oscillator Frequency vs. Calibration Value V = 3.0V, T = 25°C CC 53 3.0 V 50 47 ] z H 44 k [ y 41 c n e 38 u q e 35 r F 32 29 26 23 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 RC32KCAL[7..0] 33.5.8.3 2MHz Internal Oscillator Figure 33-338.2MHz Internal Oscillator Frequency vs. Temperature DFLL disabled 2.16 2.14 2.12 z] 2.10 H M 2.08 y [ c 2.06 n e u 2.04 eq 3.6 V Fr 2.02 3.3 V 3.0 V 2.00 2.7 V 1.98 2.2 V 1.8 V 1.96 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] XMEGA D3 [DATASHEET] 346 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-339.2MHz Internal Oscillator Frequency vs. Temperature DFLL enabled, from the 32.768kHz internal oscillator 2.010 1.8 V 2.005 2.2 V 2.000 2.7 V z] 3.0 V H M 1.995 3.3 V y [ 3.6 V c 1.990 n e u q 1.985 e Fr 1.980 1.975 1.970 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] Figure 33-340.2MHz Internal Oscillator Frequency vs. CALA Calibration Value V = 3V CC 2.6 -40 °C 2.5 2.4 25 °C Hz] 2.3 M 85 °C y [ 2.2 105 °C c n e 2.1 u q e 2.0 Fr 1.9 1.8 1.7 0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 CALA XMEGA D3 [DATASHEET] 347 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33.5.8.4 32MHz Internal Oscillator Figure 33-341.32MHz Internal Oscillator Frequency vs. Temperature DFLL disabled 36.5 36.0 35.5 35.0 Hz] 34.5 M cy [ 34.0 n e 33.5 u q Fre 33.0 3.3V 32.5 3.0V 2.7V 32.0 2.2V 31.5 1.8V 31.0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] Figure 33-342.32MHz Internal Oscillator Frequency vs. Temperature DFLL enabled, from the 32.768kHz internal oscillator 32.15 1.8V 32.10 2.2V 32.05 2.7V Hz] 32.00 3.0V M 3.3V ncy [ 31.95 e u q e 31.90 Fr 31.85 31.80 31.75 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] XMEGA D3 [DATASHEET] 348 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-343. 32MHz Internal Oscillator CALA Calibration Step Size T = -40°C, V = 3.0V CC 0.4 0.35 %] 0.3 e [ z Si 0.25 p e St 0.2 -40 °C y c n 0.15 e u q e 0.1 r F 0.05 0 0 16 32 48 64 80 96 112 128 CALA Figure 33-344. 32MHz Internal Oscillator CALA Calibration Step Size T = 25°C, V = 3.0V CC 0.28 0.26 %] 0.24 e [ z 0.22 Si p 0.2 e St y 0.18 c n 25 °C e 0.16 u q e r 0.14 F 0.12 0.1 0 16 32 48 64 80 96 112 128 CALA XMEGA D3 [DATASHEET] 349 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-345. 32MHz Internal Oscillator CALA Calibration Step Size T = 85°C, V = 3.0V CC 0.26 0.24 %] 0.22 e [ z Si 0.2 p e St 0.18 y 85 °C c n 0.16 e u q e 0.14 r F 0.12 0.1 0 16 32 48 64 80 96 112 128 CALA Figure 33-346. 32MHz Internal Oscillator CALA Calibration Step Size T = 105°C, V = 3.0V CC 0.24 0.22 %] e [ 0.2 z Si p 0.18 e St y 0.16 105 °C c n e u q 0.14 e r F 0.12 0.1 0 16 32 48 64 80 96 112 128 CALA XMEGA D3 [DATASHEET] 350 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-347.32MHz Internal Oscillator Frequency vs. CALB Calibration Value V = 3.0V CC 70 65 -40 °C 25 °C 60 85 °C z] 55 105 °C H M 50 y [ c 45 n e u 40 q e Fr 35 30 25 20 0 7 14 21 28 35 42 49 56 63 CALB 33.5.8.5 32MHz Internal Oscillator Calibrated to 48MHz Figure 33-348.48MHz Internal Oscillator Frequency vs. Temperature DFLL disabled 54 53 52 z] H M 51 y [ c 50 n e u q 49 e 3.6 V Fr 3.3 V 48 3.0 V 2.7 V 47 2.2 V 1.8 V 46 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] XMEGA D3 [DATASHEET] 351 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-349.48MHz Internal Oscillator Frequency vs. Temperature DFLL enabled, from the 32.768kHz internal oscillator 48.3 1.8 V 48.2 2.2 V 3.6 V 48.1 3.3 V z] 48.0 2.7 V H 3.0 V M 47.9 y [ c 47.8 n e u 47.7 q e Fr 47.6 47.5 47.4 47.3 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] 33.5.9 Two-Wire Interface Characteristics Figure 33-350.SDA Hold Time vs. Temperature 500 450 3 400 350 s] 2 e [n 300 m 250 old ti 200 H 150 100 50 1 0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] XMEGA D3 [DATASHEET] 352 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-351.SDA Hold Time vs. Supply Voltage 500 450 3 400 350 s] 2 e [n 300 m 250 d ti ol 200 H 150 100 50 1 0 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 V [V] CC 33.5.10 PDI Characteristics Figure 33-352.Maximum PDI Frequency vs. V CC 36 -40°C 31 25°C 85°C z] 26 H M [X MA 21 f 16 11 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 V [V] CC XMEGA D3 [DATASHEET] 353 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33.6 Atmel ATxmega384D3 33.6.1 Current Consumption 33.6.1.1 Active Mode Supply Current Figure 33-353.Active Supply Current vs. Frequency f =0 - 1MHz external clock, T = 25°C SYS 650 3.3V 600 550 3.0V 500 450 2.7V A] 400 µ 350 [C 2.2V C 300 I 250 1.8V 200 150 100 50 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz] Figure 33-354.Active Supply Current vs. Frequency f =1 - 32MHz external clock, T = 25°C SYS 11 3.3V 10 9 3.0V 8 2.7V 7 A] m 6 [C IC 5 4 2.2V 3 2 1.8V 1 0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Frequency [MHz] XMEGA D3 [DATASHEET] 354 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-355.Active Mode Supply Current vs. V CC f =32.768kHz internal oscillator SYS 500 450 -40 °C 400 25 °C 350 85 °C 300 105 °C A] [µ 250 C C I 200 150 100 50 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V [V] CC Figure 33-356.Active Mode Supply Current vs. V CC f =1MHz external clock SYS 1280 -40 °C 1160 25 °C 1040 85 °C 920 105 °C A] 800 µ c [ 680 c I 560 440 320 200 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V [V] CC XMEGA D3 [DATASHEET] 355 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-357.Active Mode Supply Current vs. V CC f =2MHz internal oscillator SYS 1980 1780 -40 °C 25 °C 1580 85 °C 1380 105 °C A] c [µ 1180 c I 980 780 580 380 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V [V] CC Figure 33-358.Active Mode Supply Current vs. V CC f =32MHz internal oscillator prescaled to 8MHz SYS 7.0 6.0 -40 °C 25 °C 85 °C 5.0 105 °C A] m c [ 4.0 c I 3.0 2.0 1.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V [V] CC XMEGA D3 [DATASHEET] 356 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-359.Active Mode Supply Current vs. V CC f =32MHz internal oscillator SYS 15.0 -40 °C 14.0 13.0 25 °C 85 °C A] 12.0 m 105 °C c [ c 11.0 I 10.0 9.0 8.0 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 V [V] CC 33.6.1.2 Idle Mode Supply Current Figure 33-360.Idle Mode Supply Current vs. Frequency f =0 - 1MHz external clock, T = 25°C SYS 130 3.3V 117 104 3.0V 91 2.7V A] 78 µ [C 65 2.2V C I 52 1.8V 39 26 13 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz] XMEGA D3 [DATASHEET] 357 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-361.Idle Mode Supply Current vs. Frequency f =1 - 32MHz external clock, T = 25°C SYS 4.0 3.3V 3.5 3.0V 3.0 2.7V A] 2.5 m [C 2.0 C I 1.5 2.2V 1.0 1.8V 0.5 0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Frequency [MHz] Figure 33-362.Idle Mode Supply Current vs. V CC f =32.768kHz internal oscillator SYS 46 105 °C 44 42 40 A] 38 µ c [ 36 85 °C c I 34 -40 °C 32 25 °C 30 28 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V [V] CC XMEGA D3 [DATASHEET] 358 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-363.Idle Mode Supply Current vs. V CC f =1MHz external clock SYS 330 105 °C 300 85 °C 25 °C 270 -40 °C 240 A] c [µ 210 c I 180 150 120 90 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V [V] CC Figure 33-364.Idle Mode Supply Current vs. V CC f =2MHz internal oscillator SYS 640 105 °C 590 85 °C 25 °C 540 -40 °C 490 A] 440 µ c [ 390 c I 340 290 240 190 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V [V] CC XMEGA D3 [DATASHEET] 359 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-365.Idle Mode Supply Current vs. V CC f =32MHz internal oscillator prescaled to 8MHz SYS 1900 -40 °C 25 °C 1700 85 °C 1500 105 °C A] 1300 µ c [ c 1100 I 900 700 500 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V [V] CC Figure 33-366.Idle Mode Current vs. V CC f =32MHz internal oscillator SYS 5100 -40 °C 4800 25 °C 4500 85 °C 105 °C A] 4200 µ cc [ 3900 I 3600 3300 3000 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 V [V] CC XMEGA D3 [DATASHEET] 360 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33.6.1.3 Power-down Mode Supply Current Figure 33-367.Power-down Mode Supply Current vs. V CC All functions disabled 18 105 °C 16 14 12 A] 10 µ c [ 8 c I 6 4 85 °C 2 25 °C 0 -40 °C 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V [V] CC Figure 33-368.Power-down Mode Supply Current vs. V CC Watchdog and sampled BOD enabled 16 105 °C 14 12 10 A] c [µ 8 Ic 6 85 °C 4 2 25 °C -40 °C 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V [V] CC XMEGA D3 [DATASHEET] 361 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-369.Power-down Mode Supply Current vs. Temperature Watchdog and sampled BOD enabled and running from internal ULP oscillator 14 3.0 V 2.7 V 12 2.2 V 1.8 V 10 A] 8 µ cc [ 6 I 4 2 0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] 33.6.2 I/O Pin Characteristics 33.6.2.1 Pull-up Figure 33-370.I/O Pin Pull-up Resistor Current vs. Input Voltage V = 1.8V CC CC 80 70 60 50 A] µ [ 40 N PI I 30 20 -40 °C 25 °C 10 85 °C 105 °C 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 V [V] PIN XMEGA D3 [DATASHEET] 362 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-371.I/O Pin Pull-up Resistor Current vs. Input Voltage V = 3.0V CC 140 120 100 A] 80 µ [ N PI 60 I 40 -40 °C 25 °C 20 85 °C 105 °C 0 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 V [V] PIN Figure 33-372.I/O Pin Pull-up Resistor Current vs. Input Voltage V = 3.3V CC 140 120 100 ° A] 80 µ [ N PI 60 I 40 -40 °C 25 °°C 20 85 °C 105 °C 0 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 V [V] PIN XMEGA D3 [DATASHEET] 363 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33.6.2.2 Output Voltage vs. Sink/Source Current Figure 33-373.I/O Pin Output Voltage vs. Source Current V = 1.8V CC 1.8 1.6 1.4 -40 °C 1.2 V] 1.0 [N 25 °C 105 °C PI 0.8 V 0.6 0.4 85 °C 0.2 0.0 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 I [mA] PIN Figure 33-374.I/O Pin Output Voltage vs. Source Current V = 3.0V CC 3.0 2.7 2.4 2.1 1.8 V] -40 °C [ 1.5 N PI V 1.2 25 °C 105 °C 0.9 0.6 85 °C 0.3 0.0 -16 -14 -12 -10 -8 -6 -4 -2 0 IPIN [mA] XMEGA D3 [DATASHEET] 364 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-375.I/O Pin Output Voltage vs. Source Current V = 3.3V CC 3.3 3.0 2.7 2.4 2.1 -40 °C V] 1.8 [ N 1.5 VPI 25 °C 1.2 0.9 0.6 85 °C 0.3 105 °C 0.0 -16 -14 -12 -10 -8 -6 -4 -2 0 I [mA] PIN Figure 33-376.I/O Pin Output Voltage vs. Sink Current V = 1.8V CC 1.8 105 °C 1.6 1.4 85 °C 1.2 V] 1.0 [ N VPI 0.8 25 °C 0.6 -40 °C 0.4 0.2 0.0 0 1 2 3 4 5 6 7 8 9 I [mA] PIN XMEGA D3 [DATASHEET] 365 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-377.I/O Pin Output Voltage vs. Sink Current V = 3.0V CC 1.0 105 °C 0.9 85 °C 0.8 25 °C 0.7 -40 °C 0.6 V] [N 0.5 PI V 0.4 0.3 0.2 0.1 0.0 0 2 4 6 8 10 12 14 16 I [mA] PIN Figure 33-378.I/O Pin Output Voltage vs. Sink Current V = 3.3V CC 1.4 105 °C 1.2 85 °C 1.0 25 °C V] 0.8 -40 °C N [ PI 0.6 V 0.4 0.2 0.0 0 2 4 6 8 10 12 14 16 18 20 IPIN [mA] XMEGA D3 [DATASHEET] 366 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33.6.2.3 Thresholds and Hysteresis Figure 33-379.I/O Pin Input Threshold Voltage vs. V CC V I/O pin read as “1” IH 1.8 -40 °C 1.7 25 °C 85 °C 1.6 105 °C 1.5 V] 1.4 [ d hol 1.3 es Vthr 1.2 1.1 1.0 0.9 0.8 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V [V] CC Figure 33-380.I/O Pin Input Threshold Voltage vs. V CC VIL I/O pin read as “0” ,p 1.70 1.55 105 °C 85 °C 1.40 25 °C V] 1.25 -40 °C [ d hol 1.10 es hr Vt 0.95 0.80 0.65 0.50 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V [V] CC XMEGA D3 [DATASHEET] 367 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-381.I/O Pin Input Hysteresis vs. V CC 0.40 0.37 0.34 V] 0.31 [ d hol 0.28 es hr Vt 0.25 -40 °C 0.22 25 °C 0.19 85 °C 105 °C 0.16 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V [V] CC 33.6.3 ADC Characteristics Figure 33-382.INL Error vs. External V REF T = 25C, V = 3.6V, external reference CC 1.6 1.4 1.2 Single-ended unsigned mode B] 1.0 S L L[ 0.8 N I 0.6 Differential mode 0.4 Single -ended signed mode 0.2 0.0 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 VREF [V] XMEGA D3 [DATASHEET] 368 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-383.INL Error vs. Sample Rate T = 25°C, V = 3.6V, V = 3.0V external CC REF 0.70 0.65 Single-ended unsigned mode 0.60 0.55 B] S 0.50 Differential mode L L[ N 0.45 I 0.40 0.35 Single-ended signed mode 0.30 0.25 50 100 150 200 250 300 ADC sample rate [ksps] Figure 33-384.INL Error vs. Input Code 1.25 1.00 0.75 0.50 ] B 0.25 S L L[ 0.00 N I -0.25 -0.50 -0.75 -1.00 -1.25 0 512 1024 1536 2048 2560 3072 3584 4096 ADC input code XMEGA D3 [DATASHEET] 369 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-385.DNL Error vs. External V REF T = 25C, V = 3.6V, external reference CC 0.70 0.65 0.60 Single-ended unsigned mode 0.55 B] S 0.50 L L [ 0.45 N D 0.40 Differential mode 0.35 0.30 Single-ended signed mode 0.25 0.20 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 VREF [V] Figure 33-386.DNL Error vs. Sample Rate T = 25C, V = 3.6V, V = 3.0V external CC REF 0.60 0.55 Single-ended unsigned mode 0.50 B] 0.45 S L L [ 0.40 N D Differential mode 0.35 0.30 Single-ended signed mode 0.25 0.20 50 100 150 200 250 300 ADC sample rate [ksps] XMEGA D3 [DATASHEET] 370 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-387.DNL Error vs. Input Code 1 0.8 ] 0.6 B S L 0.4 [ L N 0.2 D 0 -0.2 -0.4 -0.6 0 512 1024 1536 2048 2560 3072 3584 4096 ADC input code Figure 33-388.Gain Error vs. V REF T = 25C, V = 3.6V, ADC sample rate = 300ksps CC -5 -6 ] -7 V Differential mode m -8 [ r o -9 r er Single-ended signed mode n -10 ai G -11 -12 -13 Single-ended unsigned mode -14 -15 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 VREF [V] XMEGA D3 [DATASHEET] 371 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-389.Gain Error vs. V CC T = 25C, V = external 1.0V, ADC sample rate = 300ksps REF -2 -3 ] V -4 m [ Differential mode r -5 o r Single-ended signed r e mode n -6 ai G Single-ended unsigned mode -7 -8 -9 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] Figure 33-390.Offset Error vs. V REF T = 25C, V = 3.6V, ADC sample rate = 300ksps CC 9.4 9.2 9.0 V] 8.8 m r [ 8.6 Differential mode rro 8.4 e et 8.2 Offs 8.0 7.8 7.6 7.4 7.2 7.0 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 VREF [V] XMEGA D3 [DATASHEET] 372 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-391.Gain Error vs. Temperature V = 3.0V, V = external 2.0V CC REF 0 -2 Single-ended signed mode -4 V] m or [ -6 err Differential mode n -8 ai G -10 Single-ended unsigned mode -12 -14 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] Figure 33-392.Offset Error vs. V CC T = 25C, V = external 1.0V, ADC sample rate = 300ksps REF 8.00 7.00 ] V m 6.00 [ r 5.00 o r Differential mode r e 4.00 et s Off 3.00 2.00 1.00 0.00 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC [V] XMEGA D3 [DATASHEET] 373 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33.6.4 Analog Comparator Characteristics Figure 33-393.Analog Comparator Hysteresis vs. V CC Small hysteresis 19 105°C 18 85°C 17 16 25°C mV]15 V[HYST14 -40°C 13 12 11 10 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC[V] Figure 33-394.Analog Comparator Hysteresis vs. V CC Large hysteresis 36 105°C 34 85°C 32 30 25°C mV]28 V[HYST26 -40°C 24 22 20 18 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VCC[V] XMEGA D3 [DATASHEET] 374 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-395.Analog Comparator Current Source vs. Calibration Value V = 3.0V CC 7.0 6.5 A] 6.0 µ [E C UR 5.5 O S T N E RR 5.0 U C I 4.5 -40 °C 25 °C 4.0 85 °C 105 °C 3.5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CURRCALIBA[3..0] Figure 33-396.Voltage Scaler INL vs. SCALEFAC T = 25C, V = 3.0V CC 0.44 25°C 0.41 0.38 ] B 0.35 S L L [ 0.32 N I 0.29 0.26 0.23 0.2 0 5 10 15 20 25 30 35 40 45 50 55 60 65 SCALEFAC XMEGA D3 [DATASHEET] 375 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33.6.5 Internal 1.0V Reference Characteristics Figure 33-397.ADC Internal 1.0V Reference vs. Temperature 1.007 1.006 1.005 V] e [ 1.004 g a 1.003 olt V 1.002 p 1.6 V a 1.001 g d n 1.000 2.7 V a B 3.6 V 0.999 0.998 0.997 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 T [°C] 33.6.6 BOD Characteristics Figure 33-398.BOD Thresholds vs. Temperature BOD level = 1.6V 1.68 1.67 1.66 1.65 T [V] 1.64 O B 1.63 V 1.62 1.61 1.60 1.59 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] XMEGA D3 [DATASHEET] 376 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-399.BOD Thresholds vs. Temperature BOD level = 3.0V 3.16 3.14 3.12 3.10 V] T [ 3.08 O B V 3.06 3.04 3.02 3.00 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] 33.6.7 External Reset Characteristics Figure 33-400.Minimum Reset Pin Pulse Width vs. V CC 136 128 120 s] 112 n [ T RS 104 t 105 °C 96 85 °C 88 25 °C -40 °C 80 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V [V] CC XMEGA D3 [DATASHEET] 377 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-401.Reset Pin Pull-up Resistor Current vs. Reset Pin Voltage V = 1.8V CC 80 70 60 50 A] µ [T 40 E S E IR 30 20 -40 °C 25 °C 10 85 °C 105°C 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 V [V] RESET Figure 33-402.Reset Pin Pull-up Resistor Current vs. Reset Pin Voltage V = 3.0V CC 140 120 100 A] 80 µ [ T E ES 60 R I 40 -40 °C 25 °C 20 85 °C 105°C 0 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 V [V] RESET XMEGA D3 [DATASHEET] 378 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-403.Reset Pin Pull-up Resistor Current vs. Reset Pin Voltage V = 3.3V CC 144 126 108 90 A] µ [T 72 E S E IR 54 36 -40 °C 25 °C 18 85 °C 105°C 0 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 3.3 V [V] RESET Figure 33-404.Reset Pin Input Threshold Voltage vs. V CC V - Reset pin read as “1” IH 1.8 105 °C 85 °C 1.6 25 °C -40 °C 1.4 V] [ D 1.2 OL H S E 1.0 R H T V 0.8 0.6 0.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V [V] CC XMEGA D3 [DATASHEET] 379 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33.6.8 Oscillator Characteristics 33.6.8.1 Ultra Low-Power Internal Oscillator Figure 33-405.Ultra Low-Power Internal Oscillator Frequency vs. Temperature 35.5 35.0 34.5 z] 34.0 H y [k 33.5 nc 33.0 e u eq 32.5 3.6 V Fr 32.0 3.3 V 3.0 V 31.5 2.7 V 2.0 V 31.0 1.8 V 1.6 V 30.5 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] 33.6.8.2 32.768kHz Internal Oscillator Figure 33-406.32.768kHz Internal Oscillator Frequency vs. Temperature 32.90 1.6 V 32.85 1.8 V 2.2 V 32.80 2.7 V z] 3.0 V kH 32.75 3.3 V y [ 3.6 V c 32.70 n e u q 32.65 e Fr 32.60 32.55 32.50 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] XMEGA D3 [DATASHEET] 380 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-407.32.768kHz Internal Oscillator Frequency vs. Calibration Value V = 3.0V, T = 25°C CC 53 3.0 V 50 47 ] z H 44 k [ y 41 c n e 38 u q e 35 r F 32 29 26 23 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 RC32KCAL[7..0] 33.6.8.3 2MHz Internal Oscillator Figure 33-408.2MHz Internal Oscillator Frequency vs. Temperature DFLL disabled 2.20 2.18 2.16 2.14 Hz] 2.12 M 2.10 y [ c 2.08 n ue 2.06 q e 2.04 3.3V Fr 2.02 3.0V 2.7V 2.00 2.2V 1.98 1.8V 1.96 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] XMEGA D3 [DATASHEET] 381 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-409.2MHz Internal Oscillator Frequency vs. Temperature DFLL enabled, from the 32.768kHz internal oscillator 2.010 2.008 1.8V 2.006 2.2V 2.004 2.7V z] 2.002 3.0V H 3.3V M 2.000 y [ nc 1.998 e qu 1.996 e Fr 1.994 1.992 1.990 1.988 1.986 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] Figure 33-410.2MHz Internal Oscillator Frequency vs. CALA Calibration Value V = 3V CC 2.6 -40 °C 2.5 2.4 25 °C Hz] 2.3 M 85 °C y [ 2.2 105 °C c n e 2.1 u q e 2.0 Fr 1.9 1.8 1.7 0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 CALA XMEGA D3 [DATASHEET] 382 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33.6.8.4 32MHz Internal Oscillator Figure 33-411.32MHz Internal Oscillator Frequency vs. Temperature DFLL disabled 36.5 36.0 35.5 35.0 Hz] 34.5 M cy [ 34.0 n e 33.5 u q Fre 33.0 3.3V 32.5 3.0V 2.7V 32.0 2.2V 31.5 1.8V 31.0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] Figure 33-412.32MHz Internal Oscillator Frequency vs. Temperature DFLL enabled, from the 32.768kHz internal oscillator 32.15 1.8V 32.10 2.2V 32.05 2.7V Hz] 32.00 3.0V M 3.3V ncy [ 31.95 e u q e 31.90 Fr 31.85 31.80 31.75 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] XMEGA D3 [DATASHEET] 383 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 33-413.32MHz Internal Oscillator CALA Calibration Step Size V = 3.0V CC 0.35 0.33 0.31 0.29 %] 0.27 e [ p siz 0.25 Ste 0.23 -40°C 0.21 0.19 25°C 0.17 85°C 105°C 0.15 0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 CALA Figure 33-414.32MHz Internal Oscillator Frequency vs. CALB Calibration Value V = 3.0V CC 80 74 -40 °C 25 °C 68 85 °C z] 62 105 °C H M 56 y [ c 50 n e u 44 q e Fr 38 32 26 20 0 7 14 21 28 35 42 49 56 63 DFLLRC2MCALB XMEGA D3 [DATASHEET] 384 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33.6.8.5 32MHz Internal Oscillator Calibrated to 48MHz Figure 33-415.48MHz Internal Oscillator Frequency vs. Temperature DFLL disabled 55 54 53 z] 52 H M h [ 51 c n e 50 u q Fre 49 3.3V 3.0V 48 2.7V 47 2.2V 1.8V 46 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] Figure 33-416.48MHz Internal Oscillator Frequency vs. Temperature DFLL enabled, from the 32.768kHz internal oscillator 48.3 48.2 Hz] 48.1 1.8V 2.2V 23..70VV M 3.3V y [ 48.0 c n ue 47.9 q e Fr 47.8 47.7 47.6 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 Temperature [°C] XMEGA D3 [DATASHEET] 385 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33.6.9 Two-Wire Interface Characteristics Figure 33-417.SDA Hold Time vs. Temperature 500 450 3 400 350 s] 2 n 300 e [ m 250 d ti 200 ol H 150 100 50 1 0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 33-418.SDA Hold Time vs. Supply Voltage 500 450 3 400 350 s] 2 n 300 e [ m 250 old ti 200 H 150 100 50 1 0 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 V [V] CC XMEGA D3 [DATASHEET] 386 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

33.6.10 PDI Characteristics Figure 33-419.Maximum PDI Frequency vs. V CC 36 -40°C 31 25°C 85°C z] 26 H M [X MA 21 f 16 11 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 V [V] CC XMEGA D3 [DATASHEET] 387 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

34. Errata 34.1 Atmel ATxmega32D3 34.1.1 Rev. I  AC system status flags are only valid if AC-system is enabled  Sampled BOD in Active mode will cause noise when bandgap is used as reference  Temperature sensor not calibrated 1. AC system status flags are only valid if AC-system is enabled The status flags for the ac-output are updated even though the AC is not enabled which is invalid. Also, it is not possible to clear the AC interrupt flags without enabling either of the Analog comparators. Problem fix/workaround Software should clear the AC system flags once, after enabling the AC system before using the AC system status flags. 2. Sampled BOD in Active mode will cause noise when bandgap is used as reference Using the BOD in sampled mode when the device is running in Active or Idle mode will add noise on the bandgap reference for ADC, DAC, and Analog Comparator. Problem fix/workaround If the bandgap is used as reference for either the ADC, DAC and Analog Comparator, the BOD must not be set in sampled mode. 3. Temperature sensor not calibrated Temperature sensor factory calibration not implemented. Problem fix/workaround None. 34.1.2 Rev A - H Not sampled. XMEGA D3 [DATASHEET] 388 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

34.2 Atmel ATxmega64D3 34.2.1 Rev. I  AC system status flags are only valid if AC-system is enabled  Sampled BOD in Active mode will cause noise when bandgap is used as reference  Temperature sensor not calibrated 1. AC system status flags are only valid if AC-system is enabled The status flags for the ac-output are updated even though the AC is not enabled which is invalid. Also, it is not possible to clear the AC interrupt flags without enabling either of the Analog comparators. Problem fix/workaround Software should clear the AC system flags once, after enabling the AC system before using the AC system status flags. 2. Sampled BOD in Active mode will cause noise when bandgap is used as reference Using the BOD in sampled mode when the device is running in Active or Idle mode will add noise on the bandgap reference for ADC, DAC, and Analog Comparator. Problem fix/workaround If the bandgap is used as reference for either the ADC, DAC and Analog Comparator, the BOD must not be set in sampled mode. 3. Temperature sensor not calibrated Temperature sensor factory calibration not implemented. Problem fix/workaround None. 34.2.2 Rev. H Not sampled. 34.2.3 Rev. G Not sampled. 34.2.4 Rev. F Not sampled. XMEGA D3 [DATASHEET] 389 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

34.2.5 Rev. E  Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously  V voltage scaler for AC is non-linear CC  ADC gain stage cannot be used for single conversion  ADC has increased INL error for some operating conditions  ADC gain stage output range is limited to 2.4V  ADC Event on compare match non-functional  ADC propagation delay is not correct when 8× – 64× gain is used  Bandgap measurement with the ADC is non-functional when V is below 2.7V CC  Accuracy lost on first three samples after switching input to ADC gain stage  Configuration of PGM and CWCM not as described in the XMEGA D Manual  PWM is not restarted properly after a fault in cycle-by-cycle mode  BOD will be enabled at any reset  EEPROM page buffer always written when NVM DATA0 is written  Pending full asynchronous pin change interrupts will not wake the device  Pin configuration does not affect Analog Comparator Output  NMI Flag for Crystal Oscillator Failure automatically cleared  RTC Counter value not correctly read after sleep  Pending asynchronous RTC-interrupts will not wake up device  TWI Transmit collision flag not cleared on repeated start  Clearing TWI Stop Interrupt Flag may lock the bus  TWI START condition at bus timeout will cause transaction to be dropped  TWI Data Interrupt Flag (DIF) erroneously read as set  WDR instruction inside closed window will not issue reset  Non available functions and options  Sampled BOD in Active mode will cause noise when bandgap is used as reference  Temperature sensor not calibrated  Disabling of the USART transmitter does not automatically set the TxD pin direction to input. 1. Bandgap voltage input for the ACs cannot be changed when used for both ACs simultaneously If the Bandgap voltage is selected as input for one Analog Comparator (AC) and then selected/deselected as input for another AC, the first comparator will be affected for up to 1µs and could potentially give a wrong comparison result. Problem fix/workaround If the Bandgap is required for both ACs simultaneously, configure the input selection for both ACs before enabling any of them. 2. V voltage scaler for AC is non-linear CC The 6-bit V voltage scaler in the Analog Comparators is non-linear. CC XMEGA D3 [DATASHEET] 390 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 34-1. Analog Comparator Voltage Scaler vs. Scalefac T = 25°C 3.5 3.3 V 3 2.7 V 2.5 V] 2 [E 1.8 V AL C S 1.5 V 1 0.5 0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 SCALEFAC Problem fix/workaround Use external voltage input for the analog comparator if accurate voltage levels are needed. 3. ADC gain stage cannot be used for single conversion The ADC gain stage will not output correct result for single conversion that is triggered and started from soft- ware or event system. Problem fix/workaround When the gain stage is used, the ADC must be set in free running mode for correct results. 4. ADC has increased INL error for some operating conditions Some ADC configurations or operating condition will result in increased INL error. In signed mode INL is increased to: 6LSB for sample rates above 130ksps, and up to 8LSB for 200ksps sample rate. 6LSB for reference voltage below 1.1V when V is above 3.0V. CC 20LSB for ambient temperature below 0°C and reference voltage below 1.3V. In unsigned mode, the INL error cannot be guaranteed, and this mode should not be used. Problem fix/workaround None, avoid using the ADC in the above configurations in order to prevent increased INL error. Use the ADC in signed mode also for single ended measurements. 5. ADC gain stage output range is limited to 2.4V The amplified output of the ADC gain stage will never go above 2.4V, hence the differential input will only give correct output when below 2.4V/gain. For the available gain settings, this gives a differential input range of: XMEGA D3 [DATASHEET] 391 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

— 1× gain: 2.4 V — 2× gain: 1.2 V — 4× gain: 0.6 V — 8× gain: 300 mV — 16× gain: 150 mV — 32× gain: 75 mV — 64× gain: 38 mV Problem fix/workaround Keep the amplified voltage output from the ADC gain stage below 2.4V in order to get a correct result, or keep ADC voltage reference below 2.4V. 6. ADC Event on compare match non-functional ADC signalling event will be given at every conversion complete even if Interrupt mode (INTMODE) is set to BELOW or ABOVE. Problem fix/workaround Enable and use interrupt on compare match when using the compare function. 7. ADC propagation delay is not correct when 8× – 64× gain is used The propagation delay will increase by only one ADC clock cycle for all gain settings. Problem fix/workaround None. 8. Bandgap measurement with the ADC is non-functional when V is below 2.7V CC The ADC can not be used to do bandgap measurements when V is below 2.7V. CC Problem fix/workaround None. 9. Accuracy lost on first three samples after switching input to ADC gain stage Due to memory effect in the ADC gain stage, the first three samples after changing input channel must be disregarded to achieve 12-bit accuracy. Problem fix/workaround Run three ADC conversions and discard these results after changing input channels to ADC gain stage. 10. Configuration of PGM and CWCM not as described in XMEGA D Manual Enabling Common Waveform Channel Mode will enable Pattern generation mode (PGM), but not Common Waveform Channel Mode. Enabling Pattern Generation Mode (PGM) and not Common Waveform Channel Mode (CWCM) will enable both Pattern Generation Mode and Common Waveform Channel Mode. XMEGA D3 [DATASHEET] 392 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Problem fix/workaround Table 34-1. Configure PWM and CWCM According to this Table: PGM CWCM Description 0 0 PGM and CWCM disabled 0 1 PGM enabled 1 0 PGM and CWCM enabled 1 1 PGM enabled 11. PWM is not restarted properly after a fault in cycle-by-cycle mode When the AWeX fault restore mode is set to cycle-by-cycle, the waveform output will not return to normal operation at first update after fault condition is no longer present. Problem fix/workaround Do a write to any AWeX I/O register to re-enable the output. 12. BOD will be enabled after any reset If any reset source goes active, the BOD will be enabled and keep the device in reset if the V voltage is CC below the programmed BOD level. During Power-On Reset, reset will not be released until V is above the CC programmed BOD level even if the BOD is disabled. Problem fix/workaround Do not set the BOD level higher than V even if the BOD is not used. CC 13. EEPROM page buffer always written when NVM DATA0 is written If the EEPROM is memory mapped, writing to NVM DATA0 will corrupt data in the EEPROM page buffer. Problem fix/workaround Before writing to NVM DATA0, for example when doing software CRC or flash page buffer write, check if EEPROM page buffer active loading flag (EELOAD) is set. Do not write NVM DATA0 when EELOAD is set. 14. Pending full asynchronous pin change interrupts will not wake the device Any full asynchronous pin-change Interrupt from pin 2, on any port, that is pending when the sleep instruction is executed, will be ignored until the device is woken from another source or the source triggers again. This applies when entering all sleep modes where the System Clock is stopped. Problem fix/workaround None. 15. Pin configuration does not affect Analog Comparator output The Output/Pull and inverted pin configuration does not affect the Analog Comparator output. Problem fix/workaround None for Output/Pull configuration. For inverted I/O, configure the Analog Comparator to give an inverted result (that is, connect positive input to the negative AC input and vice versa), or use and external inverter to change polarity of Analog Comparator output. XMEGA D3 [DATASHEET] 393 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

16. NMI Flag for Crystal Oscillator Failure automatically cleared NMI flag for Crystal Oscillator Failure (XOSCFDIF) will be automatically cleared when executing the NMI interrupt handler. Problem fix/workaround This device revision has only one NMI interrupt source, so checking the interrupt source in software is not required. 17. RTC Counter value not correctly read after sleep If the RTC is set to wake up the device on RTC Overflow and bit 0 of RTC CNT is identical to bit 0 of RTC PER as the device is entering sleep, the value in the RTC count register can not be read correctly within the first prescaled RTC clock cycle after wake-up. The value read will be the same as the value in the register when entering sleep. The same applies if RTC Compare Match is used as wake-up source. Problem fix/workaround Wait at least one prescaled RTC clock cycle before reading the RTC CNT value. 18. Pending asynchronous RTC-interrupts will not wake up device Asynchronous Interrupts from the Real-Time-Counter that is pending when the sleep instruction is executed, will be ignored until the device is woken from another source or the source triggers again. Problem fix/workaround None. 19. TWI Transmit collision flag not cleared on repeated start The TWI transmit collision flag should be automatically cleared on start and repeated start, but is only cleared on start. Problem fix/workaround Clear the flag in software after address interrupt. 20. Clearing TWI Stop Interrupt Flag may lock the bus If software clears the STOP Interrupt Flag (APIF) on the same Peripheral Clock cycle as the hardware sets this flag due to a new address received, CLKHOLD is not cleared and the SCL line is not released. This will lock the bus. Problem fix/workaround Check if the bus state is IDLE. If this is the case, it is safe to clear APIF. If the bus state is not IDLE, wait for the SCL pin to be low before clearing APIF. Code: /* Only clear the interrupt flag if within a "safe zone". */ while ( /* Bus not IDLE: */ ((COMMS_TWI.MASTER.STATUS & TWI_MASTER_BUSSTATE_gm) != TWI_MASTER_BUSSTATE_IDLE_gc)) && /* SCL not held by slave: */ !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) ) { /* Ensure that the SCL line is low */ XMEGA D3 [DATASHEET] 394 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

if ( !(COMMS_PORT.IN & PIN1_bm) ) if ( !(COMMS_PORT.IN & PIN1_bm) ) break; } /* Check for an pending address match interrupt */ if ( !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) ) { /* Safely clear interrupt flag */ COMMS_TWI.SLAVE.STATUS |= (uint8_t)TWI_SLAVE_APIF_bm; } 21. TWI START condition at bus timeout will cause transaction to be dropped If Bus Timeout is enabled and a timeout occurs on the same Peripheral Clock cycle as a START is detected, the transaction will be dropped. Problem fix/workaround None. 22. TWI Data Interrupt Flag erroneously read as set When issuing the TWI slave response command CMD=0b11, it takes one Peripheral Clock cycle to clear the data interrupt flag (DIF). A read of DIF directly after issuing the command will show the DIF still set. Problem fix/workaround Add one NOP instruction before checking DIF. 23. WDR instruction inside closed window will not issue reset When a WDR instruction is execute within one ULP clock cycle after updating the window control register, the counter can be cleared without giving a system reset. Problem fix/workaround Wait at least one ULP clock cycle before executing a WDR instruction. 24. Non available functions and options The below function and options are not available. Writing to any registers or fuse to try and enable or configure these functions or options will have no effect, and will be as writing to a reserved address location.  TWIE, the TWI module on PORTE  TWI SDAHOLD option in the TWI CTRL register is one bit  CRC generator module  ADC 1/2× gain option, and this configuration option in the GAIN bits in the ADC Channel CTRL register  ADC VCC/2 reference option and this configuration option in the REFSEL bits on the ADC REFCTRL register  ADC option to use internal Gnd as negative input in differential measurements and this configuration option in the MUXNEG bits in the ADC Channel MUXCTRL register  ADC channel scan and the ADC SCAN register  ADC current limitation option, and the CURRLIMIT bits in the ADC CTRLB register  ADC impedance mode selection for the gain stage, and the IMPMODE bit in the ADC CTRLB register  Timer/Counter 2 and the SPLITMODE configuration option in the BYTEM bits in the Timer/Counter 0 CTRLE register  Analog Comparator (AC) current output option, and the AC CURRCTRL and CURRCALIB registers XMEGA D3 [DATASHEET] 395 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

 PORT remap functions with alternate pin locations for Timer/Counter output compare channels, USART0 and SPI, and the PORT REMAP register  PORT RTC clock output option and the RTCOUT bit in the PORT CLKEVOUT register  PORT remap functions with alternate pin locations for the clock and event output, and the CLKEVPIN bit in the PORT CLKEVOUT register  TOSC alternate pin locations, and TOSCSEL bit in FUSEBYTE2  Real Time Counter clock source options of external clock from TOSC1, and 32.768kHz from TOSC, and 32.768kHz from the 32.768kHz internal oscillator, and these configuration options in the RTCSRC bits in the Clock RTCTRL register  PLL divide by two option, and the PLLDIV bit in the Clock PLLCTRL register  PLL lock detection failure function and the PLLDIF and PLLFDEN bits in the Clock XOSCFAIL register  The high drive option for external crystal and the XOSCPWR bit on the Oscillator XOSCCTRL register  The option to enable sequential startup of the analog modules and the ANAINIT register in MCU Control memory Problem fix/workaround None. 25. Sampled BOD in Active mode will cause noise when bandgap is used as reference Using the BOD in sampled mode when the device is running in Active or Idle mode will add noise on the bandgap reference for ADC, DAC and Analog Comparator. Problem fix/workaround If the bandgap is used as reference for either the ADC, DAC and Analog Comparator, the BOD must not be set in sampled mode. 26. Temperature sensor not calibrated Temperature sensor factory calibration not implemented. Problem fix/workaround None. 27. Disabling of USART transmitter does not automatically set the TxD pin direction to input If the USART transmitter is idle with no frames to transmit, setting TXEN to zero will not automatically set the TxD pin direction to input. Problem fix/workaround The TxD pin direction can be set to input using the Port DIR register. Be advised that setting the Port DIR register to input will be immediate. Ongoing transmissions will be truncated. 34.2.6 Rev. D Not sampled. 34.2.7 Rev. C Not sampled. XMEGA D3 [DATASHEET] 396 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

34.2.8 Rev. B  Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously  VCC voltage scaler for AC is non-linear  ADC gain stage cannot be used for single conversion  ADC has increased INL error for some operating conditions  ADC gain stage output range is limited to 2.4V  ADC Event on compare match non-functional  ADC propagation delay is not correct when 8× – 64× gain is used  Bandgap measurement with the ADC is non-functional when VCC is below 2.7V  Accuracy lost on first three samples after switching input to ADC gain stage  Configuration of PGM and CWCM not as described in the XMEGA D Manual  PWM is not restarted properly after a fault in cycle-by-cycle mode  BOD will be enabled at any reset  EEPROM page buffer always written when NVM DATA0 is written  Pending full asynchronous pin change interrupts will not wake the device  Pin configuration does not affect Analog Comparator Output  NMI Flag for Crystal Oscillator Failure automatically cleared  Writing EEPROM or Flash while reading any of them will not work  RTC Counter value not correctly read after sleep  Pending asynchronous RTC-interrupts will not wake up device  TWI Transmit collision flag not cleared on repeated start  Clearing TWI Stop Interrupt Flag may lock the bus  TWI START condition at bus timeout will cause transaction to be dropped  TWI Data Interrupt Flag (DIF) erroneously read as set  WDR instruction inside closed window will not issue reset  Non available functions and options  Sampled BOD in Active mode will cause noise when bandgap is used as reference  Temperature sensor not calibrated  Disabling the USART transmitter does not automatically set the TxD pin direction to input 1. Bandgap voltage input for the ACs cannot be changed when used for both ACs simultaneously If the Bandgap voltage is selected as input for one Analog Comparator (AC) and then selected/deselected as input for another AC, the first comparator will be affected for up to 1µs and could potentially give a wrong comparison result. Problem fix/workaround If the Bandgap is required for both ACs simultaneously, configure the input selection for both ACs before enabling any of them. 2. V voltage scaler for AC is non-linear CC The 6-bit V voltage scaler in the Analog Comparators is non-linear. CC XMEGA D3 [DATASHEET] 397 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 34-2. Analog Comparator Voltage Scaler vs. Scalefac T = 25°C 3.5 3.3 V 3 2.7 V 2.5 V] 2 [E 1.8 V AL C S 1.5 V 1 0.5 0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 SCALEFAC Problem fix/workaround Use external voltage input for the analog comparator if accurate voltage levels are needed. 3. ADC gain stage cannot be used for single conversion The ADC gain stage will not output correct result for single conversion that is triggered and started from soft- ware or event system. Problem fix/workaround When the gain stage is used, the ADC must be set in free running mode for correct results. 4. ADC has increased INL error for some operating conditions Some ADC configurations or operating condition will result in increased INL error. In signed mode INL is increased to: 6LSB for sample rates above 130ksps, and up to 8LSB for 200ksps sample rate. 6LSB for reference voltage below 1.1V when V is above 3.0V. CC 20LSB for ambient temperature below 0°C and reference voltage below 1.3V. In unsigned mode, the INL error cannot be guaranteed, and this mode should not be used. Problem fix/workaround None, avoid using the ADC in the above configurations in order to prevent increased INL error. Use the ADC in signed mode also for single ended measurements. 5. ADC gain stage output range is limited to 2.4V The amplified output of the ADC gain stage will never go above 2.4V, hence the differential input will only give correct output when below 2.4V/gain. For the available gain settings, this gives a differential input range of: XMEGA D3 [DATASHEET] 398 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

— 1× gain: 2.4 V — 2× gain: 1.2 V — 4× gain: 0.6 V — 8× gain: 300 mV — 16× gain: 150 mV — 32× gain: 75 mV — 64× gain: 38 mV Problem fix/workaround Keep the amplified voltage output from the ADC gain stage below 2.4V in order to get a correct result, or keep ADC voltage reference below 2.4V. 6. ADC Event on compare match non-functional ADC signalling event will be given at every conversion complete even if Interrupt mode (INTMODE) is set to BELOW or ABOVE. Problem fix/workaround Enable and use interrupt on compare match when using the compare function. 7. ADC propagation delay is not correct when 8× – 64× gain is used The propagation delay will increase by only one ADC clock cycle for all gain settings. Problem fix/workaround None. 8. Bandgap measurement with the ADC is non-functional when V is below 2.7V CC The ADC can not be used to do bandgap measurements when V is below 2.7V. CC Problem fix/workaround None. 9. Accuracy lost on first three samples after switching input to ADC gain stage Due to memory effect in the ADC gain stage, the first three samples after changing input channel must be disregarded to achieve 12-bit accuracy. Problem fix/workaround Run three ADC conversions and discard these results after changing input channels to ADC gain stage. 10. Configuration of PGM and CWCM not as described in XMEGA D Manual Enabling Common Waveform Channel Mode will enable Pattern generation mode (PGM), but not Common Waveform Channel Mode. Enabling Pattern Generation Mode (PGM) and not Common Waveform Channel Mode (CWCM) will enable both Pattern Generation Mode and Common Waveform Channel Mode. XMEGA D3 [DATASHEET] 399 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Problem fix/workaround Table 34-2. Configure PWM and CWCM According to this Table: PGM CWCM Description 0 0 PGM and CWCM disabled 0 1 PGM enabled 1 0 PGM and CWCM enabled 1 1 PGM enabled 11. PWM is not restarted properly after a fault in cycle-by-cycle mode When the AWeX fault restore mode is set to cycle-by-cycle, the waveform output will not return to normal operation at first update after fault condition is no longer present. Problem fix/workaround Do a write to any AWeX I/O register to re-enable the output. 12. BOD will be enabled after any reset If any reset source goes active, the BOD will be enabled and keep the device in reset if the V voltage is CC below the programmed BOD level. During Power-On Reset, reset will not be released until V is above the CC programmed BOD level even if the BOD is disabled. Problem fix/workaround Do not set the BOD level higher than V even if the BOD is not used. CC 13. EEPROM page buffer always written when NVM DATA0 is written If the EEPROM is memory mapped, writing to NVM DATA0 will corrupt data in the EEPROM page buffer. Problem fix/workaround Before writing to NVM DATA0, for example when doing software CRC or flash page buffer write, check if EEPROM page buffer active loading flag (EELOAD) is set. Do not write NVM DATA0 when EELOAD is set. 14. Pending full asynchronous pin change interrupts will not wake the device Any full asynchronous pin-change Interrupt from pin 2, on any port, that is pending when the sleep instruction is executed, will be ignored until the device is woken from another source or the source triggers again. This applies when entering all sleep modes where the System Clock is stopped. Problem fix/workaround None. 15. Pin configuration does not affect Analog Comparator output The Output/Pull and inverted pin configuration does not affect the Analog Comparator output. Problem fix/workaround None for Output/Pull configuration. For inverted I/O, configure the Analog Comparator to give an inverted result (that is, connect positive input to the negative AC input and vice versa), or use and external inverter to change polarity of Analog Comparator output. XMEGA D3 [DATASHEET] 400 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

16. NMI Flag for Crystal Oscillator Failure automatically cleared NMI flag for Crystal Oscillator Failure (XOSCFDIF) will be automatically cleared when executing the NMI interrupt handler. Problem fix/workaround This device revision has only one NMI interrupt source, so checking the interrupt source in software is not required. 17. Writing EEPROM or Flash while reading any of them will not work The EEPROM and Flash cannot be written while reading EEPROM or Flash, or while executing code in Active mode. Problem fix/workaround Enter IDLE sleep mode within 2.5µs (five 2MHz clock cycles and 80 32MHz clock cycles) after starting an EEPROM or flash write operation. Wake-up source must either be EEPROM ready or NVM ready interrupt. Alternatively set up a Timer/Counter to give an overflow interrupt 7ms after the erase or write operation has started, or 13ms after atomic erase-and-write operation has started, and then enter IDLE sleep mode. 18. RTC Counter value not correctly read after sleep If the RTC is set to wake up the device on RTC Overflow and bit 0 of RTC CNT is identical to bit 0 of RTC PER as the device is entering sleep, the value in the RTC count register can not be read correctly within the first prescaled RTC clock cycle after wake-up. The value read will be the same as the value in the register when entering sleep. The same applies if RTC Compare Match is used as wake-up source. Problem fix/workaround Wait at least one prescaled RTC clock cycle before reading the RTC CNT value. 19. Pending asynchronous RTC-interrupts will not wake up device Asynchronous Interrupts from the Real-Time-Counter that is pending when the sleep instruction is executed, will be ignored until the device is woken from another source or the source triggers again. Problem fix/workaround None. 20. TWI Transmit collision flag not cleared on repeated start The TWI transmit collision flag should be automatically cleared on start and repeated start, but is only cleared on start. Problem fix/workaround Clear the flag in software after address interrupt. 21. Clearing TWI Stop Interrupt Flag may lock the bus If software clears the STOP Interrupt Flag (APIF) on the same Peripheral Clock cycle as the hardware sets this flag due to a new address received, CLKHOLD is not cleared and the SCL line is not released. This will lock the bus. XMEGA D3 [DATASHEET] 401 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Problem fix/workaround Check if the bus state is IDLE. If this is the case, it is safe to clear APIF. If the bus state is not IDLE, wait for the SCL pin to be low before clearing APIF. Code: /* Only clear the interrupt flag if within a "safe zone". */ while ( /* Bus not IDLE: */ ((COMMS_TWI.MASTER.STATUS & TWI_MASTER_BUSSTATE_gm) != TWI_MASTER_BUSSTATE_IDLE_gc)) && /* SCL not held by slave: */ !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) ) { /* Ensure that the SCL line is low */ if ( !(COMMS_PORT.IN & PIN1_bm) ) if ( !(COMMS_PORT.IN & PIN1_bm) ) break; } /* Check for an pending address match interrupt */ if ( !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) ) { /* Safely clear interrupt flag */ COMMS_TWI.SLAVE.STATUS |= (uint8_t)TWI_SLAVE_APIF_bm; } 22. TWI START condition at bus timeout will cause transaction to be dropped If Bus Timeout is enabled and a timeout occurs on the same Peripheral Clock cycle as a START is detected, the transaction will be dropped. Problem fix/workaround None. 23. TWI Data Interrupt Flag erroneously read as set When issuing the TWI slave response command CMD=0b11, it takes one Peripheral Clock cycle to clear the data interrupt flag (DIF). A read of DIF directly after issuing the command will show the DIF still set. Problem fix/workaround Add one NOP instruction before checking DIF. 24. WDR instruction inside closed window will not issue reset When a WDR instruction is execute within one ULP clock cycle after updating the window control register, the counter can be cleared without giving a system reset. Problem fix/workaround Wait at least one ULP clock cycle before executing a WDR instruction. 25. Non available functions and options The below function and options are not available. Writing to any registers or fuse to try and enable or config- ure these functions or options will have no effect, and will be as writing to a reserved address location.  TWIE, the TWI module on PORTE  TWI SDAHOLD option in the TWI CTRL register is one bit XMEGA D3 [DATASHEET] 402 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

 CRC generator module  ADC 1/2× gain option, and this configuration option in the GAIN bits in the ADC Channel CTRL register  ADC VCC/2 reference option and this configuration option in the REFSEL bits on the ADC REFCTRL register  ADC option to use internal Gnd as negative input in differential measurements and this configuration option in the MUXNEG bits in the ADC Channel MUXCTRL register  ADC channel scan and the ADC SCAN register  ADC current limitation option, and the CURRLIMIT bits in the ADC CTRLB register  ADC impedance mode selection for the gain stage, and the IMPMODE bit in the ADC CTRLB register  Timer/Counter 2 and the SPLITMODE configuration option in the BYTEM bits in the Timer/Counter 0 CTRLE register  Analog Comparator (AC) current output option, and the AC CURRCTRL and CURRCALIB registers  PORT remap functions with alternate pin locations for Timer/Counter output compare channels, USART0 and SPI, and the PORT REMAP register  PORT RTC clock output option and the RTCOUT bit in the PORT CLKEVOUT register  PORT remap functions with alternate pin locations for the clock and event output, and the CLKEVPIN bit in the PORT CLKEVOUT register  TOSC alternate pin locations, and TOSCSEL bit in FUSEBYTE2  Real Time Counter clock source options of external clock from TOSC1, and 32.768kHz from TOSC, and 32.768kHz from the 32.768kHz internal oscillator, and these configuration options in the RTCSRC bits in the Clock RTCTRL register  PLL divide by two option, and the PLLDIV bit in the Clock PLLCTRL register  PLL lock detection failure function and the PLLDIF and PLLFDEN bits in the Clock XOSCFAIL register  The high drive option for external crystal and the XOSCPWR bit on the Oscillator XOSCCTRL register  The option to enable sequential startup of the analog modules and the ANAINIT register in MCU Control memory Problem fix/workaround None. 26. Sampled BOD in Active mode will cause noise when bandgap is used as reference Using the BOD in sampled mode when the device is running in Active or Idle mode will add noise on the bandgap reference for ADC, DAC and Analog Comparator. Problem fix/workaround If the bandgap is used as reference for either the ADC, DAC and Analog Comparator, the BOD must not be set in sampled mode. 27. Temperature sensor not calibrated Temperature sensor factory calibration not implemented. Problem fix/workaround None. 28. Disabling of USART transmitter does not automatically set the TxD pin direction to input If the USART transmitter is idle with no frames to transmit, setting TXEN to zero will not automatically set the TxD pin direction to input. XMEGA D3 [DATASHEET] 403 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Problem fix/workaround The TxD pin direction can be set to input using the Port DIR register. Be advised that setting the Port DIR register to input will be immediate. Ongoing transmissions will be truncated. 34.2.9 Rev. A Not sampled. XMEGA D3 [DATASHEET] 404 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

34.3 Atmel ATxmega128D3 34.3.1 Rev. J  AC system status flags are only valid if AC-system is enabled  Sampled BOD in Active mode will cause noise when bandgap is used as reference  Temperature sensor not calibrated 1. AC system status flags are only valid if AC-system is enabled The status flags for the ac-output are updated even though the AC is not enabled which is invalid. Also, it is not possible to clear the AC interrupt flags without enabling either of the Analog comparators. Problem fix/workaround Software should clear the AC system flags once, after enabling the AC system before using the AC system status flags. 2. Sampled BOD in Active mode will cause noise when bandgap is used as reference Using the BOD in sampled mode when the device is running in Active or Idle mode will add noise on the bandgap reference for ADC, DAC and Analog Comparator. Problem fix/workaround If the bandgap is used as reference for either the ADC, DAC and Analog Comparator, the BOD must not be set in sampled mode. 3. Temperature sensor not calibrated Temperature sensor factory calibration not implemented. Problem fix/workaround None. 34.3.2 Rev. I Not sampled. 34.3.3 Rev. H Not sampled. 34.3.4 Rev. G Not sampled. 34.3.5 Rev. F Not sampled. XMEGA D3 [DATASHEET] 405 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

34.3.6 Rev. E  Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously  V voltage scaler for AC is non-linear CC  ADC gain stage cannot be used for single conversion  ADC has increased INL error for some operating conditions  ADC gain stage output range is limited to 2.4V  ADC Event on compare match non-functional  ADC propagation delay is not correct when 8× – 64× gain is used  Bandgap measurement with the ADC is non-functional when V is below 2.7V CC  Accuracy lost on first three samples after switching input to ADC gain stage  Configuration of PGM and CWCM not as described in the XMEGA D Manual  PWM is not restarted properly after a fault in cycle-by-cycle mode  BOD will be enabled at any reset  EEPROM page buffer always written when NVM DATA0 is written  Pending full asynchronous pin change interrupts will not wake the device  Pin configuration does not affect Analog Comparator Output  NMI Flag for Crystal Oscillator Failure automatically cleared  RTC Counter value not correctly read after sleep  Pending asynchronous RTC-interrupts will not wake up device  TWI Transmit collision flag not cleared on repeated start  Clearing TWI Stop Interrupt Flag may lock the bus  TWI START condition at bus timeout will cause transaction to be dropped  TWI Data Interrupt Flag (DIF) erroneously read as set  WDR instruction inside closed window will not issue reset  Non available functions and options  Sampled BOD in Active mode will cause noise when bandgap is used as reference  Temperature sensor not calibrated  Disabling the USART transmitter does not automatically set the TxD pin direction to input. 1. Bandgap voltage input for the ACs cannot be changed when used for both ACs simultaneously If the Bandgap voltage is selected as input for one Analog Comparator (AC) and then selected/deselected as input for another AC, the first comparator will be affected for up to 1µs and could potentially give a wrong comparison result. Problem fix/workaround If the Bandgap is required for both ACs simultaneously, configure the input selection for both ACs before enabling any of them. 2. VCC voltage scaler for AC is non-linear The 6-bit V voltage scaler in the Analog Comparators is non-linear. CC XMEGA D3 [DATASHEET] 406 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 34-3. Analog Comparator Voltage Scaler vs. Scalefac T = 25°C 3.5 3.3 V 3 2.7 V 2.5 V] 2 [E 1.8 V AL C S 1.5 V 1 0.5 0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 SCALEFAC Problem fix/workaround Use external voltage input for the analog comparator if accurate voltage levels are needed. 3. ADC gain stage cannot be used for single conversion The ADC gain stage will not output correct result for single conversion that is triggered and started from soft- ware or event system. Problem fix/workaround When the gain stage is used, the ADC must be set in free running mode for correct results. 4. ADC has increased INL error for some operating conditions Some ADC configurations or operating condition will result in increased INL error. In signed mode INL is increased to: 6LSB for sample rates above 130ksps, and up to 8LSB for 200ksps sample rate. 6LSB for reference voltage below 1.1V when V is above 3.0V. CC 20LSB for ambient temperature below 0°C and reference voltage below 1.3V. In unsigned mode, the INL error cannot be guaranteed, and this mode should not be used. Problem fix/workaround None, avoid using the ADC in the above configurations in order to prevent increased INL error. Use the ADC in signed mode also for single ended measurements. 5. ADC gain stage output range is limited to 2.4V The amplified output of the ADC gain stage will never go above 2.4V, hence the differential input will only give correct output when below 2.4V/gain. For the available gain settings, this gives a differential input range of: XMEGA D3 [DATASHEET] 407 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

— 1× gain: 2.4 V — 2× gain: 1.2 V — 4× gain: 0.6 V — 8× gain: 300 mV — 16× gain: 150 mV — 32× gain: 75 mV — 64× gain: 38 mV Problem fix/workaround Keep the amplified voltage output from the ADC gain stage below 2.4V in order to get a correct result, or keep ADC voltage reference below 2.4V. 6. ADC Event on compare match non-functional ADC signalling event will be given at every conversion complete even if Interrupt mode (INTMODE) is set to BELOW or ABOVE. Problem fix/workaround Enable and use interrupt on compare match when using the compare function. 7. ADC propagation delay is not correct when 8× – 64× gain is used The propagation delay will increase by only one ADC clock cycle for all gain settings. Problem fix/workaround None. 8. Bandgap measurement with the ADC is non-functional when V is below 2.7V CC The ADC can not be used to do bandgap measurements when V is below 2.7V. CC Problem fix/workaround None. 9. Accuracy lost on first three samples after switching input to ADC gain stage Due to memory effect in the ADC gain stage, the first three samples after changing input channel must be disregarded to achieve 12-bit accuracy. Problem fix/workaround Run three ADC conversions and discard these results after changing input channels to ADC gain stage. 10. Configuration of PGM and CWCM not as described in XMEGA D Manual Enabling Common Waveform Channel Mode will enable Pattern generation mode (PGM), but not Common Waveform Channel Mode. Enabling Pattern Generation Mode (PGM) and not Common Waveform Channel Mode (CWCM) will enable both Pattern Generation Mode and Common Waveform Channel Mode. XMEGA D3 [DATASHEET] 408 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Problem fix/workaround Table 34-3. Configure PWM and CWCM According to this Table: PGM CWCM Description 0 0 PGM and CWCM disabled 0 1 PGM enabled 1 0 PGM and CWCM enabled 1 1 PGM enabled 11. PWM is not restarted properly after a fault in cycle-by-cycle mode When the AWeX fault restore mode is set to cycle-by-cycle, the waveform output will not return to normal operation at first update after fault condition is no longer present. Problem fix/workaround Do a write to any AWeX I/O register to re-enable the output. 12. BOD will be enabled after any reset If any reset source goes active, the BOD will be enabled and keep the device in reset if the V voltage is CC below the programmed BOD level. During Power-On Reset, reset will not be released until V is above the CC programmed BOD level even if the BOD is disabled. Problem fix/workaround Do not set the BOD level higher than V even if the BOD is not used. CC 13. EEPROM page buffer always written when NVM DATA0 is written If the EEPROM is memory mapped, writing to NVM DATA0 will corrupt data in the EEPROM page buffer. Problem fix/workaround Before writing to NVM DATA0, for example when doing software CRC or flash page buffer write, check if EEPROM page buffer active loading flag (EELOAD) is set. Do not write NVM DATA0 when EELOAD is set. 14. Pending full asynchronous pin change interrupts will not wake the device Any full asynchronous pin-change Interrupt from pin 2, on any port, that is pending when the sleep instruction is executed, will be ignored until the device is woken from another source or the source triggers again. This applies when entering all sleep modes where the System Clock is stopped. Problem fix/workaround None. 15. Pin configuration does not affect Analog Comparator output The Output/Pull and inverted pin configuration does not affect the Analog Comparator output. Problem fix/workaround None for Output/Pull configuration. For inverted I/O, configure the Analog Comparator to give an inverted result (that is, connect positive input to the negative AC input and vice versa), or use and external inverter to change polarity of Analog Comparator output. XMEGA D3 [DATASHEET] 409 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

16. NMI Flag for Crystal Oscillator Failure automatically cleared NMI flag for Crystal Oscillator Failure (XOSCFDIF) will be automatically cleared when executing the NMI interrupt handler. Problem fix/workaround This device revision has only one NMI interrupt source, so checking the interrupt source in software is not required. 17. RTC Counter value not correctly read after sleep If the RTC is set to wake up the device on RTC Overflow and bit 0 of RTC CNT is identical to bit 0 of RTC PER as the device is entering sleep, the value in the RTC count register can not be read correctly within the first prescaled RTC clock cycle after wake-up. The value read will be the same as the value in the register when entering sleep. The same applies if RTC Compare Match is used as wake-up source. Problem fix/workaround Wait at least one prescaled RTC clock cycle before reading the RTC CNT value. 18. Pending asynchronous RTC-interrupts will not wake up device Asynchronous Interrupts from the Real-Time-Counter that is pending when the sleep instruction is executed, will be ignored until the device is woken from another source or the source triggers again. Problem fix/workaround None. 19. TWI Transmit collision flag not cleared on repeated start The TWI transmit collision flag should be automatically cleared on start and repeated start, but is only cleared on start. Problem fix/workaround Clear the flag in software after address interrupt. 20. Clearing TWI Stop Interrupt Flag may lock the bus If software clears the STOP Interrupt Flag (APIF) on the same Peripheral Clock cycle as the hardware sets this flag due to a new address received, CLKHOLD is not cleared and the SCL line is not released. This will lock the bus. Problem fix/workaround Check if the bus state is IDLE. If this is the case, it is safe to clear APIF. If the bus state is not IDLE, wait for the SCL pin to be low before clearing APIF. Code: /* Only clear the interrupt flag if within a "safe zone". */ while ( /* Bus not IDLE: */ ((COMMS_TWI.MASTER.STATUS & TWI_MASTER_BUSSTATE_gm) != TWI_MASTER_BUSSTATE_IDLE_gc)) && /* SCL not held by slave: */ !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) ) { /* Ensure that the SCL line is low */ XMEGA D3 [DATASHEET] 410 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

if ( !(COMMS_PORT.IN & PIN1_bm) ) if ( !(COMMS_PORT.IN & PIN1_bm) ) break; } /* Check for an pending address match interrupt */ if ( !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) ) { /* Safely clear interrupt flag */ COMMS_TWI.SLAVE.STATUS |= (uint8_t)TWI_SLAVE_APIF_bm; } 21. TWI START condition at bus timeout will cause transaction to be dropped If Bus Timeout is enabled and a timeout occurs on the same Peripheral Clock cycle as a START is detected, the transaction will be dropped. Problem fix/workaround None. 22. TWI Data Interrupt Flag erroneously read as set When issuing the TWI slave response command CMD=0b11, it takes one Peripheral Clock cycle to clear the data interrupt flag (DIF). A read of DIF directly after issuing the command will show the DIF still set. Problem fix/workaround Add one NOP instruction before checking DIF. 23. WDR instruction inside closed window will not issue reset When a WDR instruction is execute within one ULP clock cycle after updating the window control register, the counter can be cleared without giving a system reset. Problem fix/workaround Wait at least one ULP clock cycle before executing a WDR instruction. 24. Non available functions and options The below function and options are not available. Writing to any registers or fuse to try and enable or configure these functions or options will have no effect, and will be as writing to a reserved address location.  TWIE, the TWI module on PORTE  TWI SDAHOLD option in the TWI CTRL register is one bit  CRC generator module  ADC 1/2× gain option, and this configuration option in the GAIN bits in the ADC Channel CTRL register  ADC VCC/2 reference option and this configuration option in the REFSEL bits on the ADC REFCTRL register  ADC option to use internal Gnd as negative input in differential measurements and this configuration option in the MUXNEG bits in the ADC Channel MUXCTRL register  ADC channel scan and the ADC SCAN register  ADC current limitation option, and the CURRLIMIT bits in the ADC CTRLB register  ADC impedance mode selection for the gain stage, and the IMPMODE bit in the ADC CTRLB register  Timer/Counter 2 and the SPLITMODE configuration option in the BYTEM bits in the Timer/Counter 0 CTRLE register  Analog Comparator (AC) current output option, and the AC CURRCTRL and CURRCALIB registers XMEGA D3 [DATASHEET] 411 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

 PORT remap functions with alternate pin locations for Timer/Counter output compare channels, USART0 and SPI, and the PORT REMAP register  PORT RTC clock output option and the RTCOUT bit in the PORT CLKEVOUT register  PORT remap functions with alternate pin locations for the clock and event output, and the CLKEVPIN bit in the PORT CLKEVOUT register  TOSC alternate pin locations, and TOSCSEL bit in FUSEBYTE2  Real Time Counter clock source options of external clock from TOSC1, and 32.768kHz from TOSC, and 32.768kHz from the 32.768kHz internal oscillator, and these configuration options in the RTCSRC bits in the Clock RTCTRL register  PLL divide by two option, and the PLLDIV bit in the Clock PLLCTRL register  PLL lock detection failure function and the PLLDIF and PLLFDEN bits in the Clock XOSCFAIL register  The high drive option for external crystal and the XOSCPWR bit on the Oscillator XOSCCTRL register  The option to enable sequential startup of the analog modules and the ANAINIT register in MCU Control memory Problem fix/workaround None. 25. Sampled BOD in Active mode will cause noise when bandgap is used as reference Using the BOD in sampled mode when the device is running in Active or Idle mode will add noise on the bandgap reference for ADC, DAC and Analog Comparator. Problem fix/workaround If the bandgap is used as reference for either the ADC, DAC and Analog Comparator, the BOD must not be set in sampled mode. 26. Temperature sensor not calibrated Temperature sensor factory calibration not implemented. Problem fix/workaround None. 27. Disabling of USART transmitter does not automatically set the TxD pin direction to input If the USART transmitter is idle with no frames to transmit, setting TXEN to zero will not automatically set the TxD pin direction to input. Problem fix/workaround The TxD pin direction can be set to input using the Port DIR register. Be advised that setting the Port DIR register to input will be immediate. Ongoing transmissions will be truncated. 34.3.7 Rev. D Not sampled. 34.3.8 Rev. C Not sampled. XMEGA D3 [DATASHEET] 412 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

34.3.9 Rev. B  Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously  VCC voltage scaler for AC is non-linear  ADC gain stage cannot be used for single conversion  ADC has increased INL error for some operating conditions  ADC gain stage output range is limited to 2.4V  ADC Event on compare match non-functional  ADC propagation delay is not correct when 8× – 64× gain is used  Bandgap measurement with the ADC is non-functional when VCC is below 2.7V  Accuracy lost on first three samples after switching input to ADC gain stage  Configuration of PGM and CWCM not as described in the XMEGA D Manual  PWM is not restarted properly after a fault in cycle-by-cycle mode  BOD will be enabled at any reset  EEPROM page buffer always written when NVM DATA0 is written  Pending full asynchronous pin change interrupts will not wake the device  Pin configuration does not affect Analog Comparator Output  NMI Flag for Crystal Oscillator Failure automatically cleared  Writing EEPROM or Flash while reading any of them will not work  RTC Counter value not correctly read after sleep  Pending asynchronous RTC-interrupts will not wake up device  TWI Transmit collision flag not cleared on repeated start  Clearing TWI Stop Interrupt Flag may lock the bus  TWI START condition at bus timeout will cause transaction to be dropped  TWI Data Interrupt Flag (DIF) erroneously read as set  WDR instruction inside closed window will not issue reset  Non available functions and options  Sampled BOD in Active mode will cause noise when bandgap is used as reference  Temperature sensor not calibrated  Disabling the USART transmitter does not automatically set the TxD pin direction to input 1. Bandgap voltage input for the ACs cannot be changed when used for both ACs simultaneously If the Bandgap voltage is selected as input for one Analog Comparator (AC) and then selected/deselected as input for another AC, the first comparator will be affected for up to 1µs and could potentially give a wrong comparison result. Problem fix/workaround If the Bandgap is required for both ACs simultaneously, configure the input selection for both ACs before enabling any of them. 2. VCC voltage scaler for AC is non-linear The 6-bit V voltage scaler in the Analog Comparators is non-linear. CC XMEGA D3 [DATASHEET] 413 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 34-4. Analog Comparator Voltage Scaler vs. Scalefac T = 25°C 3.5 3.3 V 3 2.7 V 2.5 V] 2 [E 1.8 V AL C S 1.5 V 1 0.5 0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 SCALEFAC Problem fix/workaround Use external voltage input for the analog comparator if accurate voltage levels are needed. 3. ADC gain stage cannot be used for single conversion The ADC gain stage will not output correct result for single conversion that is triggered and started from soft- ware or event system. Problem fix/workaround When the gain stage is used, the ADC must be set in free running mode for correct results. 4. ADC has increased INL error for some operating conditions Some ADC configurations or operating condition will result in increased INL error. In signed mode INL is increased to: 6LSB for sample rates above 130ksps, and up to 8LSB for 200ksps sample rate. 6LSB for reference voltage below 1.1V when V is above 3.0V. CC 20LSB for ambient temperature below 0°C and reference voltage below 1.3V. In unsigned mode, the INL error cannot be guaranteed, and this mode should not be used. Problem fix/workaround None, avoid using the ADC in the above configurations in order to prevent increased INL error. Use the ADC in signed mode also for single ended measurements. 5. ADC gain stage output range is limited to 2.4V The amplified output of the ADC gain stage will never go above 2.4V, hence the differential input will only give correct output when below 2.4V/gain. For the available gain settings, this gives a differential input range of: XMEGA D3 [DATASHEET] 414 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

— 1× gain: 2.4 V — 2× gain: 1.2 V — 4× gain: 0.6 V — 8× gain: 300 mV — 16× gain: 150 mV — 32× gain: 75 mV — 64× gain: 38 mV Problem fix/workaround Keep the amplified voltage output from the ADC gain stage below 2.4V in order to get a correct result, or keep ADC voltage reference below 2.4V. 6. ADC Event on compare match non-functional ADC signalling event will be given at every conversion complete even if Interrupt mode (INTMODE) is set to BELOW or ABOVE. Problem fix/workaround Enable and use interrupt on compare match when using the compare function. 7. ADC propagation delay is not correct when 8× – 64× gain is used The propagation delay will increase by only one ADC clock cycle for all gain settings. Problem fix/workaround None. 8. Bandgap measurement with the ADC is non-functional when V is below 2.7V CC The ADC can not be used to do bandgap measurements when V is below 2.7V. CC Problem fix/workaround None. 9. Accuracy lost on first three samples after switching input to ADC gain stage Due to memory effect in the ADC gain stage, the first three samples after changing input channel must be disregarded to achieve 12-bit accuracy. Problem fix/workaround Run three ADC conversions and discard these results after changing input channels to ADC gain stage. 10. Configuration of PGM and CWCM not as described in XMEGA D Manual Enabling Common Waveform Channel Mode will enable Pattern generation mode (PGM), but not Common Waveform Channel Mode. Enabling Pattern Generation Mode (PGM) and not Common Waveform Channel Mode (CWCM) will enable both Pattern Generation Mode and Common Waveform Channel Mode. XMEGA D3 [DATASHEET] 415 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Problem fix/workaround Table 34-4. Configure PWM and CWCM According to this Table: PGM CWCM Description 0 0 PGM and CWCM disabled 0 1 PGM enabled 1 0 PGM and CWCM enabled 1 1 PGM enabled 11. PWM is not restarted properly after a fault in cycle-by-cycle mode When the AWeX fault restore mode is set to cycle-by-cycle, the waveform output will not return to normal operation at first update after fault condition is no longer present. Problem fix/workaround Do a write to any AWeX I/O register to re-enable the output. 12. BOD will be enabled after any reset If any reset source goes active, the BOD will be enabled and keep the device in reset if the V voltage is CC below the programmed BOD level. During Power-On Reset, reset will not be released until V is above the CC programmed BOD level even if the BOD is disabled. Problem fix/workaround Do not set the BOD level higher than V even if the BOD is not used. CC 13. EEPROM page buffer always written when NVM DATA0 is written If the EEPROM is memory mapped, writing to NVM DATA0 will corrupt data in the EEPROM page buffer. Problem fix/workaround Before writing to NVM DATA0, for example when doing software CRC or flash page buffer write, check if EEPROM page buffer active loading flag (EELOAD) is set. Do not write NVM DATA0 when EELOAD is set. 14. Pending full asynchronous pin change interrupts will not wake the device Any full asynchronous pin-change Interrupt from pin 2, on any port, that is pending when the sleep instruction is executed, will be ignored until the device is woken from another source or the source triggers again. This applies when entering all sleep modes where the System Clock is stopped. Problem fix/workaround None. 15. Pin configuration does not affect Analog Comparator output The Output/Pull and inverted pin configuration does not affect the Analog Comparator output. Problem fix/workaround None for Output/Pull configuration. For inverted I/O, configure the Analog Comparator to give an inverted result (that is, connect positive input to the negative AC input and vice versa), or use and external inverter to change polarity of Analog Comparator output. XMEGA D3 [DATASHEET] 416 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

16. NMI Flag for Crystal Oscillator Failure automatically cleared NMI flag for Crystal Oscillator Failure (XOSCFDIF) will be automatically cleared when executing the NMI interrupt handler. Problem fix/workaround This device revision has only one NMI interrupt source, so checking the interrupt source in software is not required. 17. Writing EEPROM or Flash while reading any of them will not work The EEPROM and Flash cannot be written while reading EEPROM or Flash, or while executing code in Active mode. Problem fix/workaround Enter IDLE sleep mode within 2.5µs (five 2MHz clock cycles and 80 32MHz clock cycles) after starting an EEPROM or flash write operation. Wake-up source must either be EEPROM ready or NVM ready interrupt. Alternatively set up a Timer/Counter to give an overflow interrupt 7ms after the erase or write operation has started, or 13ms after atomic erase-and-write operation has started, and then enter IDLE sleep mode. 18. RTC Counter value not correctly read after sleep If the RTC is set to wake up the device on RTC Overflow and bit 0 of RTC CNT is identical to bit 0 of RTC PER as the device is entering sleep, the value in the RTC count register can not be read correctly within the first prescaled RTC clock cycle after wake-up. The value read will be the same as the value in the register when entering sleep. The same applies if RTC Compare Match is used as wake-up source. Problem fix/workaround Wait at least one prescaled RTC clock cycle before reading the RTC CNT value. 19. Pending asynchronous RTC-interrupts will not wake up device Asynchronous Interrupts from the Real-Time-Counter that is pending when the sleep instruction is executed, will be ignored until the device is woken from another source or the source triggers again. Problem fix/workaround None. 20. TWI Transmit collision flag not cleared on repeated start The TWI transmit collision flag should be automatically cleared on start and repeated start, but is only cleared on start. Problem fix/workaround Clear the flag in software after address interrupt. 21. Clearing TWI Stop Interrupt Flag may lock the bus If software clears the STOP Interrupt Flag (APIF) on the same Peripheral Clock cycle as the hardware sets this flag due to a new address received, CLKHOLD is not cleared and the SCL line is not released. This will lock the bus. XMEGA D3 [DATASHEET] 417 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Problem fix/workaround Check if the bus state is IDLE. If this is the case, it is safe to clear APIF. If the bus state is not IDLE, wait for the SCL pin to be low before clearing APIF. Code: /* Only clear the interrupt flag if within a "safe zone". */ while ( /* Bus not IDLE: */ ((COMMS_TWI.MASTER.STATUS & TWI_MASTER_BUSSTATE_gm) != TWI_MASTER_BUSSTATE_IDLE_gc)) && /* SCL not held by slave: */ !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) ) { /* Ensure that the SCL line is low */ if ( !(COMMS_PORT.IN & PIN1_bm) ) if ( !(COMMS_PORT.IN & PIN1_bm) ) break; } /* Check for an pending address match interrupt */ if ( !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) ) { /* Safely clear interrupt flag */ COMMS_TWI.SLAVE.STATUS |= (uint8_t)TWI_SLAVE_APIF_bm; } 22. TWI START condition at bus timeout will cause transaction to be dropped If Bus Timeout is enabled and a timeout occurs on the same Peripheral Clock cycle as a START is detected, the transaction will be dropped. Problem fix/workaround None. 23. TWI Data Interrupt Flag erroneously read as set When issuing the TWI slave response command CMD=0b11, it takes one Peripheral Clock cycle to clear the data interrupt flag (DIF). A read of DIF directly after issuing the command will show the DIF still set. Problem fix/workaround Add one NOP instruction before checking DIF. 24. WDR instruction inside closed window will not issue reset When a WDR instruction is execute within one ULP clock cycle after updating the window control register, the counter can be cleared without giving a system reset. Problem fix/workaround Wait at least one ULP clock cycle before executing a WDR instruction. 25. Non available functions and options The below function and options are not available. Writing to any registers or fuse to try and enable or config- ure these functions or options will have no effect, and will be as writing to a reserved address location.  TWIE, the TWI module on PORTE  TWI SDAHOLD option in the TWI CTRL register is one bit XMEGA D3 [DATASHEET] 418 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

 CRC generator module  ADC 1/2× gain option, and this configuration option in the GAIN bits in the ADC Channel CTRL register  ADC VCC/2 reference option and this configuration option in the REFSEL bits on the ADC REFCTRL register  ADC option to use internal Gnd as negative input in differential measurements and this configuration option in the MUXNEG bits in the ADC Channel MUXCTRL register  ADC channel scan and the ADC SCAN register  ADC current limitation option, and the CURRLIMIT bits in the ADC CTRLB register  ADC impedance mode selection for the gain stage, and the IMPMODE bit in the ADC CTRLB register  Timer/Counter 2 and the SPLITMODE configuration option in the BYTEM bits in the Timer/Counter 0 CTRLE register  Analog Comparator (AC) current output option, and the AC CURRCTRL and CURRCALIB registers  PORT remap functions with alternate pin locations for Timer/Counter output compare channels, USART0 and SPI, and the PORT REMAP register  PORT RTC clock output option and the RTCOUT bit in the PORT CLKEVOUT register  PORT remap functions with alternate pin locations for the clock and event output, and the CLKEVPIN bit in the PORT CLKEVOUT register  TOSC alternate pin locations, and TOSCSEL bit in FUSEBYTE2  Real Time Counter clock source options of external clock from TOSC1, and 32.768kHz from TOSC, and 32.768kHz from the 32.768kHz internal oscillator, and these configuration options in the RTCSRC bits in the Clock RTCTRL register  PLL divide by two option, and the PLLDIV bit in the Clock PLLCTRL register  PLL lock detection failure function and the PLLDIF and PLLFDEN bits in the Clock XOSCFAIL register  The high drive option for external crystal and the XOSCPWR bit on the Oscillator XOSCCTRL register  The option to enable sequential startup of the analog modules and the ANAINIT register in MCU Control memory Problem fix/workaround None. 27. Sampled BOD in Active mode will cause noise when bandgap is used as reference Using the BOD in sampled mode when the device is running in Active or Idle mode will add noise on the bandgap reference for ADC, DAC and Analog Comparator. Problem fix/workaround If the bandgap is used as reference for either the ADC, DAC and Analog Comparator, the BOD must not be set in sampled mode. 28. Temperature sensor not calibrated Temperature sensor factory calibration not implemented. Problem fix/workaround None. 28. Disabling of USART transmitter does not automatically set the TxD pin direction to input If the USART transmitter is idle with no frames to transmit, setting TXEN to zero will not automatically set the TxD pin direction to input. XMEGA D3 [DATASHEET] 419 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Problem fix/workaround The TxD pin direction can be set to input using the Port DIR register. Be advised that setting the Port DIR register to input will be immediate. Ongoing transmissions will be truncated. 34.3.10Rev. A Not sampled. XMEGA D3 [DATASHEET] 420 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

34.4 Atmel ATxmega192D3 34.4.1 Rev. I  AC system status flags are only valid if AC-system is enabled  Sampled BOD in Active mode will cause noise when bandgap is used as reference  Temperature sensor not calibrated 1. AC system status flags are only valid if AC-system is enabled The status flags for the ac-output are updated even though the AC is not enabled which is invalid. Also, it is not possible to clear the AC interrupt flags without enabling either of the Analog comparators. Problem fix/workaround Software should clear the AC system flags once, after enabling the AC system before using the AC system status flags. 2. Sampled BOD in Active mode will cause noise when bandgap is used as reference Using the BOD in sampled mode when the device is running in Active or Idle mode will add noise on the bandgap reference for ADC, DAC and Analog Comparator. Problem fix/workaround If the bandgap is used as reference for either the ADC, DAC and Analog Comparator, the BOD must not be set in sampled mode. 3. Temperature sensor not calibrated Temperature sensor factory calibration not implemented. Problem fix/workaround None. 34.4.2 Rev. H Not sampled. 34.4.3 Rev. G Not sampled. 34.4.4 Rev. F Not sampled. XMEGA D3 [DATASHEET] 421 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

34.4.5 Rev. E  Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously  V voltage scaler for AC is non-linear CC  ADC gain stage cannot be used for single conversion  ADC has increased INL error for some operating conditions  ADC gain stage output range is limited to 2.4V  ADC Event on compare match non-functional  ADC propagation delay is not correct when 8× – 64× gain is used  Bandgap measurement with the ADC is non-functional when V is below 2.7V CC  Accuracy lost on first three samples after switching input to ADC gain stage  Configuration of PGM and CWCM not as described in the XMEGA D Manual  PWM is not restarted properly after a fault in cycle-by-cycle mode  BOD will be enabled at any reset  EEPROM page buffer always written when NVM DATA0 is written  Pending full asynchronous pin change interrupts will not wake the device  Pin configuration does not affect Analog Comparator Output  NMI Flag for Crystal Oscillator Failure automatically cleared  RTC Counter value not correctly read after sleep  Pending asynchronous RTC-interrupts will not wake up device  TWI Transmit collision flag not cleared on repeated start  Clearing TWI Stop Interrupt Flag may lock the bus  TWI START condition at bus timeout will cause transaction to be dropped  TWI Data Interrupt Flag (DIF) erroneously read as set  WDR instruction inside closed window will not issue reset  Non available functions and options  Sampled BOD in Active mode will cause noise when bandgap is used as reference  Temperature sensor not calibrated 1. Bandgap voltage input for the ACs cannot be changed when used for both ACs simultaneously If the Bandgap voltage is selected as input for one Analog Comparator (AC) and then selected/deselected as input for another AC, the first comparator will be affected for up to 1µs and could potentially give a wrong comparison result. Problem fix/workaround If the Bandgap is required for both ACs simultaneously, configure the input selection for both ACs before enabling any of them. 2. VCC voltage scaler for AC is non-linear The 6-bit VCC voltage scaler in the Analog Comparators is non-linear. XMEGA D3 [DATASHEET] 422 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 34-5. Analog Comparator Voltage Scaler vs. Scalefac T = 25°C 3.5 3.3 V 3 2.7 V 2.5 V] 2 [E 1.8 V AL C S 1.5 V 1 0.5 0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 SCALEFAC Problem fix/workaround Use external voltage input for the analog comparator if accurate voltage levels are needed. 3. ADC gain stage cannot be used for single conversion The ADC gain stage will not output correct result for single conversion that is triggered and started from soft- ware or event system. Problem fix/workaround When the gain stage is used, the ADC must be set in free running mode for correct results. 4. ADC has increased INL error for some operating conditions Some ADC configurations or operating condition will result in increased INL error. In signed mode INL is increased to: 6LSB for sample rates above 130ksps, and up to 8LSB for 200ksps sample rate. 6LSB for reference voltage below 1.1V when V is above 3.0V. CC 20LSB for ambient temperature below 0°C and reference voltage below 1.3V. In unsigned mode, the INL error cannot be guaranteed, and this mode should not be used. Problem fix/workaround None, avoid using the ADC in the above configurations in order to prevent increased INL error. Use the ADC in signed mode also for single ended measurements. 5. ADC gain stage output range is limited to 2.4V The amplified output of the ADC gain stage will never go above 2.4V, hence the differential input will only give correct output when below 2.4V/gain. For the available gain settings, this gives a differential input range of: XMEGA D3 [DATASHEET] 423 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

— 1× gain: 2.4 V — 2× gain: 1.2 V — 4× gain: 0.6 V — 8× gain: 300 mV — 16× gain: 150 mV — 32× gain: 75 mV — 64× gain: 38 mV Problem fix/workaround Keep the amplified voltage output from the ADC gain stage below 2.4V in order to get a correct result, or keep ADC voltage reference below 2.4V. 6. ADC Event on compare match non-functional ADC signalling event will be given at every conversion complete even if Interrupt mode (INTMODE) is set to BELOW or ABOVE. Problem fix/workaround Enable and use interrupt on compare match when using the compare function. 7. ADC propagation delay is not correct when 8× – 64× gain is used The propagation delay will increase by only one ADC clock cycle for all gain settings. Problem fix/workaround None. 8. Bandgap measurement with the ADC is non-functional when V is below 2.7V CC The ADC can not be used to do bandgap measurements when V is below 2.7V. CC Problem fix/workaround None. 9. Accuracy lost on first three samples after switching input to ADC gain stage Due to memory effect in the ADC gain stage, the first three samples after changing input channel must be disregarded to achieve 12-bit accuracy. Problem fix/workaround Run three ADC conversions and discard these results after changing input channels to ADC gain stage. 10. Configuration of PGM and CWCM not as described in XMEGA D Manual Enabling Common Waveform Channel Mode will enable Pattern generation mode (PGM), but not Common Waveform Channel Mode. Enabling Pattern Generation Mode (PGM) and not Common Waveform Channel Mode (CWCM) will enable both Pattern Generation Mode and Common Waveform Channel Mode. XMEGA D3 [DATASHEET] 424 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Problem fix/workaround Table 34-5. Configure PWM and CWCM According to this Table: PGM CWCM Description 0 0 PGM and CWCM disabled 0 1 PGM enabled 1 0 PGM and CWCM enabled 1 1 PGM enabled 11. PWM is not restarted properly after a fault in cycle-by-cycle mode When the AWeX fault restore mode is set to cycle-by-cycle, the waveform output will not return to normal operation at first update after fault condition is no longer present. Problem fix/workaround Do a write to any AWeX I/O register to re-enable the output. 12. BOD will be enabled after any reset If any reset source goes active, the BOD will be enabled and keep the device in reset if the V voltage is CC below the programmed BOD level. During Power-On Reset, reset will not be released until V is above the CC programmed BOD level even if the BOD is disabled. Problem fix/workaround Do not set the BOD level higher than V even if the BOD is not used. CC 13. EEPROM page buffer always written when NVM DATA0 is written If the EEPROM is memory mapped, writing to NVM DATA0 will corrupt data in the EEPROM page buffer. Problem fix/workaround Before writing to NVM DATA0, for example when doing software CRC or flash page buffer write, check if EEPROM page buffer active loading flag (EELOAD) is set. Do not write NVM DATA0 when EELOAD is set. 14. Pending full asynchronous pin change interrupts will not wake the device Any full asynchronous pin-change Interrupt from pin 2, on any port, that is pending when the sleep instruction is executed, will be ignored until the device is woken from another source or the source triggers again. This applies when entering all sleep modes where the System Clock is stopped. Problem fix/workaround None. 15. Pin configuration does not affect Analog Comparator output The Output/Pull and inverted pin configuration does not affect the Analog Comparator output. Problem fix/workaround None for Output/Pull configuration. For inverted I/O, configure the Analog Comparator to give an inverted result (that is, connect positive input to the negative AC input and vice versa), or use and external inverter to change polarity of Analog Comparator output. XMEGA D3 [DATASHEET] 425 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

16. NMI Flag for Crystal Oscillator Failure automatically cleared NMI flag for Crystal Oscillator Failure (XOSCFDIF) will be automatically cleared when executing the NMI interrupt handler. Problem fix/workaround This device revision has only one NMI interrupt source, so checking the interrupt source in software is not required. 17. RTC Counter value not correctly read after sleep If the RTC is set to wake up the device on RTC Overflow and bit 0 of RTC CNT is identical to bit 0 of RTC PER as the device is entering sleep, the value in the RTC count register can not be read correctly within the first prescaled RTC clock cycle after wake-up. The value read will be the same as the value in the register when entering sleep. The same applies if RTC Compare Match is used as wake-up source. Problem fix/workaround Wait at least one prescaled RTC clock cycle before reading the RTC CNT value. 18. Pending asynchronous RTC-interrupts will not wake up device Asynchronous Interrupts from the Real-Time-Counter that is pending when the sleep instruction is executed, will be ignored until the device is woken from another source or the source triggers again. Problem fix/workaround None. 19. TWI Transmit collision flag not cleared on repeated start The TWI transmit collision flag should be automatically cleared on start and repeated start, but is only cleared on start. Problem fix/workaround Clear the flag in software after address interrupt. 20. Clearing TWI Stop Interrupt Flag may lock the bus If software clears the STOP Interrupt Flag (APIF) on the same Peripheral Clock cycle as the hardware sets this flag due to a new address received, CLKHOLD is not cleared and the SCL line is not released. This will lock the bus. Problem fix/workaround Check if the bus state is IDLE. If this is the case, it is safe to clear APIF. If the bus state is not IDLE, wait for the SCL pin to be low before clearing APIF. Code: /* Only clear the interrupt flag if within a "safe zone". */ while ( /* Bus not IDLE: */ ((COMMS_TWI.MASTER.STATUS & TWI_MASTER_BUSSTATE_gm) != TWI_MASTER_BUSSTATE_IDLE_gc)) && /* SCL not held by slave: */ !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) ) { /* Ensure that the SCL line is low */ XMEGA D3 [DATASHEET] 426 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

if ( !(COMMS_PORT.IN & PIN1_bm) ) if ( !(COMMS_PORT.IN & PIN1_bm) ) break; } /* Check for an pending address match interrupt */ if ( !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) ) { /* Safely clear interrupt flag */ COMMS_TWI.SLAVE.STATUS |= (uint8_t)TWI_SLAVE_APIF_bm; } 21. TWI START condition at bus timeout will cause transaction to be dropped If Bus Timeout is enabled and a timeout occurs on the same Peripheral Clock cycle as a START is detected, the transaction will be dropped. Problem fix/workaround None. 22. TWI Data Interrupt Flag erroneously read as set When issuing the TWI slave response command CMD=0b11, it takes one Peripheral Clock cycle to clear the data interrupt flag (DIF). A read of DIF directly after issuing the command will show the DIF still set. Problem fix/workaround Add one NOP instruction before checking DIF. 23. WDR instruction inside closed window will not issue reset When a WDR instruction is execute within one ULP clock cycle after updating the window control register, the counter can be cleared without giving a system reset. Problem fix/workaround Wait at least one ULP clock cycle before executing a WDR instruction. 24. Non available functions and options The below function and options are not available. Writing to any registers or fuse to try and enable or configure these functions or options will have no effect, and will be as writing to a reserved address location.  TWIE, the TWI module on PORTE  TWI SDAHOLD option in the TWI CTRL register is one bit  CRC generator module  ADC 1/2× gain option, and this configuration option in the GAIN bits in the ADC Channel CTRL register  ADC VCC/2 reference option and this configuration option in the REFSEL bits on the ADC REFCTRL register  ADC option to use internal Gnd as negative input in differential measurements and this configuration option in the MUXNEG bits in the ADC Channel MUXCTRL register  ADC channel scan and the ADC SCAN register  ADC current limitation option, and the CURRLIMIT bits in the ADC CTRLB register  ADC impedance mode selection for the gain stage, and the IMPMODE bit in the ADC CTRLB register  Timer/Counter 2 and the SPLITMODE configuration option in the BYTEM bits in the Timer/Counter 0 CTRLE register  Analog Comparator (AC) current output option, and the AC CURRCTRL and CURRCALIB registers XMEGA D3 [DATASHEET] 427 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

 PORT remap functions with alternate pin locations for Timer/Counter output compare channels, USART0 and SPI, and the PORT REMAP register  PORT RTC clock output option and the RTCOUT bit in the PORT CLKEVOUT register  PORT remap functions with alternate pin locations for the clock and event output, and the CLKEVPIN bit in the PORT CLKEVOUT register  TOSC alternate pin locations, and TOSCSEL bit in FUSEBYTE2  Real Time Counter clock source options of external clock from TOSC1, and 32.768kHz from TOSC, and 32.768kHz from the 32.768kHz internal oscillator, and these configuration options in the RTCSRC bits in the Clock RTCTRL register  PLL divide by two option, and the PLLDIV bit in the Clock PLLCTRL register  PLL lock detection failure function and the PLLDIF and PLLFDEN bits in the Clock XOSCFAIL register  The high drive option for external crystal and the XOSCPWR bit on the Oscillator XOSCCTRL register  The option to enable sequential startup of the analog modules and the ANAINIT register in MCU Control memory Problem fix/workaround None. 25. Sampled BOD in Active mode will cause noise when bandgap is used as reference Using the BOD in sampled mode when the device is running in Active or Idle mode will add noise on the bandgap reference for ADC, DAC and Analog Comparator. Problem fix/workaround If the bandgap is used as reference for either the ADC, DAC and Analog Comparator, the BOD must not be set in sampled mode. 26. Temperature sensor not calibrated Temperature sensor factory calibration not implemented. Problem fix/workaround None. 34.4.6 Rev. D Not sampled. 34.4.7 Rev. C Not sampled. XMEGA D3 [DATASHEET] 428 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

34.4.8 Rev. B  Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously  VCC voltage scaler for AC is non-linear  ADC gain stage cannot be used for single conversion  ADC has increased INL error for some operating conditions  ADC gain stage output range is limited to 2.4V  ADC Event on compare match non-functional  ADC propagation delay is not correct when 8× – 64× gain is used  Bandgap measurement with the ADC is non-functional when VCC is below 2.7V  Accuracy lost on first three samples after switching input to ADC gain stage  Configuration of PGM and CWCM not as described in the XMEGA D Manual  PWM is not restarted properly after a fault in cycle-by-cycle mode  BOD will be enabled at any reset  EEPROM page buffer always written when NVM DATA0 is written  Pending full asynchronous pin change interrupts will not wake the device  Pin configuration does not affect Analog Comparator Output  NMI Flag for Crystal Oscillator Failure automatically cleared  Writing EEPROM or Flash while reading any of them will not work  RTC Counter value not correctly read after sleep  Pending asynchronous RTC-interrupts will not wake up device  TWI Transmit collision flag not cleared on repeated start  Clearing TWI Stop Interrupt Flag may lock the bus  TWI START condition at bus timeout will cause transaction to be dropped  TWI Data Interrupt Flag (DIF) erroneously read as set  WDR instruction inside closed window will not issue reset  Non available functions and options  Sampled BOD in Active mode will cause noise when bandgap is used as reference  Temperature sensor not calibrated 1. Bandgap voltage input for the ACs cannot be changed when used for both ACs simultaneously If the Bandgap voltage is selected as input for one Analog Comparator (AC) and then selected/deselected as input for another AC, the first comparator will be affected for up to 1µs and could potentially give a wrong comparison result. Problem fix/workaround If the Bandgap is required for both ACs simultaneously, configure the input selection for both ACs before enabling any of them. 2. VCC voltage scaler for AC is non-linear The 6-bit VCC voltage scaler in the Analog Comparators is non-linear. XMEGA D3 [DATASHEET] 429 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 34-6. Analog Comparator Voltage Scaler vs. Scalefac T = 25°C 3.5 3.3 V 3 2.7 V 2.5 V] 2 [E 1.8 V AL C S 1.5 V 1 0.5 0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 SCALEFAC Problem fix/workaround Use external voltage input for the analog comparator if accurate voltage levels are needed. 3. ADC gain stage cannot be used for single conversion The ADC gain stage will not output correct result for single conversion that is triggered and started from soft- ware or event system. Problem fix/workaround When the gain stage is used, the ADC must be set in free running mode for correct results. 4. ADC has increased INL error for some operating conditions Some ADC configurations or operating condition will result in increased INL error. In signed mode INL is increased to: 6LSB for sample rates above 130ksps, and up to 8LSB for 200ksps sample rate. 6LSB for reference voltage below 1.1V when V is above 3.0V. CC 20LSB for ambient temperature below 0°C and reference voltage below 1.3V. In unsigned mode, the INL error cannot be guaranteed, and this mode should not be used. Problem fix/workaround None, avoid using the ADC in the above configurations in order to prevent increased INL error. Use the ADC in signed mode also for single ended measurements. 5. ADC gain stage output range is limited to 2.4V The amplified output of the ADC gain stage will never go above 2.4V, hence the differential input will only give correct output when below 2.4V/gain. For the available gain settings, this gives a differential input range of: XMEGA D3 [DATASHEET] 430 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

— 1× gain: 2.4 V — 2× gain: 1.2 V — 4× gain: 0.6 V — 8× gain: 300 mV — 16× gain: 150 mV — 32× gain: 75 mV — 64× gain: 38 mV Problem fix/workaround Keep the amplified voltage output from the ADC gain stage below 2.4V in order to get a correct result, or keep ADC voltage reference below 2.4V. 6. ADC Event on compare match non-functional ADC signalling event will be given at every conversion complete even if Interrupt mode (INTMODE) is set to BELOW or ABOVE. Problem fix/workaround Enable and use interrupt on compare match when using the compare function. 7. ADC propagation delay is not correct when 8× – 64× gain is used The propagation delay will increase by only one ADC clock cycle for all gain settings. Problem fix/workaround None. 8. Bandgap measurement with the ADC is non-functional when V is below 2.7V CC The ADC can not be used to do bandgap measurements when V is below 2.7V. CC Problem fix/workaround None. 9. Accuracy lost on first three samples after switching input to ADC gain stage Due to memory effect in the ADC gain stage, the first three samples after changing input channel must be disregarded to achieve 12-bit accuracy. Problem fix/workaround Run three ADC conversions and discard these results after changing input channels to ADC gain stage. 10. Configuration of PGM and CWCM not as described in XMEGA D Manual Enabling Common Waveform Channel Mode will enable Pattern generation mode (PGM), but not Common Waveform Channel Mode. Enabling Pattern Generation Mode (PGM) and not Common Waveform Channel Mode (CWCM) will enable both Pattern Generation Mode and Common Waveform Channel Mode. XMEGA D3 [DATASHEET] 431 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Problem fix/workaround Table 34-6. Configure PWM and CWCM According to this Table: PGM CWCM Description 0 0 PGM and CWCM disabled 0 1 PGM enabled 1 0 PGM and CWCM enabled 1 1 PGM enabled 11. PWM is not restarted properly after a fault in cycle-by-cycle mode When the AWeX fault restore mode is set to cycle-by-cycle, the waveform output will not return to normal operation at first update after fault condition is no longer present. Problem fix/workaround Do a write to any AWeX I/O register to re-enable the output. 12. BOD will be enabled after any reset If any reset source goes active, the BOD will be enabled and keep the device in reset if the V voltage is CC below the programmed BOD level. During Power-On Reset, reset will not be released until V is above the CC programmed BOD level even if the BOD is disabled. Problem fix/workaround Do not set the BOD level higher than V even if the BOD is not used. CC 13. EEPROM page buffer always written when NVM DATA0 is written If the EEPROM is memory mapped, writing to NVM DATA0 will corrupt data in the EEPROM page buffer. Problem fix/workaround Before writing to NVM DATA0, for example when doing software CRC or flash page buffer write, check if EEPROM page buffer active loading flag (EELOAD) is set. Do not write NVM DATA0 when EELOAD is set. 14. Pending full asynchronous pin change interrupts will not wake the device Any full asynchronous pin-change Interrupt from pin 2, on any port, that is pending when the sleep instruction is executed, will be ignored until the device is woken from another source or the source triggers again. This applies when entering all sleep modes where the System Clock is stopped. Problem fix/workaround None. 15. Pin configuration does not affect Analog Comparator output The Output/Pull and inverted pin configuration does not affect the Analog Comparator output. Problem fix/workaround None for Output/Pull configuration. For inverted I/O, configure the Analog Comparator to give an inverted result (that is, connect positive input to the negative AC input and vice versa), or use and external inverter to change polarity of Analog Comparator output. XMEGA D3 [DATASHEET] 432 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

16. NMI Flag for Crystal Oscillator Failure automatically cleared NMI flag for Crystal Oscillator Failure (XOSCFDIF) will be automatically cleared when executing the NMI interrupt handler. Problem fix/workaround This device revision has only one NMI interrupt source, so checking the interrupt source in software is not required. 17. Writing EEPROM or Flash while reading any of them will not work The EEPROM and Flash cannot be written while reading EEPROM or Flash, or while executing code in Active mode. Problem fix/workaround Enter IDLE sleep mode within 2.5µs (five 2MHz clock cycles and 80 32MHz clock cycles) after starting an EEPROM or flash write operation. Wake-up source must either be EEPROM ready or NVM ready interrupt. Alternatively set up a Timer/Counter to give an overflow interrupt 7ms after the erase or write operation has started, or 13ms after atomic erase-and-write operation has started, and then enter IDLE sleep mode. 18. RTC Counter value not correctly read after sleep If the RTC is set to wake up the device on RTC Overflow and bit 0 of RTC CNT is identical to bit 0 of RTC PER as the device is entering sleep, the value in the RTC count register can not be read correctly within the first prescaled RTC clock cycle after wake-up. The value read will be the same as the value in the register when entering sleep. The same applies if RTC Compare Match is used as wake-up source. Problem fix/workaround Wait at least one prescaled RTC clock cycle before reading the RTC CNT value. 19. Pending asynchronous RTC-interrupts will not wake up device Asynchronous Interrupts from the Real-Time-Counter that is pending when the sleep instruction is executed, will be ignored until the device is woken from another source or the source triggers again. Problem fix/workaround None. 20. TWI Transmit collision flag not cleared on repeated start The TWI transmit collision flag should be automatically cleared on start and repeated start, but is only cleared on start. Problem fix/workaround Clear the flag in software after address interrupt. 21. Clearing TWI Stop Interrupt Flag may lock the bus If software clears the STOP Interrupt Flag (APIF) on the same Peripheral Clock cycle as the hardware sets this flag due to a new address received, CLKHOLD is not cleared and the SCL line is not released. This will lock the bus. XMEGA D3 [DATASHEET] 433 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Problem fix/workaround Check if the bus state is IDLE. If this is the case, it is safe to clear APIF. If the bus state is not IDLE, wait for the SCL pin to be low before clearing APIF. Code: /* Only clear the interrupt flag if within a "safe zone". */ while ( /* Bus not IDLE: */ ((COMMS_TWI.MASTER.STATUS & TWI_MASTER_BUSSTATE_gm) != TWI_MASTER_BUSSTATE_IDLE_gc)) && /* SCL not held by slave: */ !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) ) { /* Ensure that the SCL line is low */ if ( !(COMMS_PORT.IN & PIN1_bm) ) if ( !(COMMS_PORT.IN & PIN1_bm) ) break; } /* Check for an pending address match interrupt */ if ( !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) ) { /* Safely clear interrupt flag */ COMMS_TWI.SLAVE.STATUS |= (uint8_t)TWI_SLAVE_APIF_bm; } 22. TWI START condition at bus timeout will cause transaction to be dropped If Bus Timeout is enabled and a timeout occurs on the same Peripheral Clock cycle as a START is detected, the transaction will be dropped. Problem fix/workaround None. 23. TWI Data Interrupt Flag erroneously read as set When issuing the TWI slave response command CMD=0b11, it takes one Peripheral Clock cycle to clear the data interrupt flag (DIF). A read of DIF directly after issuing the command will show the DIF still set. Problem fix/workaround Add one NOP instruction before checking DIF. 24. WDR instruction inside closed window will not issue reset When a WDR instruction is execute within one ULP clock cycle after updating the window control register, the counter can be cleared without giving a system reset. Problem fix/workaround Wait at least one ULP clock cycle before executing a WDR instruction. XMEGA D3 [DATASHEET] 434 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

25. Non available functions and options The below function and options are not available. Writing to any registers or fuse to try and enable or config- ure these functions or options will have no effect, and will be as writing to a reserved address location.  TWIE, the TWI module on PORTE  TWI SDAHOLD option in the TWI CTRL register is one bit  CRC generator module  ADC 1/2× gain option, and this configuration option in the GAIN bits in the ADC Channel CTRL register  ADC VCC/2 reference option and this configuration option in the REFSEL bits on the ADC REFCTRL register  ADC option to use internal Gnd as negative input in differential measurements and this configuration option in the MUXNEG bits in the ADC Channel MUXCTRL register  ADC channel scan and the ADC SCAN register  ADC current limitation option, and the CURRLIMIT bits in the ADC CTRLB register  ADC impedance mode selection for the gain stage, and the IMPMODE bit in the ADC CTRLB register  Timer/Counter 2 and the SPLITMODE configuration option in the BYTEM bits in the Timer/Counter 0 CTRLE register  Analog Comparator (AC) current output option, and the AC CURRCTRL and CURRCALIB registers  PORT remap functions with alternate pin locations for Timer/Counter output compare channels, USART0 and SPI, and the PORT REMAP register  PORT RTC clock output option and the RTCOUT bit in the PORT CLKEVOUT register  PORT remap functions with alternate pin locations for the clock and event output, and the CLKEVPIN bit in the PORT CLKEVOUT register  TOSC alternate pin locations, and TOSCSEL bit in FUSEBYTE2  Real Time Counter clock source options of external clock from TOSC1, and 32.768kHz from TOSC, and 32.768kHz from the 32.768kHz internal oscillator, and these configuration options in the RTCSRC bits in the Clock RTCTRL register  PLL divide by two option, and the PLLDIV bit in the Clock PLLCTRL register  PLL lock detection failure function and the PLLDIF and PLLFDEN bits in the Clock XOSCFAIL register  The high drive option for external crystal and the XOSCPWR bit on the Oscillator XOSCCTRL register  The option to enable sequential startup of the analog modules and the ANAINIT register in MCU Control memory Problem fix/workaround None. 26. Sampled BOD in Active mode will cause noise when bandgap is used as reference Using the BOD in sampled mode when the device is running in Active or Idle mode will add noise on the bandgap reference for ADC, DAC and Analog Comparator. Problem fix/workaround If the bandgap is used as reference for either the ADC, DAC and Analog Comparator, the BOD must not be set in sampled mode. 27. Temperature sensor not calibrated Temperature sensor factory calibration not implemented. Problem fix/workaround None. XMEGA D3 [DATASHEET] 435 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

34.4.9 Rev. A Not sampled. XMEGA D3 [DATASHEET] 436 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

34.5 Atmel ATxmega256D3 34.5.1 Rev. I  AC system status flags are only valid if AC-system is enabled  Sampled BOD in Active mode will cause noise when bandgap is used as reference  Temperature sensor not calibrated 1. AC system status flags are only valid if AC-system is enabled The status flags for the ac-output are updated even though the AC is not enabled which is invalid. Also, it is not possible to clear the AC interrupt flags without enabling either of the Analog comparators. Problem fix/workaround Software should clear the AC system flags once, after enabling the AC system before using the AC system status flags. 2. Sampled BOD in Active mode will cause noise when bandgap is used as reference Using the BOD in sampled mode when the device is running in Active or Idle mode will add noise on the bandgap reference for ADC, DAC and Analog Comparator. Problem fix/workaround If the bandgap is used as reference for either the ADC, DAC and Analog Comparator, the BOD must not be set in sampled mode. 3. Temperature sensor not calibrated Temperature sensor factory calibration not implemented. Problem fix/workaround None. 34.5.2 Rev. H Not sampled. 34.5.3 Rev. G Not sampled. 34.5.4 Rev. F Not sampled. XMEGA D3 [DATASHEET] 437 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

34.5.5 Rev. E  Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously  V voltage scaler for AC is non-linear CC  ADC gain stage cannot be used for single conversion  ADC has increased INL error for some operating conditions  ADC gain stage output range is limited to 2.4V  ADC Event on compare match non-functional  ADC propagation delay is not correct when 8× – 64× gain is used  Bandgap measurement with the ADC is non-functional when V is below 2.7V CC  Accuracy lost on first three samples after switching input to ADC gain stage  Configuration of PGM and CWCM not as described in the XMEGA D Manual  PWM is not restarted properly after a fault in cycle-by-cycle mode  BOD will be enabled at any reset  EEPROM page buffer always written when NVM DATA0 is written  Pending full asynchronous pin change interrupts will not wake the device  Pin configuration does not affect Analog Comparator Output  NMI Flag for Crystal Oscillator Failure automatically cleared  RTC Counter value not correctly read after sleep  Pending asynchronous RTC-interrupts will not wake up device  TWI Transmit collision flag not cleared on repeated start  Clearing TWI Stop Interrupt Flag may lock the bus  TWI START condition at bus timeout will cause transaction to be dropped  TWI Data Interrupt Flag (DIF) erroneously read as set  WDR instruction inside closed window will not issue reset  Non available functions and options  Sampled BOD in Active mode will cause noise when bandgap is used as reference  Temperature sensor not calibrated  Disabling the USART transmitter does not automatically set the TxD pin direction to input 1. Bandgap voltage input for the ACs cannot be changed when used for both ACs simultaneously If the Bandgap voltage is selected as input for one Analog Comparator (AC) and then selected/deselected as input for another AC, the first comparator will be affected for up to 1µs and could potentially give a wrong comparison result. Problem fix/workaround If the Bandgap is required for both ACs simultaneously, configure the input selection for both ACs before enabling any of them. 2. V voltage scaler for AC is non-linear CC The 6-bit V voltage scaler in the Analog Comparators is non-linear. CC XMEGA D3 [DATASHEET] 438 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 34-7. Analog Comparator Voltage Scaler vs. Scalefac T = 25°C 3.5 3.3 V 3 2.7 V 2.5 V] 2 [E 1.8 V AL C S 1.5 V 1 0.5 0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 SCALEFAC Problem fix/workaround Use external voltage input for the analog comparator if accurate voltage levels are needed. 3. ADC gain stage cannot be used for single conversion The ADC gain stage will not output correct result for single conversion that is triggered and started from soft- ware or event system. Problem fix/workaround When the gain stage is used, the ADC must be set in free running mode for correct results. 4. ADC has increased INL error for some operating conditions Some ADC configurations or operating condition will result in increased INL error. In signed mode INL is increased to: 6LSB for sample rates above 130ksps, and up to 8LSB for 200ksps sample rate. 6LSB for reference voltage below 1.1V when V is above 3.0V. CC 20LSB for ambient temperature below 0°C and reference voltage below 1.3V. In unsigned mode, the INL error cannot be guaranteed, and this mode should not be used. Problem fix/workaround None, avoid using the ADC in the above configurations in order to prevent increased INL error. Use the ADC in signed mode also for single ended measurements. 5. ADC gain stage output range is limited to 2.4V The amplified output of the ADC gain stage will never go above 2.4V, hence the differential input will only give correct output when below 2.4V/gain. For the available gain settings, this gives a differential input range of: XMEGA D3 [DATASHEET] 439 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

— 1× gain: 2.4 V — 2× gain: 1.2 V — 4× gain: 0.6 V — 8× gain: 300 mV — 16× gain: 150 mV — 32× gain: 75 mV — 64× gain: 38 mV Problem fix/workaround Keep the amplified voltage output from the ADC gain stage below 2.4V in order to get a correct result, or keep ADC voltage reference below 2.4V. 6. ADC Event on compare match non-functional ADC signalling event will be given at every conversion complete even if Interrupt mode (INTMODE) is set to BELOW or ABOVE. Problem fix/workaround Enable and use interrupt on compare match when using the compare function. 7. ADC propagation delay is not correct when 8× – 64× gain is used The propagation delay will increase by only one ADC clock cycle for all gain settings. Problem fix/workaround None. 8. Bandgap measurement with the ADC is non-functional when V is below 2.7V CC The ADC can not be used to do bandgap measurements when V is below 2.7V. CC Problem fix/workaround None. 9. Accuracy lost on first three samples after switching input to ADC gain stage Due to memory effect in the ADC gain stage, the first three samples after changing input channel must be disregarded to achieve 12-bit accuracy. Problem fix/workaround Run three ADC conversions and discard these results after changing input channels to ADC gain stage. 10. Configuration of PGM and CWCM not as described in XMEGA D Manual Enabling Common Waveform Channel Mode will enable Pattern generation mode (PGM), but not Common Waveform Channel Mode. Enabling Pattern Generation Mode (PGM) and not Common Waveform Channel Mode (CWCM) will enable both Pattern Generation Mode and Common Waveform Channel Mode. XMEGA D3 [DATASHEET] 440 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Problem fix/workaround Table 34-7. Configure PWM and CWCM According to this Table: PGM CWCM Description 0 0 PGM and CWCM disabled 0 1 PGM enabled 1 0 PGM and CWCM enabled 1 1 PGM enabled 11. PWM is not restarted properly after a fault in cycle-by-cycle mode When the AWeX fault restore mode is set to cycle-by-cycle, the waveform output will not return to normal operation at first update after fault condition is no longer present. Problem fix/workaround Do a write to any AWeX I/O register to re-enable the output. 12. BOD will be enabled after any reset If any reset source goes active, the BOD will be enabled and keep the device in reset if the V voltage is CC below the programmed BOD level. During Power-On Reset, reset will not be released until V is above the CC programmed BOD level even if the BOD is disabled. Problem fix/workaround Do not set the BOD level higher than V even if the BOD is not used. CC 13. EEPROM page buffer always written when NVM DATA0 is written If the EEPROM is memory mapped, writing to NVM DATA0 will corrupt data in the EEPROM page buffer. Problem fix/workaround Before writing to NVM DATA0, for example when doing software CRC or flash page buffer write, check if EEPROM page buffer active loading flag (EELOAD) is set. Do not write NVM DATA0 when EELOAD is set. 14. Pending full asynchronous pin change interrupts will not wake the device Any full asynchronous pin-change Interrupt from pin 2, on any port, that is pending when the sleep instruction is executed, will be ignored until the device is woken from another source or the source triggers again. This applies when entering all sleep modes where the System Clock is stopped. Problem fix/workaround None. 15. Pin configuration does not affect Analog Comparator output The Output/Pull and inverted pin configuration does not affect the Analog Comparator output. Problem fix/workaround None for Output/Pull configuration. For inverted I/O, configure the Analog Comparator to give an inverted result (that is, connect positive input to the negative AC input and vice versa), or use and external inverter to change polarity of Analog Comparator output. XMEGA D3 [DATASHEET] 441 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

16. NMI Flag for Crystal Oscillator Failure automatically cleared NMI flag for Crystal Oscillator Failure (XOSCFDIF) will be automatically cleared when executing the NMI interrupt handler. Problem fix/workaround This device revision has only one NMI interrupt source, so checking the interrupt source in software is not required. 17. RTC Counter value not correctly read after sleep If the RTC is set to wake up the device on RTC Overflow and bit 0 of RTC CNT is identical to bit 0 of RTC PER as the device is entering sleep, the value in the RTC count register can not be read correctly within the first prescaled RTC clock cycle after wake-up. The value read will be the same as the value in the register when entering sleep. The same applies if RTC Compare Match is used as wake-up source. Problem fix/workaround Wait at least one prescaled RTC clock cycle before reading the RTC CNT value. 18. Pending asynchronous RTC-interrupts will not wake up device Asynchronous Interrupts from the Real-Time-Counter that is pending when the sleep instruction is executed, will be ignored until the device is woken from another source or the source triggers again. Problem fix/workaround None. 19. TWI Transmit collision flag not cleared on repeated start The TWI transmit collision flag should be automatically cleared on start and repeated start, but is only cleared on start. Problem fix/workaround Clear the flag in software after address interrupt. 20. Clearing TWI Stop Interrupt Flag may lock the bus If software clears the STOP Interrupt Flag (APIF) on the same Peripheral Clock cycle as the hardware sets this flag due to a new address received, CLKHOLD is not cleared and the SCL line is not released. This will lock the bus. Problem fix/workaround Check if the bus state is IDLE. If this is the case, it is safe to clear APIF. If the bus state is not IDLE, wait for the SCL pin to be low before clearing APIF. Code: /* Only clear the interrupt flag if within a "safe zone". */ while ( /* Bus not IDLE: */ ((COMMS_TWI.MASTER.STATUS & TWI_MASTER_BUSSTATE_gm) != TWI_MASTER_BUSSTATE_IDLE_gc)) && /* SCL not held by slave: */ !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) ) { /* Ensure that the SCL line is low */ XMEGA D3 [DATASHEET] 442 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

if ( !(COMMS_PORT.IN & PIN1_bm) ) if ( !(COMMS_PORT.IN & PIN1_bm) ) break; } /* Check for an pending address match interrupt */ if ( !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) ) { /* Safely clear interrupt flag */ COMMS_TWI.SLAVE.STATUS |= (uint8_t)TWI_SLAVE_APIF_bm; } 21. TWI START condition at bus timeout will cause transaction to be dropped If Bus Timeout is enabled and a timeout occurs on the same Peripheral Clock cycle as a START is detected, the transaction will be dropped. Problem fix/workaround None. 22. TWI Data Interrupt Flag erroneously read as set When issuing the TWI slave response command CMD=0b11, it takes one Peripheral Clock cycle to clear the data interrupt flag (DIF). A read of DIF directly after issuing the command will show the DIF still set. Problem fix/workaround Add one NOP instruction before checking DIF. 23. WDR instruction inside closed window will not issue reset When a WDR instruction is execute within one ULP clock cycle after updating the window control register, the counter can be cleared without giving a system reset. Problem fix/workaround Wait at least one ULP clock cycle before executing a WDR instruction. 24. Non available functions and options The below function and options are not available. Writing to any registers or fuse to try and enable or configure these functions or options will have no effect, and will be as writing to a reserved address location.  TWIE, the TWI module on PORTE  TWI SDAHOLD option in the TWI CTRL register is one bit  CRC generator module  ADC 1/2× gain option, and this configuration option in the GAIN bits in the ADC Channel CTRL register  ADC VCC/2 reference option and this configuration option in the REFSEL bits on the ADC REFCTRL register  ADC option to use internal Gnd as negative input in differential measurements and this configuration option in the MUXNEG bits in the ADC Channel MUXCTRL register  ADC channel scan and the ADC SCAN register  ADC current limitation option, and the CURRLIMIT bits in the ADC CTRLB register  ADC impedance mode selection for the gain stage, and the IMPMODE bit in the ADC CTRLB register  Timer/Counter 2 and the SPLITMODE configuration option in the BYTEM bits in the Timer/Counter 0 CTRLE register  Analog Comparator (AC) current output option, and the AC CURRCTRL and CURRCALIB registers XMEGA D3 [DATASHEET] 443 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

 PORT remap functions with alternate pin locations for Timer/Counter output compare channels, USART0 and SPI, and the PORT REMAP register  PORT RTC clock output option and the RTCOUT bit in the PORT CLKEVOUT register  PORT remap functions with alternate pin locations for the clock and event output, and the CLKEVPIN bit in the PORT CLKEVOUT register  TOSC alternate pin locations, and TOSCSEL bit in FUSEBYTE2  Real Time Counter clock source options of external clock from TOSC1, and 32.768kHz from TOSC, and 32.768kHz from the 32.768kHz internal oscillator, and these configuration options in the RTCSRC bits in the Clock RTCTRL register  PLL divide by two option, and the PLLDIV bit in the Clock PLLCTRL register  PLL lock detection failure function and the PLLDIF and PLLFDEN bits in the Clock XOSCFAIL register  The high drive option for external crystal and the XOSCPWR bit on the Oscillator XOSCCTRL register  The option to enable sequential startup of the analog modules and the ANAINIT register in MCU Control memory Problem fix/workaround None. 25. Sampled BOD in Active mode will cause noise when bandgap is used as reference Using the BOD in sampled mode when the device is running in Active or Idle mode will add noise on the bandgap reference for ADC, DAC and Analog Comparator. Problem fix/workaround If the bandgap is used as reference for either the ADC, DAC and Analog Comparator, the BOD must not be set in sampled mode. 26. Temperature sensor not calibrated Temperature sensor factory calibration not implemented. Problem fix/workaround None. 27. Disabling of USART transmitter does not automatically set the TxD pin direction to input If the USART transmitter is idle with no frames to transmit, setting TXEN to zero will not automatically set the TxD pin direction to input. Problem fix/workaround The TxD pin direction can be set to input using the Port DIR register. Be advised that setting the Port DIR register to input will be immediate. Ongoing transmissions will be truncated. 34.5.6 Rev. D Not sampled. 34.5.7 Rev. C Not sampled. XMEGA D3 [DATASHEET] 444 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

34.5.8 Rev. B  Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously  VCC voltage scaler for AC is non-linear  ADC gain stage cannot be used for single conversion  ADC has increased INL error for some operating conditions  ADC gain stage output range is limited to 2.4V  ADC Event on compare match non-functional  ADC propagation delay is not correct when 8× – 64× gain is used  Bandgap measurement with the ADC is non-functional when VCC is below 2.7V  Accuracy lost on first three samples after switching input to ADC gain stage  Configuration of PGM and CWCM not as described in the XMEGA D Manual  PWM is not restarted properly after a fault in cycle-by-cycle mode  BOD will be enabled at any reset  EEPROM page buffer always written when NVM DATA0 is written  Pending full asynchronous pin change interrupts will not wake the device  Pin configuration does not affect Analog Comparator Output  NMI Flag for Crystal Oscillator Failure automatically cleared  Writing EEPROM or Flash while reading any of them will not work  RTC Counter value not correctly read after sleep  Pending asynchronous RTC-interrupts will not wake up device  TWI Transmit collision flag not cleared on repeated start  Clearing TWI Stop Interrupt Flag may lock the bus  TWI START condition at bus timeout will cause transaction to be dropped  TWI Data Interrupt Flag (DIF) erroneously read as set  WDR instruction inside closed window will not issue reset  Non available functions and options  Sampled BOD in Active mode will cause noise when bandgap is used as reference  Temperature sensor not calibrated  Disabling the USART transmitter does not automatically set the TxD pin to input 1. Bandgap voltage input for the ACs cannot be changed when used for both ACs simultaneously If the Bandgap voltage is selected as input for one Analog Comparator (AC) and then selected/deselected as input for another AC, the first comparator will be affected for up to 1µs and could potentially give a wrong comparison result. Problem fix/workaround If the Bandgap is required for both ACs simultaneously, configure the input selection for both ACs before enabling any of them. 2. V voltage scaler for AC is non-linear CC The 6-bit V voltage scaler in the Analog Comparators is non-linear. CC XMEGA D3 [DATASHEET] 445 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Figure 34-8. Analog Comparator Voltage Scaler vs. Scalefac T = 25°C 3.5 3.3 V 3 2.7 V 2.5 V] 2 [E 1.8 V AL C S 1.5 V 1 0.5 0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 SCALEFAC Problem fix/workaround Use external voltage input for the analog comparator if accurate voltage levels are needed. 3. ADC gain stage cannot be used for single conversion The ADC gain stage will not output correct result for single conversion that is triggered and started from soft- ware or event system. Problem fix/workaround When the gain stage is used, the ADC must be set in free running mode for correct results. 4. ADC has increased INL error for some operating conditions Some ADC configurations or operating condition will result in increased INL error. In signed mode INL is increased to: 6LSB for sample rates above 130ksps, and up to 8LSB for 200ksps sample rate. 6LSB for reference voltage below 1.1V when V is above 3.0V. CC 20LSB for ambient temperature below 0°C and reference voltage below 1.3V. In unsigned mode, the INL error cannot be guaranteed, and this mode should not be used. Problem fix/workaround None, avoid using the ADC in the above configurations in order to prevent increased INL error. Use the ADC in signed mode also for single ended measurements. 5. ADC gain stage output range is limited to 2.4V The amplified output of the ADC gain stage will never go above 2.4V, hence the differential input will only give correct output when below 2.4V/gain. For the available gain settings, this gives a differential input range of: XMEGA D3 [DATASHEET] 446 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

— 1× gain: 2.4 V — 2× gain: 1.2 V — 4× gain: 0.6 V — 8× gain: 300 mV — 16× gain: 150 mV — 32× gain: 75 mV — 64× gain: 38 mV Problem fix/workaround Keep the amplified voltage output from the ADC gain stage below 2.4V in order to get a correct result, or keep ADC voltage reference below 2.4V. 6. ADC Event on compare match non-functional ADC signalling event will be given at every conversion complete even if Interrupt mode (INTMODE) is set to BELOW or ABOVE. Problem fix/workaround Enable and use interrupt on compare match when using the compare function. 7. ADC propagation delay is not correct when 8× – 64× gain is used The propagation delay will increase by only one ADC clock cycle for all gain settings. Problem fix/workaround None. 8. Bandgap measurement with the ADC is non-functional when V is below 2.7V CC The ADC can not be used to do bandgap measurements when V is below 2.7V. CC Problem fix/workaround None. 9. Accuracy lost on first three samples after switching input to ADC gain stage Due to memory effect in the ADC gain stage, the first three samples after changing input channel must be disregarded to achieve 12-bit accuracy. Problem fix/workaround Run three ADC conversions and discard these results after changing input channels to ADC gain stage. 10. Configuration of PGM and CWCM not as described in XMEGA D Manual Enabling Common Waveform Channel Mode will enable Pattern Generation Mode (PGM), but not Common Waveform Channel Mode. Enabling Pattern Generation Mode (PGM) and not Common Waveform Channel Mode (CWCM) will enable both Pattern Generation Mode and Common Waveform Channel Mode. XMEGA D3 [DATASHEET] 447 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Problem fix/workaround Table 34-8. Configure PWM and CWCM According to this Table: PGM CWCM Description 0 0 PGM and CWCM disabled 0 1 PGM enabled 1 0 PGM and CWCM enabled 1 1 PGM enabled 11. PWM is not restarted properly after a fault in cycle-by-cycle mode When the AWeX fault restore mode is set to cycle-by-cycle, the waveform output will not return to normal operation at first update after fault condition is no longer present. Problem fix/workaround Do a write to any AWeX I/O register to re-enable the output. 12. BOD will be enabled after any reset If any reset source goes active, the BOD will be enabled and keep the device in reset if the V voltage is CC below the programmed BOD level. During Power-On Reset, reset will not be released until V is above the CC programmed BOD level even if the BOD is disabled. Problem fix/workaround Do not set the BOD level higher than V even if the BOD is not used. CC 13. EEPROM page buffer always written when NVM DATA0 is written If the EEPROM is memory mapped, writing to NVM DATA0 will corrupt data in the EEPROM page buffer. Problem fix/workaround Before writing to NVM DATA0, for example when doing software CRC or flash page buffer write, check if EEPROM page buffer active loading flag (EELOAD) is set. Do not write NVM DATA0 when EELOAD is set. 14. Pending full asynchronous pin change interrupts will not wake the device Any full asynchronous pin-change Interrupt from pin 2, on any port, that is pending when the sleep instruction is executed, will be ignored until the device is woken from another source or the source triggers again. This applies when entering all sleep modes where the System Clock is stopped. Problem fix/workaround None. 15. Pin configuration does not affect Analog Comparator output The Output/Pull and inverted pin configuration does not affect the Analog Comparator output. Problem fix/workaround None for Output/Pull configuration. For inverted I/O, configure the Analog Comparator to give an inverted result (that is, connect positive input to the negative AC input and vice versa), or use and external inverter to change polarity of Analog Comparator output. XMEGA D3 [DATASHEET] 448 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

16. NMI Flag for Crystal Oscillator Failure automatically cleared NMI flag for Crystal Oscillator Failure (XOSCFDIF) will be automatically cleared when executing the NMI interrupt handler. Problem fix/workaround This device revision has only one NMI interrupt source, so checking the interrupt source in software is not required. 17. Writing EEPROM or Flash while reading any of them will not work The EEPROM and Flash cannot be written while reading EEPROM or Flash, or while executing code in Active mode. Problem fix/workaround Enter IDLE sleep mode within 2.5µs (five 2MHz clock cycles and 80 32MHz clock cycles) after starting an EEPROM or flash write operation. Wake-up source must either be EEPROM ready or NVM ready interrupt. Alternatively set up a Timer/Counter to give an overflow interrupt 7ms after the erase or write operation has started, or 13ms after atomic erase-and-write operation has started, and then enter IDLE sleep mode. 18. RTC Counter value not correctly read after sleep If the RTC is set to wake up the device on RTC Overflow and bit 0 of RTC CNT is identical to bit 0 of RTC PER as the device is entering sleep, the value in the RTC count register can not be read correctly within the first prescaled RTC clock cycle after wakeup. The value read will be the same as the value in the register when entering sleep. The same applies if RTC Compare Match is used as wake-up source. Problem fix/workaround Wait at least one prescaled RTC clock cycle before reading the RTC CNT value. 19. Pending asynchronous RTC-interrupts will not wake up device Asynchronous Interrupts from the Real-Time-Counter that is pending when the sleep instruction is executed, will be ignored until the device is woken from another source or the source triggers again. Problem fix/workaround None. 20. TWI Transmit collision flag not cleared on repeated start The TWI transmit collision flag should be automatically cleared on start and repeated start, but is only cleared on start. Problem fix/workaround Clear the flag in software after address interrupt. 21. Clearing TWI Stop Interrupt Flag may lock the bus If software clears the STOP Interrupt Flag (APIF) on the same Peripheral Clock cycle as the hardware sets this flag due to a new address received, CLKHOLD is not cleared and the SCL line is not released. This will lock the bus. XMEGA D3 [DATASHEET] 449 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Problem fix/workaround Check if the bus state is IDLE. If this is the case, it is safe to clear APIF. If the bus state is not IDLE, wait for the SCL pin to be low before clearing APIF. Code: /* Only clear the interrupt flag if within a "safe zone". */ while ( /* Bus not IDLE: */ ((COMMS_TWI.MASTER.STATUS & TWI_MASTER_BUSSTATE_gm) != TWI_MASTER_BUSSTATE_IDLE_gc)) && /* SCL not held by slave: */ !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) ) { /* Ensure that the SCL line is low */ if ( !(COMMS_PORT.IN & PIN1_bm) ) if ( !(COMMS_PORT.IN & PIN1_bm) ) break; } /* Check for an pending address match interrupt */ if ( !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) ) { /* Safely clear interrupt flag */ COMMS_TWI.SLAVE.STATUS |= (uint8_t)TWI_SLAVE_APIF_bm; } 22. TWI START condition at bus timeout will cause transaction to be dropped If Bus Timeout is enabled and a timeout occurs on the same Peripheral Clock cycle as a START is detected, the transaction will be dropped. Problem fix/workaround None. 23. TWI Data Interrupt Flag erroneously read as set When issuing the TWI slave response command CMD=0b11, it takes one Peripheral Clock cycle to clear the data interrupt flag (DIF). A read of DIF directly after issuing the command will show the DIF still set. Problem fix/workaround Add one NOP instruction before checking DIF. 24. WDR instruction inside closed window will not issue reset When a WDR instruction is execute within one ULP clock cycle after updating the window control register, the counter can be cleared without giving a system reset. Problem fix/workaround Wait at least one ULP clock cycle before executing a WDR instruction. XMEGA D3 [DATASHEET] 450 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

25. Non available functions and options The below function and options are not available. Writing to any registers or fuse to try and enable or config- ure these functions or options will have no effect, and will be as writing to a reserved address location.  TWIE, the TWI module on PORTE  TWI SDAHOLD option in the TWI CTRL register is one bit  CRC generator module  ADC 1/2× gain option, and this configuration option in the GAIN bits in the ADC Channel CTRL register  ADC VCC/2 reference option and this configuration option in the REFSEL bits on the ADC REFCTRL register  ADC option to use internal Gnd as negative input in differential measurements and this configuration option in the MUXNEG bits in the ADC Channel MUXCTRL register  ADC channel scan and the ADC SCAN register  ADC current limitation option, and the CURRLIMIT bits in the ADC CTRLB register  ADC impedance mode selection for the gain stage, and the IMPMODE bit in the ADC CTRLB register  Timer/Counter 2 and the SPLITMODE configuration option in the BYTEM bits in the Timer/Counter 0 CTRLE register  Analog Comparator (AC) current output option, and the AC CURRCTRL and CURRCALIB registers  PORT remap functions with alternate pin locations for Timer/Counter output compare channels, USART0 and SPI, and the PORT REMAP register  PORT RTC clock output option and the RTCOUT bit in the PORT CLKEVOUT register  PORT remap functions with alternate pin locations for the clock and event output, and the CLKEVPIN bit in the PORT CLKEVOUT register  TOSC alternate pin locations, and TOSCSEL bit in FUSEBYTE2  Real Time Counter clock source options of external clock from TOSC1, and 32.768kHz from TOSC, and 32.768kHz from the 32.768kHz internal oscillator, and these configuration options in the RTCSRC bits in the Clock RTCTRL register  PLL divide by two option, and the PLLDIV bit in the Clock PLLCTRL register  PLL lock detection failure function and the PLLDIF and PLLFDEN bits in the Clock XOSCFAIL register  The high drive option for external crystal and the XOSCPWR bit on the Oscillator XOSCCTRL register  The option to enable sequential startup of the analog modules and the ANAINIT register in MCU Control memory Problem fix/workaround None. 26. Sampled BOD in Active mode will cause noise when bandgap is used as reference Using the BOD in sampled mode when the device is running in Active or Idle mode will add noise on the bandgap reference for ADC, DAC and Analog Comparator. Problem fix/workaround If the bandgap is used as reference for either the ADC, DAC and Analog Comparator, the BOD must not be set in sampled mode. 27. Temperature sensor not calibrated Temperature sensor factory calibration not implemented. Problem fix/workaround None. XMEGA D3 [DATASHEET] 451 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

28. Disabling of USART transmitter does not automatically set the TxD pin direction to input If the USART transmitter is idle with no frames to transmit, setting TXEN to zero will not automatically set the TxD pin direction to input. Problem fix/workaround The TxD pin direction can be set to input using the Port DIR register. Be advised that setting the Port DIR register to input will be immediate. Ongoing transmissions will be truncated. 34.5.9 Rev. A Not sampled. XMEGA D3 [DATASHEET] 452 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

34.6 Atmel ATxmega384D3 34.6.1 Rev. B  Sampled BOD in Active mode will cause noise when bandgap is used as reference  Temperature sensor not calibrated 1. Sampled BOD in Active mode will cause noise when bandgap is used as reference Using the BOD in sampled mode when the device is running in Active or Idle mode will add noise on the bandgap reference for ADC, DAC and Analog Comparator. Problem fix/workaround If the bandgap is used as reference for either the ADC, DAC and Analog Comparator, the BOD must not be set in sampled mode. 2. Temperature sensor not calibrated Temperature sensor factory calibration not implemented. Problem fix/workaround None. 34.6.2 Rev. A Not sampled. XMEGA D3 [DATASHEET] 453 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

35. Datasheet revision history Note that the referring page numbers in this section are referred to this document. The referring revisions in this section are referring to the document revision. 35.1 8134Q – 10/2015 1. Updated “Ordering Information” on page 2.  All ATxmegayyD3-MT and ATxmegayyD3-MTR changed respectively to ATxmegayyD3-MN and ATxmegayyD3-MNR 35.2 8134P – 11/2014 1. Changed EEPROM value for ATxmega32D3 to 1K in Section 1. “Ordering Information” on page 2, in Figure 7-2 on page 16 and in Table 7-3 on page 18. 2. Section naming in Chapter “Typical Characteristics” has been corrected. 35.3 8134O – 09/2014 1. Updated “Ordering Information” on page 2. Added Ordering codes for the devices characterized @ 105C. 2. Updated “Electrical Characteristics” on page 63:  Updated Table 32-4 on page 65, Table 32-33 on page 84, Table 32-62 on page 103, Table 32-91 on page 122, Table 32-120 on page 141 and Table 32-149 on page 160. Added I Power-down power consumption for CC T=105C for all functions disabled and for WDT and sampled BOD enabled.  Updated,Table 32-17 on page 73, Table 32-46 on page 92, Table 32-75 on page 111, Table 32-104 on page 130, Table 32-133 on page 149, and Table 32-162 on page 168. Updated all tables to include values for T=85C and T=105C. Removed T=55C. 3. Updated “Typical Characteristics” on page 177. Added 105C characteristics. 4. Changed Vcc to AV in Section 25. “ADC – 12-bit Analog to Digital Converter” on page 45 and Section 26. “AC – CC Analog Comparator” on page 47. 5. Added ERRATA concerning disabling of the USART transmitter in Section 34.2 “Atmel ATxmega64D3” on page 389, Section 34.3 “Atmel ATxmega128D3” on page 405 and Section 34.5 “Atmel ATxmega256D3” on page 437. 35.4 8134N – 03/2014 1. Updated Table 28-2 on page 52. PORT PB1 has PIN# 7 XMEGA D3 [DATASHEET] 454 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

2. Updated Table 32-5 on page 66 and Table 32-34 on page 85: The condition for ADC updated from 200ksps to 16ksps, V = Ext. ref. REF 3. Added “ External 16MHz Crystal Oscillator and XOSC Characteristics” on page 95, 114, 133 and on page 171. 4. Updated the “Errata” on page 388:  Removed errata: “Crystal start-up time required after power-save even if crystal is source for RTC”  Added errata from Rev B and later: “Sampled BOD in Active mode will cause noise when bandgap is used as reference” 35.5 8134M – 07/2013 1. “Pinout/block Diagram” on page 5: USART0 removed from Port F. 2. Typical chara, Figure 33-156 on page 255 and Figure 33-226 on page 290: Scale on Y-axis updated from mA to µA. 35.6 8134L – 07/2013 1. Added errata section for “Atmel ATxmega32D3” on page 388 2. Errata Temperature sensor not calibrated added to: ATxmega64D3 “Rev. I” , “Rev. E” and “Rev. B” . ATxmega128D3 “Rev. J” , “Rev. E” and “Rev. B” . ATxmega192D3 “Rev. I” , “Rev. E” and “Rev. B” . ATxmega256D3 “Rev. I” , “Rev. E” and “Rev. B” . ATxmega384D3 “Rev. B” . 35.7 8134K – 05/2013 1. “Errata” is updated. 35.8 8134J – 03/2013 1. Almost all figures in Chapter “Typical Characteristics” are updated. 2. Added new Errata “Rev. G” on page 117. 3. Added new Errata “Rev. B” on page 125 and “Rev. E” on page 118. Non available functions and options. 4. Editing updates. 5. Added ATxmega32D3 and ATxmega384D3. 6. New datasheet template is added. 7. A lot of small corrections and a complete reorganization of “Electrical Characteristics” and “Typical Characteristics” . 8. Bullet “Optional Slew Rate Control” in Chapter “I/O Ports” on page 30 is removed. XMEGA D3 [DATASHEET] 455 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

The sentence “The port pins also have configurable slew rate limitation to reduce electromagnetic emission” in 9. Chapter “I/O Ports” on page 30 is removed. The sentence “The I/O pins complies with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output voltage limits reflect or exceed this specification” is added to Section 32.1.5 on page 68, 10. Section 32.2.5 on page 87, Section 32.6.5 on page 163, Section 33.5.2 on page 297 and Section 33.6.2 on page 331. 11. Figure 2-1 on page 5 is updated by changing V to V . DD CC 12. Table 7-1 on page 15 is updated. 13. Figure 7-2 on page 16 is updated. 14. Figure 14-7 on page 33 is updated. Former Table 32-24, Table 32-52, Table 32-79, Table 32-107, Table 32-135, Table 32-163 (title: “External clock”) have 15. each been replaced by two new tables, named respectively “External clock used as system clock without prescaling” and “External clock with prescaler for system clock”. In Table 32-29 on page 81, Table 32-58 on page 100, Table 32-87 on page 119, Table 32-116 on page 138, Table 16. 32-145 on page 157, and Table 32-174 on page 176 the value for the parameter “Input voltage” has been corrected. In Table 32-18 on page 73, Table 32-47 on page 92, Table 32-76 on page 111, Table 32-105 on page 130, Table 32- 17. 134 on page 149, and Table 32-163 on page 168 the parameter “Application erase” has been added. Table 32-14 on page 72, Table 32-43 on page 91, Table 32-101 on page 129, Table 32-130 on page 148 and Table 18. 32-159 on page 167 (Brownout detection characteristics) are updated. 19. Table 32-20 on page 74 and Table 32-49 on page 93 (2MHz internal oscillator characteristics) are updated. 20. Table 32-21 on page 74 and Table 32-50 on page 93 (32MHz internal oscillator characteristics) are updated. 21. Accuracy added in Table 32-109 on page 131. 22. Table 32-149 on page 160 has been corrected. 23 Table 32-167 on page 169; “Factory calibration accuracy” and “Accuracy” is added. Table 32-150 on page 161, Table 32-152 on page 163, Table 32-154 on page 164, Table 32-155 on page 165, Table 24. 32-156 on page 166, and Table 32-157 on page 166 has been updated. 25. Section 1. “Ordering Information” on page 2 is updated. 26. Former Section 31.3 “64Z3” has been removed. 27. Section 31.2 “64M” on page 62 has replaced the former Section 31.2 “64M2”. 35.9 8134I – 12/2010 1. Datasheet status changed to complete: Preliminary removed from front page. Updated all tables in the The maximum CPU clock frequency depends on VCC. As shown in Figure 32-8 on page 83 2. the frequency vs. VCC curve is linear between 1.8V<VCC<2.7V. on page 64. 3. Replaced Table 31-11 on page 67. 4. Replaced Table 31-17 on page 68 and added the figure “TOSC input capacitance” on page 78. 5. Added “Rev. E” on page 118. XMEGA D3 [DATASHEET] 456 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

6. Updated ERRATA for ADC (ADC has increased INL error for some operating conditions). 7. Updated ERRATA “Rev. B” on page 125 with twie (TWIE is not available). 8. Updated the last page by Atmel new Brand Style Guide. 35.10 8134H – 09/2010 1. Updated “Errata” on page 388. 35.11 8134G – 08/2010 1. Updated the Footnote 3 of “Ordering Information” on page 2. 2. All references to CRC removed. Updated Figure 3-1 on page 5. 3. Updated “Features” on page 30. 4. Updated “DC Characteristics” on page 61 by adding Icc for Flash/EEPROM Programming. 5. Added AV in “ADC Characteristics” on page 68. CC 6. Updated Start up time in “ADC Characteristics” on page 68. 7. Updated and fixed typo in “Errata” on page 388. 35.12 8134F – 02/2010 1. Added “PDI Speed” on page 105. 35.13 8134E – 01/2010 1. Updated the device pin-out Figure 2-1 on page 5. PDI_CLK and PDI_DATA renamed only PDI. 2. Updated “ADC – 12-bit Analog to Digital Converter” on page 45. 3. Updated Figure 25-1 on page 46. 4. Updated “Alternate Pin Function Description” on page 50. 5. Updated “Alternate Pin Functions” on page 51. 6. Updated “Timer/counter and AWEX Functions” on page 50. 7. Added Table 31-17 on page 68. 8. Added Table 31-18 on page 69. 9. Changed internal oscillator speed to “Power-on reset current consumption vs. VCC. BOD level = 3.0V, enabled in continuous mode.” on page 108. 10. Updated “Errata” on page 388. XMEGA D3 [DATASHEET] 457 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

35.14 8134D – 11/2009 1. Added Table 31-3 on page 64, Endurance and data retention. 2. Updated Table 31-10 on page 67, Input hysteresis is in V and not in mV. 3. Added “Errata” on page 388. 4. Editing updates. 35.15 8134C – 10/2009 1. Updated “Features” on page 1 with two-wire interfaces. 2. Updated “Pinout/block Diagram” on page 5. 3. Updated “Overview” on page 6. 4. Updated “XMEGA D# block diagram” on page 5. 5. Updated Table 13-1 on page 29. 6. Updated “Overview” on page 38. 7. Updated Table 28-5 on page 53. 8. Updated “Peripheral Module Address Map” on page 55. 35.16 8134B – 08/2009 1. Added The maximum CPU clock frequency depends on VCC. As shown in Figure 32-8 on page 83 the frequency vs. VCC curve is linear between 1.8V<VCC<2.7V. on page 64. 2. Added “Typical Characteristics” on page 177. 35.17 8134A – 03/2009 1. Initial revision. XMEGA D3 [DATASHEET] 458 Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

Table of Contents Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. Pinout/block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4. Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.1 Recommended Reading. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5. Capacitive Touch Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6. AVR CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.3 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.4 ALU - Arithmetic Logic Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.5 Program Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.6 Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.7 Stack and Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.8 Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7. Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.3 Flash Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.4 Fuses and Lock Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.5 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.6 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.7 I/O Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.8 Memory Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.9 Device ID and Revision. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.10 I/O Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.11 Flash and EEPROM Page Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8. Event System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9. System Clock and Clock Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 9.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 9.3 Clock Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 10. Power Management and Sleep Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 10.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 10.3 Sleep Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 XMEGA D3 [DATASHEET] i Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

11. System Control and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 11.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 11.3 Reset Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 11.4 Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 12. WDT – Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 12.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 13. Interrupts and Programmable Multilevel Interrupt Controller . . . . . . . . . . . . . . . . 28 13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 13.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 13.3 Interrupt Vectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 14. I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 14.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 14.3 Output Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 14.4 Input Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 14.5 Alternate Port Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 15. TC0/1 – 16-bit Timer/Counter Type 0 and 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 15.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 16. TC2 – Timer/Counter Type 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 16.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 17. AWeX – Advanced Waveform Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 17.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 18. Hi-Res – High Resolution Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 18.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 18.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 19. RTC – 16-bit Real-Time Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 19.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 19.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 20. TWI – Two-Wire Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 20.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 20.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 21. SPI – Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 21.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 21.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 22. USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 22.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 22.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 XMEGA D3 [DATASHEET] ii Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

23. IRCOM – IR Communication Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 23.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 23.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 24. CRC – Cyclic Redundancy Check generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 24.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 24.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 25. ADC – 12-bit Analog to Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 25.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 25.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 26. AC – Analog Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 26.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 26.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 27. Programming and Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 27.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 27.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 28. Pinout and Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 28.1 Alternate Pin Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 28.2 Alternate Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 29. Peripheral Module Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 30. Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 31. Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 31.1 64A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 31.2 64M. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 32. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 32.1 Atmel ATxmega32D3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 32.2 Atmel ATxmega64D3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 32.3 Atmel ATxmega128D3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 32.4 Atmel ATxmega192D3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 32.5 Atmel ATxmega256D3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 32.6 Atmel ATxmega384D3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 33. Typical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 33.1 Atmel ATxmega32D3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 33.2 Atmel ATxmega64D3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 33.3 Atmel ATxmega128D3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 33.4 Atmel ATxmega192D3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 33.5 Atmel ATxmega256D3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 33.6 Atmel ATxmega384D3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 34. Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 34.1 Atmel ATxmega32D3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 34.2 Atmel ATxmega64D3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 34.3 Atmel ATxmega128D3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 34.4 Atmel ATxmega192D3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 34.5 Atmel ATxmega256D3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 XMEGA D3 [DATASHEET] iii Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

34.6 Atmel ATxmega384D3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453 35. Datasheet revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454 35.1 8134Q – 10/2015 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454 35.2 8134P – 11/2014. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454 35.3 8134O – 09/2014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454 35.4 8134N – 03/2014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454 35.5 8134M – 07/2013 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455 35.6 8134L – 07/2013. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455 35.7 8134K – 05/2013. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455 35.8 8134J – 03/2013. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455 35.9 8134I – 12/2010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456 35.10 8134H – 09/2010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 35.11 8134G – 08/2010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 35.12 8134F – 02/2010. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 35.13 8134E – 01/2010. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 35.14 8134D – 11/2009 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458 35.15 8134C – 10/2009 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458 35.16 8134B – 08/2009. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458 35.17 8134A – 03/2009. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458 Table of Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .i XMEGA D3 [DATASHEET] iv Atmel-8134Q-ATxmega32D3-64D3-128D3-192D3-256D3-384D3_datasheet–10/2015

X X X X X X Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com © 2015 Atmel Corporation. / Rev.: Atmel-8134Q-AVR-ATxmega32D3-64D3-128D3-192D3-256D3-384D3-Datasheet_10/2015. Atmel®, Atmel logo and combinations thereof, AVR®, Enabling Unlimited Possibilities®, XMEGA®, QTouch®, and others are registered trademarks or trademarks of Atmel Corporation in U.S. and other countries. Other terms and product names may be trademarks of others. DISCLAIMER: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS AND PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and products descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. SAFETY-CRITICAL, MILITARY, AND AUTOMOTIVE APPLICATIONS DISCLAIMER: Atmel products are not designed for and will not be used in connection with any applications where the failure of such products would reasonably be expected to result in significant personal injury or death (“Safety-Critical Applications”) without an Atmel officer's specific written consent. Safety-Critical Applications include, without limitation, life support devices and systems, equipment or systems for the operation of nuclear facilities and weapons systems. Atmel products are not designed nor intended for use in military or aerospace applications or environments unless specifically designated by Atmel as military-grade. Atmel products are not designed nor intended for use in automotive applications unless specifically designated by Atmel as automotive-grade.

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: ATXMEGA128D3-AU ATXMEGA128D3-MH ATXMEGA192D3-MH ATXMEGA192D3-AU ATXMEGA256D3-AU ATXMEGA256D3-MH ATXMEGA64D3-AU ATXMEGA64D3-MH ATXMEGA384D3-AU ATXMEGA384D3-MH ATXMEGA128D3-AUR ATXMEGA128D3-MHR ATXMEGA192D3-AUR ATXMEGA192D3-MHR ATXMEGA256D3- AUR ATXMEGA256D3-MHR ATXMEGA64D3-AUR ATXMEGA64D3-MHR ATXMEGA32D3-AU ATXMEGA384D3- MHR ATXMEGA32D3-MH ATXMEGA32D3-AUR ATXMEGA32D3-MHR ATXMEGA256D3-ANR ATXMEGA128D3- MN ATXMEGA64D3-AN ATXMEGA256D3-AN ATXMEGA256D3-MNR ATXMEGA384D3-AN ATXMEGA32D3-ANR ATXMEGA64D3-MNR ATXMEGA256D3-MN ATXMEGA192D3-MN ATXMEGA192D3-ANR ATXMEGA64D3-MN ATXMEGA128D3-MNR ATXMEGA192D3-MNR ATXMEGA384D3-ANR ATXMEGA32D3-MN ATXMEGA128D3-ANR ATXMEGA384D3-MNR ATXMEGA384D3-MN ATXMEGA128D3-AN ATXMEGA32D3-AN ATXMEGA32D3-MNR ATXMEGA64D3-ANR ATXMEGA192D3-AN ATxmega384D3-AUR