8/16-bit Atmel XMEGA B3 Microcontroller ATxmega128B3 / ATxmega64B3 Features (cid:122) High-performance, low-power Atmel® AVR® XMEGA® 8/16-bit Microcontroller (cid:122) Nonvolatile program and data memories (cid:122) 64K - 128KBytes of in-system self-programmable flash (cid:122) 4K - 8KBytes boot section (cid:122) 2KBytes EEPROM (cid:122) 4K - 8KBytes internal SRAM (cid:122) Peripheral Features (cid:122) Two-channel DMA controller (cid:122) Four-channel event system (cid:122) Two 16-bit timer/counters (cid:122) One timer/counters with 4 output compare or input capture channels (cid:122) One timer/counter with 2 output compare or input capture channels (cid:122) High resolution extensions one timer/counter (cid:122) Advanced waveform extension (AWeX) on one timer/counter (cid:122) Split mode on two timer/counters (cid:122) One USB device interface (cid:122) USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant (cid:122) 32 Endpoints with full configuration flexibility (cid:122) One USARTs with IrDA support for one USART (cid:122) AES and DES crypto engine (cid:122) CRC-16 (CRC-CCITT) and CRC-32 (IEEE® 802.3) generator (cid:122) One two-wire interface with dual address match (I2C and SMBus compatible) (cid:122) One serial peripheral interface (SPI) (cid:122) 16-bit Real Time Counter (RTC) with separate oscillator (cid:122) Liquid Crystal Display (cid:122) Up to 4x25 segment driver (cid:122) Built in contrast control (cid:122) ASCII character mapping (cid:122) Flexible SWAP of segment and common terminals buses (cid:122) One eight-channel, 12-bit, 300 thousand SPS Analog to Digital Converters (cid:122) Two Analog Comparators with window compare function, and current source feature (cid:122) External interrupts on all General Purpose I/O pins (cid:122) Programmable watchdog timer with separate on-chip ultra low power oscillator (cid:122) QTouch® library support (cid:122) Capacitive touch buttons, sliders and wheels (cid:122) Special microcontroller features (cid:122) Power-on reset and programmable brown-out detection (cid:122) Internal and external clock options with PLL (cid:122) Programmable multilevel interrupt controller (cid:122) Five sleep modes (cid:122) Programming and debug interfaces (cid:122) JTAG (IEEE 1149.1 Compliant) interface, including boundary scan (cid:122) PDI (Program and Debug Interface) (cid:122) I/O and Packages (cid:122) 36 Programmable I/O pins (cid:122) 64-lead TQFP (cid:122) 64-pad QFN (cid:122) 64-pad DRQFN Atmel-8074E–AVR–ATxmega 128B3 - 64B3_datasheet-09/2014

(cid:122) Operating Voltage (cid:122) 1.6 – 3.6V (cid:122) Operating frequency (cid:122) 0 – 12MHz from 1.6V (cid:122) 0 – 32MHz from 2.7V 1. Ordering Information Flash EEPROM SRAM Power Ordering Code (Bytes) (Bytes) (Bytes) Speed (MHz) Supply Package(1)(2)(3) Temp ATxmega128B3-AU 128K + 8K 2K 8K 64A ATxmega128B3-AUR(4) 128K + 8K 2K 8K ATxmega128B3-MH 128K + 8K 2K 8K 32 1.6 - 3.6V 64M2 -40°C - 85°C ATxmega128B3-MHR(4) 128K + 8K 2K 8K ATxmega128B3-MCU 128K + 8K 2K 8K 64P2 ATxmega128B3-MCUR(4) 128K + 8K 2K 8K ATxmega64B3-AU 64K + 4K 2K 4K 64A ATxmega64B3-AUR(4) 64K + 4K 2K 4K 32 1.6 - 3.6V -40°C - 85°C ATxmega64B3-MH 64K + 4K 2K 4K 64M2 ATxmega64B3-MHR(4) 64K + 4K 2K 4K Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. For packaging information, see “Packaging information” on page 68. 4. Tape and Reel. Package Type 64A 64-lead, 14 x 14mm body size, 1.0mm body thickness, 0.5mm lead pitch, thin profile plastic quad flat package (TQFP) 64M2 64-pad, 9 x 9 x 1.0mm body size, 0.05mm lead pitch, 7.65 exposed pad, Quad Flat No-Lead Package (QFN) 64P2 64-pad, 7 x 7 x 1.0mm body size, 0.65mm pitch (Dual row staggered), Very Thin Quad No Lead Package (VQFN) Sawn Typical Applications XMEGA B3 [DATASHEET] 2 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

Industrial control Climate control Low power battery applications Factory automation RF and ZigBee® Power tools Building control USB connectivity HVAC Board control Sensor control Utility metering White goods Optical Medical applications XMEGA B3 [DATASHEET] 3 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

2. Pinout/Block Diagram 2.1 Pinout – TQFP/QFN Figure 2-1. Block diagram and TQFP/QFN pinout Power LCD Ground Programming,debug,test Digitalfunction Externalclock/Crystalpins Analogfunction/Oscillators GeneralPurposeI/O C D 3 2 1 0 7 6 5 4 3 2 1 0 C N 1 0 M M M M B B B B B B B B V G R R O O O O P P P P P P P P A A P P C C C C 4 3 2 0 0 9 8 7 6 5 4 3 2 1 0 9 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 PC0 1 Port B Port R 48 CAPH PPCC12 23 JTAG AC0:1 ADC AREF 4476 VCLACPDL PC3 4 EVENT ROUTING NETWORK 45 BIAS2 DATA BUS PC4 5 44 BIAS1 OSC/CLK Watchdog Power PC5 6 C TC0:1 Control TEMPREF Oscillator Supervision OM 43 VCC PC6 7 Port USSAPRIT0 RCeoaul nTtimere VREF CoSnltereopll er CoRnetrsoeltler CR 42 GND W GPNCD7 89 TWI ECvoennttr oSlylesr. CInotnetrrroulpletr OCD PInrtoegr/fDacbeg LCD P 4410 SSEEGG10 D Watchdog DMA VCC 10 ort USB Timer Controller 39 SEG2 P PD0 11 Crypto / BUS G 38 SEG3 CRC CPU Controller SE PD1 12 37 SEG4 IRCOM EEPROM FLASH SSRRAAMM PDI/RESET 13 36 SEG5 PDI 14 DATA BUS 35 SEG6 GND 15 SEG LCD Controller 34 SEG7 Port G Port M VCC 16 33 SEG8 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 G G G G G G G G G G G G G G G G E E E E E E E E E E E E E E E E S S S S S S S S S S S S S S S S 0 / 1 / 2 / 3 / 4 / 5 / 6 / 7 / 0 / 1 / 2 / 3 / 4 / 5 / 6 / 7 / G G G G G G G G M M M M M M M M P P P P P P P P P P P P P P P P Note: 1. For full details on pinout and alternate pin functions refer to “Pinout and Pin Functions” on page 55. XMEGA B3 [DATASHEET] 4 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

2.2 Pinout – DRQFN Figure 2-2. DRQFN pinout for ATxmega128B3 Top view Bottom view A34B30 A33B29 A32B28 A31B27 A30B26 A29B25 A28B24 A27B23 A26 A26B23 A27B24 A28B25 A29B26 A30B27 A31B28 A32B29 A33B30 A34 A1 A25 A25 A1 B1 B22 B22 B1 A2 A24 A24 A2 B2 B21 B21 B2 A3 A23 A23 A3 B3 B20 B20 B3 A4 A22 A22 A4 B4 B19 B19 B4 A5 A21 A21 A5 B5 B18 B18 B5 A6 A20 A20 A6 B6 B17 B17 B6 A7 A19 A19 A7 B7 B16 B16 B7 A8 A18 A18 A8 A9 B8A10 B9A11 B10A12 B11A13 B12A14 B13A15 B14A16 B15A17 A17 B15A16 B14A15 B13A14 B12A13 B11A12 B10A11 B9A10 B8A9 Table 2-1. DRQFN pinout for ATxmega128B3 Pin Function Pin Function Pin Function Pin Function A1 PC0 A9 PG0/SEG24 A18 SEG7 A26 CAPH B1 PC1 B8 VCC B16 SEG8 B23 COM0 A2 PC2 A10 PG2/SEG22 A19 SEG6 A27 COM1 B2 PC3 B9 PG1/SEG23 B17 SEG5 B24 COM2 A3 PC4 A11 PG3/SEG21 A20 SEG4 A28 COM3 B3 PC5 B10 PG4/SEG20 B18 SEG3 B25 PR0 A4 PC6 A12 PG5/SEG19 A21 SEG2 A29 PR1 B4 GND B11 PG6/SEG18 B19 SEG1 B26 AGND A5 PC7 A13 PG7/SEG17 A22 SEG0 A30 PB0 B5 PD0 B12 PM0/SEG16 B20 GND B27 AVCC A6 VCC A14 PM1/SEG15 A23 VCC A31 PB1 B6 PDI/RESET B13 PM2/SEG14 B21 BIAS1 B28 PB2 A7 PD1 A15 PM3/SEG13 A24 BIAS2 A32 PB3 B7 PDI B14 PM5/SEG11 B22 VLCD B29 PB4 A8 GND A16 PM4/SEG12 A25 CAPL A33 PB5 B15 PM7/SEG9 B30 PB7 A17 PM6/SEG10 A34 PB6 XMEGA B3 [DATASHEET] 5 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

3. Overview The Atmel® AVR® XMEGA® is a family of low power, high performance, and peripheral rich 8/16-bit microcontrollers based on the AVR enhanced RISC architecture. By executing instructions in a single clock cycle, the Atmel AVR XMEGA devices achieve CPU throughput approaching one million instructions per second (MIPS) per megahertz, allowing the system designer to optimize power consumption versus processing speed. The AVR CPU combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly connected to the arithmetic logic unit (ALU), allowing two independent registers to be accessed in a single instruction, executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs many times faster than conventional single-accumulator or CISC based microcontrollers. The Atmel AVR XMEGA B3 devices provide the following features: in-system programmable flash with read-while-write capabilities; internal EEPROM and SRAM; two-channel DMA controller, four-channel event system and programmable multilevel interrupt controller, 36 general purpose I/O lines, real-time counter (RTC); Liquid Crystal Display supporting up to 4x25 segment driver, ASCII character mapping and built-in contrast control (LCD); three flexible, 16-bit timer/counters with compare and PWM channels; one USARTs; one two-wire serial interface (TWI); one full speed USB 2.0 interface; one serial peripheral interface (SPI); AES and DES cryptographic engine; one 8-channel, 12-bit ADCs with programmable gain; four analog comparators (ACs) with window mode; programmable watchdog timer with separate internal oscillator; accurate internal oscillators with PLL and prescaler; and programmable brown-out detection. The program and debug interface (PDI), a fast, two-pin interface for programming and debugging, is available. The devices also have an IEEE std. 1149.1 compliant JTAG interface, and this can also be used for on-chip debug and programming. The ATx devices have five software selectable power saving modes. The idle mode stops the CPU while allowing the SRAM, DMA controller, event system, interrupt controller, and all peripherals to continue functioning. The power-down mode saves the SRAM and register contents, but stops the oscillators, disabling all other functions until the next TWI, USB resume, or pin-change interrupt, or reset. In power-save mode, the asynchronous real-time counter continues to run, allowing the application to maintain a timer base while the rest of the device is sleeping. In power-save mode, the LCD controller is allowed to refresh data to the panel. In standby mode, the external crystal oscillator keeps running while the rest of the device is sleeping. This allows very fast startup from the external crystal, combined with low power consumption. In extended standby mode, both the main oscillator and the asynchronous timer continue to run, and the LCD controller is allowed to refresh data to the panel. To further reduce power consumption, the peripheral clock to each individual peripheral can optionally be stopped in active mode and idle sleep mode. Atmel offers a free QTouch® library for embedding capacitive touch buttons, sliders and wheels functionality into AVR microcontrollers. The devices are manufactured using Atmel high-density, nonvolatile memory technology. The program flash memory can be reprogrammed in-system through the PDI or JTAG interfaces. A boot loader running in the device can use any interface to download the application program to the flash memory. The boot loader software in the boot flash section will continue to run while the application flash section is updated, providing true read-while-write operation. By combining an 8/16-bit RISC CPU with in-system, self-programmable flash, the Atmel XMEGA B1 is a powerful microcontroller family that provides a highly flexible and cost effective solution for many embedded applications. The atmel AVR ATx devices are supported with a full suite of program and system development tools, including C compilers, macro assemblers, program debugger/simulators, programmers, and evaluation kits. XMEGA B3 [DATASHEET] 6 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

3.1 Block Diagram Figure 3-1. XMEGA B3 Block Diagram PR[0..1] Power LCD XTAL1/ Ground Programming,debug,test TOSC1 Digitalfunction Externalclock/Crystalpins Analogfunction/Oscillators GeneralPurposeI/O XTAL2/ TOSC2 PORTR(2) Oscillator Circuits/ Clock Generation RealTime Watchdog Counter Oscillator EVENTROUTINGNETWORK DATABUS Watchdog Timer EventSystem Oscillator Controller Control Power VCC SRAM Supervision POR/BOD& DMA Sleep RESET GND Controller Controller RESET/ PDI_CLK Prog/Debug PDI BUSMatrix Controller PDI_DATA VCC/10 JTAG PORTB Int.Refs. AES Tempref OCD AREFB DES LCDPOWER[0..4] COM[0..3] CPU Interrupt LCD SEG[0..8] Controller ADCB CRC ACB SEG[16..9]/ NVMController PORTM(8) PB[0..7]/ PM[0..7] PORTB(8) JTAG SEG[24..17]/ Flash EEPROM PORTG(8) PG[0..7] DATABUS EVENTROUTINGNETWORK 0 IRCOM TCC0:1 USARTC SPIC TWIC USB PORTC(8) PORTD(2) PC[0..7] PD[0..1] XMEGA B3 [DATASHEET] 7 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

4. Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. 4.1 Recommended reading (cid:122) XMEGA B Manual (cid:122) XMEGA Application Notes This device data sheet only contains part specific information with a short description of each peripheral and module. The XMEGA B Manual describes the modules and peripherals in depth. The XMEGA application notes contain example code and show applied use of the modules and peripherals. All documentations are available from www.atmel.com/avr. 5. Capacitive touch sensing The Atmel QTouch® library provides a simple to use solution to realize touch sensitive interfaces on most Atmel AVR microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and includes fully debounced reporting of touch keys and includes Adjacent key suppression® (AKS®) technology for unambiguous detection of key events. The QTouch library includes support for the QTouch and QMatrix acquisition methods. Touch sensing can be added to any application by linking the appropriate Atmel QTouch library for the AVR Microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors, and then calling the touch sensing API’s to retrieve the channel information and determine the touch sensor states. The QTouch library is FREE and downloadable from the Atmel website at the following location: www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the Atmel QTouch library user guide - also available for download from the Atmel website. XMEGA B3 [DATASHEET] 8 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

6. AVR CPU 6.1 Features (cid:122) 8/16-bit, high-performance Atmel AVR RISC CPU (cid:122) 142 instructions (cid:122) Hardware multiplier (cid:122) 32x8-bit registers directly connected to the ALU (cid:122) Stack in RAM (cid:122) Stack pointer accessible in I/O memory space (cid:122) Direct addressing of up to 16MB of program memory and 16MB of data memory (cid:122) True 16/24-bit access to 16/24-bit I/O registers (cid:122) Efficient support for 8-, 16-, and 32-bit arithmetic (cid:122) Configuration change protection of system-critical features 6.2 Overview All AVR XMEGA devices use the 8/16-bit AVR CPU. The main function of the CPU is to execute the code and perform all calculations. The CPU is able to access memories, perform calculations, control peripherals, and execute the program in the flash memory. Interrupt handling is described in a separate section, refer to “Interrupts and Programmable Multilevel Interrupt Controller” on page 29. 6.3 Architectural Overview In order to maximize performance and parallelism, the AVR CPU uses a Harvard architecture with separate memories and buses for program and data. Instructions in the program memory are executed with single-level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This enables instructions to be executed on every clock cycle. For details of all AVR instructions, refer to http://www.atmel.com/avr. Figure 6-1. Block Diagram of the AVR CPU architecture. XMEGA B3 [DATASHEET] 9 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a register. Single-register operations can also be executed in the ALU. After an arithmetic operation, the status register is updated to reflect information about the result of the operation. The ALU is directly connected to the fast-access register file. The 32 x 8-bit general purpose working registers all have single clock cycle access time allowing single-cycle arithmetic logic unit (ALU) operation between registers or between a register and an immediate. Six of the 32 registers can be used as three 16-bit address pointers for program and data space addressing, enabling efficient address calculations. The memory spaces are linear. The data memory space and the program memory space are two different memory spaces. The data memory space is divided into I/O registers and SRAM. In addition, the EEPROM can be memory mapped in the data memory. All I/O status and control registers reside in the lowest 4KB addresses of the data memory. This is referred to as the I/O memory space. The lowest 64 addresses can be accessed directly, or as the data space locations from 0x00 to 0x3F. The rest is the extended I/O memory space, ranging from 0x0040 to 0x0FFF. I/O registers here must be accessed as data space locations using load (LD/LDS/LDD) and store (ST/STS/STD) instructions. The SRAM holds data. Code execution from SRAM is not supported. It can easily be accessed through the five different addressing modes supported in the AVR architecture. The first SRAM address is 0x2000. Data addresses 0x1000 to 0x1FFF are reserved for memory mapping of EEPROM. The program memory is divided in two sections, the application program section and the boot program section. Both sections have dedicated lock bits for write and read/write protection. The SPM instruction that is used for self- programming of the application flash memory must reside in the boot program section. The application section contains an application table section with separate lock bits for write and read/write protection. The application table section can be used for save storing of nonvolatile data in the program memory. 6.4 ALU - Arithmetic Logic Unit The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a register. Single-register operations can also be executed. The ALU operates in direct connection with all 32 general purpose registers. In a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed and the result is stored in the register file. After an arithmetic or logic operation, the status register is updated to reflect information about the result of the operation. ALU operations are divided into three main categories – arithmetic, logical, and bit functions. Both 8- and 16-bit arithmetic is supported, and the instruction set allows for efficient implementation of 32-bit aritmetic. The hardware multiplier supports signed and unsigned multiplication and fractional format. 6.4.1 Hardware Multiplier The multiplier is capable of multiplying two 8-bit numbers into a 16-bit result. The hardware multiplier supports different variations of signed and unsigned integer and fractional numbers: (cid:122) Multiplication of unsigned integers (cid:122) Multiplication of signed integers (cid:122) Multiplication of a signed integer with an unsigned integer (cid:122) Multiplication of unsigned fractional numbers (cid:122) Multiplication of signed fractional numbers (cid:122) Multiplication of a signed fractional number with an unsigned one A multiplication takes two CPU clock cycles. XMEGA B3 [DATASHEET] 10 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

6.5 Program Flow After reset, the CPU starts to execute instructions from the lowest address in the flash programmemory ‘0.’ The program counter (PC) addresses the next instruction to be fetched. Program flow is provided by conditional and unconditional jump and call instructions capable of addressing the whole address space directly. Most AVR instructions use a 16-bit word format, while a limited number use a 32-bit format. During interrupts and subroutine calls, the return address PC is stored on the stack. The stack is allocated in the general data SRAM, and consequently the stack size is only limited by the total SRAM size and the usage of the SRAM. After reset, the stack pointer (SP) points to the highest address in the internal SRAM. The SP is read/write accessible in the I/O memory space, enabling easy implementation of multiple stacks or stack areas. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR CPU. 6.6 Status Register The status register (SREG) contains information about the result of the most recently executed arithmetic or logic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the status register is updated after all ALU operations, as specified in the instruction set reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The status register is not automatically stored when entering an interrupt routine nor restored when returning from an interrupt. This must be handled by software. The status register is accessible in the I/O memory space. 6.7 Stack and Stack Pointer The stack is used for storing return addresses after interrupts and subroutine calls. It can also be used for storing temporary data. The stack pointer (SP) register always points to the top of the stack. It is implemented as two 8-bit registers that are accessible in the I/O memory space. Data are pushed and popped from the stack using the PUSH and POP instructions. The stack grows from a higher memory location to a lower memory location. This implies that pushing data onto the stack decreases the SP, and popping data off the stack increases the SP. The SP is automatically loaded after reset, and the initial value is the highest address of the internal SRAM. If the SP is changed, it must be set to point above address 0x2000, and it must be defined before any subroutine calls are executed or before interrupts are enabled. During interrupts or subroutine calls, the return address is automatically pushed on the stack. The return address can be two or three bytes, depending on program memory size of the device. For devices with 128KB or less of program memory, the return address is two bytes, and hence the stack pointer is decremented/incremented by two. For devices with more than 128KB of program memory, the return address is three bytes, and hence the SP is decremented/incremented by three. The return address is popped off the stack when returning from interrupts using the RETI instruction, and from subroutine calls using the RET instruction. The SP is decremented by one when data are pushed on the stack with the PUSH instruction, and incremented by one when data is popped off the stack using the POP instruction. To prevent corruption when updating the stack pointer from software, a write to SPL will automatically disable interrupts for up to four instructions or until the next I/O memory write. 6.8 Register File The register file consists of 32 x 8-bit general purpose working registers with single clock cycle access time. The register file supports the following input/output schemes: (cid:122) One 8-bit output operand and one 8-bit result input (cid:122) Two 8-bit output operands and one 8-bit result input (cid:122) Two 8-bit output operands and one 16-bit result input (cid:122) One 16-bit output operand and one 16-bit result input XMEGA B3 [DATASHEET] 11 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

Six of the 32 registers can be used as three 16-bit address register pointers for data space addressing, enabling efficient address calculations. One of these address pointers can also be used as an address pointer for lookup tables in flash program memory. XMEGA B3 [DATASHEET] 12 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

7. Memories 7.1 Features (cid:122) Flash program memory (cid:122) One linear address space (cid:122) In-system programmable (cid:122) Self-programming and boot loader support (cid:122) Application section for application code (cid:122) Application table section for application code or data storage (cid:122) Boot section for application code or bootloader code (cid:122) Separate read/write protection lock bits for all sections (cid:122) Built in fast CRC check of a selectable flash program memory section (cid:122) Data memory (cid:122) One linear address space (cid:122) Single-cycle access from CPU (cid:122) SRAM (cid:122) EEPROM (cid:122) Byte and page accessible (cid:122) Optional memory mapping for direct load and store (cid:122) I/O memory (cid:122) Configuration and status registers for all peripherals and modules (cid:122) 4 bit-accessible general purpose registers for global variables or flags (cid:122) Bus arbitration (cid:122) Safe and deterministic handling of priority between CPU, DMA controller, and other bus masters (cid:122) Separate buses for SRAM, EEPROM and I/O memory (cid:122) Simultaneous bus access for CPU and DMA controller (cid:122) Production signature row memory for factory programmed data (cid:122) ID for each microcontroller device type (cid:122) Serial number for each device (cid:122) Calibration bytes for factory calibrated peripherals (cid:122) User signature row (cid:122) One flash page in size (cid:122) Can be read and written from software (cid:122) Content is kept after chip erase 7.2 Overview The Atmel AVR architecture has two main memory spaces, the program memory and the data memory. Executable code can reside only in the program memory, while data can be stored in the program memory and the data memory. The data memory includes the internal SRAM, and EEPROM for nonvolatile data storage. All memory spaces are linear and require no memory bank switching. Nonvolatile memory (NVM) spaces can be locked for further write and read/write operations. This prevents unrestricted access to the application software. A separate memory section contains the fuse bytes. These are used for configuring important system functions, and can only be written by an external programmer. The available memory size configurations are shown in “Ordering Information” on page 2. In addition, each device has a Flash memory signature row for calibration data, device identification, serial number etc. XMEGA B3 [DATASHEET] 13 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

7.3 Flash Program Memory The Atmel AVR XMEGA devices contain on-chip, in-system reprogrammable flash memory for program storage. The flash memory can be accessed for read and write from an external programmer through the PDI or from application software running in the device. All AVR CPU instructions are 16 or 32 bits wide, and each flash location is 16 bits wide. The flash memory is organized in two main sections, the application section and the boot loader section. The sizes of the different sections are fixed, but device-dependent. These two sections have separate lock bits, and can have different levels of protection. The store program memory (SPM) instruction,which is used to write to the flash from the application software, will only operate when executed from the boot loader section. The application section contains an application table section with separate lock settings. This enables safe storage of nonvolatile data in the program memory. Figure 7-1. Flash program memory (Hexadecimal address). Word Address ATxmega128B3 ATxmega64B3 0 0 Application section (bytes) (128K/64K) ... EFFF / 77FF F000 / 7800 Application table section (bytes) (8K/4K) FFFF / 7FFF 10000 / 8000 Boot section (bytes) 10FFF / 87FF (8K/4K) 7.3.1 Application Section The Application section is the section of the flash that is used for storing the executable application code. The protection level for the application section can be selected by the boot lock bits for this section. The application section can not store any boot loader code since the SPM instruction cannot be executed from the application section. 7.3.2 Application Table Section The application table section is a part of the application section of the flashmemory that can be used for storing data. The size is identical to the boot loader section. The protection level for the application table section can be selected by the boot lock bits for this section. The possibilities for different protection levels on the application section and the application table section enable safe parameter storage in the program memory. If this section is not used for data, application code can reside here. 7.3.3 Boot Loader Section While the application section is used for storing the application code, the boot loader software must be located in the boot loader section because the SPM instruction can only initiate programming when executing from this section. The SPM instruction can access the entire flash, including the boot loader section itself. The protection level for the boot loader section can be selected by the boot loader lock bits. If this section is not used for boot loader software, application code can be stored here. XMEGA B3 [DATASHEET] 14 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

7.3.4 Production Signature Row The production signature row is a separate memory section for factory programmed data. It contains calibration data for functions such as oscillators and analog modules. Some of the calibration values will be automatically loaded to the corresponding module or peripheral unit during reset. Other values must be loaded from the signature row and written to the corresponding peripheral registers from software. For details on calibration conditions, refer to “Electrical Characteristics” on page 71. The production signature row also contains an ID that identifies each microcontroller device type and a serial number for each manufactured device. The serial number consists of the production lot number, wafer number, and wafer coordinates for the device. The device ID for the available devices is shown in Table 7-1 on page 15. The production signature row cannot be written or erased, but it can be read from application software and external programmers. Table 7-1. Device ID bytes for XMEGA B3 devices. Device Device ID bytes Byte 2 Byte 1 Byte 0 ATxmega64B3 51 96 1E ATxmega128B3 4B 97 1E 7.3.5 User Signature Row The user signature row is a separate memory section that is fully accessible (read and write) from application software and external programmers. It is one flash page in size, and is meant for static user parameter storage, such as calibration data, custom serial number, identification numbers, random number seeds, etc. This section is not erased by chip erase commands that erase the flash, and requires a dedicated erase command. This ensures parameter storage during multiple program/erase operations and on-chip debug sessions. 7.4 Fuses and Lock bits The fuses are used to configure important system functions, and can only be written from an external programmer. The application software can read the fuses. The fuses are used to configure reset sources such as brownout detector and watchdog, startup configuration, JTAG enable, and JTAG user ID. The lock bits are used to set protection levels for the different flash sections (i.e., if read and/or write access should be blocked). Lock bits can be written by external programmers and application software, but only to stricter protection levels. Chip erase is the only way to erase the lock bits. To ensure that flash contents are protected even during chip erase, the lock bits are erased after the rest of the flash memory has been erased. An unprogrammed fuse or lock bit will have the value one, while a programmed fuse or lock bit will have the value zero. Both fuses and lock bits are reprogrammable like the flash program memory. 7.5 Data Memory The data memory contains the I/O memory, internal SRAM and optionally memory mapped EEPROM. The data memory is organized as one continuous memory section, see Figure 7-2 on page 16. To simplify development, I/O Memory, EEPROM and SRAM will always have the same start addresses for all XMEGA devices. XMEGA B3 [DATASHEET] 15 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

Figure 7-2. Data memory map (hexadecimal address). Byte Address ATxmega128B3 Byte Address ATxmega64B3 0 0 I/O Registers (4K) I/O Registers (4KB) FFF FFF 1000 1000 EEPROM (2K) EEPROM (2K) 17FF 17FF RESERVED RESERVED 2000 2000 Internal SRAM (8K) Internal SRAM (4K) 3FFF 2FFF 7.6 EEPROM XMEGA B3 devices have EEPROM for nonvolatile data storage. It is either addressable in a separate data space (default) or memory mapped and accessed in normal data space. The EEPROM supports both byte and page access. Memory mapped EEPROM allows highly efficient EEPROM reading and EEPROM buffer loading. When doing this, EEPROM is accessible using load and store instructions. Memory mapped EEPROM will always start at hexadecimal address 0x1000. 7.7 I/O Memory The status and configuration registers for peripherals and modules, including the CPU, are addressable through I/O memory locations. All I/O locations can be accessed by the load (LD/LDS/LDD) and store (ST/STS/STD) instructions, which are used to transfer data between the 32 registers in the register file and the I/O memory. The IN and OUT instructions can address I/O memory locations in the range of 0x00 to 0x3F directly. In the address range 0x00 - 0x1F, single-cycle instructions for manipulation and checking of individual bits are available. The I/O memory address for all peripherals and modules in XMEGA B3 is shown in the “Peripheral Module Address Map” on page 61. 7.7.1 General Purpose I/O Registers The lowest 4 I/O memory addresses are reserved as general purpose I/O registers. These registers can be used for storing global variables and flags, as they are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions. 7.8 Data Memory and Bus Arbitration Since the data memory is organized as four separate sets of memories, the different bus masters (CPU, DMA controller read and DMA controller write, etc.) can access different memory sections at the same time. 7.9 Memory Timing Read and write access to the I/O memory takes one CPU clock cycle. A write to SRAM takes one cycle, and a read from SRAM takes two cycles. For burst read (DMA), new data are available every cycle. EEPROM page load (write) takes one cycle, and three cycles are required for read. For burst read, new data are available every second cycle. Refer to the instruction summary for more details on instructions and instruction timing. 7.10 Device ID and Revision Each device has a three-byte device ID. This ID identifies Atmel as the manufacturer of the device and the device type. A separate register contains the revision number of the device. XMEGA B3 [DATASHEET] 16 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

7.11 JTAG Disable It is possible to disable the JTAG interface from the application software. This will prevent all external JTAG access to the device until the next device reset or until JTAG is enabled again from the application software. As long as JTAG is disabled, the I/O pins required for JTAG can be used as normal I/O pins. 7.12 I/O Memory Protection Some features in the device are regarded as critical for safety in some applications. Due to this, it is possible to lock the I/O register related to the clock system, the event system, and the advanced waveform extensions. As long as the lock is enabled, all related I/O registers are locked and they can not be written from the application software. The lock registers themselves are protected by the configuration change protection mechanism. 7.13 Flash and EEPROM Page Size The flash program memory and EEPROM data memory are organized in pages. The pages are word accessible for the flash and byte accessible for the EEPROM. Table 7-2 on page 17 shows the Flash Program Memory organization. Flash write and erase operations are performed on one page at a time, while reading the Flash is done one byte at a time. For Flash access the Z-pointer (Z[m:n]) is used for addressing. The most significant bits in the address (FPAGE) give the page number and the least significant address bits (FWORD) give the word in the page. Table 7-2. Number of words and Pages in the Flash. Devices PC size Flash Page Size FWORD FPAGE Application Boot No of No of bits bytes words Size Size pages pages ATxmega64B3 16 64K + 4K 128 Z[7:1] Z[16:8] 64K 256 4K 16 ATxmega128B3 17 128K + 8K 128 Z[8:1] Z[17:9] 128K 512 8K 32 Table 7-3 on page 17 shows EEPROM memory organization for the XMEGA B3 devices. EEEPROM write and erase operations can be performed one page or one byte at a time, while reading the EEPROM is done one byte at a time. For EEPROM access the NVM address register (ADDR[m:n]) is used for addressing. The most significant bits in the address (E2PAGE) give the page number and the least significant address bits (E2BYTE) give the byte in the page. Table 7-3. Number of Bytes and Pages in the EEPROM. Devices EEPROM Page Size E2BYTE E2PAGE No of Pages Size bytes ATxmega64B3 2K 32 ADDR[4:0] ADDR[10:5] 64 ATxmega128B3 2K 32 ADDR[4:0] ADDR[10:5] 64 XMEGA B3 [DATASHEET] 17 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

8. DMAC – Direct Memory Access Controller 8.1 Features (cid:122) Allows high speed data transfers with minimal CPU intervention (cid:122) from data memory to data memory (cid:122) from data memory to peripheral (cid:122) from peripheral to data memory (cid:122) from peripheral to peripheral (cid:122) Two DMA channels with separate (cid:122) transfer triggers (cid:122) interrupt vectors (cid:122) addressing modes (cid:122) Programmable channel priority (cid:122) From 1 byte to 16MB of data in a single transaction (cid:122) Up to 64KB block transfers with repeat (cid:122) 1, 2, 4, or 8 byte burst transfers (cid:122) Multiple addressing modes (cid:122) Static (cid:122) Incremental (cid:122) Decremental (cid:122) Optional reload of source and destination addresses at the end of each (cid:122) Burst (cid:122) Block (cid:122) Transaction (cid:122) Optional interrupt on end of transaction (cid:122) Optional connection to CRC generator for CRC on DMA data 8.2 Overview The two-channel direct memory access (DMA) controller can transfer data between memories and peripherals, and thus offload these tasks from the CPU. It enables high data transfer rates with minimum CPU intervention, and frees up CPU time. The four DMA channels enable up to four independent and parallel transfers. The DMA controller can move data between SRAM and peripherals, between SRAM locations and directly between peripheral registers. With access to all peripherals, the DMA controller can handle automatic transfer of data to/from communication modules. The DMA controller can also read from memory mapped EEPROM. Data transfers are done in continuous bursts of 1, 2, 4, or 8 bytes. They build block transfers of configurable size from 1 byte to 64KB. A repeat counter can be used to repeat each block transfer for single transactions up to 16MB. Source and destination addressing can be static, incremental or decremental. Automatic reload of source and/or destination addresses can be done after each burst or block transfer, or when a transaction is complete. Application software, peripherals, and events can trigger DMA transfers. The two DMA channels have individual configuration and control settings. This include source, destination, transfer triggers, and transaction sizes. They have individual interrupt settings. Interrupt requests can be generated when a transaction is complete or when the DMA controller detects an error on a DMA channel. To allow for continuous transfers, the channels can be interlinked so that the second takes over the transfer when the first is finished, and vice versa. XMEGA B3 [DATASHEET] 18 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

9. Event System 9.1 Features (cid:122) System for direct peripheral-to-peripheral communication and signaling (cid:122) Peripherals can directly send, receive, and react to peripheral events (cid:122) CPU and DMA controller independent operation (cid:122) 100% predictable signal timing (cid:122) Short and guaranteed response time (cid:122) Four event channels for up to four different and parallel signal routings and configurations (cid:122) Events can be sent and/or used by most peripherals, clock system, and software (cid:122) Additional functions include (cid:122) Quadrature decoders (cid:122) Digital filtering of I/O pin state (cid:122) Works in active mode and idle sleep mode 9.2 Overview The event system enables direct peripheral-to-peripheral communication and signaling. It allows a change in one peripheral’s state to automatically trigger actions in other peripherals. It is designed to provide a predictable system for short and predictable response times between peripherals. It allows for autonomous peripheral control and interaction without the use of interrupts, CPU, or DMA controller resources, and is thus a powerful tool for reducing the complexity, size and execution time of application code. It also allows for synchronized timing of actions in several peripheral modules. A change in a peripheral’s state is referred to as an event, and usually corresponds to the peripheral’s interrupt conditions. Events can be directly passed to other peripherals using a dedicated routing network called the event routing network. How events are routed and used by the peripherals is configured in software. Figure 9-1 on page 20 shows a basic diagram of all connected peripherals. The event system can directly connect together analog and digital converters, analog comparators, I/O port pins, the real-time counter, timer/counters, IR communication module (IRCOM), and USB interface. It can also be used to trigger DMA transactions (DMA controller). Events can also be generated from software and the peripheral clock. XMEGA B3 [DATASHEET] 19 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

Figure 9-1. Event system overview and connected peripherals. CPU / DMA Software Controller Event Routing Network clk PER Prescaler ADC Real Time Event Counter System Controller Timer / AC Counters USB Port pins IRCOM The event routing network consists of four software-configurable multiplexers that control how events are routed and used. These are called event channels, and allow for up to four parallel event configurations and routings. The maximum routing latency is two peripheral clock cycles. The event system works in both active mode and idle sleep mode. XMEGA B3 [DATASHEET] 20 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

10. System Clock and Clock options 10.1 Features (cid:122) Fast start-up time (cid:122) Safe run-time clock switching (cid:122) Internal oscillators: (cid:122) 32MHz run-time calibrated oscillator (cid:122) 2MHz run-time calibrated oscillator (cid:122) 32.768kHz calibrated oscillator (cid:122) 32kHz ultra low power (ULP) oscillator with 1kHz output (cid:122) External clock options (cid:122) 0.4MHz - 16MHz crystal oscillator (cid:122) 32.768kHz crystal oscillator (cid:122) External clock (cid:122) PLL with 20MHz - 128MHz output frequency (cid:122) Internal and external clock options and 1x to 31x multiplication (cid:122) Lock detector (cid:122) Clock prescalers with 1x to 2048x division (cid:122) Fast peripheral clocks running at 2 and 4 times the CPU clock (cid:122) Automatic run-time calibration of internal oscillators (cid:122) External oscillator and PLL lock failure detection with optional non-maskable interrupt 10.2 Overview Atmel AVR XMEGA devices have a flexible clock system supporting a large number of clock sources. It incorporates both accurate internal oscillators and external crystal oscillator and resonator support. A high-frequency phase locked loop (PLL) and clock prescalers can be used to generate a wide range of clock frequencies. A calibration feature (DFLL) is available, and can be used for automatic run-time calibration of the internal oscillators to remove frequency drift over voltage and temperature. An oscillator failure monitor can be enabled to issue a non-maskable interrupt and switch to the internal oscillator if the external oscillator or PLL fails. When a reset occurs, all clock sources except the 32kHz ultra low power oscillator are disabled. After reset, the device will always start up running from the 2MHz internal oscillator. During normal operation, the system clock source and prescalers can be changed from software at any time. Figure 10-1 on page 22 presents the principal clock system in the XMEGA B3 family of divices. Not all of the clocks need to be active at a given time. The clocks for the CPU and peripherals can be stopped using sleep modes and power reduction registers, as described in “Power Management and Sleep Modes” on page 24. XMEGA B3 [DATASHEET] 21 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

Figure 10-1. The Clock system, clock sources and clock distribution. RealTime Non-Volatile LCD Peripherals RAM AVRCPU Counter Memory clkPER clkPER2 clkCPU clkPER4 clkRTC clkLCD USB clkUSB SystemClockPrescalers Watchdog Prescaler Timer Brown-out clkSYS Detector SystemClockMultiplexer RTCSRC (SCLKSEL) USBSRC 32 32 32 PLL V V V DI DI DI PLLSRC 4 V XOSCSEL DI 32kHz 32.768kHz 32.768kHz 0.4–16MHz 32MHz 2MHz Int.ULP Int.OSC TOSC XTAL Int.Osc Int.Osc S1OC OSC2 TAL1 TAL2 C[7:0] T T X X P 10.3 Clock Sources The clock sources are divided in two main groups: internal oscillators and external clock sources. Most of the clock sources can be directly enabled and disabled from software, while others are automatically enabled or disabled, depending on peripheral settings. After reset, the device starts up running from the 2MHz internal oscillator. The other clock sources, DFLLs and PLL, are turned off by default. The internal oscillators do not require any external components to run. For details on characteristics and accuracy of the internal oscillators, refer to the device datasheet. 10.3.1 32kHz Ultra Low Power Internal Oscillator This oscillator provides an approximate 32kHz clock. The 32kHz ultra low power (ULP) internal oscillator is a very low power clock source, and it is not designed for high accuracy.The oscillator employs a built-in prescaler that provides a XMEGA B3 [DATASHEET] 22 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

1kHz output. The oscillator is automatically enabled/disabled when it is used as clock source for any part of the device. This oscillator can be selected as the clock source for the RTC and for LCD. 10.3.2 32.768kHz Calibrated Internal Oscillator This oscillator provides an approximate 32.768kHz clock. It is calibrated during production to provide a default frequency close to its nominal frequency. The calibration register can also be written from software for run-time calibration of the oscillator frequency. The oscillator employs a built-in prescaler, which provides both a 32.768kHz output and a 1.024kHz output. This oscillator can be used as a clock source for the system clock, RTC and LCD, and as the DFLL reference clock. 10.3.3 32.768kHz Crystal Oscillator A 32.768kHz crystal oscillator can be connected between the TOSC1 and TOSC2 pins and enables a dedicated low frequency oscillator input circuit. A low power mode with reduced voltage swing on TOSC2 is available. This oscillator can be used as a clock source for the system clock, RTC and LCD, and as the DFLL reference clock. 10.3.4 0.4 - 16MHz Crystal Oscillator This oscillator can operate in four different modes optimized for different frequency ranges, all within 0.4MHz - 16MHz. 10.3.5 2MHz Run-time Calibrated Internal Oscillator The 2MHz run-time calibrated internal oscillator is the default system clock source after reset. It is calibrated during production to provide a default frequency close to its nominal frequency. A DFLL can be enabled for automatic run-time calibration of the oscillator to compensate for temperature and voltage drift and optimize the oscillator accuracy. 10.3.6 32MHz Run-time Calibrated Internal Oscillator The 32MHz run-time calibrated internal oscillator is a high-frequency oscillator. It is calibrated during production to provide a default frequency close to its nominal frequency. A digital frequency looked loop (DFLL) can be enabled for automatic run-time calibration of the oscillator to compensate for temperature and voltage drift and optimize the oscillator accuracy. This oscillator can also be adjusted and calibrated to any frequency between 30MHz and 55MHz. The production signature row contains 48 MHz calibration values intended used when the oscillator is used a full-speed USB clock source. 10.3.7 External Clock Sources The XTAL1 and XTAL2 pins can be used to drive an external oscillator, either a quartz crystal or a ceramic resonator. XTAL1 or each pin of port C can be used as input for an external clock signal. The TOSC1 and TOSC2 pins is dedicated to driving a 32.768kHz crystal oscillator. 10.3.8 PLL with 1x-31x Multiplication Factor The built-in phase locked loop (PLL) can be used to generate a high-frequency system clock. The PLL has a user- selectable multiplication factor of from 1 to 31. In combination with the prescalers, this gives a wide range of output frequencies from all clock sources. XMEGA B3 [DATASHEET] 23 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

11. Power Management and Sleep Modes 11.1 Features (cid:122) Power management for adjusting power consumption and functions (cid:122) Five sleep modes (cid:122) Idle (cid:122) Power down (cid:122) Power save (cid:122) Standby (cid:122) Extended standby (cid:122) Power reduction register to disable clock and turn off unused peripherals in active and idle modes 11.2 Overview Various sleep modes and clock gating are provided in order to tailor power consumption to application requirements. This enables the XMEGA microcontroller to stop unused modules to save power. All sleep modes are available and can be entered from active mode. In active mode, the CPU is executing application code. When the device enters sleep mode, program execution is stopped and interrupts or a reset is used to wake the device again. The application code decides which sleep mode to enter and when. Interrupts from enabled peripherals and all enabled reset sources can restore the microcontroller from sleep to active mode. In addition, power reduction registers provide a method to stop the clock to individual peripherals from software. When this is done, the current state of the peripheral is frozen, and there is no power consumption from that peripheral. This reduces the power consumption in active mode and idle sleep modes and enables much more fine-tuned power management than sleep modes alone. 11.3 Sleep Modes Sleep modes are used to shut down modules and clock domains in the microcontroller in order to save power. XMEGA microcontrollers have five different sleep modes tuned to match the typical functional stages during application execution. A dedicated sleep instruction (SLEEP) is available to enter sleep mode. Interrupts are used to wake the device from sleep, and the available interrupt wake-up sources are dependent on the configured sleep mode. When an enabled interrupt occurs, the device will wake up and execute the interrupt service routine before continuing normal program execution from the first instruction after the SLEEP instruction. If other, higher priority interrupts are pending when the wake-up occurs, their interrupt service routines will be executed according to their priority before the interrupt service routine for the wake-up interrupt is executed. After wake-up, the CPU is halted for four cycles before execution starts. The content of the register file, SRAM and registers are kept during sleep. If a reset occurs during sleep, the device will reset, start up, and execute from the reset vector. 11.3.1 Idle Mode In idle mode the CPU and nonvolatile memory are stopped (note that any ongoing programming will be completed), but all peripherals, including the interrupt controller, event system and DMA controller are kept running. Any enabled interrupt will wake the device. 11.3.2 Power-down Mode In power-down mode, all clocks, including the real-time counter clock source, are stopped. This allows operation only of asynchronous modules that do not require a running clock. The only interrupts that can wake up the MCU are the two- wire interface address match interrupt, asynchronous port interrupts, and the USB resume interrupt. XMEGA B3 [DATASHEET] 24 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

11.3.3 Power-save Mode Power-save mode is identical to power down, with two exceptions: 1. If the real-time counter (RTC) is enabled, it will keep running during sleep, and the device can also wake up from either an RTC overflow or compare match interrupt. 2. If the liquid crystal display controller (LCD) is enabled, it will keep running during sleep, and the device can wake up from LCD frame completed interrupt. 11.3.4 Standby Mode Standby mode is identical to power down, with the exception that the enabled system clock sources are kept running while the CPU, peripheral, RTC and LCD clocks are stopped. This reduces the wake-up time. 11.3.5 Extended Standby Mode Extended standby mode is identical to power-save mode, with the exception that the enabled system clock sources are kept running while the CPU and peripheral clocks are stopped. This reduces the wake-up time. XMEGA B3 [DATASHEET] 25 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

12. System Control and Reset 12.1 Features (cid:122) Reset the microcontroller and set it to initial state when a reset source goes active (cid:122) Multiple reset sources that cover different situations (cid:122) Power-on reset (cid:122) External reset (cid:122) Watchdog reset (cid:122) Brownout reset (cid:122) PDI reset (cid:122) Software reset (cid:122) Asynchronous operation (cid:122) No running system clock in the device is required for reset (cid:122) Reset status register for reading the reset source from the application code 12.2 Overview The reset system issues a microcontroller reset and sets the device to its initial state. This is for situations where operation should not start or continue, such as when the microcontroller operates below its power supply rating. If a reset source goes active, the device enters and is kept in reset until all reset sources have released their reset. The I/O pins are immediately tri-stated. The program counter is set to the reset vector location, and all I/O registers are set to their initial values. The SRAM content is kept. However, if the device accesses the SRAM when a reset occurs, the content of the accessed location can not be guaranteed. After reset is released from all reset sources, the default oscillator is started and calibrated before the device starts running from the reset vector address. By default, this is the lowest program memory address, 0, but it is possible to move the reset vector to the lowest address in the boot section. The reset functionality is asynchronous, and so no running system clock is required to reset the device. The software reset feature makes it possible to issue a controlled system reset from the user software. The reset status register has individual status flags for each reset source. It is cleared at power-on reset, and shows which sources have issued a reset since the last power-on. 12.3 Reset Sequence A reset request from any reset source will immediately reset the device and keep it in reset as long as the request is active. When all reset requests are released, the device will go through three stages before the device starts running again: (cid:122) Reset counter delay (cid:122) Oscillator startup (cid:122) Oscillator calibration If another reset requests occurs during this process, the reset sequence will start over again. 12.4 Reset Sources 12.4.1 Power-on Reset A power-on reset (POR) is generated by an on-chip detection circuit. The POR is activated when the V rises and CC reaches the POR threshold voltage (V ), and this will start the reset sequence. POT The POR is also activated to power down the device properly when the V falls and drops below the V level. CC POT The V level is higher for falling V than for rising V . Consult the datasheet for POR characteristics data. POT CC CC XMEGA B3 [DATASHEET] 26 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

12.4.2 Brownout Detection The on-chip brownout detection (BOD) circuit monitors the V level during operation by comparing it to a fixed, CC programmable level that is selected by the BODLEVEL fuses. If disabled, BOD is forced on at the lowest level during chip erase and when the PDI is enabled. 12.4.3 External Reset The external reset circuit is connected to the external RESET pin. The external reset will trigger when the RESET pin is driven below the RESET pin threshold voltage, V , for longer than the minimum pulse period, t . The reset will be RST EXT held as long as the pin is kept low. The RESET pin includes an internal pull-up resistor. 12.4.4 Watchdog Reset The watchdog timer (WDT) is a system function for monitoring correct program operation. If the WDT is not reset from the software within a programmable timout period, a watchdog reset will be given. The watchdog reset is active for one to two clock cycles of the 2MHz internal oscillator. For more details see “WDT – Watchdog Timer” on page 28. 12.4.5 Software Reset The software reset makes it possible to issue a system reset from software by writing to the software reset bit in the reset control register.The reset will be issued within two CPU clock cycles after writing the bit. It is not possible to execute any instruction from when a software reset is requested until it is issued. 12.4.6 Program and Debug Interface Reset The program and debug interface reset contains a separate reset source that is used to reset the device during external programming and debugging. This reset source is accessible only from external debuggers and programmers. XMEGA B3 [DATASHEET] 27 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

13. WDT – Watchdog Timer 13.1 Features (cid:122) Issues a device reset if the timer is not reset before its timeout period (cid:122) Asynchronous operation from dedicated oscillator (cid:122) 1kHz output of the 32kHz ultra low power oscillator (cid:122) 11 selectable timeout periods, from 8ms to 8s (cid:122) Two operation modes: (cid:122) Normal mode (cid:122) Window mode (cid:122) Configuration lock to prevent unwanted changes 13.2 Overview The watchdog timer (WDT) is a system function for monitoring correct program operation. It makes it possible to recover from error situations such as runaway or deadlocked code. The WDT is a timer, configured to a predefined timeout period, and is constantly running when enabled. If the WDT is not reset within the timeout period, it will issue a microcontroller reset. The WDT is reset by executing the WDR (watchdog timer reset) instruction from the application code. The window mode makes it possible to define a time slot or window inside the total timeout period duringwhich WDT must be reset. If the WDT is reset outside this window, either too early or too late, a system reset will be issued. Compared to the normal mode, this can also catch situations where a code error causes constant WDR execution. The WDT will run in active mode and all sleep modes, if enabled. It is asynchronous, runs from a CPU-independent clock source, and will continue to operate to issue a system reset even if the main clocks fail. The configuration change protection mechanism ensures that the WDT settings cannot be changed by accident. For increased safety, a fuse for locking the WDT settings is also available. XMEGA B3 [DATASHEET] 28 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

14. Interrupts and Programmable Multilevel Interrupt Controller 14.1 Features (cid:122) Short and predictable interrupt response time (cid:122) Separate interrupt configuration and vector address for each interrupt (cid:122) Programmable multilevel interrupt controller (cid:122) Interrupt prioritizing according to level and vector address (cid:122) Three selectable interrupt levels for all interrupts: low, medium and high (cid:122) Selectable, round-robin priority scheme within low-level interrupts (cid:122) Non-maskable interrupts for critical functions (cid:122) Interrupt vectors optionally placed in the application section or the boot loader section 14.2 Overview Interrupts signal a change of state in peripherals, and this can be used to alter program execution. Peripherals can have one or more interrupts, and all are individually enabled and configured. When an interrupt is enabled and configured, it will generate an interrupt request when the interrupt condition is present. The programmable multilevel interrupt controller (PMIC) controls the handling and prioritizing of interrupt requests. When an interrupt request is acknowledged by the PMIC, the program counter is set to point to the interrupt vector, and the interrupt handler can be executed. All peripherals can select between three different priority levels for their interrupts: low, medium, and high. Interrupts are prioritized according to their level and their interrupt vector address. Medium-level interrupts will interrupt low-level interrupt handlers. High-level interrupts will interrupt both medium- and low-level interrupt handlers. Within each level, the interrupt priority is decided from the interrupt vector address, where the lowest interrupt vector address has the highest interrupt priority. Low-level interrupts have an optional round-robin scheduling scheme to ensure that all interrupts are serviced within a certain amount of time. Non-maskable interrupts (NMI) are also supported, and can be used for system critical functions. 14.3 Interrupt vectors The interrupt vector is the sum of the peripheral’s base interrupt address and the offset address for specific interrupts in each peripheral. The base addresses for the XMEGA B3 devices are shown in Table 14-1. Offset addresses for each interrupt available in the peripheral are described for each peripheral in the XMEGA B manual. For peripherals or modules that have only one interrupt, the interrupt vector is shown in Table 14-1. The program address is the word address. Table 14-1. Reset and Interrupt Vectors. Program Address (Base Address) Source Interrupt Description 0x000 RESET 0x002 OSCF_INT_vect Crystal Oscillator Failure Interrupt vector (NMI) 0x004 PORTC_INT_base Port C Interrupt base 0x008 PORTR_INT_base Port R Interrupt base 0x00C DMA_INT_base DMA Controller Interrupt base 0x014 RTC_INT_base Real Time Counter Interrupt base 0x018 TWIC_INT_base Two-Wire Interface on Port C Interrupt base 0x01C TCC0_INT_base Timer/Counter 0 on port C Interrupt base XMEGA B3 [DATASHEET] 29 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

Program Address (Base Address) Source Interrupt Description 0x028 TCC1_INT_base Timer/Counter 1 on port C Interrupt base 0x030 SPIC_INT_vect SPI on port C Interrupt vector 0x032 USARTC0_INT_base USART 0 on port C Interrupt base 0x03E USB_INT_base USB on port D Interrupt base 0x046 LCD_INT_base LCD Interrupt base 0x048 AES_INT_vect AES Interrupt vector 0x04A NVM_INT_base Non-Volatile Memory Interrupt base 0x04E PORTB_INT_base Port B Interrupt base 0x052 ACB_INT_base Analog Comparator on Port B Interrupt base 0x058 ADCB_INT_base Analog to Digital Converter on Port B Interrupt base 0x060 PORTD_INT_base Port D Interrupt base 0x064 PORTG_INT_base Port G Interrupt base 0x068 PORTM_INT_base Port M Interrupt base XMEGA B3 [DATASHEET] 30 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

15. I/O Ports 15.1 Features (cid:122) 36 General purpose input and output pins with individual configuration (cid:122) Output driver with configurable driver and pull settings: (cid:122) Totem-pole (cid:122) Wired-AND (cid:122) Wired-OR (cid:122) Bus-keeper (cid:122) Inverted I/O (cid:122) Input with synchronous and/or asynchronous sensing with interrupts and events (cid:122) Sense both edges (cid:122) Sense rising edges (cid:122) Sense falling edges (cid:122) Sense low level (cid:122) Optional pull-up and pull-down resistor on input and Wired-OR/AND configurations (cid:122) Optional slew rate control (cid:122) Asynchronous pin change sensing that can wake the device from all sleep modes (cid:122) Two port interrupts with pin masking per I/O port (cid:122) Efficient and safe access to port pins (cid:122) Hardware read-modify-write through dedicated toggle/clear/set registers (cid:122) Configuration of multiple pins in a single operation (cid:122) Mapping of port registers into bit-accessible I/O memory space (cid:122) Peripheral clocks output on port pin (cid:122) Real-time counter clock output to port pin (cid:122) Event channels can be output on port pin (cid:122) Remapping of digital peripheral pin functions (cid:122) Selectable USART, SPI, and timer/counter input/output pin locations 15.2 Overview One port consists of up to eight port pins: pin 0 to 7. Each port pin can be configured as input or output with configurable driver and pull settings. They also implement synchronous and asynchronous input sensing with interrupts and events for selectable pin change conditions. Asynchronous pin-change sensing means that a pin change can wake the device from all sleep modes, included the modes where no clocks are running. All functions are individual and configurable per pin, but several pins can be configured in a single operation. The pins have hardware read-modify-write (RMW) functionality for safe and correct change of drive value and/or pull resistor configuration. The direction of one port pin can be changed without unintentionally changing the direction of any other pin. The port pin configuration also controls input and output selection of other device functions. It is possible to have both the peripheral clock and the real-time clock output to a port pin, and available for external use. The same applies to events from the event system that can be used to synchronize and control external functions. Other digital peripherals, such as USART, SPI, and timer/counters, can be remapped to selectable pin locations in order to optimize pin-out versus application needs. The notation of the ports are PORTB, PORTC, PORTD, PORTG, PORTM and PORTR. XMEGA B3 [DATASHEET] 31 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

15.3 Output Driver All port pins (Pn) have programmable output configuration. The port pins also have configurable slew rate limitation to reduce electromagnetic emission. 15.3.1 Push-pull Figure 15-1. I/O configuration - Totem-pole DIRn OUTn Pn INn 15.3.2 Pull-down Figure 15-2. I/O configuration - Totem-pole with pull-down (on input) DIRn OUTn Pn INn 15.3.3 Pull-up Figure 15-3. I/O configuration - Totem-pole with pull-up (on input) DIRn OUTn Pn INn XMEGA B3 [DATASHEET] 32 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

15.3.4 Bus-keeper The bus-keeper’s weak output produces the same logical level as the last output level. It acts as a pull-up if the last level was ‘1’, and pull-down if the last level was ‘0’. Figure 15-4. I/O configuration - Totem-pole with bus-keeper DIRn OUTn Pn INn 15.3.5 Others Figure 15-5. Output configuration - Wired-OR with optional pull-down OUTn Pn INn Figure 15-6. I/O configuration - Wired-AND with optional pull-up INn Pn OUTn XMEGA B3 [DATASHEET] 33 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

15.4 Input sensing Input sensing is synchronous or asynchronous depending on the enabled clock for the ports, and the configuration is shown in Figure 15-7 on page 34. Figure 15-7. Input sensing system overview Asynchronous sensing EDGE Interrupt DETECT IREQ Control Synchronous sensing Pn Synchronizer INn EDGE D QD Q DETECT Event INVERTED I/O R R When a pin is configured with inverted I/O, the pin value is inverted before the input sensing. 15.5 Alternate Port Functions Most port pins have alternate pin functions in addition to being a general purpose I/O pin. When an alternate function is enabled, it might override the normal port pin function or pin value. This happens when other peripherals that require pins are enabled or configured to use pins. If and how a peripheral will override and use pins is described in the section for that peripheral. “Pinout and Pin Functions” on page 55 shows which modules on peripherals that enable alternate functions on a pin, and which alternate functions that are available on a pin. XMEGA B3 [DATASHEET] 34 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

16. T/C – 16-bit Timer/Counter Type 0 and 1 16.1 Features (cid:122) Two 16-bit timer/counters (cid:122) One timer/counters of type 0 (cid:122) One timer/counters of type 1 (cid:122) 32-bit Timer/Counter support by cascading two timer/counters (cid:122) Up to four compare or capture (CC) channels (cid:122) Four CC channels for timer/counters of type 0 (cid:122) Two CC channels for timer/counters of type 1 (cid:122) Double buffered timer period setting (cid:122) Double buffered capture or compare channels (cid:122) Waveform generation: (cid:122) Frequency generation (cid:122) Single-slope pulse width modulation (cid:122) Dual-slope pulse width modulation (cid:122) Input capture: (cid:122) Input capture with noise cancelling (cid:122) Frequency capture (cid:122) Pulse width capture (cid:122) 32-bit input capture (cid:122) Timer overflow and error interrupts/events (cid:122) One compare match or input capture interrupt/event per CC channel (cid:122) Can be used with event system for: (cid:122) Quadrature decoding (cid:122) Count and direction control (cid:122) Capture (cid:122) Can be used with DMA and to trigger DMA transactions (cid:122) High-resolution extension (cid:122) Increases frequency and waveform resolution by 4x (2-bit) or 8x (3-bit) (cid:122) Advanced waveform extension: (cid:122) Low- and high-side output with programmable dead-time insertion (DTI) (cid:122) Event controlled fault protection for safe disabling of drivers 16.2 Overview Atmel AVR XMEGA B3 devices have a set of two flexible 16-bit Timer/Counters (TC). Their capabilities include accurate program execution timing, frequency and waveform generation, and input capture with time and frequency measurement of digital signals. Two timer/counters can be cascaded to create a 32-bit timer/counter with optional 32-bit capture. A timer/counter consists of a base counter and a set of compare or capture (CC) channels. The base counter can be used to count clock cycles or events. It has direction control and period setting that can be used for timing. The CC channels can be used together with the base counter to do compare match control, frequency generation, and pulse width waveform modulation, as well as various input capture operations. A timer/counter can be configured for either capture or compare functions, but cannot perform both at the same time. A timer/counter can be clocked and timed from the peripheral clock with optional prescaling or from the event system. The event system can also be used for direction control and capture trigger or to synchronize operations. There are two differences between timer/counter type 0 and type 1. Timer/counter 0 has four CC channels, and timer/counter 1 has two CC channels. All information related to CC channels 3 and 4 is valid only for timer/counter 0. Only Timer/Counter 0 has the split mode feature that split it into 2 8-bit Timer/Counters with four compare channels each. XMEGA B3 [DATASHEET] 35 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

Some timer/counters have extensions to enable more specialized waveform and frequency generation. The advanced waveform extension (AWeX) is intended for motor control and other power control applications. It enables low- and high- side output with dead-time insertion, as well as fault protection for disabling and shutting down external drivers. It can also generate a synchronized bit pattern across the port pins. The Advanced Waveform Extension can be enabled to provide extra and more advanced features for the Timer/Counter. This are only available for Timer/Counter 0. See “TC2 –16-bit Timer/Counter Type 2” on page 37 for more details. The high-resolution (hi-res) extension can be used to increase the waveform output resolution by four or eight times by using an internal clock source running up to four times faster than the peripheral clock. See “Hi-Res – High Resolution Extension” on page 39 for more details. Figure 16-1. Overview of a Timer/Counter and closely related peripherals Timer/Counter Base Counter Prescaler clk PER Timer Period Control Logic Event Counter System clk PER4 Compare/Capture Channel D Compare/Capture Channel C AWeX Compare/Capture Channel B CoCmompaparera/Ctoarpture CChaaptnunree l A DIenasde-rTtioimne GePnFaeattruealrttni o n Hi-Res PORT Control Protection Waveform Buffer Generation PORTC has one Timer/Counter 0 and one Timer/Counter1. Notation of these are TCC0 (Time/Counter C0) and TCC1 respectively. XMEGA B3 [DATASHEET] 36 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

17. TC2 –16-bit Timer/Counter Type 2 17.1 Features (cid:122) A system of two eight-bit timer/counters (cid:122) Low-byte timer/counter (cid:122) High-byte timer/counter (cid:122) Eight compare channels (cid:122) Four compare channels for the low-byte timer/counter (cid:122) Four compare channels for the high-byte timer/counter (cid:122) Waveform generation (cid:122) Single slope pulse width modulation (cid:122) Timer underflow interrupts/events (cid:122) One compare match interrupt/event per compare channel for the low-byte timer/counter (cid:122) Can be used with the event system for count control (cid:122) Can be used to trigger DMA transactions (cid:122) High-resolution extension increases frequency and waveform resolution by 4x or 8x 17.2 Overview A timer/counter 2 is realized when a timer/counter 0 is set in split mode. It is a system of two eight-bit timer/counters, each with four compare channels. This results in eight configurable pulse width modulation (PWM) channels with individually controlled duty cycles, and is intended for applications that require a high number of PWM channels. The two eight-bit timer/counters in this system are referred to as the low-byte timer/counter and high-byte timer/counter, respectively. The difference between them is that only the low-byte timer/counter can be used to generate compare match interrupts, events and DMA triggers. The two eight-bit timer/counters have a shared clock source and separate period and compare settings. They can be clocked and timed from the peripheral clock, with optional prescaling, or from the event system. The counters are always counting down. The timer/counter 2 is set back to timer/counter 0 by setting it in normal mode; hence, one timer/counter can exist only as either type 0 or type 2. PORTC has one Timer/Counter 2. Notation of these are TCC2 (Time/Counter C2). XMEGA B3 [DATASHEET] 37 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

18. AWeX – Advanced Waveform Extension 18.1 Features (cid:122) Waveform output with complementary output from each compare channel (cid:122) Four dead-time insertion (DTI) units (cid:122) 8-bit resolution (cid:122) Separate high and low side dead-time setting (cid:122) Double buffered dead time (cid:122) Optionally halts timer during dead-time insertion (cid:122) Pattern generation unit creating synchronised bit pattern across the port pins (cid:122) Double buffered pattern generation (cid:122) Optional distribution of one compare channel output across the port pins (cid:122) Event controlled fault protection for instant and predictable fault triggering 18.2 Overview The advanced waveform extension (AWeX) provides extra functions to the timer/counter in waveform generation (WG) modes. It is primarily intended for use with different types of motor control and other power control applications. It enables low- and high side output with dead-time insertion and fault protection for disabling and shutting down external drivers. It can also generate a synchronized bit pattern across the port pins. Each of the waveform generator outputs from the timer/counter 0 are split into a complimentary pair of outputs when any AWeX features are enabled. These output pairs go through a dead-time insertion (DTI) unit that generates the non- inverted low side (LS) and inverted high side (HS) of the WG output with dead-time insertion between LS and HS switching. The DTI output will override the normal port value according to the port override setting. The pattern generation unit can be used to generate a synchronized bit pattern on the port it is connected to. In addition, the WG output from compare channel A can be distributed to and override all the port pins. When the pattern generator unit is enabled, the DTI unit is bypassed. The fault protection unit is connected to the event system, enabling any event to trigger a fault condition that will disable the AWeX output. The event system ensures predictable and instant fault reaction, and gives flexibility in the selection of fault triggers. The AWEX is available for TCC0. The notation of this is AWEXC. XMEGA B3 [DATASHEET] 38 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

19. Hi-Res – High Resolution Extension 19.1 Features (cid:122) Increases waveform generator resolution up to 8x (3 bits) (cid:122) Supports frequency, single-slope PWM, and dual-slope PWM generation (cid:122) Supports the AWeX when this is used for the same timer/counter 19.2 Overview The high-resolution (hi-res) extension can be used to increase the resolution of the waveform generation output from a timer/counter by four or eight. It can be used for a timer/counter doing frequency, single-slope PWM, or dual-slope PWM generation. It can also be used with the AWeX if this is used for the same timer/counter. The hi-res extension uses the peripheral 4x clock (Clk ). The system clock prescalers must be configured so the PER4 peripheral 4x clock frequency is four times higher than the peripheral and CPU clock frequency when the hi-res extension is enabled. Atmel AVR XMEGA B3 devices have one Hi-Res Extension that can be enabled for the timer/counters pair on PORTC. The notation of this is HIRESC. XMEGA B3 [DATASHEET] 39 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

20. RTC – 16-bit Real-Time Counter 20.1 Features (cid:122) 16-bit resolution (cid:122) Selectable clock source (cid:122) 32.768kHz external crystal (cid:122) External clock (cid:122) 32.768kHz internal oscillator (cid:122) 32kHz internal ULP oscillator (cid:122) Programmable 10-bit clock prescaling (cid:122) One compare register (cid:122) One period register (cid:122) Clear counter on period overflow (cid:122) Optional interrupt/event on overflow and compare match 20.2 Overview The 16-bit real-time counter (RTC) is a counter that typically runs continuously, including in low-power sleep modes, to keep track of time. It can wake up the device from sleep modes and/or interrupt the device at regular intervals. The reference clock is typically the 1.024kHz output from a high-accuracy crystal of 32.768kHz, and this is the configuration most optimized for low power consumption. The faster 32.768kHz output can be selected if the RTC needs a resolution higher than 1ms. The RTC can also be clocked from an external clock signal, the 32.768kHz internal oscillator or the 32kHz internal ULP oscillator. The RTC includes a 10-bit programmable prescaler that can scale down the reference clock before it reaches the counter. A wide range of resolutions and time-out periods can be configured. With a 32.768kHz clock source, the maximum resolution is 30.5µs, and time-out periods can range up to 2000 seconds. With a resolution of 1s, the maximum timeout period is more than18 hours (65536 seconds). The RTC can give a compare interrupt and/or event when the counter equals the compare register value, and an overflow interrupt and/or event when it equals the period register value. Figure 20-1. Real-time Counter overview External Clock TOSC1 32.768kHz Crystal Osc TOSC2 32.768kHz Int. Osc 32kHz int ULP (DIV32) D D IV IV 3 3 2 2 PER RTCSRC TOP/ clk = RTC Overflow 10-bit CNT prescaler ”match”/ = Compare COMP XMEGA B3 [DATASHEET] 40 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

21. USB – Universal Serial Bus Interface 21.1 Features (cid:122) One USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant interface (cid:122) Integrated on-chip USB transceiver, no external components needed (cid:122) 16 endpoint addresses with full endpoint flexibility for up to 31 endpoints (cid:122) One input endpoint per endpoint address (cid:122) One output endpoint per endpoint address (cid:122) Endpoint address transfer type selectable to (cid:122) Control transfers (cid:122) Interrupt transfers (cid:122) Bulk transfers (cid:122) Isochronous transfers (cid:122) Configurable data payload size per endpoint, up to 1023 bytes (cid:122) Endpoint configuration and data buffers located in internal SRAM (cid:122) Configurable location for endpoint configuration data (cid:122) Configurable location for each endpoint's data buffer (cid:122) Built-in direct memory access (DMA) to internal SRAM for: (cid:122) Endpoint configurations (cid:122) Reading and writing endpoint data (cid:122) Ping-pong operation for higher throughput and double buffered operation (cid:122) Input and output endpoint data buffers used in a single direction (cid:122) CPU/DMA controller can update data buffer during transfer (cid:122) Multipacket transfer for reduced interrupt load and software intervention (cid:122) Data payload exceeding maximum packet size is transferred in one continuous transfer (cid:122) No interrupts or software interaction on packet transaction level (cid:122) Transaction complete FIFO for workflow management when using multiple endpoints (cid:122) Tracks all completed transactions in a first-come, first-served work queue (cid:122) Clock selection independent of system clock source and selection (cid:122) Minimum 1.5MHz CPU clock required for low speed USB operation (cid:122) Minimum 12MHz CPU clock required for full speed operation (cid:122) Connection to event system (cid:122) On chip debug possibilities during USB transactions 21.2 Overview The USB module is a USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant interface. The USB supports 16 endpoint addresses. All endpoint addresses have one input and one output endpoint, for a total of 31 configurable endpoints and one control endpoint. Each endpoint address is fully configurable and can be configured for any of the four transfer types: control, interrupt, bulk, or isochronous. The data payload size is also selectable, and it supports data payloads up to 1023 bytes. No dedicated memory is allocated for or included in the USB module. Internal SRAM is used to keep the configuration for each endpoint address and the data buffer for each endpoint. The memory locations used for endpoint configurations and data buffers are fully configurable. The amount of memory allocated is fully dynamic, according to the number of endpoints in use and the configuration of these. The USB module has built-in direct memory access (DMA), and will read/write data from/to the SRAM when a USB transaction takes place. To maximize throughput, an endpoint address can be configured for ping-pong operation. When done, the input and output endpoints are both used in the same direction. The CPU or DMA controller can then read/write one data buffer while the USB module writes/reads the others, and vice versa. This gives double buffered communication. XMEGA B3 [DATASHEET] 41 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

Multipacket transfer enables a data payload exceeding the maximum packet size of an endpoint to be transferred as multiple packets without software intervention. This reduces the CPU intervention and the interrupts needed for USB transfers. For low-power operation, the USB module can put the microcontroller into any sleep mode when the USB bus is idle and a suspend condition is given. Upon bus resumes, the USB module can wake up the microcontroller from any sleep mode. PORTD has one USB. Notation of this is USB. XMEGA B3 [DATASHEET] 42 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

22. TWI – Two Wire Interface 22.1 Features (cid:122) One two-wire interface peripheral (cid:122) Bidirectional, two-wire communication interface (cid:122) Phillips I2C compatible (cid:122) System Management Bus (SMBus) compatible (cid:122) Bus master and slave operation supported (cid:122) Slave operation (cid:122) Single bus master operation (cid:122) Bus master in multi-master bus environment (cid:122) Multi-master arbitration (cid:122) Flexible slave address match functions (cid:122) 7-bit and general call address recognition in hardware (cid:122) 10-bit addressing supported (cid:122) Address mask register for dual address match or address range masking (cid:122) Optional software address recognition for unlimited number of addresses (cid:122) Slave can operate in all sleep modes, including power-down (cid:122) Slave address match can wake device from all sleep modes (cid:122) 100kHz and 400kHz bus frequency support (cid:122) Slew-rate limited output drivers (cid:122) Input filter for bus noise and spike suppression (cid:122) Support arbitration between start/repeated start and data bit (SMBus) (cid:122) Slave arbitration allows support for address resolve protocol (ARP) (SMBus) 22.2 Overview The two-wire interface (TWI) is a bidirectional, two-wire communication interface. It is I2C and System Management Bus (SMBus) compatible. The only external hardware needed to implement the bus is one pull-up resistor on each bus line. A device connected to the bus must act as a master or a slave. The master initiates a data transaction by addressing a slave on the bus and telling whether it wants to transmit or receive data. One bus can have many slaves and one or several masters that can take control of the bus. An arbitration process handles priority if more than one master tries to transmit data at the same time. Mechanisms for resolving bus contention are inherent in the protocol. The TWI module supports master and slave functionality. The master and slave functionality are separated from each other, and can be enabled and configured separately. The master module supports multi-master bus operation and arbitration. It contains the baud rate generator. Both 100kHz and 400kHz bus frequency is supported. Quick command and smart mode can be enabled to auto-trigger operations and reduce software complexity. The slave module implements 7-bit address match and general address call recognition in hardware. 10-bit addressing is also supported. A dedicated address mask register can act as a second address match register or as a register for address range masking. The slave continues to operate in all sleep modes, including power-down mode. This enables the slave to wake up the device from all sleep modes on TWI address match. It is possible to disable the address matching to let this be handled in software instead. The TWI module will detect START and STOP conditions, bus collisions, and bus errors. Arbitration lost, errors, collision, and clock hold on the bus are also detected and indicated in separate status flags available in both master and slave modes. It is possible to disable the TWI drivers in the device, and enable a four-wire digital interface for connecting to an external TWI bus driver. This can be used for applications where the device operates from a different V voltage than used by CC the TWI bus. PORTC has one TWI. Notation of this peripheral is TWIC. XMEGA B3 [DATASHEET] 43 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

23. SPI – Serial Peripheral Interface 23.1 Features (cid:122) One SPI peripheral (cid:122) Full-duplex, three-wire synchronous data transfer (cid:122) Master or slave operation (cid:122) Lsb first or msb first data transfer (cid:122) Eight programmable bit rates (cid:122) Interrupt flag at the end of transmission (cid:122) Write collision flag to indicate data collision (cid:122) Wake up from idle sleep mode (cid:122) Double speed master mode 23.2 Overview The Serial Peripheral Interface (SPI) is a high-speed synchronous data transfer interface using three or four pins. It allows fast communication between an XMEGA device and peripheral devices or between several microcontrollers. The SPI supports full-duplex communication. A device connected to the bus must act as a master or slave.The master initiates and controls all data transactions. PORTC has one SPI. Notation of this peripheral is SPIC. XMEGA B3 [DATASHEET] 44 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

24. USART 24.1 Features (cid:122) One USART peripherals (cid:122) Full-duplex operation (cid:122) Asynchronous or synchronous operation (cid:122) Synchronous clock rates up to 1/2 of the device clock frequency (cid:122) Asynchronous clock rates up to 1/8 of the device clock frequency (cid:122) Supports serial frames with 5, 6, 7, 8, or 9 data bits and 1 or 2 stop bits (cid:122) Fractional baud rate generator (cid:122) Can generate desired baud rate from any system clock frequency (cid:122) No need for external oscillator with certain frequencies (cid:122) Built-in error detection and correction schemes (cid:122) Odd or even parity generation and parity check (cid:122) Data overrun and framing error detection (cid:122) Noise filtering includes false start bit detection and digital low-pass filter (cid:122) Separate interrupts for (cid:122) Transmit complete (cid:122) Transmit data register empty (cid:122) Receive complete (cid:122) Multiprocessor communication mode (cid:122) Addressing scheme to address a specific devices on a multidevice bus (cid:122) Enable unaddressed devices to automatically ignore all frames (cid:122) Master SPI mode (cid:122) Double buffered operation (cid:122) Configurable data order (cid:122) Operation up to 1/2 of the peripheral clock frequency (cid:122) IRCOM module for IrDA compliant pulse modulation/demodulation 24.2 Overview The universal synchronous and asynchronous serial receiver and transmitter (USART) is a fast and flexible serial communication module. The USART supports full-duplex communication and asynchronous and synchronous operation. The USART can be configured to operate in SPI master mode and used for SPI communication. Communication is frame based, and the frame format can be customized to support a wide range of standards. The USART is buffered in both directions, enabling continued data transmission without any delay between frames. Separate interrupts for receive and transmit complete enable fully interrupt driven communication. Frame error and buffer overflow are detected in hardware and indicated with separate status flags. Even or odd parity generation and parity check can also be enabled. The clock generator includes a fractional baud rate generator that is able to generate a wide range of USART baud rates from any system clock frequencies. This removes the need to use an external crystal oscillator with a specific frequency to achieve a required baud rate. It also supports external clock input in synchronous slave operation. When the USART is set in master SPI mode, all USART-specific logic is disabled, leaving the transmit and receive buffers, shift registers, and baud rate generator enabled. Pin control and interrupt generation are identical in both modes. The registers are used in both modes, but their functionality differs for some control settings. An IRCOM module can be enabled for one USART to support IrDA 1.4 physical compliant pulse modulation and demodulation for baud rates up to 115.2kbps. PORTC has one USART. Notation of this peripheral is USARTC0. XMEGA B3 [DATASHEET] 45 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

25. IRCOM – IR Communication Module 25.1 Features (cid:122) Pulse modulation/demodulation for infrared communication (cid:122) IrDA compatible for baud rates up to 115.2kbps (cid:122) Selectable pulse modulation scheme (cid:122) 3/16 of the baud rate period (cid:122) Fixed pulse period, 8-bit programmable (cid:122) Pulse modulation disabled (cid:122) Built-in filtering (cid:122) Can be connected to and used by any USART 25.2 Overview XMEGA devices contain an infrared communication module (IRCOM) that is IrDA compatible for baud rates up to 115.2kbps. It can be connected to any USART to enable infrared pulse encoding/decoding for that USART. XMEGA B3 [DATASHEET] 46 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

26. AES and DES Crypto Engine 26.1 Features (cid:122) Data Encryption Standard (DES) CPU instruction (cid:122) Advanced Encryption Standard (AES) crypto module (cid:122) DES Instruction (cid:122) Encryption and decryption (cid:122) DES supported (cid:122) Encryption/decryption in 16 CPU clock cycles per 8-byte block (cid:122) AES crypto module (cid:122) Encryption and decryption (cid:122) Supports 128-bit keys (cid:122) Supports XOR data load mode to the state memory (cid:122) Encryption/decryption in 375 clock cycles per 16-byte block 26.2 Overview The Advanced Encryption Standard (AES) and Data Encryption Standard (DES) are two commonly used standards for cryptography. These are supported through an AES peripheral module and a DES CPU instruction, and the communication interfaces and the CPU can use these for fast, encrypted communication and secure data storage. DES is supported by an instruction in the AVR CPU. The 8-byte key and 8-byte data blocks must be loaded into the register file, and then the DES instruction must be executed 16 times to encrypt/decrypt the data block. The AES crypto module encrypts and decrypts 128-bit data blocks with the use of a 128-bit key. The key and data must be loaded into the key and state memory in the module before encryption/decryption is started. It takes 375 peripheral clock cycles before the encryption/decryption is done. The encrypted/encrypted data can then be read out, and an optional interrupt can be generated. The AES crypto module also has DMA support with transfer triggers when encryption/decryption is done and optional auto-start of encryption/decryption when the state memory is fully loaded. XMEGA B3 [DATASHEET] 47 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

27. CRC – Cyclic Redundancy Check Generator 27.1 Features (cid:122) Cyclic redundancy check (CRC) generation and checking for (cid:122) Communication data (cid:122) Program or data in flash memory (cid:122) Data in SRAM and I/O memory space (cid:122) Integrated with flash memory, DMA controller and CPU (cid:122) Continuous CRC on data going through a DMA channel (cid:122) Automatic CRC of the complete or a selectable range of the flash memory (cid:122) CPU can load data to the CRC generator through the I/O interface (cid:122) CRC polynomial software selectable to (cid:122) CRC-16 (CRC-CCITT) (cid:122) CRC-32 (IEEE 802.3) (cid:122) Zero remainder detection 27.2 Overview A cyclic redundancy check (CRC) is an error detection technique test algorithm used to find accidental errors in data, and it is commonly used to determine the correctness of a data transmission, and data present in the data and program memories. A CRC takes a data stream or a block of data as input and generates a 16- or 32-bit output that can be appended to the data and used as a checksum. When the same data are later received or read, the device or application repeats the calculation. If the new CRC result does not match the one calculated earlier, the block contains a data error. The application will then detect this and may take a corrective action, such as requesting the data to be sent again or simply not using the incorrect data. Typically, an n-bit CRC applied to a data block of arbitrary length will detect any single error burst not longer than n bits (any single alteration that spans no more than n bits of the data), and will detect the fraction 1-2-n of all longer error bursts. The CRC module in XMEGA devices supports two commonly used CRC polynomials; CRC-16 (CRC-CCITT) and CRC-32 (IEEE802.3). (cid:122) CRC-16: Polynomial: x16+x12+x5+1 Hex value: 0x1021 (cid:122) CRC-32: Polynomial: x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x+1 Hex value: 0x04C11DB7 XMEGA B3 [DATASHEET] 48 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

28. LCD - Liquid Crystal Display Controller 28.1 Features (cid:122) Display capacity up to 25 segment and up to 4 common terminals (cid:122) Supports up to 16 GPIO's (cid:122) Shadow display memory gives full freedom in segment update (cid:122) ASCII character mapping (cid:122) Swap capability option on segment and/or common terminal buses (cid:122) Supports from static up to 1/4 duty (cid:122) Supports static and 1/3 bias (cid:122) LCD driver active in power save mode for low power operation (cid:122) Software selectable low power waveform (cid:122) Flexible selection of frame frequency (cid:122) Programmable blink mode and frequency on two segment terminals (cid:122) Uses Only 32 kHz RTC clock source (cid:122) On-chip LCD power supply (cid:122) Software contrast adjustment control (cid:122) Equal source and sink capability to Increase glass life time (cid:122) Extended interrupt mode for display update or wake-up from sleep mode 28.2 Overview The LCD controller is intended for monochrome passive liquid crystal display (LCD) with up to 4 Common terminals and up to 40 Segments terminals. If the application does not need all the LCD segments available on the XMEGA, up to 16 of the unused LCD pins can be used as general purpose I/O pins. The LCD controller can be clocked by an internal or an external asynchronous 32kHz clock source. This 32kHz oscillator source selection is the same as for the real time counter (RTC). Dedicated Low Power Waveform, Contrast Control, Extended Interrupt Mode, Selectable Frame Frequency and Blink functionality are supported to offload the CPU, reduce interrupts and reduce power consumption. To reduce hardware design complexity, the LCD includes integrated LCD buffers, an integrated power supply voltage and an innovative SWAP mode. Using SWAP mode, the hardware designers have more flexibility during board layout as they can rearrange the pin sequence on Segment and/or Common Terminal Buses. Figure 28-1. LCD overview Character Timing Control&Swap Mapping SEG[24:0] Shadow Analog Display Display Switch Memory Memory Array COM[3:0] VLCD LCDPower BIAS1 Supply BIAS2 CAPH CAPL XMEGA B3 [DATASHEET] 49 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

29. ADC – 12-bit Analog to Digital Converter 29.1 Features (cid:122) One Analog to Digital Converters (ADC) (cid:122) 12-bit resolution (cid:122) Up to 300 thousand samples per second (cid:122) Down to 2.3µs conversion time with 8-bit resolution (cid:122) Down to 3.35µs conversion time with 12-bit resolution (cid:122) Differential and single-ended input (cid:122) Up to 16 single-ended inputs (cid:122) 16x4 differential inputs without gain (cid:122) 16x4 differential input with gain (cid:122) Built-in differential gain stage (cid:122) 1/2x, 1x, 2x, 4x, 8x, 16x, 32x, and 64x gain options (cid:122) Single, continuous and scan conversion options (cid:122) Three internal inputs (cid:122) Internal temperature sensor (cid:122) AV voltage divided by 10 CC (cid:122) 1.1V bandgap voltage (cid:122) Internal and external reference options (cid:122) Compare function for accurate monitoring of user defined thresholds (cid:122) Optional event triggered conversion for accurate timing (cid:122) Optional DMA transfer of conversion results (cid:122) Optional interrupt/event on compare result 29.2 Overview The ADC converts analog signals to digital values. The ADC has 12-bit resolution and is capable of converting up to 300 thousand samples per second (KSPS). The input selection is flexible, and both single-ended and differential measurements can be done. For differential measurements, an optional gain stage is available to increase the dynamic range. In addition, several internal signal inputs are available. The ADC can provide both signed and unsigned results. The ADC measurements can either be started by application software or an incoming event from another peripheral in the device. The ADC measurements can be started with predictable timing, and without software intervention. It is possible to use DMA to move ADC results directly to memory or peripherals when conversions are done. Both internal and external reference voltages can be used. An integrated temperature sensor is available for use with the ADC. The output from the AV /10 and the bandgap voltage can also be measured by the ADC. CC The ADC has a compare function for accurate monitoring of user defined thresholds with minimum software intervention required. XMEGA B3 [DATASHEET] 50 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

Figure 29-1. ADC overview Compare ADC0 (cid:129) Register (cid:129) (cid:129) V < INP ADC15 > Threshold (IntReq) Internal ADC CH0Result signals ADC0 (cid:129) V (cid:129) INN (cid:129) ADC7 Internal1.00V InternalAVCC/1.6V InternalAVCC/2 Reference AREFA Voltage AREFB The ADC may be configured for 8- or 12-bit result, reducing the minimum conversion time (propagation delay) from 3.35µs for 12-bit to 2.3µs for 8-bit result. ADC conversion results are provided left- or right adjusted with optional ‘1’ or ‘0’ padding. This eases calculation when the result is represented as a signed integer (signed 16-bit number). PORTB has one ADC. Notation of this peripheral is ADCB. XMEGA B3 [DATASHEET] 51 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

30. AC – Analog Comparator 30.1 Features (cid:122) Two Analog Comparators (AC) (cid:122) Selectable hysteresis (cid:122) No (cid:122) Small (cid:122) Large (cid:122) Analog comparator output available on pin (cid:122) Flexible input selection (cid:122) All pins on the port (cid:122) Bandgap reference voltage (cid:122) A 64-level programmable voltage scaler of the internal AV voltage CC (cid:122) Interrupt and event generation on: (cid:122) Rising edge (cid:122) Falling edge (cid:122) Toggle (cid:122) Window function interrupt and event generation on: (cid:122) Signal above window (cid:122) Signal inside window (cid:122) Signal below window (cid:122) Constant current source with configurable output pin selection 30.2 Overview The analog comparator (AC) compares the voltage levels on two inputs and gives a digital output based on this comparison. The analog comparator may be configured to generate interrupt requests and/or events upon several different combinations of input change. One important property of the analog comparator’s dynamic behavior is the hysteresis. This parameter may be adjusted in order to achieve the optimal operation for each application. The input selection includes analog port pins, several internal signals, and a 64-level programmable voltage scaler. The analog comparator output state can also be output on a pin for use by external devices. A constant current source can be enabled and output on a selectable pin. This can be used to replace, for example, external resistors used to charge capacitors in capacitive touch sensing applications. The analog comparators are always grouped in pairs on each port. These are called analog comparator 0 (AC0) and analog comparator 1 (AC1). They have identical behavior, but separate control registers. Used as pair, they can be set in window mode to compare a signal to a voltage range instead of a voltage level. PORTB has one AC pair. Notation is ACB. XMEGA B3 [DATASHEET] 52 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

Figure 30-1. Analog comparator overview PinInput + AC0 AC0OUT PinInput - Hysteresis Enable Interrupt Interrupts Interrupt Sensititivity Voltage ACnMUXCTRL ACnCTRL Mode WINCTRL Control Scaler & Events Window Function Enable Bandgap Hysteresis + PinInput AC1 AC1OUT - PinInput The window function is realized by connecting the external inputs of the two analog comparators in a pair as shown in Figure 30-2. Figure 30-2. Analog comparator window function + AC0 Upper limit of window - Interrupts Interrupt Input signal sensitivity Events control + AC1 Lower limit of window - XMEGA B3 [DATASHEET] 53 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

31. Programming and Debugging 31.1 Features (cid:122) Programming (cid:122) External programming through PDI or JTAG interfaces (cid:122) Minimal protocol overhead for fast operation (cid:122) Built-in error detection and handling for reliable operation (cid:122) Boot loader support for programming through any communication interface (cid:122) Debugging (cid:122) Nonintrusive, real-time, on-chip debug system (cid:122) No software or hardware resources required from device except pin connection (cid:122) Program flow control (cid:122) Go, Stop, Reset, Step Into, Step Over, Step Out, Run-to-Cursor (cid:122) Unlimited number of user program breakpoints (cid:122) Unlimited number of user data breakpoints, break on: (cid:122) Data location read, write, or both read and write (cid:122) Data location content equal or not equal to a value (cid:122) Data location content is greater or smaller than a value (cid:122) Data location content is within or outside a range (cid:122) No limitation on device clock frequency (cid:122) Program and Debug Interface (PDI) (cid:122) Two-pin interface for external programming and debugging (cid:122) Uses the Reset pin and a dedicated pin (cid:122) No I/O pins required during programming or debugging (cid:122) JTAG interface (cid:122) Four-pin, IEEE Std. 1149.1 compliant interface for programming and debugging (cid:122) Boundary scan capabilities according to IEEE Std. 1149.1 (JTAG) 31.2 Overview The Program and Debug Interface (PDI) is an Atmel proprietary interface for external programming and on-chip debugging of a device. The PDI supports fast programming of nonvolatile memory (NVM) spaces; flash, EEPOM, fuses, lock bits, and the user signature row. Debug is supported through an on-chip debug system that offers nonintrusive, real-time debug. It does not require any software or hardware resources except for the device pin connection. Using the Atmel tool chain, it offers complete program flow control and support for an unlimited number of program and complex data breakpoints. Application debug can be done from a C or other high-level language source code level, as well as from an assembler and disassembler level. Programming and debugging can be done through two physical interfaces. The primary one is the PDI physical layer, which is available on all devices. This is a two-pin interface that uses the Reset pin for the clock input (PDI_CLK) and one other dedicated pin for data input and output (PDI_DATA). A JTAG interface is also available on most devices, and this can be used for programming and debugging through the four-pin JTAG interface. The JTAG interface is IEEE Std. 1149.1 compliant, and supports boundary scan. Any external programmer or on-chip debugger/emulator can be directly connected to either of these interfaces. Unless otherwise stated, all references to the PDI assume access through the PDI physical layer. XMEGA B3 [DATASHEET] 54 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

32. Pinout and Pin Functions The device pinout is shown in “Pinout/Block Diagram” on page 4. In addition to general purpose I/O functionality, each pin can have several alternate functions. This will depend on which peripheral is enabled and connected to the actual pin. Only one of the pin functions can be used at time. 32.1 Alternate Pin Function Description The tables below show the notation for all pin functions available and describe its function. 32.1.1 Operation/Power Supply VCC Digital supply voltage AVCC Analog supply voltage GND Ground AGND Analog Ground 32.1.2 Port Interrupt functions SYNC Port pin with full synchronous and limited asynchronous interrupt function ASYNC Port pin with full synchronous and full asynchronous interrupt function 32.1.3 Analog functions ACn Analog Comparator input pin n ACnOUT Analog Comparator n Output ADCn Analog to Digital Converter input pin n AREF Analog Reference input pin 32.1.4 LCD functions SEGn LCD Segment Drive Output n COMn LCD Common Drive Output n VLCD LCD Voltage Multiplier Output BIAS2 LCD Intermediate Voltage 2 Output (VLCD * 2/3) BIAS1 LCD Intermediate Voltage 1 Output (VLCD * 1/3) CAPH LCD High End Of Flying Capacitor CAPL LCD Low End Of Flying Capacitor XMEGA B3 [DATASHEET] 55 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

32.1.5 Timer/Counter and AWEX functions OCnxLS Output Compare Channel x Low Side for Timer/Counter n OCnxHS Output Compare Channel x High Side for Timer/Counter n 32.1.6 Communication functions SCL Serial Clock for TWI SDA Serial Data for TWI SCLIN Serial Clock In for TWI when external driver interface is enabled SCLOUT Serial Clock Out for TWI when external driver interface is enabled SDAIN Serial Data In for TWI when external driver interface is enabled SDAOUT Serial Data Out for TWI when external driver interface is enabled XCKn Transfer Clock for USART n RXDn Receiver Data for USART n TXDn Transmitter Data for USART n SS Slave Select for SPI MOSI Master Out Slave In for SPI MISO Master In Slave Out for SPI SCK Serial Clock for SPI D- Data- for USB D+ Data+ for USB 32.1.7 Oscillators, Clock and Event TOSCn Timer Oscillator pin n XTALn Input/Output for Oscillator pin n CLKOUT Peripheral Clock Output EVOUT Event Channel 0 Output RTCOUT RTC Clock Source Output 32.1.8 Debug/System functions RESET Reset pin PDI_CLK Program and Debug Interface Clock pin PDI_DATA Program and Debug Interface Data pin XMEGA B3 [DATASHEET] 56 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

TCK JTAG Test Clock TDI JTAG Test Data In TDO JTAG Test Data Out TMS JTAG Test Mode Select 32.2 Alternate Pin Functions The tables below show the primary/default function for each pin on a port in the first column, the pin number in the second column, and then all alternate pin functions in the remaining columns. The head row shows what peripheral that enable and use the alternate pin functions. For better flexibility, some alternate functions also have selectable pin locations for their functions, this is noted under the first table where this apply. Table 32-1. Port B - Alternate functions ADCA ADCB PORT B PIN # INTERRUPT POS/GAIN POS/GAIN ADCB ADCB ACB ACB ACB REFB JTAG POS POS NEG GAINNEG POS NEG OUT AGND 55 AVDD 56 PB0 57 SYNC ADC8 ADC0 ADC0 AC0 AC0 AREF PB1 58 SYNC ADC9 ADC1 ADC1 AC1 AC1 PB2 59 SYNC/ASYNC ADC10 ADC2 ADC2 AC2 PB3 60 SYNC ADC11 ADC3 ADC3 AC3 AC3 PB4 61 SYNC ADC12 ADC4 ADC4 AC4 TMS PB5 62 SYNC ADC13 ADC5 ADC5 AC5 AC5 TDI PB6 64 SYNC ADC14 ADC6 ADC6 AC6 AC1OUT TCK PB7 64 SYNC ADC15 ADC7 ADC7 AC7 AC0OUT TDO XMEGA B3 [DATASHEET] 57 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

Table 32-2. Port C - Alternate functions. PIN CLOCKOUT EVENTOUT PORT C # INTERRUPT TCC0(1) AWEXC TCC1 USARTC0(2) SPIC(3) TWIC EXTCLK (4) (5) PC0 1 SYNC OC0A OC0ALS SDA EXTCLKC0 PC1 2 SYNC OC0B OC0AHS XCK0 SCL EXTCLKC1 PC2 3 SYNC/ASYNC OC0C OC0BLS RXD0 EXTCLKC2 PC3 4 SYNC OC0D OC0BHS TXD0 EXTCLKC3 PC4 5 SYNC OC0CLS OC1A SS EXTCLKC4 PC5 6 SYNC OC0CHS OC1B MOSI EXTCLKC5 PC6 7 SYNC OC0DLS MISO EXTCLKC6 RTCOUT PC7 8 SYNC OC0DHS SCK EXTCLKC7 clk EVOUT PER Notes: 1. Pin mapping of all TC0 can optionally be moved to high nibble of port. 2. Pin mapping of all USART0 can optionally be moved to high nibble of port. 3. Pins MOSI and SCK for all SPI can optionally be swapped. 4. CLKOUT can optionally be moved between port C and E and between pin 4 and 7. 5. EVOUT can optionally be moved between port C and E and between pin 4 and 7. Table 32-3. Port D - Alternate functions. PORT D PIN # INTERRUPT USBD GND 9 VCC 10 PD0 11 SYNC D- PD1 12 SYNC D+ Table 32-4. Program and Debug functions. PROG PIN # INTERRUPT PROG RESET 13 PDI_CLK PDI 14 PDI_DATA Table 32-5. LCD LCD(1)(2) PIN # INTERRUPT(1) GPIO(1) BLINK(1) GND 15 VCC 16 SEG24 17 SYNC PG0 SEG23 18 SYNC PG1 SEG22 19 SYNC/ASYNC PG2 SEG21 20 SYNC PG3 SEG20 21 SYNC PG4 SEG19 22 SYNC PG5 XMEGA B3 [DATASHEET] 58 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

LCD(1)(2) PIN # INTERRUPT(1) GPIO(1) BLINK(1) SEG18 23 SYNC PG6 SEG17 24 SYNC PG7 SEG16 25 SYNC PM0 SEG15 26 SYNC PM1 SEG14 27 SYNC/ASYNC PM2 SEG13 28 SYNC PM3 SEG12 29 SYNC PM4 SEG11 30 SYNC PM5 SEG10 31 SYNC PM6 SEG9 32 SYNC PM7 SEG8 33 SEG7 34 SEG6 35 SEG5 36 SEG4 37 SEG3 38 SEG2 39 SEG1 40 BLINK SEG0 41 BLINK GND 42 VCC 43 BIAS1 44 BIAS2 45 VLCD 46 CAPL 47 CAPH 48 COM0 49 COM1 50 COM2 51 COM3 52 Notes: 1. Pin mapping of all Segment terminals (SEGn) can be optionnaly swapped. Interrupt, GPIO and Blink functions will be automatically swapped. 2. Pin mapping of all Common terminals (COMn) can be optionnaly swapped. XMEGA B3 [DATASHEET] 59 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

Table 32-6. Port R- Alternate functions. PORT R PIN # INTERRUPT XTAL TOSC PR0 53 SYNC XTAL2 TOSC2 PR1 54 SYNC XTAL1 TOSC1 XMEGA B3 [DATASHEET] 60 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

33. Peripheral Module Address Map The address maps show the base address for each peripheral and module in XMEGA B3. For complete register description and summary for each peripheral module, refer to the XMEGA B Manual. Table 33-1. Peripheral module address map. Base address Name Description 0x0000 GPIO General Purpose IO Registers 0x0010 VPORT0 Virtual Port 0 0x0014 VPORT1 Virtual Port 1 0x0018 VPORT2 Virtual Port 2 0x001C VPORT3 Virtual Port 3 0x0030 CPU CPU 0x0040 CLK Clock Control 0x0048 SLEEP Sleep Controller 0x0050 OSC Oscillator Control 0x0060 DFLLRC32M DFLL for the 32MHz Internal Oscillator 0x0068 DFLLRC2M DFLL for the 2MHz Internal Oscillator 0x0070 PR Power Reduction 0x0078 RST Reset Controller 0x0080 WDT Watch-Dog Timer 0x0090 MCU MCU Control 0x00A0 PMIC Programmable Multilevel Interrupt Controller 0x00B0 PORTCFG Port Configuration 0x00C0 AES AES Module 0x00D0 CRC CRC Module 0x0100 DMA DMA Controller 0x0180 EVSYS Event System 0x01C0 NVM Non Volatile Memory (NVM) Controller 0x0200 ADCA Analog to Digital Converter on port A 0x0240 ADCB Analog to Digital Converter on port B 0x0380 ACA Analog Comparator pair on port A 0x0390 ACB Analog Comparator pair on port B 0x0400 RTC Real Time Counter 0x0480 TWIC Two Wire Interface on port C 0x04C0 USB USB Device 0x0620 PORTB Port B 0x0640 PORTC Port C 0x0660 PORTD Port D 0x06C0 PORTG Port G 0x0760 PORTM Port M 0x07E0 PORTR Port R 0x0800 TCC0 Timer/Counter 0 on port C XMEGA B3 [DATASHEET] 61 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

Base address Name Description 0x0840 TCC1 Timer/Counter 1 on port C 0x0880 AWEXC Advanced Waveform Extension on port C 0x0890 HIRESC High Resolution Extension on port C 0x08A0 USARTC0 USART 0 on port C 0x08C0 SPIC Serial Peripheral Interface on port C 0x08F8 IRCOM Infrared Communication Module 0x0D00 LCD Liquid Crystal Display XMEGA B3 [DATASHEET] 62 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

34. Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks Arithmetic and Logic Instructions ADD Rd, Rr Add without Carry Rd ← Rd + Rr Z,C,N,V,S,H 1 ADC Rd, Rr Add with Carry Rd ← Rd + Rr + C Z,C,N,V,S,H 1 ADIW Rd, K Add Immediate to Word Rd ← Rd + 1:Rd + K Z,C,N,V,S 2 SUB Rd, Rr Subtract without Carry Rd ← Rd - Rr Z,C,N,V,S,H 1 SUBI Rd, K Subtract Immediate Rd ← Rd - K Z,C,N,V,S,H 1 SBC Rd, Rr Subtract with Carry Rd ← Rd - Rr - C Z,C,N,V,S,H 1 SBCI Rd, K Subtract Immediate with Carry Rd ← Rd - K - C Z,C,N,V,S,H 1 SBIW Rd, K Subtract Immediate from Word Rd + 1:Rd ← Rd + 1:Rd - K Z,C,N,V,S 2 AND Rd, Rr Logical AND Rd ← Rd • Rr Z,N,V,S 1 ANDI Rd, K Logical AND with Immediate Rd ← Rd • K Z,N,V,S 1 OR Rd, Rr Logical OR Rd ← Rd v Rr Z,N,V,S 1 ORI Rd, K Logical OR with Immediate Rd ← Rd v K Z,N,V,S 1 EOR Rd, Rr Exclusive OR Rd ← Rd ⊕ Rr Z,N,V,S 1 COM Rd One’s Complement Rd ← $FF - Rd Z,C,N,V,S 1 NEG Rd Two’s Complement Rd ← $00 - Rd Z,C,N,V,S,H 1 SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V,S 1 CBR Rd,K Clear Bit(s) in Register Rd ← Rd • ($FFh - K) Z,N,V,S 1 INC Rd Increment Rd ← Rd + 1 Z,N,V,S 1 DEC Rd Decrement Rd ← Rd - 1 Z,N,V,S 1 TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V,S 1 CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V,S 1 SER Rd Set Register Rd ← $FF None 1 MUL Rd,Rr Multiply Unsigned R1:R0 ← Rd x Rr (UU) Z,C 2 MULS Rd,Rr Multiply Signed R1:R0 ← Rd x Rr (SS) Z,C 2 MULSU Rd,Rr Multiply Signed with Unsigned R1:R0 ← Rd x Rr (SU) Z,C 2 FMUL Rd,Rr Fractional Multiply Unsigned R1:R0 ← Rd x Rr<<1 (UU) Z,C 2 FMULS Rd,Rr Fractional Multiply Signed R1:R0 ← Rd x Rr<<1 (SS) Z,C 2 FMULSU Rd,Rr Fractional Multiply Signed with Unsigned R1:R0 ← Rd x Rr<<1 (SU) Z,C 2 DES K Data Encryption if (H = 0) then R15:R0 ← Encrypt(R15:R0, K) 1/2 else if (H = 1) then R15:R0 ← Decrypt(R15:R0, K) Branch instructions RJMP k Relative Jump PC ← PC + k + 1 None 2 IJMP Indirect Jump to (Z) PC(15:0) ← Z, None 2 PC(21:16) ← 0 EIJMP Extended Indirect Jump to (Z) PC(15:0) ← Z, None 2 PC(21:16) ← EIND JMP k Jump PC ← k None 3 RCALL k Relative Call Subroutine PC ← PC + k + 1 None 2 / 3 (1) XMEGA B3 [DATASHEET] 63 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

Mnemonics Operands Description Operation Flags #Clocks ICALL Indirect Call to (Z) PC(15:0) ← Z, None 2 / 3 (1) PC(21:16) ← 0 EICALL Extended Indirect Call to (Z) PC(15:0) ← Z, None 3 (1) PC(21:16) ← EIND CALL k call Subroutine PC ← k None 3 / 4 (1) RET Subroutine Return PC ← STACK None 4 / 5 (1) RETI Interrupt Return PC ← STACK I 4 / 5 (1) CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1 / 2 / 3 CP Rd,Rr Compare Rd - Rr Z,C,N,V,S,H 1 CPC Rd,Rr Compare with Carry Rd - Rr - C Z,C,N,V,S,H 1 CPI Rd,K Compare with Immediate Rd - K Z,C,N,V,S,H 1 SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b) = 0) PC ← PC + 2 or 3 None 1 / 2 / 3 SBRS Rr, b Skip if Bit in Register Set if (Rr(b) = 1) PC ← PC + 2 or 3 None 1 / 2 / 3 SBIC A, b Skip if Bit in I/O Register Cleared if (I/O(A,b) = 0) PC ← PC + 2 or 3 None 2 / 3 / 4 SBIS A, b Skip if Bit in I/O Register Set If (I/O(A,b) =1) PC ← PC + 2 or 3 None 2 / 3 / 4 BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC ← PC + k + 1 None 1 / 2 BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC ← PC + k + 1 None 1 / 2 BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1 / 2 BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1 / 2 BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1 / 2 BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1 / 2 BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1 / 2 BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1 / 2 BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1 / 2 BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1 / 2 BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1 None 1 / 2 BRLT k Branch if Less Than, Signed if (N ⊕ V= 1) then PC ← PC + k + 1 None 1 / 2 BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1 / 2 BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1 / 2 BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1 None 1 / 2 BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1 / 2 BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1 / 2 BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1 / 2 BRIE k Branch if Interrupt Enabled if (I = 1) then PC ← PC + k + 1 None 1 / 2 BRID k Branch if Interrupt Disabled if (I = 0) then PC ← PC + k + 1 None 1 / 2 Data transfer instructions MOV Rd, Rr Copy Register Rd ← Rr None 1 MOVW Rd, Rr Copy Register Pair Rd+1:Rd ← Rr+1:Rr None 1 LDI Rd, K Load Immediate Rd ← K None 1 XMEGA B3 [DATASHEET] 64 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

Mnemonics Operands Description Operation Flags #Clocks LDS Rd, k Load Direct from data space Rd ← (k) None 2 (1)(2) LD Rd, X Load Indirect Rd ← (X) None 1 (1)(2) LD Rd, X+ Load Indirect and Post-Increment Rd ← (X) None 1 (1)(2) X ← X + 1 LD Rd, -X Load Indirect and Pre-Decrement X ← X - 1, ← X - 1 None 2 (1)(2) Rd ← (X) ← (X) LD Rd, Y Load Indirect Rd ← (Y) ← (Y) None 1 (1)(2) LD Rd, Y+ Load Indirect and Post-Increment Rd ← (Y) None 1 (1)(2) Y ← Y + 1 LD Rd, -Y Load Indirect and Pre-Decrement Y ← Y - 1 None 2 (1)(2) Rd ← (Y) LDD Rd, Y+q Load Indirect with Displacement Rd ← (Y + q) None 2 (1)(2) LD Rd, Z Load Indirect Rd ← (Z) None 1 (1)(2) LD Rd, Z+ Load Indirect and Post-Increment Rd ← (Z), None 1 (1)(2) Z ← Z+1 LD Rd, -Z Load Indirect and Pre-Decrement Z ← Z - 1, None 2 (1)(2) Rd ← (Z) LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2 (1)(2) STS k, Rr Store Direct to Data Space (k) ← Rd None 2 (1) ST X, Rr Store Indirect (X) ← Rr None 1 (1) ST X+, Rr Store Indirect and Post-Increment (X) ← Rr, None 1 (1) X ← X + 1 ST -X, Rr Store Indirect and Pre-Decrement X ← X - 1, None 2 (1) (X) ← Rr ST Y, Rr Store Indirect (Y) ← Rr None 1 (1) ST Y+, Rr Store Indirect and Post-Increment (Y) ← Rr, None 1 (1) Y ← Y + 1 ST -Y, Rr Store Indirect and Pre-Decrement Y ← Y - 1, None 2 (1) (Y) ← Rr STD Y+q, Rr Store Indirect with Displacement (Y + q) ← Rr None 2 (1) ST Z, Rr Store Indirect (Z) ← Rr None 1 (1) ST Z+, Rr Store Indirect and Post-Increment (Z) ← Rr None 1 (1) Z ← Z + 1 ST -Z, Rr Store Indirect and Pre-Decrement Z ← Z - 1 None 2 (1) STD Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None 2 (1) LPM Load Program Memory R0 ← (Z) None 3 LPM Rd, Z Load Program Memory Rd ← (Z) None 3 LPM Rd, Z+ Load Program Memory and Post-Increment Rd ← (Z), None 3 Z ← Z + 1 ELPM Extended Load Program Memory R0 ← (RAMPZ:Z) None 3 ELPM Rd, Z Extended Load Program Memory Rd ← (RAMPZ:Z) None 3 ELPM Rd, Z+ Extended Load Program Memory and Post- Rd ← (RAMPZ:Z), None 3 Increment Z ← Z + 1 SPM Store Program Memory (RAMPZ:Z) ← R1:R0 None - SPM Z+ Store Program Memory and Post-Increment (RAMPZ:Z) ← R1:R0, None - by 2 Z ← Z + 2 XMEGA B3 [DATASHEET] 65 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

Mnemonics Operands Description Operation Flags #Clocks IN Rd, A In From I/O Location Rd ← I/O(A) None 1 OUT A, Rr Out To I/O Location I/O(A) ← Rr None 1 PUSH Rr Push Register on Stack STACK ← Rr None 1 (1) POP Rd Pop Register from Stack Rd ← STACK None 2 (1) XCH Z, Rd Exchange RAM location Temp ← Rd, None 2 Rd ← (Z), (Z) ← Temp LAS Z, Rd Load and Set RAM location Temp ← Rd, None 2 Rd ← (Z), (Z) ← Temp v (Z) LAC Z, Rd Load and Clear RAM location Temp ← Rd, None 2 Rd ← (Z), (Z) ← ($FFh – Rd) • (Z) LAT Z, Rd Load and Toggle RAM location Temp ← Rd, None 2 Rd ← (Z), (Z) ← Temp ⊕ (Z) Bit and bit-test instructions LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Z,C,N,V,H 1 Rd(0) ← 0, C ← Rd(7) LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Z,C,N,V 1 Rd(7) ← 0, C ← Rd(0) ROL Rd Rotate Left Through Carry Rd(0) ← C, Z,C,N,V,H 1 Rd(n+1) ← Rd(n), C ← Rd(7) ROR Rd Rotate Right Through Carry Rd(7) ← C, Z,C,N,V 1 Rd(n) ← Rd(n+1), C ← Rd(0) ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1 SWAP Rd Swap Nibbles Rd(3..0) ↔ Rd(7..4) None 1 BSET s Flag Set SREG(s) ← 1 SREG(s) 1 BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1 SBI A, b Set Bit in I/O Register I/O(A, b) ← 1 None 1 CBI A, b Clear Bit in I/O Register I/O(A, b) ← 0 None 1 BST Rr, b Bit Store from Register to T T ← Rr(b) T 1 BLD Rd, b Bit load from T to Register Rd(b) ← T None 1 SEC Set Carry C ← 1 C 1 CLC Clear Carry C ← 0 C 1 SEN Set Negative Flag N ← 1 N 1 CLN Clear Negative Flag N ← 0 N 1 SEZ Set Zero Flag Z ← 1 Z 1 CLZ Clear Zero Flag Z ← 0 Z 1 SEI Global Interrupt Enable I ← 1 I 1 CLI Global Interrupt Disable I ← 0 I 1 SES Set Signed Test Flag S ← 1 S 1 CLS Clear Signed Test Flag S ← 0 S 1 XMEGA B3 [DATASHEET] 66 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

Mnemonics Operands Description Operation Flags #Clocks SEV Set Two’s Complement Overflow V ← 1 V 1 CLV Clear Two’s Complement Overflow V ← 0 V 1 SET Set T in SREG T ← 1 T 1 CLT Clear T in SREG T ← 0 T 1 SEH Set Half Carry Flag in SREG H ← 1 H 1 CLH Clear Half Carry Flag in SREG H ← 0 H 1 MCU control instructions BREAK Break (See specific descr. for BREAK) None 1 NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep) None 1 WDR Watchdog Reset (see specific descr. for WDR) None 1 Notes: 1. Cycle times for Data memory accesses assume internal memory accesses, and are not valid for accesses via the external RAM interface. 2. One extra cycle must be added when accessing Internal SRAM. XMEGA B3 [DATASHEET] 67 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

35. Packaging information 35.1 64A PIN 1 B e PIN 1 IDENTIFIER E1 E D1 D C 0°~7° A1 A2 A L COMMON DIMENSIONS (Unit of measure = mm) SYMBOL MIN NOM MAX NOTE A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 15.75 16.00 16.25 D1 13.90 14.00 14.10 Note 2 E 15.75 16.00 16.25 Notes: E1 13.90 14.00 14.10 Note 2 1.This package conforms to JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable B 0.30 – 0.45 protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum C 0.09 – 0.20 plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10mm maximum. L 0.45 – 0.75 e 0.80 TYP 2010-10-20 TITLE DRAWING NO. REV. 2325 Orchard Parkway 64A, 64-lead, 14 x 14mm Body Size, 1.0mm Body Thickness, San Jose, CA 95131 64A C 0.8mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) XMEGA B3 [DATASHEET] 68 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

35.2 64M2 D Marked Pin# 1 ID E C SEATING PLANE A1 TOP VIEW A3 A K 0.08 C L Pin #1 Corner SIDE VIEW D2 1 2 Option A Pin #1 Triangle 3 COMMON DIMENSIONS (Unit of Measure = mm) E2 SYMBOL MIN NOM MAX NOTE Option B Pin #1 A 0.80 0.90 1.00 Chamfer (C 0.30) A1 – 0.02 0.05 A 3 0.20 REF b 0.1 8 0.25 0.30 D 8.90 9.00 9.10 Option C K b e PNiont c#h1 D 2 7.50 7.6 5 7.80 (0.20 R) E 8.90 9.00 9.10 BOTTOM VIEW E 2 7.5 0 7.65 7.80 e 0.50 B SC L 0.35 0.40 0.45 K 0.20 0.27 0.40 Notes: 1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD. 2. Dimension and tolerance conform to ASMEY14.5M-1994. 2014-05-30 TITLE DRAWING NO. REV. 2325 Orchard Parkway 64M2, 64-pad, 9 x 9 x 1.0mm Body, Lead Pitch 0.50mm, San Jose, CA 95131 64M2 F 7.65mm Exposed Pad, Quad Flat No LeadPackage (QFN) XMEGA B3 [DATASHEET] 69 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

35.3 64P2 XMEGA B3 [DATASHEET] 70 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

36. Electrical Characteristics All typical values are measured at T = 25°C unless other temperature condition is given. All minimum and maximum values are valid across operating temperature and voltage unless other conditions are given. 36.1 Absolute Maximum Ratings Stresses beyond those listed in Table 36-1 on page 71 under may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 36-1. Absolute maximum ratings. Symbol Parameter Min. Typ. Max. Units VCC Power supply voltage -0.3 4 V I Current into a Vcc pin 200 mA VCC I Current out of a Gnd pin 200 mA GND V Pin voltage with respect to Gnd and VCC -0.5 Vcc+0.5 V PIN I I/O pin sink/source current -25 25 mA PIN T Storage temperature -65 150 °C A T Junction temperature 150 °C j 36.2 General Operating Ratings The device must operate within the ratings listed in Table 36-2 on page 71 in order for all other electrical characteristics and typical characteristics of the device to be guaranteed and valid. Table 36-2. General operating conditions. Symbol Parameter Min. Typ. Max. Units VCC Power supply voltage 1.6 3.6 V AVCC Power supply voltage 1.6 3.6 V T Temperature range -40 85 °C A T Junction temperature -40 105 °C j Table 36-3. Operating voltage and frequency. Symbol Parameter Condition Min Typ. Max. Units V = 1.6V 0 12 CC V = 1.8V 0 12 CC Clk CPU clock frequency MHz CPU V = 2.7V 0 32 CC V = 3.6V 0 32 CC The maximum System clock frequency of the Atmel® AVR® XMEGA B3 devices is depending on V . As shown in Figure CC 36-1 on page 72 the Frequency vs. V curve is linear between 1.8V<V <2.7V. CC CC XMEGA B3 [DATASHEET] 71 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

Figure 36-1. Maximum Frequency vs. Vcc MHz 32 Safe Operating Area 12 1.6 1.8 2.7 3.6 V XMEGA B3 [DATASHEET] 72 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

36.3 DC Characteristics Table 36-4. Current Consumption for active and sleep modes. Symbol Parameter Condition Min Typ Max Units V = 1.8V 150 CC 32kHz, Ext. Clk V = 3.0V 320 CC V = 1.8V 350 µA CC 1MHz, Ext. Clk Active Power V = 3.0V 700 consumption(1) CC V = 1.8V 650 800 CC 2MHz, Ext. Clk 1.0 1.6 V = 3.0V mA CC 32MHz, Ext. Clk 10 15 V = 1.8V 4.0 CC 32kHz, Ext. Clk V = 3.0V 8.0 CC V = 1.8V 80 CC 1MHz, Ext. Clk µA Idle Power V = 3.0V 150 consumption(1) CC V = 1.8V 160 250 CC 2MHz, Ext. Clk I 300 600 CC V = 3.0V CC 32MHz, Ext. Clk 4.7 7 mA T=25°C 0.1 1.0 V = 3.0V CC T=85°C 2.1 5 Power-down power WDT and Sampled BOD enabled, T=25°C V = 1.8V 1.2 2.5 µA CC consumption WDT and Sampled BOD enabled, T=25°C 1.3 3 V = 3.0V CC WDT and Sampled BOD enabled, T=85°C 3.1 7 V = 1.8V 1.2 RTC on ULP clock, WDT and sampled BOD CC enabled, T=25°C V = 3.0V 1.3 CC Power-save V = 1.8V 0.8 RTC on 1.024kHz low power 32.768kHz CC power µA TOSC, T=25°C consumption(2) VCC = 3.0V 0.9 V = 1.8V 1.3 RTC from low power 32.768kHz TOSC, CC T=25°C V = 3.0V 1.6 CC XMEGA B3 [DATASHEET] 73 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

Symbol Parameter Condition Min Typ Max Units V = 1.8V 4.6 RTC on ULP clock, WDT, sampled BOD and CC LCD enabled, and all pixels ON, T=25°C V = 3.0V 5.2 CC Power-save RTC on 1.024kHz low power 32.768kHz V = 1.8V 3.9 CC power TOSC, LCD enabled and all pixels ON µA I consumption(2) T=25°C VCC = 3.0V 4.3 CC V = 1.8V 4.0 RTC from low power 32.768kHz TOSC, LCD CC enabled and all pixels ON, T=25°C V = 3.0V 4.5 CC Reset power Current through RESET pin substracted V = 3.0V 420 µA consumption CC Notes: 1. All Power Reduction Registers set. 2. Maximum limits are based on characterization and not tested in production. XMEGA B3 [DATASHEET] 74 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

Table 36-5. Current Consumption for modules and peripherals. Symbol Parameter Condition(1) Min Typ Max Units ULP oscillator 1.0 µA 32.768kHz int. 26 µA oscillator 80 2MHz int. µA oscillator DFLL enabled with 32.768kHz int. osc. as reference 112 255 32MHz int. µA oscillator DFLL enabled with 32.768kHz int. osc. as reference 444 PLL Multiplication factor = 20x 316 µA Watchdog Timer 1 µA Continuous mode 126 BOD µA Sampled mode, include ULP oscillator 1.3 All pixels OFF 3.0 Contrast min 100 pixels ON 3.0 All pixels ON 3.0 All pixels OFF 3.3 No pixel load Contrast typ 100 pixels ON 3.4 ICC LCD(2) All pixels ON 3.4 µA All pixels OFF 3.8 Contrast max 100 pixels ON 3.9 All pixels ON 3.9 All pixels OFF 3.7 22pF pixel load Contrast typ All pixels ON 4.3 Internal 1.0V 100 µA reference Temperature 100 µA sensor 1.3 CURRLIMIT = LOW 1.1 16ksps VREF = Ext ref CURRLIMIT = MEDIUM 1.0 ADC CURRLIMIT = HIGH 0.9 mA 75ksps 1.7 VREF = Ext ref 300ksps 3.1 VREF = Ext ref XMEGA B3 [DATASHEET] 75 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

Symbol Parameter Condition(1) Min Typ Max Units AC 440 µA DMA 615Kbps between I/O registers and SRAM 115 µA I CC USART Rx and Tx enabled, 9600 BAUD 9 µA Flash memory and EEPROM programming 4.4 mA Notes: 1. .All parameters measured as the difference in current consumption between module enabled and disabled. All data at V = 3.0V, ClkSYS = 1MHz External CC clock without prescaling, T = 25°C unless other conditiond are given. 2. LCD configuration: internal voltage generation, 32Hz low power frame rate, 1/3 bias, clocked by low power 32.768kHz TOSC. 36.4 Wake-up time from sleep modes Table 36-6. Device wake-up time from sleep modes with various system clock sources. Symbol Parameter Condition Min Typ Max Units External 2MHz clock 2 32.768kHz internal oscillator 120 Wake-up time from Idle, Standby, and Extend Standby 2MHz internal oscillator 2 32MHz internal oscillator 0.2 t µs wakeup External 2MHz clock 4.5 32.768kHz internal oscillator 320 Wake-up time from Power-save and Power-down mode 2MHz internal oscillator 9 32MHz internal oscillator 5 Note: 1. The wake-up time is the time from the wake-up request is given until the peripheral clock is available on pin, see Figure 36-2 on page 76. All peripherals and modules start execution from the first clock cycle, expect the CPU that is halted for four clock cycles before program execution starts. Figure 36-2. Wake-up time definition. Wake-up time Wake-up request Clock output XMEGA B3 [DATASHEET] 76 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

36.5 I/O Pin Characteristics The I/O pins complies with the JEDEC LVTTL and LVCSMOS specification and the high- and low level input and output voltage limits reflect or exceed this specification. Table 36-7. I/O Pin Characteristics. Symbol Parameter Condition Min Typ Max Units (1)I / OH I/O pin source/sink current -20 20 mA (2)I OL V = 3.0 - 3.6V 0.6*V V +0.3 CC CC CC V High Level Input Voltage V = 2.3 - 2.7V 0.6*V V +0.3 V IH CC CC CC V = 1.6 - 2.3V 0.6*V V +0.3 CC CC CC V = 3.0 - 3.6V -0.3 0.4*V CC CC V Low Level Input Voltage V = 2.3 - 2.7V -0.3 0.4*V V IL CC CC V = 1.6 - 2.3V -0.3 0.4*V CC CC V = 3.3V I = 15mA 0.4 0.76 CC OL V Output Low Voltage GPIO V = 3.0V I = 10mA 0.26 0.64 V OL CC OL V = 1.8V I = 5mA 0.17 0.46 CC OL V = 3.3V I = -8mA 2.6 2.8 CC OH V Output High Voltage GPIO V = 3.0V I = -6mA 2.1 2.6 V OH CC OH V = 1.8V I = -2mA 1.4 1.6 CC OH I Input Leakage Current I/O pin <0.01 1 µA IN R Pull/Buss keeper Resistor 25 kΩ P R Reset pin Pull-up Resistor 25 kW RST 4 (3)t Rise time No load ns r slew rate limitation 7 Notes: 1. The sum of all I for PORTA and PORTB must not exceed 100mA. OH The sum of all I for PORTC, PORTD, PORTE and PDI must for each port not exceed 200mA OH TThe sum of all I for PORTG and PORTM must not exceed 100mA. OH The sum of all I for PORTR must not exceed 100mA. OH 2. The sum of all I for PORTA and PORTB must not exceed 100mA. OL The sum of all I for PORTC, PORTD, PORTE must for each port not exceed 200mA. OL The sum of all I for PORTG and PORTM must not exceed 100mA. OL The sum of all I PORTR must not exceed 100mA. OL 3. From design simulations XMEGA B3 [DATASHEET] 77 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

36.6 Liquid Crystal Display Characteristics Table 36-8. Liquid crystal display characteristics. Symbol Parameter Condition Min Typ Max Units SEG Segment terminal pins 0 40 COM Common terminal pins 0 4 f LCD frame frequency F(clk )=32.768kHz 31.25 512 Hz Frame LCD C Flying capacitor 100 nF Flying Contrast Contrast adjustment -0.5 0 0.5 V 3 LCD CFlying = 0.1µF V BIAS2 LCD regulated voltages 0.1µF on V , BIAS2 and 2*V /3 LCD LCD BIAS1 pins BIAS1 V /3 LCD R Common output impedance COM0 to COM3(1) 0.25 0.5 1 COM kΩ R Segment output impedance SEG0 to SEG39(1) 2 4 8 SEG Notes: 1. Applies to Static and 1/3 bias 36.7 ADC characteristics Table 36-9. Power supply, reference and input range. Symbol Parameter Condition Min. Typ. Max. Units AVCC Analog supply voltage V - 0.3 V + 0.3 V CC CC VREF Reference voltage 1 AV - 0.6 V CC R Input resistance Switched 4.5 kΩ in C Input capacitance Switched 5 pF in R Reference input resistance (leakage only) >10 MΩ AREF C Reference input capacitance Static load 7 pF AREF Vin Input range 0 V V REF Vin Conversion range Differential mode, Vinp - Vinn -0.95*V 0.95*V V REF REF Vin Conversion range Single ended unsigned mode, Vinp -0.05*V 0.95*V V REF REF Table 36-10. Clock and timing. Symbol Parameter Condition Min. Typ. Max. Units Maximum is 1/4 of Peripheral clock 100 1800 frequency Clk ADC Clock frequency kHz ADC Measuring internal signals 125 f Sample rate 16 300 ksps ClkADC XMEGA B3 [DATASHEET] 78 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

Symbol Parameter Condition Min. Typ. Max. Units Current limitation (CURRLIMIT) off 16 300 CURRLIMIT = LOW 250 f Sample rate ksps ADC CURRLIMIT = MEDIUM 150 CURRLIMIT = HIGH 50 Sampling Time 1/2 Clk cycle 0.25 5 µs ADC (RES+2)/2+(GAIN !=0) Clk Conversion time (latency) 6 10 ADC RES (Resolution) = 8 or 12 cycles Clk Start-up time ADC clock cycles 12 24 ADC cycles Clk ADC ADC settling time After changing reference or input mode 7 7 cycles Table 36-11. Accuracy characteristics. Symbol Parameter Condition(2) Min. Typ. Max. Units Differential 8 12 12 RES Resolution 12-bit resolution Single ended signed 7 11 11 Bits Single ended unsigned 8 12 12 16kSPS, VREF = 3V 1 16kSPS, VREF = 1V 2 Differential mode 300kSPS, VREF = 3V 1 INL(1) Integral non-linearity lsb 300kSPS, VREF = 1V 2 16kSPS, VREF = 3.0V 1 1.5 Single ended unsigned mode 16kSPS, VREF = 1.0V 2 3 16kSPS, VREF = 3V 1 16kSPS, VREF = 1V 2 Differential mode 300kSPS, VREF = 3V 1 DNL(1) Differential non-linearity lsb 300kSPS, VREF = 1V 2 16kSPS, VREF = 3.0V 1 1.5 Single ended unsigned mode 16kSPS, VREF = 1.0V 2 3 8 mV Offset Error Differential mode Temperature drift 0.01 mV/K Operating voltage drift 0.25 mV/V XMEGA B3 [DATASHEET] 79 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

Symbol Parameter Condition(2) Min. Typ. Max. Units External reference -5 AVCC/1.6 -5 mV AVCC/2.0 -6 Gain Error Differential mode Bandgap ±10 Temperature drift 0.02 mV/K Operating voltage drift 2 mV/V External reference -8 AVCC/1.6 -8 mV AVCC/2.0 -8 Single ended Gain Error unsigned mode Bandgap ±10 Temperature drift 0.03 mV/K Operating voltage drift 2 mV/V Notes: 1. Maximum numbers are based on characterisation and not tested in production, and valid for 10% to 90% input voltage range. 2. Unless otherwise noted all linearity, offset and gain error numbers are valid under the condition that external VREF is used. Table 36-12. Gain stage characteristics. Symbol Parameter Condition Min. Typ. Max. Units R Input resistance Switched in normal mode 4.0 kΩ in C Input capacitance Switched in normal mode 4.4 pF sample Signal range Gain stage output 0 AV - 0.6 V CC Clk Propagation delay ADC conversion rate 1/2 1 3 ADC cycles Clock rate Same as ADC 100 1800 kHz 0.5x gain, normal mode -1 1x gain, normal mode -1 Gain error % 8x gain, normal mode -1 64x gain, normal mode 10 0.5x gain, normal mode 10 Offset error, 1x gain, normal mode 5 mV input referred 8x gain, normal mode -20 64x gain, normal mode -126 XMEGA B3 [DATASHEET] 80 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

36.8 Analog Comparator Characteristics Table 36-13. Analog comparator characteristics. Symbol Parameter Condition Min. Typ. Max. Units V Input offset voltage 10 mV off I Input leakage current <10 50 nA lk Input voltage range 0.1 AV - 0.1 V CC AC startup time 50 µs V Hysteresis, none V = 1.6V - 3.6V 0 mV hys1 CC V Hysteresis, small V = 1.6V - 3.6V 12 mV hys2 CC V Hysteresis, large V = 1.6V - 3.6V 28 mV hys3 CC V = 3.0V, T= 85°C 22 30 CC t Propagation delay ns delay V = 1.6V - 3.6V 21 40 CC 64-Level Voltage Scaler Integral non- 0.3 0.5 lsb linearity (INL) Current source accuracy after calibration 5 % Current source calibration range Single mode 4 6 µA Current source calibration range Double mode 8 12 µA 36.9 Bandgap and Internal 1.0V Reference Characteristics Table 36-14. Bandgap and internal 1.0V reference characteristics. Symbol Parameter Condition Min Typ Max Units As reference for ADC 1 Clk + 2.5µs PER Startup time µs As input voltage to ADC and AC 1.5 Bandgap voltage 1.1 V INT1V Internal 1.00V reference for ADC T= 85°C, After calibration 0.99 1 1.01 V Variation over voltage and temperature Calibrated at T= 85°C 2.25 % XMEGA B3 [DATASHEET] 81 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

36.10 Brownout Detection Characteristics Table 36-15. Brownout Detection Characteristics(1). Symbol Parameter Condition Min Typ Max Units BOD level 0 falling Vcc T = 85°C, calibrated 1.5 1.6 1.72 BOD level 1 falling Vcc 1.8 BOD level 2 falling Vcc 2.0 BOD level 3 falling Vcc 2.2 V BOD level 4 falling Vcc 2.4 BOD level 5 falling Vcc 2.6 BOD level 6 falling Vcc 2.8 BOD level 7 falling Vcc 3.0 Continuous mode 0.4 t Detection time µs BOD Sampled mode 1000 V Hysteresis 1.6 % HYST Note: 1. BOD is calibrated at 85°C within BOD level 0 values, and BOD level 0 is the default level. 36.11 External Reset Characteristics Table 36-16. External reset characteristics. Symbol Parameter Condition Min Typ Max Units t Minimum reset pulse width 90 1000 ns EXT V = 2.7 - 3.6V 0.50*V CC CC V Reset threshold voltage V RST V = 1.6 - 2.7V 0.40*V CC CC 36.12 Power-on Reset Characteristics Table 36-17. Power-on reset characteristics. Symbol Parameter Condition Min Typ Max Units V falls faster than 1V/ms 0.4 1.0 CC V (1) POR threshold voltage falling V V POT- CC V falls at 1V/ms or slower 0.8 1.3 CC V POR threshold voltage rising V 1.3 1.59 V POT+ CC Note: 1. Both V values are only valid when BOD is disabled. When BOD is enabled the µBOD is enabled, and V =V POT- POT- POT+ XMEGA B3 [DATASHEET] 82 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

36.13 Flash and EEPROM Memory Characteristics Table 36-18. Endurance and data retention. Symbol Parameter Condition Min Typ Max Units 25°C 10K Write/Erase cycles Cycle 85°C 10K Flash 25°C 100 Data retention Year 55°C 25 25°C 100K Write/Erase cycles Cycle 85°C 100K EEPROM 25°C 100 Data retention Year 55°C 25 Table 36-19. Programming time. Symbol Parameter Condition Min Typ(1) Max Units 128KB Flash, EEPROM(2) 75 Chip Erase ms 64KB Flash, EEPROM(2) 55 Page Erase 4 Flash Page Write 4 ms Page Write Automatic Page Erase and Write 8 Page Erase 4 EEPROM Page Write 4 ms Page Write Automatic Page Erase and Write 8 Notes: 1. Programming is timed from the 2MHz internal oscillator. 2. EEPROM is not erased if the EESAVE fuse is programmed. 36.14 Clock and Oscillator Characteristics 36.14.1Calibrated 32.768kHz Internal Oscillator characteristics Table 36-20. Calibrated 32.768kHz internal oscillator characteristics. Symbol Parameter Condition Min Typ Max Units Frequency 32.768 kHz Factory calibrated accuracy T = 85°C, V = 3.0V -0.5 0.5 % CC User calibration accuracy -0.5 0.5 % XMEGA B3 [DATASHEET] 83 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

36.14.2Calibrated 2MHz RC Internal Oscillator characteristics Table 36-21. Calibrated 2MHz internal oscillator characteristics. Symbol Parameter Condition Min Typ Max Units DFLL can tune to this frequency over Frequency range 1.8 2.2 MHz voltage and temperature Factory calibrated frequency 2.0 MHz Factory calibration accuracy T = 85°C, V = 3.0V -1.5 1.5 % CC User calibration accuracy -0.2 0.2 % DFLL calibration stepsize 0.22 % 36.14.3 Calibrated and tunable 32MHz Internal Oscillator characteristics Table 36-22. Calibrated 32MHz internal oscillator characteristics. Symbol Parameter Condition Min Typ Max Units DFLL can tune to this frequency over Frequency range 30 35 voltage and temperature MHz Factory calibrated frequency 32 Factory calibration accuracy T = 85°C, V = 3.0V -1.5 1.5 CC User calibration accuracy -0.2 0.2 % DFLL calibration step size 0.23 36.14.432kHz Internal ULP Oscillator characteristics Table 36-23. 32kHz internal ULP oscillator characteristics. Symbol Parameter Condition Min Typ Max Units Factory calibrated frequency 32 kHz Factory calibration accuracy T = 85°C, V = 3.0V -12 12 % CC 36.14.5Phase Locked Loop (PLL) characteristics Table 36-24. Calibrated 32MHz internal oscillator characteristics. Symbol Parameter Condition Min Typ Max Units f Input Frequency Output frequency must be within f 0.4 64 MHz IN OUT V = 1.60V 20 32 CC f Output frequency(1) MHz OUT V = 2.70V 20 128 CC Start-up time 23 100 µs re-lock time 20 50 µs Note: 1. The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than 4 times the maximum CPU frequency. XMEGA B3 [DATASHEET] 84 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

36.14.6External Clock Characteristics Figure 36-3. External Clock Drive Waveform t t CH CH t t CR CF V IH1 V IL1 t CL t CK Table 36-25. External clock used as system clock without prescaling. Symbol Parameter Condition Min Typ Max Units V = 1.6 - 1.8V 0 12 CC 1/t Clock frequency(1) MHz CK V = 2.7 - 3.6V 0 32 CC V = 1.6 - 1.8V 83.3 CC t Clock period ns CK V = 2.7 - 3.6V 31.5 CC V = 1.6 - 1.8V 30.0 CC t Clock high time ns CH V = 2.7 - 3.6V 12.5 CC V = 1.6 - 1.8V 30.0 CC t Clock low time ns CL V = 2.7 - 3.6V 12.5 CC V = 1.6 - 1.8V 10 CC t Rise time (for maximum frequency) ns CR V = 2.7 - 3.6V 3 CC V = 1.6 - 1.8V 10 CC t Fall time (for maximum frequency) ns CF V = 2.7 - 3.6V 3 CC Δt Change in period from one clock cycle to the next 10 % CK Note: 1. The maximum frequency vs. supply voltage is linear between 1.8V and 2.7V, and the same applies for all other parameters with supply voltage conditions. XMEGA B3 [DATASHEET] 85 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

Table 36-26. External clock with prescaler(1) for system clock Symbol Parameter Condition Min Typ Max Units V = 1.6 - 1.8V 0 90 CC 1/t Clock Frequency(2) MHz CK V = 2.7 - 3.6V 0 142 CC V = 1.6 - 1.8V 11 CC t Clock Period ns CK V = 2.7 - 3.6V 7 CC V = 1.6 - 1.8V 4.5 CC t Clock High Time ns CH V = 2.7 - 3.6V 2.4 CC V = 1.6 - 1.8V 4.5 CC t Clock Low Time ns CL V = 2.7 - 3.6V 2.4 CC V = 1.6 - 1.8V 1.5 CC t Rise Time (for maximum frequency) ns CR V = 2.7 - 3.6V 1.0 CC V = 1.6 - 1.8V 1.5 CC t Fall Time (for maximum frequency) ns CF V = 2.7 - 3.6V 1.0 CC Δt Change in period from one clock cycle to the next 10 % CK Notes: 1. System Clock Prescalers must be set so that maximum CPU clock frequency for device is not exceeded. 2. The maximum frequency vs. supply voltage is linear between 1.8V and 2.7V, and the same applies for all other parameters with supply voltage conditions 36.14.7External 16MHz crystal oscillator and XOSC characteristics Table 36-27. External 16MHz crystal oscillator and XOSC characteristics. Symbol Parameter Condition Min. Typ. Max. Units XOSCPWR=0, FRQRANGE=0 0 Cycle to cycle jitter XOSCPWR=0, FRQRANGE=1, 2, or 3 0 ns XOSCPWR=1 0 XOSCPWR=0, FRQRANGE=0 0 Long term jitter XOSCPWR=0, FRQRANGE=1, 2, or 3 0 ns XOSCPWR=1 0 XOSCPWR=0, FRQRANGE=0 0.03 XOSCPWR=0, FRQRANGE=1 0.03 Frequency error % XOSCPWR=0, FRQRANGE=2 or 3 0.03 XOSCPWR=1 0.03 XOSCPWR=0, FRQRANGE=0 50 XOSCPWR=0, FRQRANGE=1 50 Duty cycle % XOSCPWR=0, FRQRANGE=2 or 3 50 XOSCPWR=1 50 XMEGA B3 [DATASHEET] 86 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

Symbol Parameter Condition Min. Typ. Max. Units 0.4MHz resonator, CL=100pF 44k XOSCPWR=0, 1MHz crystal, CL=20pF 67k FRQRANGE=0 2MHz crystal, CL=20pF 67k 2MHz crystal 82k XOSCPWR=0, FRQRANGE=1, 8MHz crystal 1500 CL=20pF 9MHz crystal 1500 8MHz crystal 2700 XOSCPWR=0, FRQRANGE=2, 9MHz crystal 2700 CL=20pF 12MHz crystal 1000 9MHz crystal 3600 XOSCPWR=0, FRQRANGE=3, 12MHz crystal 1300 R Negative impedance (1) CL=20pF Ω Q 16MHz crystal 590 9MHz crystal 390 XOSCPWR=1, FRQRANGE=0, 12MHz crystal 50 CL=20pF 16MHz crystal 10 9MHz crystal 1500 XOSCPWR=1, FRQRANGE=1, 12MHz crystal 650 CL=20pF 16MHz crystal 270 XOSCPWR=1, 12MHz crystal 1000 FRQRANGE=2, CL=20pF 16MHz crystal 440 XOSCPWR=1, 12MHz crystal 1300 FRQRANGE=3, CL=20pF 16MHz crystal 590 XOSCPWR=0, 0.4MHz resonator, CL=100pF 1.0 FRQRANGE=0 XOSCPWR=0, 2MHz crystal, CL=20pF 2.6 FRQRANGE=1 XOSCPWR=0, Start-up time 8MHz crystal, CL=20pF 0.8 ms FRQRANGE=2 XOSCPWR=0, 12MHz crystal, CL=20pF 1.0 FRQRANGE=3 XOSCPWR=1, 16MHz crystal, CL=20pF 1.4 FRQRANGE=3 ESR SF = Safety factor min(RQ)/SF kΩ XMEGA B3 [DATASHEET] 87 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

Symbol Parameter Condition Min. Typ. Max. Units C Parasitic capacitance 5.9 XTAL1 C Parasitic capacitance 8.3 pF XTAL2 C Parasitic capacitance load 3.5 LOAD Note: 1. Numbers for negative impedance are not tested but guaranteed from design and characterization. 36.14.8External 32.768kHz crystal oscillator and TOSC characteristics Table 36-28. External 32.768kHz crystal oscillator and TOSC characteristics. Symbol Parameter Condition Min Typ Max Units Crystal load capacitance 6.5pF 60 Recommended crystal equivalent ESR/R1 Crystal load capacitance 9.0pF 35 kΩ series resistance (ESR) Crystal load capacitance 12.0pF 28 Normal mode 3.5 C Input capacitance between TOSC pins pF IN_TOSC Low power mode 3.5 capacitance load matched to Recommended Safety factor 3 crystal specification Long term Jitter (SIT) 0 % Note: 1. See Figure 36-4 on page 88 for definition Figure 36-4. TOSC input capacitance C C L1 L2 Device internal TOSC1 TOSC2 External The input capacitance between the TOSC pins is C + C in series as seen from the crystal when oscillating without L1 L2 external capacitors. XMEGA B3 [DATASHEET] 88 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

36.15 SPI characteristics Figure 36-5. SPI interface requirements in master mode SS tMOS tSCKR tSCKF SCK (CPOL = 0) tSCKW SCK (CPOL = 1) tSCKW tMIS tMIH tSCK MISO MSB LSB (Data Input) tMOH tMOH MOSI MSB LSB (Data Output) Figure 36-6. SPI timing requirements in slave mode SS tSSS tSCKR tSCKF tSSH SCK (CPOL = 0) tSSCKW SCK (CPOL = 1) tSSCKW tSIS tSIH tSSCK MOSI MSB LSB (Data Input) tSOSSS tSOS tSOSSH MISO MSB LSB (Data Output) XMEGA B3 [DATASHEET] 89 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

Table 36-29. SPI Timing characteristics and requirements. Symbol Parameter Condition Min Typ Max Units (See Table 21-4 in t SCK Period Master SCK XMEGA B Manual) t SCK high/low width Master 0.5*SCK SCKW t SCK Rise time Master 2.7 SCKR t SCK Fall time Master 2.7 SCKF t MISO setup to SCK Master 11 MIS t MISO hold after SCK Master 0 MIH t MOSI setup SCK Master 0.5*SCK MOS t MOSI hold after SCK Master 1 MOH t Slave SCK Period Slave 4*tClk SSCK PER ns t SCK high/low width Slave 2*tClk SSCKW PER t SCK Rise time Slave 1600 SSCKR t SCK Fall time Slave 1600 SSCKF t MOSI setup to SCK Slave 3 SIS t MOSI hold after SCK Slave tClk SIH PER t SS setup to SCK Slave 21 SSS t SS hold after SCK Slave 20 SSH t MISO setup SCK Slave 8 SOS t MISO hold after SCK Slave 13 SOH t MISO setup after SS low Slave 11 SOSS t MISO hold after SS high Slave 8 SOSH XMEGA B3 [DATASHEET] 90 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

36.16 Two-Wire Interface Characteristics Table 2-1 describes the requirements for devices connected to the Two Wire Serial Bus. The XMEGA Two-Wire Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 36-7. Figure 36-7. Two-Wire Interface Bus Timing t t of HIGH t t LOW r SCL tSU;STA tHD;STA tHD;DAT tSU;DAT tSU;STO SDA t BUF Table 36-30. Two wire serial bus characteristics. Symbol Parameter Condition Min Typ Max Units V Input High Voltage 0.7*V V +0.5 IH CC CC V Input Low Voltage -0.5 0.3*V IL CC V V Hysteresis of Schmitt Trigger Inputs 0.05V (1) 0 hys CC V Output Low Voltage 3mA, sink current 0 0.4 OL t Rise Time for both SDA and SCL 20+0.1C (1)(2) 300 r b t Output Fall Time from V to V 10pF < C < 400pF(2) 20+0.1C (1)(2) 250 ns of IHmin ILmax b b t Spikes Suppressed by Input Filter 0 50 SP I Input Current for each I/O Pin 0.1V < V < 0.9V -10 10 µA I CC I CC C Capacitance for each I/O Pin 10 pF I f SCL Clock Frequency f (3)>max(10f , 250kHz) 0 400 kHz SCL PER SCL R Value of Pull-up resistor fSCL ≤ 100kHz V----C----C----–-----0---.-4----V--- 1----0--0----n---s-- 3----0--0----n---s-- Ω P 3mA C C f > 100kHz b b SCL f ≤ 100kHz 4.0 SCL t Hold Time (repeated) START condition µs HD;STA f > 100kHz 0.6 SCL f ≤ 100kHz 4.7 SCL t Low Period of SCL Clock µs LOW f > 100kHz 1.3 SCL f ≤ 100kHz 4.0 SCL t High Period of SCL Clock µs HIGH f > 100kHz 0.6 SCL f ≤ 100kHz 4.7 SCL t Set-up time for a repeated START condition µs SU;STA f > 100kHz 0.6 SCL f ≤ 100kHz 0 3.5 SCL t Data hold time µs HD;DAT f > 100kHz 0 0.9 SCL XMEGA B3 [DATASHEET] 91 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

Symbol Parameter Condition Min Typ Max Units f ≤ 100kHz 250 SCL t Data setup time ns SU;DAT f > 100kHz 100 SCL f ≤ 100kHz 4.0 SCL t Setup time for STOP condition µs SU;STO f > 100kHz 0.6 SCL f ≤ 100kHz 4.7 Bus free time between a STOP and START SCL t µs BUF condition f > 100kHz 1.3 SCL Notes: 1. Required only for f > 100kHz SCL 2. C = Capacitance of one bus line in pF b 3. f = Peripheral clock frequency PER XMEGA B3 [DATASHEET] 92 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

37. Typical Characteristics 37.1 Current consumption 37.1.1 Active mode supply current Figure 37-1. Active supply current vs. frequency. f =0 - 1MHz external clock, T = 25°C. SYS 1000 3.6V 900 800 3.0V 700 2.7V A] µ 600 [C C I 500 2.2V 400 1.8V 1.6V 300 200 100 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz] Figure 37-2. Active supply current vs. frequency. f =1 - 32MHz external clock, T = 25°C. SYS 14 3.6V 12 10 3.0V A] 2.7V m 8 [ c c I 6 2.2V 4 1.8V 2 0 0 4 8 12 16 20 24 28 32 Frequency [MHz] XMEGA B3 [DATASHEET] 93 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

Figure 37-3. Active mode supply current vs. V . CC f =2MHz internal oscillator. SYS 2100 1900 -40°C 25°C 1700 85°C 1500 A] u [C 1300 C I 1100 900 700 500 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 V [V] CC Figure 37-4. Active mode supply current vs. V . CC f =32MHz internal oscillator. SYS 14000 13250 -40 °C 25 °C 12500 85 °C 11750 A] µ cc[ 11000 I 10250 9500 8750 8000 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 Vcc [V] XMEGA B3 [DATASHEET] 94 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

37.1.2 Idle mode supply current Figure 37-5. Idle mode supply current vs. frequency. f =0 - 1MHz external clock, T = 25°C. SYS 180 3.6V 160 140 3.0V 120 A] 2.7V µ [ 100 c c I 2.2V 80 1.8V 60 1.6V 40 20 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency [MHz] Figure 37-6. Idle mode supply current vs. frequency. f =1 - 32MHz external clock, T = 25°C. SYS 6 3.6V 5 4 3.0V A] 2.7V m 3 [ c c I 2 2.2V 1 1.8V 0 0 4 8 12 16 20 24 28 32 Frequency [MHz] XMEGA B3 [DATASHEET] 95 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

Figure 37-7. Idle mode supply current vs. V . CC f =32.768kHz internal oscillator. SYS 34.5 -40°C 33.75 85°C 33 32.25 A] 31.5 25°C µ [ c 30.75 c I 30 29.25 28.5 27.75 27 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 V [V] CC Figure 37-8. Idle mode supply current vs. V . CC f =2MHz internal oscillator. SYS 450 -40°C 425 25°C 400 85°C 375 350 A] µ 325 c [ 300 c I 275 250 225 200 175 150 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 V [V] CC XMEGA B3 [DATASHEET] 96 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

Figure 37-9. Idle mode current vs. V . CC f =32MHz internal oscillator. SYS 5800 -40 °C 25 °C 5300 85 °C 4800 4300 A] µ C [ 3800 C I 3300 2800 2300 1800 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 V [V] CC 37.1.3 Power-down mode supply current Figure 37-10.Power-down mode supply current vs. Temperature. All functions disabled. 2.5 3.0 V 2.25 2.7 V 2 2.2 V 1.8 V 1.75 A] 1.5 µ c [ 1.25 c I 1 0.75 0.5 0.25 0 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] XMEGA B3 [DATASHEET] 97 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

Figure 37-11.Power-down mode supply current vs. Temperature. Watchdog and sampled BOD enabled. 3.5 3.0 V 3.25 2.7 V 2.2 V 3 1.8 V 2.75 A] 2.5 µ [ c 2.25 c I 2 1.75 1.5 1.25 1 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature [°C] 37.2 I/O Pin Characteristics 37.2.1 Pull-up Figure 37-12.I/O pin pull-up resistor current vs. input voltage. V = 1.8V. CC 80 70 60 A] 50 µ [N PI 40 I 30 20 85°C 10 25°C -40°C 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 V [V] PIN XMEGA B3 [DATASHEET] 98 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

Figure 37-13.I/O pin pull-up resistor current vs. input voltage. V = 3.0V. CC 140 120 100 A] µ 80 [N PI I 60 40 85°C 20 25°C -40°C 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 V [V] PIN Figure 37-14.I/O pin pull-up resistor current vs. pin voltage. V = 3.3V. CC 160 140 120 A] 100 µ [N 80 PI I 60 40 85°C 20 25°C -40°C 0 0 0.35 0.7 1.05 1.4 1.75 2.1 2.45 2.8 3.15 3.5 V [V] PIN XMEGA B3 [DATASHEET] 99 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

37.2.2 Output Voltage vs. Sink/Source Current Figure 37-15.I/O pin output voltage vs. source current. V = 1.8V. CC 1.3 -40°C 25°C 1.2 85°C 1.1 V] 1 [ N PI V 0.9 0.8 0.7 0.6 -6 -5.4 -4.8 -4.2 -3.6 -3 -2.4 -1.8 -1.2 -0.6 0 I [mA] PIN Figure 37-16.I/O pin output voltage vs. source current. V = 3.0V. CC 3.1 -40°C 25°C 2.9 85°C 2.7 2.5 V] 2.3 [N PI V 2.1 1.9 1.7 1.5 1.3 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 I [mA] PIN XMEGA B3 [DATASHEET] 100 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

Figure 37-17.I/O pin output voltage vs. source current. V = 3.3V. CC 2.5 85°C 2.25 25°C -40°C 2 V] [N PI 1.75 V 1.5 1.25 1 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 I [mA] PIN Figure 37-18.I/O pin output voltage vs. sink current. V = 1.8V. CC 1.8 85°C 1.6 1.4 1.2 V] [N 1 PI V 0.8 25°C 0.6 -40°C 0.4 0.2 0 0 2 4 6 8 10 12 14 16 18 20 I [mA] PIN XMEGA B3 [DATASHEET] 101 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

Figure 37-19.I/O pin output voltage vs. sink current. V = 3.0V. CC 0.6 85°C 0.54 25°C 0.48 -40°C 0.42 V] 0.36 [N PI 0.3 V 0.24 0.18 0.12 0.06 0 0 2 4 6 8 10 12 14 16 18 20 I [mA] PIN Figure 37-20.I/O pin output voltage vs. sink current. V = 3.3V. CC 0.4 85°C 0.35 25°C -40°C 0.3 0.25 V] [N PI 0.2 V 0.15 0.1 0.05 0 0 2 4 6 8 10 12 14 16 18 20 I [mA] PIN XMEGA B3 [DATASHEET] 102 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

37.2.3 Thresholds and Hysteresis Figure 37-21.I/O pin input threshold voltage vs. V . CC V I/O pin read as “1”. IH 1.8 -40°C 25°C 85°C 1.6 V] [D 1.4 L O H S E HR 1.2 T V 1 0.8 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 V [V] CC Figure 37-22.I/O pin input threshold voltage vs. V . CC V I/O pin read as “0”. IL 1.7 -40°C 25°C 1.5 85°C 1.3 V] [D L O 1.1 H S E R T V 0.9 0.7 0.5 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 V [V] CC XMEGA B3 [DATASHEET] 103 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

Figure 37-23.I/O pin input hysteresis vs. V . CC 350 300 V] m [S 250 SI E R E ST 200 Y H V 150 -40°C 25°C 85°C 100 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 V [V] CC 37.3 ADC Characteristics Figure 37-24.ADC INL vs. V . REF Differential signed mode, V = 3.6V, external reference. CC 2.5 2.3 2.1 1.9 B] 1.7 S L L [ 1.5 N I 1.3 -40ºC 1.1 85ºC 0.9 25ºC 0.7 0.5 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 V [V] REF XMEGA B3 [DATASHEET] 104 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

Figure 37-25.ADC INL vs. V . REF SE Unsigned mode, V = 3.6V, external reference. CC 3.5 3.3 3.1 2.9 2.7 2.5 B] 2.3 LS 2.1 L [ 1.9 N I 1.7 1.5 1.3 1.1 85ºC 0.9 25ºC -40ºC 0.7 0.5 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 V [V] REF Figure 37-26.ADC DNL vs. V . REF Differential signed mode, V = 3.6V, external reference. CC 2.1 2 1.9 1.8 1.7 B] 1.6 S L 1.5 L [ N 1.4 D 1.3 1.2 -40ºC 1.1 85ºC 1 0.9 25ºC 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 V [V] REF XMEGA B3 [DATASHEET] 105 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

Figure 37-27.ADC DNL vs. V . REF SE Unsigned mode, V = 3.6V, external reference. CC 3.0 2.8 2.6 2.4 B] 2.2 S L L [ 2.0 N D 1.8 1.6 1.4 -40ºC 1.2 25ºC 85ºC 1.0 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 V [V] REF Figure 37-28.ADC Offset vs. V . CC SE Unsigned mode, V = 1.0V, external reference. REF 14 85ºC 12 25ºC -40ºC 10 V] m et [ 8 s Off 6 4 2 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 V [V] CC XMEGA B3 [DATASHEET] 106 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

Figure 37-29.ADC Offset vs. V . REF SE Unsigned mode, V = 3.6V, external reference. CC 19 85ºC 18 17 25ºC 16 V] 15 m et [ 14 s Off -40ºC 13 12 11 10 9 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 V [V] REF Figure 37-30.ADC Offset vs. V . REF Differential signed mode, V = 3.6V, external reference. CC 10.0 9.0 8.0 85ºC 25ºC V] 7.0 m -40ºC et [ 6.0 s Off 5.0 4.0 3.0 2.0 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 V V] REF XMEGA B3 [DATASHEET] 107 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

Figure 37-31.ADC Offset vs. V . CC Differential signed mode, V = 1.0V, external reference. REF -3 -3.5 -4 -4.5 V] -5 m et [ -5.5 s Off -6 85ºC -6.5 25ºC -7 -7.5 -8 -40ºC 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 V [V] CC Figure 37-32.ADC Gain Error vs. V . REF Differential signed mode, external reference. -1.0 -3.0 V] -5.0 m or [ -7.0 Err n Gai -9.0 -40ºC 25ºC -11.0 85ºC -13.0 -15.0 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 V [V] REF XMEGA B3 [DATASHEET] 108 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

Figure 37-33.ADC Gain Error vs. V . REF SE Unsigned mode, external reference. 0.0 -1.0 -2.0 -3.0 V] m -40ºC or [ -4.0 Err -5.0 n Gai -6.0 25ºC -7.0 -8.0 85ºC -9.0 -10.0 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 V [V] REF Figure 37-34.ADC Gain Error vs. V . CC Differential signed mode, external reference. -3.0 -3.5 -4.0 V] -4.5 m or [ -5.0 Err n -5.5 25ºC ai G -6.0 -40ºC -6.5 -7.0 85ºC -7.5 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 V [V] CC XMEGA B3 [DATASHEET] 109 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

Figure 37-35.ADC Gain Error vs. V . CC SE Unsigned mode, external reference. 0 -1 -2 V] m -3 or [ Err -4 n ai G -5 -40ºC -6 25ºC 85ºC -7 -8 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 V [V] CC Figure 37-36.ADC Gain Error vs. Temperature. Differential signed mode, external reference. -5.0 -6.0 1.0V Vref -7.0 V] m or [ -8.0 1.5V Vref Err ain -9.0 2.0V Vref G -10.0 2.5V Vref -11.0 3.0V Vref -12.0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature [ºC] XMEGA B3 [DATASHEET] 110 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

Figure 37-37.ADC Gain Error vs. Temperature. SE Unsigned mode, V = 3.6V, external reference. CC -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 -3.0 -4.0 V] -5.0 m Error [ -6.0 1.0V Vref n ai 1.5V Vref G -7.0 2.0V Vref -8.0 2.5V Vref 3.0V Vref -9.0 Temperature [ºC] 37.4 Analog Comparator Characteristics Figure 37-38.Analog comparator hysteresis vs. V . CC High-speed mode, small hysteresis. 16 15 14 V] 13 85ºC m [ 12 t s y11 H 25ºC V 10 9 -40ºC 8 7 6 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 V [V] CC XMEGA B3 [DATASHEET] 111 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

Figure 37-39.Analog comparator hysteresis vs. V . CC High-speed mode, large hysteresis. 32 85°C 30 V] 28 m 25°C [ 26 t s y H 24 V -40°C 22 20 18 16 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 V [V] CC Figure 37-40.Analog comparator propagation delay vs. V . CC High speed mode. 34 32 30 28 ] s n 26 [ D P t 24 22 20 85°C 18 25°C -40°C 16 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 Vcc [V] XMEGA B3 [DATASHEET] 112 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

Figure 37-41.Analog comparator current consumption vs. V . CC High-speed mode. 290 A] 270 µ n [ 85°C ptio 250 m u 230 25°C s -40°C n o C 210 e ul d o 190 M 170 150 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 V [V] CM Figure 37-42.Analog comparator voltage scaler vs. SCALEFAC. T = 25°C. 4 3.6V 3.5 3.3V 3 3.0V V] 2.7V E [ 2.5 L A C 2 S 1.8V V 1.6V 1.5 1 0.5 0 0 7 14 21 28 35 42 49 56 63 SCALEFAC XMEGA B3 [DATASHEET] 113 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

Figure 37-43.Analog comparator offset voltage vs. Common mode voltage. High-speed mode. 20 -40°C 18 ] V 16 m 14 25°C [ T E 12 85°C S F F 10 O V 8 6 4 2 0 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 V [V] CC Figure 37-44.Analog comparator current source vs. Calibration. V = 3.0V, double mode. CC 12 11.5 A] µ E [ 11 C R U 10.5 O S T N 10 E R R U 9.5 C I 9 -40°C 25°C 8.5 85°C 8 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CURRCALIBA[3..0] XMEGA B3 [DATASHEET] 114 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

37.5 Internal 1.0V reference Characteristics Figure 37-45.ADC/DAC Internal 1.0V reference vs. temperature. 1.012 1.01 V] e [ 1.008 g a olt V 1.006 p a g d 1.004 n a B 1.8V 1.002 2.7V 1 3.0V 0.998 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature [°C] 37.6 BOD Characteristics Figure 37-46.BOD current consumption vs. V . CC Continuous mode, BOD level = 1.6V. 150 85°C 140 25°C A] 130 µ al [ 120 -40°C b o Gl c 110 c I 100 90 80 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 V [V] CC XMEGA B3 [DATASHEET] 115 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

Figure 37-47.BOD current consumption vs. V . CC Sampled mode, BOD level = 1.6V. 5 4.5 4 85°C A] 3.5 µ al [ 3 b Glo 2.5 c c 2 I 1.5 25°C -40°C 1 0.5 0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 V [V] CC Figure 37-48.BOD thresholds vs. temperature. BOD level = 1.6V. 1.626 1.624 1.622 1.62 1.618 V] T [ 1.616 Rising Vcc O B V 1.614 1.612 1.61 1.608 Falling Vcc 1.606 1.604 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature [°C] XMEGA B3 [DATASHEET] 116 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

Figure 37-49.BOD thresholds vs. temperature. BOD level = 2.2V. 2.35 2.345 2.34 Rising Vcc 2.335 V] [T 2.33 O B V 2.325 2.32 2.315 Falling Vcc 2.31 2.305 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 37-50.BOD thresholds vs. temperature. BOD level = 3.0V. 3.07 3.06 Rising Vcc 3.05 V] T [ 3.04 O B V 3.03 3.02 Falling Vcc 3.01 3 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature [°C] XMEGA B3 [DATASHEET] 117 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

37.7 External Reset Characteristics Figure 37-51.Minimum Reset pin pulse width vs. V . CC 140 130 120 ] s n [ST 110 R t 100 85°C 90 25°C -40°C 80 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 V [V] CC Figure 37-52.Reset pin pull-up resistor current vs. reset pin voltage. V = 1.8V. CC 70 60 50 A] µ 40 [T E S E IR 30 20 85°C 10 25°C -40°C 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 V [V] RESET XMEGA B3 [DATASHEET] 118 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

Figure 37-53.Reset pin pull-up resistor current vs. reset pin voltage. V = 3.0V. CC 140 120 100 A] µ [T 80 E S E IR 60 40 85°C 20 25°C -40°C 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 V [V] RESET Figure 37-54.Reset pin pull-up resistor current vs. reset pin voltage. V = 3.3V. CC 140 120 100 A] µ [T 80 E S E IR 60 40 85°C 20 25°C -40°C 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 3.3 V [V] RESET XMEGA B3 [DATASHEET] 119 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

Figure 37-55.Reset pin input threshold voltage vs. V CC. V - Reset pin read as “1”. IH 1.8 -40°C 25°C 1.6 85°C 1.4 V] [D L 1.2 O H S E R H 1 VT 0.8 0.6 0.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 V [V] CC Figure 37-56.Reset pin input threshold voltage vs. V CC. V - Reset pin read as “0”. IL 1.8 -40 °C 25 °C 1.6 85 °C 1.4 V] D [ L O 1.2 H S E R H VT 1 0.8 0.6 0.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 V [V] CC XMEGA B3 [DATASHEET] 120 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

37.8 Oscillator Characteristics 37.8.1 32.768kHz Internal Oscillator Figure 37-57.32.768kHz internal oscillator frequency vs. temperature. 32.83 1.8V 32.82 1.6V 32.81 2.2V 3.6V z] 32.8 2.7V H 3.0V k 32.79 y [ nc 32.78 e u q 32.77 e r F 32.76 32.75 32.74 32.73 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature [°C] Figure 37-58.32.768kHz ULP internal oscillator frequency vs. temperature. 36000 35500 35000 ] z 34500 H [ y 34000 c n ue 33500 q e 3.6V r 33000 F 3.0V 32500 2.7V 1.8V 32000 1.6V 31500 31000 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature [°C] XMEGA B3 [DATASHEET] 121 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

Figure 37-59.32.768kHz internal oscillator calibration step size. T = -40°C to 85°C, V = 3V. CC 0.01 0.005 85°C 25°C 0.000 ] -40°C z H -0.005 k e: f [ -0.01 z -0.015 si p -0.02 e St -0.025 -0.03 -0.035 -0.04 -0.045 0 32 64 96 128 160 192 224 256 RC32KCAL[7..0] Figure 37-60.32.768kHz internal oscillator frequency vs. calibration value. V = 3.0V, T = 25°C. CC 55 50 3.0 V ] z 45 H k [ cy 40 n e u q e 35 r F 30 25 20 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 RC32KCAL[7..0] XMEGA B3 [DATASHEET] 122 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

37.8.2 2MHz Internal Oscillator Figure 37-61.2MHz internal oscillator frequency vs. temperature. DFLL disabled. 2.16 2.14 z] 2.12 H M 2.1 y [ nc 2.08 e u q 2.06 e r F 2.04 2.02 3.6 V 3.0 V 2.00 2.7 V 2.2 V 1.98 1.8 V 1.96 1.6 V -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 37-62.2MHz internal oscillator frequency vs. temperature. DFLL enabled. 2.006 1.6 V 2.005 2.2 V ] Hz 2.004 1.8 V M 2.7 V [ 3.0 V y c 2.003 3.6 V n e u q 2.002 e r F 2.001 2.000 1.999 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature [°C] XMEGA B3 [DATASHEET] 123 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

Figure 37-63.2MHz internal oscillator CALA calibration step size. V = 3V. CC -0.14 85 °C -0.15 -0.16 25 °C -0.17 %] -0.18 -40 °C r [ -0.19 o Err -0.2 ep -0.21 St -0.22 -0.23 -0.24 -0.25 -0.26 -0.27 0 10 20 30 40 50 60 70 80 90 100 110 120 130 DFLLRC2MCALA Figure 37-64.2MHz internal oscillator CALB calibration step size. V = 3V, DFLL enabled. CC -0.155 -0.165 85°C -0.175 25°C %] -0.185 or [ -0.195 -40°C rr E p -0.205 e St -0.215 -0.225 -0.235 -0.245 -0.255 0 7 14 21 28 35 42 49 56 63 DFLLRC2MCALB XMEGA B3 [DATASHEET] 124 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

37.8.3 32MHz Internal Oscillator Figure 37-65.32MHz internal oscillator frequency vs. temperature. DFLL disabled. 35.5 35 ] z 34.5 H M [ 34 y c n 33.5 e u q 33 e r F 32.5 3.6V 3.0V 32 2.7V 2.2V 31.5 1.8V 1.6V 31 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 37-66.32MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator. 32.08 1.8V 32.06 3.3V z] 2.2V H M 32.04 1.6V y [ c 2.7V n e u 32.02 3.0V q e r F 32 31.98 31.96 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] XMEGA B3 [DATASHEET] 125 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

Figure 37-67.32MHz internal oscillator CALA calibration step size. V = 3.0V. CC -0.1 -0.12 25°C -0.14 85°C %] -0.16 -40°C or [ -0.18 rr E p -0.2 e St -0.22 -0.24 -0.26 -0.28 -0.3 0 10 20 30 40 50 60 70 80 90 100 110 120 130 DFLLRC32MCALA Figure 37-68.32MHz internal oscillator CALB calibration step size. V = 3.0V, CALA = mid value. CC 0.60 0.50 %] r [ 0.40 o Err 0.30 p e 0.20 St -40°C e: 0.10 z si 0.00 p e St -0.10 25°C -0.20 85°C -0.30 -0.40 0 8 16 24 32 40 48 56 64 DFLLRC32MCALB XMEGA B3 [DATASHEET] 126 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

Figure 37-69.32MHz internal oscillator frequency vs. CALA calibration value. V = 3.0V. CC 56 -40°C 54 ] z H M 52 25°C y [ 50 c n 85°C e u 48 q e r 46 F 44 42 40 38 36 0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 DFLLRC32MCALA Figure 37-70.32MHz internal oscillator frequency vs. CALB calibration value. V = 3.0V, DFLL enabled. CC 70 -40°C 25°C 65 85°C ] Hz 60 M [ 55 y c n 50 e u q 45 e Fr 40 35 30 25 20 0 7 14 21 28 35 42 49 56 63 DFLLRC32MCALB XMEGA B3 [DATASHEET] 127 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

37.8.4 32MHz internal oscillator calibrated to 48MHz Figure 37-71.48MHz internal oscillator frequency vs. temperature. DFLL disabled. 53 52 z] H 51 M y [ c 50 n e u q e 49 r F 3.6V 48 3.0V 2.7V 2.2V 47 1.8V 1.6V 46 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] Figure 37-72.48MHz internal oscillator frequency vs. temperature. DFLL enabled, from the 32.768kHz internal oscillator. 48.12 1.8V 48.1 2.2V 3.6V ] 48.08 3.0V z H 1.6V M 48.06 2.7V [ y 48.04 c n e 48.02 u q e 48 r F 47.98 47.96 47.94 47.92 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 Temperature [°C] XMEGA B3 [DATASHEET] 128 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

Figure 37-73. 32MHz internal oscillator CALA calibration step size. Using 48MHz calibration value from signature row, V = 3.0V. CC 0.80 ] % 0.60 [ r o r Er 0.40 p e St 0.20 -40°C e: z 85°C si 0.00 p e St -0.20 -0.40 25°C -0.60 0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 CALA Figure 37-74. 48MHz internal oscillator frequency vs. CALA calibration value. V = 3.0V. CC 60 -40°C 58 56 25°C ] z H 54 M 85°C y [ 52 c n e 50 u q re 48 F 46 44 42 40 0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 128 CALA XMEGA B3 [DATASHEET] 129 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

37.9 PDI characteristics Figure 37-75.Maximum PDI frequency vs. V . CC 20.5 20.0 25°C 19.5 ] z H k 19.0 n [ -40°C mi f 18.5 18.0 85°C 17.5 17.0 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 V [V] CC XMEGA B3 [DATASHEET] 130 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

37.10 LCD Characteristics Figure 37-76.I vs. Frame Rate CC 32Hz Low Power Frame Rate from 32.768KHz TOSC, w/ and w/o pixel load, V = 1.8V, T = 25°C CC 11 22pF All Pixels ON 10 9 8 A] 22pF All Pixels OFF µ [ C 7 C I 6 5 0pF All Pixels ON 4 0pF All Pixels OFF 3 32 64 96 128 160 192 224 256 Frame Rate[Hz] Figure 37-77.I vs. Frame Rate CC 32Hz Low Power Frame Rate from 32.768KHz TOSC, w/ and w/o pixel load, V = 3.0V, T = 25°C CC 13 12 22pF All Pixels ON 11 10 A] 9 [µC 8 22pF 100 Pixels ON C I 7 22pF All Pixels OFF 6 0pF All Pixels ON 5 0pF 100 Pixels ON 4 0pF All Pixels OFF 3 32 64 96 128 160 192 224 256 Frame Rate[Hz] XMEGA B3 [DATASHEET] 131 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

Figure 37-78.I vs. Frame Rate CC 0pF load 15 85°C 13 25°C 11 -40°C ]A µ [ C C 9 I 7 5 3 32 64 96 128 160 192 224 256 Frame Rate[Hz] Figure 37-79.I vs. Contrast CC 32Hz Low Power Frame Rate from 32.768KHz TOSC, w/o pixel load, V = 1.8V CC 7.5 7 6.5 85°C 6 ] A µ 5.5 [ C C I 5 25°C 4.5 -40°C 4 3.5 3 -32 -23 -14 -5 4 13 22 31 Contrast XMEGA B3 [DATASHEET] 132 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

Figure 37-80.I vs. Contrast CC 32Hz Low Power Frame Rate from 32.768KHz TOSC, w/o pixel load, V = 3.0V CC 7.5 7 85°C 6.5 6 ] A µ 5.5 [ C C 5 25°C I 4.5 -40°C 4 3.5 3 -32 -23 -14 -5 4 13 22 31 Contrast Figure 37-81.Psave LCD LP 32Hz vs. Temperature 3.2 A] µ n [ 3 o pti m 2.8 u s n o eC 2.6 3.6V ul d o M 2.4 c 3.0V c I 2.2V 2.2 1.8V 1.6V 2 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature [°C] XMEGA B3 [DATASHEET] 133 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

Figure 37-82.Psave LCD LP 32Hz vs. Temperature RTC, WDT, BOD sampled 3.6 A] µ 3.4 n [ o pti 3.2 m su 3.0 n o C 3.6V e 2.8 ul d o 2.6 3.0V M c c 2.2V I 2.4 1.8V 2.2 1.6V 2.0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature [°C] Figure 37-83.Psave vs. Temperature RTC, WDT, BOD sampled. 0.3 A] µ n [ 0.275 o pti m 0.25 3.6V u s n o C 0.225 e ul 3.0V d o M 0.2 c c 2.2V I 0.175 1.8V 0.15 1.6V -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature [°C] XMEGA B3 [DATASHEET] 134 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

38. Errata 38.1 ATxmega64B3, ATxmega128B3 38.1.1 Rev. C (cid:122) Device revision number (cid:122) AWeX fault protection restore is not done correct in Pattern Generation Mode 1. Device revision number is unchanged between rev. B and rev. C 2. AWeX fault protection restore is not done correctly in Pattern Generation Mode When a fault is detected the OUTOVEN register is cleared, and when fault condition is cleared, OUTOVEN is restored according to the corresponding enabled DTI channels. For Common Waveform Channel Mode (CWCM), this has no effect as the OUTOVEN is correct after restoring from fault. For Pattern Generation Mode (PGM), OUTOVEN should instead have been restored according to the DTILSBUF register. Problem fix/Workaround For CWCM no workaround is required. For PGM in latched mode, disable the DTI channels before returning from the fault condition. Then, set correct OUTOVEN value and enable the DTI channels, before the direction (DIR) register is written to enable the correct outputs again. For PGM in cycle-by-cycle mode there is no workaround. 38.1.2 Rev. B Not sampled. 38.1.3 Rev. A (cid:122) Power down consumption (cid:122) ADC conversion error when x0.5 gain is used 1. Power Down consumption After reset, when system enters in power down or when ADC is disabled, extra power consumption is drawn. Problem fix/Workaround Set ADC to a configuration different from differential mode. 2. ADC conversion error when x0.5 gain is used When the gain is set to x0.5, the conversion result is similar to the gain setting x1. Problem fix/Workaround There is no workaround. 3. Disabling of USART transmitter does not automatically set the TxD pin direction to input If the USART transmitter is idle with no frames to transmit, setting TXEN to zero will not automatically set the TxD pin direction to input. Problem fix/Workaround The TxD pin direction can be set to input using the Port DIR register. Be advised that setting the Port DIR register to input will be immediate. Ongoing transmissions will be truncated. XMEGA B3 [DATASHEET] 135 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

39. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 39.1 8074E – 07/2014 1. Changed Vcc to AVcc in Section 29. “ADC – 12-bit Analog to Digital Converter” on page 50 and Section 30. “AC – Analog Comparator” on page 52. 2. Added information on USART transmitter in Section 38. “Errata” on page 135. 3. Changed unit notification for t to ns in Table 36-30 on page 91. SU;DAT 39.2 8074D – 08/2013 1. 64-pad DRQFN package option added for ATxmega128B3: (cid:122) “Ordering Information” on page 2: New ordering codes for ATxmega128B3 added. (cid:122) “Pinout – DRQFN” on page 5: Pinout figure and table added. (cid:122) “Packaging information” : “64P2” on page 70 added. 39.3 8074C – 02/2013 1. Updated “Ordering Information” on page 2: Added -AUR option. 2. Updated “Packaging information” : Added package drawing for “64M2” on page 69 3. Updated Table 32-4 on page 58: PDI and RESET pins updated. 4. Updated “External clock with prescaler for system clock” Table 36-26 on page 86 5. Added ESR parameter to the “External 16MHz crystal oscillator and XOSC characteristics.” Table 36-27 on page 86. 6. Updated “Errata” , “Rev. C” on page 132: “JTAG revision” replaced by “Device revision number” 7. Updated template. 39.4 8074B – 02/2012 1. Updated the Table 7-2 on page 17. The page size (words) for ATxmega128B3 changed from 256 to 128. 2. Updated all “Electrical Characteristics” on page 71. 3. Updated all “Typical Characteristics” on page 93. 4. Updated “Errata” on page 135. XMEGA B3 [DATASHEET] 136 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

39.5 8074A – 10/2011 1. Initial revision. XMEGA B3 [DATASHEET] 137 Atmel-8074E-AVR-ATxmega 128B3 - 64B3_Datasheet–09/2014

XMEGA B3 [DATASHEET] 138 Atmel-8074E–AVR-ATxmega 128B3 - 64B3_datasheet–09/2014

Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. Pinout/Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Pinout – TQFP/QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 Pinout – DRQFN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4. Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.1 Recommended reading. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5. Capacitive touch sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6. AVR CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.3 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.4 ALU - Arithmetic Logic Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.5 Program Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.6 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.7 Stack and Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.8 Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7. Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.3 Flash Program Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.4 Fuses and Lock bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.5 Data Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.6 EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.7 I/O Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.8 Data Memory and Bus Arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.9 Memory Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.10 Device ID and Revision. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.11 JTAG Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.12 I/O Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.13 Flash and EEPROM Page Size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8. DMAC – Direct Memory Access Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 9. Event System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 10. System Clock and Clock options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 XMEGA B1 [DATASHEET] i Atmel-8330G-AVR-ATxmega64B1-128B1_Datasheet-09/2014

10.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 10.3 Clock Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 11. Power Management and Sleep Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 11.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 11.3 Sleep Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 12. System Control and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 12.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 12.3 Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 12.4 Reset Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 13. WDT – Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 13.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 14. Interrupts and Programmable Multilevel Interrupt Controller . . . . . . . . . . . . . . . . 29 14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 14.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 14.3 Interrupt vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 15. I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 15.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 15.3 Output Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 15.4 Input sensing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 15.5 Alternate Port Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 16. T/C – 16-bit Timer/Counter Type 0 and 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 16.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 17. TC2 –16-bit Timer/Counter Type 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 17.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 18. AWeX – Advanced Waveform Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 18.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 18.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 19. Hi-Res – High Resolution Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 19.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 19.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 20. RTC – 16-bit Real-Time Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 20.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 20.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 21. USB – Universal Serial Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 21.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 21.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 XMEGA B1 [DATASHEET] ii Atmel-8330G-AVR-ATxmega64B1-128B1_Datasheet-09/2014

22. TWI – Two Wire Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 22.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 22.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 23. SPI – Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 23.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 23.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 24. USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 24.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 24.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 25. IRCOM – IR Communication Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 25.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 25.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 26. AES and DES Crypto Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 26.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 26.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 27. CRC – Cyclic Redundancy Check Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 27.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 27.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 28. LCD - Liquid Crystal Display Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 28.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 28.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 29. ADC – 12-bit Analog to Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 29.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 29.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 30. AC – Analog Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 30.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 30.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 31. Programming and Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 31.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 31.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 32. Pinout and Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 32.1 Alternate Pin Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 32.2 Alternate Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 33. Peripheral Module Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 34. Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 35. Packaging information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 35.1 64A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 35.2 64M2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 35.3 64P2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 36. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 XMEGA B1 [DATASHEET] iii Atmel-8330G-AVR-ATxmega64B1-128B1_Datasheet-09/2014

36.1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 36.2 General Operating Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 36.3 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 36.4 Wake-up time from sleep modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 36.5 I/O Pin Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 36.6 Liquid Crystal Display Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 36.7 ADC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 36.8 Analog Comparator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 36.9 Bandgap and Internal 1.0V Reference Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 36.10 Brownout Detection Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 36.11 External Reset Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 36.12 Power-on Reset Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 36.13 Flash and EEPROM Memory Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 36.14 Clock and Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 36.15 SPI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 36.16 Two-Wire Interface Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 37. Typical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 37.1 Current consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 37.2 I/O Pin Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 37.3 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 37.4 Analog Comparator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 37.5 Internal 1.0V reference Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 37.6 BOD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 37.7 External Reset Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 37.8 Oscillator Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 37.9 PDI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 37.10 LCD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 38. Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 38.1 ATxmega64B3, ATxmega128B3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 39. Datasheet Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 39.1 8074E – 07/2014. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 39.2 8074D – 08/2013. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 39.3 8074C – 02/2013. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 39.4 8074B – 02/2012. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 39.5 8074A – 10/2011. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Table of Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .i XMEGA B1 [DATASHEET] iv Atmel-8330G-AVR-ATxmega64B1-128B1_Datasheet-09/2014

XMEGA B1 [DATASHEET] v Atmel-8330G-AVR-ATxmega64B1-128B1_Datasheet-09/2014

X X X X X X Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com © 2014 Atmel Corporation. / Rev.: Atmel-8330F-AVR-Document-Title-or-Devices-Filename-Datasheet_09/2014. Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities, and others are registered trademarks or trademarks of Atmel Corporation in U.S. and other countries. Other terms and product names may be trademarks of others. DISCLAIMER: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS AND PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and products descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. SAFETY-CRITICAL, MILITARY, AND AUTOMOTIVE APPLICATIONS DISCLAIMER: Atmel products are not designed for and will not be used in connection with any applications where the failure of such products would reasonably be expected to result in significant personal injury or death (“Safety-Critical Applications”) without an Atmel officer's specific written consent. Safety-Critical Applications include, without limitation, life support devices and systems, equipment or systems for the operation of nuclear facilities and weapons systems. Atmel products are not designed nor intended for use in military or aerospace applications or environments unless specifically designated by Atmel as military-grade. Atmel products are not designed nor intended for use in automotive applications unless specifically designated by Atmel as automotive-grade.

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: ATXMEGA128B3-AU ATXMEGA128B3-MH ATXMEGA64B3-AU ATXMEGA64B3-AUR ATXMEGA64B3-MUR ATXMEGA128B3-MHR ATXMEGA128B3-MCU ATXMEGA128B3-MCUR ATXMEGA128B3-MUR ATXMEGA64B3- MH ATXMEGA128B3-AUR ATXMEGA128B3-MN ATXMEGA64B3-MN ATXMEGA64B3-AN ATXMEGA128B3-ANR ATXMEGA128B3-AN ATXMEGA128B3-MNR ATXMEGA64B3-ANR ATXMEGA64B3-MNR