Features • Core – ARM® Cortex®-M3 revision 2.0 running at up to 48 MHz – Thumb®-2 instruction – 24-bit SysTick Counter – Nested Vector Interrupt Controller (cid:129) Pin-to-pin compatible with SAM7S legacy products (48- and 64-pin versions) and SAM3S (48-, 64- and 100-pin versions) (cid:129) Memories – From 16 to 256 Kbytes embedded Flash, 128-bit wide access, memory accelerator, single plane AT91SAM – From 4 to 24 Kbytes embedded SRAM – 16 Kbytes ROM with embedded bootloader routines (UART) and IAP routines ARM-based (cid:129) System – Embedded voltage regulator for single supply operation Flash MCU – Power-on-Reset (POR), Brown-out Detector (BOD) and Watchdog for safe operation – Quartz or ceramic resonator oscillators: 3 to 20 MHz main power with Failure Detection and optional low power 32.768 kHz for RTC or device clock SAM3N Series – High precision 8/12 MHz factory trimmed internal RC oscillator with 4 MHz default frequency for device startup. In-application trimming access for frequency adjustment – Slow Clock Internal RC oscillator as permanent low-power mode device clock – One PLL up to 130 MHz for device clock – Up to 10 peripheral DMA (PDC) channels Summary (cid:129) Low Power Modes – Sleep and Backup modes, down to 3 µA in Backup mode – Ultra low power RTC (cid:129) Peripherals – Up to 2 USARTs with RS-485 and SPI mode support. One USART (USART0) has ISO7816, IrDA® and PDC support in addition – Two 2-wire UARTs – 2 Two Wire Interface (I2C compatible), 1 SPI – Up to 6 Three-Channel 16-bit Timer/Counter with capture, waveform, compare and PWM mode. Quadrature Decoder Logic and 2-bit Gray Up/Down Counter for Stepper Motor – 4-channel 16-bit PWM – 32-bit Real-time Timer and RTC with calendar and alarm features – Up to 16 channels, 384 KSPS 10-bit ADC – One 500 KSPS 10-bit DAC (cid:129) I/O – Up to 79 I/O lines with external interrupt capability (edge or level sensitivity), debouncing, glitch filtering and on-die Series Resistor Termination – Three 32-bit Parallel Input/Output Controllers (cid:129) Packages – 100-lead LQFP, 14 x 14 mm, pitch 0.5 mm/100-ball TFBGA, 9 x 9 mm, pitch 0.8 mm – 64-lead LQFP, 10 x 10 mm, pitch 0.5 mm/64-pad QFN 9x9 mm, pitch 0.5 mm – 48-lead LQFP, 7 x 7 mm, pitch 0.5 mm/48-pad QFN 7x7 mm, pitch 0.5 mm 11011BS–ATARM–22-Feb-12

1. SAM3N Description Atmel's SAM3N series is a member of a family of Flash microcontrollers based on the high per- formance 32-bit ARM Cortex-M3 RISC processor. It operates at a maximum speed of 48 MHz and features up to 256 Kbytes of Flash and up to 24 Kbytes of SRAM. The peripheral set includes 2x USARTs, 2x UARTs, 2x TWIs, 3x SPI, as well as 1 PWM timer, 6x general purpose 16-bit timers, an RTC, a 10-bit ADC and a 10-bit DAC. The SAM3N series is ready for capacitive touch thanks to the QTouch library, offering an easy way to implement buttons, wheels and sliders. The SAM3N device is an entry-level general purpose microcontroller. That makes the SAM3N the ideal starting point to move from 8- /16-bit to 32-bit microcontrollers. It operates from 1.62V to 3.6V and is available in 48-pin, 64-pin and 100-pin QFP, 48-pin and 64-pin QFN, and 100-pin BGA packages. The SAM3N series is the ideal migration path from the SAM3S for applications that require a reduced BOM cost. The SAM3N series is pin-to-pin compatible with the SAM3S series. Its aggressive price point and high level of integration pushes its scope of use far into cost-sensi- tive, high-volume applications. SAM3N Summary 2 11011BS–ATARM–22-Feb-12

SAM3N Summary 1.1 Configuration Summary The SAM3N4/2/1/0/00 differ in memory size, package and features list. Table 1-1 summarizes the configurations of the 9 devices. Table 1-1. Configuration Summary Number PDC Device Flash SRAM Package of PIOs ADC Timer Channels USART DAC LQFP48 SAM3N4A 256 Kbytes 24 Kbytes 34 8 channels 6(1) 8 1 _ QFN48 LQFP64 SAM3N4B 256 Kbytes 24 Kbytes 47 10 channels 6(2) 10 2 1 QFN64 LQFP100 SAM3N4C 256 Kbytes 24 Kbytes 79 16 channels 6 10 2 1 BGA100 LQFP48 SAM3N2A 128 Kbytes 16 Kbytes 34 8 channels 6(1) 8 1 _ QFN48 LQFP64 SAM3N2B 128 Kbytes 16 Kbytes 47 10 channels 6((2) 10 2 1 QFN64 LQFP100 SAM3N2C 128 Kbytes 16 Kbytes 79 16 channels 6 10 2 1 BGA100 LQFP48 SAM3N1A 64 Kbytes 8 Kbytes 34 8 channels 6(1) 8 1 _ QFN48 LQFP64 SAM3N1B 64 Kbytes 8 Kbytes 47 10 channels 6(2) 10 2 1 QFN64 LQFP100 SAM3N1C 64 Kbytes 8 Kbytes 79 16 channels 6 10 2 1 BGA100 LQFP48 SAM3N0A 32 Kbytes 8 Kbytes 34 8 channels 6(1) 8 1 _ QFN48 LQFP64 SAM3N0B 32 Kbytes 8 Kbytes 47 10 channels 6(2) 10 2 1 QFN64 LQFP100 SAM3N0C 32 Kbytes 8 Kbytes 79 16 channels 6 10 2 1 BGA100 LQFP48 SAM3N00A 16 Kbytes 4 KBytes 34 8 channels 6(1) 8 1 _ QFN48 LQFP64 SAM3N00B 16 Kbytes 4 KBytes 47 10 channels 6(2) 10 2 1 QFN64 Notes: 1. Only two TC channels are accessible through the PIO. 2. Only three TC channels are accessible through the PIO. 3 11011BS–ATARM–22-Feb-12

2. SAM3N Block Diagram Figure 2-1. SAM3N 100-pin version Block Diagram WO TDITDO/TTRMAS/CSTECWSKD/ISOWCLK JTAGSEL VDDIN VDDOUT System Controller Voltage TST Regulator PCK0-PCK2 PMC JTAG & Serial Wire XIN OSC XOUT 3-20 MHz WDT In-Circuit Emulator FLASH SRAM 24-bit 12R/C8/ 4O MSCHz SM SysTick Counter NV 256 KBytes 24 KBytes Cortex-M3 Processor I 128 KBytes 16 KBytes ROM SUPC Fmax 48 MHz C 64 KBytes 8 KBytes 16 KBytes XIN32 OSC 32k XOUT32 I/D S ERASE RC 32k PLL 3- layer AHB Bus Matrix Fmax 48 MHz RTT RTC POR VDDIO RSTC NRST Peripheral PIOA PIOB Bridge PIOC VDDCORE URXD0 UART0 Timer Counter A TCLK[0:2] UTXD0 PDC TC[0..2] TIOA[0:2] URXD1 UART1 TIOB[0:2] UTXD1 RXD0 TXD0 SCK0 USART0 RTS0 Timer Counter B TCLK[3:5] RCXTDS01 PDC TC[3..5] TIOA[3:5] TXD1 TIOB[3:5] SCK1 USART1 RTS1 CTS1 PDC NPCS0 NPCS1 NPCS2 SPI NPCS3 PWM[0:3] PWM MMIOSSO SPCK ADTRG 10-bit ADC PDC TWI0 TTWWCDK00 AD[0..15] PDC ADVREF TWI1 TWCK1 TWD1 DAC0 10-bit DAC DATRG PDC SAM3N Summary 4 11011BS–ATARM–22-Feb-12

SAM3N Summary Figure 2-2. SAM3N 64-pin version Block Diagram WO TDITDO/TTRMAS/CSTECWSKD/ISOWCLK JTAGSEL VDDIN VDDOUT System Controller Voltage TST Regulator PCK0-PCK2 PMC JTAG & Serial Wire XIN OSC XOUT WDT 3-20 MHz In-Circuit Emulator FLASH SRAM 24-bit 12R/C8/ 4O MSCHz SM SysTick Counter NV 256 KBytes 24 KBytes Cortex-M3 Processor I 128 KBytes 16 KBytes ROM SUPC Fmax 48 MHz C 64 KBytes 8 KBytes 16 KBytes XIN32 OSC 32k XOUT32 I/D S ERASE RC 32k PLL 3-lay3er- AlaHyBe rB AusH MBa Btriux sF mMaaxt r4ix8 MFmHzax 48 MHz RTT RTC POR VDDIO RSTC NRST Peripheral PIOA PIOB Bridge VDDCORE URXD0 UART0 Timer Counter A TCLK[0:2] UTXD0 PDC TC[0..2] TIOA[0:2] URXD1 UART1 TIOB[0:2] UTXD1 RXD0 TXD0 SCK0 USART0 Timer Counter B RTS0 CTS0 PDC RXD1 TC[3..5] TXD1 SCK1 USART1 RTS1 CTS1 PDC NPCS0 NPCS1 NPCS2 SPI NPCS3 PWM[0:3] PWM MMIOSSO SPCK ADTRG 10-bit ADC PDC TWI0 TTWWCDK00 AD[0..9] PDC ADVREF TWI1 TWCK1 TWD1 DAC0 10-bit DAC DATRG PDC 5 11011BS–ATARM–22-Feb-12

Figure 2-3. SAM3N 48-pin version Block Diagramz WO TDITDO/TTRMAS/CSTECWSKD/ISOWCLK JTAGSEL VDDIN VDDOUT System Controller Voltage TST Regulator PCK0-PCK2 PMC JTAG & Serial Wire XIN OSC XOUT 3-20 MHz WDT In-Circuit Emulator FLASH SRAM 24-bit 256 KBytes 12R/C8/ 4O MSCHz SM SysTick Counter NV 128 KBytes 24 KBytes Cortex-M3 Processor I 64 KBytes 16 KBytes ROM SUPC Fmax 48 MHz C 32 KBytes 8 KBytes 16 KBytes 16 KBytes 4 KBytes XIN32 OSC 32k XOUT32 I/D S ERASE RC 32k PLL 3-lay3e-r AlaHyBe rB AusH MBa Btruixs F Mmaaxtr 4ix8 FMmHzax 48 MHz RTT RTC POR VDDIO RSTC NRST Peripheral PIOA PIOB Bridge VDDCORE URXD0 UART0 Timer Counter A TCLK[0..1] UTXD0 PDC TC[0..1] TIOA[0..1] URXD1 UART1 TIOB[0..1] UTXD1 RXD0 TXD0 Timer Counter B SCK0 USART0 CRTTSS00 PDC TC[3..5] PDC NPCS0 NPCS1 NPCS2 SPI NPCS3 PWM[0:3] PWM MMIOSSO SPCK ADTRG PDC TWI0 TWCK0 AD[0..7] 10-bit ADC TWD0 ADVREF PDC TWI1 TWCK1 TWD1 SAM3N Summary 6 11011BS–ATARM–22-Feb-12

SAM3N Summary 3. Signal Description Table 3-1 gives details on the signal name classified by peripheral. Table 3-1. Signal Description List Active Voltage Signal Name Function Type Level Reference Comments Power Supplies VDDIO Peripherals I/O Lines Power Supply Power 1.62V to 3.6V Voltage Regulator, ADC and DAC Power VDDIN Power 1.8V to 3.6V(3) Supply VDDOUT Voltage Regulator Output Power 1.8V Output VDDPLL Oscillator and PLL Power Supply Power 1.65 V to 1.95V 1.65V to 1.95V Power the core, the embedded memories VDDCORE Power Connected externally and the peripherals to VDDOUT GND Ground Ground Clocks, Oscillators and PLLs XIN Main Oscillator Input Input Reset State: - PIO Input XOUT Main Oscillator Output Output - Internal Pull-up XIN32 Slow Clock Oscillator Input Input disabled - Schmitt Trigger XOUT32 Slow Clock Oscillator Output Output enabled(1) VDDIO Reset State: - PIO Input - Internal Pull-up PCK0 - PCK2 Programmable Clock Output Output enabled - Schmitt Trigger enabled(1) ICE and JTAG TCK/SWCLK Test Clock/Serial Wire Clock Input Reset State: TDI Test Data In Input - SWJ-DP Mode Test Data Out/Trace Asynchronous Data - Internal pull-up TDO/TRACESWO Output Out disabled VDDIO - Schmitt Trigger Test Mode Select /Serial Wire TMS/SWDIO Input / I/O enabled(1) Input/Output Permanent Internal JTAGSEL JTAG Selection Input High pull-down 7 11011BS–ATARM–22-Feb-12

Table 3-1. Signal Description List (Continued) Active Voltage Signal Name Function Type Level Reference Comments Flash Memory Reset State: - Erase Input Flash and NVM Configuration Bits Erase - Internal pull-down ERASE Input High VDDIO Command enabled - Schmitt Trigger enabled(1) Reset/Test Permanent Internal NRST Microcontroller Reset I/O Low VDDIO pull-up Permanent Internal TST Test Mode Select Input VDDIO pull-down Universal Asynchronous Receiver Transceiver - UARTx URXDx UART Receive Data Input UTXDx UART Transmit Data Output PIO Controller - PIOA - PIOB - PIOC PA0 - PA31 Parallel IO Controller A I/O Reset State: - PIO or System PB0 - PB14 Parallel IO Controller B I/O IOs(2) VDDIO - Internal pull-up enabled PC0 - PC31 Parallel IO Controller C I/O - Schmitt Trigger enabled(1) Universal Synchronous Asynchronous Receiver Transmitter USARTx SCKx USARTx Serial Clock I/O TXDx USARTx Transmit Data I/O RXDx USARTx Receive Data Input RTSx USARTx Request To Send Output CTSx USARTx Clear To Send Input Timer/Counter - TC TCLKx TC Channel x External Clock Input Input TIOAx TC Channel x I/O Line A I/O TIOBx TC Channel x I/O Line B I/O Pulse Width Modulation Controller- PWMC PWMx PWM Waveform Output for channel x Output SAM3N Summary 8 11011BS–ATARM–22-Feb-12

SAM3N Summary Table 3-1. Signal Description List (Continued) Active Voltage Signal Name Function Type Level Reference Comments Serial Peripheral Interface - SPI MISO Master In Slave Out I/O MOSI Master Out Slave In I/O SPCK SPI Serial Clock I/O SPI_NPCS0 SPI Peripheral Chip Select 0 I/O Low SPI_NPCS1 - SPI Peripheral Chip Select Output Low SPI_NPCS3 Two-Wire Interface- TWIx TWDx TWIx Two-wire Serial Data I/O TWCKx TWIx Two-wire Serial Clock I/O Analog ADVREF ADC and DAC Reference Analog 10-bit Analog-to-Digital Converter - ADC AD0 - AD15 Analog Inputs Analog ADTRG ADC Trigger Input VDDIO Digital-to-Analog Converter Controller- DACC DAC0 DACC channel analog output Analog DATRG DACC Trigger Input VDDIO Fast Flash Programming Interface PGMEN0-PGMEN2 Programming Enabling Input PGMM0-PGMM3 Programming Mode Input PGMD0-PGMD15 Programming Data I/O PGMRDY Programming Ready Output High VDDIO PGMNVALID Data Direction Output Low PGMNOE Programming Read Input Low PGMCK Programming Clock Input PGMNCMD Programming Command Input Low Notes: 1. Schmitt Triggers can be disabled through PIO registers. 2. Some PIO lines are shared with System IOs. 3. See Section 5.3 “Typical Powering Schematics” for restriction on voltage range of Analog Cells. 9 11011BS–ATARM–22-Feb-12

4. Package and Pinout SAM3N4/2/1/0/00 series is pin-to-pin compatible with SAM3S products. Furthermore SAM3N4/2/1/0/00 devices have new functionalities referenced in italic inTable 4-1, Table 4-3 and Table 4-4. 4.1 SAM3N4/2/1/0/00C Package and Pinout 4.1.1 100-lead LQFP Package Outline Figure 4-1. Orientation of the 100-lead LQFP Package 75 51 76 50 100 26 1 25 4.1.2 100-ball TFBGA Package Outline The 100-Ball TFBGA package has a 0.8 mm ball pitch and respects Green Standards. Its dimensions are 9 x 9 x 1.1 mm. Figure 4-2. Orientation of the 100-ball TFBGA Package TOP VIEW 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K BALL A1 SAM3N Summary 10 11011BS–ATARM–22-Feb-12

SAM3N Summary 4.1.3 100-Lead LQFP Pinout Table 4-1. 100-lead LQFP SAM3N4/2/1/0/00C Pinout 1 ADVREF 26 GND 51 TDI/PB4 76 TDO/TRACESWO/PB5 2 GND 27 VDDIO 52 PA6/PGMNOE 77 JTAGSEL 3 PB0/AD4 28 PA16/PGMD4 53 PA5/PGMRDY 78 PC18 4 PC29/AD13 29 PC7 54 PC28 79 TMS/SWDIO/PB6 5 PB1/AD5 30 PA15/PGMD3 55 PA4/PGMNCMD 80 PC19 6 PC30/AD14 31 PA14/PGMD2 56 VDDCORE 81 PA31 7 PB2/AD6 32 PC6 57 PA27 82 PC20 8 PC31/AD15 33 PA13/PGMD1 58 PC8 83 TCK/SWCLK/PB7 9 PB3/AD7 34 PA24 59 PA28 84 PC21 10 VDDIN 35 PC5 60 NRST 85 VDDCORE 11 VDDOUT 36 VDDCORE 61 TST 86 PC22 12 PA17/PGMD5/AD0 37 PC4 62 PC9 87 ERASE/PB12 13 PC26 38 PA25 63 PA29 88 PB10 14 PA18/PGMD6/AD1 39 PA26 64 PA30 89 PB11 15 PA21/AD8 40 PC3 65 PC10 90 PC23 16 VDDCORE 41 PA12/PGMD0 66 PA3 91 VDDIO 17 PC27 42 PA11/PGMM3 67 PA2/PGMEN2 92 PC24 18 PA19/PGMD7/AD2 43 PC2 68 PC11 93 PB13/DAC0 19 PC15/AD11 44 PA10/PGMM2 69 VDDIO 94 PC25 20 PA22/AD9 45 GND 70 GND 95 GND 21 PC13/AD10 46 PA9/PGMM1 71 PC14 96 PB8/XOUT 22 PA23 47 PC1 72 PA1/PGMEN1 97 PB9/PGMCK/XIN PA8/XOUT32/ 23 PC12/AD12 48 73 PC16 98 VDDIO PGMM0 PA7/XIN32/ 24 PA20/AD3 49 74 PA0/PGMEN0 99 PB14 PGMNVALID 25 PC0 50 VDDIO 75 PC17 100 VDDPLL 11 11011BS–ATARM–22-Feb-12

4.1.4 100-ball TFBGA Pinout Table 4-2. 100-ball TFBGA SAM3N4/2/1/0/00C Pinout A1 PB1 C6 PB7 F1 PA18 H6 PC4 A2 PC29 C7 PC16 F2 PC26 H7 PA11 A3 VDDIO C8 PA1 F3 VDDOUT H8 PC1 A4 PB9 C9 PC17 F4 GND H9 PA6 A5 PB8 C10 PA0 F5 VDDIO H10 PB4 A6 PB13 D1 PB3 F6 PA27 J1 PC15 A7 PB11 D2 PB0 F7 PC8 J2 PC0 A8 PB10 D3 PC24 F8 PA28 J3 PA16 A9 PB6 D4 PC22 F9 TST J4 PC6 A10 JTAGSEL D5 GND F10 PC9 J5 PA24 B1 PC30 D6 GND G1 PA21 J6 PA25 B2 ADVREF D7 VDDCORE G2 PC27 J7 PA10 B3 GNDANA D8 PA2 G3 PA15 J8 GND B4 PB14 D9 PC11 G4 VDDCORE J9 VDDCORE B5 PC21 D10 PC14 G5 VDDCORE J10 VDDIO B6 PC20 E1 PA17 G6 PA26 K1 PA22 B7 PA31 E2 PC31 G7 PA12 K2 PC13 B8 PC19 E3 VDDIN G8 PC28 K3 PC12 B9 PC18 E4 GND G9 PA4 K4 PA20 B10 PB5 E5 GND G10 PA5 K5 PC5 C1 PB2 E6 NRST H1 PA19 K6 PC3 C2 VDDPLL E7 PA29 H2 PA23 K7 PC2 C3 PC25 E8 PA30 H3 PC7 K8 PA9 C4 PC23 E9 PC10 H4 PA14 K9 PA8 C5 PB12 E10 PA3 H5 PA13 K10 PA7 SAM3N Summary 12 11011BS–ATARM–22-Feb-12

SAM3N Summary 4.2 SAM3N4/2/1/0/00B Package and Pinout Figure 4-3. Orientation of the 64-pad QFN Package 64 49 1 48 16 33 17 32 TOP VIEW Figure 4-4. Orientation of the 64-lead LQFP Package 48 33 49 32 64 17 1 16 13 11011BS–ATARM–22-Feb-12

4.2.1 64-Lead LQFP and QFN Pinout 64-pin version SAM3N devices are pin-to-pin compatible with SAM3S products. Furthermore, SAM3N products have new functionalities shown in italic in Table 4-3. Table 4-3. 64-pin SAM3N4/2/1/0/00B Pinout 1 ADVREF 17 GND 33 TDI/PB4 49 TDO/TRACESWO/PB5 2 GND 18 VDDIO 34 PA6/PGMNOE 50 JTAGSEL 3 PB0/AD4 19 PA16/PGMD4 35 PA5/PGMRDY 51 TMS/SWDIO/PB6 4 PB1AD5 20 PA15/PGMD3 36 PA4/PGMNCMD 52 PA31 5 PB2/AD6 21 PA14/PGMD2 37 PA27/PGMD15 53 TCK/SWCLK/PB7 6 PB3/AD7 22 PA13/PGMD1 38 PA28 54 VDDCORE 7 VDDIN 23 PA24/PGMD12 39 NRST 55 ERASE/PB12 8 VDDOUT 24 VDDCORE 40 TST 56 PB10 9 PA17/PGMD5/AD0 25 PA25/PGMD13 41 PA29 57 PB11 10 PA18/PGMD6/AD1 26 PA26/PGMD14 42 PA30 58 VDDIO 11 PA21/PGMD9/AD8 27 PA12/PGMD0 43 PA3 59 PB13/DAC0 12 VDDCORE 28 PA11/PGMM3 44 PA2/PGMEN2 60 GND 13 PA19/PGMD7/AD2 29 PA10/PGMM2 45 VDDIO 61 XOUT/PB8 14 PA22/PGMD10/AD9 30 PA9/PGMM1 46 GND 62 XIN/PGMCK/PB9 PA8/XOUT32/PGMM 15 PA23/PGMD11 31 47 PA1/PGMEN1 63 PB14 0 PA7/XIN32/XOUT32/ 16 PA20/PGMD8/AD3 32 48 PA0/PGMEN0 64 VDDPLL PGMNVALID Note: The bottom pad of the QFN package must be connected to ground. SAM3N Summary 14 11011BS–ATARM–22-Feb-12

SAM3N Summary 4.3 SAM3N4/2/1/0/00A Package and Pinout Figure 4-5. Orientation of the 48-pad QFN Package 48 37 1 36 12 25 13 24 TOP VIEW Figure 4-6. Orientation of the 48-lead LQFP Package 36 25 37 24 48 13 1 12 15 11011BS–ATARM–22-Feb-12

4.3.1 48-Lead LQFP and QFN Pinout Table 4-4. 48-pin SAM3N4/2/1/0/00A Pinout TDO/TRACESWO/ 1 ADVREF 13 VDDIO 25 TDI/PB4 37 PB5 2 GND 14 PA16/PGMD4 26 PA6/PGMNOE 38 JTAGSEL 3 PB0/AD4 15 PA15/PGMD3 27 PA5/PGMRDY 39 TMS/SWDIO/PB6 4 PB1/AD5 16 PA14/PGMD2 28 PA4/PGMNCMD 40 TCK/SWCLK/PB7 5 PB2/AD6 17 PA13/PGMD1 29 NRST 41 VDDCORE 6 PB3/AD7 18 VDDCORE 30 TST 42 ERASE/PB12 7 VDDIN 19 PA12/PGMD0 31 PA3 43 PB10 8 VDDOUT 20 PA11/PGMM3 32 PA2/PGMEN2 44 PB11 9 PA17/PGMD5/AD0 21 PA10/PGMM2 33 VDDIO 45 XOUT/PB8 10 PA18/PGMD6/AD1 22 PA9/PGMM1 34 GND 46 XIN/P/PB9/GMCK PA8/XOUT32/PG 11 PA19/PGMD7/AD2 23 35 PA1/PGMEN1 47 VDDIO MM0 PA7/XIN32/PGMN 12 PA20/AD3 24 36 PA0/PGMEN0 48 VDDPLL VALID Note: The bottom pad of the QFN package must be connected to ground. SAM3N Summary 16 11011BS–ATARM–22-Feb-12

SAM3N Summary 5. Power Considerations 5.1 Power Supplies The SAM3N product has several types of power supply pins: (cid:129) VDDCORE pins: Power the core, including the processor, the embedded memories and the peripherals. Voltage ranges from 1.62V and 1.95V. (cid:129) VDDIO pins: Power the Peripherals I/O lines, Backup part, 32 kHz crystal oscillator and oscillator pads. Voltage ranges from 1.62V and 3.6V (cid:129) VDDIN pin: Voltage Regulator, ADC and DAC Power Supply. Voltage ranges from 1.8V to 3.6V for the Voltage Regulator (cid:129) VDDPLL pin: Powers the PLL, the Fast RC and the 3 to 20 MHz oscillators. Voltage ranges from 1.62V and 1.95V. 5.2 Voltage Regulator The SAM3N embeds a voltage regulator that is managed by the Supply Controller. This internal regulator is intended to supply the internal core of SAM3N. It features two different operating modes: (cid:129) In Normal mode, the voltage regulator consumes less than 700 µA static current and draws 60 mA of output current. Internal adaptive biasing adjusts the regulator quiescent current depending on the required load current. In Wait Mode quiescent current is only 7 µA. (cid:129) In Backup mode, the voltage regulator consumes less than 1 µA while its output (VDDOUT) is driven internally to GND. The default output voltage is 1.80V and the start-up time to reach Normal mode is less than100 µs. For adequate input and output power supply decoupling/bypassing, refer to the Voltage Regula- tor section in the Electrical Characteristics section of the datasheet. 5.3 Typical Powering Schematics The SAM3N supports a 1.62V-3.6V single supply mode. The internal regulator input connected to the source and its output feeds VDDCORE. Figure 5-1 shows the power schematics. As VDDIN powers the voltage regulator and the ADC/DAC, when the user does not want to use the embedded voltage regulator, it can be disabled by software via the SUPC (note that it is dif- ferent from Backup mode). 17 11011BS–ATARM–22-Feb-12

Figure 5-1. Single Supply VDDIO I/Os. Main Supply (1.8V-3.6V) ADC, DAC VDDIN VDDOUT Voltage Regulator VDDCORE VDDPLL Figure 5-2. Core Externally Supplied VDDIO Main Supply (1.62V-3.6V) I/Os. Can be the same supply ADC, DAC ADC, DAC Supply VDDIN (3V-3.6V) VDDOUT Voltage Regulator VDDCORE VDDCORE Supply (1.62V-1.95V) VDDPLL Note: Restrictions With Main Supply < 3V, ADC and DAC are not usable. With Main Supply >= 3V, all peripherals are usable. Figure 5-3 below provides an example of the powering scheme when using a backup battery. Since the PIO state is preserved when in backup mode, any free PIO line can be used to switch off the external regulator by driving the PIO line at low level (PIO is input, pull-up enabled after backup reset). External wake-up of the system can be from a push button or any signal. See Section 5.6 “Wake-up Sources” for further details.TFBGA SAM3N Summary 18 11011BS–ATARM–22-Feb-12

SAM3N Summary Figure 5-3. Core Externally Supplied (backup battery) ADC, DAC Supply (3V-3.6V) VDDIO Backup I/Os. Battery + - ADC, DAC VDDIN Main Supply VDDOUT IN OUT Voltage 3.3V Regulator LDO VDDCORE ON/OFF VDDPLL PIOx (Output) WAKEUPx External wakeup signal Note: The two diodes provide a “switchover circuit” (for illustration purpose) between the backup battery and the main supply when the system is put in backup mode. 5.4 Active Mode Active mode is the normal running mode with the core clock running from the fast RC oscillator, the main crystal oscillator or the PLL. The power management controller can be used to adapt the frequency and to disable the peripheral clocks. 5.5 Low Power Modes The various low-power modes of the SAM3N are described below: 5.5.1 Backup Mode The purpose of backup mode is to achieve the lowest power consumption possible in a system that is performing periodic wakeups to carry out tasks but not requiring fast startup time (<0.1ms). Total current consumption is 3 µA typical. The Supply Controller, zero-power power-on reset, RTT, RTC, Backup registers and 32 kHz oscillator (RC or crystal oscillator selected by software in the Supply Controller) are running. The regulator and the core supply are off. Backup mode is based on the Cortex-M3 deep sleep mode with the voltage regulator disabled. The SAM3N can be awakened from this mode through WUP0-15 pins, the supply monitor (SM), the RTT or RTC wake-up event. Backup mode is entered by using WFE instructions with the SLEEPDEEP bit in the System Con- trol Register of the Cortex-M3 set to 1. (See the Power management description in The ARM Cortex M3 Processor section of the product datasheet). Exit from Backup mode happens if one of the following enable wake-up events occurs: (cid:129) WKUPEN0-15 pins (level transition, configurable debouncing) 19 11011BS–ATARM–22-Feb-12

(cid:129) Supply Monitor alarm (cid:129) RTC alarm (cid:129) RTT alarm 5.5.2 Wait Mode The purpose of the wait mode is to achieve very low power consumption while maintaining the whole device in a powered state for a startup time of less than 10 µs. Current Consumption in Wait mode is typically 15 µA (total current consumption) if the internal voltage regulator is used or 8 µA if an external regulator is used. In this mode, the clocks of the core, peripherals and memories are stopped. However, the core, peripherals and memories power supplies are still powered. From this mode, a fast start up is available. This mode is entered via Wait for Event (WFE) instructions with LPM = 1 (Low Power Mode bit in PMC_FSMR). The Cortex-M3 is able to handle external or internal events in order to wake up the core (WFE). By configuring the WUP0-15 external lines as fast startup wake-up pins (refer to Section 5.7 “Fast Start-Up”). RTC or RTT Alarm wake-up events can be used to wake up the CPU (exit from WFE). Entering Wait Mode: (cid:129) Select the 4/8/12 MHz fast RC oscillator as Main Clock (cid:129) Set the LPM bit in the PMC Fast Startup Mode Register (PMC_FSMR) (cid:129) Execute the Wait-For-Event (WFE) instruction of the processor Note: Internal Main clock resynchronization cycles are necessary between the writing of MOSCRCEN bit and the effective entry in Wait mode. Depending on the user application, Waiting for MOSCRCEN bit to be cleared is recommended to ensure that the core will not execute undesired instructions. 5.5.3 Sleep Mode The purpose of sleep mode is to optimize power consumption of the device versus response time. In this mode, only the core clock is stopped. The peripheral clocks can be enabled. The current consumption in this mode is application dependent. This mode is entered via Wait for Interrupt (WFI) or Wait for Event (WFE) instructions with LPM= 0 in PMC_FSMR. The processor can be woke up from an interrupt if WFI instruction of the Cortex M3 is used, or from an event if the WFE instruction is used to enter this mode. SAM3N Summary 20 11011BS–ATARM–22-Feb-12

SAM3N Summary 5.5.4 Low Power Mode Summary Table The modes detailed above are the main low power modes. Each part can be set to on or off sep- arately and wake up sources can be individually configured. Table 5-1 below shows a summary of the configurations of the low power modes. Table 5-1. Low Power Mode Configuration Summary SUPC, 32 kHz Oscillator RTC RTT Backup Registers, Core POR PIO State (Backup Memory Potential Wake Up Core at while in Low PIO State Consumption Wake Up Mode Region) Regulator Peripherals Mode Entry Sources Wake Up Power Mode at Wake Up (2) (3) Time(1) PIOA & WUP0-15 pins WFE PIOB & Backup OFF BOD alarm Previous ON OFF +SLEEPDEEP Reset PIOC 3 µA typ(4) < 0.1 ms Mode (Not powered) RTC alarm state saved bit = 1 Inputs with RTT alarm pull ups WFE Any Event from: Fast startup through Wait Powered +SLEEPDEEP Clocked Previous ON ON WUP0-15 pins Unchanged 5 µA/15 µA (5) < 10 µs Mode (Not clocked) bit = 0 back state saved RTC alarm +LPM bit = 1 RTT alarm Entry mode = WFI Interrupt Only; Entry mode = WFE Any WFE or WFI Enabled Interrupt Sleep Powered(7) +SLEEPDEEP and/or Any Event Clocked Previous ON ON Unchanged (6) (6) Mode (Not clocked) bit = 0 from: Fast start-up back state saved +LPM bit = 0 through WUP0-15 pins RTC alarm RTT alarm Notes: 1. When considering wake-up time, the time required to start the PLL is not taken into account. Once started, the device works with the 4/8/12 MHz Fast RC oscillator. The user has to add the PLL start-up time if it is needed in the system. The wake-up time is defined as the time taken for wake up until the first instruction is fetched. 2. The external loads on PIOs are not taken into account in the calculation. 3. Supply Monitor current consumption is not included. 4. Total Current consumption. 5. 5 µA on VDDCORE, 15 µA for total current consumption (using internal voltage regulator), 8 µA for total current consumption (without using internal voltage regulator). 6. Depends on MCK frequency. 7. In this mode the core is supplied and not clocked but some peripherals can be clocked. 21 11011BS–ATARM–22-Feb-12

5.6 Wake-up Sources The wake-up events allow the device to exit backup mode. When a wake-up event is detected, the Supply Controller performs a sequence which automatically reenables the core power sup- ply and the SRAM power supply, if they are not already enabled. Figure 5-4. Wake-up Source BODEN brown_out RTCEN rtc_alarm Core RTTEN Supply rtt_alarm Restart WKUPT0 WKUPEN0 WKUPIS0 Falling/Rising WKUP0 Edge WKUPDBC Detector WKUPT1 WKUPEN1 WKUPIS1 SLCK WKUPS Falling/Rising Debouncer WKUP1 Edge Detector WKUPT15 WKUPEN15 WKUPIS15 Falling/Rising WKUP15 Edge Detector SAM3N Summary 22 11011BS–ATARM–22-Feb-12

SAM3N Summary 5.7 Fast Start-Up The SAM3N allows the processor to restart in a few microseconds while the processor is in wait mode. A fast start up can occur upon detection of a low level on one of the 19 wake-up inputs (WKUP0 to 15 + SM + RTC + RTT). The fast restart circuitry, as shown in Figure 5-5, is fully asynchronous and provides a fast start- up signal to the Power Management Controller. As soon as the fast start-up signal is asserted, the PMC automatically restarts the embedded 4 MHz fast RC oscillator, switches the master clock on this 4 MHz clock and reenables the processor clock. Figure 5-5. Fast Start-Up Sources RTCEN rtc_alarm RTTEN rtt_alarm FSTT0 fast_restart Falling/Rising WKUP0 Edge Detector FSTT15 Falling/Rising WKUP15 Edge Detector 23 11011BS–ATARM–22-Feb-12

6. Input/Output Lines The SAM3N has several kinds of input/output (I/O) lines such as general purpose I/Os (GPIO) and system I/Os. GPIOs can have alternate functionality due to multiplexing capabilities of the PIO controllers. The same PIO line can be used whether in IO mode or by the multiplexed peripheral. System I/Os include pins such as test pins, oscillators, erase or analog inputs. 6.1 General Purpose I/O Lines GPIO Lines are managed by PIO Controllers. All I/Os have several input or output modes such as pull-up or pull-down, input Schmitt triggers, multi-drive (open-drain), glitch filters, debouncing or input change interrupt. Programming of these modes is performed independently for each I/O line through the PIO controller user interface. For more details, refer to the product PIO control- ler section. The input output buffers of the PIO lines are supplied through VDDIO power supply rail. The SAM3N embeds high speed pads able to handle up to 45 MHz for SPI clock lines and 35 MHz on other lines. See AC Characteristics Section in the Electrical Characteristics Section of the datasheet for more details. Typical pull-up and pull-down value is 100 kΩ for all I/Os. Each I/O line also embeds an ODT (On-Die Termination), (see Figure 6-1). It consists of an internal series resistor termination scheme for impedance matching between the driver output (SAM3N) and the PCB trace impedance preventing signal reflection. The series resistor helps to reduce I/O switching current (di/dt) thereby reducing in turn, EMI. It also decreases overshoot and undershoot (ringing) due to inductance of interconnect between devices or between boards. In conclusion ODT helps diminish signal integrity issues. Figure 6-1. On-Die Termination Z0 ~ Zout + Rodt ODT 36 Ohms Typ. Rodt Receiver SAM3 Driver with PCB Trace Zout ~ 10 Ohms Z0 ~ 50 Ohms 6.2 System I/O Lines System I/O lines are pins used by oscillators, test mode, reset and JTAG to name but a few. Described below are the SAM3N system I/O lines shared with PIO lines: These pins are software configurable as general purpose I/O or system pins. At startup the default function of these pins is always used. SAM3N Summary 24 11011BS–ATARM–22-Feb-12

SAM3N Summary Table 6-1. System I/O Configuration Pin List. SYSTEM_IO Default function Constraints for bit number after reset Other function normal start Configuration Low Level at 12 ERASE PB12 startup(1) In Matrix User Interface Registers 7 TCK/SWCLK PB7 - (Refer to the System I/O Configuration Register in the Bus 6 TMS/SWDIO PB6 - Matrix section of the product 5 TDO/TRACESWO PB5 - datasheet.) 4 TDI PB4 - - PA7 XIN32 - See footnote (2) below - PA8 XOUT32 - - PB9 XIN - See footnote (3) below - PB8 XOUT - Notes: 1. If PB12 is used as PIO input in user applications, a low level must be ensured at startup to prevent Flash erase before the user application sets PB12 into PIO mode. 2. In the product Datasheet Refer to: Slow Clock Generator of the Supply Controller section. 3. In the product Datasheet Refer to: 3 to 20 MHZ Crystal Oscillator information in the PMC section. 6.2.1 Serial Wire JTAG Debug Port (SWJ-DP) Pins The SWJ-DP pins are TCK/SWCLK, TMS/SWDIO, TDO/SWO, TDI and commonly provided on a standard 20-pin JTAG connector defined by ARM. For more details about voltage reference and reset state, refer to Table 3-1 on page 7. At startup, SWJ-DP pins are configured in SWJ-DP mode to allow connection with debugging probe. Please refer to the Debug and Test Section of the product datasheet. SWJ-DP pins can be used as standard I/Os to provide users more general input/output pins when the debug port is not needed in the end application. Mode selection between SWJ-DP mode (System IO mode) and general IO mode is performed through the AHB Matrix Special Function Registers (MATRIX_SFR). Configuration of the pad for pull-up, triggers, debouncing and glitch filters is possible regardless of the mode. The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. It integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left uncon- nected for normal operations. By default, the JTAG Debug Port is active. If the debugger host wants to switch to the Serial Wire Debug Port, it must provide a dedicated JTAG sequence on TMS/SWDIO and TCK/SWCLK which disables the JTAG-DP and enables the SW-DP. When the Serial Wire Debug Port is active, TDO/TRACESWO can be used for trace. The asynchronous TRACE output (TRACESWO) is multiplexed with TDO. So the asynchronous trace can only be used with SW-DP, not JTAG-DP. For more information about SW-DP and JTAG-DP switching, please refer to the Debug and Test Section. 25 11011BS–ATARM–22-Feb-12

6.3 Test Pin The TST pin is used for JTAG Boundary Scan Manufacturing Test or Fast Flash programming mode of the SAM3N series. The TST pin integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations. To enter fast programming mode, see the Fast Flash Programming Interface (FFPI) section. For more on the manufacturing and test mode, refer to the “Debug and Test” section of the product datasheet. 6.4 NRST Pin The NRST pin is bidirectional. It is handled by the on-chip reset controller and can be driven low to provide a reset signal to the external components or asserted low externally to reset the microcontroller. It will reset the Core and the peripherals except the Backup region (RTC, RTT and Supply Controller). There is no constraint on the length of the reset pulse and the reset con- troller can guarantee a minimum pulse length. The NRST pin integrates a permanent pull-up resistor to VDDIO of about 100 kΩ . By default, the NRST pin is configured as an input. 6.5 ERASE Pin The ERASE pin is used to reinitialize the Flash content (and some of its NVM bits) to an erased state (all bits read as logic level 1). It integrates a pull-down resistor of about 100 kΩ to GND, so that it can be left unconnected for normal operations. This pin is debounced by SCLK to improve the glitch tolerance. When the ERASE pin is tied high during less than 100 ms, it is not taken into account. The pin must be tied high during more than 220 ms to perform a Flash erase operation. The ERASE pin is a system I/O pin and can be used as a standard I/O. At startup, the ERASE pin is not configured as a PIO pin. If the ERASE pin is used as a standard I/O, startup level of this pin must be low to prevent unwanted erasing. Please refer to Section 11.2 “Peripheral Sig- nals Multiplexing on I/O Lines” on page 42. Also, if the ERASE pin is used as a standard I/O output, asserting the pin to low does not erase the Flash. SAM3N Summary 26 11011BS–ATARM–22-Feb-12

SAM3N Summary 7. Processor and Architecture 7.1 ARM Cortex-M3 Processor (cid:129) Version 2.0 (cid:129) Thumb-2 (ISA) subset consisting of all base Thumb-2 instructions, 16-bit and 32-bit. (cid:129) Harvard processor architecture enabling simultaneous instruction fetch with data load/store. (cid:129) Three-stage pipeline. (cid:129) Single cycle 32-bit multiply. (cid:129) Hardware divide. (cid:129) Thumb and Debug states. (cid:129) Handler and Thread modes. (cid:129) Low latency ISR entry and exit. 7.2 APB/AHB Bridge The SAM3N4/2/1/0/00 product embeds one peripheral bridge: The peripherals of the bridge are clocked by MCK. 7.3 Matrix Masters The Bus Matrix of the SAM3N product manages 3 masters, which means that each master can perform an access concurrently with others, to an available slave. Each master has its own decoder, which is defined specifically for each master. In order to sim- plify the addressing, all the masters have the same decodings. Table 7-1. List of Bus Matrix Masters Master 0 Cortex-M3 Instruction/Data Master 1 Cortex-M3 System Master 2 Peripheral DMA Controller (PDC) 7.4 Matrix Slaves The Bus Matrix of the SAM3N product manages 4 slaves. Each slave has its own arbiter, allow- ing a different arbitration per slave. Table 7-2. List of Bus Matrix Slaves Slave 0 Internal SRAM Slave 1 Internal ROM Slave 2 Internal Flash Slave 3 Peripheral Bridge 27 11011BS–ATARM–22-Feb-12

7.5 Master to Slave Access All the Masters can normally access all the Slaves. However, some paths do not make sense, for example allowing access from the Cortex-M3 S Bus to the Internal ROM. Thus, these paths are forbidden or simply not wired, and shown as “-” in Table 7-3. Table 7-3. SAM3N Master to Slave Access Masters 0 1 2 Slaves Cortex-M3 I/D Bus Cortex-M3 S Bus PDC 0 Internal SRAM - X X 1 Internal ROM X - X 2 Internal Flash X - - 3 Peripheral Bridge - X X 7.6 Peripheral DMA Controller (cid:129) Handles data transfer between peripherals and memories (cid:129) Low bus arbitration overhead – One Master Clock cycle needed for a transfer from memory to peripheral – Two Master Clock cycles needed for a transfer from peripheral to memory (cid:129) Next Pointer management for reducing interrupt latency requirement The Peripheral DMA Controller handles transfer requests from the channel according to the fol- lowing priorities (Low to High priorities): Table 7-4. Peripheral DMA Controller Instance name Channel T/R 100 & 64 Pins 48 Pins TWI0 Transmit x x UART0 Transmit x x USART0 Transmit x x DAC Transmit x N/A SPI Transmit x x TWI0 Receive x x UART0 Receive x x USART0 Receive x x ADC Receive x x SPI Receive x x SAM3N Summary 28 11011BS–ATARM–22-Feb-12

SAM3N Summary 7.7 Debug and Test Features (cid:129) Debug access to all memory and registers in the system, including Cortex-M3 register bank when the core is running, halted, or held in reset. (cid:129) Serial Wire Debug Port (SW-DP) and Serial Wire JTAG Debug Port (SWJ-DP) debug access (cid:129) Flash Patch and Breakpoint (FPB) unit for implementing breakpoints and code patches (cid:129) Data Watchpoint and Trace (DWT) unit for implementing watchpoints, data tracing, and system profiling (cid:129) Instrumentation Trace Macrocell (ITM) for support of printf style debugging (cid:129) IEEE1149.1 JTAG Boundary-can on All Digital Pins 29 11011BS–ATARM–22-Feb-12

8. Product Mapping Figure 8-1. SAM3N4/2/1/0/00 Product Mapping 0x00000000 Code 0x00000000Address Memory Space 0x40000000 Peripherals 0x400E0000 System Controller Boot Memory Reserved Reserved 0x00400000 Code 0x40004000 0x400E0200 Internal Flash Reserved MATRIX 0x00800000 1 MByte 0x20000000 0x40008000 0x400E0400 0x00C00000 Internal ROM briet gbiaonnd 0x20100000 SRAM 0x4000C000 SPI 21 0x400E0600 PMC 5 Reserved Reserved UART0 0x1FFFFFFF 0x22000000 0x40010000 0x400E0740 8 TC0 Undefined TC0 CHIPID 0x24000000 +0x40 23 0x400E0800 32 MBytes TC0 0x40000000 bit band alias +0x80 TC1 24 0x400E0A00 UART1 9 TC0 TC2 EEFC Peripherals 0x40014000 TC1 25 0x400E0C00 6 TC3 Reserved 0x60000000 +0x40 26 0x400E0E00 TC1 Reserved +0x80 TC4 27 0x400E1000 PIOA 11 TC1 TC5 PIOB 0xA0000000 0x40018000 28 0x400E1200 12 TWI0 PIOC Reserved 0x4001C000 19 0x400E1400 13 1 MByte SYSC TWI1 bit band RSTC 0xE0000000 0x40020000 20 region +0x10 1 SYSC PWM SUPC System 0x40024000 31 +0x30 SYSC USART0 RTT 0xFFFFFFFF 0x40028000 14 +0x50 3 SYSC USART1 WDT 0x4002C000 15 +0x60 4 SYSC Reserved RTC 0x40038000 +0x90 2 offset SYSC block ADC GPBR peripheral ID 0x4003C000 29 0x400E1600 DACC Reserved 0x40040000 30 0x4007FFFF Reserved 0x40044000 Reserved 0x40048000 Reserved 0x400E0000 System Controller 0x400E2600 RReesseerrvveedd 0x40100000 Reserved 0x40200000 32 MBytes bit band alias 0x40400000 Reserved 0x60000000 SAM3N Summary 30 11011BS–ATARM–22-Feb-12

SAM3N Summary 9. Memories 9.1 Embedded Memories 9.1.1 Internal SRAM The SAM3N4 product embeds a total of 24-Kbytes high-speed SRAM. The SAM3N2 product embeds a total of 16-Kbytes high-speed SRAM. The SAM3N1 product embeds a total of 8-Kbytes high-speed SRAM. The SRAM is accessible over System Cortex-M3 bus at address 0x2000 0000. The SRAM is in the bit band region. The bit band alias region is from 0x2200 0000 and 0x23FF FFFF. RAM size must be configurable by calibration fuses. 9.1.2 Internal ROM The SAM3N product embeds an Internal ROM, which contains the SAM Boot Assistant (SAM-BA), In Application Programming routines (IAP) and Fast Flash Programming Interface (FFPI). At any time, the ROM is mapped at address 0x0080 0000. 9.1.3 Embedded Flash 9.1.3.1 Flash Overview The Flash of the SAM3N4 (256 Kbytes) is organized in one bank of 1024 pages of 256 bytes (Single plane). The Flash of the SAM3N2 (128 Kbytes) is organized in one bank of 512 pages of 256 bytes (Sin- gle Plane). The Flash of the SAM3N1 (64 Kbytes) is organized in one bank of 256 pages of 256 bytes (Sin- gle plane). The Flash contains a 128-byte write buffer, accessible through a 32-bit interface. 9.1.3.2 Flash Power Supply The Flash is supplied by VDDCORE. 9.1.3.3 Enhanced Embedded Flash Controller The Enhanced Embedded Flash Controller (EEFC) manages accesses performed by the mas- ters of the system. It enables reading the Flash and writing the write buffer. It also contains a User Interface, mapped on the APB. The Enhanced Embedded Flash Controller ensures the interface of the Flash block with the 32- bit internal bus. Its 128-bit wide memory interface increases performance. The user can choose between high performance or lower current consumption by selecting either 128-bit or 64-bit access. It also manages the programming, erasing, locking and unlocking sequences of the Flash using a full set of commands. One of the commands returns the embedded Flash descriptor definition that informs the system about the Flash organization, thus making the software generic. 31 11011BS–ATARM–22-Feb-12

9.1.3.4 Flash Speed The user needs to set the number of wait states depending on the frequency used. For more details, refer to the AC Characteristics sub section in the product Electrical Character- istics Section. 9.1.3.5 Lock Regions Several lock bits used to protect write and erase operations on lock regions. A lock region is composed of several consecutive pages, and each lock region has its associated lock bit. Table 9-1. Lock bit number Product Number of lock bits Lock region size SAM3N4 16 16 kbytes (64 pages) SAM3N2 8 16 kbytes (64 pages) SAM3N1 4 16 kbytes (64 pages) If a locked-region’s erase or program command occurs, the command is aborted and the EEFC triggers an interrupt. The lock bits are software programmable through the EEFC User Interface. The command “Set Lock Bit” enables the protection. The command “Clear Lock Bit” unlocks the lock region. Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash. 9.1.3.6 Security Bit Feature The SAM3N features a security bit, based on a specific General Purpose NVM bit (GPNVM bit 0). When the security is enabled, any access to the Flash, either through the ICE interface or through the Fast Flash Programming Interface, is forbidden. This ensures the confidentiality of the code programmed in the Flash. This security bit can only be enabled, through the command “Set General Purpose NVM Bit 0” of the EEFC User Interface. Disabling the security bit can only be achieved by asserting the ERASE pin at 1, after a full Flash erase is performed. When the security bit is deactivated, all accesses to the Flash are permitted. It is important to note that the assertion of the ERASE pin should always be longer than 200 ms. As the ERASE pin integrates a permanent pull-down, it can be left unconnected during normal operation. However, it is safer to connect it directly to GND for the final application. 9.1.3.7 Calibration Bits NVM bits are used to calibrate the brownout detector and the voltage regulator. These bits are factory configured and cannot be changed by the user. The ERASE pin has no effect on the cal- ibration bits. 9.1.3.8 Unique Identifier Each device integrates its own 128-bit unique identifier. These bits are factory configured and cannot be changed by the user. The ERASE pin has no effect on the unique identifier. SAM3N Summary 32 11011BS–ATARM–22-Feb-12

SAM3N Summary 9.1.3.9 Fast Flash Programming Interface The Fast Flash Programming Interface allows programming the device through either a serial JTAG interface or through a multiplexed fully-handshaked parallel port. It allows gang program- ming with market-standard industrial programmers. The FFPI supports read, page program, page erase, full erase, lock, unlock and protect commands. The Fast Flash Programming Interface is enabled and the Fast Programming Mode is entered when TST and PA0 and PA1are tied low. 9.1.3.10 SAM-BA Boot The SAM-BA Boot is a default Boot Program which provides an easy way to program in-situ the on-chip Flash memory. The SAM-BA Boot Assistant supports serial communication via the UART0. The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI). The SAM-BA Boot is in ROM and is mapped in Flash at address 0x0 when GPNVM bit 1 is set to 0. 9.1.3.11 GPNVM Bits The SAM3N features three GPNVM bits that can be cleared or set respectively through the com- mands “Clear GPNVM Bit” and “Set GPNVM Bit” of the EEFC User Interface. . Table 9-2. General-purpose Non volatile Memory Bits GPNVMBit[#] Function 0 Security bit 1 Boot mode selection 9.1.4 Boot Strategies The system always boots at address 0x0. To ensure a maximum boot possibilities the memory layout can be changed via GPNVM. A general purpose NVM (GPNVM) bit is used to boot either on the ROM (default) or from the Flash. The GPNVM bit can be cleared or set respectively through the commands “Clear General-pur- pose NVM Bit” and “Set General-purpose NVM Bit” of the EEFC User Interface. Setting the GPNVM Bit 1 selects the boot from the Flash, clearing it selects the boot from the ROM. Asserting ERASE clears the GPNVM Bit 1 and thus selects the boot from the ROM by default. 33 11011BS–ATARM–22-Feb-12

10. System Controller The System Controller is a set of peripherals, which allow handling of key elements of the sys- tem, such as power, resets, clocks, time, interrupts, watchdog, etc... See the System Controller block diagram in Figure 10-1 on page 35. SAM3N Summary 34 11011BS–ATARM–22-Feb-12

SAM3N Summary Figure 10-1. System Controller Block Diagram VDDIO VDDOUT vr_on Software Controlled vr_mode Voltage Regulator VDDIN Zero-Power Supply Power-on Reset Controller VDDIO bod_on Supply PIOA/B/C PIOx Monitor brown_out (Backup) WKUP0 - WKUP15 Genera l Purpose ADC ADx Backup Registers ADVREF rtc_nreset SLCK RTC DAC rtc_alarm DAC0 rtt_nreset SLCK RTT rtt_alarm osc32k_xtal_en core_nreset XIN32 Xtal 32 kHz osc32k_sel Oscillator Slow Clock bod_core_on Brownout XOUT32 SLCK lcore_brown_out Detector (Core) Embedded 32 kHz RC osc32k_rc_en Oscillator SRAM Backup Power Supply Peripherals core_nreset Reset proc_nreset Matrix VDDCORE Controller periph_nreset Peripheral ice_nreset Bridge NRST Cortex-M3 FSTT0 - FSTT15 Embedded SLCK 12/8/4 MHz Main Clock Flash RC MAINCK Master Clock Oscillator MCK Power XIN Xtal Management Oscillator Controller XOUT PLL SLCK Watchdog Timer Core Power Supply FSTT0 - FSTT15 are possible Fast Startup Sources, generated by WKUP0-WKUP15 Pins, but are not physical pins. 35 11011BS–ATARM–22-Feb-12

10.1 System Controller and Peripherals Mapping Please refer to Figure 8-1, "SAM3N4/2/1/0/00 Product Mapping" on page 30. All the peripherals are in the bit band region and are mapped in the bit band alias region. 10.2 Power-on-Reset, Brownout and Supply Monitor The SAM3N embeds three features to monitor, warn and/or reset the chip: (cid:129) Power-on-Reset on VDDIO (cid:129) Brownout Detector on VDDCORE (cid:129) Supply Monitor on VDDIO 10.2.1 Power-on-Reset The Power-on-Reset monitors VDDIO. It is always activated and monitors voltage at start up but also during power down. If VDDIO goes below the threshold voltage, the entire chip is reset. For more information, refer to the Electrical Characteristics section of the datasheet. 10.2.2 Brownout Detector on VDDCORE The Brownout Detector monitors VDDCORE. It is active by default. It can be deactivated by soft- ware through the Supply Controller (SUPC_MR). It is especially recommended to disable it during low-power modes such as wait or sleep modes. If VDDCORE goes below the threshold voltage, the reset of the core is asserted. For more infor- mation, refer to the Supply Controller (SUPC) and Electrical Characteristics sections of the datasheet. 10.2.3 Supply Monitor on VDDIO The Supply Monitor monitors VDDIO. It is inactive by default. It can be activated by software and is fully programmable with 16 steps for the threshold (between 1.9V to 3.4V). It is controlled by the Supply Controller (SUPC). A sample mode is possible. It allows to divide the supply monitor power consumption by a factor of up to 2048. For more information, refer to the SUPC and Elec- trical Characteristics sections of the datasheet. 10.3 Reset Controller The Reset Controller is based on a Power-on-Reset cell, and a Supply Monitor on VDDCORE. The Reset Controller is capable to return to the software the source of the last reset, either a general reset, a wake-up reset, a software reset, a user reset or a watchdog reset. The Reset Controller controls the internal resets of the system and the NRST pin input/output. It is capable to shape a reset signal for the external devices, simplifying to a minimum connection of a push-button on the NRST pin to implement a manual reset. The configuration of the Reset Controller is saved as supplied on VDDIO. 10.4 Supply Controller (SUPC) The Supply Controller controls the power supplies of each section of the processor and the peripherals (via Voltage regulator control) The Supply Controller has its own reset circuitry and is clocked by the 32 kHz slow clock generator. SAM3N Summary 36 11011BS–ATARM–22-Feb-12

SAM3N Summary The reset circuitry is based on a zero-power power-on reset cell and a brownout detector cell. The zero-power power-on reset allows the Supply Controller to start properly, while the soft- ware-programmable brownout detector allows detection of either a battery discharge or main voltage loss. The Slow Clock generator is based on a 32 kHz crystal oscillator and an embedded 32 kHz RC oscillator. The Slow Clock defaults to the RC oscillator, but the software can enable the crystal oscillator and select it as the Slow Clock source. The Supply Controller starts up the device by sequentially enabling the internal power switches and the Voltage Regulator, then it generates the proper reset signals to the core power supply. It also enables to set the system in different low power modes and to wake it up from a wide range of events. 10.5 Clock Generator The Clock Generator is made up of: (cid:129) One Low Power 32768Hz Slow Clock Oscillator with bypass mode (cid:129) One Low-Power RC Oscillator (cid:129) One 3-20 MHz Crystal or Ceramic resonator Oscillator, which can be bypassed (cid:129) One Fast RC Oscillator factory programmed, 3 output frequencies can be selected: 4, 8 or 12 MHz. By default 4 MHz is selected. (cid:129) One 60 to 130 MHz programmable PLL, capable to provide the clock MCK to the processor and to the peripherals. The input frequency of PLL is from 3.5 to 20 MHz. Figure 10-2. Clock Generator Block Diagram Clock Generator XTALSEL On Chip 32 kHz RC OSC Slow Clock SLCK XIN32 Slow Clock Oscillator XOUT32 XIN 3-20 MHz Main XOUT Oscillator Main Clock MAINCK On Chip 12/8/4 MHz RC OSC MAINSEL PLL and PLLA Clock Divider A PLLACK Status Control Power Management Controller 37 11011BS–ATARM–22-Feb-12

10.6 Power Management Controller The Power Management Controller provides all the clock signals to the system. It provides: (cid:129) the Processor Clock HCLK (cid:129) the Free running processor clock FCLK (cid:129) the Cortex SysTick external clock (cid:129) the Master Clock MCK, in particular to the Matrix and the memory interfaces (cid:129) independent peripheral clocks, typically at the frequency of MCK (cid:129) three programmable clock outputs: PCK0, PCK1 and PCK2 The Supply Controller selects between the 32 kHz RC oscillator or the crystal oscillator. The unused oscillator is disabled automatically so that power consumption is optimized. By default, at startup the chip runs out of the Master Clock using the Fast RC Oscillator running at 4 MHz. The user can trim by software the 8 and 12 MHz RC Oscillator frequency. Figure 10-3. SAM3N4/2/1/0/00 Power Management Controller Block Diagram Processor Clock HCK Controller int Sleep Mode Divider SystTick /8 FCLK Master Clock Controller SLCK Prescaler MAINCK /1,/2,/4,..,/64 MCK PLLCK Peripherals Clock Controller periph_clk[..] ON/OFF Programmable Clock Controller ON/OFF SLCK Prescaler pck[..] MAINCK /1,/2,/4,..,/64 PLLCK The SysTick calibration value is fixed at 6000 which allows the generation of a time base of 1 ms with SysTick clock at 6 MHz (48 MHz/8) 10.7 Watchdog Timer (cid:129) 16-bit key-protected only-once-Programmable Counter (cid:129) Windowed, prevents the processor to be in a dead-lock on the watchdog access SAM3N Summary 38 11011BS–ATARM–22-Feb-12

SAM3N Summary 10.8 SysTick Timer (cid:129) 24-bit down counter (cid:129) Self-reload capability (cid:129) Flexible System timer 10.9 Real-time Timer (cid:129) Real-time Timer, allowing backup of time with different accuracies – 32-bit Free-running back-up Counter – Integrates a 16-bit programmable prescaler running on slow clock – Alarm register capable to generate a wake-up of the system through the Shut Down Controller 10.10 Real Time Clock (cid:129) Low power consumption (cid:129) Full asynchronous design (cid:129) Two hundred year calendar (cid:129) Programmable Periodic Interrupt (cid:129) Alarm and update parallel load (cid:129) Control of alarm and update Time/Calendar Data In 10.11 General Purpose Backup Registers (cid:129) Eight 32-bit general-purpose backup registers 10.12 Nested Vectored Interrupt Controller (cid:129) Thirty Two maskable external interrupts (cid:129) Sixteen priority levels (cid:129) Processor state automatically saved on interrupt entry, and restored on (cid:129) Dynamic reprioritization of interrupts (cid:129) Priority grouping – selection of pre-empting interrupt levels and non pre-empting interrupt levels (cid:129) Support for tail-chaining and late arrival of interrupts – back-to-back interrupt processing without the overhead of state saving and restoration between interrupts. (cid:129) Processor state automatically saved on interrupt entry and restored on interrupt exit, with no instruction overhead 39 11011BS–ATARM–22-Feb-12

10.13 Chip Identification (cid:129) Chip Identifier (CHIPID) registers permit recognition of the device and its revision. Table 10-1. SAM3N Chip ID Register Chip Name CHIPID_CIDR CHIPID_EXID ATSAM3N4C (Rev A) 0x29540960 0x0 ATSAM3N2C (Rev A) 0x29590760 0x0 ATSAM3N1C (Rev A) 0x29580560 0x0 ATSAM3N4B (Rev A) 0x29440960 0x0 ATSAM3N2B (Rev A) 0x29490760 0x0 ATSAM3N1B (Rev A) 0x29480560 0x0 ATSAM3N4A (Rev A) 0x29340960 0x0 ATSAM3N2A (Rev A) 0x29390760 0x0 ATSAM3N1A (Rev A) 0x29380560 0x0 (cid:129) JTAG ID: 0x05B2E03F 10.14 UART (cid:129) Two-pin UART – Implemented features are 100% compatible with the standard Atmel USART – Independent receiver and transmitter with a common programmable Baud Rate Generator – Even, Odd, Mark or Space Parity Generation – Parity, Framing and Overrun Error Detection – Automatic Echo, Local Loopback and Remote Loopback Channel Modes – Support for two PDC channels with connection to receiver and transmitter 10.15 PIO Controllers (cid:129) 3 PIO Controllers, PIOA, PIOB and PIOC (100-pin version only) controlling a maximum of 79 I/O Lines (cid:129) Each PIO Controller controls up to 32 programmable I/O Lines (cid:129) Fully programmable through Set/Clear Registers Table 10-2. PIO available according to pin count Version 48 pin 64 pin 100 pin PIOA 21 32 32 PIOB 13 15 15 PIOC - - 32 (cid:129) Multiplexing of four peripheral functions per I/O Line (cid:129) For each I/O Line (whether assigned to a peripheral or used as general purpose I/O) – Input change, rising edge, falling edge, low level and level interrupt – Debouncing and Glitch filter SAM3N Summary 40 11011BS–ATARM–22-Feb-12

SAM3N Summary – Multi-drive option enables driving in open drain – Programmable pull up on each I/O line – Pin data status register, supplies visibility of the level on the pin at any time (cid:129) Selection of the drive level (cid:129) Synchronous output, provides Set and Clear of several I/O lines in a single write 11. Peripherals 11.1 Peripheral Identifiers Table 11-1 defines the Peripheral Identifiers of the SAM3N4/2/1/0/00. A peripheral identifier is required for the control of the peripheral interrupt with the Nested Vectored Interrupt Controller and for the control of the peripheral clock with the Power Management Controller. Table 11-1. Peripheral Identifiers Instance ID Instance Name NVIC Interrupt PMC Clock Control Instance Description 0 SUPC X Supply Controller 1 RSTC X Reset Controller 2 RTC X Real Time Clock 3 RTT X Real Time Timer 4 WDT X Watchdog Timer 5 PMC X Power Management Controller 6 EEFC X Enhanced Flash Controller 7 - - Reserved 8 UART0 X X UART 0 9 UART1 X X UART 1 10 - - - Reserved 11 PIOA X X Parallel I/O Controller A 12 PIOB X X Parallel I/O Controller B 13 PIOC X X Parallel I/O Controller C 14 USART0 X X USART 0 15 USART1 X X USART 1 16 - - - Reserved 17 - - - Reserved 18 - - - Reserved 19 TWI0 X X Two Wire Interface 0 20 TWI1 X X Two Wire Interface 1 21 SPI X X Serial Peripheral Interface 22 - - - Reserved 23 TC0 X X Timer/Counter 0 24 TC1 X X Timer/Counter 1 41 11011BS–ATARM–22-Feb-12

Table 11-1. Peripheral Identifiers (Continued) Instance ID Instance Name NVIC Interrupt PMC Clock Control Instance Description 25 TC2 X X Timer/Counter 2 26 TC3 X X Timer/Counter 3 27 TC4 X X Timer/Counter 4 28 TC5 X X Timer/Counter 5 29 ADC X X Analog-to-Digital Converter 30 DACC X X Digital-to-Analog Converter 31 PWM X X Pulse Width Modulation 11.2 Peripheral Signals Multiplexing on I/O Lines The SAM3N product features 2 PIO controllers (48-pin and 64-pin version) or 3 PIO controllers (100-pin version), PIOA, PIOB and PIOC, that multiplex the I/O lines of the peripheral set. The SAM3N 64-pin and 100-pin PIO Controller controls up to 32 lines (see Table10-2, “PIO available according to pin count,” on page40). Each line can be assigned to one of three periph- eral functions: A, B or C. The multiplexing tables in the following paragraphs define how the I/O lines of the peripherals A, B and C are multiplexed on the PIO Controllers. The column “Com- ments” has been inserted in this table for the user’s own comments; it may be used to track how pins are defined in an application. Note that some peripheral functions which are output only, might be duplicated within the tables. SAM3N Summary 42 11011BS–ATARM–22-Feb-12

SAM3N Summary 11.2.1 PIO Controller A Multiplexing Table 11-2. Multiplexing on PIO Controller A (PIOA) I/O Line Peripheral A Peripheral B Peripheral C Extra Function System Function Comments PA0 PWM0 TIOA0 WKUP0 High drive PA1 PWM1 TIOB0 WKUP1 High drive PA2 PWM2 SCK0 DATRG WKUP2 High drive PA3 TWD0 NPCS3 High drive PA4 TWCK0 TCLK0 WKUP3 PA5 RXD0 NPCS3 WKUP4 PA6 TXD0 PCK0 PA7 RTS0 PWM3 XIN32 PA8 CTS0 ADTRG WKUP5 XOUT32 PA9 URXD0 NPCS1 WKUP6 PA10 UTXD0 NPCS2 PA11 NPCS0 PWM0 WKUP7 PA12 MISO PWM1 PA13 MOSI PWM2 PA14 SPCK PWM3 WKUP8 PA15 TIOA1 WKUP14 PA16 TIOB1 WKUP15 PA17 PCK1 AD0 PA18 PCK2 AD1 PA19 AD2/WKUP9 PA20 AD3/WKUP10 PA21 RXD1 PCK1 AD8 64/100-pin versions PA22 TXD1 NPCS3 AD9 64/100-pin versions PA23 SCK1 PWM0 64/100-pin versions PA24 RTS1 PWM1 64/100-pin versions PA25 CTS1 PWM2 64/100-pin versions PA26 TIOA2 64/100-pin versions PA27 TIOB2 64/100-pin versions PA28 TCLK1 64/100-pin versions PA29 TCLK2 64/100-pin versions PA30 NPCS2 WKUP11 64/100-pin versions PA31 NPCS1 PCK2 64/100-pin versions 43 11011BS–ATARM–22-Feb-12

11.2.2 PIO Controller B Multiplexing Table 11-3. Multiplexing on PIO Controller B (PIOB) I/O Line Peripheral A Peripheral B Peripheral C Extra Function System Function Comments PB0 PWM0 AD4 PB1 PWM1 AD5 PB2 URXD1 NPCS2 AD6/WKUP12 PB3 UTXD1 PCK2 AD7 PB4 TWD1 PWM2 TDI TDO/ PB5 TWCK1 WKUP13 TRACESWO PB6 TMS/SWDIO PB7 TCK/SWCLK PB8 XOUT PB9 XIN PB10 PB11 PB12 ERASE PB13 PCK0 DAC0 64/100-pin versions PB14 NPCS1 PWM3 64/100-pin versions SAM3N Summary 44 11011BS–ATARM–22-Feb-12

SAM3N Summary 11.2.3 PIO Controller C Multiplexing I/O Line Peripheral A Peripheral B Peripheral C Extra Function System Function Comments PC0 100-pin version PC1 100-pin version PC2 100-pin version PC3 100-pin version PC4 NPCS1 100-pin version PC5 100-pin version PC6 100-pin version PC7 NPCS2 100-pin version PC8 PWM0 100-pin version PC9 PWM1 100-pin version PC10 PWM2 100-pin version PC11 PWM3 100-pin version PC12 AD12 100-pin version PC13 AD10 100-pin version PC14 PCK2 100-pin version PC15 AD11 100-pin version PC16 PCK0 100-pin version PC17 PCK1 100-pin version PC18 PWM0 100-pin version PC19 PWM1 100-pin version PC20 PWM2 100-pin version PC21 PWM3 100-pin version PC22 PWM0 100-pin version PC23 TIOA3 100-pin version PC24 TIOB3 100-pin version PC25 TCLK3 100-pin version PC26 TIOA4 100-pin version PC27 TIOB4 100-pin version PC28 TCLK4 100-pin version PC29 TIOA5 AD13 100-pin version PC30 TIOB5 AD14 100-pin version PC31 TCLK5 AD15 100-pin version 45 11011BS–ATARM–22-Feb-12

12. Embedded Peripherals Overview 12.1 Serial Peripheral Interface (SPI) (cid:129) Supports communication with serial external devices – Four chip selects with external decoder support allow communication with up to 15 peripherals – Serial memories, such as DataFlash and 3-wire EEPROMs – Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors – External co-processors (cid:129) Master or slave serial peripheral bus interface – 8- to 16-bit programmable data length per chip select – Programmable phase and polarity per chip select – Programmable transfer delays between consecutive transfers and between clock and data per chip select – Programmable delay between consecutive transfers – Selectable mode fault detection (cid:129) Very fast transfers supported – Transfers with baud rates up to MCK – The chip select line may be left active to speed up transfers on the same device 12.2 Two Wire Interface (TWI) (cid:129) Master, Multi-Master and Slave Mode Operation (cid:129) Compatibility with Atmel two-wire interface, serial memory and I2C compatible devices (cid:129) One, two or three bytes for slave address (cid:129) Sequential read/write operations (cid:129) Bit Rate: Up to 400 kbit/s (cid:129) General Call Supported in Slave Mode (cid:129) Connecting to PDC channel capabilities optimizes data transfers in Master Mode only (for TWI0 only) – One channel for the receiver, one channel for the transmitter – Next buffer support 12.3 Universal Asynchronous Receiver Transceiver (UART) (cid:129) Two-pin UART – Implemented features are 100% compatible with the standard Atmel USART – Independent receiver and transmitter with a common programmable Baud Rate Generator – Even, Odd, Mark or Space Parity Generation – Parity, Framing and Overrun Error Detection – Automatic Echo, Local Loopback and Remote Loopback Channel Modes SAM3N Summary 46 11011BS–ATARM–22-Feb-12

SAM3N Summary – Support for two PDC channels with connection to receiver and transmitter (for UART0 only) 12.4 USART (cid:129) Programmable Baud Rate Generator (cid:129) 5- to 9-bit full-duplex synchronous or asynchronous serial communications – 1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode – Parity generation and error detection – Framing error detection, overrun error detection – MSB- or LSB-first – Optional break generation and detection – By 8 or by-16 over-sampling receiver frequency – Hardware handshaking RTS-CTS – Receiver time-out and transmitter timeguard – Optional Multi-drop Mode with address generation and detection (cid:129) RS485 with driver control signal (cid:129) ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards (Only on USART0) – NACK handling, error counter with repetition and iteration limit (cid:129) SPI Mode – Master or Slave – Serial Clock programmable Phase and Polarity – SPI Serial Clock (SCK) Frequency up to MCK/4 (cid:129) IrDA modulation and demodulation (Only on USART0) – Communication at up to 115.2 Kbps (cid:129) Test Modes – Remote Loopback, Local Loopback, Automatic Echo (cid:129) PDC support (for USART0 only) 12.5 Timer Counter (TC) (cid:129) Six 16-bit Timer Counter Channels (cid:129) Wide range of functions including: – Frequency Measurement – Event Counting – Interval Measurement – Pulse Generation – Delay Timing – Pulse Width Modulation – Up/down Capabilities (cid:129) Each channel is user-configurable and contains: – Three external clock inputs – Five internal clock inputs 47 11011BS–ATARM–22-Feb-12

– Two multi-purpose input/output signals (cid:129) Two global registers that act on all three TC Channels (cid:129) Quadrature decoder – Advanced line filtering – Position/revolution/speed (cid:129) 2-bit Gray Up/Down Counter for Stepper Motor 12.6 Pulse Width Modulation Controller (PWM) (cid:129) Four channels, one 16-bit counter per channel (cid:129) Common clock generator, providing thirteen different clocks – One Modulo n counter providing eleven clocks – Two independent linear dividers working on modulo n counter outputs (cid:129) Independent channel programming – Independent enable/disable commands – Independent clock selection – Independent period and duty cycle, with double buffering – Programmable selection of the output waveform polarity 12.7 10-bit Analog-to-Digital Converter (cid:129) Up to 16-channel ADC (cid:129) 10-bit 384 Ksamples/sec. or 8-bit 583 Ksamples/sec. Successive Approximation Register ADC (cid:129) ±2 LSB Integral Non Linearity, ±1 LSB Differential Non Linearity (cid:129) Integrated 8-to-1 multiplexer, offering eight independent 3.3V analog inputs (cid:129) External voltage reference for better accuracy on low voltage inputs (cid:129) Individual enable and disable of each channel (cid:129) Multiple trigger source – Hardware or software trigger – External trigger pin – Timer Counter 0 to 2 outputs TIOA0 to TIOA2 trigger (cid:129) Sleep Mode and conversion sequencer – Automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels 12.8 Digital-to-Analog Converter (DAC) (cid:129) 1 channel 10-bit DAC (cid:129) Up to 500 ksamples/s conversion rate (cid:129) Flexible conversion range (cid:129) Multiple trigger sources (cid:129) One PDC channel SAM3N Summary 48 11011BS–ATARM–22-Feb-12

SAM3N Summary 13. Package Drawings The SAM3N series devices are available in LQFP, QFN and TFBGA packages. Figure 13-1. 100-lead LQFP Package Drawing Note : 1. This drawing is for general information only. Refer to JEDEC Drawing MS-026 for additional information. 49 11011BS–ATARM–22-Feb-12

Figure 13-2. 100-ball TFBGA Package Drawing SAM3N Summary 50 11011BS–ATARM–22-Feb-12

SAM3N Summary Figure 13-3. 64- and 48-lead LQFP Package Drawing 51 11011BS–ATARM–22-Feb-12

Table 13-1. 48-lead LQFP Package Dimensions (in mm) Millimeter Inch Symbol Min Nom Max Min Nom Max A – – 1.60 – – 0.063 A1 0.05 – 0.15 0.002 – 0.006 A2 1.35 1.40 1.45 0.053 0.055 0.057 D 9.00 BSC 0.354 BSC D1 7.00 BSC 0.276 BSC E 9.00 BSC 0.354 BSC E1 7.00 BSC 0.276 BSC R2 0.08 – 0.20 0.003 – 0.008 R1 0.08 – – 0.003 – – q 0° 3.5° 7° 0° 3.5° 7° θ 0° – – 0° – – 1 θ 11° 12° 13° 11° 12° 13° 2 θ 11° 12° 13° 11° 12° 13° 3 c 0.09 – 0.20 0.004 – 0.008 L 0.45 0.60 0.75 0.018 0.024 0.030 L1 1.00 REF 0.039 REF S 0.20 – – 0.008 – – b 0.17 0.20 0.27 0.007 0.008 0.011 e 0.50 BSC. 0.020 BSC. D2 5.50 0.217 E2 5.50 0.217 Tolerances of Form and Position aaa 0.20 0.008 bbb 0.20 0.008 ccc 0.08 0.003 ddd 0.08 0.003 SAM3N Summary 52 11011BS–ATARM–22-Feb-12

SAM3N Summary Table 13-2. 64-lead LQFP Package Dimensions (in mm) Millimeter Inch Symbol Min Nom Max Min Nom Max A – – 1.60 – – 0.063 A1 0.05 – 0.15 0.002 – 0.006 A2 1.35 1.40 1.45 0.053 0.055 0.057 D 12.00 BSC 0.472 BSC D1 10.00 BSC 0.383 BSC E 12.00 BSC 0.472 BSC E1 10.00 BSC 0.383 BSC R2 0.08 – 0.20 0.003 – 0.008 R1 0.08 – – 0.003 – – q 0° 3.5° 7° 0° 3.5° 7° θ 0° – – 0° – – 1 θ 11° 12° 13° 11° 12° 13° 2 θ 11° 12° 13° 11° 12° 13° 3 c 0.09 – 0.20 0.004 – 0.008 L 0.45 0.60 0.75 0.018 0.024 0.030 L1 1.00 REF 0.039 REF S 0.20 – – 0.008 – – b 0.17 0.20 0.27 0.007 0.008 0.011 e 0.50 BSC. 0.020 BSC. D2 7.50 0.285 E2 7.50 0.285 Tolerances of Form and Position aaa 0.20 0.008 bbb 0.20 0.008 ccc 0.08 0.003 ddd 0.08 0.003 53 11011BS–ATARM–22-Feb-12

Figure 13-4. 48-pad QFN Package Drawing SAM3N Summary 54 11011BS–ATARM–22-Feb-12

SAM3N Summary Table 13-3. 48-pad QFN Package Dimensions (in mm) Millimeter Inch Symbol Min Nom Max Min Nom Max A – – 090 – – 0.035 A1 – – 0.050 – – 0.002 A2 – 0.65 0.70 – 0.026 0.028 A3 0.20 REF 0.008 REF b 0.18 0.20 0.23 0.007 0.008 0.009 D 7.00 bsc 0.276 bsc D2 5.45 5.60 5.75 0.215 0.220 0.226 E 7.00 bsc 0.276 bsc E2 5.45 5.60 5.75 0.215 0.220 0.226 L 0.35 0.40 0.45 0.014 0.016 0.018 e 0.50 bsc 0.020 bsc R 0.09 – – 0.004 – – Tolerances of Form and Position aaa 0.10 0.004 bbb 0.10 0.004 ccc 0.05 0.002 55 11011BS–ATARM–22-Feb-12

Figure 13-5. 64-pad QFN Package Drawing SAM3N Summary 56 11011BS–ATARM–22-Feb-12

SAM3N Summary 14. Ordering Information Table 14-1. Flash Temperature Ordering Code MRL (Kbytes) Package Package Type Operating Range Industrial ATSAM3N4CA-AU A 256 LQFP100 Green -40°C to 85°C Industrial ATSAM3N4CA-CU A 256 TFBGA100 Green -40°C to 85°C Industrial ATSAM3N4BA-AU A 256 LQFP64 Green -40°C to 85°C Industrial ATSAM3N4BA-MU A 256 QFN64 Green -40°C to 85°C Industrial ATSAM3N4AA-AU A 256 LQFP48 Green -40°C to 85°C Industrial ATSAM3N4AA-MU A 256 QFN48 Green -40°C to 85°C Industrial ATSAM3N2CA-AU A 128 LQFP100 Green -40°C to 85°C Industrial ATSAM3N2CA-CU A 128 TFBGA100 Green -40°C to 85°C Industrial ATSAM3N2BA-AU A 128 LQFP64 Green -40°C to 85°C Industrial ATSAM3N2BA-MU A 128 QFN64 Green -40°C to 85°C Industrial ATSAM3N2AA-AU A 128 LQFP48 Green -40°C to 85°C Industrial ATSAM3N2AA-MU A 128 QFN48 Green -40°C to 85°C Industrial ATSAM3N1CA-AU A 64 LQFP100 Green -40°C to 85°C Industrial ATSAM3N1CB-AU B 64 LQFP100 Green -40°C to 85°C Industrial ATSAM3N1CA-CU A 64 TFBGA100 Green -40°C to 85°C Industrial ATSAM3N1CB-CU B 64 TFBGA100 Green -40°C to 85°C Industrial ATSAM3N1BA-AU A 64 LQFP64 Green -40°C to 85°C Industrial ATSAM3N1BB-AU B 64 LQFP64 Green -40°C to 85°C Industrial ATSAM3N1BA-MU A 64 QFN 64 Green -40°C to 85°C Industrial ATSAM3N1BB-MU B 64 QFN 64 Green -40°C to 85°C 57 11011BS–ATARM–22-Feb-12

Table 14-1. Flash Temperature Ordering Code MRL (Kbytes) Package Package Type Operating Range Industrial ATSAM3N1AA-AU A 64 LQFP48 Green -40°C to 85°C Industrial ATSAM3N1AB-AU B 64 LQFP48 Green -40°C to 85°C Industrial ATSAM3N1AA-MU A 64 QFN48 Green -40°C to 85°C Industrial ATSAM3N1AB-MU B 64 QFN48 Green -40°C to 85°C Industrial ATSAM3N0CA-AU A 32 LQFP100 Green -40°C to 85°C Industrial ATSAM3N0CA-CU A 32 TFBGA100 Green -40°C to 85°C Industrial ATSAM3N0BA-AU A 32 LQFP64 Green -40°C to 85°C Industrial ATSAM3N0BA-MU A 32 QFN64 Green -40°C to 85°C Industrial ATSAM3N0AA-AU A 32 LQFP48 Green -40°C to 85°C Industrial ATSAM3N0AA-MU A 32 QFN48 Green -40°C to 85°C Industrial ATSAM3N00BA-AU A 16 LQFP64 Green -40°C to 85°C Industrial ATSAM3N00BA-MU A 16 QFN64 Green -40°C to 85°C Industrial ATSAM3N00AA-AU A 16 LQFP48 Green -40°C to 85°C Industrial ATSAM3N00AA-MU A 16 QFN48 Green -40°C to 85°C SAM3N Summary 58 11011BS–ATARM–22-Feb-12

SAM3N Summary Revision History Doc. Rev. Change 11011BS Comments Request Ref. Overview: All mentions of 100-ball LFBGA changed into 100-ball TFBGA 8044 Section 8. “Product Mapping”, Heading was ‘Memories’. Changed to ‘Product Mapping’ 7685 Section 4.1.4 “100-ball TFBGA Pinout”, whole pinout table updated 7201 Updated package dimensions in ‘Features’ 7965 Change Doc. Rev Comments Request Ref. 11011AS First issue 59 11011BS–ATARM–22-Feb-12

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