Features • High-density, High-performance, Electrically-erasable Complex Programmable Logic Device – 3.0V to 3.6V Operating Range – 128 Macrocells – 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell – 84, 100, 160 Pins – 15 ns Maximum Pin-to-pin Delay – Registered Operation up to 77 MHz – Enhanced Routing Resources (cid:127) Flexible Logic Macrocell High- – D/T/Latch Configurable Flip-flops – Global and Individual Register Control Signals performance – Global and Individual Output Enable – Programmable Output Slew Rate EE PLD – Programmable Output Open Collector Option – Maximum Logic Utilization by Burying a Register within a COM Output (cid:127) Advanced Power Management Features – Automatic 5 µA Standby for “L” Version ATF1508ASV – Pin-controlled 100 µA Standby Mode – Programmable Pin-keeper Inputs and I/Os ATF1508ASVL – Reduced-power Feature per Macrocell (cid:127) Available in Commercial and Industrial Temperature Ranges (cid:127) Available in 84-lead PLCC and 100-lead PQFP and TQFP and 160-lead PQFP Packages (cid:127) Advanced EE Technology – 100% Tested – Completely Reprogrammable – 10,000 Program/Erase Cycles – 20 Year Data Retention – 2000V ESD Protection – 200 mA Latch-up Immunity (cid:127) JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported (cid:127) Fast In-System Programmability (ISP) via JTAG (cid:127) PCI-compliant (cid:127) Security Fuse Feature (cid:127) Green (Pb/Halide-free/RoHS Compliant) Package Options Enhanced Features (cid:127) Improved Connectivity (Additional Feedback Routing, Alternate Input Routing) (cid:127) Output Enable Product Terms (cid:127) Transparent-latch Mode (cid:127) Combinatorial Output with Registered Feedback within Any Macrocell (cid:127) Three Global Clock Pins (cid:127) ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O (cid:127) Fast Registered Input from Product Term (cid:127) Programmable “Pin-keeper” Option (cid:127) V Power-up Reset Option CC (cid:127) Pull-up Option on JTAG Pins TMS and TDI (cid:127) Advanced Power Management Features – Edge-controlled Power-down “L” – Individual Macrocell Power Option – Disable ITD on Global Clocks, Inputs and I/O for “Z” Parts Rev. 1408H–PLD–7/05 1

84-lead PLCC 100-lead PQFP Top View Top View I/OI/OI/OI/OGNDI/OI/OI/OVCCINTINPUT/OE2/GCLK2INPUT/GCLRINPUT/OE1INPUT/GCLK1GNDI/O/GCLK3I/OI/OVCCIOI/OI/OI/O I/OI/OI/OGNDI/OI/OI/OVCCINTINPUT/OE2/GCLK2INPUT/GCLRINPUT/OE1INPUT/GCLK1GNDI/O/GCLK3I/OI/OVCCIOI/OI/OI/O I/O/PD1 1211109876543218483828180797877767574 I/O 10099989796959493929190898887868584838281 I/O 1 80 I/O VCCIO 13 73 I/O I/O 2 79 I/O I/O/TDI 14 72 GND I/O/PD1 3 78 I/O I/O 15 71 I/O/TDO I/O 4 77 I/O I/O 16 70 I/O VCCIO 5 76 GND I/O 17 69 I/O I/O/TDI 6 75 I/O/TDO I/O 18 68 I/O I/O 7 74 I/O GND 19 67 I/O I/O 8 73 I/O I/O 20 66 VCCIO I/O 9 72 I/O I/O 21 65 I/O I/O 10 71 I/O I/O 22 64 I/O I/O 11 70 I/O I/O/TMS 23 63 I/O I/O 12 69 I/O I/O 24 62 I/O/TCK GND 13 68 VCCIO I/O 25 61 I/O I/O 14 67 I/O VCCIO 26 60 I/O I/O 15 66 I/O I/O 27 59 GND I/O 16 65 I/O I/O 28 58 I/O I/O/TMS 17 64 I/O/TCK I/O 29 57 I/O I/O 18 63 I/O I/O 19 62 I/O I/O 30 56 I/O VCCIO 20 61 GND I/O 31 55 I/O I/O 21 60 I/O GND 3233343536373839404142434445464748495051525354 I/O I/O 22 59 I/O I/O 23 58 I/O I/OI/OI/OI/OI/OVCCIOI/OI/OI/OGNDVCCINTI/OI/O/PD2I/OGNDI/OI/OI/OI/OI/OVCCIO III///OOO 222456 555765 III///OOO I/O 27 54 I/O GND 28 53 VCCIO I/O 29 52 I/O I/O 30 51 I/O 3132333435363738394041424344454647484950 I/OI/OI/OI/OI/OVCCIOI/OI/OI/OGNDVCCINTI/OI/O/PD2I/OGNDI/OI/OI/OI/OI/O 100-lead TQFP 160-lead PQFP Top View Top View I/OI/OI/OI/OI/OGNDI/OI/OI/OVCCINTINPUT/OE2/GCLK2INPUT/GCLRINPUT/OE1INPUT/GCLK1GNDI/O/GCLK3I/OI/OVCCIOI/OI/OI/OI/OI/OI/O 160I/O159I/O/PD2158I/O157N/C156N/C155N/C154N/C153I/O152I/O151I/O150I/O149I/O148GND147I/O146I/O145I/O144I/O143VCCINT142INPUT/OE2/GCLK2141INPUT/GCLR140INPUT/OE1139INPUT/GCLK1138GND137I/O/GCLK3136I/O135I/O134I/O133VCCIO132I/O131I/O130I/O129I/O128I/O127N/C126N/C125N/C124N/C123I/O122I/O121I/O 100999897969594939291908988878685848382818079787776 NN//CC 12 112109 NN//CC I/O/PD1 1 75 I/O NN//CC 34 111187 NN//CC I/O 2 74 GND N/C 5 116 N/C VCCIO 3 73 I/O/TDO N/C 6 115 N/C I/O/TDI 4 72 I/O N/C 7 114 N/C I/O 5 71 I/O IV/OC/CTIDOI 89 111132 GI/ON/DTDO I/O 6 70 I/O I/O 10 111 I/O I/O 7 69 I/O I/O 11 110 I/O I/O 8 68 I/O I/O 12 109 I/O I/O 9 67 I/O II//OO 1134 110087 II//OO I/O 10 66 VCCIO I/O 15 106 I/O GND 11 65 I/O I/O 16 105 I/O I/O 12 64 I/O GND 17 104 VCCIO I/O 18 103 I/O I/O 13 63 I/O I/O 19 102 I/O I/O 14 62 I/O/TCK I/O 20 101 I/O I/O/TMS 15 61 I/O I/O 21 100 I/O I/O 16 60 I/O I/O/TMS 22 99 I/O/TCK I/O 23 98 I/O I/O 17 59 GND I/O 24 97 I/O VCCIO 18 58 I/O I/O 25 96 I/O I/O 19 57 I/O VCCIO 26 95 GND I/O 20 56 I/O II//OO 2278 9943 II//OO I/O 21 55 I/O I/O 29 92 I/O I/O 22 54 I/O I/O 30 91 I/O I/O 23 53 I/O I/O 31 90 I/O I/O 24 52 I/O II//OO 3323 8898 II//OO I/O 25 51 VCCIO N/C 34 87 N/C N/C 35 86 N/C 26272829303133333435363738394041424344454647484950 N/C 36 85 N/C N/C 37 84 N/C GNDI/OI/OI/OI/OI/OI/OI/OVCCIOI/OI/OI/OGNDVCCINTI/OI/O/PD2I/OGNDI/OI/OI/OI/OI/OI/OI/O NNN///CCC 334890 888321 NNN///CCC 41424344454647484950515253545556575859606162636465666768697071727374757677787980 I/OGNDI/ON/CN/CN/CN/CI/OI/OI/OI/OI/OI/OI/OVCCIOI/OI/OI/OI/OGNDVCCINTI/OI/O/PD1I/OI/OGNDI/OI/OI/OI/OI/OI/OI/ON/CN/CN/CN/CI/OVCCIOI/O ATF1508ASV(L) 2 1408H–PLD–7/05

ATF1508ASV(L) Block Diagram 6 to 12 3 1408H–PLD–7/05

Description The ATF1508ASV(L) is a high-performance, high-density complex programmable logic device (CPLD) that utilizes Atmel’s proven electrically-erasable technology. With 128 logic macrocells and up to 100 inputs, it easily integrates logic from several TTL, SSI, MSI, LSI and classic PLDs. The ATF1508ASV(L)’s enhanced routing switch matrices increase usable gate count and increase odds of successful pin-locked design modifications. The ATF1508ASV(L) has up to 96 bi-directional I/O pins and four dedicated input pins, depending on the type of device package selected. Each dedicated pin can also serve as a global control signal, register clock, register reset or output enable. Each of these control signals can be selected for use individually within each macrocell. Each of the 128 macrocells generates a buried feedback that goes to the global bus. Each input and I/O pin also feeds into the global bus. The switch matrix in each logic block then selects 40 individual signals from the global bus. Each macrocell also gener- ates a foldback logic term that goes to a regional bus. Cascade logic between macrocells in the ATF1508ASV(L) allows fast, efficient generation of complex logic func- tions. The ATF1508ASV(L) contains eight such logic chains, each capable of creating sum term logic with a fan-in of up to 40 product terms. The ATF1508ASV(L) macrocell, shown in Figure 1, is flexible enough to support highly- complex logic functions operating at high-speed. The macrocell consists of five sections: product terms and product term select multiplexer, OR/XOR/CASCADE logic, a flip-flop, output select and enable, and logic array inputs. Unused macrocells are automatically disabled by the compiler to decrease power con- sumption. A security fuse, when programmed, protects the contents of the ATF1508ASV(L). Two bytes (16 bits) of User Signature are accessible to the user for purposes such as storing project name, part number, revision or date. The User Signa- ture is accessible regardless of the state of the security fuse. The ATF1508ASV(L) device is an in-system programmable (ISP) device. It uses the industry-standard 4-pin JTAG interface (IEEE Std. 1149.1), and is fully-compliant with JTAG’s Boundary-scan Description Language (BSDL). ISP allows the device to be pro- grammed without removing it from the printed circuit board. In addition to simplifying the manufacturing flow, ISP also allows design modifications to be made in the field via software. Product Terms and Select Each ATF1508ASV(L) macrocell has five product terms. Each product term receives as Mux its inputs all signals from both the global bus and regional bus. The product term select multiplexer (PTMUX) allocates the five product terms as needed to the macrocell logic gates and control signals. The PTMUX programming is determined by the design compiler, which selects the optimum macrocell configuration. OR/XOR/CASCADE Logic The ATF1508ASV(L)’s logic structure is designed to efficiently support all types of logic. Within a single macrocell, all the product terms can be routed to the OR gate, creating a 5-input AND/OR sum term. With the addition of the CASIN from neighboring macrocells, this can be expanded to as many as 40 product terms with little additional delay. The macrocell’s XOR gate allows efficient implementation of compare and arithmetic functions. One input to the XOR comes from the OR sum term. The other XOR input can be a product term or a fixed high- or low-level. For combinatorial outputs, the fixed level input allows polarity selection. For registered functions, the fixed levels allow DeMorgan minimization of product terms. The XOR gate is also used to emulate T- and JK-type flip-flops. ATF1508ASV(L) 4 1408H–PLD–7/05

ATF1508ASV(L) Flip-flop The ATF1508ASV(L)’s flip-flop has very flexible data and control functions. The data input can come from either the XOR gate, from a separate product term or directly from the I/O pin. Selecting the separate product term allows creation of a buried registered feedback within a combinatorial output macrocell. (This feature is automatically imple- mented by the fitter software). In addition to D, T, JK and SR operation, the flip-flop can also be configured as a flow-through latch. In this mode, data passes through when the clock is high and is latched when the clock is low. The clock itself can either be the Global CLK Signal (GCK) or an individual product term. The flip-flop changes state on the clock's rising edge. When the GCK signal is used as the clock, one of the macrocell product terms can be selected as a clock enable. When the clock enable function is active and the enable signal (product term) is low, all clock edges are ignored. The flip-flop’s asynchronous reset signal (AR) can be either the Glo- bal Clear (GCLEAR), a product term, or always off. AR can also be a logic OR of GCLEAR with a product term. The asynchronous preset (AP) can be a product term or always off. Figure 1. ATF1508ASV(L) Macrocell 5 1408H–PLD–7/05

Extra Feedback The ATF15xxSE Family macrocell output can be selected as registered or combinato- rial. The extra buried feedback signal can be either combinatorial or a registered signal regardless of whether the output is combinatorial or registered. (This enhancement function is automatically implemented by the fitter software.) Feedback of a buried com- binatorial output allows the creation of a second latch within a macrocell. I/O Control The output enable multiplexer (MOE) controls the output enable signal. Each I/O can be individually configured as an input, output or for bi-directional operation. The output enable for each macrocell can be selected from the true or compliment of the two output enable pins, a subset of the I/O pins, or a subset of the I/O macrocells. This selection is automatically done by the fitter software when the I/O is configured as an input, all mac- rocell resources are still available, including the buried feedback, expander and cascade logic. Global Bus/Switch Matrix The global bus contains all input and I/O pin signals as well as the buried feedback sig- nal from all 128 macrocells. The switch matrix in each logic block receives as its inputs all signals from the global bus. Under software control, up to 40 of these signals can be selected as inputs to the logic block. Foldback Bus Each macrocell also generates a foldback product term. This signal goes to the regional bus and is available to 16 macrocells. The foldback is an inverse polarity of one of the macrocell’s product terms. The 16 foldback terms in each region allow generation of high fan-in sum terms (up to 21 product terms) with little additional delay. Open-collector Output Option This option enables the device output to provide control signals such as an interrupt that can be asserted by any of the several devices. ATF1508ASV(L) 6 1408H–PLD–7/05

ATF1508ASV(L) Programmable Pin- The ATF1508ASV(L) offers the option of programming all input and I/O pins so that “pin- keeper Option for keeper” circuits can be utilized. When any pin is driven high or low and then subse- quently left floating, it will stay at that previous high- or low-level. This circuitry prevents Inputs and I/Os unused input and I/O lines from floating to intermediate voltage levels, which causes unnecessary power consumption and system noise. The keeper circuits eliminate the need for external pull-up resistors and eliminate their DC power consumption. Input Diagram Speed/Power The ATF1508ASV(L) has several built-in speed and power management features. The Management ATF1508ASV(L) contains circuitry that automatically puts the device into a low-power standby mode when no logic transitions are occurring. This not only reduces power con- sumption during inactive periods, but also provides proportional power-savings for most applications running at system speeds below 5 MHz. To further reduce power, each ATF1508ASV(L) macrocell has a reduced-power bit fea- ture. This feature allows individual macrocells to be configured for maximum power- savings. This feature may be selected as a design option. I/O Diagram 7 1408H–PLD–7/05

All ATF1508 also have an optional power-down mode. In this mode, current drops to below 10 mA. When the power-down option is selected, either PD1 or PD2 pins (or both) can be used to power down the part. The power-down option is selected in the design source file. When enabled, the device goes into power-down when either PD1 or PD2 is high. In the power-down mode, all internal logic signals are latched and held, as are any enabled outputs. All pin transitions are ignored until the PD pin is brought low. When the power-down fea- ture is enabled, the PD1 or PD2 pin cannot be used as a logic input or output. However, the pin’s macrocell may still be used to generate buried foldback and cascade logic signals. All power-down AC characteristic parameters are computed from external input or I/O pins, with reduced-power bit turned on. For macrocells in reduced-power mode (reduced-power bit turned on), the reduced-power adder, t , must be added to the AC RPA parameters, which include the data paths t , t , t , t , t and t . LAD LAC IC ACL ACH SEXP Each output also has individual slew rate control. This may be used to reduce system noise by slowing down outputs that do not need to operate at maximum speed. Outputs default to slow switching, and may be specified as fast switching in the design file. Design Software ATF1508ASV(L) designs are supported by several third-party tools. Automated fitters Support allow logic synthesis using a variety of high-level description languages and formats. Power-up Reset The ATF1508ASV is designed with a power-up reset, a feature critical for state machine initialization. At a point delayed slightly from V crossing V , all registers will be ini- CC RST tialized, and the state of each output will depend on the polarity of its buffer. However, due to the asynchronous nature of reset and uncertainty of how V actually rises in the CC system, the following conditions are required: 1. The V rise must be monotonic, CC 2. After reset occurs, all input and feedback setup times must be met before driving the clock pin high, and, 3. The clock must remain stable during T . D The ATF1508ASV has two options for the hysteresis about the reset level, V , Small RST and Large. To ensure a robust operating environment in applications where the device is operated near 3.0V, Atmel recommends that during the fitting process users configure the device with the Power-up Reset hysteresis set to Large. For conversions, Atmel POF2JED users should include the flag “-power_reset” on the command line after “file- name.POF”. To allow the registers to be properly reinitialized with the Large hysteresis option selected, the following condition is added: 4. If V falls below 2.0V, it must shut off completely before the device is turned on CC again. When the Large hysteresis option is active, I is reduced by several hundred micro- CC amps as well. Security Fuse Usage A single fuse is provided to prevent unauthorized copying of the ATF1508ASV(L) fuse patterns. Once programmed, fuse verify is inhibited. However, User Signature and device ID remains accessible. ATF1508ASV(L) 8 1408H–PLD–7/05

ATF1508ASV(L) Programming ATF1508ASV(L) devices are in-system programmable (ISP) devices utilizing the 4-pin JTAG protocol. This capability eliminates package handling normally required for pro- gramming and facilitates rapid design iterations and field changes. Atmel provides ISP hardware and software to allow programming of the ATF1508ASV(L) via the PC. ISP is performed by using either a download cable, a com- parable board tester or a simple microprocessor interface. To allow ISP programming support by the Automated Test Equipment (ATE) vendors, Serial Vector Format (SVF) files can be created by the Atmel ISP software. Conversion to other ATE tester format beside SVF is also possible ATF1508ASV(L) devices can also be programmed using standard third-party program- mers. With third-party programmer, the JTAG ISP port can be disabled thereby allowing four additional I/O pins to be used for logic. Contact your local Atmel representatives or Atmel PLD applications for details. ISP Programming The ATF1508ASV(L) has a special feature that locks the device and prevents the inputs Protection and I/O from driving if the programming process is interrupted for any reason. The inputs and I/O default to high-Z state during such a condition. In addition the pin-keeper option preserves the former state during device programming. All ATF1508ASV(L) devices are initially shipped in the erased state thereby making them ready to use for ISP. Note: For more information refer to the “Designing for In-System Programmability with Atmel CPLDs” application note. 9 1408H–PLD–7/05

DC and AC Operating Conditions Commercial Industrial Operating Temperature (Ambient) 0°C - 70°C -40°C - 85°C V (3.3V) Power Supply 3.0V - 3.6V 3.0V - 3.6V CC DC Characteristics Symbol Parameter Condition Min Typ Max Units Input or I/O Low I V = V -2 -10 µA IL Leakage Current IN CC Input or I/O High I 2 10 µA IH Leakage Current Tri-State Output I V = V or GND -40 40 µA OZ Off-State Current O CC Com. 115 mA Std Mode Power Supply V = Max Ind. 135 mA I CC CC1 Current, Standby VIN = 0, VCC Com. 5 µA “L” Mode Ind. 5 µA Power Supply Current, V = Max I CC “PD” Mode 0.1 5 mA CC2 Power-down Mode V = 0, V IN CC Reduced-power Mode V = Max Com. 60 mA I (2) CC Std Mode CC3 Supply Current, Standby VIN = 0, VCC Ind. 80 mA V Input Low Voltage -0.3 0.8 V IL V Input High Voltage 1.7 V + 0.3 V IH CCIO V = V or V Com. 0.45 V Output Low Voltage (TTL) IN IH IL VCC = Min, IOL = 8 mA Ind. 0.45 V V OL V = V or V Com. 0.2 V Output Low Voltage (CMOS) IN IH IL VCC = Min, IOL = 0.1 mA Ind. 0.2 V Output High Voltage V = V or V IN IH IL 2.4 V – 3.3V (TTL) V = Min, I = -2.0 mA CC OH V OH Output High Voltage V = V or V IN IH IL V - 0.2 V – 3.3V (CMOS) V = Min, I = -0.1 mA CCIO CCIO OH Notes: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec. 2. I refers to the current in the reduced-power mode when macrocell reduced-power is turned ON. CC3 Pin Capacitance Typ Max Units Conditions C 8 pF V = 0V; f = 1.0 MHz IN IN C 8 pF V = 0V; f = 1.0 MHz I/O OUT Note: Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. The OGI pin (high-voltage pin during programming) has a maximum capacitance of 12 pF. ATF1508ASV(L) 10 1408H–PLD–7/05

ATF1508ASV(L) Absolute Maximum Ratings* Temperature Under Bias..................................-40°C to +85°C *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam- Storage Temperature.....................................-65°C to +150°C age to the device. This is a stress rating only and functional operation of the device at these or any Voltage on Any Pin with other conditions beyond those indicated in the Respect to Ground.........................................-2.0V to +7.0V(1) operational sections of this specification is not implied. Exposure to absolute maximum rating Voltage on Input Pins conditions for extended periods may affect device with Respect to Ground reliability. During Programming.....................................-2.0V to +14.0V(1) Note: 1. Minimum voltage is -0.6V DC, which may under- shoot to -2.0V for pulses of less than 20 ns. Max- Programming Voltage with imum output pin voltage is V + 0.75V DC, CC Respect to Ground.......................................-2.0V to +14.0V(1) which may overshoot to 7.0V for pulses of less than 20 ns. Timing Model Internal Output Enable Delay tIOE Global Control Delay DIneplauyt tGLOB Register tIN Logic Array CascDaedlea yLogic DteSlUay Output Switch Delay tPEXP tH Delay MtUaItMrix Regis DttteLLteIrAAC lCDaCyontrol Fast Input tCttttPtCFORFSRLHDMRUEB ttttttOOOtZZZXXXXDDDZ123123 tEN Delay tFIN Foldback Term Delay tSEXP I/O Delay tIO 11 1408H–PLD–7/05

AC Characteristics(1) -15 -20 Symbol Parameter Min Max Min Max Units t Input or Feedback to Non-registered Output 3 15 20 ns PD1 t I/O Input or Feedback to Non-registered Feedback 3 12 16 ns PD2 t Global Clock Setup Time 11 13.5 ns SU t Global Clock Hold Time 0 0 ns H t Global Clock Setup Time of Fast Input 3 3 ns FSU t Global Clock Hold Time of Fast Input 1.0 2.0 MHz FH t Global Clock to Output Delay 9 12 ns COP t Global Clock High Time 5 6 ns CH t Global Clock Low Time 5 6 ns CL t Array Clock Setup Time 5 7 ns ASU t Array Clock Hold Time 4 4 ns AH t Array Clock Output Delay 15 18.5 ns ACOP t Array Clock High Time 6 8 ns ACH t Array Clock Low Time 6 8 ns ACL t Minimum Clock Global Period 13 17 ns CNT f Maximum Internal Global Clock Frequency 76.9 66 MHz CNT t Minimum Array Clock Period 13 17 ns ACNT f Maximum Internal Array Clock Frequency 76.9 58.8 MHz ACNT f Maximum Clock Frequency 100 83.3 MHz MAX t Input Pad and Buffer Delay 2 2.5 ns IN t I/O Input Pad and Buffer Delay 2 2.5 ns IO t Fast Input Delay 2 2 ns FIN t Foldback Term Delay 8 10 ns SEXP t Cascade Logic Delay 1 1 ns PEXP t Logic Array Delay 6 8 ns LAD t Logic Control Delay 3.5 4.5 ns LAC t Internal Output Enable Delay 3 3 ns IOE Output Buffer and Pad Delay t 3 4 ns OD1 (Slow slew rate = OFF; V = 5V; C = 35 pF) CCIO L Output Buffer and Pad Delay t 3 4 ns OD2 (Slow slew rate = OFF; V = 3.3V; C = 35 pF) CCIO L Output Buffer and Pad Delay t 5 6 ns OD3 (Slow slew rate = ON; V = 5V or 3.3V; C = 35 pF) CCIO L Output Buffer Enable Delay t 7 9 ZX1 (Slow slew rate = OFF; V = 5.0V; C = 35 pF) CCIO L ATF1508ASV(L) 12 1408H–PLD–7/05

ATF1508ASV(L) AC Characteristics(1) (Continued) -15 -20 Symbol Parameter Min Max Min Max Units Output Buffer Enable Delay t 7 9 ns ZX2 (Slow slew rate = OFF; V = 3.3V; C = 35 pF) CCIO L Output Buffer Enable Delay t 10 11 ns ZX3 (Slow slew rate = ON; V = 5.0V/3.3V; C = 35 pF) CCIO L Output Buffer Disable Delay t 6 7 ns XZ (C = 5 pF) L t Register Setup Time 5 6 ns SU t Register Hold Time 4 5 ns H t Register Setup Time of Fast Input 2 2 ns FSU t Register Hold Time of Fast Input 2 2 ns FH t Register Delay 2 2.5 ns RD t Combinatorial Delay 2 3 ns COMB t Array Clock Delay 6 7 ns IC t Register Enable Time 6 7 ns EN t Global Control Delay 2 3 ns GLOB t Register Preset Time 4 5 ns PRE t Register Clear Time 4 5 ns CLR t Switch Matrix Delay 2 2.5 ns UIM t Reduced-Power Adder(2) 10 13 ns RPA Notes: 1. See ordering information for valid part numbers. 2. The t parameter must be added to the t , t ,t , t , and t parameters for macrocells running in the reduced- RPA LAD LAC TIC ACL SEXP power mode. Input Test Waveforms and Measurement Levels t , t = 1.5 ns typical R F 13 1408H–PLD–7/05

Output AC Test Loads 3.0V 703 8060 Power-down Mode The ATF1508ASV(L) includes two pins for optional pin-controlled power-down feature. When this mode is enabled, the PD pin acts as the power-down pin. When the PD1 and PD2 pin is high, the device supply current is reduced to less than 5 mA. During power- down, all output data and internal logic states are latched and held. Therefore, all regis- tered and combinatorial output data remain valid. Any outputs that were in a high-Z state at the onset will remain at high-Z. During power-down, all input signals except the power-down pin are blocked. Input and I/O hold latches remain active to ensure that pins do not float to indeterminate levels, further reducing system power. The power- down pin feature is enabled in the logic design file. Designs using either power-down pin may not use the PD pin logic array input. However, buried logic resources in this macro- cell may still be used. Power Down AC Characteristics(1)(2) -15 -20 Symbol Parameter Min Max Min Max Units t Valid I, I/O before PD High 15 20 ns IVDH t Valid OE(2) before PD High 15 20 ns GVDH t Valid Clock(2) before PD High 15 20 ns CVDH t I, I/O Don’t Care after PD High 25 30 ns DHIX t OE(2) Don’t Care after PD High 25 30 ns DHGX t Clock(2) Don’t Care after PD High 25 30 ns DHCX t PD Low to Valid I, I/O 1 1 µs DLIV t PD Low to Valid OE (Pin or Term) 1 1 µs DLGV t PD Low to Valid Clock (Pin or Term) 1 1 µs DLCV t PD Low to Valid Output 1 1 µs DLOV Notes: 1. For slow slew outputs, add t . SSO 2. Pin or product term. ATF1508ASV(L) 14 1408H–PLD–7/05

ATF1508ASV(L) JTAG-BST Overview The JTAG-BST (JTAG boundary-scan testing) is controlled by the Test Access Port (TAP) controller in the ATF1508ASV(L). The boundary-scan technique involves the inclusion of a shift-register stage (contained in a boundary-scan cell) adjacent to each component so that signals at component boundaries can be controlled and observed using scan testing principles. Each input pin and I/O pin has its own Boundary-scan Cell (BSC) in order to support boundary-scan testing. The ATF1508ASV(L) does not cur- rently include a Test Reset (TRST) input pin because the TAP controller is automatically reset at power-up. The six JTAG-BST modes supported include: SAMPLE/PRELOAD, EXTEST, BYPASS and IDCODE. BST on the ATF1508ASV(L) is implemented using the Boundary-scan Definition Language (BSDL) described in the JTAG specification (IEEE Standard 1149.1). Any third-party tool that supports the BSDL format can be used to perform BST on the ATF1508ASV(L). The ATF1508ASV(L) also has the option of using four JTAG-standard I/O pins for in- system programming (ISP). The ATF1508ASV(L) is programmable through the four JTAG pins using programming-compatible with the IEEE JTAG Standard 1149.1. Pro- gramming is performed by using 5V TTL-level programming signals from the JTAG ISP interface. The JTAG feature is a programmable option. If JTAG (BST or ISP) is not needed, then the four JTAG control pins are available as I/O pins. JTAG Boundary-scan The ATF1508ASV(L) contains up to 96 I/O pins and four input pins, depending on the Cell (BSC) Testing device type and package type selected. Each input pin and I/O pin has its own bound- ary-scan cell (BSC) in order to support boundary-scan testing as described in detail by IEEE Standard 1149.1. A typical BSC consists of three capture registers or scan regis- ters and up to two update registers. There are two types of BSCs, one for input or I/O pin, and one for the macrocells. The BSCs in the device are chained together through the (BST) capture registers. Input to the capture register chain is fed in from the TDI pin while the output is directed to the TDO pin. Capture registers are used to capture active device data signals, to shift data in and out of the device and to load data into the update registers. Control signals are generated internally by the JTAG TAP controller. The BSC configuration for the input and I/O pins and macrocells are shown below. BSC Configuration Pins and Macrocells (Except JTAG TAP Pins) Note: The ATF1508ASV(L) has pull-up option on TMS and TDI pins. This feature is selected as a design option. 15 1408H–PLD–7/05

Boundary-scan These are now available in all package types via the Atmel web site. These models can Definition Language be used for Boundary-scan Test Operation in the ATF1508ASV(L) and have been scheduled to conform to the IEEE 1149.1 standard. (BSDL) Models for the ATF1508 BSC Configuration for Macrocell Pin BSC TDO 0 DQ Pin 1 Capture DR TDI Clock Shift TDO OEJ 0 1 0 D Q D Q 1 OUTJ 0 1 Pin 0 D Q D Q 1 Capture Update DR DR TDI Mode Shift Clock Macrocell BSC ATF1508ASV(L) 16 1408H–PLD–7/05

ATF1508ASV(L) ATF1508ASV(L) Dedicated Pinouts Dedicated Pin 84-lead J-lead 100-lead PQFP 100-lead TQFP 160-lead PQFP INPUT/OE2/GCLK2 2 92 90 142 INPUT/GCLR 1 91 89 141 INPUT/OE1 84 90 88 140 INPUT/GCLK1 83 89 87 139 I/O/GCLK3 81 87 85 137 I/O/PD (1, 2) 12,45 3,43 1,41 63,159 I/O/TDI(JTAG) 14 6 4 9 I/O/TMS(JTAG) 23 17 15 22 I/O/TCK(JTAG) 62 64 62 99 I/O/TDO(JTAG) 71 75 73 112 7,19,32,42, 13,28,40,45, 11,26,38,43, 17,42,60,66,95, GND 47,59,72,82 61,76,88,97 59,74,86,95 113,138,148 3,13,26,38, 5,20,36,41, 3,18,34,39, VCC 8,26,55,61,79,104,133,143 43,53,66,78 53,68,84,93 51,66,82,91 1,2,3,4,5,6,7,34,35,36, 37,38,39,40,44,45,46, 47,74,75,76,77,81,82, N/C - - - 83,84,85,86,87,114, 115,116,117,118,119, 120,124,125,126,127, 154,155,156,157 # of SIGNAL PINS 68 84 84 100 # USER I/O PINS 64 80 80 96 OE (1, 2) Global OE pins GCLR Global Clear pin GCLK (1, 2, 3) Global Clock pins PD (1, 2) Power-down pins TDI, TMS, TCK, TDO JTAG pins used for boundary-scan testing or in-system programming GND Ground pins VCC VCC pins for the device 17 1408H–PLD–7/05

ATF1508ASV(L) I/O Pinouts 84-lead 100-lead 100-lead 160-lead 84-lead 100-lead 100-lead 160-lead MC PLB J-lead PQFP TQFP PQFP MC PLB J-lead PQFP TQFP PQFP 1 A - 4 2 160 33 C - 27 25 41 2 A - - - - 34 C - - - - A/ 3 12 3 1 159 35 C 31 26 24 33 PD1 4 A - - - 158 36 C - - - 32 5 A 11 2 100 153 37 C 30 25 23 31 6 A 10 1 99 152 38 C 29 24 22 30 7 A - - - - 39 C - - - - 8 A 9 100 98 151 40 C 28 23 21 29 9 A - 99 97 150 41 C - 22 20 28 10 A - - - - 42 C - - - - 11 A 8 98 96 149 43 C 27 21 19 27 12 A - - - 147 44 C - - - 25 13 A 6 96 94 146 45 C 25 19 17 24 14 A 5 95 93 145 46 C 24 18 16 23 15 A - - - - 47 C - - - - C/ 16 A 4 94 92 144 48 23 17 15 22 TMS 17 B 22 16 14 21 49 D 41 39 37 59 18 B - - - - 50 D - - - - 19 B 21 15 13 20 51 D 40 38 36 58 20 B - - - 19 52 D - - - 57 21 B 20 14 12 18 53 D 39 37 35 56 22 B - 12 10 16 54 D - 35 33 54 23 B - - - - 55 D - - - - 24 B 18 11 9 15 56 D 37 34 32 53 25 B 17 10 8 14 57 D 36 33 31 52 26 B - - - - 58 D - - - - 27 B 16 9 7 13 59 D 35 32 30 51 28 B - - - 12 60 D - - - 50 29 B 15 8 6 11 61 D 34 31 29 49 30 B - 7 5 10 62 D - 30 28 48 31 B - - - - 63 D - - - - B/ 32 14 6 4 9 64 D 33 29 27 43 TDI 65 E 44 42 40 62 97 G 63 65 63 100 66 E - - - - 98 G - - - - ATF1508ASV(L) 18 1408H–PLD–7/05

ATF1508ASV(L) ATF1508ASV(L) I/O Pinouts (Continued) 84-lead 100-lead 100-lead 160-lead 84-lead 100-lead 100-lead 160-lead MC PLB J-lead PQFP TQFP PQFP MC PLB J-lead PQFP TQFP PQFP E/ 67 45 43 41 63 99 G 64 66 64 101 PD2 68 E - - - 64 100 G - - - 102 69 E 46 44 42 65 101 G 65 67 65 103 70 E - 46 44 67 102 G - 69 67 105 71 E - - - - 103 G - - - - 72 E 48 47 45 68 104 G 67 70 68 106 73 E 49 48 46 69 105 G 68 71 69 107 74 E - - - - 106 G - - - - 75 E 50 49 47 70 107 G 69 72 70 108 76 E - - - 71 108 G - - - 109 77 E 51 50 48 72 109 G 70 73 71 110 78 E - 51 49 73 110 G - 74 72 111 79 E - - - - 111 G - - - - G/ 80 E 52 52 50 78 112 71 75 73 112 TDO 81 F - 54 52 80 113 H - 77 75 121 82 F - - - - 114 H - - - - 83 F 54 55 53 88 115 H 73 78 76 122 84 F - - - 89 116 H - - - 123 85 F 55 56 54 90 117 H 74 79 77 128 86 F 56 57 55 91 118 H 75 80 78 129 87 F - - - - 119 H - - - - 88 F 57 58 56 92 120 H 76 81 79 130 89 F - 59 57 93 121 H - 82 80 131 90 F - - - - 122 H - - - - 91 F 58 60 58 94 123 H 77 83 81 132 92 F - - - 96 124 H - - - 134 93 F 60 62 60 97 125 H 79 85 83 135 94 F 61 63 61 98 126 H 80 86 84 136 95 F - - - - 127 H - - - - F/ H/ 96 62 64 62 99 128 81 87 85 137 TCK GCLK3 19 1408H–PLD–7/05

SUPPLY CURRENT VS. SUPPLY VOLTAGE SUPPLY CURRENT VS. SUPPLY VOLTAGE (TA = 25°C, F = 0) PIN-CONTROLLED POWER-DOWN MODE 200 (TA = 25°C, F = 0) 800 STANDARD POWER STANDARD & REDUCED POWER MODE 700 A) I (mCC 100 I (uA)CC600 REDUCED POWER 500 0 2.50 2.75 3.00 3.25 3.50 3.75 4.00 400 2.50 2.75 3.00 3.25 3.50 3.75 4.00 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) SUPPLY CURRENT VS. FREQUENCY STANDARD POWER (TA = 25°C) SUPPLY CURRENT VS. FREQUENCY LOW-POWER ("L") VERSION 250.0 (TA = 25°C) 125.0 200.0 STANDARD POWER STANDARD POWER 100.0 A) 150.0 I (mCC 100.0 REDUCED POWER MODE I (mA)CC 5705..00 REDUCED POWER 50.0 25.0 0.0 0.0 0.00 20.00 40.00 60.00 80.00 100.00 0.00 5.00 10.00 15.00 20.00 FREQUENCY (MHz) FREQUENCY (MHz) SUPPLY CURRENT VS. SUPPLY VOLTAGE LOW POWER ("L") MODE 10 (TA = 25°C, F = 0) 9 8 7 6 A) I (uCC 45 3 2 1 0 2.50 2.75 3.00 3.25 3.50 3.75 4.00 SUPPLY VOLTAGE (V) ATF1508ASV(L) 20 1408H–PLD–7/05

ATF1508ASV(L) OUTPUT SOURCE CURRENT VS. SUPPLY VOLTAGE (VOH = 2.4V, TA = 25°C) OUTPUT SOURCE CURRENT 0 VS. OUTPUT VOLTAGE (VCC = 3.3V,TA = 25°C) 10 -2 0 -4 -10 I (mA)OH -1--086 I (mA)OH ---432000 -12 -50 -60 -14 -70 -16 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 2.75 3.00 3.25 3.50 3.75 4.00 OUTPUT VOLTAGE (V) SUPPLY VOLTAGE (V) OUTPUT SINK CURRENT OUTPUT SINK CURRENT VS. SUPPLY VOLTAGE (VOL = 0.5V, TA = 25°C) VS. OUTPUT VOLTAGE (VCC = 3.3V, TA = 25°C) 100 40 80 35 A) mA) 60 I (mOL 30 I (OL 40 25 20 0 20 0 0.5 1 1.5 2 2.5 3 3.5 4 2.75 3.00 3.25 3.50 3.75 4.00 OUTPUT VOLTAGE (V) SUPPLY VOLTAGE (V) INPUT CURRENT vs. INPUT VOLTAGE INPUT CLAMP CURRENT VS. INPUT VOLTAGE (VCC = 3.3V, TA = 25°C) 15 (VCC = 3.3V, TA = 25°C) 0 NPUT CURRENT (mA) ----86420000 INPUT CURRENT (uA) 1-0505 I -100 -10 -1 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0 0.5 1 1.5 2 2.5 3 3.5 INPUT VOLTAGE (V) INPUT VOLTAGE (V) 21 1408H–PLD–7/05

Ordering Information ATF1508ASV(L) Standard Package Options t t f PD CO1 MAX (ns) (ns) (MHz) Ordering Code Package Operation Range ATF1508ASV-15 JC84 84J ATF1508ASV-15 QC100 100Q1 Commercial 8 100 ATF1508ASV-15 AC100 100A (0°C to 70°C) ATF1508ASV-15 QC160 160Q 15 ATF1508ASV-15 JI84 84J ATF1508ASV-15 QI100 100Q1 Industrial 8 100 ATF1508ASV-15 AI100 100A (-40°C to +85°C) ATF1508ASV-15 QI160 160Q ATF1508ASVL-20 JC84 84J ATF1508ASVL-20 QC100 100Q1 Commercial 12 83.3 ATF1508ASVL-20 AC100 100A (0°C to 70°C) ATF1508ASVL-20 QC160 160Q 20 ATF1508ASVL-20 JI84 84J ATF1508ASVL-20 QI100 100Q1 Industrial 12 83.3 ATF1508ASVL-20 AI100 100A (-40°C to +85°C) ATF1508ASVL-20 QI160 160Q Note: 1. The last time buy is Sept. 30, 2005 for shaded parts. Using “C” Product for Industrial There is very little risk in using “C” devices for industrial applications because the V conditions for 3.3V products are CC thesame for commercial and industrial (there is only 15°C difference at the high end of the temperature range). To use commercial product for industrial temperature ranges, de-rate I by 15%. CC ATF1508ASV(L) Green Package Options (Pb/Halide-free/RoHS Compliant) t t f PD CO1 MAX (ns) (ns) (MHz) Ordering Code Package Operation Range ATF1508ASV-15 JU84 84J Industrial 15 8 100 ATF1508ASV-15 AU100 100A (-40°C to +85°C) ATF1508ASVL-20 JU84 84J Industrial 20 12 83.3 ATF1508ASVL-20 AU100 100A (-40°C to +85°C) Package Type 84J 84-lead, Plastic J-leaded Chip Carrier (PLCC) 100Q1 100-lead, Plastic Quad Pin Flat Package (PQFP) 100A 100-lead, Very Thin Plastic Gull Wing Quad Flat Package (TQFP) 160Q 160-lead, Plastic Quad Pin Flat Package (PQFP) ATF1508ASV(L) 22 1408H–PLD–7/05

ATF1508ASV(L) Packaging Information 84J – PLCC 1.14(0.045) X 45˚ 1.14(0.045) X 45˚ PIN NO. 1 0.318(0.0125) IDENTIFIER 0.191(0.0075) E1 E B1 D2/E2 B e A2 D1 A1 D A 0.51(0.020)MAX 45˚ MAX (3X) COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A 4.191 – 4.572 A1 2.286 – 3.048 A2 0.508 – – D 30.099 – 30.353 D1 29.210 – 29.413 Note 2 E 30.099 – 30.353 Notes: 1.This package conforms to JEDEC reference MS-018, Variation AF. E1 29.210 – 29.413 Note 2 2.Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 D2/E2 27.686 – 28.702 and E1 include mold mismatch and are measured at the extreme B 0.660 – 0.813 material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. B1 0.330 – 0.533 e 1.270 TYP 10/04/01 TITLE DRAWING NO. REV. 2325 Orchard Parkway 84J, 84-lead, Plastic J-leaded Chip Carrier (PLCC) San Jose, CA 95131 84J B R 23 1408H–PLD–7/05

100Q1 – PQFP E PIN 1 ID PIN 1 e D1 B D E1 COMMON DIMENSIONS (Unit of Measure = mm) A JEDEC STANDARD MS-022, GC-1 0º~7º C SYMBOL MIN NOM MAX NOTE L A – 3.04 3.4 A1 A1 0.25 0.33 0.5 D 23.20 BSC E 17.20 BSC E1 14.00 BSC B 0.22 – 0.40 C 0.11 – 0.23 D1 20 BSC L 0.73 – 1.03 e 0.65 BSC 07/6/2005 TITLE DRAWING NO. REV. 2325 Orchard Parkway San Jose, CA 95131 100Q1, 100-lead, 14 x 20 mm Body, 3.2 mm Footprint, 0.65 mm Pitch, 100Q1 C R Plastic Quad Flat Package (PQFP) ATF1508ASV(L) 24 1408H–PLD–7/05

ATF1508ASV(L) 100A – TQFP PIN 1 B PIN 1 IDENTIFIER e E1 E D1 D C 0˚~7˚ A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 15.75 16.00 16.25 D1 13.90 14.00 14.10 Note 2 E 15.75 16.00 16.25 Notes: 1.This package conforms to JEDEC reference MS-026, Variation AED. E1 13.90 14.00 14.10 Note 2 2.Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum B 0.17 – 0.27 plastic body size dimensions including mold mismatch. C 0.09 – 0.20 3. Lead coplanarity is 0.08 mm maximum. L 0.45 – 0.75 e 0.50 TYP 10/5/2001 TITLE DRAWING NO. REV. 2325 Orchard Parkway 100A, 100-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness, San Jose, CA 95131 100A C R 0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) 25 1408H–PLD–7/05

160Q – PQFP Dimensions in Millimeters and (Inches). Controlling dimension: Millimeters. JEDEC Standard MS-022 DC-1 31.45(1.238) SQ 30.95(1.218) PIN 1 ID PIN 1 0.40(0.016) 0.22(0.009) 0.65(0.0256)BSC 28.10(1.106) SQ 27.90(1.098) 4.10(0.161)MAX 0.23(0.009) 0º~7º 0.11(0.004) 1.03(0.041) 0.50(0.020) 0.73(0.029) 0.25(0.010) 10/23/03 TITLE DRAWING NO. REV. 2325 Orchard Parkway 160Q, 160-lead, 28 x 28 mm Body, 3.2 mm Footprint, San Jose, CA 95131 160Q B R 0.65 mm Pitch, Plastic Quad Flat Package (PQFP) ATF1508ASV(L) 26 1408H–PLD–7/05

ATF1508ASV(L) Revision History Revision Comments 1408H Corrected list of last buy parts. 1408G Green package options added. 27 1408H–PLD–7/05

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Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: ATF1508ASV-15AC100 ATF1508ASV-15AI100 ATF1508ASV-15AU100 ATF1508ASV-15JU84 ATF1508ASVL- 20AC100 ATF1508ASVL-20AI100 ATF1508ASVL-20AU100 ATF1508ASVL-20JC84 ATF1508ASVL-20JI84 ATF1508ASVL-20JU84 ATF1508ASVL-20QC100 ATF1508ASVL-20QC160 ATF1508ASVL-20QI100 ATF1508ASVL- 20QI160 ATF1508ASV-15QI160 ATF1508ASV-15JI84 ATF1508ASV-15JC84 ATF1508ASV-15QC160 ATF1508ASV- 15QI100 ATF1508ASV-15AU100-T