Features • High-density, High-performance, Electrically-erasable Complex Programmable Logic Device – 3.0 to 3.6V Operating Range – 64 Macrocells – 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell – 44, 68, 84, 100 Pins – 15 ns Maximum Pin-to-pin Delay – Registered Operation up to 77 MHz – Enhanced Routing Resources (cid:127) In-System Programmability (ISP) via JTAG Low-voltage, (cid:127) Flexible Logic Macrocell – D/T/Latch Configurable Flip-flops Complex – Global and Individual Register Control Signals – Global and Individual Output Enable Programmable – Programmable Output Slew Rate – Programmable Output Open-collector Option Logic Device – Maximum Logic Utilization by Burying a Register with a COM Output (cid:127) Advanced Power Management Features – Automatic 5 µA Standby for “L” Version – Pin-controlled 100 µA Standby Mode (Typical) ATF1504ASV – Programmable Pin-keeper Circuits on Inputs and I/Os – Reduced-power Feature per Macrocell ATF1504ASVL (cid:127) Available in Commercial and Industrial Temperature Ranges (cid:127) Available in 44-, 68-, and 84-lead PLCC; 44- and 100-lead TQFP; and 100-lead PQFP (cid:127) Advanced EE Technology – 100% Tested – Completely Reprogrammable – 10,000 Program/Erase Cycles – 20 Year Data Retention – 2000V ESD Protection – 200 mA Latch-up Immunity (cid:127) JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported (cid:127) PCI-compliant (cid:127) Security Fuse Feature (cid:127) Green (Pb/Halide-free/RoHS Compliant) Package Options Enhanced Features (cid:127) Improved Connectivity (Additional Feedback Routing, Alternate Input Routing) (cid:127) Output Enable Product Terms (cid:127) Transparent-latch Mode (cid:127) Combinatorial Output with Registered Feedback within Any Macrocell (cid:127) Three Global Clock Pins (cid:127) ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O (cid:127) Fast Registered Input from Product Term (cid:127) Programmable “Pin-keeper” Option (cid:127) V Power-up Reset Option CC (cid:127) Pull-up Option on JTAG Pins TMS and TDI (cid:127) Advanced Power Management Features – Edge-controlled Power-down “L” – Individual Macrocell Power Option – Disable ITD on Global Clocks, Inputs and I/O Rev. 1409J–PLD–6/05 1

44-lead TQFP 44-lead PLCC Top View Top View I/OI/OI/OVCCGCLK2/OE2/IGCLR/II/OE1GCLK1/IGNDGCLK3/I/OI/O I/OI/OI/OVCCGCLK2/OE2/IGCLR/IOE1/IGCLK1/IGNDGCLK3/I/OI/O 4443424140393837363534 TDI/I/O 7654321444342414039 I/O I/O/TDI 1 33 I/O I/O 8 38 I/O/TDO I/O 2 32 I/O/TDO I/O 9 37 I/O I/O 3 31 I/O GND 10 36 I/O GND 4 30 I/O PD1/I/O 11 35 VCC PD1/I/O 5 29 VCC I/O 12 34 I/O I/O 6 28 I/O I/O/TMS 13 33 I/O TMS/I/O 7 27 I/O I/O 14 32 I/O/TCK I/O 8 26 I/O/TCK VCC 15 31 I/O VCC 9 25 I/O I/O 16 30 GND I/O 10 24 GND I/O 17 29 I/O 89012345678 I/O 11 23 I/O 11222222222 1213141516171819202122 I/OI/OI/OI/OGNDVCCI/O2/I/OI/OI/OI/O D OOOODCOOOOO P I/I/I/I/GNVCI/2/I/I/I/I/ D P 68-lead PLCC 84-lead PLCC Top View Top View I/OI/OI/OGNDI/OI/OVCCINTGCLK2/OE2/IGCLR/IOE1/IGCLK1/IGNDGCLK3/I/OI/OVCCIOI/OI/O I/OI/OI/OI/OGNDI/OI/OI/OVCCINTGCLK2/OE2/II/GCLRI/OE1GCLK1/IGNDGCLK3/I/OI/OI/OVCCIO1/OI/OI/O I/O 10987654321686766656463626160 I/O I/O 1211109876543218483828180797877767574 I/O VCCIO 11 59 I/O VCCIO 13 73 I/O I/O/TD1 12 58 GND I/O/TDI 14 72 GND I/O 13 57 I/O/TDO I/O 15 71 I/O/TDO I/O 14 56 I/O I/O 16 70 I/O I/O 15 55 I/O I/O 17 69 I/O GND 16 54 I/O I/O 18 68 I/O I/O/PD1 17 53 VCCIO GND 19 67 I/O I/O 18 52 I/O I/O/PD1 20 66 VCCIO I/O/TMS 19 51 I/O I/O 21 65 I/O I/O 20 50 I/O/TCK I/O 22 64 I/O VCCIO 21 49 I/O I/O/TMS 23 63 I/O I/O 22 48 GND I/O 24 62 I/O/TCK I/O 23 47 I/O I/O 25 61 I/O I/O 24 46 I/O VCCIO 26 60 I/O I/O 25 45 I/O I/O 27 59 GND GND 26 44 I/O I/O 28 58 I/O 78901234567890123 22233333333334444 I/O 29 57 I/O OOOOOOODTO2DOOOOO I/O 30 56 I/O I/I/I/I/VCCII/I/GNVCCINI/I/O/PDGNI/I/I/I/VCCI GNI/OD 33123456789012345678901235554 II//OO 333333344444444445555 OOOOOOOOODTOO2DOOOOOO I/I/I/I/I/VCCII/I/I/GNVCCINI/I/I/O/PDGNI/I/I/I/I/VCCI ATF1504ASV(L) 2 1409J–PLD–6/05

ATF1504ASV(L) 100-lead PQFP 100-lead TQFP Top View Top View I/OI/OI/OGNDI/OI/OI/OVCCINTINPUT/OE2/GCLK2INPUT/GCLRINPUT/OE1INPUT/GCLK1GNDI/O/GCLK3I/OI/OVCCIOI/OI/OI/O I/OI/OI/OI/OI/OGNDI/OI/OI/OVCCINTINPUT/OE2/GCLK2INPUT/GCLRINPUT/OE1INPUT/GCLK1GNDI/O/GCLK3I/OI/OVCCIOI/OI/OI/ONCNCI/O 10099989796959493929190898887868584838281 100999897969594939291908988878685848382818079787776 NC 1 75 I/O NC 1 80 NC NC 2 74 GND NC 2 79 NC VCCIO 3 73 I/O/TDO I/O 3 78 I/O I/O/TDI 4 72 NC I/O 4 77 I/O NC 5 71 I/O VCCIO 5 76 GND I/O 6 70 NC I/O/TDI 6 75 I/O/TDO NC 7 69 I/O NC 7 74 NC I/O 8 68 I/O I/O 8 73 I/O I/O 9 67 I/O NC 9 72 NC I/O 10 66 VCCIO I/O 10 71 I/O GND 11 65 I/O I/O 11 70 I/O I/O/PD1 12 64 I/O I/O 12 69 I/O I/O 13 63 I/O GND 13 68 VCCIO I/O 14 62 I/O/TCK I/O/PD1 14 67 I/O I/O/TMS 15 61 I/O I/O 15 66 I/O I/O 16 60 I/O I/O 16 65 I/O I/O 17 59 GND I/O/TMS 17 64 I/O/TCK VCCIO 18 58 I/O I/O 18 63 I/O I/O 19 57 I/O I/O 19 62 I/O I/O 20 56 I/O VCCIO 20 61 GND I/O 21 55 NC I/O 21 60 I/O NC 22 54 I/O I/O 22 59 I/O I/O 23 53 NC I/O 23 58 I/O NC 24 52 I/O NC 24 57 NC I/O 25 51 VCCIO I/O 25 56 I/O NC 26 55 NC 26272829303132333435363738394041424344454647484950 I/O 27 54 I/O GNNNCCD 223890 555321 VNNCCCCIO GNDNCNCI/OI/OI/OI/OI/OVCCIOI/OI/OI/OGNDVCCINTI/OI/OI/O/PD2GNDI/OI/OI/OI/OI/ONCNC 3132333435363738394041424344454647484950 I/OI/OI/OI/OI/OVCCIOI/OI/OI/OGNDVCCINTI/OI/OI/O/PD2GNDI/OI/OI/OI/OI/O 3 1409J–PLD–6/05

Description The ATF1504ASV(L) is a high-performance, high-density complex programmable logic device (CPLD) that utilizes Atmel’s proven electrically-erasable memory technology. With 64 logic macrocells and up to 68 inputs, it easily integrates logic from several TTL, SSI, MSI, LSI and classic PLDs. The ATF1504ASV(L)’s enhanced routing switch matri- ces increase usable gate count and the odds of successful pin-locked design modifications. The ATF1504ASV(L) has up to 68 bi-directional I/O pins and four dedicated input pins, depending on the type of device package selected. Each dedicated pin can also serve as a global control signal, register clock, register reset or output enable. Each of these control signals can be selected for use individually within each macrocell. Each of the 64 macrocells generates a buried feedback that goes to the global bus. Each input and I/O pin also feeds into the global bus. The switch matrix in each logic block then selects 40 individual signals from the global bus. Each macrocell also gener- ates a foldback logic term that goes to a regional bus. Cascade logic between macrocells in the ATF1504ASV(L) allows fast, efficient generation of complex logic func- tions. The ATF1504ASV(L) contains four such logic chains, each capable of creating sum term logic with a fan-in of up to 40 product terms. The ATF1504ASV(L) macrocell, shown in Figure 1, is flexible enough to support highly- complex logic functions operating at high speed. The macrocell consists of five sections: product terms and product term select multiplexer, OR/XOR/CASCADE logic, a flip-flop, output select and enable, and logic array inputs. ATF1504ASV(L) 4 1409J–PLD–6/05

ATF1504ASV(L) Block Diagram Unused product terms are automatically disabled by the compiler to decrease power consumption. A security fuse, when programmed, protects the contents of the ATF1504ASV(L). Two bytes (16 bits) of User Signature are accessible to the user for purposes such as storing project name, part number, revision or date. The User Signa- ture is accessible regardless of the state of the security fuse. The ATF1504ASV(L) device is an in-system programmable (ISP) device. It uses the industry-standard 4-pin JTAG interface (IEEE Std. 1149.1), and is fully-compliant with JTAG’s Boundary-scan Description Language (BSDL). ISP allows the device to be pro- grammed without removing it from the printed circuit board. In addition to simplifying the manufacturing flow, ISP also allows design modifications to be made in the field via software. Product Terms and Select Each ATF1504ASV(L) macrocell has five product terms. Each product term receives as Mux its inputs all signals from both the global bus and regional bus. The product term select multiplexer (PTMUX) allocates the five product terms as needed to the macrocell logic gates and control signals. The PTMUX programming is determined by the design compiler, which selects the optimum macrocell configuration. 5 1409J–PLD–6/05

OR/XOR/CASCADE Logic The ATF1504ASV(L)’s logic structure is designed to efficiently support all types of logic. Within a single macrocell, all the product terms can be routed to the OR gate, creating a 5-input AND/OR sum term. With the addition of the CASIN from neighboring macrocells, this can be expanded to as many as 40 product terms with little additional delay. The macrocell’s XOR gate allows efficient implementation of compare and arithmetic functions. One input to the XOR comes from the OR sum term. The other XOR input can be a product term or a fixed high- or low-level. For combinatorial outputs, the fixed level input allows polarity selection. For registered functions, the fixed levels allow DeMorgan minimization of product terms. The XOR gate is also used to emulate T- and JK-type flip-flops. Flip-flop The ATF1504ASV(L)’s flip-flop has very flexible data and control functions. The data input can come from either the XOR gate, from a separate product term or directly from the I/O pin. Selecting the separate product term allows creation of a buried registered feedback within a combinatorial output macrocell. (This feature is automatically imple- mented by the fitter software). In addition to D, T, JK and SR operation, the flip-flop can also be configured as a flow-through latch. In this mode, data passes through when the clock is high and is latched when the clock is low. The clock itself can either be one of the Global CLK Signal (GCK[0:2]) or an individual product term. The flip-flop changes state on the clock’s rising edge. When the GCK sig- nal is used as the clock, one of the macrocell product terms can be selected as a clock enable. When the clock enable function is active and the enable signal (product term) is low, all clock edges are ignored. The flip-flop’s asynchronous reset signal (AR) can be either the Global Clear (GCLEAR), a product term, or always off. AR can also be a logic OR of GCLEAR with a product term. The asynchronous preset (AP) can be a product term or always off. Extra Feedback The ATF1504ASV(L) macrocell output can be selected as registered or combinatorial. The extra buried feedback signal can be either combinatorial or a registered signal regardless of whether the output is combinatorial or registered. (This enhancement function is automatically implemented by the fitter software.) Feedback of a buried com- binatorial output allows the creation of a second latch within a macrocell. I/O Control The output enable multiplexer (MOE) controls the output enable signal. Each I/O can be individually configured as an input, output or for bi-directional operation. The output enable for each macrocell can be selected from the true or compliment of the two output enable pins, a subset of the I/O pins, or a subset of the I/O macrocells. This selection is automatically done by the fitter software when the I/O is configured as an input, all mac- rocell resources are still available, including the buried feedback, expander and cascade logic. Global Bus/Switch Matrix The global bus contains all input and I/O pin signals as well as the buried feedback sig- nal from all 64 macrocells. The switch matrix in each logic block receives as its inputs all signals from the global bus. Under software control, up to 40 of these signals can be selected as inputs to the logic block. Foldback Bus Each macrocell also generates a foldback product term. This signal goes to the regional bus and is available to four macrocells. The foldback is an inverse polarity of one of the macrocell’s product terms. The four foldback terms in each region allow generation of high fan-in sum terms (up to nine product terms) with little additional delay. ATF1504ASV(L) 6 1409J–PLD–6/05

ATF1504ASV(L) Figure 1. ATF1504ASV(L) Macrocell Programmable Pin-keeper Option for Inputs and I/Os The ATF1504ASV(L) offers the option of programming all input and I/O pins so that pin keeper circuits can be utilized. When any pin is driven high or low and then subsequently left floating, it will stay at that previous high- or low-level. This cir- cuitry prevents unused input and I/O lines from floating to intermediate voltage levels, which causes unnecessary power consumption and system noise. The keeper circuits eliminate the need for external pull-up resistors and eliminate their DC power consumption. 7 1409J–PLD–6/05

Input Diagram I/O Diagram Speed/Power The ATF1504ASV(L) has several built-in speed and power management features. The Management ATF1504ASV(L) contains circuitry that automatically puts the device into a low power standby mode when no logic transitions are occurring. This not only reduces power con- sumption during inactive periods, but also provides proportional power savings for most applications running at system speeds below 5 MHz. This feature may be selected as a device option. To further reduce power, each ATF1504ASV(L) macrocell has a reduced-power bit fea- ture. This feature allows individual macrocells to be configured for maximum power savings. This feature may be selected as a design option. All ATF1504ASV(L) also have an optional power-down mode. In this mode, current drops to below 5 mA. When the power-down option is selected, either PD1 or PD2 pins (or both) can be used to power down the part. The power-down option is selected in the design source file. When enabled, the device goes into power down when either PD1 or PD2 is high. In the power-down mode, all internal logic signals are latched and held, as are any enabled outputs. All pin transitions are ignored until the PD pin is brought low. When the power-down fea- ture is enabled, the PD1 or PD2 pin cannot be used as a logic input or output. However, the pin’s macrocell may still be used to generate buried foldback and cascade logic signals. ATF1504ASV(L) 8 1409J–PLD–6/05

ATF1504ASV(L) All power-down AC characteristic parameters are computed from external input or I/O pins, with reduced-power bit turned on. For macrocells in reduced-power mode (reduced-power bit turned on), the reduced-power adder, t , must be added to the AC RPA parameters, which include the data paths t , t , t , t , t and t . LAD LAC IC ACL ACH SEXP The ATF1504ASV(L) macrocell also has an option whereby the power can be reduced on a per macrocell basis. By enabling this power-down option, macrocells that are not used in an application can be turned down, thereby reducing the overall power con- sumption of the device. Each output also has individual slew rate control. This may be used to reduce system noise by slowing down outputs that do not need to operate at maximum speed. Outputs default to slow switching, and may be specified as fast switching in the design file. Design Software ATF1504ASV(L) designs are supported by several industry standard third party tools. Support Automated fitters allow logic synthesis using a variety of high-level description lan- guages and formats. Power-up Reset The ATF1504ASV is designed with a power-up reset, a feature critical for state machine initialization. At a point delayed slightly from V crossing V , all registers will be ini- CC RST tialized, and the state of each output will depend on the polarity of its buffer. However, due to the asynchronous nature of reset and uncertainty of how V actually rises in the CC system, the following conditions are required: 1. The V rise must be monotonic, CC 2. After reset occurs, all input and feedback setup times must be met before driving the clock pin high, and, 3. The clock must remain stable during T . D The ATF1504ASV has two options for the hysteresis about the reset level, V , Small RST and Large. To ensure a robust operating environment in applications where the device is operated near 3.0V, Atmel recommends that during the fitting process users configure the device with the Power-up Reset hysteresis set to Large. For conversions, Atmel POF2JED users should include the flag “-power_reset” on the command line after “file- name.POF”. To allow the registers to be properly reinitialized with the Large hysteresis option selected, the following condition is added: 4. If V falls below 2.0V, it must shut off completely before the device is turned on CC again. When the Large hysteresis option is active, I is reduced by several hundred micro- CC amps as well. Security Fuse Usage A single fuse is provided to prevent unauthorized copying of the ATF1504ASV(L) fuse patterns. Once programmed, fuse verify is inhibited. However, the 16-bit User Signature remains accessible. 9 1409J–PLD–6/05

Programming ATF1504ASV(L) devices are in-system programmable (ISP) devices utilizing the 4-pin JTAG protocol. This capability eliminates package handling normally required for pro- gramming and facilitates rapid design iterations and field changes. Atmel provides ISP hardware and software to allow programming of the ATF1504ASV(L) via the PC. ISP is performed by using either a download cable, a com- parable board tester or a simple microprocessor interface. To facilitate ISP programming by the Automated Test Equipment (ATE) vendors. Serial Vector Format (SVF) files can be created by Atmel provided software utilities. ATF1504ASV(L) devices can also be programmed using standard third-party program- mers. With third-party programmer the JTAG ISP port can be disabled thereby allowing fouradditional I/O pins to be used for logic. Contact your local Atmel representatives or Atmel PLD applications for details. ISP Programming The ATF1504ASV(L) has a special feature that locks the device and prevents the inputs Protection and I/O from driving if the programming process is interrupted for any reason. The inputs and I/O default to high-Z state during such a condition. In addition the pin keeper option preserves the former state during device programming, if this circuit were previ- ously programmed on the device. This prevents disturbing the operation of other circuits in the system while the ATF1504ASV(L) is being programmed via ISP. All ATF1504ASV(L) devices are initially shipped in the erased state thereby making them ready to use for ISP. Note: For more information refer to the “Designing for In-SystemProgrammability with Atmel CPLDs” application note. ATF1504ASV(L) 10 1409J–PLD–6/05

ATF1504ASV(L) DC and AC Operating Conditions Commercial Industrial Operating Temperature (Ambient)) 0°C - 70°C -40°C - 85°C V (3.3V) Power Supply 3.0V - 3.6V 3.0V - 3.6V CC DC Characteristics Symbol Parameter Condition Min Typ Max Units Input or I/O Low I V = V -2 -10 µA IL Leakage Current IN CC Input or I/O High I 2 10 IH Leakage Current Tri-State Output I V = V or GND -40 40 µA OZ Off-State Current O CC Com. 60 mA Std Mode Power Supply Current, V = Max Ind. 75 mA I CC CC1 Standby VIN = 0, VCC Com. 5 µA “L” Mode Ind. 5 µA Power Supply Current, V = Max I CC “PD” Mode 0.1 5 mA CC2 Power-down Mode V = 0, V IN CC Reduced-power Mode V = Max Com 40 ma I (2) CC Std Power CC3 Supply Current, Standby VIN = 0, VCC Ind 55 V Input Low Voltage -0.3 0.8 V IL V Input High Voltage 1.7 V + 0.3 V IH CCIO V = V or V Com. 0.45 V Output Low Voltage (TTL) IN IH IL VCCIO = Min, IOL = 8 mA Ind. 0.45 V OL V = V or V Com. 0.2 V Output Low Voltage (CMOS) IN IH IL VCC = Min, IOL = 0.1 mA Ind. 0.2 V Output High Voltage V = V or V IN IH IL 2.4 V - 3.3V (TTL) V = Min, I = -2.0 mA CCIO OH V OH Output High Voltage V = V or V IN IH IL V - 0.2 V - 3.3V (CMOS) V = Min, I = -0.1 mA CCIO CCIO OH Notes: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec. 2. When microcell reduced-power feature is enabled. Pin Capacitance Typ Max Units Conditions C 8 pF V = 0V; f = 1.0 MHz IN IN C 8 pF V = 0V; f = 1.0 MHz I/O OUT Note: Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. The OGI pin (high-voltage pin during programming) has a maximum capacitance of 12 pF. 11 1409J–PLD–6/05

Absolute Maximum Ratings* Temperature Under Bias..................................-40°C to +85°C *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam- Storage Temperature.....................................-65°C to +150°C age to the device. This is a stress rating only and functional operation of the device at these or any Voltage on Any Pin with other conditions beyond those indicated in the Respect to Ground.........................................-2.0V to +7.0V(1) operational sections of this specification is not implied. Exposure to absolute maximum rating Voltage on Input Pins conditions for extended periods may affect with Respect to Ground device reliability. During Programming.....................................-2.0V to +14.0V(1) Note: 1. Minimum voltage is -0.6V DC, which may under- shoot to -2.0V for pulses of less than 20 ns. Max- Programming Voltage with imum output pin voltage is V + 0.75V DC, CC Respect to Ground.......................................-2.0V to +14.0V(1) which may overshoot to 7.0V for pulses of less than 20 ns. Timing Model Internal Output Enable Delay t IOE Global Control Delay Input t GLOB Delay Cascade Logic Register tIN Delay Delay Output Switch LogDice lAayrray tPEXP tStU Delay H t Matrix tLAD tPRE tOD1 tUIM tCLR tOD2 Register Control t OD3 RD t Delay t XZ COMB t t t ZX1 LAC FSU t tIC Fast Input tFH tZX2 tEN Delay ZX3 t FIN Foldback Term Delay t I/O SEXP Delay t IO ATF1504ASV(L) 12 1409J–PLD–6/05

ATF1504ASV(L) AC Characteristics -15 -20 Symbol Parameter Min Max Min Max Units t Input or Feedback to Non-Registered Output 3 15 20 ns PD1 t I/O Input or Feedback to Non-Registered Feedback 3 12 16 ns PD2 t Global Clock Setup Time 11 13.5 ns SU t Global Clock Hold Time 0 0 ns H t Global Clock Setup Time of Fast Input 3 3 ns FSU t Global Clock Hold Time of Fast Input 1.0 2 MHz FH t Global Clock to Output Delay 9 12 ns COP t Global Clock High Time 5 6 ns CH t Global Clock Low Time 5 6 ns CL t Array Clock Setup Time 5 7 ns ASU t Array Clock Hold Time 4 4 ns AH t Array Clock Output Delay 15 18.5 ns ACOP t Array Clock High Time 6 8 ns ACH t Array Clock Low Time 6 8 ns ACL t Minimum Clock Global Period 13 17 ns CNT f Maximum Internal Global Clock Frequency 76.9 66 MHz CNT t Minimum Array Clock Period 13 17 ns ACNT f Maximum Internal Array Clock Frequency 76.9 58.8 MHz ACNT f Maximum Clock Frequency 100 83.3 MHz MAX t Input Pad and Buffer Delay 2 2.5 ns IN t I/O Input Pad and Buffer Delay 2 2.5 ns IO t Fast Input Delay 2 2 ns FIN t Foldback Term Delay 8 10 ns SEXP t Cascade Logic Delay 1 1 ns PEXP t Logic Array Delay 6 8 ns LAD t Logic Control Delay 3.5 4.5 ns LAC t Internal Output Enable Delay 3 3 ns IOE Output Buffer and Pad Delay t 3 4 ns OD1 (Slow slew rate = OFF; V = 5V; C = 35 pF) CCIO L Output Buffer and Pad Delay t 3 4 ns OD2 (Slow slew rate = OFF; V = 3.3V; C = 35 pF) CCIO L Output Buffer and Pad Delay t 5 6 ns OD3 (Slow slew rate = ON; V = 5V or 3.3V; C = 35 pF) CCIO L Output Buffer Enable Delay t 7 9 ns ZX1 (Slow slew rate = OFF; V = 5.0V; C = 35 pF) CCIO L 13 1409J–PLD–6/05

AC Characteristics (Continued) -15 -20 Symbol Parameter Min Max Min Max Units Output Buffer Enable Delay t 7 9 ns ZX2 (Slow slew rate = OFF; V = 3.3V; C = 35 pF) CCIO L Output Buffer Enable Delay t 10 11 ns ZX3 (Slow slew rate = ON; V = 5.0V/3.3V; C = 35 pF) CCIO L t Output Buffer Disable Delay (C = 5 pF) 6 7 ns XZ L t Register Setup Time 5 6 ns SU t Register Hold Time 4 5 ns H t Register Setup Time of Fast Input 2 2 ns FSU t Register Hold Time of Fast Input 2 2 ns FH t Register Delay 2 2.5 ns RD t Combinatorial Delay 2 3 ns COMB t Array Clock Delay 6 7 ns IC t Register Enable Time 6 7 ns EN t Global Control Delay 2 3 ns GLOB t Register Preset Time 4 5 ns PRE t Register Clear Time 4 5 ns CLR t Switch Matrix Delay 2 2.5 ns UIM t Reduced-power Adder(2) 10 13 ns RPA Notes: 1. See ordering information for valid part numbers. 2. The t parameter must be added to the t , t ,t , t , and t parameters for macrocells running in the reduced- RPA LAD LAC TIC ACL SEXP power mode. 3. See ordering information for valid part numbers. Input Test Waveforms and Measurement Levels t , t = 1.5 ns typical R F Output AC Test Loads 3.0V R1 = 703Ω OUTPUT PIN R2 = 8060Ω CL = 35 pF ATF1504ASV(L) 14 1409J–PLD–6/05

ATF1504ASV(L) Power-down Mode The ATF1504ASV(L) includes an optional pin-controlled power-down feature. When this mode is enabled, the PD pin acts as the power-down pin. When the PD pin is high, the device supply current is reduced to less than 3 mA. During power down, all output data and internal logic states are latched internally and held. Therefore, all registered and combinatorial output data remain valid. Any outputs that were in a High-Z state at the onset will remain at High-Z. During power down, all input signals except the power-down pin are blocked. Input and I/O hold latches remain active to ensure that pins do not float to indeterminate levels, further reducing system power. The power-down mode feature is enabled in the logic design file or as a fitted or translated s/w option. Designs using the power-down pin may not use the PD pin as a logic array input. However, all other PD pin macrocell resources may still be used, including the buried feedback and foldback product term array inputs. Power Down AC Characteristics(1)(2) -15 -20 Symbol Parameter Min Max Min Max Units t Valid I, I/O before PD High 15 20 ns IVDH t Valid OE(2) before PD High 15 20 ns GVDH t Valid Clock(2) before PD High 15 20 ns CVDH t I, I/O Don’t Care after PD High 25 30 ns DHIX t OE(2) Don’t Care after PD High 25 30 ns DHGX t Clock(2) Don’t Care after PD High 25 30 ns DHCX t PD Low to Valid I, I/O 1 1 µs DLIV t PD Low to Valid OE (Pin or Term) 1 1 µs DLGV t PD Low to Valid Clock (Pin or Term) 1 1 µs DLCV t PD Low to Valid Output 1 1 µs DLOV Notes: 1. For slow slew outputs, add t . SSO 2. Pin or product term. 3. Includes t for reduced-power bit enabled. RPA 15 1409J–PLD–6/05

JTAG-BST/ISP The JTAG boundary-scan testing is controlled by the Test Access Port (TAP) controller Overview in the ATF1504ASV(L). The boundary-scan technique involves the inclusion of a shift- register stage (contained in a boundary-scan cell) adjacent to each component so that signals at component boundaries can be controlled and observed using scan testing principles. Each input pin and I/O pin has its own boundary-scan cell (BSC) in order to support boundary-scan testing. The ATF1504ASV(L) does not currently include a Test Reset (TRST) input pin because the TAP controller is automatically reset at power-up. The five JTAG modes supported include: SAMPLE/PRELOAD, EXTEST, BYPASS, IDCODE and HIGHZ. The ATF1504ASV(L)’s ISP can be fully described using JTAG’s BSDL as described in IEEE Standard 1149.1b. This allows ATF1504ASV(L) program- ming to be described and implemented using any one of the third-party development tools supporting this standard. The ATF1504ASV(L) has the option of using four JTAG-standard I/O pins for boundary- scan testing (BST) and in-system programming (ISP) purposes. The ATF1504ASV(L) is programmable through the four JTAG pins using the IEEE standard JTAG programming protocol established by IEEE Standard 1149.1 using 5V TTL-level programming signals from the ISP interface for in-system programming. The JTAG feature is a programmable option. If JTAG (BST or ISP) is not needed, then the four JTAG control pins are avail- able as I/O pins. JTAG Boundary-scan The ATF1504ASV(L) contains up to 68 I/O pins and four input pins, depending on the Cell (BSC) Testing device type and package type selected. Each input pin and I/O pin has its own bound- ary-scan cell (BSC) in order to support boundary-scan testing as described in detail by IEEE Standard 1149.1. A typical BSC consists of three capture registers or scan regis- ters and up to two update registers. There are two types of BSCs, one for input or I/O pin, and one for the macrocells. The BSCs in the device are chained together through the capture registers. Input to the capture register chain is fed in from the TDI pin while the output is directed to the TDO pin. Capture registers are used to capture active device data signals, to shift data in and out of the device and to load data into the update registers. Control signals are generated internally by the JTAG TAP controller. The BSC configuration for the input and I/O pins and macrocells are shown below. BSC Configuration for Input and I/O Pins (Except JTAG TAP Pins) Note: The ATF1504ASV(L) has pull-up option on TMS and TDI pins. This feature is selected as a design option. ATF1504ASV(L) 16 1409J–PLD–6/05

ATF1504ASV(L) BSC Configuration for Macrocell Pin BSC TDO 0 DQ Pin 1 Capture DR TDI Clock Shift TDO OEJ 0 1 0 D Q D Q 1 OUTJ 0 1 Pin 0 D Q D Q 1 Capture Update DR DR TDI Mode Shift Clock Macrocell BSC 17 1409J–PLD–6/05

ATF1504ASV Dedicated Pinouts 44-lead 44-lead 68-lead 84-lead 100-lead 100-lead Dedicated Pin TQFP J-lead J-lead J-lead PQFP TQFP INPUT/OE2/GCLK2 40 2 2 2 92 90 INPUT/GCLR 39 1 1 1 91 89 INPUT/OE1 38 44 68 84 90 88 INPUT/GCLK1 37 43 67 83 89 87 I/O /GCLK3 35 41 65 81 87 85 I/O / PD (1,2) 5, 19 11, 25 17, 37 20, 46 14, 44 12, 42 I/O / TDI (JTAG) 1 7 12 14 6 4 I/O / TMS (JTAG) 7 13 19 23 17 15 I/O / TCK (JTAG) 26 32 50 62 64 62 I/O / TDO (JTAG) 32 38 57 71 75 73 6, 16, 26, 34, 7, 19, 32, 42, 13, 28, 40, 45, 11, 26, 38, 43, GND 4, 16, 24, 36 10, 22, 30, 42 38, 48, 58, 66 47, 59, 72, 82 61, 76, 88, 97 59, 74, 86, 95 3, 11, 21, 31, 3,13, 26, 38, 5, 20, 36, 41, 3, 18, 34, 39, V 9, 17, 29, 41 3, 15, 23, 35 CC 35, 43, 53, 63 43, 53, 66, 78 53, 68, 84, 93 51, 66, 82, 91 1, 2, 7, 9, 1, 2, 5, 7, 22, 24, 26, 29, 30, 24, 27, 28, 49, N/C – – – – 51, 52, 55, 57, 50, 53, 55, 70, 72, 74, 79, 80 72, 77, 78 # of Signal Pins 36 36 52 68 68 68 # User I/O Pins 32 32 48 64 64 64 OE (1, 2) Global OE pins GCLR Global Clear pin GCLK (1, 2, 3) Global Clock pins PD (1, 2) Power-down pins TDI, TMS, TCK, TDO JTAG pins used for boundary-scan testing or in-system programming GND Ground pins VCC VCC pins for the device ATF1504ASV(L) 18 1409J–PLD–6/05

ATF1504ASV(L) ATF1504ASV I/O Pinouts 100- 100- 100- 100- 44-lead 44-lead 68-lead 84-lead lead lead 44-lead 44-lead 68-lead 84-lead lead lead MC PLC PLCC TQFP PLCC PLCC PQFP TQFP MC PLC PLCC TQFP PLCC PLCC PQFP TQFP 1 A 12 6 18 22 16 14 33 C 24 18 36 44 42 40 2 A - - - 21 15 13 34 C - - - 45 43 41 A/ C/ 3 11 5 17 20 14 12 35 25 19 37 46 44 42 PD1 PD2 4 A 9 3 15 18 12 10 36 C 26 20 39 48 46 44 5 A 8 2 14 17 11 9 37 C 27 21 40 49 47 45 6 A - - 13 16 10 8 38 C - - 41 50 48 46 7 A - - - 15 8 6 39 C - - - 51 49 47 8/ A 7 1 12 14 6 4 40 C 28 22 42 52 50 48 TDI 9 A - - 10 12 4 100 41 C 29 23 44 54 54 52 10 A - - - 11 3 99 42 C - - - 55 56 54 11 A 6 44 9 10 100 98 43 C - - 45 56 58 56 12 A - - 8 9 99 97 44 C - - 46 57 59 57 13 A - - 7 8 98 96 45 C - - 47 58 60 58 14 A 5 43 5 6 96 94 46 C 31 25 49 60 62 60 15 A - - - 5 95 93 47 C - - - 61 63 61 48/ 16 A 4 42 4 4 94 92 C 32 26 50 62 64 62 TCK 17 B 21 15 33 41 39 37 49 D 33 27 51 63 65 63 18 B - - - 40 38 36 50 D - - - 64 66 64 19 B 20 14 32 39 37 35 51 D 34 28 52 65 67 65 20 B 19 13 30 37 35 33 52 D 36 30 54 67 69 67 21 B 18 12 29 36 34 32 53 D 37 31 55 68 70 68 22 B - - 28 35 33 31 54 D - - 56 69 71 69 23 B - - - 34 32 30 55 D - - - 70 73 71 56/ 24 B 17 11 27 33 31 29 D 38 32 57 71 75 73 TDO 25 B 16 10 25 31 27 25 57 D 39 33 59 73 77 75 26 B - - - 30 25 23 58 D - - - 74 78 76 27 B - - 24 29 23 21 59 D - - 60 75 81 79 28 B - - 23 28 22 20 60 D - - 61 76 82 80 29 B - - 22 27 21 19 61 D - - 62 77 83 81 30 B 14 8 20 25 19 17 62 D 40 34 64 79 85 83 31 B - - - 24 18 16 63 D - - - 80 86 84 32/ D/ B 13 7 19 23 17 15 64 41 35 65 81 87 85 TMS GCLK3 19 1409J–PLD–6/05

SUPPLY CURRENT VS. SUPPLY VOLTAGE SUPPLY CURRENT VS. FREQUENCY (TA = 25°C, F = 0) LOW-POWER ("L") VERSION (TA = 25°C) 100 100.0 75 80.0 STANDARD POWER I (mA)CC 50 REDUCED POWER MODE I (mA)CC 4600..00 STANDARD POWER REDUCED POWER 25 20.0 0 0.0 2.50 2.75 3.00 3.25 3.50 3.75 4.00 0.00 5.00 10.00 15.00 20.00 SUPPLY VOLTAGE (V) FREQUENCY (MHz) SUPPLY CURRENT VS. SUPPLY VOLTAGE OUTPUT SOURCE CURRENT PIN-CONTROLLED POWER-DOWN MODE VS. SUPPLY VOLTAGE (TA = 25°C, F = 0) (VOH = 2.4V, TA = 25°C) 800 0 -2 700 -4 I (uA)CC 600 STANDARD & REDUCED POWER MODE I (mA)OH -1--086 500 -12 -14 -16 400 2.75 3.00 3.25 3.50 3.75 4.00 2.50 2.75 3.00 3.25 3.50 3.75 4.00 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) OUTPUT SOURCE CURRENT SUPPLY CURRENT VS. FREQUENCY VS. OUTPUT VOLTAGE STANDARD POWER (TA = 25°C) (VCC = 3.3V, TA = 25°C) 150.0 10 0 125.0 -10 100.0 STANDARD POWER A) -20 I (mA)CC 5705..00 REDUCED POWER MODE I (mOH ---543000 -60 25.0 -70 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0.0 0.00 20.00 40.00 60.00 80.00 100.00 OUTPUT VOLTAGE (V) FREQUENCY (MHz) OUTPUT SINK CURRENT VS. SUPPLY VOLTAGE SUPPLLYO CWU-RPROEWNETR V S(".L S"U) VPEPRLYS IVOONLTAGE (VOL = 0.5V, TA = 25°C) 40 (TA = 25°C, F = 0) 25 35 20 A) I (uA)CC 1105 I (mOL 2350 5 20 2.75 3.00 3.25 3.50 3.75 4.00 0 2.50 2.75 3.00 3.25 3.50 3.75 4.00 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) ATF1504ASV(L) 20 1409J–PLD–6/05

ATF1504ASV(L) OUTPUT SINK CURRENT VS. OUTPUT VOLTAGE INPUT CURRENT VS. INPUT VOLTAGE (VCC = 3.3V, TA = 25°C) (VCC = 3.3V, TA = 25°C) 100 15 80 A) 10 mA) 60 RENT (u 5 I (OL 40 UT CUR 0 P 20 IN -5 0 -10 0 0.5 1 1.5 2 2.5 3 3.5 4 0 0.5 1 1.5 2 2.5 3 3.5 OUTPUT VOLTAGE (V) INPUT VOLTAGE (V) INPUT CLAMP CURRENT VS. INPUT VOLTAGE (VCC = 3.3V, TA = 25°C) 0 A) -20 m NT ( -40 E R R U -60 C UT NP -80 I -100 -1 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 INPUT VOLTAGE (V) 21 1409J–PLD–6/05

Ordering Information ATF1504ASV(L) Standard Package Options t t f PD CO1 MAX (ns) (ns) (MHz) Ordering Code Package Operation Range ATF1504ASV-15 AC44 44A ATF1504ASV-15 JC44 44J ATF1504ASV-15 JC68(2) 68J Commercial 15 8 100 ATF1504ASV-15 JC84(3) 84J (0°C to 70°C) ATF1504ASV-15 QC100(2) 100Q1 ATF1500ASV-15 AC100 100A ATF1504ASV-15 AI44 44A ATF1504ASV-15 JI44 44J ATF1504ASV-15 JI68 68J Industrial 15 8 100 ATF1504ASV-15 JI84 84J (-40°C to +85°C) ATF1504ASV-15 QI100 100Q1 ATF1504ASV-15 AI100 100A ATF1504ASVL-20 AC44 44A ATF1504ASVL-20 JC44 44J ATF1504ASVL-20 JC68(2) 68J Commercial 20 12 83.3 ATF1504ASVL-20 JC84(3) 84J (0°C to 70°C) ATF1504ASVL-20 QC100(2) 100Q1 ATF1504ASVL-20 AC100 100A ATF1504ASVL-20 AI44 44A ATF1504ASVL-20 JI44 44J ATF1504ASVL-20 JI68 68J Industrial 20 12 83.3 ATF1504ASVL-20 JI84 84J (-40°C to +85°C) ATF1504ASVL-20 QI100 100Q1 ATF1504ASVL-20 AI100 100A Note: 1. The last time buy is Sept. 30, 2005 for shaded parts. 2. The recommended migration for QC100 or JC68 packages is the AU100 or the smaller JU44 packages. 3. The recommended migration for the JC84 package is the ATF1508ASV-15JU84 Using “C” Product for Industrial There is very little risk in using “C” devices for industrial applications because the V conditions for 3.3V products are the CC same for commercial and industrial (there is only 15°C difference at the high end of the temperature range). To use com- mercial product for industrial temperature ranges, de-rate I by 15%. CC ATF1504ASV(L) 22 1409J–PLD–6/05

ATF1504ASV(L) ATF1504ASV(L) Green Package Options (Pb/Halide-free/RoHS Compliant) t t f PD CO1 MAX (ns) (ns) (MHz) Ordering Code Package Operation Range ATF1504ASV-15 AU44 44A Industrial 15 8 100 ATF1504ASV-15 JU44 44J (-40°C to +85°C) ATF1504ASV-15 AU100 100A ATF1504ASVL-20 AU44 44A Industrial 20 12 83.3 ATF1504ASVL-20 JU44 44J (-40°C to +85°C) ATF1504ASVL-20 AU100 100A Package Type 44A 44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP) 44J 44-lead, Plastic J-leaded Chip Carrier (PLCC) 68J 68-lead, Plastic J-leaded Chip Carrier (PLCC) 84J 84-lead, Plastic J-leaded Chip Carrier (PLCC) 100Q1 100-lead, 14 x 20 mm Body, Plastic Quad Flat Package (PQFP) 100A 100-lead, 14 x 14 mm Body, Thin Profile Plastic Quad Flat Package (TQFP) 23 1409J–PLD–6/05

Packaging Information 44A – TQFP PIN 1 B PIN 1 IDENTIFIER e E1 E D1 D C 0˚~7˚ A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 11.75 12.00 12.25 D1 9.90 10.00 10.10 Note 2 E 11.75 12.00 12.25 Notes: 1.This package conforms to JEDEC reference MS-026, Variation ACB. E1 9.90 10.00 10.10 Note 2 2.Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum B 0.30 – 0.45 plastic body size dimensions including mold mismatch. C 0.09 – 0.20 3. Lead coplanarity is 0.10 mm maximum. L 0.45 – 0.75 e 0.80 TYP 10/5/2001 TITLE DRAWING NO. REV. 2325 Orchard Parkway 44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness, San Jose, CA 95131 44A B R 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) ATF1504ASV(L) 24 1409J–PLD–6/05

ATF1504ASV(L) 44J – PLCC 1.14(0.045) X 45˚ 1.14(0.045) X 45˚ PIN NO. 1 0.318(0.0125) IDENTIFIER 0.191(0.0075) E1 E B1 D2/E2 B e A2 D1 A1 D A 0.51(0.020)MAX 45˚ MAX (3X) COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A 4.191 – 4.572 A1 2.286 – 3.048 A2 0.508 – – D 17.399 – 17.653 D1 16.510 – 16.662 Note 2 E 17.399 – 17.653 Notes: 1.This package conforms to JEDEC reference MS-018, Variation AC. E1 16.510 – 16.662 Note 2 2.Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 D2/E2 14.986 – 16.002 and E1 include mold mismatch and are measured at the extreme B 0.660 – 0.813 material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. B1 0.330 – 0.533 e 1.270 TYP 10/04/01 TITLE DRAWING NO. REV. 2325 Orchard Parkway 44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC) San Jose, CA 95131 44J B R 25 1409J–PLD–6/05

68J – PLCC 1.14(0.045) X 45˚ 1.14(0.045) X 45˚ PIN NO. 1 0.318(0.0125) IDENTIFIER 0.191(0.0075) E1 E B1 D2/E2 B e A2 D1 A1 D A 0.51(0.020)MAX 45˚ MAX (3X) COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A 4.191 – 4.572 A1 2.286 – 3.048 A2 0.508 – – D 25.019 – 25.273 D1 24.130 – 24.333 Note 2 E 25.019 – 25.273 Notes: 1.This package conforms to JEDEC reference MS-018, Variation AE. E1 24.130 – 24.333 Note 2 2.Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 D2/E2 22.606 – 23.622 and E1 include mold mismatch and are measured at the extreme B 0.660 – 0.813 material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. B1 0.330 – 0.533 e 1.270 TYP 10/04/01 TITLE DRAWING NO. REV. 2325 Orchard Parkway 68J, 68-lead, Plastic J-leaded Chip Carrier (PLCC) San Jose, CA 95131 68J B R ATF1504ASV(L) 26 1409J–PLD–6/05

ATF1504ASV(L) 84J – PLCC 1.14(0.045) X 45˚ 1.14(0.045) X 45˚ PIN NO. 1 0.318(0.0125) IDENTIFIER 0.191(0.0075) E1 E B1 D2/E2 B e A2 D1 A1 D A 0.51(0.020)MAX 45˚ MAX (3X) COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A 4.191 – 4.572 A1 2.286 – 3.048 A2 0.508 – – D 30.099 – 30.353 D1 29.210 – 29.413 Note 2 E 30.099 – 30.353 Notes: 1.This package conforms to JEDEC reference MS-018, Variation AF. E1 29.210 – 29.413 Note 2 2.Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 D2/E2 27.686 – 28.702 and E1 include mold mismatch and are measured at the extreme B 0.660 – 0.813 material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. B1 0.330 – 0.533 e 1.270 TYP 10/04/01 TITLE DRAWING NO. REV. 2325 Orchard Parkway 84J, 84-lead, Plastic J-leaded Chip Carrier (PLCC) San Jose, CA 95131 84J B R 27 1409J–PLD–6/05

100Q1 – PQFP E PIN 1 ID PIN 1 e D1 B D E1 COMMON DIMENSIONS (Unit of Measure = mm) A JEDEC STANDARD MS-022, GC-1 0º~7º C SYMBOL MIN NOM MAX NOTE L A – 3.04 3.4 A1 A1 0.25 0.33 0.5 D 23.20 BSC E 17.20 BSC E1 14.00 BSC B 0.22 – 0.40 D1 20 BSC L 0.73 – 1.03 e 0.65 BSC 09/10/2002 TITLE DRAWING NO. REV. 2325 Orchard Parkway San Jose, CA 95131 100Q1, 100-lead, 14 x 20 mm Body, 3.2 mm Footprint, 0.65 mm Pitch, 100Q1 B R Plastic Quad Flat Package (PQFP) ATF1504ASV(L) 28 1409J–PLD–6/05

ATF1504ASV(L) 100A – TQFP PIN 1 B PIN 1 IDENTIFIER e E1 E D1 D C 0˚~7˚ A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 15.75 16.00 16.25 D1 13.90 14.00 14.10 Note 2 E 15.75 16.00 16.25 Notes: 1.This package conforms to JEDEC reference MS-026, Variation AED. E1 13.90 14.00 14.10 Note 2 2.Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum B 0.17 – 0.27 plastic body size dimensions including mold mismatch. C 0.09 – 0.20 3. Lead coplanarity is 0.08 mm maximum. L 0.45 – 0.75 e 0.50 TYP 10/5/2001 TITLE DRAWING NO. REV. 2325 Orchard Parkway 100A, 100-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness, San Jose, CA 95131 100A C R 0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) 29 1409J–PLD–6/05

Revision History Revision Comments 1409J Green package options added. ATF1504ASV(L) 30 1409J–PLD–6/05

Atmel Corporation Atmel Operations 2325 Orchard Parkway Memory RF/Automotive San Jose, CA 95131, USA 2325 Orchard Parkway Theresienstrasse 2 Tel: 1(408) 441-0311 San Jose, CA 95131, USA Postfach 3535 Fax: 1(408) 487-2600 Tel: 1(408) 441-0311 74025 Heilbronn, Germany Fax: 1(408) 436-4314 Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Regional Headquarters Microcontrollers Europe 2325 Orchard Parkway 1150 East Cheyenne Mtn. Blvd. Atmel Sarl San Jose, CA 95131, USA Colorado Springs, CO 80906, USA Route des Arsenaux 41 Tel: 1(408) 441-0311 Tel: 1(719) 576-3300 Case Postale 80 Fax: 1(408) 436-4314 Fax: 1(719) 540-1759 CH-1705 Fribourg La Chantrerie Biometrics/Imaging/Hi-Rel MPU/ Switzerland BP 70602 High Speed Converters/RF Datacom Tel: (41) 26-426-5555 44306 Nantes Cedex 3, France Avenue de Rochepleine Fax: (41) 26-426-5500 Tel: (33) 2-40-18-18-18 BP 123 Asia Fax: (33) 2-40-18-19-60 38521 Saint-Egreve Cedex, France Room 1219 Tel: (33) 4-76-58-30-00 Chinachem Golden Plaza ASIC/ASSP/Smart Cards Fax: (33) 4-76-58-34-80 Zone Industrielle 77 Mody Road Tsimshatsui 13106 Rousset Cedex, France East Kowloon Tel: (33) 4-42-53-60-00 Hong Kong Fax: (33) 4-42-53-60-01 Tel: (852) 2721-9778 Fax: (852) 2722-1369 1150 East Cheyenne Mtn. Blvd. Japan Colorado Springs, CO 80906, USA 9F, Tonetsu Shinkawa Bldg. Tel: 1(719) 576-3300 1-24-8 Shinkawa Fax: 1(719) 540-1759 Chuo-ku, Tokyo 104-0033 Japan Scottish Enterprise Technology Park Tel: (81) 3-3523-3551 Maxwell Building Fax: (81) 3-3523-7581 East Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743 Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise,to any intellectualproperty right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN- TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representationsor warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustainlife. © Atmel Corporation 2005. All rights reserved. Atmel®, logo and combinations thereof, Everywhere You Are® and others, are registered trade- marks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Printed on recycled paper. 1409J–PLD–6/05 xM

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