ATF1502AS and ATF1502ASL High-performance EEPROM Complex Programmable Logic Device DATASHEET Features  High-density, High-performance, Electrically-erasable Complex Programmable Logic Device ̶ 32 Macrocells ̶ 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell ̶ 44 Pins ̶ 7.5ns Maximum Pin-to-pin Delay ̶ Registered Operation up to 125MHz ̶ Enhanced Routing Resources  In-System Programmability (ISP) via JTAG  Flexible Logic Macrocell ̶ D/T Latch Configurable Flip-flops ̶ Global and Individual Register Control Signals ̶ Global and Individual Output Enable ̶ Programmable Output Slew Rate ̶ Programmable Output Open Collector Option ̶ Maximum Logic Utilization by Burying a Register with a COM Output  Advanced Power Management Features ̶ Automatic 10μA Standby for “L” Version ̶ Pin-controlled 1mA Standby Mode ̶ Programmable Pin-keeper Inputs and I/Os ̶ Reduced-power Feature per Macrocell  Available in Commercial and Industrial Temperature Ranges  Available in 44-lead PLCC and 44-lead TQFP  Advanced EEPROM Technology ̶ 100% Tested ̶ Completely Reprogrammable ̶ 10,000 Program/Erase Cycles ̶ 20 Year Data Retention ̶ 2000V ESD Protection ̶ 200mA Latch-up Immunity  JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported  PCI-compliant  Security Fuse Feature  Green (Pb/Halide-fee/RoHS Compliant) Package Options Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014

Enhanced Features  Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)  Output Enable Product Terms  D Latch Mode  Combinatorial Output with Registered Feedback within Any Macrocell  Three Global Clock Pins  ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O (“L” Versions)  Fast Registered Input from Product Term  Programmable “Pin-keeper” Option  V Power-up Reset Option CC  Pull-up Option on JTAG Pins TMS and TDI  Advanced Power Management Features ̶ Input Transition Detection ̶ Power-down (“L” Versions) ̶ Individual Macrocell Power Option ̶ Disable ITD on Global Clocks, Inputs, and I/O Description The Atmel® ATF1502AS(L) is a high-performance, high-density Complex Programmable Logic Device (CPLD) which utilizes the Atmel proven electrically-erasable technology. With 32 logic macrocells and up to 36 inputs, it easily integrates logic from several TTL, SSI, MSI, LSI, and classic PLDs. The ATF1502AS(L)’s enhanced routing switch matrices increase usable gate count and the odds of successful pin-locked design modifications. The ATF1502AS(L) has up to 32 bi-directional I/O pins and four dedicated input pins, depending on the type of device package selected. Each dedicated pin can serve as a global control signal, register clock, register reset, or output enable. Each of these control signals can be selected for use individually within each macrocell. Each of the 32 macrocells generates a buried feedback which goes to the global bus. Each input and I/O pin also feeds into the global bus. The switch matrix in each logic block then selects 40 individual signals from the global bus. Each macrocell also generates a foldback logic term that goes to a regional bus. Cascade logic between macrocells in the ATF1502AS(L) allows fast, efficient generation of complex logic functions. The ATF1502AS(L) contains four such logic chains, each capable of creating sum term logic with a fan-in of up to 40 product terms. The ATF1502AS(L) macrocell, shown in Figure 1, is flexible enough to support highly complex logic functions operating at high speed. The macrocell consists of five sections:  Product Terms and Product Term Select Multiplexer  OR/XOR/CASCADE Logic  Flip-flop  Output Select and Enable  Logic Array Inputs 2 ATF1502AS(L) [DATASHEET] Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014

Figure 1. ATF1502AS(L) Macrocell SWITCH REGIONAL MATRIX FOLDBACK OUTPUTS BUS LOGIC FOLDBACK CASIN GOE[0:5] MOE HX WITCATRI SM I/O Pin PTMUX I/O Pin GCK[0:2] SLEW RATE OPEN COLLECTOR OPTION GCLEAR- MACROCELL REDUCED POWER BIT CASOUT GLOBAL BUS ATF1502AS(L) [DATASHEET] 3 Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014

1. Pin Configurations and Pinouts Figure 1-1. Pinouts 44-lead TQFP 44-lead PLCC (Top View) (Top View) 2/I E2/I O I/OI/OI/OVCCGCLK2/OEGCLR/II/OE1GCLK1/IGNDGCLK3/I/OI/O I/OI/OI/OVCCGCLK2/OGCLR/IOE1/IGCLK1/IGNDGCLK3/I/I/O 43210987654 65432143210 44444333333 TDI/I/O 7 4444439 I/O I/O/TDI 1 33 I/O I/O 8 38 I/O/TDO I/O 2 32 I/O/TDO I/O 9 37 I/O I/O 3 31 I/O GND 10 36 I/O GND 4 30 I/O PD1/I/O 11 35 VCC PD1/I/O 5 29 VCC I/O 12 34 I/O I/O 6 28 I/O I/O/TMS 13 33 I/O TMS/I/O 7 27 I/O I/O 8 26 I/O/TCK I/O 14 32 I/O/TCK VCC 9 25 I/O VCC 15 31 I/O I/O 10 24 GND I/O 16 30 GND I/O 11 23 I/O I/O 17 29 I/O 89012345678 11222222222 23456789012 11111111222 OOOODCOOOOO I/OI/OI/OI/OGNDVCCI/OD2/I/OI/OI/OI/O I/I/I/I/GNVCI/PD2/I/I/I/I/ P 44-lead TQFP Top View 44-lead PLCC Top View 4 ATF1502AS(L) [DATASHEET] Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014

2. Block Diagram Figure 2-1. Block Diagram Logic Block A gional dbacks Macrocells ReFol 1 to 16 I/O Pins SwitchMatrix BUS) Logic Block B I/O Pins S K C A L B A D OBUSEE LBF G d n a GOE[0:5] GCK[0:2] GCLEAR GOE[0:5] EOnuatpbulet (INPUTS GCLEAR GCK[0:2] GOE[0:5] Switch Matrix I/O (MC32)/GCLK3 Global Clock GCK[0:2] Mux INPUT/GCLK1 OE1/INPUT INPUT/OE2/GCLK2 Global Clear GCLEAR Mux INPUT/GCLR Unused product terms are automatically disabled by the compiler to decrease power consumption. A security fuse, when programmed, protects the contents of the ATF1502AS(L). Two bytes (16 bits) of User Signature are accessible to the user for purposes such as storing project name, part number, revision, or date. The User Signature is accessible regardless of the state of the security fuse. The ATF1502AS(L) device is an In-System Programmable (ISP) device. It uses the industry standard 4-pin JTAG interface (IEEE Std. 1149.1), and is fully compliant with JTAG’s Boundary-scan Description Language (BSDL). ISP allows the device to be programmed without removing it from the printed circuit board. In addition to simplifying the manufacturing flow, ISP also allows design modifications to be made in the field via software. ATF1502AS(L) [DATASHEET] 5 Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014

3. Macrocell Sections Table 3-1. Macrocell Sections Section Description Each ATF1502AS(L) macrocell has five product terms. Each product term receives as its inputs all signals from both the global bus and regional bus. Product Terms and The Product Term Select Multiplexer (PTMUX) allocates the five product terms as needed to the Select Mux macrocell logic gates and control signals. The PTMUX programming is determined by the design compiler, which selects the optimum macrocell configuration. The ATF1502AS(L) logic structure is designed to efficiently support all types of logic. Within a single macrocell, all the product terms can be routed to the OR gate, creating a 5-input AND/OR sum term. With the addition of the CASIN from neighboring macrocells, this can be expanded to as many as 40 product terms with little additional delay. OR/XOR/CASCADE The macrocell’s XOR gate allows efficient implementation of compare and arithmetic functions. Logic One input to the XOR comes from the OR sum term. The other XOR input can be a product term or a fixed high or low level. For combinatorial outputs, the fixed level input allows polarity selection. For registered functions, the fixed levels allow DeMorgan minimization of product terms. The XOR gate is also used to emulate T-type and JK-type flip-flops. The ATF1502AS(L) flip-flop has very flexible data and control functions. The data input can come from either the XOR gate, from a separate product term, or directly from the I/O pin. Selecting the separate product term allows creation of a buried registered feedback within a combinatorial output macrocell. (This feature is automatically implemented by the fitter software). In addition to D, T, JK, and SR operation, the flip-flop can be configured as a flow-through latch. In this mode, data passes through when the clock is high and is latched when the clock is low. Flip-flop The clock itself can be either one of the Global CLK signals (GCK[0:2]) or an individual product term. The flip-flop changes state on the clock’s rising edge. When the GCK signal is used as the clock, one of the macrocell product terms can be selected as a clock enable. When the clock enable function is active and the enable signal (product term) is low, all clock edges are ignored. The flip-flop’s Asynchronous Reset (AR) signal can be either the Global Clear (GCLEAR), a product term, or always off. AR can also be a logic OR of GCLEAR with a product term. The Asynchronous Preset (AP) can be a product term or always off. The ATF1502AS(L) macrocell output can be selected as registered or combinatorial. The extra buried feedback signal can be either combinatorial or a registered signal regardless of whether the output is combinatorial or registered. (This enhancement function is automatically implemented by the fitter software.) Feedback of a buried combinatorial output allows the creation of a second latch within a macrocell. I/O Control: The Output Enable Multiplexer (MOE) controls the output enable signal. Extra Feedback Each I/O can be individually configured as an input, output, or for bi-directional operation. The output enable for each macrocell can be selected from the true or compliment of the two output enable pins, a subset of the I/O pins, or a subset of the I/O macrocells. This selection is automatically done by the fitter software when the I/O is configured as an input, all macrocell resources are still available, including the buried feedback, expander, and cascade logic. The global bus contains all input and I/O pin signals as well as the buried feedback signal from all Global Bus/Switch 32 macrocells. The switch matrix in each logic block receives as its inputs all signals from the Matrix global bus. Under software control, up to 40 of these signals can be selected as inputs to the logic block. Each macrocell also generates a foldback product term. This signal goes to the regional bus and is available to four macrocells. The foldback is an inverse polarity of one of the macrocell’s Foldback Bus product terms. The four foldback terms in each region allow generation of high fan-in sum terms (up to nine product terms) with little additional delay. 6 ATF1502AS(L) [DATASHEET] Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014

4. Programmable Pin-keeper Option for Inputs and I/Os The ATF1502AS(L) offers the option of programming all input and I/O pins so the pin-keeper circuits can be utilized. When any pin is driven high or low and then subsequently left floating, it will stay at that previous high or low level. This circuitry prevents unused input and I/O lines from floating to intermediate voltage levels, which causes unnecessary power consumption and system noise. The keeper circuits eliminate the need for external pull-up resistors and eliminate their DC power consumption. Figure 4-1. Input Diagram VCC Input 100K ESD Protection Circuit Programmable Option Figure 4-2. I/O Diagram VCC OE Data I/O VCC 100K Programmable Option ATF1502AS(L) [DATASHEET] 7 Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014

5. Speed/Power Management The ATF1502AS(L) has several built-in speed and power management features. The ATF1502AS(L) contains circuitry which automatically puts the device into a low-power standby mode when no logic transitions are occurring. This not only reduces power consumption during inactive periods, but also provides proportional power savings for most applications running at system speeds below 50MHz. This feature may be selected as a design option. To further reduce power, each ATF1502AS(L) macrocell has a reduced-power bit feature. This feature allows individual macrocells to be configured for maximum power savings. This feature may be selected as a design option. The ATF1502AS(L) also has an optional power-down mode. In this mode, current drops to below 10mA. When the power-down option is selected, either PD1 or PD2 pins (or both) can be used to power down the part. The power-down option is selected in the design source file. When enabled, the device goes into power-down when either PD1 or PD2 is high. In the power-down mode, all internal logic signals are latched and held, as are any enabled outputs. All pin transitions are ignored until the PD pin is brought low. When the power-down feature is enabled, the PD1 or PD2 pin cannot be used as a logic input or output; however, the pin’s macrocell may still be used to generate buried foldback and cascade logic signals. All power-down AC characteristic parameters are computed from external input or I/O pins, with reduced-power bit turned on. For macrocells in reduced-power mode (reduced-power bit turned on), the reduced-power adder, t , must be added to the AC parameters, which include the data paths t , t , t , t , t , and t . RPA LAD LAC IC ACL ACH SEXP The ATF1502AS(L) macrocell also has an option whereby the power can be reduced on a per-macrocell basis. By enabling this power-down option, macrocells that are not used in an application can be turned down, thereby reducing the overall power consumption of the device. Each output also has individual slew rate control. This may be used to reduce system noise by slowing down outputs that do not need to operate at maximum speed. Outputs default to slow switching, and may be specified as fast switching in the design file. 6. Design Software Support ATF1502AS(L) designs are supported by several third-party tools. Automated fitters allow logic synthesis using a variety of high-level description languages and formats. 7. Power-up Reset The ATF1502AS(L) is designed with a power-up reset, a feature critical for state machine initialization. At a point delayed slightly from V crossing V , all registers will be initialized, and the state of each output will CC RST depend on the polarity of its buffer. However, due to the asynchronous nature of reset and uncertainty of how V actually rises in the system, the following conditions are required: CC  The V rise must be monotonic, CC  After reset occurs, all input and feedback setup times must be met before driving the clock pin high, and,  The clock must remain stable during T . D The ATF1502AS(L) has two options for the hysteresis about the reset level, V , Small and Large. During the RST fitting process, users may configure the device with the Power-up Reset hysteresis set to Large or Small. Atmel POF2JED users may select the Large option by including the flag “-power_reset” on the command line after “filename.POF”. To allow the registers to be properly reinitialized with the Large hysteresis option selected, the following condition is added:  If V falls below 2.0V, it must shut off completely before the device is turned on again. CC When the Large hysteresis option is active, I is reduced by several hundred micro amps as well. CC 8 ATF1502AS(L) [DATASHEET] Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014

8. Security Fuse Usage A single fuse is provided to prevent unauthorized copying of the ATF1502AS(L) fuse patterns. Once programmed, fuse verify is inhibited; however, the 16-bit User Signature remains accessible. 9. Programming ATF1502AS(L) devices are In-System Programmable (ISP) devices utilizing the 4-pin JTAG protocol. This capability eliminates package handling normally required for programming and facilitates rapid design iterations and field changes. Atmel provides ISP hardware and software to allow programming of the ATF1502AS(L) via the PC. ISP is performed by using either a download cable, a comparable board tester, or a simple microprocessor interface. When using the ISP hardware or software to program the ATF1502AS(L) devices, four I/O pins must be reserved for the JTAG interface. However, the logic features that the macrocells have associated with these I/O pins are still available to the design for burned logic functions. To facilitate ISP programming by the Automated Test Equipment (ATE) vendors, Serial Vector Format (SVF) files can be created by Atmel-provided software utilities. ATF1502AS(L) devices can also be programmed using standard third-party programmers. With a third-party programmer, the JTAG ISP port can be disabled, thereby allowing four additional I/O pins to be used for logic. Contact your local Atmel representatives or Atmel PLD applications for details. 10. ISP Programming Protection The ATF1502AS(L) has a special feature which locks the device and prevents the inputs and I/O from driving if the programming process is interrupted for any reason. The inputs and I/O default to high-Z state during such a condition. In addition, the pin-keeper option preserves the previous state of the input and I/O PMS during programming. All ATF1502AS(L) devices are initially shipped in the erased state, thereby making them ready to use for ISP. Note: For more information refer to the “Designing for In-System Programmability with Atmel CPLDs” application note. ATF1502AS(L) [DATASHEET] 9 Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014

11. Electrical Characteristics 11.1 Absolute Maximum Ratings* Temperature Under Bias . . . . . . . . . . . . . . . . .-40°C to +85°C *Notice: Stresses beyond those listed under “Absolute Maximum Ratings” may cause Storage Temperature. . . . . . . . . . . . . . . . . . .-65°C to +150°C permanent damage to the device. This is a stress rating only and functional operation of Voltage on Any Pin with the device at these or any other conditions Respect to Ground. . . . . . . . . . . . . . . . . . . . .-2.0V to +7.0V(1) beyond those indicated in the operational sections of this specification is not implied. Voltage on Input Pins with Respect to Ground During Programming. . . . . . . . . .-2.0V to +14.0V(1) Exposure to absolute maximum rating conditions for extended periods may affect Programming Voltage with device reliability. Respect to Ground. . . . . . . . . . . . . . . . . . . .-2.0V to +14.0V(1) Note: 1. Minimum voltage is -0.6VDC, which may undershoot to -2.0V for pulses of less than 20ns. Maximum output pin voltage is V + 0.75VDC, which may overshoot to 7.0V for pulses of less than 20ns. CC 11.2 Pin Capacitance Table 11-1. Pin Capacitance(1) Typ Max Units Conditions C 8 10 pF V = 0V; f = 1MHz IN IN C 8 10 pF V = 0V; f = 1MHz I/O OUT Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. The OGI pin (high-voltage pin during programming) has a maximum capacitance of 12pF. 11.3 DC and AC Operating Conditions Table 11-2. DC and AC Operating Conditions Commercial Industrial Operating Temperature (Ambient) 0C to 70C -40C to 85C V (5.0V) Power Supply 5V± 5% 5V± 10% CC 10 ATF1502AS(L) [DATASHEET] Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014

11.4 DC Characteristics Table 11-3. DC Characteristics Symbol Parameter Condition Min Typ Max Units Input or I/O Low I V = V -2 -10 μA IL Leakage Current IN CC Input or I/O High I 2 10 IH Leakage Current Tri-state Output I V = V or GND -40 40 μA OZ Off-state Current O CC Com. 60 mA Std Mode Ind. 75 mA Power Supply Current, V = Max I CC CC1 Standby V = 0, V IN CC Com. 10 μA “L” Mode Ind. 10 μA Power Supply Current, V = Max I CC “PD” Mode 1 5 mA CC2 Power-down Mode V = 0, V IN CC Com. 35 mA Reduced-power Mode V = Max I (2) CC Std Mode CC3 Supply Current, Standby V = 0, V IN CC Ind. 40 mA V Input Low Voltage -0.3 0.8 V IL V Input High Voltage 2.0 V + 0.3 V IH CCIO Com. 3.0 0.45 V V = V or V Output Low Voltage (TTL) IN IH IL V = Min, I = 12mA CC OL Ind. 0.45 V OL Com. 0.2 V V = V or V Output Low Voltage (CMOS) IN IH IL V = Min, I = 0.1mA CC OL Ind. 0.2 V V = V or V V Output High Voltage (TTL) IN IH IL 2.4 V OH V = Min, I = -4.0mA CC OH Notes: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30s. 2. I refers to the current in the reduced-power mode when macrocell reduced-power is turned on. CC3 ATF1502AS(L) [DATASHEET] 11 Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014

11.5 AC Characteristics Table 11-4. AC Characteristics(11.9) -7 -10 -25 Symbol Parameter Min Max Min Max Min Max Units t Input or Feedback to Non-registered Output 7.5 10 25 ns PD1 t I/O Input or Feedback to Non-registered Feedback 7 9 25 ns PD2 t Global Clock Setup Time 6 7 20 ns SU t Global Clock Hold Time 0 0 0 ns H t Global Clock Setup Time of Fast Input 3 3 5 ns FSU t Global Clock Hold Time of Fast Input 0.5 0.5 2 MHz FH t Global Clock to Output Delay 4.5 5 13 ns COP t Global Clock High Time 3 4 7 ns CH t Global Clock Low Time 3 4 7 ns CL t Array Clock Setup Time 3 3 5 ns ASU t Array Clock Hold Time 2 3 6 ns AH t Array Clock Output Delay 7.5 10 25 ns ACOP t Array Clock High Time 3 4 10 ns ACH t Array Clock Low Time 3 4 10 ns ACL t Minimum Clock Global Period 8 10 22 ns CNT f Maximum Internal Global Clock Frequency 125 100 50 MHz CNT t Minimum Array Clock Period 8 10 22 ns ACNT f Maximum Internal Array Clock Frequency 125 100 50 MHz ACNT f Maximum Clock Frequency 166.7 125 60 MHz MAX t Input Pad and Buffer Delay 0.5 0.5 2 ns IN t I/O Input Pad and Buffer Delay 0.5 0.5 2 ns IO t Fast Input Delay 1 1 2 ns FIN t Foldback Term Delay 4 5 12 ns SEXP t Cascade Logic Delay 0.8 0.8 2 ns PEXP t Logic Array Delay 3 5 8 ns LAD t Logic Control Delay 3 5 8 ns LAC t Internal Output Enable Delay 2 2 4 ns IOE Output Buffer and Pad Delay t 2 1.5 6 ns OD1 (Slow slew rate = OFF; V = 5.0V; C = 35pF) CC L Notes: 1. See ordering information for valid part numbers. 2. The t parameter must be added to the t , t ,t , t , and t parameters for macrocells running in RPA LAD LAC TIC ACL SEXP the reduced-power mode. 12 ATF1502AS(L) [DATASHEET] Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014

Table 11-4. AC Characteristics(11.9) (Continued) -7 -10 -25 Symbol Parameter Min Max Min Max Min Max Units Output Buffer Enable Delay t 4.0 5.0 10 ns ZX1 (Slow slew rate = OFF; V = 5.0V; C = 35pF) CCIO L Output Buffer Enable Delay t 4.5 5.5 10 ns ZX2 (Slow slew rate = OFF; V = 3.3V; C = 35pF) CCIO L Output Buffer Enable Delay t 9 9 12 ns ZX3 (Slow slew rate = ON; V = 5.0V/3.3V; C = 35pF) CCIO L t Output Buffer Disable Delay (C = 5pF) 4 5 8 ns XZ L t Register Setup Time 3 3 6 ns SU t Register Hold Time 2 3 6 ns H t Register Setup Time of Fast Input 3 3 3 ns FSU t Register Hold Time of Fast Input 0.5 0.5 5 ns FH t Register Delay 1 2 2 ns RD t Combinatorial Delay 1 2 2 ns COMB t Array Clock Delay 3 5 8 ns IC t Register Enable Time 3 5 8 ns EN t Global Control Delay 1 1 1 ns GLOB t Register Preset Time 2 3 6 ns PRE t Register Clear Time 2 3 6 ns CLR t Switch Matrix Delay 1 1 2 ns UIM t Reduced-power Adder(2) 10 11 15 ns RPA Notes: 1. See ordering information for valid part numbers. 2. The t parameter must be added to the t , t ,t , t , and t parameters for macrocells running in RPA LAD LAC TIC ACL SEXP the reduced-power mode. ATF1502AS(L) [DATASHEET] 13 Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014

11.6 Timing Model Figure 11-1. Timing Model Internal Output Enable Delay tIOE Global Control Delay Input Delay tGLOB Cascade Logic RDegeilsatyer tIN SMwtaUiIttMrcixh ReLgoisgDDtittetceeLLtErIAA Cll ANaaCDCyyroranytrol DtPIenElXpaPuyFttFa DIsNetlay ttttttttSHPCRCFFSHUROLDUREMB ODuttttttteOOOXZZZtXXXlZDDDpa123123uyt Foldback Term Delay I/O tSEXP Delay tIO 11.7 Input Test Waveforms and Measurement Levels Figure 11-2. Input Test Waveforms and Measurement Levels 3.0V AC AC Driving 1.5V Measurement Levels Level 0.0V Note: t , t = 1.5ns typical R F 11.8 Output AC Test Loads Figure 11-3. Output AC Test Loads 5.0V R1 = 464Ω Output Pin R2 = 250Ω CL = 35pF 14 ATF1502AS(L) [DATASHEET] Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014

11.9 Power-down Mode The ATF1502AS(L) includes an optional pin-controlled power-down feature. When this mode is enabled, the PD pin acts as the power-down pin. When the PD pin is high, the device supply current is reduced to less than 5mA. During power-down, all output data and internal logic states are latched and held. Therefore, all registered and combinatorial output data remain valid. Any outputs that were in a high-Z state at the onset will remain at high-Z. During power-down, all input signals except the power-down pin are blocked. Input and I/O hold latches remain active to ensure the pins do not float to indeterminate levels, further reducing system power. The power-down pin feature is enabled in the logic design file. Designs using the power-down pin may not use the PD pin logic array input; however, all other PD pin macrocell resources may still be used, including the buried feedback and foldback product term array inputs. 11.9.1 Power-down AC Characteristics Table 11-5. Power-down AC Characteristics(1)(2) -7 -10 -25 Symbol Parameter Min Max Min Max Min Max Units t Valid I, I/O before PD High 7 10 25 ns IVDH t Valid OE(2) before PD High 7 10 25 ns GVDH t Valid Clock(2) before PD High 7 10 25 ns CVDH t I, I/O Don’t Care after PD High 12 15 35 ns DHIX t OE(2) Don’t Care after PD High 12 15 35 ns DHGX t Clock(2) Don’t Care after PD High 12 15 35 ns DHCX t PD Low to Valid I, I/O 1 1 1 μs DLIV t PD Low to Valid OE (Pin or Term) 1 1 1 μs DLGV t PD Low to Valid Clock (Pin or Term) 1 1 1 μs DLCV t PD Low to Valid Output 1 1 1 μs DLOV Notes: 1. For slow slew outputs, add t . SSO 2. Pin or product term. ATF1502AS(L) [DATASHEET] 15 Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014

12. JTAG-BST/ISP Overview The JTAG boundary-scan testing is controlled by the Test Access Port (TAP) controller in the ATF1502AS(L). The boundary-scan technique involves the inclusion of a shift-register stage (contained in a Boundary-Scan Cell) adjacent to each component so signals at component boundaries can be controlled and observed using scan testing methods. Each input pin and I/O pin has its own Boundary-Scan Cell (BSC) to support Boundary-Scan Testing (BST). The ATF1502AS(L) does not include a Test Reset (TRST) input pin because the TAP controller is automatically reset at power-up. The five JTAG modes supported include:  SAMPLE/PRELOAD  EXTEST  BYPASS  IDCODE  HIGHZ The ATF1502AS(L) ISP can fully be described using JTAG’s BSDL as described in IEEE Standard 1149.1b. This allows ATF1502AS(L) programming to be described and implemented using any one of the third-party development tools supporting this standard. The ATF1502AS(L) has the option of using four JTAG-standard I/O pins for BST and ISP purposes. The ATF1502AS(L) is programmable through the four JTAG pins using the IEEE standard JTAG programming protocol established by IEEE Standard 1149.1 using 5V TTL-level programming signals from the ISP interface for in-system programming. The JTAG feature is a programmable option. If JTAG (BST or ISP) is not needed, then the four JTAG control pins are available as I/O pins. 13. JTAG Boundary-scan Cell (BSC) Testing The ATF1502AS(L) contains up to 32 I/O pins and four input pins, depending on the device type and package type selected. Each input pin and I/O pin has its own BSC in order to support BST as described in detail by IEEE Standard 1149.1. A typical BSC consists of three capture registers or scan registers and up to two update registers. There are two types of BSCs, one for input or I/O pin and one for the macrocells. The BSCs in the device are chained together through the capture registers. Input to the capture register chain is fed in from the TDI pin while the output is directed to the TDO pin. Capture registers are used to capture active device data signals, to shift data in and out of the device, and to load data into the update registers. Control signals are generated internally by the JTAG TAP controller. The BSC configuration for the input and I/O pins and macrocells is shown below. Figure 13-1. BSC Configuration for Input and I/O Pins (Except JTAG TAP Pins) Dedicated Input To Internal Logic 0 D Q TDO 1 Capture Registers Clock Shift TDI (From Next Register) Note: 1. TheATF1502AS(L)hasapull-upoptiononTMSandTDIpins.Thisfeatureisselectedasadesignoption. 16 ATF1502AS(L) [DATASHEET] Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014

Figure 13-2. BSC Configuration for Macrocell TDO Q D 0 1 CLOCK TDI TDO(cid:1) OEJ 0 1 0 D Q D Q 1 OUTJ 0 1 Pin 0 D Q D Q 1 Capture Update DR DR TDI Mode Shift Clock BSC for I/O Pins and Macrocells ATF1502AS(L) [DATASHEET] 17 Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014

14. PCI Compliance The ATF1502AS(L) supports the growing need in the industry to support the new Peripheral Component Interconnect (PCI) interface standard in PCI-based designs and specifications. The PCI interface calls for high current drivers, which are much larger than the traditional TTL drivers. In general, PLDs and FPGAs parallel outputs to support the high current load required by the PCI interface. The ATF1502AS(L) allows this without contributing to system noise while delivering low output to output skew. Having a programmable high drive option is also possible without increasing output delay or pin capacitance. Figure 14-1. PCI Voltage-to-current Curves for Figure 14-2. PCI Voltage-to-current Curves for +5.0V Signaling in Pull-up Mode +5.0V Signaling in Pull-down Mode Pull Up Pull Down VCC VCC e Test Point e AC drive g g a a point olt olt V V 2.4 2.2 DC DC drive point drive point 1.4 AC drive 0.55 point Test Point -2 -44 Current (mA)-178 3,6 95 Current (mA)380 Table 14-1. PCI DC Characteristics Symbol Parameter Conditions Min Max Units V Supply Voltage 4.75 5.25 V CC V Input High Voltage 2.0 V + 0.5 V IH CC V Input Low Voltage -0.5 0.8 V IL I Input High Leakage Current(1) V = 2.7V 70 μA IH IN I Input Low Leakage Current(1) V = 0.5V -70 μA IL IN V Output High Voltage I = -2mA 2.4 V OH OUT V Output Low Voltage I = 3mA, 6mA 0.55 V OL OUT C Input Pin Capacitance 10 pF IN C CLK Pin Capacitance 12 pF CLK C IDSEL Pin Capacitance 8 pF IDSEL L Pin Inductance 20 nH PIN Note: 1. Leakage current is with pin-keeper off. 18 ATF1502AS(L) [DATASHEET] Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014

Table 14-2. PCI AC Characteristics Symbol Parameter Conditions Min Max Units 0 < V  1.4 -44 mA OUT Switching 1.4 < V < 2.4 -44 + (V - 1.4)/0.024 mA OUT OUT I Current High OH(AC) (Test High) 3.1 < VOUT < VCC Equation A mA V = 3.1V -142 μA OUT V >2.2V 95 mA OUT Switching 2.2 > V > 0 V /0.023 mA OUT OUT I Current Low OL(AC) (Test Point) 0.1 > VOUT > 0 Equation B mA V = 0.71 206 mA OUT I Low Clamp Current -5 < V -1 -25 + (V + 1)/0.015 mA CL IN IN SLEW Output Rise Slew Rate 0.4V to 2.4V Load 1 5 V/ns R SLEW Output Fall Slew Rate 2.4V to 0.4V Load 1 5 V/ns F Notes: 1. Equation A: I = 11.9 (V - 5.25) * (V + 2.45) for V > V > 3.1V. OH OUT OUT CC OUT 2. Equation B: I = 78.5 * V * (4.4 - V ) for 0V < V < 0.71V. OL OUT OUT OUT ATF1502AS(L) [DATASHEET] 19 Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014

15. Pinouts 15.1 ATF1502AS(L) Dedicated Pinouts 44-lead 44-lead Dedicated Pin TQFP J-lead INPUT/OE2/GCLK2 40 2 INPUT/GCLR 39 1 INPUT/OE1 38 44 INPUT/GCLK1 37 43 I/O / GCLK3 35 41 I/O / PD (1,2) 5, 19 11, 25 I/O / TDI (JTAG) 1 7 I/O / TMS (JTAG) 7 13 I/O / TCK (JTAG) 26 32 I/O / TDO (JTAG) 32 38 GND 4, 16, 24, 36 10, 22, 30, 42 V 9, 17, 29, 41 3, 15, 23, 35 CC # of Signal Pins 36 36 # User I/O Pins 32 32 Note: OE (1, 2) . . . . . . . . . . . . . Global OE pins GCLR . . . . . . . . . . . . . . . Global Clear pin GCLK (1, 2, 3). . . . . . . . . Global Clock pins PD (1, 2) . . . . . . . . . . . . . Power-down pins TDI, TMS, TCK, TDO . . . JTAG pins used for boundary-scan testing or in-system programming GND . . . . . . . . . . . . . . . . Ground pins V . . . . . . . . . . . . . . . . . V pins for the device (+5V) CC CC 20 ATF1502AS(L) [DATASHEET] Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014

15.2 ATF1502AS(L) I/O Pinouts MC PLC 44-lead PLCC 44-lead TQFP 1 A 4 42 2 A 5 43 3 A/PD1 6 44 4/TDI A 7 1 5 A 8 2 6 A 9 3 7 A 11 5 8 A 12 6 9/TMS A 13 7 10 A 14 8 11 A 16 10 12 A 17 11 13 A 18 12 14 A 19 13 15 A 20 14 16 A 21 15 17 B 41 35 18 B 40 34 19 B 39 33 20/TDO B 38 32 21 B 37 31 22 B 36 30 23 B 34 28 24 B 33 27 25/TCK B 32 26 26 B 31 25 27 B 29 23 28 B 28 22 29 B 27 21 30 B 26 20 31 B 25 19 32 B 24 18 ATF1502AS(L) [DATASHEET] 21 Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014

22 ATF1502AS(L) [DATASHEET] Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014

ATF1502AS(L) [DATASHEET] 23 Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014

24 ATF1502AS(L) [DATASHEET] Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014

16. Ordering Information 16.1 Green Package Options (Pb/Halide-free/RoHS Compliant) t t f PD CO1 MAX (ns) (ns) (MHz) Ordering Code Package Operation Range ATF1502AS-7AX44 44A Commercial 7.5 4.5 166.7 (0Cto70C) ATF1502AS-7JX44 44J ATF1502AS-10AU44 44A Industrial 10 5 125 (-40Cto+85C) ATF1502AS-10JU44 44J ATF1502ASL-25AU44 44A Industrial 25 13 60 (-40Cto+85C) ATF1502ASL-25JU44 44J Package Type 44A 44-lead, Thin Plastic Gull Wing Quad Flatpack Package (TQFP) 44J 44-lead, Plastic J-leaded Chip Carrier OTP (PLCC) ATF1502AS(L) [DATASHEET] 25 Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014

17. Packaging Information 17.1 44A — 44-lead TQFP D1 D e E E1 b BOTTOM VIEW TOP VIEW C 0°~7° A1 A2 A L SIDE VIEW COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 11.75 12.00 12.25 D1 9.90 10.00 10.10 Note 2 E 11.75 12.00 12.25 E1 9.90 10.00 10.10 Note 2 Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. B 0.30 – 0.45 2. Dimensions D1 and E1 do not include mold protrusion. Allowable C 0.09 – 0.20 protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. L 0.45 – 0.75 3. Lead coplanarity is 0.10 mm maximum. e 0.80 TYP 1/10/13 TITLE GPC DRAWING NO. REV. 44A, 44-lead 10.0 x 10.0x1.0 mm Body, 0.80 mm Package Drawing Contact: Lead Pitch, Thin Profile Plastic Quad Flat AIX 44A D packagedrawings@atmel.com Package (TQFP) 26 ATF1502AS(L) [DATASHEET] Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014

17.2 44J — 44-lead PLCC 1.14(0.045) X 45° 1.14(0.045) X 45° PIN NO. 1 0.318(0.0125) IDENTIFIER 0.191(0.0075) E1 E B1 D2/E2 B e A2 D1 A1 D A 0.51(0.020)MAX 45° MAX (3X) COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A 4.191 – 4.572 A1 2.286 – 3.048 A2 0.508 – – D 17.399 – 17.653 D1 16.510 – 16.662 Note 2 E 17.399 – 17.653 Notes: 1. This package conforms to JEDEC reference MS-018, Variation AC. E1 16.510 – 16.662 Note 2 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 D2/E2 14.986 – 16.002 and E1 include mold mismatch and are measured at the extreme B 0.660 – 0.813 material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. B1 0.330 – 0.533 e 1.270 TYP 10/04/01 TITLE DRAWING NO. REV. Package Drawing Contact: 44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC) 44J B packagedrawings@atmel.com ATF1502AS(L) [DATASHEET] 27 Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014

18. Revision History Revision Date Comments Remove lead based package offering and 15ns speed grade. 0995L 03/2014 Update template, logos, and disclaimer page. 0995K 06/2005 Green package options added. 28 ATF1502AS(L) [DATASHEET] Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014

X X X X X X Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com © 2014 Atmel Corporation. / Rev.: Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014. Atmel®, Atmel logo and combinations thereof, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. DISCLAIMER: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS AND PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and products descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. SAFETY-CRITICAL, MILITARY, AND AUTOMOTIVE APPLICATIONS DISCLAIMER: Atmel products are not designed for and will not be used in connection with any applications where the failure of such products would reasonably be expected to result in significant personal injury or death (“Safety-Critical Applications”) without an Atmel officer's specific written consent. Safety-Critical Applications include, without limitation, life support devices and systems, equipment or systems for the operation of nuclear facilities and weapons systems. Atmel products are not designed nor intended for use in military or aerospace applications or environments unless specifically designated by Atmel as military-grade. Atmel products are not designed nor intended for use in automotive applications unless specifically designated by Atmel as automotive-grade.

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: ATF1502AS-10AU44 ATF1502AS-10JU44 ATF1502AS-7AX44 ATF1502AS-7JX44 ATF1502ASL-25AU44 ATF1502ASL-25JU44