ATA8203/ATA8204/ATA8205 Industrial UHF ASK/FSK Receiver DATASHEET Features ● Frequency receiving range of (3 versions) ● f = 312.5MHz to 317.5MHz or 0 ● f = 431.5MHz to 436.5MHz or 0 ● f = 868MHz to 870MHz 0 ● 30dB image rejection ● Receiving bandwidth ● B = 300kHz for 315MHz/433MHz version IF ● B = 600kHz for 868MHz version IF ● Fully integrated LC-VCO and PLL loop filter ● Very high sensitivity with power matched LNA ● Atmel® ATA8203/ATA8204: ● –107dBm, FSK, BR_0 (1.0Kbit/s to 1.8Kbit/s), Manchester, BER 10E-3 ● –113dBm, ASK, BR_0 (1.0Kbit/s to 1.8Kbit/s), Manchester, BER 10E-3 ● Atmel ATA8205: ● –105dBm, FSK, BR_0 (1.0Kbit/s to 1.8Kbit/s), Manchester, BER 10E-3 ● –111dBm, ASK, BR_0 (1.0Kbit/s to 1.8Kbit/s), Manchester, BER 10E-3 ● High system IIP3 ● –18dBm at 868MHz ● –23dBm at 433MHz ● –24dBm at 315MHz ● System 1-dB compression point ● –27.7dBm at 868MHz ● –32.7dBm at 433MHz ● –33.7dBm at 315MHz ● High large-signal capability at GSM band (blocking –33dBm at +10MHz, IIP3=–24dBm at +20MHz) ● Logarithmic RSSI output ● XTO start-up with negative resistor of 1.5kΩ ● 5V to 20V automotive compatible data interface ● Data clock available for manchester and bi-phase-coded signals ● Programmable digital noise suppression ● Low power consumption due to configurable polling 9121D-INDCO-09/14

● Temperature range –40°C to +85°C ● ESD protection 2kV HBM, All pins ● Communication to microcontroller possible using a single bi-directional data line ● Low-cost solution due to high integration level with minimum external circuitry requirements ● Supply voltage range 4.5V to 5.5V Benefits ● Low BOM list due to high integration ● Use of low-cost 13MHz crystal ● Lowest average current consumption for application due to self polling feature ● Reuse of Atmel ATA5743 software ● World-wide coverage with one PCB due to 3 versions are pin compatible 2 ATA8203/ATA8204/ATA8205 [DATASHEET] 9121D–INDCO–09/14

1. Description The Atmel® ATA8203/ATA8204/ATA8205 is a multi-chip PLL receiver device supplied in an SSO20 package. It has been specially developed for the demands of RF low-cost data transmission systems with data rates from 1Kbit/s to 10Kbit/s in Manchester or Bi-phase code. Its main applications are in the areas of aftermarket keyless entry systems, and tire pressure monitoring systems, telemetering, consumer/industrial remote control applications, home entertainment, access control systems, and security technology systems. It can be used in the frequency receiving range of f =312.5MHz to 317.5MHz, 0 f =431.5MHz to 436.5MHz or f =868MHz to 870MHz for ASK or FSK data transmission. All the statements made below 0 0 refer to 315MHz, 433MHz and 868.3MHz applications. Figure 1-1. System Block Diagram UHF ASK/FSK UHF ASK/FSK Remote control transmitter Remote control receiver ATA8401/02/03/04/05 ATA8203/ ATA8204/ 1 to 5 Micro- ATA8205 Demod. Control controller XTO PLL IF Amp Antenna Antenna VCO PLL XTO Power LNA VCO amp. ATA8203/ATA8204/ATA8205 [DATASHEET] 3 9121D–INDCO–09/14

Figure 1-2. Block Diagram FSK/ASK Dem_out Data CDEM Demodulator DATA Interface and Data Filter RSSI RSSI Limiter out RSSI POLLING/_ON SENS IF Amp. Sensitivity Polling Circuit reduction and Control Logic AVCC DATA_CLK AGND MODE 4. Order DGND f0 = 1 MHz FE CLK DVCC IC_ACTIVE LPF Standby fg = 2.2 MHz Logic IF Loop Amp. Filter XTAL2 XTO XTAL1 Poly-LPF fg = 7 MHz f LC-VCO :2 or :3 LNAREF f f LNA_IN LNA :2 :128 or :4 or :64 LNAGND 4 ATA8203/ATA8204/ATA8205 [DATASHEET] 9121D–INDCO–09/14

2. Pin Configuration Figure 2-1. Pinning SSO20 SENS 1 20 DATA IC_ACTIVE 2 19 POLLING/_ON CDEM 3 18 DGND AVCC 4 17 DATA_CLK TEST1 5 ATA8203/ 16 MODE ATA8204/ RSSI 6 ATA8205 15 DVCC AGND 7 14 XTAL2 LNAREF 8 13 XTAL1 LNA_IN 9 12 TEST3 LNAGND 10 11 TEST2 Table 2-1. Pin Description Pin Symbol Function 1 SENS Sensitivity-control resistor 2 IC_ACTIVE IC condition indicator: Low = sleep mode, High = active mode 3 CDEM Lower cut-off frequency data filter 4 AVCC Analog power supply 5 TEST 1 Test pin, during operation at GND 6 RSSI RSSI output 7 AGND Analog ground 8 LNAREF High-frequency reference node LNA and mixer 9 LNA_IN RF input 10 LNAGND DC ground LNA and mixer 11 TEST 2 Do not connect during operating 12 TEST 3 Test pin, during operation at GND 13 XTAL1 Crystal oscillator XTAL connection 1 14 XTAL2 Crystal oscillator XTAL connection 2 15 DVCC Digital power supply Selecting 315MHz/other versions 16 MODE Low: 315MHz version (Atmel ATA8203) High: 433MHz/868MHz versions (Atmel ATA8204/ATA8205) 17 DATA_CLK Bit clock of data stream 18 DGND Digital ground 19 POLLING/_ON Selects polling or receiving mode; Low: receiving mode, High: polling mode 20 DATA Data output/configuration input ATA8203/ATA8204/ATA8205 [DATASHEET] 5 9121D–INDCO–09/14

3. RF Front-end The RF front-end of the receiver is a low-IF heterodyne configuration that converts the input signal into about 1MHz IF signal with a typical image rejection of 30dB. According to Figure Figure 1-2 on page 4 the front-end consists of an LNA (Low Noise Amplifier), LO (Local Oscillator), I/Q mixer, polyphase low-pass filter and an IF amplifier. The PLL generates the drive frequency f for the mixer using a fully integrated synthesizer with integrated low noise LC- LO VCO (Voltage Controlled Oscillator) and PLL-loop filter. The XTO (crystal oscillator) generates the reference frequency f =f /2 (868MHz and 433MHz versions) or f =f /3 (315MHz version). The integrated LC-VCO generates two or REF XTO REF XTO four times the mixer drive frequency f . The I/Q signals for the mixer are generated with a divide by two or four circuit VCO (f =f /2 for 868MHz version, f =f /4 for 433MHz and 315MHz versions). f is divided by a factor of 128 or 64 and LO VCO LO VCO VCO feeds into a phase frequency detector and is compared with f . The output of the phase frequency detector is fed into an REF integrated loop filter and thereby generates the control voltage for the VCO. If f is determined, f can be calculated using LO XTO the following formula: f =f /128 for 868MHz band, f =f /64 for 433MHz bands, f =f /64 for 315MHz bands. REF LO REF LO REF LO The XTO is a two-pin oscillator that operates at the series resonance of the quartz crystal with high current but low voltage signal, so that there is only a small voltage at the crystal oscillator frequency at pins XTAL1 and XTAL2. According to Figure 3-1, the crystal should be connected to GND with two capacitors C and C from XTAL1 and XTAL2 respectively. L1 L2 The value of these capacitors are recommended by the crystal supplier. Due to an inductive impedance at steady state oscillation and some PCB parasitics, a lower value of C and C is normally necessary. L1 L2 The value of C should be optimized for the individual board layout to achieve the exact value of f and hence of f . (The Lx XTO LO best way is to use a crystal with known load resonance frequency to find the right value for this capacitor.) When designing the system in terms of receiving bandwidth and local oscillator accuracy, the accuracy of the crystal and the XTO must be considered. Figure 3-1. XTO Peripherals V S DVCC C L2 XTAL2 XTAL1 C L1 TEST3 TEST2 The nominal frequency f is determined by the RF input frequency f and the IF frequency f using the following formula LO RF IF (low-side injection): f = f – f LO RF IF To determine f , the construction of the IF filter must be considered. The nominal IF frequency is f =950kHz. To achieve a LO IF good accuracy of the filter corner frequencies, the filter is tuned by the crystal frequency f . This means that there is a fixed XTO relationship between f and f . IF LO f = f /318 for the 315MHz band (Atmel® ATA8203) IF LO f = f /438 for the 433.92MHz band (Atmel ATA8204) IF LO f = f /915 for the 868.3MHz band (Atmel ATA8205) IF LO The relationship is designed to achieve the nominal IF frequency of: f = 987Hz for the 315MHz and B = 300kHz (Atmel ATA8203) IF IF f = 987kHz for the 433.92MHz and B = 300kHz (Atmel ATA8204) IF IF f = 947.8kHz for the 868.3MHz and B = 600kHz (Atmel ATA8205) IF IF The RF input either from an antenna or from an RF generator must be transformed to the RF input pin LNA_IN. The input impedance of this pin is provided in the electrical parameters. The parasitic board inductances and capacitances influence the input matching. The RF receiver Atmel ATA8203/ATA8204/ATA8205 exhibits its highest sensitivity if the LNA is power matched. Because of this, matching to a SAW filter, a 50Ω or an antenna is easier. Figure 14-1 on page 30 “Application Circuit” shows a typical input matching network for f =315MHz, f =433.92MHz or RF RF f =868.3MHz to 50Ω . The input matching network shown in Table 14-2 on page 30 is the reference network for the RF parameters given in the electrical characteristics. 6 ATA8203/ATA8204/ATA8205 [DATASHEET] 9121D–INDCO–09/14

4. Analog Signal Processing 4.1 IF Filter The signals coming from the RF front-end are filtered by the fully integrated 4th-order IF filter. The IF center frequency is: f = 987kHz for the 315 MHz and B = 300kHz (Atmel® ATA8203) IF IF f = 987kHz for the 433.92 MHz and B = 300kHz (Atmel ATA8204) IF IF f = 947.9kHz for the 868.3 MHz and B = 600kHz (Atmel ATA8205) IF IF The nominal bandwidth is 300 kHz for ATA8203 and ATA8204 and 600 kHz for ATA8205. 4.2 Limiting RSSI Amplifier The subsequent RSSI amplifier enhances the output signal of the IF amplifier before it is fed into the demodulator. The dynamic range of this amplifier is Δ R =60dB. If the RSSI amplifier is operated within its linear range, the best S/N ratio is RSSI maintained in ASK mode. If the dynamic range is exceeded by the transmitter signal, the S/N ratio is defined by the ratio of the maximum RSSI output voltage and the RSSI output voltage due to a disturber. The dynamic range of the RSSI amplifier is exceeded if the RF input signal is approximately 60dB higher compared to the RF input signal at full sensitivity. The S/N ratio is not affected by the dynamic range of the RSSI amplifier in FSK mode because only the hard limited signal from a high-gain limiting amplifier is used by the demodulator. The output voltage of the RSSI amplifier (VRSSI) is available at pin RSSI. Using the RSSI output signal, the signal strength of different transmitters can be distinguished. The usable input power range P is –100dBm to –55dBm. Ref Figure 4-1. RSSI Characteristics Atmel ATA8204 RSSI Characteristics 3.5 4.5V -40°C 5.0V -40°C 3 5.5V -40°C 4.5V 25°C V) 2.5 5.0V 25°C SI ( 5.5V 25°C S R 4.5V 85°C _ 2 V 5.0V 85°C 5.5V 85°C 1.5 1 -120 -110 -100 -90 -80 -70 -60 -50 -40 PIN (dBm) The output voltage of the RSSI amplifier is internally compared to a threshold voltage V . V is determined by the Th_red Th_red value of the external resistor R . R is connected between pin SENS and GND or V . The output of the comparator is Sens Sens S fed into the digital control logic. By this means, it is possible to operate the receiver at a lower sensitivity. If R is connected to GND, the receiver switches to full sensitivity. It is also possible to connect the pin SENS directly to Sens GND to get the maximum sensitivity. If R is connected to V , the receiver operates at a lower sensitivity. The reduced sensitivity is defined by the value of Sens S R , and the maximum sensitivity is defined by the signal-to-noise ratio of the LNA input. The reduced sensitivity depends Sens on the signal strength at the output of the RSSI amplifier. Since different RF input networks may exhibit slightly different values for the LNA gain, the sensitivity values given in the electrical characteristics refer to a specific input matching. This matching is described and illustrated in Section 14. “Data Interface” on page 30. ATA8203/ATA8204/ATA8205 [DATASHEET] 7 9121D–INDCO–09/14

R can be connected to V or GND using a microcontroller. The receiver can be switched from full sensitivity to reduced Sens S sensitivity or vice versa at any time. In polling mode, the receiver does not wake up if the RF input signal does not exceed the selected sensitivity. If the receiver is already active, the data stream at pin DATA disappears when the input signal is lower than defined by the reduced sensitivity. Instead of the data stream, the pattern according to Figure 4-2 “Steady L State Limited DATA Output Pattern” is issued at pin DATA to indicate that the receiver is still active (see Figure 13-2 on page 28 “Data Interface”). Figure 4-2. Steady L State Limited DATA Output Pattern DATA t t DATA_min DATA_L_max 4.3 FSK/ASK Demodulator and Data Filter The signal coming from the RSSI amplifier is converted into the raw data signal by the ASK/FSK demodulator. The operating mode of the demodulator is set using the bit ASK/_FSK in the OPMODE register. Logic L sets the demodulator to FSK, applying H to ASK mode. In ASK mode an automatic threshold control circuit (ATC) is employed to set the detection reference voltage to a value where a good signal to noise ratio is achieved. This circuit also implements the effective suppression of any kind of in-band noise signals or competing transmitters. If the S/N (ratio to suppress in-band noise signals) exceeds about 10dB the data signal can be detected properly. However, better values are found for many modulation schemes of the competing transmitter. The FSK demodulator is intended to be used for an FSK deviation of 10kHz≤Δ f≤100kHz. The data signal in FSK mode can be detected if the S/N (ratio to suppress in-band noise signals) exceeds about 2dB. This value is valid for all modulation schemes of a disturber signal. The output signal of the demodulator is filtered by the data filter before it is fed into the digital signal processing circuit. The data filter improves the S/N ratio as its pass-band can be adopted to the characteristics of the data signal. The data filter consists of a 1st order high-pass and a 2nd order low-pass filter. The high-pass filter cut-off frequency is defined by an external capacitor connected to pin CDEM. The cut-off frequency of the high-pass filter is defined by the following formula: 1 fcu_DF = ---------------------------------------------------------- 2×π×30 kΩ ×CDEM In self-polling mode the data filter must settle very rapidly to achieve a low current consumption. Therefore, CDEM cannot be increased to very high values if self-polling is used. On the other hand, CDEM must be large enough to meet the data filter requirements according to the data signal. Recommended values for CDEM are given in the electrical characteristics. The cut-off frequency of the low-pass filter is defined by the selected baud-rate range (BR_Range). The BR_Range is defined in the OPMODE register (refer to Section 11. “Configuring the Receiver” on page 23). The BR_Range must be set in accordance to the baud-rate used. The Atmel® ATA8203/ATA8204/ATA8205 is designed to operate with data coding where the DC level of the data signal is 50%. This is valid for Manchester and Bi-phase coding. If other modulation schemes are used, the DC level should always remain within the range of V =33% and V =66%. The sensitivity may be reduced by up to 2dB in that condition. DC_min DC_max Each BR_Range is also defined by a minimum and a maximum edge-to-edge time (t ). These limits are defined in the ee_sig electrical characteristics. They should not be exceeded to maintain full sensitivity of the receiver. 8 ATA8203/ATA8204/ATA8205 [DATASHEET] 9121D–INDCO–09/14

5. Receiving Characteristics The RF receiver Atmel® ATA8203/ATA8204/ATA8205 can be operated with and without a SAW front-end filter. In a typical automotive application, a SAW filter is used to achieve better selectivity and large signal capability. The receiving frequency response without a SAW front-end filter is illustrated in Figure 5-1 “Narrow Band Receiving Frequency Response ATA8204”. This example relates to ASK mode. FSK mode exhibits a similar behavior. The plots are printed relatively to the maximum sensitivity. If a SAW filter is used, an insertion loss of about 3dB must be considered, but the overall selectivity is much better. When designing the system in terms of receiving bandwidth, the LO deviation must be considered as it also determines the IF center frequency. The total LO deviation is calculated, to be the sum of the deviation of the crystal and the XTO deviation of the Atmel ATA8203/ATA8204/ATA8205. Low-cost crystals are specified to be within ±90ppm over tolerance, temperature, and aging. The XTO deviation of the Atmel ATA8203/ATA8204/ATA8205 is an additional deviation due to the XTO circuit. This deviation is specified to be ±10ppm worst case for a crystal with CM=7fF. If a crystal of ±90ppm is used, the total deviation is ±100ppm in that case. Note that the receiving bandwidth and the IF-filter bandwidth are equivalent in ASK mode but not in FSK mode. Figure 5-1. Narrow Band Receiving Frequency Response ATA8204 Image Rejection versus RF Frequency 10 0 4.5V -40°C -10 5.0V -40 °C 5.5V -40°C -20 4.5V 25°C B) -30 5.0V 25°C d ( 5.5V 25°C -40 -50 -60 -70 430 431 432 433 434 435 436 437 438 (MHz) 6. Polling Circuit and Control Logic The receiver is designed to consume less than 1 mA while being sensitive to signals from a corresponding transmitter. This is achieved using the polling circuit. This circuit enables the signal path periodically for a short time. During this time the bit- check logic verifies the presence of a valid transmitter signal. Only if a valid signal is detected, the receiver remains active and transfers the data to the connected microcontroller. If there is no valid signal present, the receiver is in sleep mode most of the time resulting in low current consumption. This condition is called polling mode. A connected microcontroller is disabled during that time. All relevant parameters of the polling logic can be configured by the connected microcontroller. This flexibility enables the user to meet the specifications in terms of current consumption, system response time, data rate etc. The receiver is very flexible with regards to the number of connection wires to the microcontroller. It can be either operated by a single bi-directional line to save ports to the connected microcontroller or it can be operated by up to five uni-directional ports. ATA8203/ATA8204/ATA8205 [DATASHEET] 9 9121D–INDCO–09/14

7. Basic Clock Cycle of the Digital Circuitry The complete timing of the digital circuitry and the analog filtering is derived from one clock. This clock cycle T is derived Clk from the crystal oscillator (XTO) in combination with a divide by 28 or 30 circuit. According to Section 3. “RF Front-end” on page 6, the frequency of the crystal oscillator (f ) is defined by the RF input signal (f ) which also defines the operating XTO RFin frequency of the local oscillator (f ). The basic clock cycle for Atmel® ATA8204 and Atmel ATA8205 is T 28/f giving LO Clk XTO T =2.066µs for f =868.3MHz and T =2.069µs for f =433.92MHz. For Atmel ATA8203 the basic clock cycle is Clk RF Clk RF T =30/f giving T =2.0382µs for f =315MHz. Clk REF Clk RF T controls the following application-relevant parameters: Clk ● Timing of the polling circuit including bit check ● Timing of the analog and digital signal processing ● Timing of the register programming ● Frequency of the reset marker ● IF filter center frequency (fIF0) Most applications are dominated by three transmission frequencies: f =315MHz is mainly used in USA, Transmit f =868.3MHz and 433.92MHz in Europe. All timings are based on T . For the aforementioned frequencies, T is Transmit Clk Clk given as: ● Application 315MHz band (f = 14.71875MHz, f = 314.13MHz, T = 2.0382µs) XTO LO Clk ● Application 868.3MHz band (f = 13.55234MHz, f = 867.35MHz, T = 2.066µs) XTO LO Clk ● Application 433.92MHz band (f = 13.52875MHz, f = 432.93MHz, T = 2.0696µs) XTO LO Clk For calculation of T for applications using other frequency bands, see table in Section 18. “Electrical Characteristics Atmel Clk ATA8204, ATA8205” on page 35. The clock cycle of some function blocks depends on the selected baud-rate range (BR_Range), which is defined in the OPMODE register. This clock cycle T is defined by the following formulas: XClk BR_Range = BR_Range0: T = 8 × T XClk Clk BR_Range1: T = 4 × T XClk Clk BR_Range2: T = 2 × T XClk Clk BR_Range3: T = 1 × T XClk Clk 10 ATA8203/ATA8204/ATA8205 [DATASHEET] 9121D–INDCO–09/14

8. Polling Mode According to Figure 8-1 on page 12, the receiver stays in polling mode in a continuous cycle of three different modes. In sleep mode the signal processing circuitry is disabled for the time period T while consuming low current of I =I . Sleep S Soff During the start-up period, T , all signal processing circuits are enabled and settled. In the following bit-check mode, the Startup incoming data stream is analyzed bit-by-bit and compared with a valid transmitter signal. If no valid signal is present, the receiver is set back to sleep mode after the period T . This period varies according to each check as it is a statistical Bit-check process. An average value for T is given in the electrical characteristics. During T and T , the current Bitcheck Startup Bit-check consumption is I =I . The condition of the receiver is indicated on pin IC_ACTIVE. The average current consumption in S Son polling mode is dependent on the duty cycle of the active mode and can be calculated as: I ×T +I ×(T +T ) I = ---S--o---f-f------------S---l-e--e--p------------S--o---n---------------S--t--a--r-t--u--p-------------B---i-t----c--h---e--c--k---- Spoll T +T +T Sleep Startup Bit-check During T and T , the receiver is not sensitive to a transmitter signal. To guarantee the reception of a transmitted Sleep Startup command, the transmitter must start the telegram with an adequate preburst. The required length of the preburst depends on the polling parameters T , T , T and the start-up time of a connected microcontroller, T . Thus, Sleep Startup Bit-check Start_microcontroller T depends on the actual bit rate and the number of bits (N ) to be tested. Bit-check Bit-check The following formula indicates how to calculate the preburst length. T ≥ T + T + T + T Preburst Sleep Startup Bit-check Start_microcontroller 8.1 Sleep Mode The length of period T is defined by the 5-bit word Sleep of the OPMODE register, the extension factor X (according Sleep Sleep to Table 11-8 on page 25), and the basic clock cycle T . It is calculated to be: Clk T =Sleep×X ×1024×T Sleep Sleep Clk The maximum value of T is about 60ms if X is set to1. The time resolution is about 2ms in that case. The sleep Sleep Sleep time can be extended to almost half a second by setting X to8. X can be set to8 by bit X to “1”. Sleep Sleep SleepStd Setting the configuration word Sleep to its maximal value puts the receiver into a permanent sleep mode. The receiver remains in this state until another value for Sleep is programmed into the OPMODE register. This is particularily useful when several devices share a single data line. (It can also be used for microcontroller polling: using pin POLLING/_ON, the receiver can be switched on and off.) ATA8203/ATA8204/ATA8205 [DATASHEET] 11 9121D–INDCO–09/14

Figure 8-1. Polling Mode Flow Chart Sleep Mode: All circuits for signal processing are disabled. Only XTO and Polling logic are enabled. Output level on Pin IC_ACTIVE = > low Sleep: 5-bit word defined by Sleep 0 to IS = ISoff Sleep 4 in OPMODE register TSleep = Sleep x XSleep x 1024 x TClk XSleep: Extension factor defined by XSleepStd according to Table 11-8 TClk: Basic clock cycle defined by fXTO and Pin MODE Start-up Mode: The signal processing circuits are TStartup: Is defined by the selected baud rate enabled. After the start-up time (TStartup) range and TClk. The baud-rate range all circuits are in stable is defined by Baud 0 and Baud 1 in condition and ready to receive. the OPMODE register. Output level on Pin IC_ACTIVE = > high IS = ISon TStartup Bit-check Mode: The incoming data stream is analyzed. If the timing indicates a valid transmitter signal, the receiver is set to receiving mode. Otherwise it is set to TBit-check: Depends on the result of the bit check Sleep mode. Output level on Pin IC_ACTIVE = > high If the bit check is ok, TBit-check depends on the number of bits to be IS = ISon checked (NBit-check) and on the TBit-check data rate used. Bit Check NO OK ? If the bit check fails, the average time period for that check depends on the selected baud-rate range and YES on TClk. The baud-rate range is defined by Baud 0 and Baud 1 in the Receiving Mode: OPMODE register. The receiver is turned on permanently and passes the data stream to the connected microcontroller. It can be set to Sleep mode through an OFF command via Pin DATA or Polling/_ON. Output level on Pin IC_ACTIVE = > high IS = ISon OFF Command 8.2 Bit-check Mode In bit-check mode the incoming data stream is examined to distinguish between a valid signal from a corresponding transmitter and signals due to noise. This is done by subsequent time frame checks where the distances between 2 signal edges are continuously compared to a programmable time window. The maximum number of these edge-to-edge tests, before the receiver switches to receiving mode, is also programmable. 12 ATA8203/ATA8204/ATA8205 [DATASHEET] 9121D–INDCO–09/14

8.3 Configuring the Bit Check Assuming a modulation scheme that contains two edges per bit, two time frame checks verify one bit. This is valid for Manchester, Bi-phase, and most other modulation schemes. The maximum count of bits to be checked can be set to 0, 3, 6, or 9 bits using the variable N in the OPMODE register. This implies 0, 6, 12, and 18 edge-to-edge checks respectively. Bit-check If N is set to a higher value, the receiver is less likely to switch to receiving mode due to noise. In the presence of a Bit-check valid transmitter signal, the bit check takes less time if N is set to a lower value. In polling mode, the bit-check time is Bit-check not dependent on NBit-check. Figure 8-2 shows an example where three bits are tested successfully and the data signal is transferred to pin DATA. Figure 8-2. Timing Diagram for Complete Successful Bit Check Bit check ok (Number of checked Bits: 3) IC_ACTIVE Bit check 1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit Dem_out Data_out (DATA) T T Start-up Bit-check Start-up mode Start-check mode Receiving mode According to Figure 8-3, the time window for the bit check is defined by two separate time limits. If the edge-to-edge time t ee is in between the lower bit-check limit T and the upper bit-check limit T , the check continues. If t is smaller than Lim_min Lim_max ee T or t exceeds T , the bit check is terminated and the receiver switches to sleep mode. Lim_min ee Lim_max Figure 8-3. Valid Time Window for Bit Check 1/f Sig t Dem_out ee T Lim_min T Lim_max For best noise immunity using a low span between T and T is recommended. This is achieved using a fixed Lim_min Lim_max frequency at a 50% duty cycle for the transmitter preburst. A “11111...” or a “10101...” sequence in Manchester or Bi-phase is suitable for this. A good compromise between receiver sensitivity and susceptibility to noise is a time window of ±30% regarding the expected edge-to-edge time t . Using pre-burst patterns that contain various edge-to-edge time periods, the ee bit-check limits must be programmed according to the required span. The bit-check limits are determined by means of the formula below. T = Lim_min × T Lim_min XClk T = (Lim_max – 1) × T Lim_max XClk Lim_min and Lim_max are defined by a 5-bit word each within the LIMIT register. Using above formulas, Lim_min and Lim_max can be determined according to the required T , T and T . The Lim_min Lim_max XClk time resolution defining T and T is T . The minimum edge-to-edge time t (t , t ) is defined Lim_min Lim_max XClk ee DATA_L_min DATA_H_min according to the Section 8.6 “Digital Signal Processing” on page 15. The lower limit should be set to Lim_min≥10. The maximum value of the upper limit is Lim_max=63. If the calculated value for Lim_min is < 19, it is recommended to check 6 or 9 bits (N ) to prevent switching to receiving Bit-check mode due to noise. ATA8203/ATA8204/ATA8205 [DATASHEET] 13 9121D–INDCO–09/14

Figure 8-4, Figure 8-5, and Figure 8-6 illustrate the bit check for the bit-check limits Lim_min=14 and Lim_max=24. When the IC is enabled, the signal processing circuits are enabled during T . The output of the ASK/FSK demodulator Startup (Dem_out) is undefined during that period. When the bit check becomes active, the bit-check counter is clocked with the cycle T . XClk Figure 8-4 shows how the bit check proceeds if the bit-check counter value CV_Lim is within the limits defined by Lim_min and Lim_max at the occurrence of a signal edge. In Figure 8-5 the bit check fails as the value CV_Lim is lower than the limit Lim_min. The bit check also fails if CV_Lim reaches Lim_max. This is illustrated in Figure 8-6. Figure 8-4. Timing Diagram During Bit Check Bit check ok Bit check ok (Lim_min = 14, Lim_max = 24) IC_ACTIVE Bit check 1/2 Bit 1/2 Bit 1/2 Bit Dem_out Bit-check 0 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 91011121314151617181 2 3 4 5 6 7 8 91011121314151 2 3 4 counter T XClk T T Start-up Bit-check Start-up mode Bit-check mode Figure 8-5. Timing Diagram for Failed Bit Check (Condition: CV_Lim < Lim_min) (Lim_min = 14, Lim_max = 24) Bit check failed (CV_Lim_ < Lim_min) IC_ACTIVE Bit check 1/2 Bit Dem_out Bit-check 0 1 2 3 4 5 6 1 2 3 4 5 6 7 8 9101112 0 counter T T T Start-up Bit-check Sleep Start-up mode Bit-check mode Sleep mode Figure 8-6. Timing Diagram for Failed Bit Check (Condition: CV_Lim ≥ Lim_max) (Lim_min = 14, Lim_max = 24) Bit check failed (CV_Lim >= Lim_max) IC_ACTIVE Bit check 1/2 Bit Dem_out Bit-check 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 9101112131415161718192021222324 0 counter T T T Start-up Bit-check Sleep Start-up mode Bit-check mode Sleep mode 14 ATA8203/ATA8204/ATA8205 [DATASHEET] 9121D–INDCO–09/14

8.4 Duration of the Bit Check If no transmitter signal is present during the bit check, the output of the ASK/FSK demodulator delivers random signals. The bit check is a statistical process and T varies for each check. Therefore, an average value for T is given in the Bit-check Bit-check electrical characteristics. T depends on the selected baud-rate range and on T . A higher baud-rate range causes a Bit-check Clk lower value for T resulting in a lower current consumption in polling mode. Bit-check In the presence of a valid transmitter signal, T is dependent on the frequency of that signal, f , and the count of the Bit-check Sig checked bits, N . A higher value for N thereby results in a longer period for T requiring a higher value for Bit-check Bit-check Bit-check the transmitter pre-burst T . Preburst 8.5 Receiving Mode If the bit check was successful for all bits specified by N , the receiver switches to receiving mode. According to Figure Bit-check 8-2 on page 13, the internal data signal is switched to pin DATAin that case, and the data clock is available after the start bit has been detected (see Figure 9-1 on page 18). A connected microcontroller can be woken up by the negative edge at pin DATA or by the data clock at pin DATA_CLK. The receiver stays in that condition until it is switched back to polling mode explicitly. 8.6 Digital Signal Processing The data from the ASK/FSK demodulator (Dem_out) is digitally processed in different ways and as a result converted into the output signal data. This processing depends on the selected baud-rate range (BR_Range). Figure 8-7 illustrates how Dem_out is synchronized by the extended clock cycle T . This clock is also used for the bit-check counter. Data can XClk change its state only after T has elapsed. The edge-to-edge time period t of the Data signal as a result is always an XClk ee integral multiple of T . XClk The minimum time period between two edges of the data signal is limited to t ≥T . This implies an efficient ee DATA_min suppression of spikes at the DATA output. At the same time it limits the maximum frequency of edges at DATA. This eases the interrupt handling of a connected microcontroller. The maximum time period for DATA to stay low is limited to T . This function is employed to ensure a finite DATA_L_max response time in programming or switching off the receiver via pin DATA. T is therefore longer than the maximum DATA_L_max time period indicated by the transmitter data stream. Figure 8-9 on page 16 gives an example where Dem_out remains Low after the receiver has switched to receiving mode. Figure 8-7. Synchronization of the Demodulator Output T XClk Clock bit-check counter Dem_out Data_out (DATA) t ee Figure 8-8. Debouncing of the Demodulator Output Dem_out Data_out (DATA) t t t DATA_min DATA_min DATA_min t t t ee ee ee ATA8203/ATA8204/ATA8205 [DATASHEET] 15 9121D–INDCO–09/14

Figure 8-9. Steady L State Limited DATA Output Pattern After Transmission IC_ACTIVE Bit check Dem_out Data_out (DATA) t t DATA_min DATA_L_max Start-up mode Bit-check mode Receiving mode After the end of a data transmission, the receiver remains active. Depending of the bit Noise_Disable in the OPMODE register, the output signal at pin DATA is high or random noise pulses appear at pin DATA (see Section 10. “Digital Noise Suppression” on page 21). The edge-to-edge time period t of the majority of these noise pulses is equal or slightly higher ee than T . DATA_min 8.7 Switching the Receiver Back to Sleep Mode The receiver can be set back to polling mode via pin DATA or via pin POLLING/_ON. When using pin DATA, this pin must be pulled to low by the connected microcontroller for the period t1. Figure 8-10 illustrates the timing of the OFF command (see Figure 13-2 on page 28). The minimum value of t1 depends on the BR_Range. The maximum value for t1 is not limited; however, exceeding the specified value to prevent erasing the reset marker is not recommended. Note also that an internal reset for the OPMODE and the LIMIT register is generated if t1 exceeds the specified values. This item is explained in more detail in the Section 11. “Configuring the Receiver” on page 23. Setting the receiver to sleep mode via DATA is achieved by programming bit 1 to “1” during the register configuration. Only one sync pulse (t3) is issued. The duration of the OFF command is determined by the sum of t1, t2, and t10. The sleep time T elapses after the OFF Sleep command. Note that the capacitive load at pin DATA is limited (see Section 14. “Data Interface” on page 30). Figure 8-10. Timing Diagram of the OFF Command using Pin DATA IC_ACTIVE t1 t2 t3 t5 t4 t10 t7 Out1 (microcontroller) Data_out (DATA) X Serial bi-directional X data line Bit 1 ("1") (Start Bit) OFF-command T T Sleep Start-up Receiving mode Sleep mode Start-up mode 16 ATA8203/ATA8204/ATA8205 [DATASHEET] 9121D–INDCO–09/14

Figure 8-11. Timing Diagram of the OFF Command using Pin POLLING/_ON IC_ACTIVE t t Bit check ok on2 on3 POLLING/_ON Data_out (DATA) X X Serial bi-directional data line X X Receiving mode Sleep mode Start-up mode Bit-check mode Receiving mode Figure 8-12. Activating the Receiving Mode using Pin POLLING/_ON IC_ACTIVE t on1 POLLING/_ON X Data_out (DATA) Serial bi-directional X data line Sleep mode Start-up mode Receiving mode Figure 8-11 “Timing Diagram of the OFF Command using Pin POLLING/_ON” illustrates how to set the receiver back to polling mode using pin POLLING/_ON. The pin POLLING/_ON must be held to low for the time period t . After the positive on2 edge on pin POLLING/_ON and the delay t , the polling mode is active and the sleep time T elapses. on3 Sleep Using the POLLING/_ON command is faster than using pin DATA; however, this requires the use of an additional connection to the microcontroller. Figure 8-12 “Activating the Receiving Mode using Pin “POLLING/_ON” illustrates how to set the receiver to receiving mode using the pin POLLING/_ON. The pin POLLING/_ON must be held to low. After the delay t , the receiver changes from on1 sleep mode to start-up mode regardless of the programmed values for T and N . As long as POLLING/_ON is held Sleep Bit-check to low, the values for T and N is ignored, but not deleted (see Section 10. “Digital Noise Suppression” on page 21). Sleep Bit-check If the receiver is polled exclusively by a microcontroller, T must be programmed to31 (permanent sleep mode). In this Sleep case the receiver remains in sleep mode as long as POLLING/_ON is held to high. ATA8203/ATA8204/ATA8205 [DATASHEET] 17 9121D–INDCO–09/14

9. Data Clock The pin DATA_CLK makes a data shift clock available to sample the data stream into a shift register. Using this data clock, a microcontroller can easily synchronize the data stream. This clock can only be used for Manchester and Bi-phase coded signals. 9.1 Generation of the Data Clock After a successful bit check, the receiver switches from polling mode to receiving mode and the data stream is available at pin DATA. In receiving mode, the data clock control logic (Manchester/Bi-phase demodulator) is active and examines the incoming data stream. This is done, as with the bit check, by subsequent time frame checks where the distance between two edges is continuously compared to a programmable time window. As illustrated in Figure 9-1 on page 18, only two distances between two edges in Manchester and Bi-phase coded signals are valid (Tand 2T). The limits for T are the same as used with the bit check. They can be programmed in the LIMIT-register (Lim_min and Lim_max, see Table 11-10 on page 26 and Table 11-11 on page 26). The limits for 2T are calculated as follows: Lower limit of 2T: Lim_min_2T = (Lim_min + Lim_max) – (Lim_max – Lim_min)/2 Upper limit of 2T: Lim_max_2T= (Lim_min + Lim_max) + (Lim_max – Lim_min)/2 (If the result for ’Lim_min_2T’ or ’Lim_max_2T’ is not an integer value, it is rounded up.) The data clock is available, after the data clock control logic has detected the distance2T (Start bit) and is issued with the delay t after the edge on pin DATA (see Figure 9-1 on page 18). Delay If the data clock control logic detects a timing or logical error (Manchester code violation), as illustrated in Figure 9-2 on page 19 and Figure 9-3 on page 19, it stops the output of the data clock. The receiver remains in receiving mode and starts with the bit check. If the bit check was successful and the start bit has been detected, the data clock control logic starts again with the generation of the data clock (see Figure 9-4 on page 19). Use the function of the data clock only in conjunction with the bit check 3, 6 or 9 is recommended. If the bit check is set to 0 or the receiver is set to receiving mode using the pin POLLING/_ON, the data clock is available if the data clock control logic has detected the distance 2T (Start bit). Note that for Bi-phase-coded signals, the data clock is issued at the end of the bit. Figure 9-1. Timing Diagram of the Data Clock Preburst Data Bit check ok T 2T '1' '1' '1' '1' '1' '0' '1' '1' '0' '1' '0' Dem_out Data_out (DATA) DATA_CLK t t Bit-check mode Start bit Delay P_Data_Clk Receiving mode, data clock control logic active 18 ATA8203/ATA8204/ATA8205 [DATASHEET] 9121D–INDCO–09/14

Figure 9-2. Data Clock Disappears Because of a Timing Error Data Timing error Tee < TLim_min or tLim_max < Tee < TLim_min_2T or Tee > TLim_max_2T T ee '1' '1' '1' '1' '1' '0' '1' '1' '0' '1' '0' Dem_out Data_out (DATA) DATA_CLK Receiving mode, Receiving mode, data clock control bit check active logic active Figure 9-3. Data Clock Disappears Because of a Logical Error Data Logical error (Manchester code violation) '1' '1' '1' '0' '1' '1' '?' '0' '0' '1' '0' Dem_out Data_out (DATA) DATA_CLK Receiving mode, Receiving mode, data clock control bit check active logic active Figure 9-4. Output of the Data Clock After a Successful Bit Check Data Bit check ok '1' '1' '1' '1' '1' '0' '1' '1' '0' '1' '0' Dem_out Data_out (DATA) DATA_CLK Receiving mode, Start bit Receiving mode, bit check active data clock control logic active The delay of the data clock is calculated as follows: t = t + t Delay Delay1 Delay2 ATA8203/ATA8204/ATA8205 [DATASHEET] 19 9121D–INDCO–09/14

t is the delay between the internal signals Data_Out and Data_In. For the rising edge, t depends on the capacitive Delay1 Delay1 load C at pin DATA and the external pull-up resistor R . For the falling edge, t depends additionally on the external L pup Delay1 voltage V (see Figure 9-5, Figure 9-6 on page 20 and Figure 13-2 on page 28). When the level of Data_In is equal to the X level of Data_Out, the data clock is issued after an additional delay t . Delay2 Note that the capacitive load at pin DATA is limited. If the maximum tolerated capacitive load at pin DATA is exceeded, the data clock disappears (see Section 14. “Data Interface” on page 30). Figure 9-5. Timing Characteristic of the Data Clock (Rising Edge on Pin DATA) Data_Out V X V = 0.65 V IH S Serial bi-directional VII = 0.65 VS data line Data_In DATA_CLK t t Delay1 Delay2 t t Delay P_Data_Clk Figure 9-6. Timing Characteristic of the Data Clock (Falling Edge of the Pin DATA) Data_Out V X VIH = 0.65 VS Serial bi-didreacttaio lninael VII = 0.35 VS Data_In DATA_CLK t t Delay1 Delay2 t t Delay P_Data_Clk 20 ATA8203/ATA8204/ATA8205 [DATASHEET] 9121D–INDCO–09/14

10. Digital Noise Suppression After a data transmission, digital noise appears on the data output (see Figure 10-1 “Output of Digital Noise at the End of the Data Stream”). To prevent digital noise keeping the connected microcontroller busy, it can be suppressed in two different ways: ● Automatic Noise Suppression ● Controlled Noise Suppression by the Microcontroller 10.1 Automatic Noise Suppression The receiver changes to bit-check mode at the end of a valid data stream if the bit Noise_Disable (Table 11-9 on page 25) in the OPMODE register is set to 1 (default). The digital noise is suppressed, and the level at pin DATA is high. The receiver changes back to receiving mode, if the bit check was successful. This method of noise suppression is recommended if the data stream is Manchester or Bi-phase coded and is active after power on. Figure 10-3 “Occurrence of a Pulse at the End of the Data Stream” illustrates the behavior of the data output at the end of a data stream. If the last period of the data stream is a high period (rising edge to falling edge), a pulse occurs on pin DATA. The length of the pulse depends on the selected baud-rate range. Figure 10-1. Output of Digital Noise at the End of the Data Stream Bit check ok Bit check ok Preburst Data Digital Noise Digital Noise Preburst Data Digital Noise Data_out (DATA) DATA_CLK Bit-check Receiving mode, Receiving mode, Receiving mode, Receiving mode, mode data clock control bit check active data clock control bit check active logic active logic active Figure 10-2. Automatic Noise Suppression Bit check ok Bit check ok Preburst Data Preburst Data Data_out (DATA) DATA_CLK Bit-check Receiving mode, Bit-check Receiving mode, Bit-check mode data clock control mode data clock control mode logic active logic active ATA8203/ATA8204/ATA8205 [DATASHEET] 21 9121D–INDCO–09/14

Figure 10-3. Occurrence of a Pulse at the End of the Data Stream Timing error tee < TLim_min or TLim_max < tee < tLim_min_2T or tee > TLim_max_2T T ee Data stream Digital noise '1' '1' '1' Dem_out Data_out (DATA) T pulse DATA_CLK Receiving mode, Bit-check mode data clock control logic active 10.2 Controlled Noise Suppression by the Microcontroller Digital noise appears at the end of a valid data stream if the bit Noise_Disable (see Table 11-9 on page 25) in the OPMODE register is set to 0. To suppress the noise, the pin POLLING/_ON must be set to low. The receiver remains in receiving mode. The OFF command then causes a change to start-up mode. The programmed sleep time (see Table 11-7 on page 25) is not executed because the level at pin POLLING/_ON is low; however, the bit check is active in this case. The OFF command also activates the bit check if the pin POLLING/_ON is held to low. The receiver changes back to receiving mode if the bit check was successful. To activate the polling mode at the end of the data transmission, the pin POLLING/_ON must be set to high. This way of suppressing the noise is recommended if the data stream is not Manchester or Bi-phase coded. Figure 10-4. Controlled Noise Suppression Bit check ok OFF-command Bit check ok Serial bi-directional data line Preburst Data Digital Noise Preburst Data Digital Noise (DATA_CLK) POLLING/_ON Bit-check Receiving mode Start-up Bit-check Receiving mode Sleep mode mode mode mode 22 ATA8203/ATA8204/ATA8205 [DATASHEET] 9121D–INDCO–09/14

11. Configuring the Receiver The Atmel® ATA8203/ATA8204/ATA8205 receiver is configured using two 12-bit RAM registers called OPMODE and LIMIT. The registers can be programmed by means of the bidirectional DATA port. If the register content has changed due to a voltage drop, this condition is indicated by a the output pattern called reset marker (RM). If this occurs, the receiver must be reprogrammed. After a Power-On Reset (POR), the registers are set to default mode. If the receiver is operated in default mode, there is no need to program the registers. Table 11-3 on page 23 shows the structure of the registers. According to Table 11-1, bit 1 defines whether the receiver is set back to polling mode using the OFF command (see “Receiving Mode” on page 15) or whether it is programmed. Bit 2 represents the register address. It selects the appropriate register to be programmed. For high programming reliability, bit15 (Stop bit), at the end of the programming operation, must be set to0. Table 11-1. Effect of Bit1 and Bit2 on Programming the Registers Bit 1 Bit 2 Action 1 x The receiver is set back to polling mode (OFF command) 0 1 The OPMODE register is programmed 0 0 The LIMIT register is programmed Table 11-2. Effect of Bit15 on Programming the Register Bit 15 Action 0 The values are written into the register (OPMODE or LIMIT) 1 The values are not written into the register Table 11-3. Effect of the Configuration Words within the Registers Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 Bit 14 Bit 15 OFF command 1 – – – – – – – – – – – – – – – OPMODE register – Modu- Noise BR_Range N Sleep X Bit-check lation Sleep Suppression 0 1 0 ASK/ Noise_ Baud1 Baud0 BitChk1 BitChk0 Sleep4 Sleep3 Sleep2 Sleep1 Sleep0 X _FSK SleepStd Disable Default values of 0 0 0 1 0 0 0 1 1 0 0 1 – Bit 3...14 – LIMIT register – Lim_min Lim_max – 0 0 Lim_ Lim_ Lim_ Lim_ Lim_ Lim_ Lim_ Lim_ Lim_ Lim_ Lim_ Lim_ 0 min5 min4 min3 min2 min1 min0 max5 max4 max3 max2 max1 max0 Default values of 0 1 0 1 0 1 1 0 1 0 0 1 – Bit 3...14 ATA8203/ATA8204/ATA8205 [DATASHEET] 23 9121D–INDCO–09/14

The following tables illustrate the effect of the individual configuration words. The default configuration is highlighted for each word. BR_Range sets the appropriate baud-rate range and simultaneously defines XLim. XLim is used to define the bit-check limits T and T as shown in Table 11-10 on page 26 and Table 11-11 on page 26. Lim_min Lim_max Table 11-4. Effect of the configuration word BR_Range BR_Range Baud1 Baud0 Baud-rate Range/Extension Factor for Bit-check Limits (XLim) BR_Range0 0 0 (BR_Range0 = 1.0Kbit/s to 1.8Kbit/s) XLim = 8 (default) BR_Range1 0 1 (BR_Range1 = 1.8Kbit/s to 3.2Kbit/s) XLim = 4 BR_Range2 1 0 (BR_Range2 = 3.2Kbit/s to 5.6Kbit/s) XLim = 2 BR_Range3 1 1 (BR_Range3 = 5.6Kbit/s to 10Kbit/s) XLim = 1 Table 11-5. Effect of the Configuration word N Bit-check N Bit-check BitChk1 BitChk0 Number of Bits to be Checked 0 0 0 0 1 3 (default) 1 0 6 1 1 9 Table 11-6. Effect of the Configuration Bit Modulation Modulation Selected Modulation ASK/_FSK – 0 FSK (default) 1 ASK 24 ATA8203/ATA8204/ATA8205 [DATASHEET] 9121D–INDCO–09/14

Table 11-7. Effect of the Configuration Word Sleep Sleep Start Value for Sleep Counter Sleep4 Sleep3 Sleep2 Sleep1 Sleep0 (T = Sleep × X × 1024 × T ) Sleep Sleep Clk 0 (Receiver polls continuously until a valid signal 0 0 0 0 0 occurs) If X = 1 Sleep T = 2.11ms for f = 868.3MHz, 0 0 0 0 1 Sleep RF T = 2.12ms for f = 433.92MHz Sleep RF T = 2.08ms for f = 315MHz Sleep RF 0 0 0 1 0 2 0 0 0 1 1 3 ... ... ... ... ... ... If X = 1 Sleep T = 12.69ms for f = 868.3MHz, 0 0 1 1 0 Sleep RF T = 12.71ms for f = 433.92MHz Sleep RF T = 12.52ms for f = 315MHz Sleep RF ... ... ... ... ... ... 1 1 1 0 1 29 1 1 1 1 0 30 1 1 1 1 1 31 (permanent sleep mode) Table 11-8. Effect of the Configuration Bit XSleep X Sleep Extension Factor for Sleep Time X (T = Sleep × X × 1024 × T SleepStd Sleep Sleep Clk) 0 1 (default) 1 8 Table 11-9. Effect of the Configuration Bit Noise Suppression Noise Suppression Noise_Disable Suppression of the Digital Noise at Pin DATA 0 Noise suppression is inactive 1 Noise suppression is active (default) ATA8203/ATA8204/ATA8205 [DATASHEET] 25 9121D–INDCO–09/14

Table 11-10.Effect of the Configuration Word Lim_min Lim_min(1) (Lim_min < 10 is not Applicable) Lower Limit Value for Bit Check Lim_min5 Lim_min4 Lim_min3 Lim_min2 Lim_min1 Lim_min0 (T = Lim_min × XLim × T ) Lim_min Clk 0 0 1 0 1 0 10 0 0 1 0 1 1 11 0 0 1 1 0 0 12 .. .. .. .. .. .. 21 (default, BR_Range0) (T = 347µs for f = 868.3MHz 0 1 0 1 0 1 Lim_min RF T = 347µs for f = 433.92MHz Lim_min RF T = 342µs for f = 315MHz) Lim_min RF .. .. .. .. .. .. 1 1 1 1 0 1 61 1 1 1 1 1 0 62 1 1 1 1 1 1 63 Note: 1. Lim_min is also used to determine the margins of the data clock control logic (see Section 9. “Data Clock” on page 18). . Table 11-11.Effect of the Configuration Word Lim_max Lim_max(1) (Lim_max < 12 is not applicable) Upper Limit Value for Bit Check Lim_max5 Lim_max4 Lim_max3 Lim_max2 Lim_max1 Lim_max0 (TLim_max = (Lim_max – 1) × XLim × T ) Clk 0 0 1 1 0 0 12 0 0 1 1 0 1 13 0 0 1 1 1 0 14 .. .. .. .. .. .. 41 (default, BR_Range0) (T = 66µs for f = 868.3MHz 1 0 1 0 0 1 Lim_max RF T = 662µs for f = 433.92MHz Lim_max RF T = 652µs for f = 315MHz) Lim_max RF .. .. .. .. .. .. 1 1 1 1 0 1 61 1 1 1 1 1 0 62 1 1 1 1 1 1 63 Note: 1. Lim_max is also used to determine the margins of the data clock control logic (see Section 9. “Data Clock” on page 18). 26 ATA8203/ATA8204/ATA8205 [DATASHEET] 9121D–INDCO–09/14

12. Conservation of the Register Information The Atmel® ATA8203/ATA8204/ATA8205 uses an integrated power-on reset and brown-out detection circuitry as a mechanism to preserve the RAM register information. According to Figure 12-1, a power-on reset (POR) is generated if the supply voltage V drops below the threshold voltage S V . The default parameters are programmed into the configuration registers in that condition. The POR is cancelled ThReset after the minimum reset period t when V exceeds V . A POR is also generated when the supply voltage of the Rst S ThReset receiver is turned on. To indicate that condition, the receiver displays a reset marker (RM) at pin DATA after a reset. The RM is represented by the fixed frequency f at a 50% duty-cycle. RM can be cancelled using a low pulse t1 at pin DATA. The RM has the following RM characteristics: ● f is lower than the lowest feasible frequency of a data signal. Due to this, RM cannot be misinterpreted by the RM connected microcontroller. ● If the receiver is set back to polling mode using pin DATA, RM cannot be cancelled accidentally if t1 is applied as described in the proposal in Section 13. “Programming the Configuration Register” on page 28. Using this conservation mechanism, the receiver cannot lose its register information without communicating this condition using the reset marker RM. Figure 12-1. Generation of the Power-on Reset V V S Threset POR t Rst Data_out (DATA) X 1/f RM ATA8203/ATA8204/ATA8205 [DATASHEET] 27 9121D–INDCO–09/14

13. Programming the Configuration Register Figure 13-1. Timing of the Register Programming IC_ACTIVE t1 t2 t3 t5 t9 t4 t8 t6 t7 Out1 (microcontroller) Data_out (DATA) X Serial bi-directional X data line Bit 1 Bit 2 Bit 14 Bit 15 ("0") ("1") ("0") ("0") (Start bit) (Register (Poll 8) (Stop bit) select) Programming frame TSleep TStart-up Receiving Sleep Start-up mode mode mode Figure 13-2. Data Interface ATA8203 VX = 5V to 20V Microcontroller VS = 4.5V to 5.5V ATA8204 ATA8205 Rpup DATA I/O 0V/5V Input 0V to 20V Interface Data_in Serial bi-directional data line I D C L Data_out Out1 (microcontroller) The configuration registers are serially programmed using the bi-directional data line as shown in Figure 13-1 and Figure 13-2. To start programming, the serial data line DATA is pulled to low by the microcontroller for the time period t1. When DATA has been released, the receiver becomes the master device. When the programming delay period t2 has elapsed, the receiver emits 15 subsequent synchronization pulses with the pulse length t3. After each of these pulses, a programming window occurs. The delay until the program window starts is determined by t4, the duration is defined by t5. The individual bits are set within the programming window. If the microcontroller pulls down pin DATA for the time period t7 during t5, the corresponding bit is set to “0”. If no programming pulse t7 is issued, this bit is set to “1”. All 15 bits are programmed this way. The time frame to program a bit is defined by t6. Bit 15 is followed by the equivalent time window t9. During this window, the equivalence acknowledge pulse t8 (E_Ack) occurs if the just programmed mode word is equivalent to the mode word that was already stored in that register. E_Ack should be used to verify that the mode word was correctly transferred to the register. The register must be programmed twice in that case. A register can be programmed when the receiver is in both sleep-mode and active mode. During programming, the LNA, LO, low-pass filter, IF-amplifier, and the FSK/MSK demodulator are disabled. The t1 pulse is used to start the programming or to switch the receiver back to polling mode (OFF command). (The receiver is switched back to polling mode with the OFF command if bit 1 is set to „1“.) The following convention should be considered for the length of the programming start pulse t1: 28 ATA8203/ATA8204/ATA8205 [DATASHEET] 9121D–INDCO–09/14

Using a t1 value of t1 (min) < t1 < 5632TClk (where t1 (min) is the minimum specified value for the relevant BR_Range) when the receiver is active i.e., not in reset mode initiates the programming or OFF command. However, if this t1 value is used when the receiver is in reset mode, programming or OFF command is NOT initiated and RM remains present at pin DATA. Note, the RM cannot be deleted when using this t1 value. Using a t1 value of t1 > 7936´TClk, programming or OFF command is initiated when the receiver is in both reset mode and active mode. The registers PMODE and LIMIT are set to the default values and the RM is deleted, if present. This t1 values can be used if the connected microcontroller detects an RM. Additionally, this t1 value can generally be used if the receiver operates in default mode. Note that the capacitive load at pin DATA is limited. ATA8203/ATA8204/ATA8205 [DATASHEET] 29 9121D–INDCO–09/14

14. Data Interface The data interface (see Figure 13-2 on page 28) is designed for automotive requirements. It can be connected using the pull- up resistor R up to 20V and is short-circuit-protected. pup The applicable pull-up resistor R depends on the load capacity C at pin DATA and the selected BR_range (see pup L Table 14-1). Table 14-1. Applicable R pup - BR_range Applicable R pup B0 1.6kΩ to 47kΩ B1 1.6kΩ to 22kΩ C ≤ 1nF L B2 1.6 Ω to 12kΩ B3 1.6kΩ to 5.6kΩ B0 1.6kΩ to 470kΩ B1 1.6kΩ to 220kΩ C ≤ 100pF L B2 1.6kΩ to 120kΩ B3 1.6kΩ to 56kΩ Figure 14-1. Application Circuit: f = 315MHz(1), 433.92MHz or 868MHz without SAW Filter RF VS RSSI + C7 IC_ACTIVE 4.7μF R2 10% Sensitivity reduction 56kΩ to 150kΩ GND VX = 5V to 20V R3 1.6kΩ C14 1 20 39nF SENS DATA DATA 2 19 5% IC_ACTIVE POLLING/_ON POLLING/_ON 3 18 CDEM DGND 17 DATA_CLK DATA_CLK 4 16 AVCC MODE C12 C13 5 ATA8203 10nF TEST1 10nF 6 ATA8204 15 10% 10% 7 RSSI ATA8205 DVCC 14 CL2 AGND XTAL2 F RF_IN C17 8 LNAREF XTAL1 13 crystal 9 12 LNA_IN TEST3 CL1 10 11 C16 LNAGND TEST2 L1 Note: For 315MHz application pin MODE must be connected to GND. Table 14-2. Input Matching to 50Ω LNA Matching Crystal Frequency RF Frequency (MHz) C16 (pF) C17 (pF) L1 (nH) f (MHz) XTAL 315 Not connected 3 39 14.71875 433.92 Not connected 3 20 13.52875 868.3 1 3 6.8 13.55234 30 ATA8203/ATA8204/ATA8205 [DATASHEET] 9121D–INDCO–09/14

15. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Symbol Min. Max. Unit Supply voltage V 6 V S Power dissipation P 1000 mW tot Junction temperature T 150 °C j Storage temperature T –55 +125 °C stg Ambient temperature T –40 +85 °C amb Maximum input level, input matched to 50Ω P 10 dBm in_max 16. Thermal Resistance Parameters Symbol Value Unit Junction ambient R 100 K/W thJA ATA8203/ATA8204/ATA8205 [DATASHEET] 31 9121D–INDCO–09/14

17. Electrical Characteristics Atmel ATA8203 All parameters refer to GND, T = 25°C, V = 5V, f = 315MHz unlessotherwise specified. amb S 0 f = 315MHz RF 14.71875MHz Oscillator VariableOscillator Test No. Parameter Conditions Symbol Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit Type* 1 Basic Clock Cycle of the Digital Circuitry Basic clock 1.1 T 2.0382 2.0382 30/f 30/f µs A cycle Clk XTO XTO BR_Range0 16.3057 16.3057 8 × T 8 × T µs Extended Clk Clk BR_Range1 8.1528 8.1528 4 × T 4 × T µs 1.2 basic clock T Clk Clk A BR_Range2 XClk 4.0764 4.0764 2 × T 2 × T µs cycle Clk Clk BR_Range3 2.0382 2.0382 1 × T 1 × T µs Clk Clk 2 Polling Mode Sleep time Sleep and (see Sleep × Sleep × XSleep are Sleep × Sleep × Figure 8-1, X × X × 2.1 defined in the T Sleep Sleep X × X × ms A Figure 8-10 Sleep 1024 × 1024 × Sleep Sleep OPMODE 1024 × T 1024 × T and 2.0382 2.0382 Clk Clk register Figure 13-1) BR_Range0 1827 1827 896.5 896.5 µs Start-up time BR_Range1 1044 1044 512.5 512.5 µs (see Figure 2.2 BR_Range2 T 1044 1044 512.5 512.5 µs A 8-1 and Startup BR_Range3 653 653 320.5 320.5 µs Figure 8-4) × T × T µs Clk Clk Average bit- check time while polling, no RF applied Time for bit (see Figure 8-5 2.3 check (see T C and Figure 8-6) Bit-check Figure 8-1 BR_Range0 0.45 0.45 ms BR_Range1 0.24 0.24 ms BR_Range2 0.14 0.14 ms BR_Range3 0.08 0.08 ms Bit-check time for a valid input signal f (see Time for bit Sig Figure 8-5) 2.4 check (see T C N = 0 Bit-check Figure 8-1 Bit-check 1 × T 1 × T 1 × T 1 × T ms N = 3 XClk XClk XClk Clk Bit-check 3/f 3.5/f 3/f 3.5/f ms N = 6 Sig Sig Sig Sig Bit-check 6/f 6.5/f 6/f 6.5/f ms N = 9 Sig Sig Sig Sig Bit-check 9/f 9.5/f 9/f 9.5/f ms Sig Sig Sig Sig 3 Receiving Mode Intermediate 3.1 f 987 f =f /318 kHz A frequency IF IF LO BR_Range0 1.0 1.8 BR_Range0 × 2 µs/T Kbit/s Clk Baud-rate BR_Range1 BR_Rang 1.8 3.2 BR_Range1 × 2 µs/T Kbit/s 3.2 Clk A range BR_Range2 e 3.2 5.6 BR_Range2 × 2 µs/T Kbit/s Clk BR_Range3 5.6 10.0 BR_Range3 × 2 µs/T Kbit/s Clk *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 32 ATA8203/ATA8204/ATA8205 [DATASHEET] 9121D–INDCO–09/14

17. Electrical Characteristics Atmel ATA8203 (Continued) All parameters refer to GND, T = 25°C, V = 5V, f = 315MHz unlessotherwise specified. amb S 0 f = 315MHz RF 14.71875MHz Oscillator VariableOscillator Test No. Parameter Conditions Symbol Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit Type* Minimum time period between BR_Range = edges at pin DATA BR_Range0 163.06 163.06 10 × T 10 × T µs XClk XClk (see Figure BR_Range1 81.53 81.53 10 × T 10 × T µs XClk XClk 3.3 4-2 and BR_Range2 t 40.76 40.76 10 × T 10 × T µs A DATA_min XClk XClk Figure 8-8, BR_Range3 20.38 20.38 10 × T 10 × T µs XClk XClk Figure 8-9) (With the exception of parameter T ) Pulse Maximum BR_Range = Low period BR_Range0 2120 2120 130 × T 130 × T µs XClk XClk 3.4 at pin DATA BR_Range1 t 1060 1060 130 × T 130 × T µs A DATA_L_max XClk XClk (see BR_Range2 530 530 130 × T 130 × T µs XClk XClk Figure 4-2) BR_Range3 265 265 130 × T 130 × T µs XClk XClk Delay to activate the 3.5 start-up Ton1 19.36 21.4 9.5 × T 10.5 × T µs A Clk Clk mode (see Figure 8-12) OFF command at pin 3.6 Ton2 16.3 8 × T µs A POLLING/ Clk _ON (see Figure 8-11) Delay to activate the 3.7 sleep mode Ton3 17.32 19.36 8.5 × T 9.5 × T µs A Clk Clk (see Figure 8-11) Pulse on pin DATA at the BR_Range = end of a data BR_Range0 16.3 16.3 8 × T 8 × T µs 3.8 T Clk Clk C stream BR_Range1 Pulse 8.15 8.15 4 × T 4 × T µs Clk Clk (see BR_Range2 4.07 4.07 2 × T 2 × T µs Clk Clk Figure 10-3) BR_Range3 2.04 2.04 1 × T 1 × T µs Clk Clk *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter ATA8203/ATA8204/ATA8205 [DATASHEET] 33 9121D–INDCO–09/14

17. Electrical Characteristics Atmel ATA8203 (Continued) All parameters refer to GND, T = 25°C, V = 5V, f = 315MHz unlessotherwise specified. amb S 0 f = 315MHz RF 14.71875MHz Oscillator VariableOscillator Test No. Parameter Conditions Symbol Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit Type* 4 Configuration of the Receiver (see Figure 12-1 and Figure 13-1) Frequency is Frequency 1/ 1/ stable within 4.1 of the reset f 119.78 119.78 (4096 × (4096 × Hz A 50ms after RM marker T ) T ) POR Clk Clk BR_Range = BR_Range0 3310 11479 1624 × T 5632 × T µs Clk Clk Programmin BR_Range1 2242 11479 1100 × T 5632 × T µs 4.2 t1 Clk Clk A g start pulse BR_Range2 1708 11479 838 × T 5632 × T µs Clk Clk BR_Range3 1441 11479 707 × T 5632 × T µs Clk Clk after POR 16175 7936 × T µs Clk Programmin 385.5 × 4.3 g delay t2 783 785 384.5 × T µs A Clk T period Clk Synchroniza 4.4 - t3 261 261 128 × T 128 × T µs A Clk Clk tion pulse Delay until of the program 4.5 t4 129 129 63.5 × T 63.5 × T µs A window Clk Clk starts Programmin 4.6 t5 522 522 256 × T 256 × T µs A g window Clk Clk Time frame 4.7 t6 1044 1044 512 × T 512 × T µs A ofa bit Clk Clk Programmin 4.8 t7 130.5 522 64 × T 256 × T µs C g pulse Clk Clk Equivalent acknowledg 4.9 t8 261 261 128 × T 128 × T µs A e pulse: Clk Clk E_Ack Equivalent 4.10 t9 526 526 258 × T 258 × T µs A time window Clk Clk OFF-bit 449.5 × 4.11 programmin t10 916 916 449.5 × T µs A Clk T g window Clk 5 Data Clock (see Figure 9-1 and Figure 9-6) Minimum BR_Range = delay time BR_Range0 0 16.3057 0 1 × T µs XClk between BR_Range1 0 8.1528 0 1 × T µs 5.1 t XClk C edge at BR_Range2 Delay2 0 4.0764 0 1 × T µs XClk DATA and BR_Range3 0 2.0382 0 1 × T µs XClk DATA_CLK BR_Range = Pulse width BR_Range0 65.2 65.2 4 × T 4 × T µs of negative XClk XClk 5.2 BR_Range1 t 32.6 32.6 4 × T 4 × T µs A pulse at pin P_DATA_CLK XClk XClk BR_Range2 16.3 16.3 4 × T 4 × T µs DATA_CLK XClk XClk BR_Range3 8.15 8.15 4 × T 4 × T µs XClk XClk *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 34 ATA8203/ATA8204/ATA8205 [DATASHEET] 9121D–INDCO–09/14

18. Electrical Characteristics Atmel ATA8204, ATA8205 All parameters refer to GND, T = 25°C, V = 5V, f = 433.92MHz and f = 868.3MHz unlessotherwise specified. amb S 0 0 f = 433.92MHz f = 868.3MHz, RF RF 13.52875MHz Oscillator 13.55234MHz Oscillator VariableOscillator Test No. Parameter Conditions Symbol Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit Type* 6 Basic Clock Cycle of the Digital Circuitry Basic clock 6.1 T 2.0696 2.0696 2.066 2.066 28/f 28/f µs A cycle Clk XTO XTO BR_Range0 16.557 16.557 16.528 16.528 8 × T 8 × T µs Extended Clk Clk BR_Range1 8.278 8.278 8.264 8.264 4 × T 4 × T µs 6.2 basic clock T Clk Clk A BR_Range2 XClk 4.139 4.139 4.132 4.132 2 × T 2 × T µs cycle Clk Clk BR_Range3 2.069 2.069 2.066 2.066 1 × T 1 × T µs Clk Clk 7 Polling Mode Sleep time Sleep and (see Sleep × Sleep × Sleep × Sleep × XSleep are Sleep × Sleep × Figure 8-1, X × X × X × X × 7.1 defined in the T Sleep Sleep Sleep Sleep X × X × ms A Figure 8-10 Sleep 1024 × 1024 × 1024 × 1024 × Sleep Sleep OPMODE 1024 × T 1024 × T and 2.0696 2.0696 2.066 2.066 Clk Clk register Figure 13-1) BR_Range0 1855 1855 1852 1852 896.5 896.5 µs Start-up time BR_Range1 1060 1060 1058 1058 512.5 512.5 µs (see Figure 7.2 BR_Range2 T 1060 1060 1058 1058 512.5 512.5 µs A 8-1 and Startup BR_Range3 663 663 662 662 320.5 320.5 µs Figure 8-4) × T × T µs Clk Clk Average bit- check time while polling, no RF applied (see Figure 8- Time for bit 8 on page 15 7.3 check (see T C and Figure 8-9 Bit-check Figure 8-1 on page 16) BR_Range0 0.45 0.45 0.45 ms BR_Range1 0.24 0.24 0.24 ms BR_Range2 0.14 0.14 0.14 ms BR_Range3 0.08 0.08 0.08 ms Bit-check time for a valid input signal f Sig Time for bit (see Figure 8- 7.4 check (see 5 on page 14) T C Bit-check Figure 8-1 N = 0 1 × T 1 × T 1 × T 1 × T 1 × T 1 × T ms Bit-check XClk XClk XClk XClk XClk Clk N = 3 3/f 3.5/f 3/f 3.5/f 3/f 3.5/f ms Bit-check Sig Sig Sig Sig Sig Sig N = 6 6/f 6.5/f 6/f 6.5/f 6/f 6.5/f ms Bit-check Sig Sig Sig Sig Sig Sig N = 9 9/f 9.5/f 9/f 9.5/f 9/f 9.5/f ms Bit-check Sig Sig Sig Sig Sig Sig 8 Receiving Mode f =f /438 for the 433.92MHz IF LO Intermediate band (ATA8204) 8.1 f 987 947.9 kHz A frequency IF f =f /915 for the 868.3MHz band IF LO (ATA8205) BR_Range0 1.0 1.8 1.0 1.8 BR_Range0 × 2 µs/T Kbit/s Clk Baud-rate BR_Range1 BR_Rang 1.8 3.2 1.8 3.2 BR_Range1 × 2 µs/T Kbit/s 8.2 Clk A range BR_Range2 e 3.2 5.6 3.2 5.6 BR_Range2 × 2 µs/T Kbit/s Clk BR_Range3 5.6 10.0 5.6 10.0 BR_Range3 × 2 µs/T Kbit/s Clk *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter ATA8203/ATA8204/ATA8205 [DATASHEET] 35 9121D–INDCO–09/14

18. Electrical Characteristics Atmel ATA8204, ATA8205 (Continued) All parameters refer to GND, T = 25°C, V = 5V, f = 433.92MHz and f = 868.3MHz unlessotherwise specified. amb S 0 0 f = 433.92MHz f = 868.3MHz, RF RF 13.52875MHz Oscillator 13.55234MHz Oscillator VariableOscillator Test No. Parameter Conditions Symbol Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit Type* Minimum time period between BR_Range = edges at pin DATA BR_Range0 165.5 165.5 165.3 165.3 10 × T 10 × T µs XClk XClk (see Figure BR_Range1 82.8 82.8 82.6 82.6 10 × T 10 × T µs XClk XClk 8.3 4-2 and BR_Range2 t 41.4 41.4 41.3 41.3 10 × T 10 × T µs A DATA_min XClk XClk Figure 8-8, BR_Range3 20.7 20.7 20.6 20.6 10 × T 10 × T µs XClk XClk Figure 8-9) (With the exception of parameter T ) Pulse Maximum BR_Range = Low period BR_Range0 2152 2152 2148 2148 130 × T 130 × T µs XClk XClk 8.4 at pin DATA BR_Range1 t 1076 1076 1074 1074 130 × T 130 × T µs A DATA_L_max XClk XClk (see BR_Range2 538 538 537 537 130 × T 130 × T µs XClk XClk Figure 4-2) BR_Range3 269 269 268.5 268.5 130 × T 130 × T µs XClk XClk Delay to activate the 8.5 start-up Ton1 19.6 21.7 19.6 21.7 9.5 × T 10.5 × T µs A Clk Clk mode (see Figure 8-12) OFF command at pin 8.6 Ton2 16.5 16.5 8 × T µs A POLLING/ Clk _ON (see Figure 8-11) Delay to activate the 8.7 sleep mode Ton3 17.6 19.6 17.6 19.6 8.5 × T 9.5 × T µs A Clk Clk (see Figure 8-11) Pulse on pin DATA at the BR_Range = end of a data BR_Range0 16.557 16.557 16.528 16.528 8 × T 8 × T µs 8.8 T Clk Clk C stream BR_Range1 Pulse 8.278 8.278 8.264 8.264 4 × T 4 × T µs Clk Clk (see BR_Range2 4.139 4.139 4.132 4.132 2 × T 2 × T µs Clk Clk Figure 10-3) BR_Range3 2.069 2.069 2.066 2.066 1 × T 1 × T µs Clk Clk *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 36 ATA8203/ATA8204/ATA8205 [DATASHEET] 9121D–INDCO–09/14

18. Electrical Characteristics Atmel ATA8204, ATA8205 (Continued) All parameters refer to GND, T = 25°C, V = 5V, f = 433.92MHz and f = 868.3MHz unlessotherwise specified. amb S 0 0 f = 433.92MHz f = 868.3MHz, RF RF 13.52875MHz Oscillator 13.55234MHz Oscillator VariableOscillator Test No. Parameter Conditions Symbol Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit Type* 9 Configuration of the Receiver (see Figure 12-1 and Figure 13-1) Frequency is Frequency of 1/ 1/ stable within 9.1 the reset f 117.9 117.9 118.2 118.2 (4096 × (4096 × Hz A 50ms after RM marker T ) T ) POR Clk Clk BR_Range = BR_Range0 3361 11656 3355 11636 1624 × T 5632 × T µs Program- Clk Clk BR_Range1 2276 11656 2272 11636 1100 × T 5632 × T µs 9.2 ming start t1 Clk Clk A BR_Range2 1734 11656 1731 11636 838 × T 5632 × T µs pulse Clk Clk BR_Range3 1463 11656 1460 11636 707 × T 5632 × T µs Clk Clk after POR 16425 7936 × T µs Clk Programmin 385.5 × 9.3 g delay t2 796 798 794 796 384.5 × T µs A Clk T period Clk Synchroniza- 9.4 t3 265 265 264 264 128 × T 128 × T µs A tion pulse Clk Clk Delay until of the program 9.5 t4 131 131 131 131 63.5 × T 63.5 × T µs A window Clk Clk starts Programmin 9.6 t5 530 530 529 529 256 × T 256 × T µs A g window Clk Clk Time frame 9.7 t6 1060 1060 1058 1058 512 × T 512 × T µs A ofa bit Clk Clk Programmin 9.8 t7 132 530 132 529 64 × T 256 × T µs C g pulse Clk Clk Equivalent 9.9 acknowledge t8 265 265 264 264 128 × T 128 × T µs A Clk Clk pulse: E_Ack Equivalent 9.10 t9 534 534 533 533 258 × T 258 × T µs A time window Clk Clk OFF-bit 449.5 × 9.11 programmin t10 930 930 929 929 449.5 × T µs A Clk T g window Clk 10 Data Clock (see Figure 9-1 and Figure 9-6) Minimum BR_Range = delay time BR_Range0 0 16.557 0 16.528 0 1 × T µs XClk between BR_Range1 0 8.278 0 8.264 0 1 × T µs 10.1 t XClk C edge at BR_Range2 Delay2 0 4.139 0 4.132 0 1 × T µs XClk DATA and BR_Range3 0 2.069 0 2.066 0 1 × T µs XClk DATA_CLK BR_Range = Pulse width BR_Range0 66.2 62.2 66.1 66.1 4 × T 4 × T µs of negative XClk XClk 10.2 BR_Range1 t 33.1 33.1 33.0 33.0 4 × T 4 × T µs A pulse at pin P_DATA_CLK XClk XClk BR_Range2 16.5 16.5 16.5 16.5 4 × T 4 × T µs DATA_CLK XClk XClk BR_Range3 8.3 8.3 8.25 8.25 4 × T 4 × T µs XClk XClk *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter ATA8203/ATA8204/ATA8205 [DATASHEET] 37 9121D–INDCO–09/14

19. Electrical Characteristics Atmel ATA8203, ATA8204, ATA8205 All parameters refer to GND, T = 25°C, V = 5V, f = 868.3MHz, f = 433.92MHz and f =315MHz, unlessotherwise specified. amb S 0 0 0 No. Parameters Test Conditions Symbol Min. Typ. Max. Unit Type* 11 Current Consumption Sleep mode IS 170 290 µA A (XTO and polling logic active) off IC active (start-up-, bit-check-, 11.1 Current consumption receiving mode) PinDATA=H IS A FSK on 8.5 11.0 mA ASK 8.0 10.4 mA 12 LNA, Mixer, Polyphase Low-pass and IF Amplifier (Input Matched According to Figure 14-1 on page 30 Referred to RFIN) LNA/mixer/IF amplifier 868MHz –18 12.1 Third-order intercept point IIP3 dBm C 433MHz –23 315MHz –24 12.2 LO spurious emission Required according to I-ETS300220 IS –70 –57 dBm A LORF 12.3 System noise figure With power matching |S11| < –10dB NF 5 dB B At 868.3MHz (14.15 – Ω j73.53) (19.3 – 12.4 LNA_IN input impedance AT 433.92MHz Zi Ω C LNA_IN j113.3) (26.97 – At 315MHz j158.7) Ω At 868.3MHz –27.7 12.5 1dB compression point AT 433.92MHz IP –32.7 dBm C 1db At 315MHz –33.7 12.6 Image rejection Within the complete image band 20 30 dB A BER ≤ 10-3, 12.7 Maximum input level FSK mode P –10 dBm C in_max ASK mode –10 dBm 13 Local Oscillator ATA8205 868 870 MHz Operating frequency range 13.1 ATA8204 f 431.5 436.5 MHz A VCO VCO ATA8203 312.5 317.5 MHz f = 868.3MHz at 10MHz –140 –130 osc 13.2 Phase noise local oscillator f = 433.92MHz at 10MHz L (fm) –143 –133 dBC/Hz B osc f = 315MHz at 10MHz –143 –133 osc 13.3 Spurious of the VCO At ±f –55 –45 dBC B XTO XTO pulling, appropriate load capacitance must be connected to XTAL, crystal CL1 13.4 XTO pulling and CL2 B f = 14.71875MHz (315MHz band) XTAL f = 13.52875MHz (433MHz band) f –10ppm f +10ppm MHz XTAL XTO XTAL f = 13.55234MHz (868MHz band) XTAL Series resonance resistor of 13.5 Parameter of the supplied crystal R 120 Ω B the crystal S *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 38 ATA8203/ATA8204/ATA8205 [DATASHEET] 9121D–INDCO–09/14

19. Electrical Characteristics Atmel ATA8203, ATA8204, ATA8205 (Continued) All parameters refer to GND, T = 25°C, V = 5V, f = 868.3MHz, f = 433.92MHz and f =315MHz, unlessotherwise specified. amb S 0 0 0 No. Parameters Test Conditions Symbol Min. Typ. Max. Unit Type* Static capacitance at pin Parameter of the supplied crystal and 13.6 C –5% 18 +5% pF B XTAL1 to GND board parasitics L1 Static capacitance at pin Parameter of the supplied crystal and 13.7 C –5% 18 +5% pF B XTAL2 to GND board parasitics L2 C < 1.8pF, C = 9pF 0 L 1.5 kΩ B f = 14.71875MHz Crystal series resistor Rm at XTAL 13.8 C < 2.0pF, C = 9pF start-up 0 L f = 13.52875MHz 1.5 kΩ B XTAL f = 13.55234MHz XTAL 14 Analog Signal Processing (Input Matched According to Figure 14-1 on page 30 Referred to RFIN) ASK (level of carrier) BER ≤ 10-3, 100% Mod f = 315MHz/433.92MHz in V = 5V, T = 25°C S amb Input sensitivity ASK f = 987kHz IF 14.1 300 kHz IF Filter P BR_Range0 Ref_ASK –111 –113 –115 dBm B (ATA8203/ATA8204) BR_Range1 –109.5 –111.5 –113.5 dBm B BR_Range2 –109 –111 –113 dBm B BR_Range3 –107 –109 –111 dBm B ASK (level of carrier) BER ≤ 10-3, 100% Mod f = 868.3MHz in V = 5V, T = 25°C S amb Input sensitivity ASK f = 948kHz IF 14.2 600 kHz IF Filter P BR_Range0 Ref_ASK –109 –111 –113 dBm B (ATA8205) BR_Range1 –107.5 –109.5 –111.5 dBm B BR_Range2 –107 –109 –111 dBm B BR_Range3 –105 –107 –109 dBm B Sensitivity variation ASK for the full operating range 300kHz and 600kHz compared to T =25°C, 14.3 amb f = 315MHz/433.92MHz/868.3MHz Δ P +2.5 –1.5 dB B V =5V in Ref S P = P + Δ P (ATA8203/ATA8204/ATA8205 ASK Ref_ASK Ref ) 300kHz version (ATA8203/ATA8204) f = 315MHz/433.92MHz in f = 987kHz Δ P +7.5 –1.5 dB B IF Ref f = –110kHz to +110kHz +9.5 –1.5 dB Sensitivity variation ASK for IF f = –140kHz to +140kHz 14.4 fIuFl lf ioltpeer rcaotimngp arraendg eto i ncluding PIFASK = PRef_ASK + Δ PRef 600kHz version (ATA8205) T =25°C, V = 5V amb S f = 868.3MHz in f = 948kHz IF Δ P +6.5 –1.5 dB B f = –210kHz to +210kHz Ref IF +8.5 –1.5 dB f = –270kHz to +270kHz IF P = P + Δ P ASK Ref_ASK Ref *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter ATA8203/ATA8204/ATA8205 [DATASHEET] 39 9121D–INDCO–09/14

19. Electrical Characteristics Atmel ATA8203, ATA8204, ATA8205 (Continued) All parameters refer to GND, T = 25°C, V = 5V, f = 868.3MHz, f = 433.92MHz and f =315MHz, unlessotherwise specified. amb S 0 0 0 No. Parameters Test Conditions Symbol Min. Typ. Max. Unit Type* BER ≤ 10-3 f = 315MHz/433.92MHz in V = 5V, T = 25°C S amb f = 987kHz IF BR_Range0 df = ±16kHz P –104 –107 –108.5 dBm B Ref_FSK df = ±10kHz to ±30kHz –102 –108.5 dBm Input sensitivity FSK BR_Range1 14.5 300kHz IF filter df = ±16kHz P –102 –105 –106.5 dBm B (ATA8203/ATA8204) Ref_FSK df = ±10kHz to ±30kHz –100 –106.5 dBm BR_Range2 df = ±16kHz P –100.5 –103.5 –105 dBm B Ref_FSK df = ±10kHz to ±30kHz –98.5 –105 dBm BR_Range3 df = ±16kHz P –98.5 –101.5 –103 dBm B Ref_FSK df = ±10kHz to ±30kHz –96.5 –103 dBm BER ≤ 10-3 f = 868.3MHz in V = 5V, T = 25°C S amb f = 948kHz IF BR_Range0 df = ±16kHz to ±28kHz P –102 –105 –106.5 dBm B Ref_FSK df = ±10kHz to ±100kHz –100 –106.5 dBm Input sensitivity FSK BR_Range1 14.6 600kHz IF filter df = ±16kHz ±28kHz P –100 –103 –104.5 dBm B (ATA8205) Ref_FSK df = ±10kHz to ±100kHz –98 –104.5 dBm BR_Range2 df = ±18kHz ±31kHz P –98.5 –101.5 –103 dBm B Ref_FSK df = ±13kHz to ±100kHz –96.5 –103 dBm BR_Range3 df = ±25kHz ±44kHz P –96.5 –99.5 –101 dBm B Ref_FSK df = ±20kHz to ±100kHz –94.5 –101 dBm Sensitivity variation FSK for the full operating range 300kHz and 600kHz versions compared to T =25°C, 14.7 amb f = 315MHz/433.92MHz/868.3MHz Δ P +3 –1.5 dB B V =5V in Ref S P = P + Δ P (ATA8203/ATA8204/ATA8205 FSK Ref_FSK Ref ) *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 40 ATA8203/ATA8204/ATA8205 [DATASHEET] 9121D–INDCO–09/14

19. Electrical Characteristics Atmel ATA8203, ATA8204, ATA8205 (Continued) All parameters refer to GND, T = 25°C, V = 5V, f = 868.3MHz, f = 433.92MHz and f =315MHz, unlessotherwise specified. amb S 0 0 0 No. Parameters Test Conditions Symbol Min. Typ. Max. Unit Type* 300kHz version (ATA8203/ATA8204) f = 315MHz/433.92MHz in f = 987kHz IF +8 –2 dB f = –110kHz to +110kHz Δ P B IF Ref +10 –2 dB f = –140kHz to +140kHz Sensitivity variation FSK for IF +13 –2 dB f = –180kHz to +180kHz the full operating range PIF = P + Δ P 14.8 including IF filter compared to FSK Ref_FSK Ref 600kHz version (ATA8205) T = 25°C, amb f = 868.3MHz V = 5V in S f = 948kHz IF +7 –2 dB f = –150kHz to +150kHz Δ P B IF Ref +9 –2 dB f = –200kHz to +200kHz IF +12 –2 dB f = –260kHz to +150kHz IF P = P + Δ P FSK Ref_FSK Ref S/N ratio to suppress in-band noise signals. Noise signals ASK mode SNR 10 12 dB 14.9 ASK C may have any modulation FSK mode SNR 2 3 dB FSK scheme Dynamic range RSSI 14.10 Δ R 60 dB A amplifier RSSI 14.11RSSI output voltage range V 1 3.5 V A RSSI 14.12RSSI gain G 20 mV/dB A RSSI 1 f = ---------------------------------------------------------- Lower cut-off frequency of the cu_DF 2×π×30 kΩ ×CDEM 14.13 fcu_DF 0.11 0.16 0.20 kHz B data filter CDEM = 33nF BR_Range0 (default) 39 nF Recommended CDEM for BR_Range1 22 nF 14.14 CDEM C best performance BR_Range2 12 nF BR_Range3 8.2 nF BR_Range0 (default) 270 1000 ms Edge-to-edge time period of BR_Range1 156 560 ms 14.15the input data signal for full t C BR_Range2 ee_sig 89 320 ms sensitivity BR_Range3 50 180 ms Upper cut-off frequency programmable in 4 ranges usingaserial mode word Upper cut-off frequency data 14.16 BR_Range0 (default) 2.8 3.4 4.0 kHz B filter BR_Range1 fu 4.8 6.0 7.2 kHz BR_Range2 8.0 10.0 12.0 kHz BR_Range3 15.0 19.0 23.0 kHz 300kHz version (ATA8203/ATA8204) R connected from pin SENS Sense dBm to V , input matched according to S (peak Figure 14-1 “Application Circuit, level) 14.17Reduced sensitivity f =315MHz/433.92MHz, in V = 5V, T = +25°C S amb R = 56kΩ P –71 –79 –86 dBm B Sense Ref_Red R = 100kΩ P –80 –88 –96 dBm B Sense Ref_Red *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter ATA8203/ATA8204/ATA8205 [DATASHEET] 41 9121D–INDCO–09/14

19. Electrical Characteristics Atmel ATA8203, ATA8204, ATA8205 (Continued) All parameters refer to GND, T = 25°C, V = 5V, f = 868.3MHz, f = 433.92MHz and f =315MHz, unlessotherwise specified. amb S 0 0 0 No. Parameters Test Conditions Symbol Min. Typ. Max. Unit Type* 600kHz version (ATA8205) R connected from pin SENS Sense dBm to V , input matched according to S (peak Figure 14-1 “Application Circuit, level) 14.18Reduced sensitivity f =868.3MHz, in V = 5V, T = +25°C S amb R = 56kΩ P –60 –68 –76 dBm B Sense Ref_Red R = 100kΩ P –69 –77 –85 dBm B Sense Ref_Red R = 56kΩ 5 0 0 dB Reduced sensitivity variation Sense 14.19 R = 100kΩ Δ P 5 0 0 dB C over full operating range Sense Red P = P + Δ P Red Ref_Red Red Values relative to R = 56kΩ Sense R = 56kΩ 0 dB Reduced sensitivity variation Sense 14.20 R = 68kΩ Δ P –3.5 dB C for different values of R Sense Red Sense R = 82kΩ –6.0 dB Sense R = 100kΩ –9.0 dB Sense 14.21Threshold voltage for reset V 1.95 2.8 3.75 V A ThRESET 15 Digital Ports Data output - Saturation voltage Low I ≤ 12mA V 0.35 0.8 V ol ol I = 2mA V 0.08 0.3 V ol ol - max voltage at pin DATA V 20 V oh - quiescent current V = 20V I 20 µA oh qu 15.1 - short-circuit current V = 0.8V to 20V I 13 30 45 mA A ol ol_lim - ambient temp. in case of V = 0V to 20V t 85 °C oh amb_sc permanent short-circuit Data input - Input voltage Low V 0.35 × V Il - Input voltage High V 0.65 × V V V ich S S DATA_CLK output 0.1 15.2 - Saturation voltage Low IDATA_CLK = 1mA V 0.4 V A ol V – - Saturation voltage High IDATA_CLK = –1mA V V – 0.4V S V oh S 0.15V IC_ACTIVE output 0.1 15.3 - Saturation voltage Low IIC_ACTIVE = 1mA V 0.4 V A ol V – 0.4 V – - Saturation voltage High IIC_ACTIVE = –1mA V S S V oh V 0.15V POLLING/_ON input 15.4 - Low level input voltage Receiving mode V 0.2 × V V A Il S - High level input voltage Polling mode V 0.8 × V V Ih S MODE pin 15.5 Test input must always be set to High A - High level input voltage V 0.8 × V V Ih S TEST 1 pin 15.6 Test input must always be set to Low A - Low level input voltage V 0.2 × V V Il S *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 42 ATA8203/ATA8204/ATA8205 [DATASHEET] 9121D–INDCO–09/14

20. Ordering Information Extended Type Number Package Remarks ATA8203P3C-TKQW SSO20 315MHz version, MOQ 4000 ATA8204P3C-TKQW SSO20 433MHz version, MOQ 4000 ATA8205P6C-TKQW SSO20 868MHz version, MOQ 4000 21. Package Information D E1 L 1 2 A C b A A E e 20 11 technical drawings according to DIN specifications Dimensions in mm 1 10 COMMON DIMENSIONS (Unit of Measure = mm) Symbol MIN NOM MAX NOTE A 0.9 1.0 1.1 A1 0.05 0.1 0.15 A2 0.85 0.9 0.95 D 6.4 6.5 6.6 E 6.3 6.4 6.5 E1 4.3 4.4 4.5 L 0.5 0.6 0.7 C 0.1 0.15 0.2 b 0.2 0.25 0.3 e 0.65 BSC 04/16/14 TITLE GPC DRAWING NO. REV. Package Drawing Contact: Package: SSO20 packagedrawings@atmel.com 4.4mm 6.543-5182.01-4 1 ATA8203/ATA8204/ATA8205 [DATASHEET] 43 9121D–INDCO–09/14

22. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. History • Section 20 “Ordering Information” on page 44 updated 9121D-INDCO-09/14 • Section 21 “Package Information” on page 44 updated 9121C-INDCO-12/12 • Section 20 “Ordering Information” on page 43 changed 9121B-INDCO-04/09 • Figure 1-1 “System Block Diagram” on page 2 changed 44 ATA8203/ATA8204/ATA8205 [DATASHEET] 9121D–INDCO–09/14

X X X X X X Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com © 2014 Atmel Corporation. / Rev.: Rev.: 9121D–INDCO–09/14 Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities®, and others are registered trademarks or trademarks of Atmel Corporation in U.S. and other countries. Other terms and product names may be trademarks of others. DISCLAIMER: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS AND PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and products descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. SAFETY-CRITICAL, MILITARY, AND AUTOMOTIVE APPLICATIONS DISCLAIMER: Atmel products are not designed for and will not be used in connection with any applications where the failure of such products would reasonably be expected to result in significant personal injury or death (“Safety-Critical Applications”) without an Atmel officer's specific written consent. Safety-Critical Applications include, without limitation, life support devices and systems, equipment or systems for the operation of nuclear facilities and weapons systems. Atmel products are not designed nor intended for use in military or aerospace applications or environments unless specifically designated by Atmel as military-grade. Atmel products are not designed nor intended for use in automotive applications unless specifically designated by Atmel as automotive-grade.

Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: M icrochip: ATA8203P3C-TKQY ATA8204P3C-TKQY ATA8205P6C-TKQY ATA8204P3C-TKQW ATA8205P6C-TKQW ATA8203P3C-TKQW