AT93C56B and AT93C66B 3-wire Serial EEPROM 2K (256 x 8 or 128 x 16) and 4K (512 x 8 or 256 x 16) DATASHEET Features  Low-voltage Operation ̶ V = 1.7V to 5.5V CC  User-selectable Internal Organization ̶ 2K: 256 x 8 or 128 x 16 ̶ 4K: 512 x 8 or 256 x 16  3-wire Serial Interface  Sequential Read Operation  2MHz Clock Rate (5V)  Self-timed Write Cycle (5ms Max)  High Reliability ̶ Endurance: 1,000,000 Write Cycles ̶ Data Retention: 100 Years  8-lead JEDEC SOIC, 8-lead TSSOP, 8-pad UDFN, 8-pad XDFN, and 8-ball VFBGA packages Description The Atmel® AT93C56B/66B provides 2,048/4,096 bits of Serial Electrically Erasable Programmable Read-Only Memory (EEPROM) organized as 128/256 words of 16 bits each (when the ORG pin is connected to V ) and 256/512 words CC of 8 bits each (when the ORG pin is tied to ground). The device is optimized for use in many industrial and commercial applications where low-power and low- voltage operations are essential. The AT93C56B/66B is available in space-saving 8-lead JEDEC SOIC, 8-lead TSSOP, 8-pad UDFN, 8-pad XDFN, and 8-ball VFBGA packages. The AT93C56B/66B is enabled through the Chip Select pin (CS) and accessed via a 3-wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock (SK). Upon receiving a Read instruction at DI, the address is decoded, and the data is clocked out serially on the DO pin. The write cycle is completely self-timed, and no separate erase cycle is required before Write. The write cycle is only enabled when the part is in the Erase/Write Enable state. When CS is brought high following the initiation of a write cycle, the DO pin outputs the Ready/Busy status of the part. The AT93C56B/66B operates from 1.7V to 5.5V. Atmel-8735C-SEEPROM-AT93C56B-66B-Datasheet_012015

1. Pin Configurations and Pinouts Table 1-1. Pin Configurations 8-lead SOIC 8-lead TSSOP Pin Name Function CS Chip Select CS 1 8 VCC CS 1 8 VCC SK 2 7 NC SK 2 7 NC SK Serial Data Clock DI 3 6 ORG DI 3 6 ORG DO 4 5 GND DI Serial Data Input DO 4 5 GND Top View DO Serial Data Output Top View GND Ground V Power Supply CC 8-pad UDFN/XDFN 8-ball VFBGA ORG Internal Organization VCC 8 1 CS VCC 8 1 CS NC No Connect NC 7 2 SK NC 7 2 SK ORG 6 3 DI ORG 6 3 DI GND 5 4 DO GND 5 4 DO Bottom View Bottom View Note: Drawings are not to scale. 2. Absolute Maximum Ratings* Operating Temperature55C to +125C *Notice: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage Storage Temperature65C to +150C to the device. This is a stress rating only, and functional operation of the device at these or any Voltage on any pin other conditions beyond those indicated in the with respect to ground1.0V to +7.0V operational sections of this specification is not implied. Exposure to absolute maximum rating Maximum Operating Voltage . . . . . . . . . . . . . . . 6.25V conditions for extended periods may affect device DC Output Current. . . . . . . . . . . . . . . . . . . . . . .5.0mA reliability. 2 AT93C56B/66B [DATASHEET] Atmel-8735C-SEEPROM-AT93C56B-66B-Datasheet_012015

3. Block Diagram V GND CC Memory Array Address 256/512 x 8 ORG Decoder or 128/256 x 16 Data Register DI Output Buffer Mode Decode Logic CS Clock SK DO Generator Note: When the ORG pin is connected to V , the x16 organization is selected. When it is connected to ground, CC the x8 organization is selected. If the ORG pin is left unconnected, and the application does not load the input beyond the capability of the internal 1M pull-up resistor, then the x16 organization is selected. AT93C56B/66B [DATASHEET] 3 Atmel-8735C-SEEPROM-AT93C56B-66B-Datasheet_012015

4. Memory Organization 4.1 Pin Capacitance(1) Applicable over recommended operating range from T = 25C, f = 1.0MHz, V = 5.0V (unless otherwise noted). A CC Symbol Test Conditions Max Units Conditions C Output Capacitance (DO) 5 pF V = 0V OUT OUT C Input Capacitance (CS, SK, DI) 5 pF V = 0V IN IN Note: 1. This parameter is characterized, and is not 100% tested. 4.2 DC Characteristics Applicable over recommended operating range from T = -40°C to +85°C, V = 1.7V to 5.5V (unless otherwise noted). AI CC Symbol Parameter Test Condition Min Typ Max Unit V Supply Voltage 1.7 5.5 V CC1 V Supply Voltage 2.5 5.5 V CC2 V Supply Voltage 4.5 5.5 V CC3 Read at 1.0MHz 0.5 2.0 mA I Supply Current V = 5.0V CC CC Write at 1.0MHz 0.5 2.0 mA I Standby Current V = 1.7V CS = 0V 0.4 1.0 μA SB1 CC I Standby Current V = 2.5V CS = 0V 6.0 10.0 μA SB2 CC I Standby Current V = 5.0V CS = 0V 10.0 15.0 μA SB3 CC I Input Leakage V = 0V to V 0.1 3.0 μA IL IN CC I Output Leakage V = 0V to V 0.1 3.0 μA OL IN CC V (1) Input Low Voltage 2.5V V  5.5V 0.6 0.8 V IL1 CC V (1) Input High Voltage 2.5V V  5.5V 2.0 V + 1 V IH1 CC CC V (1) Input Low Voltage 1.7V  V  2.5V 0.6 V x 0.3 V IL2 CC CC V (1) Input High Voltage 1.7V  V  2.5V V x 0.7 V + 1 V IH2 CC CC CC V Output Low Voltage 2.5V  V  5.5V I = 2.1mA 0.4 V OL1 CC OL V Output High Voltage 2.5V  V  5.5V I = 0.4mA 2.4 V OH1 CC OH V Output Low Voltage 1.7V  V  2.5V I = 0.15mA 0.2 V OL2 CC OL V Output High Voltage 1.7V  V  2.5V I = 100μA V  0.2 V OH2 CC OH CC Note: 1. V min and V max are reference only, and are not tested. IL IH 4 AT93C56B/66B [DATASHEET] Atmel-8735C-SEEPROM-AT93C56B-66B-Datasheet_012015

4.3 AC Characteristics Applicable over recommended operating range from T = -40°C to + 85°C, V = as specified, CL = 1 TTL gate and 100pF AI CC (unless otherwise noted). Symbol Parameter Test Condition Min Max Units 4.5V  V  5.5V 0 2 MHz CC f SK Clock Frequency 2.5V  V  5.5V 0 1 MHz SK CC 1.7V  V  5.5V 0 250 kHz CC 2.5V  V  5.5V 250 ns CC t SK High Time SKH 1.7V  V  5.5V 1000 ns CC 2.5V  V  5.5V 250 ns CC t SK Low Time SKL 1.7V  V  5.5V 1000 ns CC 2.5V  V  5.5V 250 ns CC t Minimum CS Low Time CS 1.7V  V  5.5V 1000 ns CC 2.5V  V  5.5V 50 ns CC t CS Setup Time Relative to SK CSS 1.7V  V  5.5V 200 ns CC 2.5V  V  5.5V 100 ns CC t DI Setup Time Relative to SK DIS 1.7V  V  5.5V 400 ns CC t CS Hold Time Relative to SK 0 ns CSH 2.5V  V  5.5V 100 ns CC t DI Hold Time Relative to SK DIH 1.7V  V  5.5V 400 ns CC 2.5V  V  5.5V 250 ns CC t Output Delay to 1 AC Test PD1 1.7V  V  5.5V 1000 ns CC 2.5V  V  5.5V 250 ns CC t Output Delay to 0 AC Test PD0 1.7V  V  5.5V 1000 ns CC 2.5V  V  5.5V 250 ns CC t CS to Status Valid AC Test SV 1.7V  V  5.5V 1000 ns CC AC Test 2.5V  V  5.5V 150 ns CS to DO in CC t DF High-impedance CS = V 1.7V  V  5.5V 400 ns IL CC t Write Cycle Time 1.7V  V  5.5V 5 ms WP CC Endurance(1) 5.0V, 25°C 1,000,000 Write Cycles Note: 1. This parameter is characterized, and is not 100% tested. AT93C56B/66B [DATASHEET] 5 Atmel-8735C-SEEPROM-AT93C56B-66B-Datasheet_012015

5. Functional Description The AT93C56B/66B is accessed via a simple and versatile 3-wire serial communication interface. Device operation is controlled by seven instructions issued by the Host processor. A valid instruction starts with a rising edge of CS and consists of a Start bit (Logic 1), followed by the appropriate opcode, and the desired memory address location. Table 5-1. AT93C56B/66B Instruction Set Address Data Instruction SB Opcode x8(1) x16(1) x8 x16 Comments Reads data stored in memory at READ 1 10 A – A A – A 8 0 7 0 specified address. Write Enable must precede all EWEN 1 00 11XXXXXXX 11XXXXXX programming modes. ERASE 1 11 A – A A – A Erases memory location A – A . 8 0 7 0 N 0 WRITE 1 01 A – A A – A D – D D – D Writes memory location A – A . 8 0 7 0 7 0 15 0 N 0 Erases all memory locations. ERAL 1 00 10XXXXXXX 10XXXXXX Valid only at V (Section 4.2, “DC CC3 Characteristics” on page 4). Writes all memory locations. WRAL 1 00 01XXXXXXX 01XXXXXX D – D D – D Valid only at V (Section 4.2) and 7 0 15 0 CC3 Disable Register cleared. Disables all programming EWDS 1 00 00XXXXXXX 00XXXXXX instructions. Note: 1. The Xs in the address field represent don’t care values, and must be clocked. READ: The READ instruction contains the address code for the memory location to be read. After the instruction and address are decoded, data from the selected memory location is available at the Serial Output pin, DO. Output data changes are synchronized with the rising edges of the Serial Clock pin, SK. It should be noted that a dummy bit (Logic 0) precedes the 8-bit or 16-bit data output string. The AT93C56B/66B supports sequential Read operations. The device will automatically increment the internal address pointer and clock out the next memory location as long as Chip Select (CS) is held high. In this case, the dummy bit (Logic 0) will not be clocked out between memory locations, thus allowing for a continuous stream of data to be read. Erase/Write Enable (EWEN): To ensure data integrity, the part automatically goes into the Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable (EWEN) instruction must be executed first before any programming instructions can be carried out. Note: Once in the EWEN state, programming remains enabled until an EWDS instruction is executed, or V CC power is removed from the part. 6 AT93C56B/66B [DATASHEET] Atmel-8735C-SEEPROM-AT93C56B-66B-Datasheet_012015

ERASE: The ERASE instruction programs all bits in the specified memory location to the Logic 1 state. The self- timed erase cycle starts once the ERASE instruction and address are decoded. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of t . A Logic 1 at the CS DO pin indicates that the selected memory location has been erased, and the part is ready for another instruction. WRITE: The WRITE instruction contains the 8-bits or 16-bits of data to be written into the specified memory location. The self-timed programming cycle, t , starts after the last bit of data is received at Serial Data Input WP pin DI. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of t . A CS Logic 0 at DO indicates that programming is still in progress. A Logic 1 indicates that the memory location at the specified address has been written with the data pattern contained in the instruction, and the part is ready for further instructions. A Ready/Busy status cannot be obtained if CS is brought high after the end of the self-timed programming cycle, t . WP Erase All (ERAL): The Erase All (ERAL) instruction programs every bit in the Memory Array to the Logic 1 state and is primarily used for testing purposes. The DO pin outputs the ready/busy status of the part if CS is brought high after being kept low for a minimum of t . The ERAL instruction is valid only at V (Section 4.2, “DC CS CC3 Characteristics” on page 4). Write All (WRAL): The Write All (WRAL) instruction programs all memory locations with the data patterns specified in the instruction. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of t . The WRAL instruction is valid only at V (Section 4.2). CS CC3 Erase/Write Disable (EWDS): To protect against accidental data disturbance, the Erase/Write Disable (EWDS) instruction disables all programming modes and should be executed after all programming operations. The operation of the Read instruction is independent of both the EWEN and EWDS instructions and can be executed at any time. AT93C56B/66B [DATASHEET] 7 Atmel-8735C-SEEPROM-AT93C56B-66B-Datasheet_012015

6. Timing Diagrams Figure 6-1. Synchronous Data Timing V IH CS V IL tCSS tSKH tSKL tCSH V IH SK V IL tDIS tDIH V IH DI V IL tPD0 tPD1 tDF V OH DO (Read) V OL tSV tDF V OH DO (Program) Status Valid V OL Table 6-1. Organization Key for Timing Diagrams AT93C56B (2K) AT93C66B (4K) I/O x8 x16 x8 x16 A A (1) A (2) A A N 8 7 8 7 D D D D D N 7 15 7 15 Notes: 1. A is a don’t-care value, but the extra clock is required. 8 2. A is a don’t-care value, but the extra clock is required. 7 Figure 6-2. READ Timing CS tCS SK DI 1 1 0 AN A0 High-impedance DO 0 DN D0 8 AT93C56B/66B [DATASHEET] Atmel-8735C-SEEPROM-AT93C56B-66B-Datasheet_012015

Figure 6-3. EWEN Timing CS tCS SK DI 1 0 0 1 1 ... Figure 6-4. ERASE Timing tCS CS Check Standby Status SK DI 1 1 1 AN AN-1 AN-2 ... A0 tSV tDF High-impedance High-impedance DO Busy Ready tWP Figure 6-5. WRITE Timing CS tCS SK DI 1 0 1 AN ... A0 DN ... D0 High-impedance DO Busy Ready tWP AT93C56B/66B [DATASHEET] 9 Atmel-8735C-SEEPROM-AT93C56B-66B-Datasheet_012015

Figure 6-6. ERAL Timing(1) tCS CCSS Check Standby Status SSKK DDII 1 0 0 1 0 tSV tDF High-impedance High-impedance DDOO Busy Ready tWP Note: 1. Valid only at V (Section 4.2). CC3 Figure 6-7. WRAL Timing(1) tCS CCSS SSKK DDII 1 0 0 0 1 ... DN ... D0 High-impedance DDOO Busy Ready tWP Note: 1. Valid only at V (Section 4.2). CC3 Figure 6-8. EWDS Timing CS tCS SK DI 1 0 0 0 0 ... 10 AT93C56B/66B [DATASHEET] Atmel-8735C-SEEPROM-AT93C56B-66B-Datasheet_012015

7. Ordering Code Detail A T 9 3 C 5 6 B - S S H M - B Atmel Designator Shipping Carrier Option B or Blank = Bulk (Tubes) T = Tape and Reel, Standard Quantity Option E = Tape and Reel, Expanded Quantity Option Product Family 93C = Microwire-compatible 3-Wire Serial EEPROM Operating Voltage M = 1.7V to 5.5V Device Density 56 = 2k Package Device Grade or 66 = 4k Wafer/Die Thickness H = Green, NiPdAu Lead Finish Industrial Temperature Range Device Revision (-40°C to +85°C) U = Green, Matte Sn Lead Finish Industrial Temperature Range (-40°C to +85°C) 11 = 11mil Wafer Thickness Package Option SS = JEDEC SOIC X = TSSOP MA = UDFN ME = XDFN C = VFBGA WWU = Wafer Unsawn AT93C56B/66B [DATASHEET] 11 Atmel-8735C-SEEPROM-AT93C56B-66B-Datasheet_012015

8. Ordering Information Delivery Information Operation Atmel Ordering Code Lead Finish Package Form Quantity Range AT93C56B-SSHM-B Bulk (Tubes) 100 per Tube 8S1 AT93C56B-SSHM-T Tape and Reel 4,000 per Reel AT93C56B-XHM-B Bulk (Tubes) 100 per Tube 8X NiPdAu AT93C56B-XHM-T Tape and Reel 5,000 per Reel (Lead-free/Halogen-free) Industrial AT93C56B-MAHM-T Tape and Reel 5,000 per Reel Temperature 8MA2 (-40C to 85C) AT93C56B-MAHM-E Tape and Reel 15,000 per Reel AT93C56B-MEHM-T 8ME1 Tape and Reel 5,000 per Reel SnAgCu AT93C56B-CUM-T 8U3-1 Tape and Reel 5,000 per Reel (Lead-free/Halogen-free) AT93C56B-WWU11M(1) N/A Wafer Sale Note 1 AT93C66B-SSHM-B Bulk (Tubes) 100 per Tube 8S1 AT93C66B-SSHM-T Tape and Reel 4,000 per Reel AT93C66B-XHM-B Bulk (Tubes) 100 per Tube 8X NiPdAu AT93C66B-XHM-T Tape and Reel 5,000 per Reel (Lead-free/Halogen-free) Industrial AT93C66B-MAHM-T Tape and Reel 5,000 per Reel Temperature 8MA2 (-40C to 85C) AT93C66B-MAHM-E Tape and Reel 15,000 per Reel AT93C66B-MEHM-T 8ME1 Tape and Reel 5,000 per Reel SnAgCu AT93C66B-CUM-T 8U3-1 Tape and Reel 5,000 per Reel (Lead-free/Halogen-free) AT93C66B-WWU11M(1) N/A Wafer Sale Note 1 Note: 1. For wafer sales, please contact Atmel sales. Package Type 8S1 8-lead, 0.150” wide, Plastic Gull Wing, Small Outline (JEDEC SOIC) 8X 8-lead, 0.170” wide, Thin Shrink Small Outline (TSSOP) 8MA2 8-pad, 2.00mm x 3.00mm body, 0.50mm pitch, Ultra Thin Dual No Lead (UDFN) 8ME1 8-pad, 1.80mm x 2.20mm body, Extra Thin Dual No Lead (XDFN) 8U3-1 8-ball, 1.50mm x 2.00mm body, 0.50mm pitch, Small Die Ball Grid Array (VFBGA) 12 AT93C56B/66B [DATASHEET] Atmel-8735C-SEEPROM-AT93C56B-66B-Datasheet_012015

9. Part Markings AT93C56B and AT93C66B: Package Marking Information 8-lead SOIC 8-lead TSSOP 8-pad UDFN 2.0 x 3.0 mm Body ATHYWW ### ATMLHYWW ###% @ ###% @ H%@ AAAAAAAA AAAAAAA YXX 8-pad XDFN 8-ball VFBGA 1.8 x 2.2 mm Body 1.5 x 2.0 mm Body ### ###U YXX YMXX PIN 1 Note 1: designates pin 1 Note 2: Package drawings are not to scale Catalog Number Truncation AT93C56B Truncation Code ###: 56B AT93C66B Truncation Code ###: 66B Date Codes Voltages Y = Year M = Month WW = Work Week of Assembly % = Minimum Voltage 3: 2013 7: 2017 A: January 02: Week 2 M: 1.7V min 4: 2014 8: 2018 B: February 04: Week 4 5: 2015 9: 2019 ... ... 6: 2016 0: 2020 L: December 52: Week 52 Country of Assembly L ot Number Grade/Lead Finish Material @ = Country of Assembly AAA...A = Atmel Wafer Lot Number U: Industrial/Matte Tin/SnAgCu H: Industrial/NiPdAu Trace Code Atmel Truncation XX = Trace Code (Atmel Lot Numbers Correspond to Code) AT: Atmel Example: AA, AB.... YZ, ZZ ATM: Atmel ATML: Atmel 3/22/13 TITLE DRAWING NO. REV. 93C56-66BSM, AT93C56B and AT93C66B Package Marking Package Mark Contact: Information 93C56-66BSM B DL-CSO-Assy_eng@atmel.com AT93C56B/66B [DATASHEET] 13 Atmel-8735C-SEEPROM-AT93C56B-66B-Datasheet_012015

10. Packaging Information 10.1 8S1 — 8-lead JEDEC SOIC C 1 E E1 L N Ø TOP VIEW END VIEW e b A COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A1 A 1.35 – 1.75 A1 0.10 – 0.25 b 0.31 – 0.51 C 0.17 – 0.25 D 4.80 – 5.05 D E1 3.81 – 3.99 E 5.79 – 6.20 SIDE VIEW e 1.27 BSC Notes: This drawing is for general information only. L 0.40 – 1.27 Refer to JEDEC Drawing MS-012, Variation AA ØØ 0° – 8° for proper dimensions, tolerances, datums, etc. 6/22/11 TITLE GPC DRAWING NO. REV. 8S1, 8-lead (0.150” Wide Body), Plastic Gull Wing SWB 8S1 G Package Drawing Contact: Small Outline (JEDEC SOIC) packagedrawings@atmel.com 14 AT93C56B/66B [DATASHEET] Atmel-8735C-SEEPROM-AT93C56B-66B-Datasheet_012015

10.2 8X — 8-lead TSSOP C 1 Pin 1 indicator this corner E1 E L1 N L Top View End View A b A1 COMMON DIMENSIONS e A2 (Unit of Measure = mm) D SYMBOL MIN NOM MAX NOTE Side View A - - 1.20 A1 0.05 - 0.15 Notes: 1. This drawing is for general information only. A2 0.80 1.00 1.05 Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. D 2.90 3.00 3.10 2, 5 2. Dimension D does not include mold Flash, protrusions or gate E 6.40 BSC burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15mm (0.006in) per side. E1 4.30 4.40 4.50 3, 5 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25mm b 0.19 0.25 0.30 4 (0.010in) per side. e 0.65 BSC 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08mm total in excess L 0.45 0.60 0.75 of the b dimension at maximum material condition. Dambar L1 1.00 REF cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07mm. C 0.09 - 0.20 5. Dimension D and E1 to be determined at Datum Plane H. 2/27/14 TITLE GPC DRAWING NO. REV. 8X, 8-lead 4.4mm Body, Plastic Thin Package Drawing Contact: Shrink Small Outline Package (TSSOP) TNR 8X E packagedrawings@atmel.com AT93C56B/66B [DATASHEET] 15 Atmel-8735C-SEEPROM-AT93C56B-66B-Datasheet_012015

10.3 8MA2 — 8-pad UDFN E 1 8 Pin 1 ID 2 7 D 3 6 4 5 TOP VIEW C SIDE VIEW A2 A A1 E2 b (8x) 8 1 COMMON DIMENSIONS 7 2 Pin#1 ID (Unit of Measure = mm) D2 6 3 SYMBOL MIN NOM MAX NOTE A 0.50 0.55 0.60 5 4 A1 0.0 0.02 0.05 e (6x) A2 - - 0.55 L (8x) K D 1.90 2.00 2.10 BOTTOM VIEW D2 1.40 1.50 1.60 Notes: 1. This drawing is for general information only. Refer to E 2.90 3.00 3.10 Drawing MO-229, for proper dimensions, tolerances, E2 1.20 1.30 1.40 datums, etc. 2. The Pin #1 ID is a laser-marked feature on Top View. b 0.18 0.25 0.30 3 3. Dimensions b applies to metallized terminal and is C 1.52 REF measured between 0.15 mm and 0.30 mm from the terminal tip. If the terminal has the optional radius on L 0.30 0.35 0.40 the other end of the terminal, the dimension should e 0.50 BSC not be measured in that radius area. 4. The Pin #1 ID on the Bottom View is an orientation K 0.20 - - feature on the thermal pad. 11/26/14 TITLE GPC DRAWING NO. REV. 8MA2, 8-pad 2 x 3 x 0.6mm Body, Thermally Package Drawing Contact: Enhanced Plastic Ultra Thin Dual Flat No-Lead YNZ 8MA2 G packagedrawings@atmel.com Package (UDFN) 16 AT93C56B/66B [DATASHEET] Atmel-8735C-SEEPROM-AT93C56B-66B-Datasheet_012015

10.4 8ME1 — 8-pad XDFN D 8 7 6 5 PIN #1 ID E 1 2 3 4 A1 Top View A Side View e1 b L COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE 0.10 A – – 0.40 PIN #1 ID A1 0.00 – 0.05 D 1.70 1.80 1.90 0.15 E 2.10 2.20 2.30 b 0.15 0.20 0.25 b e 0.40 TYP e e1 1.20 REF L 0.26 0.30 0.35 End View 9/10/2012 TITLE GPC DRAWING NO. REV. 8ME1, 8-pad (1.80mm x 2.20mm body) DTP 8ME1 B Package Drawing Contact: Extra Thin DFN (XDFN) packagedrawings@atmel.com AT93C56B/66B [DATASHEET] 17 Atmel-8735C-SEEPROM-AT93C56B-66B-Datasheet_012015

10.5 8U3-1 — 8-ball VFBGA E D 2. b PIN 1 BALL PAD CORNER A1 A2 TOP VIEW A SIDE VIEW PIN 1 BALL PAD CORNER 1 2 3 4 d (d1) 8 7 6 5 e COMMON DIMENSIONS (Unit of Measure - mm) (e1) SYMBOL MIN NOM MAX NOTE BOTTOM VIEW A 0.73 0.79 0.85 8 SOLDER BALLS A1 0.09 0.14 0.19 A2 0.40 0.45 0.50 Notes: b 0.20 0.25 0.30 2 1. This drawing is for general information only. D 1.50 BSC E 2.0 BSC 2. Dimension ‘b’ is measured at maximum solder ball diameter. e 0.50 BSC 3. Solder ball composition shall be 95.5Sn-4.0Ag-.5Cu. e1 0.25 REF d 1.00 BSC d1 0.25 REF 6/11/13 TITLE GPC DRAWING NO. REV. 8U3-1, 8-ball, 1.50mm x 2.00mm body, 0.50mm pitch, Package Drawing Contact: Very Thin, Fine-Pitch Ball Grid Array Package (VFBGA) GXU 8U3-1 F packagedrawings@atmel.com 18 AT93C56B/66B [DATASHEET] Atmel-8735C-SEEPROM-AT93C56B-66B-Datasheet_012015

11. Revision History Rev. No. Date Comments Add the UDFN extended quantity option and update package outline drawings. 8735C 01/2015 Update the 8MA2 package drawing. Correct Synchronous Data Timing figure and remove note. Update TSSOP package option from 8A2 to 8X. 8735B 04/2013 Update UDFN package option from 8Y6 to 8MA2. Update template and Atmel logos. 8735A 01/2011 Initial document release. AT93C56B/66B [DATASHEET] 19 Atmel-8735C-SEEPROM-AT93C56B-66B-Datasheet_012015

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