AT93C46D 3-wire Serial EEPROM 1K (128 x 8 or 64 x 16) DATASHEET Features  Low-voltage Operation ̶ V = 1.8V to 5.5V CC  User-selectable Internal Organization ̶ 1K: 128 x 8 or 64 x 16  3-wire Serial Interface  2MHz Clock Rate (5V)  Self-timed Write Cycle (5ms Max)  High Reliability ̶ Endurance: 1,000,000 Write Cycles ̶ Data Retention: 100 Years  8-lead JEDEC SOIC, 8-lead TSSOP, 8-pad UDFN, 8-lead PDIP, and 8-ball VFBGA Packages Description The Atmel® AT93C46D provides 1,024 bits of Serial Electrically Erasable Programmable Read-Only Memory (EEPROM) organized as 64 words of 16 bits each (when the ORG pin is connected to V ) and 128 words of 8 bits each (when CC the ORG pin is tied to ground). The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operations are essential. The AT93C46D is available in space-saving 8-lead JEDEC SOIC, 8-lead TSSOP, 8-pad UDFN, 8-lead PDIP, and 8-ball VFBGA packages. The AT93C46D is enabled through the Chip Select pin (CS) and accessed via a 3-wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock (SK). Upon receiving a Read instruction at DI, the address is decoded, and the data is clocked out serially on the DO pin. The write cycle is completely self-timed, and no separate erase cycle is required before Write. The write cycle is only enabled when the part is in the Erase/Write Enable state. When CS is brought high following the initiation of a write cycle, the DO pin outputs the Ready/Busy status of the part. The AT93C46D operates from 1.8V to 5.5V. Atmel-5193H-SEEPROM-AT93C46D-Datasheet_012015

1. Pin Configurations and Pinouts Table 1-1. Pin Configurations 8-lead SOIC 8-lead TSSOP Pin Name Function (Top View) (Top View) CS Chip Select CS 1 8 VCC CS 1 8 VCC SK Serial Data Clock SK 2 7 NC SK 2 7 NC DI 3 6 ORG DI 3 6 ORG DO 4 5 GND DI Serial Data Input DO 4 5 GND DO Serial Data Output GND Ground 8-pad UDFN 8-lead PDIP (Top View) (Top View) V Power Supply CC ORG Internal Organization CSSK 12 87 VNCCC CS 1 8 VCC DI 3 6 ORG SK 2 7 NC NC No Connect DO 4 5 GND DI 3 6 ORG DO 4 5 GND 8-ball VFBGA (Top View) CS 1 8 VCC SK 2 7 NC DI 3 6 ORG DO 4 5 GND Note: Drawings are not to scale. 2. Absolute Maximum Ratings* Operating Temperature . . . . . . . . . . .-55C to +125C *Notice: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage Storage Temperature. . . . . . . . . . . . .-65C to +150C to the device. This is a stress rating only, and functional operation of the device at these or any Voltage on any pin other conditions beyond those indicated in the with respect to ground . . . . . . . . . . . . . -1.0V to +7.0V operational sections of this specification is not implied. Exposure to absolute maximum rating Maximum Operating Voltage . . . . . . . . . . . . . . . 6.25V conditions for extended periods may affect device DC Output Current. . . . . . . . . . . . . . . . . . . . . . .5.0mA reliability. 2 AT93C46D [DATASHEET] Atmel-5193H-SEEPROM-AT93C46D-Datasheet_012015

3. Block Diagram Figure 3-1. Block Diagram V GND CC Memory Array Address 128 x 8 ORG Decoder or 64 x 16 Data Register DI Output Buffer Mode Decode Logic CS Clock SK DO Generator Notes: 1. When the ORG pin is connected to V , the x16 organization is selected. When it is connected to ground, CC the x8 organization is selected. If the ORG pin is left unconnected and the application does not load the input beyond the capability of the internal 1M pull-up resistor, then the x16 organization is selected. 2. If the x16 organization is the mode of choice and pin 6 (ORG) is left unconnected, Atmel recommends using AT93C46E device. For more details, see the AT93C46E datasheet. AT93C46D [DATASHEET] 3 Atmel-5193H-SEEPROM-AT93C46D-Datasheet_012015

4. Memory Organization 4.1 Pin Capacitance Table 4-1. Pin Capacitance(1) Applicable over recommended operating range from T = 25C, f = 1.0MHz, V = 1.8V (unless otherwise noted). A CC Symbol Test Conditions Max Units Conditions C Output Capacitance (DO) 5 pF V = 0V OUT OUT C Input Capacitance (CS, SK, DI) 5 pF V = 0V IN IN Note: 1. This parameter is characterized, and is not 100% tested. 4.2 DC Characteristics Table 4-2. DC Characteristics Applicable over recommended operating range from T = -40°C to +85°C, V = 1.8V to 5.5V (unless otherwise noted). AI CC Symbol Parameter Test Condition Min Typ Max Unit V Supply Voltage 1.8 5.5 V CC1 V Supply Voltage 2.7 5.5 V CC2 V Supply Voltage 4.5 5.5 V CC3 Read at 1.0MHz 0.5 2.0 mA I Supply Current V = 5.0V CC CC Write at 1.0MHz 0.5 2.0 mA I Standby Current V = 1.8V CS = 0V 0.4 1.0 μA SB1 CC I Standby Current V = 2.7V CS = 0V 6.0 10.0 μA SB2 CC I Standby Current V = 5.0V CS = 0V 10.0 15.0 μA SB3 CC I Input Leakage V = 0V to V 0.1 1.0 μA IL IN CC I Output Leakage V = 0V to V 0.1 1.0 μA OL IN CC V (1) Input Low Voltage 2.7V V  5.5V 0.6 0.8 V IL1 CC V (1) Input High Voltage 2.7V V  5.5V 2.0 V + 1 V IH1 CC CC V (1) Input Low Voltage 1.8V  V  2.7V 0.6 V x 0.3 V IL2 CC CC V (1) Input High Voltage 1.8V  V  2.7V V x 0.7 V + 1 V IH2 CC CC CC V Output Low Voltage 2.7V  V  5.5V I = 2.1mA 0.4 V OL1 CC OL V Output High Voltage 2.7V  V  5.5V I = 0.4mA 2.4 V OH1 CC OH V Output Low Voltage 1.8V  V  2.7V I = 0.15mA 0.2 V OL2 CC OL V Output High Voltage 1.8V  V  2.7V I = 100μA V  0.2 V OH2 CC OH CC Note: 1. V min and V max are reference only, and are not tested. IL IH 4 AT93C46D [DATASHEET] Atmel-5193H-SEEPROM-AT93C46D-Datasheet_012015

4.3 AC Characteristics Table 4-3. AC Characteristics Applicable over recommended operating range from T = 40°C to + 85°C, V = as specified, AI CC CL = 1 TTL gate and 100pF (unless otherwise noted). Symbol Parameter Test Condition Min Typ Max Units 4.5V  V  5.5V 0 2 MHz CC f SK Clock Frequency 2.7V  V  5.5V 0 1 MHz SK CC 1.8V  V  5.5V 0 250 kHz CC 4.5V  V  5.5V 250 ns CC t SK High Time 2.7V  V  5.5V 250 ns SKH CC 1.8V  V  5.5V 1000 ns CC 4.5V  V  5.5V 250 ns CC t SK Low Time 2.7V  V  5.5V 250 ns SKL CC 1.8V  V  5.5V 1000 ns CC 4.5V  V  5.5V 250 ns CC t Minimum CS Low Time 2.7V  V  5.5V 250 ns CS CC 1.8V  V  5.5V 1000 ns CC 4.5V  V  5.5V 50 ns CC t CS Setup Time Relative to SK 2.7V  V  5.5V 50 ns CSS CC 1.8V  V  5.5V 200 ns CC 4.5V  V  5.5V 100 ns CC t DI Setup Time Relative to SK 2.7V  V  5.5V 100 ns DIS CC 1.8V  V  5.5V 400 ns CC t CS Hold Time Relative to SK 0 ns CSH 4.5V  V  5.5V 100 ns CC t DI Hold Time Relative to SK 2.7V  V  5.5V 400 ns DIH CC 1.8V  V  5.5V ns CC 4.5V  V  5.5V 250 ns CC t Output Delay to 1 AC Test 2.7V  V  5.5V 250 ns PD1 CC 1.8V  V  5.5V 1000 ns CC 4.5V  V  5.5V 250 ns CC t Output Delay to 0 AC Test 2.7V  V  5.5V 250 ns PD0 CC 1.8V  V  5.5V 1000 ns CC 4.5V  V  5.5V 250 ns CC t CS to Status Valid AC Test 2.7V  V  5.5V 250 ns SV CC 1.8V  V  5.5V 1000 ns CC 4.5V  V  5.5V 100 ns CC CS to DO in AC Test t 2.7V  V  5.5V 250 ns DF High-impedance CS = V CC IL 1.8V  V  5.5V 400 ns CC t Write Cycle Time 1.8V  V  5.5V 0.1 3 5 ms WP CC Endurance(1) 5.0V, 25°C 1,000,000 Write Cycles Note: 1. This parameter is characterized, and is not 100% tested. AT93C46D [DATASHEET] 5 Atmel-5193H-SEEPROM-AT93C46D-Datasheet_012015

5. Functional Description The AT93C46D is accessed via a simple and versatile 3-wire serial communication interface. Device operation is controlled by seven instructions issued by the Host processor. A valid instruction starts with a rising edge of CS and consists of a Start bit (Logic 1), followed by the appropriate opcode, and the desired memory address location. Table 5-1. AT93C46D Instruction Set Address Data Instruction SB Opcode x8(1) x16(1) x8 x16 Comments Reads data stored in memory at READ 1 10 A – A A – A 6 0 5 0 specified address. Write Enable must precede all EWEN 1 00 11XXXXXXX 11XXXXXX programming modes. ERASE 1 11 A – A A – A Erases memory location A – A . 6 0 5 0 N 0 WRITE 1 01 A – A A – A D – D D – D Writes memory location A – A . 6 0 5 0 7 0 15 0 N 0 Erases all memory locations. ERAL 1 00 10XXXXXXX 10XXXXXX Valid only at V (Section 4.2, “DC CC3 Characteristics” on page 4). Writes all memory locations. WRAL 1 00 01XXXXXXX 01XXXXXX D – D D – D 7 0 15 0 Valid only at V (Section 4.2). CC3 Disables all programming EWDS 1 00 00XXXXXXX 00XXXXXX instructions. Note: 1. The ‘X’ in the address field represent don’t care values, and must be clocked. READ: The READ instruction contains the address code for the memory location to be read. After the instruction and address are decoded, data from the selected memory location is available at the Serial Output pin, DO. Output data changes are synchronized with the rising edges of the Serial Clock pin, SK. It should be noted that a dummy bit (Logic 0) precedes the 8-bit or 16-bit data output string. Erase/Write Enable (EWEN): To ensure data integrity, the part automatically goes into the Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable (EWEN) instruction must be executed first before any programming instructions can be carried out. Note: Once in the EWEN state, programming remains enabled until an EWDS instruction is executed, or V power is removed from the part. CC ERASE: The ERASE instruction programs all bits in the specified memory location to the Logic 1 state. The self-timed erase cycle starts once the ERASE instruction and address are decoded. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of t . A Logic 1 at the CS DO pin indicates that the selected memory location has been erased, and the part is ready for another instruction. 6 AT93C46D [DATASHEET] Atmel-5193H-SEEPROM-AT93C46D-Datasheet_012015

WRITE: The WRITE instruction contains the 8-bits or 16-bits of data to be written into the specified memory location. The self-timed programming cycle, t , starts after the last bit of data is received at Serial Data Input WP pin DI. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of t . A Logic 0 at DO indicates that programming is still in progress. A Logic 1 indicates that the CS memory location at the specified address has been written with the data pattern contained in the instruction, and the part is ready for further instructions. A Ready/Busy status cannot be obtained if CS is brought high after the end of the self-timed programming cycle, t . WP Erase All (ERAL): The Erase All (ERAL) instruction programs every bit in the Memory Array to the Logic 1 state and is primarily used for testing purposes. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of t . The ERAL instruction is valid only at V = 5.0V ± 10% (Section 4.2, CS CC “DC Characteristics” on page 4). Write All (WRAL): The Write All (WRAL) instruction programs all memory locations with the data patterns specified in the instruction. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of t . The WRAL instruction is valid only at V = 5.0V ± 10% (Section 4.2). CS CC Erase/Write Disable (EWDS): To protect against accidental data disturbance, the Erase/Write Disable (EWDS) instruction disables all programming modes and should be executed after all programming operations. The operation of the Read instruction is independent of both the EWEN and EWDS instructions and can be executed at any time. AT93C46D [DATASHEET] 7 Atmel-5193H-SEEPROM-AT93C46D-Datasheet_012015

6. Timing Diagrams Figure 6-1. Synchronous Data Timing VIH 1µs (1) CS VIL tCSS tSKH tSKL tCSH VIH SK VIL tDIS tDIH VIH DI VIL tPD0 tPD1 tDF VOH DO (Read) VOL tSV tDF VOH DO (Program) Status Valid VOL Note: 1. This is the minimum SK period. Table 6-1. Organization Key for Timing Diagrams AT93C46D (1K) I/O x8 x16 A A A N 6 5 D D D N 7 15 8 AT93C46D [DATASHEET] Atmel-5193H-SEEPROM-AT93C46D-Datasheet_012015

Figure 6-2. READ Timing CS tCS SK DI 1 1 0 AN A0 High-impedance DO 0 DN D0 Figure 6-3. EWEN Timing CS tCS SK DI 1 0 0 1 1 ... Figure 6-4. EWDS Timing CS tCS SK DI 1 0 0 0 0 ... AT93C46D [DATASHEET] 9 Atmel-5193H-SEEPROM-AT93C46D-Datasheet_012015

Figure 6-5. WRITE Timing CS tCS SK DI 1 0 1 AN ... A0 DN ... D0 High-impedance DO Busy Ready tWP Figure 6-6. WRAL Timing(1) tCS CCSS SSKK DDII 1 0 0 0 1 ... DN ... D0 High-impedance DDOO Busy Ready tWP Note: 1. Valid only at V (Section 4.2, “DC Characteristics” on page 4). CC3 10 AT93C46D [DATASHEET] Atmel-5193H-SEEPROM-AT93C46D-Datasheet_012015

Figure 6-7. ERASE Timing tCS CS Check Standby Status SK DI 1 1 1 AN AN-1 AN-2 ... A0 tSV tDF High-impedance High-impedance DO Busy Ready tWP Figure 6-8. ERAL Timing(1) tCS CCSS Check Standby Status SSKK DDII 1 0 0 1 0 tSV tDF High-impedance High-impedance DDOO Busy Ready tWP Note: 1. Valid only at V (Section 4.2, “DC Characteristics” on page 4). CC3 AT93C46D [DATASHEET] 11 Atmel-5193H-SEEPROM-AT93C46D-Datasheet_012015

7. Ordering Code Detail A T 9 3 C 4 6 D N - S H - B Atmel Designator Shipping Carrier Option B = Bulk T = Tape and Reel, Standard Quantity Option Product Family E = Tape and Reel, Expanded Quantity Option 93C = Microwire-compatible 3-Wire Serial EEPROM Package Device Grade or Wafer/Die Thickness Device Density H = Green, NiPdAu Lead Finish 46 = 1-Kilobit Industrial Temperature Range (-40°C to +85°C) U = Green, Matte Tin Lead Finish Device Revision or SnAgCu Ball Industrial Temperature Range (-40°C to +85°C) Package Variation (if applicable) 11 = 11mil Wafer Thickness N = 0.150” Wide JEDEC SOIC Y6 = 2.0x3.0mm Body UDFN U3 = 1.5x2.0mm Body VFBGA Package Option S = SOIC T = TSSOP Y = UDFN P = PDIP U = VFBGA WWU = Wafer Unsawn 12 AT93C46D [DATASHEET] Atmel-5193H-SEEPROM-AT93C46D-Datasheet_012015

8. Ordering Information Delivery Information Operation Atmel Ordering Code Lead Finish Package Form Quantity Range AT93C46DN-SH-B Bulk (Tubes) 100 per Tube 8S1 AT93C46DN-SH-T Tape and Reel 4,000 per Reel AT93C46D-TH-B Bulk (Tubes) 100 per Tube NiPdAu 8X (Lead-free/Halogen-free) AT93C46D-TH-T Tape and Reel 5,000 per Reel Industrial AT93C46DY6-YH-T Tape and Reel 5,000 per Reel Temperature (-40C to 85C) 8MA2 AT93C46DY6-YH-E Tape and Reel 15,000 per Reel Matte Tin AT93C46D-PU 8P3 Bulk (Tubes) 50 per Tube (Lead-free/Halogen free) SnAgCu AT93C46DU3-UU-T 8U3-1 Tape and Reel 5,000 per Reel (Lead-free/Halogen-free) AT93C46D-W-11(1) N/A Wafer Sale Note 1 Note: 1. For wafer sales, please contact Atmel sales. Bumped die available upon request. Package Type 8S1 8-lead, 0.150” wide, Plastic Gull Wing, Small Outline (JEDEC SOIC) 8X 8-lead, 0.170” wide, Thin Shrink Small Outline (TSSOP) 8MA2 8-pad, 2.00mm x 3.00mm body, 0.50mm pitch, Ultra Thin Dual No Lead (UDFN) 8P3 8-lead, 0.300” wide body, Plastic Dual In-line Package (PDIP) 8U3-1 8-ball, 1.50mm x 2.00mm body, 0.50mm pitch, Small Die Ball Grid Array (VFBGA) AT93C46D [DATASHEET] 13 Atmel-5193H-SEEPROM-AT93C46D-Datasheet_012015

9. Part Markings AT93C46D: Package Marking Information 8-lead SOIC 8-lead TSSOP 8-pad UDFN 2.0 x 3.0 mm Body ATMLHYWW HYWW ### ### % ###% H% AAAAAAAA YXX Note: Lot Number and location of assembly and on the bottom side of the package. 8-lead PDIP 8-ball VFBGA 1.5 x 2.0 mm Body ATMLUYWW ### % AAAAAAAA ###U YMXX PIN 1 Note 1: designates pin 1 Note 2: Package drawings are not to scale Catalog Number Truncation AT93C46D Truncation Code ###: 46D Date Codes V oltages Y = Year M = Month WW = Work Week of Assembly % = Minimum Voltage 4: 2014 8: 2018 A: January 02: Week 2 1: 1.8V min 5: 2015 9: 2019 B: February 04: Week 4 6: 2016 0: 2020 ... ... 7: 2017 1: 2021 L: December 52: Week 52 Country of Assembly L ot Number Grade/Lead Finish Material @ = Country of Assembly AAA...A = Atmel Wafer Lot Number H: Industrial/NiPdAu U: Industrial/Matte Tin/SnAgCu Trace Code Atmel Truncation XX = Trace Code (Atmel Lot Numbers Correspond to Code) AT: Atmel Example: AA, AB.... YZ, ZZ ATM: Atmel ATML: Atmel 6/11/14 TITLE DRAWING NO. REV. 93C46DSM, AT93C46D Package Marking Information Package Mark Contact: 93C46DSM A DL-CSO-Assy_eng@atmel.com 14 AT93C46D [DATASHEET] Atmel-5193H-SEEPROM-AT93C46D-Datasheet_012015

10. Packaging Information 10.1 8S1 — 8-lead JEDEC SOIC C 1 E E1 L N Ø TOP VIEW END VIEW e b A COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A1 A 1.35 – 1.75 A1 0.10 – 0.25 b 0.31 – 0.51 C 0.17 – 0.25 D 4.80 – 5.05 D E1 3.81 – 3.99 E 5.79 – 6.20 SIDE VIEW e 1.27 BSC Notes: This drawing is for general information only. L 0.40 – 1.27 Refer to JEDEC Drawing MS-012, Variation AA ØØ 0° – 8° for proper dimensions, tolerances, datums, etc. 6/22/11 TITLE GPC DRAWING NO. REV. 8S1, 8-lead (0.150” Wide Body), Plastic Gull Wing SWB 8S1 G Package Drawing Contact: Small Outline (JEDEC SOIC) packagedrawings@atmel.com AT93C46D [DATASHEET] 15 Atmel-5193H-SEEPROM-AT93C46D-Datasheet_012015

10.2 8X — 8-lead TSSOP C 1 Pin 1 indicator this corner E1 E L1 N L Top View End View A b A1 COMMON DIMENSIONS (Unit of Measure = mm) e A2 SYMBOL MIN NOM MAX NOTE D A - - 1.20 Side View A1 0.05 - 0.15 Notes: 1. This drawing is for general information only. A2 0.80 1.00 1.05 Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. D 2.90 3.00 3.10 2, 5 2. Dimension D does not include mold Flash, protrusions or gate E 6.40 BSC burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15mm (0.006in) per side. E1 4.30 4.40 4.50 3, 5 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25mm b 0.19 0.25 0.30 4 (0.010in) per side. e 0.65 BSC 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08mm total in excess L 0.45 0.60 0.75 of the b dimension at maximum material condition. Dambar L1 1.00 REF cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07mm. C 0.09 - 0.20 5. Dimension D and E1 to be determined at Datum Plane H. 2/27/14 TITLE GPC DRAWING NO. REV. 8X, 8-lead 4.4mm Body, Plastic Thin Package Drawing Contact: Shrink Small Outline Package (TSSOP) TNR 8X E packagedrawings@atmel.com 16 AT93C46D [DATASHEET] Atmel-5193H-SEEPROM-AT93C46D-Datasheet_012015

10.3 8MA2 — 8-pad UDFN E 1 8 Pin 1 ID 2 7 D 3 6 4 5 TOP VIEW C SIDE VIEW A2 A A1 E2 b (8x) 8 1 COMMON DIMENSIONS 7 2 Pin#1 ID (Unit of Measure = mm) D2 6 3 SYMBOL MIN NOM MAX NOTE A 0.50 0.55 0.60 5 4 A1 0.0 0.02 0.05 e (6x) A2 - - 0.55 L (8x) K D 1.90 2.00 2.10 BOTTOM VIEW D2 1.40 1.50 1.60 Notes: 1. This drawing is for general information only. Refer to E 2.90 3.00 3.10 Drawing MO-229, for proper dimensions, tolerances, E2 1.20 1.30 1.40 datums, etc. 2. The Pin #1 ID is a laser-marked feature on Top View. b 0.18 0.25 0.30 3 3. Dimensions b applies to metallized terminal and is C 1.52 REF measured between 0.15 mm and 0.30 mm from the terminal tip. If the terminal has the optional radius on L 0.30 0.35 0.40 the other end of the terminal, the dimension should e 0.50 BSC not be measured in that radius area. 4. The Pin #1 ID on the Bottom View is an orientation K 0.20 - - feature on the thermal pad. 11/26/14 TITLE GPC DRAWING NO. REV. 8MA2, 8-pad 2 x 3 x 0.6mm Body, Thermally Package Drawing Contact: Enhanced Plastic Ultra Thin Dual Flat No-Lead YNZ 8MA2 G packagedrawings@atmel.com Package (UDFN) AT93C46D [DATASHEET] 17 Atmel-5193H-SEEPROM-AT93C46D-Datasheet_012015

10.4 8P3 — 8-lead PDIP E 1 E1 .381 Gage Plane N Top View c eA End View COMMON DIMENSIONS D (Unit of Measure = mm) e D1 A2 A SYMBOL MIN NOM MAX NOTE A - - 5.334 2 A1 0.381 - - A2 2.921 3.302 4.953 b 0.356 0.457 0.559 5 b2 1.143 1.524 1.778 6 A1 b3 0.762 0.991 1.143 6 c 0.203 0.254 0.356 b2 L D 9.017 9.271 10.160 3 b3 D1 0.127 0.000 0.000 3 4 PLCS b v 0.254m C E 7.620 7.874 8.255 4 E1 6.096 6.350 7.112 3 Side View e 2.540 BSC eA 7.620 BSC 4 L 2.921 3.302 3.810 2 Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm). 07/31/14 TITLE GPC DRAWING NO. REV. 8P3, 8-lead, 0.300” Wide Body, Plastic Dual Package Drawing Contact: In-line Package (PDIP) PTC 8P3 E packagedrawings@atmel.com 18 AT93C46D [DATASHEET] Atmel-5193H-SEEPROM-AT93C46D-Datasheet_012015

10.5 8U3-1 — 8-ball VFBGA E D 2. b PIN 1 BALL PAD CORNER A1 A2 TOP VIEW A SIDE VIEW PIN 1 BALL PAD CORNER 1 2 3 4 d (d1) 8 7 6 5 e COMMON DIMENSIONS (Unit of Measure - mm) (e1) SYMBOL MIN NOM MAX NOTE BOTTOM VIEW A 0.73 0.79 0.85 8 SOLDER BALLS A1 0.09 0.14 0.19 A2 0.40 0.45 0.50 Notes: b 0.20 0.25 0.30 2 1. This drawing is for general information only. D 1.50 BSC E 2.0 BSC 2. Dimension ‘b’ is measured at maximum solder ball diameter. e 0.50 BSC 3. Solder ball composition shall be 95.5Sn-4.0Ag-.5Cu. e1 0.25 REF d 1.00 BSC d1 0.25 REF 6/11/13 TITLE GPC DRAWING NO. REV. 8U3-1, 8-ball, 1.50mm x 2.00mm body, 0.50mm pitch, Package Drawing Contact: Very Thin, Fine-Pitch Ball Grid Array Package (VFBGA) GXU 8U3-1 F packagedrawings@atmel.com AT93C46D [DATASHEET] 19 Atmel-5193H-SEEPROM-AT93C46D-Datasheet_012015

11. Revision History Revision No. Date Comments Added the UDFN expanded quantity option and the ordering information section. 5193H 01/2015 Updated the 8MA2 and 8P3 package drawings. 5193G 08/2014 Updated package drawings, template, logos, and disclaimer page. 5193F 01/2008 Removed the ‘preliminary’ status. 5193E 11/2007 Modified the ‘max’ value in AC Characteristics table. Moved Pinout figure. Added new feature for Die Sales. 5193D 08/2007 Modified Ordering Information table layout. Modified Park Marking Schemes. Updated to new template. Added Product Markup Scheme. 5193C 06/2007 Added Technical email contact. Corrected Figures 4 and 5. 5193B 02/2007 Added ‘Ultra Thin’ description to 8-lead Mini-MAP package. 5193A 01/2007 Initial document release. 20 AT93C46D [DATASHEET] Atmel-5193H-SEEPROM-AT93C46D-Datasheet_012015

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