Features • High-performance, Low-power AVR® 8-bit Microcontroller • Advanced RISC Architecture – 133 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers + Peripheral Control Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz – On-chip 2-cycle Multiplier • Non volatile Program and Data Memories – 32K/64K/128K Bytes of In-System Reprogrammable Flash (AT90CAN32/64/128) • Endurance: 10,000 Write/Erase Cycles – Optional Boot Code Section with Independent Lock Bits 8-bit • Selectable Boot Size: 1K Bytes, 2K Bytes, 4K Bytes or 8K Bytes • In-System Programming by On-Chip Boot Program (CAN, UART, ...) Microcontroller • True Read-While-Write Operation – 1K/2K/4K Bytes EEPROM (Endurance: 100,000 Write/Erase Cycles) (AT90CAN32/64/128) – 2K/4K/4K Bytes Internal SRAM (AT90CAN32/64/128) with – Up to 64K Bytes Optional External Memory Space – Programming Lock for Software Security • JTAG (IEEE std. 1149.1 Compliant) Interface 32K/64K/128K – Boundary-scan Capabilities According to the JTAG Standard – Programming Flash (Hardware ISP), EEPROM, Lock & Fuse Bits Bytes of – Extensive On-chip Debug Support • CAN Controller 2.0A & 2.0B - ISO 16845 Certified (1) – 15 Full Message Objects with Separate Identifier Tags and Masks ISP Flash – Transmit, Receive, Automatic Reply and Frame Buffer Receive Modes – 1Mbits/s Maximum Transfer Rate at 8 MHz and – Time stamping, TTC & Listening Mode (Spying or Autobaud) • Peripheral Features – Programmable Watchdog Timer with On-chip Oscillator CAN Controller – 8-bit Synchronous Timer/Counter-0 • 10-bit Prescaler • External Event Counter • Output Compare or 8-bit PWM Output – 8-bit Asynchronous Timer/Counter-2 AT90CAN32 • 10-bit Prescaler • External Event Counter AT90CAN64 • Output Compare or 8-Bit PWM Output • 32Khz Oscillator for RTC Operation – Dual 16-bit Synchronous Timer/Counters-1 & 3 AT90CAN128 • 10-bit Prescaler • Input Capture with Noise Canceler • External Event Counter • 3-Output Compare or 16-Bit PWM Output • Output Compare Modulation – 8-channel, 10-bit SAR ADC • 8 Single-ended Channels • 7 Differential Channels • 2 Differential Channels With Programmable Gain at 1x, 10x, or 200x – On-chip Analog Comparator – Byte-oriented Two-wire Serial Interface – Dual Programmable Serial USART – Master/Slave SPI Serial Interface • Programming Flash (Hardware ISP) • Special Microcontroller Features – Power-on Reset and Programmable Brown-out Detection – Internal Calibrated RC Oscillator – 8 External Interrupt Sources – 5 Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down & Standby – Software Selectable Clock Frequency – Global Pull-up Disable • I/O and Packages – 53 Programmable I/O Lines – 64-lead TQFP and 64-lead QFN • Operating Voltages: 2.7 - 5.5V • Operating temperature: Industrial (-40°C to +85°C) • Maximum Frequency: 8 MHz at 2.7V, 16 MHz at 4.5V Rev. 7679H–CAN–08/08 Note: 1. Details on section 19.4.3 on page 242.

1. Description 1.1 Comparison Between AT90CAN32, AT90CAN64 and AT90CAN128 AT90CAN32, AT90CAN64 and AT90CAN128 are hardware and software compatible. They dif- fer only in memory sizes as shown in Table 1-1. Table 1-1. Memory Size Summary Device Flash EEPROM RAM AT90CAN32 32K Bytes 1K Byte 2K Bytes AT90CAN64 64K Bytes 2K Bytes 4K Bytes AT90CAN128 128K Bytes 4K Byte 4K Bytes 1.2 Part Description The AT90CAN32/64/128 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the AT90CAN32/64/128 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. The AVR core combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than con- ventional CISC microcontrollers. The AT90CAN32/64/128 provides the following features: 32K/64K/128K bytes of In-System Pro- grammable Flash with Read-While-Write capabilities, 1K/2K/4K bytes EEPROM, 2K/4K/4K bytes SRAM, 53 general purpose I/O lines, 32 general purpose working registers, a CAN con- troller, Real Time Counter (RTC), four flexible Timer/Counters with compare modes and PWM, 2 USARTs, a byte oriented Two-wire Serial Interface, an 8-channel 10-bit ADC with optional differ- ential input stage with programmable gain, a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chip Debug system and programming and five software selectable power sav- ing modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI/CAN ports and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to main- tain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. The device is manufactured using Atmel’s high-density nonvolatile memory technology. The On- chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By AT90CAN32/64/128 2 7679H–CAN–08/08

AT90CAN32/64/128 combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel AT90CAN32/64/128 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The AT90CAN32/64/128 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emula- tors, and evaluation kits. 1.3 Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized. 3 7679H–CAN–08/08

1.4 Block Diagram Figure 1-1. Block Diagram PF7 - PF0 PA7 - PA0 PC7 - PC0 TAL1 TAL2 ESET X X R VCC PORTF DRIVERS PORTA DRIVERS PORTC DRIVERS GND DATAREGISTER DATADIR. DATAREGISTER DATADIR. DATAREGISTER DATADIR. PORTF REG.PORTF PORTA REG.PORTA PORTC REG.PORTC 8-BIT DATA BUS POR - BOD RESET AVCC INTERNAL CALIB. OSC OSCILLATOR ADC AGND AREF OSCILLATOR WATCHDOG PROGRAM STACK TIMER JTAG TAP COUNTER POINTER OSCILLATOR CAN(cid:31) ON-CHIP DEBUG PRFOLAGSRHAM SRAM MCRUE GCOISNTTERROL TCIMOINNTGR AONLD CONTROLLER BOUSNCDAANRY- INRSETGRUISCTTEIRON PGUERNPEORSAEL COTUIMNETRER/S REGISTERS X PROGLORGAMICMING INDSETRCUOCDTEIRON YZ INTEURNRITUPT CONTROL LINES ALU EEPROM STATUS REGISTER TWO-WIRE SERIAL USART0 SPI USART1 INTERFACE R O ANALOGMPARAT +- DATAPROERGTIESTER RDEGAT.APODRIRT.E DATAPROERGTIBSTER RDEGAT.APODRIRT.B DATAPROERGTDISTER RDEGAT.APODRIRT.D DAPTOARRTEGG. RDEAGTA.PDOIRR.TG O C PORTE DRIVERS PORTB DRIVERS PORTD DRIVERS PORTG DRIVERS PE7 - PE0 PB7 - PB0 PD7 - PD0 PG4 - PG0 AT90CAN32/64/128 4 7679H–CAN–08/08

AT90CAN32/64/128 1.5 Pin Configurations Figure 1-2. Pinout AT90CAN32/64/128 - TQFP CK) MS) DO) DI) T T T T C0) C1) C2) C3) C4 / C5 / C6 / C7 / 0) 1) 2) D D D D D D D D D D D VCC ND REF F0 (A F1 (A F2 (A F3 (A F4 (A F5 (A F6 (A F7 (A ND CC A0 (A A1 (A A2 (A A G A P P P P P P P P G V P P P 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 NC(1) 1 48 PA3 (AD3) (RXD0 / PDI) PE0 2 47 PA4 (AD4) INDEX CORNER (TXD0 / PDO) PE1 3 46 PA5 (AD5) (XCK0 / AIN0) PE2 4 45 PA6 (AD6) (OC3A / AIN1) PE3 5 44 PA7 (AD7) (OC3B / INT4) PE4 6 43 PG2 (ALE) (OC3C / INT5) PE5 7 42 PC7 (A15 / CLKO) (T3 / INT6) PE6 8 41 PC6 (A14) (64-lead TQFP top view) (ICP3 / INT7) PE7 9 40 PC5 (A13) (SS) PB0 10 39 PC4 (A12) (SCK) PB1 11 38 PC3 (A11) (MOSI) PB2 12 37 PC2 (A10) (MISO) PB3 13 36 PC1 (A9) (OC2A) PB4 14 35 PC0 (A8) (OC1A) PB5 15 34 PG1 (RD) (OC1B) PB6 16 33 PG0 (WR) 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 7 3 4 T C D 2 1 0 1 2 3 4 5 6 7 1C) PB (2)2 ) PG (2)1 ) PG RESE VC GN XTAL XTAL T0) PD T1) PD T2) PD T3) PD P1) PD K1) PD T1) PD T0) PD (OC0A / OC (TOSC (TOSC (SCL / IN (SDA / IN (RXD1 / IN (TXD1 / IN (IC (TXCAN / XC (RXCAN / ( (1) NC = Do not connect (May be used in future devices) (2) Timer2 Oscillator 5 7679H–CAN–08/08

Figure 1-3. Pinout AT90CAN32/64/128 - QFN CK) MS) DO) DI) T T T T C0) C1) C2) C3) C4 / C5 / C6 / C7 / 0) 1) 2) D D D D D D D D D D D VCC ND REF F0 (A F1 (A F2 (A F3 (A F4 (A F5 (A F6 (A F7 (A ND CC A0 (A A1 (A A2 (A A G A P P P P P P P P G V P P P 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 6 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 NC(1) 1 48 PA3 (AD3) (RXD0 / PDI) PE0 2 47 PA4 (AD4) (TXD0 / PDO) PE1 3 46 PA5 (AD5) INDEX CORNER (XCK0 / AIN0) PE2 4 45 PA6 (AD6) (OC3A / AIN1) PE3 5 44 PA7 (AD7) (OC3B / INT4) PE4 6 43 PG2 (ALE) (OC3C / INT5) PE5 7 42 PC7 (A15 / CLKO) (T3 / INT6) PE6 8 41 PC6 (A14) (64-lead QFN top view) (ICP3 / INT7) PE7 9 40 PC5 (A13) (SS) PB0 10 39 PC4 (A12) (SCK) PB1 11 38 PC3 (A11) (MOSI) PB2 12 37 PC2 (A10) (MISO) PB3 13 36 PC1 (A9) (OC2A) PB4 14 35 PC0 (A8) (OC1A) PB5 15 34 PG1 (RD) (OC1B) PB6 16 33 PG0 (WR) 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3 3 7 3 4 T C D 2 1 0 1 2 3 4 5 6 7 1C) PB (2)2 ) PG (2)1 ) PG RESE VC GN XTAL XTAL T0) PD T1) PD T2) PD T3) PD P1) PD K1) PD T1) PD T0) PD (OC0A / OC (TOSC (TOSC (SCL / IN (SDA / IN (RXD1 / IN (TXD1 / IN (IC (TXCAN / XC (RXCAN / ( (1) NC = Do not connect (May be used in future devices) (2) Timer2 Oscillator Note: The large center pad underneath the QFN package is made of metal and internally connected to GND. It should be soldered or glued to the board to ensure good mechanical stability. If the center pad is left unconnected, the package might loosen from the board. 1.6 Pin Descriptions 1.6.1 VCC Digital supply voltage. 1.6.2 GND Ground. AT90CAN32/64/128 6 7679H–CAN–08/08

AT90CAN32/64/128 1.6.3 Port A (PA7..PA0) Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the AT90CAN32/64/128 as listed on page 74. 1.6.4 Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the AT90CAN32/64/128 as listed on page 76. 1.6.5 Port C (PC7..PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port C also serves the functions of special features of the AT90CAN32/64/128 as listed on page 78. 1.6.6 Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the AT90CAN32/64/128 as listed on page 80. 1.6.7 Port E (PE7..PE0) Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port E also serves the functions of various special features of the AT90CAN32/64/128 as listed on page 83. 1.6.8 Port F (PF7..PF0) Port F serves as the analog inputs to the A/D Converter. 7 7679H–CAN–08/08

Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal pull-up resistors (selected for each bit). The Port F output buffers have sym- metrical drive characteristics with both high sink and source capability. As inputs, Port F pins that are externally pulled low will source current if the pull-up resistors are activated. The Port F pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port F also serves the functions of the JTAG interface. If the JTAG interface is enabled, the pull- up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a reset occurs. 1.6.9 Port G (PG4..PG0) Port G is a 5-bit I/O port with internal pull-up resistors (selected for each bit). The Port G output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up resistors are activated. The Port G pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port G also serves the functions of various special features of the AT90CAN32/64/128 as listed on page 88. 1.6.10 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset. The minimum pulse length is given in characteristics. Shorter pulses are not guaranteed to generate a reset. The I/O ports of the AVR are immediately reset to their initial state even if the clock is not running. The clock is needed to reset the rest of the AT90CAN32/64/128. 1.6.11 XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. 1.6.12 XTAL2 Output from the inverting Oscillator amplifier. 1.6.13 AVCC AVCC is the supply voltage pin for the A/D Converter on Port F. It should be externally con- nected to V , even if the ADC is not used. If the ADC is used, it should be connected to V CC CC through a low-pass filter. 1.6.14 AREF This is the analog reference pin for the A/D Converter. 2. About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documen- tation for more details. AT90CAN32/64/128 8 7679H–CAN–08/08

AT90CAN32/64/128 3. AVR CPU Core 3.1 Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 3.2 Architectural Overview Figure 3-1. Block Diagram of the AVR Architecture Data Bus 8-bit Program Status Flash Counter and Control Program Memory Interrupt 32 x 8 Unit Instruction General Register Purpose SPI Registrers Unit Instruction Watchdog Decoder Timer g g n ssin essi ALU Analog Control Lines dre ddr Comparator d A ct A ect Dire Indir I/O Module1 Data I/O Module 2 SRAM I/O Module n EEPROM I/O Lines In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruc- tion is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory. 9 7679H–CAN–08/08

The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ- ical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic opera- tion, the Status Register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word for- mat. Every program memory address contains a 16- or 32-bit instruction. Program Flash memory space is divided in two sections, the Boot Program section and the Application Program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM (Store Program Memory) instruction that writes into the Application Flash memory section must reside in the Boot Program section. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector posi- tion. The lower the Interrupt Vector address, the higher is the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis- ters, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the AT90CAN32/64/128 has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used. 3.3 ALU – Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruction Set Summary” section for a detailed description. AT90CAN32/64/128 10 7679H–CAN–08/08

AT90CAN32/64/128 3.4 Status Register The Status Register contains information about the result of the most recently executed arith- metic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. The AVR Status Register – SREG – is defined as: Bit 7 6 5 4 3 2 1 0 I T H S V N Z C SREG Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set to enabled the interrupts. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference. • Bit 6 – T: Bit Copy Storage The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or desti- nation for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction. • Bit 5 – H: Half Carry Flag The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful in BCD arithmetic. See the “Instruction Set Description” for detailed information. • Bit 4 – S: Sign Bit, S = N ⊕ V The S-bit is always an EXCLUSIVE OR between the negative flag N and the Two’s Complement Overflow Flag V. See the “Instruction Set Description” for detailed information. • Bit 3 – V: Two’s Complement Overflow Flag The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Description” for detailed information. • Bit 2 – N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 11 7679H–CAN–08/08

• Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 3.5 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit output operand and one 8-bit result input • Two 8-bit output operands and one 8-bit result input • Two 8-bit output operands and one 16-bit result input • One 16-bit output operand and one 16-bit result input Figure 3-2 shows the structure of the 32 general purpose working registers in the CPU. Figure 3-2. AVR CPU General Purpose Working Registers 7 0 Addr. R0 0x00 R1 0x01 R2 0x02 … R13 0x0D General R14 0x0E Purpose R15 0x0F Working R16 0x10 Registers R17 0x11 … R26 0x1A X-register Low Byte R27 0x1B X-register High Byte R28 0x1C Y-register Low Byte R29 0x1D Y-register High Byte R30 0x1E Z-register Low Byte R31 0x1F Z-register High Byte Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions. As shown in Figure 3-2, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically imple- mented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file. 3.5.1 The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These reg- isters are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 3-3. AT90CAN32/64/128 12 7679H–CAN–08/08

AT90CAN32/64/128 Figure 3-3. The X-, Y-, and Z-registers 15 XH XL 0 X-register 7 0 7 0 R27 (0x1B) R26 (0x1A) 15 YH YL 0 Y-register 7 0 7 0 R29 (0x1D) R28 (0x1C) 15 ZH ZL 0 Z-register 7 0 7 0 R31 (0x1F) R30 (0x1E) In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 3.5.2 Extended Z-pointer Register for ELPM/SPM – RAMPZ Bit 7 6 5 4 3 2 1 0 – – – – – – – RAMPZ0 RAMPZ Read/Write R R R R R R R R/W Initial Value 0 0 0 0 0 0 0 0 • Bits 7..1 – Res: Reserved Bits These bits are reserved for future use and will always read as zero. For compatibility with future devices, be sure to write to write them to zero. • Bit 0 – RAMPZ0: Extended RAM Page Z-pointer The RAMPZ Register is normally used to select which 64K RAM Page is accessed by the Z- pointer. As the AT90CAN32/64/128 does not support more than 64K of SRAM memory, this reg- ister is used only to select which page in the program memory is accessed when the ELPM/SPM instruction is used. The different settings of the RAMPZ0 bit have the following effects: RAMPZ0 = 0:Program memory address 0x0000 - 0x7FFF (lower 64K bytes) is accessed by ELPM/SPM RAMPZ0 = 1:Program memory address 0x8000 - 0xFFFF (higher 64K bytes) is accessed by ELPM/SPM – AT90CAN32 and AT90CAN64: RAMPZ0 exists as register bit but it is not used for program memory addressing. – AT90CAN128: RAMPZ0 exists as register bit and it is used for program memory addressing. Figure 3-4. The Z-pointer used by ELPM and SPM Bit (Individually) 7 0 7 0 7 0 RAMPZ ZH ZL Bit (Z-pointer) 23 16 15 8 7 0 Note: LPM (different of ELPM) is never affected by the RAMPZ setting. 13 7679H–CAN–08/08

3.6 Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory loca- tions to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer. The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above 0xFF. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when data is popped from the Stack with return from subroutine RET or return from interrupt RETI. The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementa- tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. Bit 15 14 13 12 11 10 9 8 SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL 7 6 5 4 3 2 1 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3.7 Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk , directly generated from the selected clock source for the CPU chip. No internal clock division is used. Figure 3-5 shows the parallel instruction fetches and instruction executions enabled by the Har- vard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. Figure 3-5. The Parallel Instruction Fetches and Instruction Executions T1 T2 T3 T4 clk CPU 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch AT90CAN32/64/128 14 7679H–CAN–08/08

AT90CAN32/64/128 Figure 3-6 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destina- tion register. Figure 3-6. Single Cycle ALU Operation T1 T2 T3 T4 clk CPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back 3.8 Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software security. See the section “Memory Program- ming” on page 336 for details. The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 60. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL bit in the MCU Control Register (MCUCR). Refer to “Interrupts” on page 60 for more information. The Reset Vector can also be moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see “Boot Loader Support – Read-While-Write Self-Programming” on page 321. 3.8.1 Interrupt Behavior When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis- abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. There are basically two types of interrupts. The first type is triggered by an event that sets the interrupt flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding inter- rupt flag. Interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the interrupt flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding interrupt flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority. 15 7679H–CAN–08/08

The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have interrupt flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence. Assembly Code Example in r16, SREG ; store SREG value cli ; disable interrupts during timed sequence sbi EECR, EEMWE ; start EEPROM write sbi EECR, EEWE out SREG, r16 ; restore SREG value (I-bit) C Code Example char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= (1<<EEMWE); /* start EEPROM write */ EECR |= (1<<EEWE); SREG = cSREG; /* restore SREG value (I-bit) */ When using the SEI instruction to enable interrupts, the instruction following SEI will be exe- cuted before any pending interrupts, as shown in this example. Assembly Code Example sei ; set Global Interrupt Enable sleep ; enter sleep, waiting for interrupt ; note: will enter sleep before any pending ; interrupt(s) C Code Example _SEI(); /* set Global Interrupt Enable */ _SLEEP(); /* enter sleep, waiting for interrupt */ /* note: will enter sleep before any pending interrupt(s) */ AT90CAN32/64/128 16 7679H–CAN–08/08

AT90CAN32/64/128 3.8.2 Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles mini- mum. After four clock cycles the program vector address for the actual interrupt handling routine is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by four clock cycles. This increase comes in addition to the start-up time from the selected sleep mode. A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. 17 7679H–CAN–08/08

4. Memories This section describes the different memories in the AT90CAN32/64/128. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the AT90CAN32/64/128 features an EEPROM Memory for data storage. All three memory spaces are linear and regular. Table 4-1. Memory Mapping. Memory Mnemonic AT90CAN32 AT90CAN64 AT90CAN128 Size Flashsize 32 K bytes 64 K bytes 128 K bytes Start Address - 0x00000 Flash 0x07FFF(1) 0x0FFFF(1) 0x1FFFF(1) End Address Flashend 0x3FFF(2) 0x7FFF(2) 0xFFFF(2) Size - 32 bytes 32 Start Address - 0x0000 Registers End Address - 0x001F Size - 64 bytes I/O Start Address - 0x0020 Registers End Address - 0x005F Size - 160 bytes Ext I/O Start Address - 0x0060 Registers End Address - 0x00FF Size ISRAMsize 2 K bytes 4 K bytes 4 K bytes Internal Start Address ISRAMstart 0x0100 SRAM End Address ISRAMend 0x08FF 0x10FF 0x10FF Size XMemsize 0-64 K bytes External Start Address XMemstart 0x0900 0x1100 0x1100 Memory End Address XMemend 0xFFFF Size E2size 1 K bytes 2 K bytes 4 K bytes EEPROM Start Address - 0x0000 End Address E2end 0x03FF 0x07FF 0x0FFF Notes: 1. Byte address. 2. Word (16-bit) address. 4.1 In-System Reprogrammable Flash Program Memory The AT90CAN32/64/128 contains On-chip In-System Reprogrammable Flash memory for pro- gram storage (see “Flashsize”). Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 16 bits wide. For software security, the Flash Program memory space is divided into two sections, Boot Program section and Application Program section. The Flash memory has an endurance of at least 10,000 write/erase cycles. The AT90CAN32/64/128 Program Counter (PC) address the program memory locations. The opera- tion of Boot Program section and associated Boot Lock bits for software protection are described in detail in “Boot Loader Support – Read-While-Write Self-Programming” on page 321. “Memory Programming” on page 336 contains a detailed description on Flash data serial downloading using the SPI pins or the JTAG interface. AT90CAN32/64/128 18 7679H–CAN–08/08

AT90CAN32/64/128 Constant tables can be allocated within the entire program memory address space (see the LPM – Load Program Memory and ELPM – Extended Load Program Memory instruction description). Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Tim- ing” on page 14. Figure 4-1. Program Memory Map Program Memory 0x0000 Application Flash Section Boot Flash Section Flash end 4.2 SRAM Data Memory Figure 4-2 shows how the AT90CAN32/64/128 SRAM Memory is organized. The AT90CAN32/64/128 is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. The lower data memory locations address both the Register File, the I/O memory, Extended I/O memory, and the internal data SRAM. The first 32 locations address the Register File, the next 64 location the standard I/O memory, then 160 locations of Extended I/O memory, and the next locations address the internal data SRAM (see “ISRAMsize”). An optional external data SRAM can be used with the AT90CAN32/64/128. This SRAM will occupy an area in the remaining address locations in the 64K address space. This area starts at the address following the internal SRAM. The Register file, I/O, Extended I/O and Internal SRAM occupies the lowest bytes, so when using 64 KB (65,536 bytes) of External Memory, “XMemsize” bytes of External Memory are available. See “External Memory Interface” on page 27 for details on how to take advantage of the external memory map. 19 7679H–CAN–08/08

4.2.1 SRAM Data Access When the addresses accessing the SRAM memory space exceeds the internal data memory locations, the external data SRAM is accessed using the same instructions as for the internal data memory access. When the internal data memories are accessed, the read and write strobe pins (PG0 and PG1) are inactive during the whole access cycle. External SRAM operation is enabled by setting the SRE bit in the XMCRA Register. Accessing external SRAM takes one additional clock cycle per byte compared to access of the internal SRAM. This means that the commands LD, ST, LDS, STS, LDD, STD, PUSH, and POP take one additional clock cycle. If the Stack is placed in external SRAM, interrupts, subroutine calls and returns take three clock cycles extra because the two-byte program counter is pushed and popped, and external memory access does not take advantage of the internal pipe-line memory access. When external SRAM interface is used with wait-state, one-byte external access takes two, three, or four additional clock cycles for one, two, and three wait-states respectively. Interrupts, subroutine calls and returns will need five, seven, or nine clock cycles more than specified in the instruction set manual for one, two, and three wait-states. The five different addressing modes for the data memory cover: Direct, Indirect with Displace- ment, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register File, registers R26 to R31 feature the indirect addressing pointer registers. The direct addressing reaches the entire data space. The Indirect with Displacement mode reaches 63 address locations from the base address given by the Y- or Z-register. When using register indirect addressing modes with automatic pre-decrement and post-incre- ment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and the “ISRAM size” bytes of internal data SRAM in the AT90CAN32/64/128 are all accessible through all these addressing modes. The Register File is described in “General Purpose Regis- ter File” on page 12. AT90CAN32/64/128 20 7679H–CAN–08/08

AT90CAN32/64/128 Figure 4-2. Data Memory Map Data Memory 32 Registers 0x0000 - 0x001F 64 I/O Registers 0x0020 - 0x005F 160 Ext I/O Reg. 0x0060 - 0x00FF ISRAM start Internal SRAM (ISRAM size) ISRAM end XMem start External SRAM (XMem size) 0xFFFF 4.2.2 SRAM Data Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk cycles as described in Figure 4-3. CPU Figure 4-3. On-chip Data SRAM Access Cycles T1 T2 T3 clk CPU Address Compute Address Address valid Data e Writ WR Data d a e R RD Memory Access Instruction Next Instruction 21 7679H–CAN–08/08

4.3 EEPROM Data Memory The AT90CAN32/64/128 contains EEPROM memory (see “E2size”). It is organized as a sepa- rate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Reg- ister, and the EEPROM Control Register. For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM, see “SPI Serial Programming Overview” on page 348, “JTAG Programming Overview” on page 352, and “Parallel Programming Overview” on page 339 respectively. 4.3.1 EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space. The write access time for the EEPROM is given in Table 4-2. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instruc- tions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V is likely to rise or fall slowly on power-up/down. This causes the device for some CC period of time to run at a voltage lower than specified as minimum for the clock frequency used. See “Preventing EEPROM Corruption” on page 26.for details on how to avoid problems in these situations. In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed. 4.3.2 The EEPROM Address Registers – EEARH and EEARL Bit 15 14 13 12 11 10 9 8 – – – – EEAR11 EEAR10 EEAR9 EEAR8 EEARH EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL 7 6 5 4 3 2 1 0 Read/Write R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 X X X X X X X X X X X X • Bits 15..12 – Reserved Bits These bits are reserved bits in the AT90CAN32/64/128 and will always read as zero. • Bits 11..0 – EEAR11..0: EEPROM Address The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the EEPROM space (see “E2size”). The EEPROM data bytes are addressed linearly between 0 and “E2end”. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed. – AT90CAN32: EEAR11 & EEAR10 exist as register bit but they are not used for addressing. – AT90CAN64: EEAR11 exists as register bit but it is not used for addressing. AT90CAN32/64/128 22 7679H–CAN–08/08

AT90CAN32/64/128 4.3.3 The EEPROM Data Register – EEDR Bit 7 6 5 4 3 2 1 0 EEDR7 EEDR6 EEDR5 EEDR4 EEDR3 EEDR2 EEDR1 EEDR0 EEDR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bits 7..0 – EEDR7.0: EEPROM Data For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR. 4.3.4 The EEPROM Control Register – EECR Bit 7 6 5 4 3 2 1 0 – – – – EERIE EEMWE EEWE EERE EECR Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 X 0 • Bits 7..4 – Reserved Bits These bits are reserved bits in the AT90CAN32/64/128 and will always read as zero. • Bit 3 – EERIE: EEPROM Ready Interrupt Enable Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant inter- rupt when EEWE is cleared. • Bit 2 – EEMWE: EEPROM Master Write Enable The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is set, setting EEWE within four clock cycles will write data to the EEPROM at the selected address If EEMWE is zero, setting EEWE will have no effect. When EEMWE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure. • Bit 1 – EEWE: EEPROM Write Enable The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be written to one to write the value into the EEPROM. The EEMWE bit must be written to one before a logical one is written to EEWE, oth- erwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential): 1. Wait until EEWE becomes zero. 2. Wait until SPMEN (Store Program Memory Enable) in SPMCSR (Store Program Mem- ory Control and Status Register) becomes zero. 3. Write new EEPROM address to EEAR (optional). 4. Write new EEPROM data to EEDR (optional). 5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR. 6. Within four clock cycles after setting EEMWE, write a logical one to EEWE. The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a Boot Loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See “Boot Loader 23 7679H–CAN–08/08

Support – Read-While-Write Self-Programming” on page 321 for details about Boot programming. Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared during all the steps to avoid these problems. When the write access time has elapsed, the EEWE bit is cleared by hardware. The user soft- ware can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruction is executed. • Bit 0 – EERE: EEPROM Read Enable The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed. The user should poll the EEWE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR Register. The calibrated Oscillator is used to time the EEPROM accesses. Table 4-2 lists the typical pro- gramming time for EEPROM access from the CPU. Table 4-2. EEPROM Programming Time. Symbol Number of Calibrated RC Oscillator Cycles Typ Programming Time EEPROM write (from CPU) 67 584 8.5 ms AT90CAN32/64/128 24 7679H–CAN–08/08

AT90CAN32/64/128 The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts glo- bally) so that no interrupts will occur during execution of these functions. The examples also assume that no Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish. Assembly Code Example EEPROM_write: ; Wait for completion of previous write sbic EECR,EEWE rjmp EEPROM_write ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ; Write data (r16) to data register out EEDR,r16 ; Write logical one to EEMWE sbi EECR,EEMWE ; Start eeprom write by setting EEWE sbi EECR,EEWE ret C Code Example void EEPROM_write (unsigned int uiAddress, unsigned char ucData) { /* Wait for completion of previous write */ while(EECR & (1<<EEWE)); /* Set up address and data registers */ EEAR = uiAddress; EEDR = ucData; /* Write logical one to EEMWE */ EECR |= (1<<EEMWE); /* Start eeprom write by setting EEWE */ EECR |= (1<<EEWE); } 25 7679H–CAN–08/08

The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example EEPROM_read: ; Wait for completion of previous write sbic EECR,EEWE rjmp EEPROM_read ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ; Start eeprom read by writing EERE sbi EECR,EERE ; Read data from data register in r16,EEDR ret C Code Example unsigned char EEPROM_read(unsigned int uiAddress) { /* Wait for completion of previous write */ while(EECR & (1<<EEWE)); /* Set up address register */ EEAR = uiAddress; /* Start eeprom read by writing EERE */ EECR |= (1<<EERE); /* Return data from data register */ return EEDR; } 4.3.5 Preventing EEPROM Corruption During periods of low V the EEPROM data can be corrupted because the supply voltage is CC, too low for the CPU and the EEPROM to operate properly. These issues are the same as for board level systems using EEPROM, and the same design solutions should be applied. An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Sec- ondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low. EEPROM data corruption can easily be avoided by following this design recommendation: Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal BOD does not match the needed detection level, an external low V reset Protection circuit can CC be used. If a reset occurs while a write operation is in progress, the write operation will be com- pleted provided that the power supply voltage is sufficient. AT90CAN32/64/128 26 7679H–CAN–08/08

AT90CAN32/64/128 4.4 I/O Memory The I/O space definition of the AT90CAN32/64/128 is shown in “Register Summary” on page 405. All AT90CAN32/64/128 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set section for more details. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The AT90CAN32/64/128 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVR’s, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. The I/O and peripherals control registers are explained in later sections. 4.5 External Memory Interface With all the features the External Memory Interface provides, it is well suited to operate as an interface to memory devices such as External SRAM and Flash, and peripherals such as LCD- display, A/D, and D/A. The main features are: • Four different wait-state settings (including no wait-state). • Independent wait-state setting for different extErnal Memory sectors (configurable sector size). • The number of bits dedicated to address high byte is selectable. • Bus keepers on data lines to minimize current consumption (optional). 4.5.1 Overview When the eXternal MEMory (XMEM) is enabled, address space outside the internal SRAM becomes available using the dedicated External Memory pins (see Figure 1-2 on page 5 or Fig- ure 1-3 on page 6, Table 9-3 on page 74, Table 9-9 on page 78, and Table 9-21 on page 88). The memory configuration is shown in Figure 4-4. 27 7679H–CAN–08/08

Figure 4-4. External Memory with Sector Select 0x0000 Internal memory ISRAM end XMem start Lower sector SRW01 SRW00 SRL[2..0] External Memory Upper sector (0-64K x 8) SRW11 SRW10 0xFFFF 4.5.2 Using the External Memory Interface The interface consists of: • AD7:0: Multiplexed low-order address bus and data bus. • A15:8: High-order address bus (configurable number of bits). • ALE: Address latch enable. • RD: Read strobe. • WR: Write strobe. The control bits for the External Memory Interface are located in two registers, the External Memory Control Register A – XMCRA, and the External Memory Control Register B – XMCRB. When the XMEM interface is enabled, the XMEM interface will override the setting in the data direction registers that corresponds to the ports dedicated to the XMEM interface. For details about the port override, see the alternate functions in section “I/O-Ports” on page 66. The XMEM interface will auto-detect whether an access is internal or external. If the access is external, the XMEM interface will output address, data, and the control signals on the ports according to Fig- ure 4-6 (this figure shows the wave forms without wait-states). When ALE goes from high-to-low, there is a valid address on AD7:0. ALE is low during a data transfer. When the XMEM interface is enabled, also an internal access will cause activity on address, data and ALE ports, but the RD and WR strobes will not toggle during internal access. When the External Memory Interface is disabled, the normal pin and data direction settings are used. Note that when the XMEM inter- face is disabled, the address space above the internal SRAM boundary is not mapped into the internal SRAM. Figure 4-5 illustrates how to connect an external SRAM to the AVR using an octal latch (typically “74x573” or equivalent) which is transparent when G is high. AT90CAN32/64/128 28 7679H–CAN–08/08

AT90CAN32/64/128 4.5.3 Address Latch Requirements Due to the high-speed operation of the XRAM interface, the address latch must be selected with care for system frequencies above 8 MHz @ 4V and 4 MHz @ 2.7V. When operating at condi- tions above these frequencies, the typical old style 74HC series latch becomes inadequate. The External Memory Interface is designed in compliance to the 74AHC series latch. However, most latches can be used as long they comply with the main timing parameters. The main parameters for the address latch are: • D to Q propagation delay (t ). PD • Data setup time before G low (t ). SU • Data (address) hold time after G low ( ). TH The External Memory Interface is designed to guaranty minimum address hold time after G is asserted low of t = 5 ns. Refer to t / t in Table 26-7 through Table 26-14 of Sec- h LAXX_LD LLAXX_ST tion 26.9 on page 375. The D-to-Q propagation delay (t ) must be taken into consideration PD when calculating the access time requirement of the external component. The data setup time before G low (t ) must not exceed address valid to ALE low (t ) minus PCB wiring delay SU AVLLC (dependent on the capacitive load). Figure 4-5. External SRAM Connected to the AVR D[7:0] AD7:0 D Q A[7:0] ALE G SRAM AVR A15:8 A[15:8] RD RD WR WR 4.5.4 Pull-up and Bus-keeper The pull-ups on the AD7:0 ports may be activated if the corresponding Port register is written to one. To reduce power consumption in sleep mode, it is recommended to disable the pull-ups by writing the Port register to zero before entering sleep. The XMEM interface also provides a bus-keeper on the AD7:0 lines. The bus-keeper can be dis- abled and enabled in software as described in “External Memory Control Register B – XMCRB” on page 33. When enabled, the bus-keeper will ensure a defined logic level (zero or one) on the AD7:0 bus when these lines would otherwise be tri-stated by the XMEM interface. 4.5.5 Timing External Memory devices have different timing requirements. To meet these requirements, the AT90CAN32/64/128 XMEM interface provides four different wait-states as shown in Table 4-4. It is important to consider the timing specification of the External Memory device before selecting the wait-state. The most important parameters are the access time for the external memory compared to the set-up requirement of the AT90CAN32/64/128. The access time for the Exter- nal Memory is defined to be the time from receiving the chip select/address until the data of this 29 7679H–CAN–08/08

address actually is driven on the bus. The access time cannot exceed the time from the ALE pulse must be asserted low until data is stable during a read sequence (see t + t - t LLRL RLRH DVRH in Table 26-7 through Table 26-14). The different wait-states are set up in software. As an addi- tional feature, it is possible to divide the external memory space in two sectors with individual wait-state settings. This makes it possible to connect two different memory devices with different timing requirements to the same XMEM interface. For XMEM interface timing details, please refer to Table 26-7 through Table 26-14 and Figure 26-6 to Figure 26-9 in the “External Data Memory Characteristics” on page 375. Note that the XMEM interface is asynchronous and that the waveforms in the following figures are related to the internal system clock. The skew between the internal and external clock (XTAL1) is not guarantied (varies between devices temperature, and supply voltage). Conse- quently, the XMEM interface is not suited for synchronous operation. Figure 4-6. External Data Memory Cycles no Wait-state (SRWn1=0 and SRWn0=0)(1) T1 T2 T3 T4 System Clock (CLKCPU) ALE A15:8 Prev. addr. Address e DA7:0 Prev. data Address XX Data Writ WR DA7:0 (XMBK = 0) Prev. data Address Data d DA7:0 (XMBK = 1) Prev. data Address XXXXX Data XXXXXXXX ea R RD Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sector). The ALE pulse in period T4 is only present if the next instruction accesses the RAM (internal or external). Figure 4-7. External Data Memory Cycles with SRWn1 = 0 and SRWn0 = 1(1) T1 T2 T3 T4 T5 System Clock (CLKCPU) ALE A15:8 Prev. addr. Address e DA7:0 Prev. data Address XX Data Writ WR DA7:0 (XMBK = 0) Prev. data Address Data d DA7:0 (XMBK = 1) Prev. data Address Data ea R RD AT90CAN32/64/128 30 7679H–CAN–08/08

AT90CAN32/64/128 Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sector). The ALE pulse in period T5 is only present if the next instruction accesses the RAM (internal or external). Figure 4-8. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 0(1) T1 T2 T3 T4 T5 T6 System Clock (CLKCPU) ALE A15:8 Prev. addr. Address e DA7:0 Prev. data Address XX Data Writ WR DA7:0 (XMBK = 0) Prev. data Address Data d DA7:0 (XMBK = 1) Prev. data Address Data ea R RD Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sector). The ALE pulse in period T6 is only present if the next instruction accesses the RAM (internal or external). Figure 4-9. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 1(1) T1 T2 T3 T4 T5 T6 T7 System Clock (CLKCPU) ALE A15:8 Prev. addr. Address DA7:0 Prev. data Address XX Data Write WR DA7:0 (XMBK = 0) Prev. data Address Data DA7:0 (XMBK = 1) Prev. data Address Data Read RD Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sector). The ALE pulse in period T7 is only present if the next instruction accesses the RAM (internal or external). 31 7679H–CAN–08/08

4.5.6 External Memory Control Register A – XMCRA Bit 7 6 5 4 3 2 1 0 SRE SRL2 SRL1 SRL0 SRW11 SRW10 SRW01 SRW00 XMCRA Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 7 – SRE: External SRAM/XMEM Enable Writing SRE to one enables the External Memory Interface.The pin functions AD7:0, A15:8, ALE, WR, and RD are activated as the alternate pin functions. The SRE bit overrides any pin direction settings in the respective data direction registers. Writing SRE to zero, disables the External Memory Interface and the normal pin and data direction settings are used. Note that when the XMEM interface is disabled, the address space above the internal SRAM boundary is not mapped into the internal SRAM. • Bit 6..4 – SRL2, SRL1, SRL0: Wait-state Sector Limit It is possible to configure different wait-states for different External Memory addresses. The external memory address space can be divided in two sectors that have separate wait-state bits. The SRL2, SRL1, and SRL0 bits select the split of the sectors, see Table 4-3 and Figure 4-4. By default, the SRL2, SRL1, and SRL0 bits are set to zero and the entire external memory address space is treated as one sector. When the entire SRAM address space is configured as one sec- tor, the wait-states are configured by the SRW11 and SRW10 bits. Table 4-3. Sector limits with different settings of SRL2..0 SRL2 SRL1 SRL0 Sector Addressing Lower sector N/A 0 0 0 Upper sector “XMemstart”(1) - 0xFFFF Lower sector “XMemstart”(1) - 0x1FFF 0 0 1 Upper sector 0x2000 - 0xFFFF Lower sector “XMemstart”(1) - 0x3FFF 0 1 0 Upper sector 0x4000 - 0xFFFF Lower sector “XMemstart”(1) - 0x5FFF 0 1 1 Upper sector 0x6000 - 0xFFFF Lower sector “XMemstart”(1) - 0x7FFF 1 0 0 Upper sector 0x8000 - 0xFFFF Lower sector “XMemstart”(1) - 0x9FFF 1 0 1 Upper sector 0xA000 - 0xFFFF Lower sector “XMemstart”(1) - 0xBFFF 1 1 0 Upper sector 0xC000 - 0xFFFF Lower sector “XMemstart”(1) - 0xDFFF 1 1 1 Upper sector 0xE000 - 0xFFFF Note: 1. See Table 4-1 on page 18 for “XMemstart” setting. AT90CAN32/64/128 32 7679H–CAN–08/08

AT90CAN32/64/128 • Bit 3..2 – SRW11, SRW10: Wait-state Select Bits for Upper Sector The SRW11 and SRW10 bits control the number of wait-states for the upper sector of the exter- nal memory address space, see Table 4-4. • Bit 1..0 – SRW01, SRW00: Wait-state Select Bits for Lower Sector The SRW01 and SRW00 bits control the number of wait-states for the lower sector of the exter- nal memory address space, see Table 4-4. Table 4-4. Wait States(1) SRWn1 SRWn0 Wait States 0 0 No wait-states 0 1 Wait one cycle during read/write strobe 1 0 Wait two cycles during read/write strobe Wait two cycles during read/write and wait one cycle before driving out new 1 1 address Note: 1. n = 0 or 1 (lower/upper sector). For further details of the timing and wait-states of the External Memory Interface, see Figures 4-6 through Figures 4-9 for how the setting of the SRW bits affects the timing. 4.5.7 External Memory Control Register B – XMCRB Bit 7 6 5 4 3 2 1 0 XMBK – – – – XMM2 XMM1 XMM0 XMCRB Read/Write R/W R R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 7– XMBK: External Memory Bus-keeper Enable Writing XMBK to one enables the bus keeper on the AD7:0 lines. When the bus keeper is enabled, it will ensure a defined logic level (zero or one) on AD7:0 when they would otherwise be tri-stated. Writing XMBK to zero disables the bus keeper. XMBK is not qualified with SRE, so even if the XMEM interface is disabled, the bus keepers are still activated as long as XMBK is one. • Bit 6..4 – Reserved Bits These are reserved bits and will always read as zero. When writing to this address location, write these bits to zero for compatibility with future devices. • Bit 2..0 – XMM2, XMM1, XMM0: External Memory High Mask When the External Memory is enabled, all Port C pins are default used for the high address byte. If the full address space is not required to access the External Memory, some, or all, Port C pins can be released for normal Port Pin function as described in Table 4-5. As described in “Using all 64KB Locations of External Memory” on page 35, it is possible to use the XMMn bits to access all 64KB locations of the External Memory. 33 7679H–CAN–08/08

Table 4-5. Port C Pins Released as Normal Port Pins when the External Memory is Enabled XMM2 XMM1 XMM0 # Bits for External Memory Address Released Port Pins 0 0 0 8 (Full External Memory Space) None 0 0 1 7 PC7 0 1 0 6 PC7 .. PC6 0 1 1 5 PC7 .. PC5 1 0 0 4 PC7 .. PC4 1 0 1 3 PC7 .. PC3 1 1 0 2 PC7 .. PC2 1 1 1 No Address high bits Full Port C 4.5.8 Using all Locations of External Memory Smaller than 64 KB Since the external memory is mapped after the internal memory as shown in Figure 4-4, the external memory is not addressed when addressing the first “ISRAMsize” bytes of data space. It may appear that the first “ISRAMsize” bytes of the external memory are inaccessible (external memory addresses 0x0000 to “ISRAMend”). However, when connecting an external memory smaller than 64 KB, for example 32 KB, these locations are easily accessed simply by address- ing from address 0x8000 to “ISRAMend + 0x8000”. Since the External Memory Address bit A15 is not connected to the external memory, addresses 0x8000 to “ISRAM end + 0x8000” will appear as addresses 0x0000 to “ISRAM end” for the external memory. Addressing above address “ISRAMend + 0x8000” is not recommended, since this will address an external mem- ory location that is already accessed by another (lower) address. To the Application software, the external 32 KB memory will appear as one linear 32 KB address space from “XMemstart” to “XMemstart + 0x8000”. This is illustrated in Figure 4-10. Figure 4-10. Address Map with 32 KB External Memory AVR Memory Map External 32K SRAM (Size=0x8000) 0x0000 0x0000 Internal Memory ISRAM end ISRAM end XMem start XMem start External Memory 0x7FFF 0x7FFF 0x8000 ISRAM end + 0x8000 XMem start + 0x8000 (Unused) 0xFFFF AT90CAN32/64/128 34 7679H–CAN–08/08

AT90CAN32/64/128 4.5.9 Using all 64KB Locations of External Memory Since the External Memory is mapped after the Internal Memory as shown in Figure 4-4, only (64K-(“ISRAM size”+256)) bytes of External Memory is available by default (address space 0x0000 to “ISRAMend” is reserved for internal memory). However, it is possible to take advan- tage of the entire External Memory by masking the higher address bits to zero. This can be done by using the XMMn bits and control by software the most significant bits of the address. By set- ting Port C to output 0x00, and releasing the most significant bits for normal Port Pin operation, the Memory Interface will address 0x0000 - 0x1FFF. See the following code examples. Assembly Code Example(1) ; OFFSET is defined to 0x2000 to ensure ; external memory access ; Configure Port C (address high byte) to ; output 0x00 when the pins are released ; for normal Port Pin operation ldi r16, 0xFF out DDRC, r16 ldi r16, 0x00 out PORTC, r16 ; release PC7:5 ldi r16, (1<<XMM1)|(1<<XMM0) sts XMCRB, r16 ; write 0xAA to address 0x0001 of external ; memory ldi r16, 0xaa sts 0x0001+OFFSET, r16 ; re-enable PC7:5 for external memory ldi r16, (0<<XMM1)|(0<<XMM0) sts XMCRB, r16 ; store 0x55 to address (OFFSET + 1) of ; external memory ldi r16, 0x55 sts 0x0001+OFFSET, r16 C Code Example(1) #define OFFSET 0x2000 void XRAM_example(void) { unsigned char *p = (unsigned char *) (OFFSET + 1); DDRC = 0xFF; PORTC = 0x00; XMCRB = (1<<XMM1) | (1<<XMM0); *p = 0xaa; XMCRB = 0x00; *p = 0x55; } Note: 1. The example code assumes that the part specific header file is included. Care must be exercised using this option as most of the memory is masked away. 35 7679H–CAN–08/08

4.6 General Purpose I/O Registers The AT90CAN32/64/128 contains three General Purpose I/O Registers. These registers can be used for storing any information, and they are particularly useful for storing global variables and status flags. The General Purpose I/O Register 0, within the address range 0x00 - 0x1F, is directly bit-acces- sible using the SBI, CBI, SBIS, and SBIC instructions. 4.6.1 General Purpose I/O Register 0 – GPIOR0 Bit 7 6 5 4 3 2 1 0 GPIOR07 GPIOR06 GPIOR05 GPIOR04 GPIOR03 GPIOR02 GPIOR01 GPIOR00 GPIOR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 4.6.2 General Purpose I/O Register 1 – GPIOR1 Bit 7 6 5 4 3 2 1 0 GPIOR17 GPIOR16 GPIOR15 GPIOR14 GPIOR13 GPIOR12 GPIOR11 GPIOR10 GPIOR1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 4.6.3 General Purpose I/O Register 2 – GPIOR2 Bit 7 6 5 4 3 2 1 0 GPIOR27 GPIOR26 GPIOR25 GPIOR24 GPIOR23 GPIOR22 GPIOR21 GPIOR20 GPIOR2 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 AT90CAN32/64/128 36 7679H–CAN–08/08

AT90CAN32/64/128 5. System Clock 5.1 Clock Systems and their Distribution Figure 5-1 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to unused modules can be halted by using different sleep modes, as described in “Power Management and Sleep Modes” on page 46. The clock systems are detailed below. Figure 5-1. Clock Distribution Asynchronous CAN General I/O Flash and ADC CPU Core RAM Timer/Counter2 Controller Modules EEPROM clk ADC clkI/O AVR Clock clkCPU Control Unit CLKO clk clk ASY FLASH CKOUT Fuse Reset Logic Watchdog Timer Source clock Watchdog clock Prescaler Watchdog Clock Oscillator Multiplexer Multiplexer Timer/Counter2 Timer/Counter2 Crystal Low-frequency Calibrated RC External Clock External Clock Oscillator Oscillator Crystal Oscillator Oscillator TOSC1 TOSC2 XTAL1 XTAL2 5.1.1 CPU Clock – clk CPU The CPU clock is routed to parts of the system concerned with operation of the AVR core. Examples of such modules are the General Purpose Register File, the Status Register and the data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing general operations and calculations. 5.1.2 I/O Clock – clk I/O The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, CAN, USART. The I/O clock is also used by the External Interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted. Also note that address recognition in the TWI module is carried out asynchro- nously when clk is halted, enabling TWI address reception in all sleep modes. I/O 5.1.3 Flash Clock – clk FLASH The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul- taneously with the CPU clock. 37 7679H–CAN–08/08

5.1.4 Asynchronous Timer Clock – clk ASY The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly from an external clock or an external 32 kHz clock crystal. The dedicated clock domain allows using this Timer/Counter as a real-time counter even when the device is in sleep mode. 5.1.5 ADC Clock – clk ADC The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results. 5.2 Clock Sources The device has the following clock source options, selectable by Flash Fuse bits as shown below. The clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules. Table 5-1. Device Clocking Options Select(1) Device Clocking Option CKSEL3..0 External Crystal/Ceramic Resonator 1111 - 1000 External Low-frequency Crystal 0111 - 0100 Calibrated Internal RC Oscillator 0010 External Clock 0000 Reserved 0011, 0001 Note: 1. For all fuses “1” means unprogrammed while “0” means programmed. The various choices for each clocking option is given in the following sections. When the CPU wakes up from Power-down or Power-save, the selected clock source is used to time the start- up, ensuring stable Oscillator operation before instruction execution starts. When the CPU starts from reset, there is an additional delay allowing the power to reach a stable level before starting normal operation. The Watchdog Oscillator is used for timing this real-time part of the start-up time. The number of WDT Oscillator cycles used for each time-out is shown in Table 5-2. The frequency of the Watchdog Oscillator is voltage dependent as shown in “AT90CAN32/64/128 Typical Characteristics” on page 384. Table 5-2. Number of Watchdog Oscillator Cycles Typ Time-out (V = 5.0V) Typ Time-out (V = 3.0V) Number of Cycles CC CC 4.1 ms 4.3 ms 4K (4,096) 65 ms 69 ms 64K (65,536) 5.3 Default Clock Source The device is shipped with CKSEL = “0010”, SUT = “10”, and CKDIV8 programmed. The default clock source setting is the Internal RC Oscillator with longest start-up time and an initial system clock prescaling of 8. This default setting ensures that all users can make their desired clock source setting using an In-System or Parallel programmer. AT90CAN32/64/128 38 7679H–CAN–08/08

AT90CAN32/64/128 5.4 Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be con- figured for use as an On-chip Oscillator, as shown in Figure 5-2. Either a quartz crystal or a ceramic resonator may be used. C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for use with crystals are given in Table 5-3. For ceramic resonators, the capacitor values given by the manufacturer should be used. For more information on how to choose capacitors and other details on Oscillator operation, refer to the Multi-purpose Oscillator Application Note. Figure 5-2. Crystal Oscillator Connections C2 XTAL2 C1 XTAL1 GND The Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 5-3. Table 5-3. Crystal Oscillator Operating Modes Recommended Range for Capacitors C1 and CKSEL3..1 Frequency Range (MHz) C2 for Use with Crystals (pF) 100(1) 0.4 - 0.9 12 - 22 101 0.9 - 3.0 12 - 22 110 3.0 - 8.0 12 - 22 111 8.0 - 16.0 12 - 22 Note: 1. This option should not be used with crystals, only with ceramic resonators. The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in Table 5-4. 39 7679H–CAN–08/08

Table 5-4. Start-up Times for the Oscillator Clock Selection Start-up Time from Additional Delay CKSEL0 SUT1..0 Power-down and from Reset Recommended Usage Power-save (V = 5.0V) CC Ceramic resonator, fast 0 00 258 CK(1) 14 CK + 4.1 ms rising power Ceramic resonator, slowly 0 01 258 CK(1) 14 CK + 65 ms rising power Ceramic resonator, BOD 0 10 1K CK(2) 14 CK enabled Ceramic resonator, fast 0 11 1K CK(2) 14 CK + 4.1 ms rising power Ceramic resonator, slowly 1 00 1K CK(2) 14 CK + 65 ms rising power Crystal Oscillator, BOD 1 01 16K CK 14 CK enabled Crystal Oscillator, fast 1 10 16K CK 14 CK + 4.1 ms rising power Crystal Oscillator, slowly 1 11 16K CK 14 CK + 65 ms rising power Notes: 1. These options should only be used when not operating close to the maximum frequency of the device, and only if frequency stability at start-up is not important for the application. These options are not suitable for crystals. 2. These options are intended for use with ceramic resonators and will ensure frequency stability at start-up. They can also be used with crystals when not operating close to the maximum fre- quency of the device, and if frequency stability at start-up is not important for the application. 5.5 Low-frequency Crystal Oscillator To use a 32.768kHz watch crystal as the clock source for the device, the low-frequency crystal Oscillator must be selected by setting the CKSEL Fuses to “0100”, “0101”, “0110”, or “0111”. The crystal should be connected as shown in Figure 5-3. Figure 5-3. Low-frequency Crystal Oscillator Connections 12 - 22 pF XTAL2 32.768 KHz XTAL1 12 - 22 pF GND 12-22 pF capacitors may be necessary if the parasitic impedance (pads, wires & PCB) is very low. AT90CAN32/64/128 40 7679H–CAN–08/08

AT90CAN32/64/128 When this Oscillator is selected, start-up times are determined by the SUT1..0 fuses as shown in Table 5-5 and CKSEL1..0 fuses as shown in Table 5-6. Table 5-5. Start-up Times for the Low-frequency Crystal Oscillator Clock Selection SUT1..0 Additional Delay from Reset (V = 5.0V) Recommended Usage CC 00 14 CK Fast rising power or BOD enabled 01 14 CK + 4.1 ms Slowly rising power 10 14 CK + 65 ms Stable frequency at start-up 11 Reserved Table 5-6. Start-up Times for the Low-frequency Crystal Oscillator Clock Selection Start-up Time from CKSEL3..0 Recommended Usage Power-down and Power-save 0100(1) 1K CK 0101 32K CK Stable frequency at start-up 0110(1) 1K CK 0111 32K CK Stable frequency at start-up Note: 1. These options should only be used if frequency stability at start-up is not important for the application 5.6 Calibrated Internal RC Oscillator The calibrated internal RC Oscillator provides a fixed 8.0 MHz clock. The frequency is nominal value at 3V and 25°C. If 8 MHz frequency exceeds the specification of the device (depends on V ), the CKDIV8 Fuse must be programmed in order to divide the internal frequency by 8 dur- CC ing start-up. The device is shipped with the CKDIV8 Fuse programmed. See “System Clock Prescaler” on page 44. for more details. This clock may be selected as the system clock by pro- gramming the CKSEL Fuses as shown in Table 5-7. If selected, it will operate with no external components. During reset, hardware loads the calibration byte into the OSCCAL Register and thereby automatically calibrates the RC Oscillator. At 5V and 25°C, this calibration gives a fre- quency within ± 10% of the nominal frequency. Using calibration methods as described in application notes available at www.atmel.com/avr it is possible to achieve ± 2% accuracy at any given VCC and temperature. When this Oscillator is used as the chip clock, the Watchdog Oscil- lator will still be used for the Watchdog Timer and for the Reset Time-out. For more information on the pre-programmed calibration value, see the section “Calibration Byte” on page 339. Table 5-7. Internal Calibrated RC Oscillator Operating Modes(1) CKSEL3..0 Nominal Frequency 0010 8.0 MHz Note: 1. The device is shipped with this option selected. 41 7679H–CAN–08/08

When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 5-8. Table 5-8. Start-up times for the internal calibrated RC Oscillator clock selection Start-up Time from Power- Additional Delay from SUT1..0 Recommended Usage down and Power-save Reset (V = 5.0V) CC 00 6 CK 14 CK BOD enabled 01 6 CK 14 CK + 4.1 ms Fast rising power 10(1) 6 CK 14 CK + 65 ms Slowly rising power 11 Reserved Note: 1. The device is shipped with this option selected. 5.6.1 Oscillator Calibration Register – OSCCAL Bit 7 6 5 4 3 2 1 0 – CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 OSCCAL Read/Write R R/W R/W R/W R/W R/W R/W R/W Initial Value 0 <----- ----------- Device Specific Calibration Value ----------- -----> • Bit 7 – Reserved Bit This bit is reserved for future use. • Bits 6..0 – CAL6..0: Oscillator Calibration Value Writing the calibration byte to this address will trim the internal Oscillator to remove process vari- ations from the Oscillator frequency. This is done automatically during Chip Reset. When OSCCAL is zero, the lowest available frequency is chosen. Writing non-zero values to this regis- ter will increase the frequency of the internal Oscillator. Writing 0x7F to the register gives the highest available frequency. The calibrated Oscillator is used to time EEPROM and Flash access. If EEPROM or Flash is written, do not calibrate to more than 10% above the nominal fre- quency. Otherwise, the EEPROM or Flash write may fail. Note that the Oscillator is intended for calibration to 8.0 MHz. Tuning to other values is not guaranteed, as indicated in Table 5-9. Table 5-9. Internal RC Oscillator Frequency Range. Min Frequency in Percentage of Max Frequency in Percentage of OSCCAL Value Nominal Frequency Nominal Frequency 0x00 50% 100% 0x3F 75% 150% 0x7F 100% 200% 5.7 External Clock To drive the device from an external clock source, XTAL1 should be driven as shown in Figure 5-4. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”. AT90CAN32/64/128 42 7679H–CAN–08/08

AT90CAN32/64/128 Figure 5-4. External Clock Drive Configuration NC XTAL2 External Clock XTAL1 Signal GND Table 5-10. External Clock Frequency CKSEL3..0 Frequency Range 0000 0 - 16 MHz When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 5-11. Table 5-11. Start-up Times for the External Clock Selection Start-up Time from Power- Additional Delay from SUT1..0 Recommended Usage down and Power-save Reset (V = 5.0V) CC 00 6 CK 14 CK BOD enabled 01 6 CK 14 CK + 4.1 ms Fast rising power 10 6 CK 14 CK + 65 ms Slowly rising power 11 Reserved When applying an external clock, it is required to avoid sudden changes in the applied clock fre- quency to ensure stable operation of the MCU. A variation in frequency of more than 2% from one clock cycle to the next can lead to unpredictable behavior. It is required to ensure that the MCU is kept in Reset during such changes in the clock frequency. Note that the System Clock Prescaler can be used to implement run-time changes of the internal clock frequency while still ensuring stable operation. Refer to “System Clock Prescaler” on page 44 for details. 5.8 Clock Output Buffer When the CKOUT Fuse is programmed, the system Clock will be output on CLKO. This mode is suitable when chip clock is used to drive other circuits on the system. The clock will be output also during reset and the normal operation of I/O pin will be overridden when the fuse is pro- grammed. Any clock source, including internal RC Oscillator, can be selected when CLKO serves as clock output. If the System Clock Prescaler is used, it is the divided system clock that is output (CKOUT Fuse programmed). 5.9 Timer/Counter2 Oscillator For AVR microcontrollers with Timer/Counter2 Oscillator pins (TOSC1 and TOSC2), the crystal is connected directly between the pins. The Oscillator is optimized for use with a 32.768kHz watch crystal. 12-22 pF capacitors may be necessary if the parasitic impedance (pads, wires & PCB) is very low. 43 7679H–CAN–08/08

AT90CAN32/64/128 share the Timer/Counter2 Oscillator Pins (TOSC1 and TOSC2) with PG4 and PG3. This means that both PG4 and PG3 can only be used when the Timer/Counter2 Oscil- lator is not enable. Applying an external clock source to TOSC1 can be done in asynchronous operation if EXTCLK in the ASSR Register is written to logic one. See “Asynchronous operation of the Timer/Counter2” on page 160 for further description on selecting external clock as input instead of a 32 kHz crystal. In this configuration, PG4 cannot be used but PG3 is available. 5.10 System Clock Prescaler The AT90CAN32/64/128 system clock can be divided by setting the Clock Prescaler Register – CLKPR. This feature can be used to decrease power consumption when the requirement for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals. clk , clk , clk , and clk I/O ADC CPU FLASH are divided by a factor as shown in Table 5-12. 5.10.1 Clock Prescaler Register – CLKPR Bit 7 6 5 4 3 2 1 0 CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 CLKPR Read/Write R/W R R R R/W R/W R/W R/W Initial Value 0 0 0 0 <----- See Bit Description -----> • Bit 7 – CLKPCE: Clock Prescaler Change Enable The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is cleared by hardware four cycles after it is written or when CLKPS bits are written. Rewriting the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the CLKPCE bit. • Bit 6..0 – Reserved Bits These bits are reserved for future use. • Bits 3..0 – CLKPS3..0: Clock Prescaler Select Bits 3 - 0 These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchro- nous peripherals is reduced when a division factor is used. The division factors are given in Table 5-12. To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the CLKPS bits: 1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero. 2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE. Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted. The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to AT90CAN32/64/128 44 7679H–CAN–08/08

AT90CAN32/64/128 “0011”, giving a division factor of 8 at start up. This feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operat- ing conditions. Note that any value can be written to the CLKPS bits regardless of the CKDIV8 Fuse setting. The Application software must ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed. Table 5-12. Clock Prescaler Select CLKPS3 CLKPS2 CLKPS1 CLKPS0 Clock Division Factor 0 0 0 0 1 0 0 0 1 2 0 0 1 0 4 0 0 1 1 8 0 1 0 0 16 0 1 0 1 32 0 1 1 0 64 0 1 1 1 128 1 0 0 0 256 1 0 0 1 Reserved 1 0 1 0 Reserved 1 0 1 1 Reserved 1 1 0 0 Reserved 1 1 0 1 Reserved 1 1 1 0 Reserved 1 1 1 1 Reserved Note: The frequency of the asynchronous clock must be lower than 1/4th of the frequency of the scaled down Source clock. Otherwise, interrupts may be lost, and accessing the Timer/Counter2 regis- ters may fail. 45 7679H–CAN–08/08

6. Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consump- tion to the application’s requirements. To enter any of the five sleep modes, the SE bit in SMCR must be written to logic one and a SLEEP instruction must be executed. The SM2, SM1, and SM0 bits in the SMCR Register select which sleep mode (Idle, ADC Noise Reduction, Power-down, Power-save, or Standby) will be activated by the SLEEP instruction. See Table 6-1 for a summary. If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the register file and SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode, the MCU wakes up and exe- cutes from the Reset Vector. Figure 5-1 on page 37 presents the different clock systems in the AT90CAN32/64/128, and their distribution. The figure is helpful in selecting an appropriate sleep mode. 6.0.1 Sleep Mode Control Register – SMCR The Sleep Mode Control Register contains control bits for power management. Bit 7 6 5 4 3 2 1 0 – – – – SM2 SM1 SM0 SE SMCR Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 7..4 – Reserved Bits These bits are reserved for future use. • Bits 3..1 – SM2..0: Sleep Mode Select Bits 2, 1, and 0 These bits select between the five available sleep modes as shown in Table 6-1. Table 6-1. Sleep Mode Select SM2 SM1 SM0 Sleep Mode 0 0 0 Idle 0 0 1 ADC Noise Reduction 0 1 0 Power-down 0 1 1 Power-save 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Standby(1) 1 1 1 Reserved Note: 1. Standby mode is only recommended for use with external crystals or resonators. • Bit 1 – SE: Sleep Enable The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s AT90CAN32/64/128 46 7679H–CAN–08/08

AT90CAN32/64/128 purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately after waking up. 6.1 Idle Mode When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing SPI, CAN, USART, Analog Comparator, ADC, Two-wire Serial Interface, Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep mode basically halts clk and clk , while allowing the other clocks to run. CPU FLASH Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer Overflow and USART Transmit Complete interrupts. If wake-up from the Analog Comparator interrupt is not required, the Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automati- cally when this mode is entered. 6.2 ADC Noise Reduction Mode When the SM2..0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC Noise Reduction mode, stopping the CPU but allowing the ADC, the External Interrupts, the Two-wire Serial Interface address watch, Timer/Counter2, CAN and the Watchdog to continue operating (if enabled). This sleep mode basically halts clk , clk , and clk , while allowing I/O CPU FLASH the other clocks to run. This improves the noise environment for the ADC, enabling higher resolution measurements. If the ADC is enabled, a conversion starts automatically when this mode is entered. Apart from the ADC Conversion Complete interrupt, only an External Reset, a Watchdog Reset, a Brown-out Reset, a Two-wire Serial Interface address match interrupt, a Timer/Counter2 interrupt, an SPM/EEPROM ready interrupt, an External Level Interrupt on INT7:4, or an External Interrupt on INT3:0 can wake up the MCU from ADC Noise Reduction mode. 6.3 Power-down Mode When the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter Power- down mode. In this mode, the External Oscillator is stopped, while the External Interrupts, the Two-wire Serial Interface address watch, and the Watchdog continue operating (if enabled). Only an External Reset, a Watchdog Reset, a Brown-out Reset, a Two-wire Serial Interface address match interrupt, an External Level Interrupt on INT7:4, or an External Interrupt on INT3:0 can wake up the MCU. This sleep mode basically halts all generated clocks, allowing operation of asynchronous modules only. Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed level must be held for some time to wake up the MCU. Refer to “External Interrupts” on page 93 for details. When waking up from Power-down mode, there is a delay from the wake-up condition occurs until the wake-up becomes effective. This allows the clock to restart and become stable after having been stopped. The wake-up period is defined by the same CKSEL fuses that define the Reset Time-out period, as described in “Clock Sources” on page 38. 6.4 Power-save Mode When the SM2..0 bits are written to 011, the SLEEP instruction makes the MCU enter Power- save mode. This mode is identical to Power-down, with one exception: 47 7679H–CAN–08/08

If Timer/Counter2 is clocked asynchronously, i.e., the AS2 bit in ASSR is set, Timer/Counter2 will run during sleep. The device can wake up from either Timer Overflow or Output Compare event from Timer/Counter2 if the corresponding Timer/Counter2 interrupt enable bits are set in TIMSK2, and the global interrupt enable bit in SREG is set. If the Asynchronous Timer is NOT clocked asynchronously, Power-down mode is recommended instead of Power-save mode because the contents of the registers in the asynchronous timer should be considered undefined after wake-up in Power-save mode if AS2 is 0. This sleep mode basically halts all clocks except clk , allowing operation only of asynchronous ASY modules, including Timer/Counter2 if clocked asynchronously. 6.5 Standby Mode When the SM2..0 bits are 110 and an External Crystal/Resonator clock option is selected, the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down with the exception that the Oscillator is kept running. From Standby mode, the device wakes up in 6 clock cycles. Table 6-2. Active Clock Domains and Wake-up Sources in the Different Sleep Modes. Active Clock Domains Oscillators Wake-up Sources Main Timer TWI SPM/ Sleep Clock Timer Other clk clk clk clk clk Osc. INT7:0 Address EEPROM ADC Mode CPU FLASH IO ADC ASY Source 2 I/O Enabled Match Ready Enabled Idle X X X X X(2) X X X X X X ADC Noise X X X X(2) X(3) X X(2) X X Reduction Power- X(3) X down Power- X(2) X(2) X(3) X X(2) save Standby(1) X X(3) X Notes: 1. Only recommended with external crystal or resonator selected as clock source. 2. If AS2 bit in ASSR is set. 3. Only INT3:0 or level interrupt INT7:4. 6.6 Minimizing Power Consumption There are several issues to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possible of the device’s functions are operating. All functions not needed should be disabled. In particular, the following modules may need special consideration when trying to achieve the lowest possible power consumption. 6.6.1 Analog to Digital Converter If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be dis- abled before entering any sleep mode. When the ADC is turned off and on again, the next conversion will be an extended conversion. Refer to “Analog to Digital Converter - ADC” on page 273 for details on ADC operation. AT90CAN32/64/128 48 7679H–CAN–08/08

AT90CAN32/64/128 6.6.2 Analog Comparator When entering Idle mode, the Analog Comparator should be disabled if not used. When entering ADC Noise Reduction mode, the Analog Comparator should be disabled. In other sleep modes, the Analog Comparator is automatically disabled. However, if the Analog Comparator is set up to use the Internal Voltage Reference as input, the Analog Comparator should be disabled in all sleep modes. Otherwise, the Internal Voltage Reference will be enabled, independent of sleep mode. Refer to “Analog Comparator” on page 269 for details on how to configure the Analog Comparator. 6.6.3 Brown-out Detector If the Brown-out Detector is not needed by the application, this module should be turned off. If the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute sig- nificantly to the total current consumption. Refer to “Brown-out Detection” on page 54 for details on how to configure the Brown-out Detector. 6.6.4 Internal Voltage Reference The Internal Voltage Reference will be enabled when needed by the Brown-out Detection, the Analog Comparator or the ADC. If these modules are disabled as described in the sections above, the internal voltage reference will be disabled and it will not be consuming power. When turned on again, the user must allow the reference to start up before the output is used. If the reference is kept on in sleep mode, the output can be used immediately. Refer to “Internal Volt- age Reference” on page 56 for details on the start-up time. 6.6.5 Watchdog Timer If the Watchdog Timer is not needed in the application, the module should be turned off. If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consump- tion. Refer to “Watchdog Timer” on page 57 for details on how to configure the Watchdog Timer. 6.6.6 Port Pins When entering a sleep mode, all port pins should be configured to use minimum power. The most important is then to ensure that no pins drive resistive loads. In sleep modes where both the I/O clock (clk ) and the ADC clock (clk ) are stopped, the input buffers of the device will I/O ADC be disabled. This ensures that no power is consumed by the input logic when not needed. In some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled. Refer to the section “Digital Input Enable and Sleep Modes” on page 70 for details on which pins are enabled. If the input buffer is enabled and the input signal is left floating or have an analog signal level close to V /2, the input buffer will use excessive power. CC For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close to V /2 on an input pin can cause significant current even in active mode. Digital CC input buffers can be disabled by writing to the Digital Input Disable Registers (DIDR1 and DIDR0). Refer to “Digital Input Disable Register1 – DIDR1” on page 272 and “Digital Input Dis- able Register0 – DIDR0” on page 292 for details. 6.6.7 JTAG Interface and On-chipDebugSystem If the On-chip debug system is enabled by OCDEN Fuse and the chip enter sleep mode, the main clock source is enabled, and hence, always consumes power. In the deeper sleep modes, 49 7679H–CAN–08/08

this will contribute significantly to the total current consumption. There are three alternative ways to avoid this: • Disable OCDEN Fuse. • Disable JTAGEN Fuse. • Write one to the JTD bit in MCUCR. The TDO pin is left floating when the JTAG interface is enabled while the JTAG TAP controller is not shifting data. If the hardware connected to the TDO pin does not pull up the logic level, power consumption will increase. Note that the TDI pin for the next device in the scan chain con- tains a pull-up that avoids this problem. Writing the JTD bit in the MCUCR register to one or leaving the JTAG fuse unprogrammed disables the JTAG interface. AT90CAN32/64/128 50 7679H–CAN–08/08

AT90CAN32/64/128 7. System Control and Reset 7.1 Reset 7.1.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – Absolute Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. The circuit diagram in Figure 7-1 shows the reset logic. Table 7-1 defines the electrical parameters of the reset circuitry. The I/O ports of the AVR are immediately reset to their initial state when a reset source goes active. This does not require any clock source to be running. After all reset sources have gone inactive, a delay counter is invoked, stretching the internal reset. This allows the power to reach a stable level before normal operation starts. The time-out period of the delay counter is defined by the user through the SUT and CKSEL Fuses. The dif- ferent selections for the delay period are presented in “Clock Sources” on page 38. 7.1.2 Reset Sources The AT90CAN32/64/128 has five sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V ). POT • External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length. • Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the Watchdog is enabled. • Brown-out Reset. The MCU is reset when the supply voltage V is below the Brown-out CC Reset threshold (V ) and the Brown-out Detector is enabled. BOT • JTAG AVR Reset. The MCU is reset as long as there is a logic one in the Reset Register, one of the scan chains of the JTAG system. Refer to the section “Boundary-scan IEEE 1149.1 (JTAG)” on page 300 for details. 51 7679H–CAN–08/08

Figure 7-1. Reset Logic DATA BUS MCU Status Register (MCUSR) FFFFF RRRRR OOTDT Power-on Reset PBEXWJ Circuit Brown-out BODLEVEL [2..0] Reset Circuit Pull-up Resistor Spike Filter JTAG Reset Register Watchdog Oscillator Clock CK Delay Counters TIMEOUT Generator CKSEL[3:0] SUT[1:0] Table 7-1. Reset Characteristics Symbol Parameter Condition Min. Typ. Max. Units Power-on Reset Threshold Voltage (rising) 1.4 2.3 V V POT Power-on Reset Threshold Voltage (falling)(1) 1.3 2.3 V Vcc Start Voltage to ensure V - 0.05 GND + 0.05 V POR internal Power-on Reset signal Vcc Rise Rate to ensure V 0.3 V/ms CCRR internal Power-on Reset signal 0.2 0.85 V RESET Pin Threshold Voltage V RST Vcc Vcc t Minimum pulse width on RESET Pin Vcc = 5 V, temperature = 25 °C 400 ns RST Note: 1. The Power-on Reset will not work unless the supply voltage has been below V (falling) POT 7.1.3 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in Table 7-1. The POR is activated whenever V is below the detection level. The CC POR circuit can be used to trigger the start-up Reset, as well as to detect a failure in supply voltage. A Power-on Reset (POR) circuit ensures that the device is properly reset from Power-on if V CC started from V with a rise rate upper than V . Reaching the Power-on Reset threshold POR CCRR voltage invokes the delay counter, which determines how long the device is kept in RESET after AT90CAN32/64/128 52 7679H–CAN–08/08

AT90CAN32/64/128 V rise. The RESET signal is activated again, without any delay, when V decreases below CC CC the detection level. Figure 7-2. MCU Start-up, RESET Tied to V CC V CCRR V CC V V POT POR RESET V CCRR TIME-OUT tTOUT INTERNAL RESET Figure 7-3. MCU Start-up, RESET Extended Externally V CCRR V CC V POR RESET V RST TIME-OUT tTOUT INTERNAL RESET Note: If V or V parameter range can not be followed, an External Reset is required. POR CCRR 7.1.4 External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see Table 7-1) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage – V – on its positive edge, the delay counter starts the MCU after RST the Time-out period – t –has expired. TOUT 53 7679H–CAN–08/08

Figure 7-4. External Reset During Operation CC 7.1.5 Brown-out Detection AT90CAN32/64/128 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V CC level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as V = BOT+ V + V /2 and V = V - V /2. BOT HYST BOT- BOT HYST Table 7-2. BODLEVEL Fuse Coding(1) BODLEVEL 2..0 Fuses Min V Typ V Max V Units BOT BOT BOT 111 BOD Disabled 110 4.1 V 101 4.0 V 100 3.9 V 011 3.8 V 010 2.7 V 001 2.6 V 000 2.5 V Note: 1. V may be below nominal minimum operating voltage for some devices. For devices where BOT this is the case, the device is tested down to V = V during the production test. This guar- CC BOT antees that a Brown-Out Reset will occur before V drops to a voltage where correct CC operation of the microcontroller is no longer guaranteed. The test is performed using BODLEVEL=010 for Low Operating Voltage and BODLEVEL=101 for High Operating Volt- age . Table 7-3. Brown-out Characteristics Symbol Parameter Min. Typ. Max. Units V Brown-out Detector Hysteresis 70 mV HYST t Min Pulse Width on Brown-out Reset 2 µs BOD When the BOD is enabled, and V decreases to a value below the trigger level (V in Figure CC BOT- 7-5), the Brown-out Reset is immediately activated. When V increases above the trigger level CC AT90CAN32/64/128 54 7679H–CAN–08/08

AT90CAN32/64/128 (V in Figure 7-5), the delay counter starts the MCU after the Time-out period t has BOT+ TOUT expired. The BOD circuit will only detect a drop in VCC if the voltage stays below the trigger level for longer than t given in Table 7-3. BOD Figure 7-5. Brown-out Reset During Operation V V CC V BOT+ BOT- RESET TIME-OUT tTOUT INTERNAL RESET 7.1.6 Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period t . Refer to TOUT page 57 for details on operation of the Watchdog Timer. Figure 7-6. Watchdog Reset During Operation CC CK 55 7679H–CAN–08/08

7.1.7 MCU Status Register – MCUSR The MCU Status Register provides information on which reset source caused an MCU reset. Bit 7 6 5 4 3 2 1 0 – – – JTRF WDRF BORF EXTRF PORF MCUSR Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 See Bit Description • Bit 7..5 – Reserved Bits These bits are reserved for future use. • Bit 4 – JTRF: JTAG Reset Flag This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic zero to the flag. • Bit 3 – WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. • Bit 2 – BORF: Brown-out Reset Flag This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. • Bit 1 – EXTRF: External Reset Flag This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. • Bit 0 – PORF: Power-on Reset Flag This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the Reset flags to identify a reset condition, the user should read and then reset the MCUSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags. 7.2 Internal Voltage Reference AT90CAN32/64/128 features an internal bandgap reference. This reference is used for Brown- out Detection, and it can be used as an input to the Analog Comparator or the ADC. 7.2.1 Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given in Table 7-4. To save power, the reference is not always turned on. The reference is on during the following situations: 1. When the BOD is enabled (by programming the BODLEVEL [2..0] Fuse). 2. When the bandgap reference is connected to the Analog Comparator (by setting the ACBG bit in ACSR). 3. When the ADC is enabled. Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user must always allow the reference to start up before the output from the Analog Comparator or AT90CAN32/64/128 56 7679H–CAN–08/08

AT90CAN32/64/128 ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering Power-down mode. 7.2.2 Voltage Reference Characteristics Table 7-4. Internal Voltage Reference Characteristics Symbol Parameter Condition Min. Typ. Max. Units V Bandgap reference voltage 1.0 1.1 1.2 V BG t Bandgap reference start-up time 40 70 µs BG Bandgap reference current I 15 µA BG consumption 7.3 Watchdog Timer The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1MHz. This is the typical value at V = 5V. See characterization data for typical values at other V levels. By CC CC controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as shown in Table 7-6 on page 58. The WDR – Watchdog Reset – instruction resets the Watchdog Timer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs. Eight different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog Reset, the AT90CAN32/64/128 resets and executes from the Reset Vector. For timing details on the Watchdog Reset, refer to Table 7-6 on page 58. To prevent unintentional disabling of the Watchdog or unintentional change of time-out period, two different safety levels are selected by the fuse WDTON as shown in Table 7-5. Refer to “Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 59 for details. Table 7-5. WDT Configuration as a Function of the Fuse Settings of WDTON Safety WDT Initial How to Disable How to Change WDTON Level State the WDT Time-out Unprogrammed 1 Disabled Timed sequence Timed sequence Programmed 2 Enabled Always enabled Timed sequence Figure 7-7. Watchdog Timer WATCHDOG OSCILLATOR ~1 MHz 57 7679H–CAN–08/08

7.3.1 Watchdog Timer Control Register – WDTCR Bit 7 6 5 4 3 2 1 0 – – – WDCE WDE WDP2 WDP1 WDP0 WDTCR Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bits 7..5 – Reserved Bits These bits are reserved bits for future use. • Bit 4 – WDCE: Watchdog Change Enable This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not be disabled. Once written to one, hardware will clear this bit after four clock cycles. Refer to the description of the WDE bit for a Watchdog disable procedure. This bit must also be set when changing the prescaler bits. See “Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 59. • Bit 3 – WDE: Watchdog Enable When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared if the WDCE bit has logic level one. To disable an enabled Watchdog Timer, the following procedure must be followed: 1. In the same operation, write a logic one to WDCE and WDE. A logic one must be writ- ten to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog. In safety level 2, it is not possible to disable the Watchdog Timer, even with the algorithm described above. See “Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 59. • Bits 2..0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0 The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when the Watch- dog Timer is enabled. The different prescaling values and their corresponding Timeout Periods are shown in Table 7-6. Table 7-6. Watchdog Timer Prescale Select Number of WDT Typical Time-out at Typical Time-out at WDP2 WDP1 WDP0 Oscillator Cycles V = 3.0V V = 5.0V CC CC 0 0 0 16K cycles 17.1 ms 16.3 ms 0 0 1 32K cycles 34.3 ms 32.5 ms 0 1 0 64K cycles 68.5 ms 65 ms 0 1 1 32/64K cycles 0.14 s 0.13 s 1 0 0 256K cycles 0.27 s 0.26 s 1 0 1 512K cycles 0.55 s 0.52 s 1 1 0 1,024K cycles 1.1 s 1.0 s 1 1 1 2,048K cycles 2.2 s 2.1 s AT90CAN32/64/128 58 7679H–CAN–08/08

AT90CAN32/64/128 The following code example shows one assembly and one C function for turning off the WDT. The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions. Assembly Code Example(1) WDT_off: ; Write logical one to WDCE and WDE ldi r16, (1<<WDCE)|(1<<WDE) sts WDTCR, r16 ; Turn off WDT ldi r16, (0<<WDE) sts WDTCR, r16 ret C Code Example(1) void WDT_off(void) { /* Write logical one to WDCE and WDE */ WDTCR = (1<<WDCE) | (1<<WDE); /* Turn off WDT */ WDTCR = 0x00; } Note: 1. The example code assumes that the part specific header file is included. 7.4 Timed Sequences for Changing the Configuration of the Watchdog Timer The sequence for changing configuration differs slightly between the two safety levels. Separate procedures are described for each level. 7.4.1 Safety Level 1 In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit to 1 without any restriction. A timed sequence is needed when changing the Watchdog Time-out period or disabling an enabled Watchdog Timer. To disable an enabled Watchdog Timer, and/or changing the Watchdog Time-out, the following procedure must be followed: 1. In the same operation, write a logic one to WDCE and WDE. A logic one must be writ- ten to WDE regardless of the previous value of the WDE bit. 2. Within the next four clock cycles, in the same operation, write the WDE and WDP bits as desired, but with the WDCE bit cleared. 7.4.2 Safety Level 2 In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as one. A timed sequence is needed when changing the Watchdog Time-out period. To change the Watchdog Time-out, the following procedure must be followed: 1. In the same operation, write a logical one to WDCE and WDE. Even though the WDE always is set, the WDE must be written to one to start the timed sequence. 2. Within the next four clock cycles, in the same operation, write the WDP bits as desired, but with the WDCE bit cleared. The value written to the WDE bit is irrelevant. 59 7679H–CAN–08/08

8. Interrupts This section describes the specifics of the interrupt handling as performed in AT90CAN32/64/128. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 15. 8.1 Interrupt Vectors in AT90CAN32/64/128 Table 8-1. Reset and Interrupt Vectors Vector Program Source Interrupt Definition No. Address(1) External Pin, Power-on Reset, Brown-out Reset, 1 0x0000(2) RESET Watchdog Reset, and JTAG AVR Reset 2 0x0002 INT0 External Interrupt Request 0 3 0x0004 INT1 External Interrupt Request 1 4 0x0006 INT2 External Interrupt Request 2 5 0x0008 INT3 External Interrupt Request 3 6 0x000A INT4 External Interrupt Request 4 7 0x000C INT5 External Interrupt Request 5 8 0x000E INT6 External Interrupt Request 6 9 0x0010 INT7 External Interrupt Request 7 10 0x0012 TIMER2 COMP Timer/Counter2 Compare Match 11 0x0014 TIMER2 OVF Timer/Counter2 Overflow 12 0x0016 TIMER1 CAPT Timer/Counter1 Capture Event 13 0x0018 TIMER1 COMPA Timer/Counter1 Compare Match A 14 0x001A TIMER1 COMPB Timer/Counter1 Compare Match B 15 0x001C TIMER1 COMPC Timer/Counter1 Compare Match C 16 0x001E TIMER1 OVF Timer/Counter1 Overflow 17 0x0020 TIMER0 COMP Timer/Counter0 Compare Match 18 0x0022 TIMER0 OVF Timer/Counter0 Overflow 19 0x0024 CANIT CAN Transfer Complete or Error 20 0x0026 OVRIT CAN Timer Overrun 21 0x0028 SPI, STC SPI Serial Transfer Complete 22 0x002A USART0, RX USART0, Rx Complete 23 0x002C USART0, UDRE USART0 Data Register Empty 24 0x002E USART0, TX USART0, Tx Complete 25 0x0030 ANALOG COMP Analog Comparator 26 0x0032 ADC ADC Conversion Complete 27 0x0034 EE READY EEPROM Ready 28 0x0036 TIMER3 CAPT Timer/Counter3 Capture Event AT90CAN32/64/128 60 7679H–CAN–08/08

AT90CAN32/64/128 Table 8-1. Reset and Interrupt Vectors (Continued) Vector Program Source Interrupt Definition No. Address(1) 29 0x0038 TIMER3 COMPA Timer/Counter3 Compare Match A 30 0x003A TIMER3 COMPB Timer/Counter3 Compare Match B 31 0x003C TIMER3 COMPC Timer/Counter3 Compare Match C 32 0x003E TIMER3 OVF Timer/Counter3 Overflow 33 0x0040 USART1, RX USART1, Rx Complete 34 0x0042 USART1, UDRE USART1 Data Register Empty 35 0x0044 USART1, TX USART1, Tx Complete 36 0x0046 TWI Two-wire Serial Interface 37 0x0048 SPM READY Store Program Memory Ready Notes: 1. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot Flash Section. The address of each Interrupt Vector will then be the address in this table added to the start address of the Boot Flash Section. 2. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at reset, see “Boot Loader Support – Read-While-Write Self-Programming” on page 321. Table 8-2 shows reset and Interrupt Vectors placement for the various combinations of BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. Table 8-2. Reset and Interrupt Vectors Placement(1) BOOTRST IVSEL Reset Address Interrupt Vectors Start Address 1 0 0x0000 0x0002 1 1 0x0000 Boot Reset Address + 0x0002 0 0 Boot Reset Address 0x0002 0 1 Boot Reset Address Boot Reset Address + 0x0002 Note: 1. The Boot Reset Address is shown in Table 24-6 on page 334. For the BOOTRST Fuse “1” means unprogrammed while “0” means programmed. The most typical and general program setup for the Reset and Interrupt Vector Addresses in AT90CAN32/64/128 is: ;Address Labels Code Comments 0x0000 jmp RESET ; Reset Handler 0x0002 jmp EXT_INT0 ; IRQ0 Handler 0x0004 jmp EXT_INT1 ; IRQ1 Handler 0x0006 jmp EXT_INT2 ; IRQ2 Handler 0x0008 jmp EXT_INT3 ; IRQ3 Handler 0x000A jmp EXT_INT4 ; IRQ4 Handler 0x000C jmp EXT_INT5 ; IRQ5 Handler 0x000E jmp EXT_INT6 ; IRQ6 Handler 0x0010 jmp EXT_INT7 ; IRQ7 Handler 61 7679H–CAN–08/08

0x0012 jmp TIM2_COMP ; Timer2 Compare Handler 0x0014 jmp TIM2_OVF ; Timer2 Overflow Handler 0x0016 jmp TIM1_CAPT ; Timer1 Capture Handler 0x0018 jmp TIM1_COMPA; Timer1 CompareA Handler 0x001A jmp TIM1_COMPB; Timer1 CompareB Handler 0x001C jmp TIM1_OVF ; Timer1 CompareC Handler 0x001E jmp TIM1_OVF ; Timer1 Overflow Handler 0x0020 jmp TIM0_COMP ; Timer0 Compare Handler 0x0022 jmp TIM0_OVF ; Timer0 Overflow Handler 0x0024 jmp CAN_IT ; CAN Handler 0x0026 jmp CTIM_OVF ; CAN Timer Overflow Handler 0x0028 jmp SPI_STC ; SPI Transfer Complete Handler 0x002A jmp USART0_RXC; USART0 RX Complete Handler 0x002C jmp USART0_DRE; USART0,UDR Empty Handler 0x002E jmp USART0_TXC; USART0 TX Complete Handler 0x0030 jmp ANA_COMP ; Analog Comparator Handler 0x0032 jmp ADC ; ADC Conversion Complete Handler 0x0034 jmp EE_RDY ; EEPROM Ready Handler 0x0036 jmp TIM3_CAPT ; Timer3 Capture Handler 0x0038 jmp TIM3_COMPA; Timer3 CompareA Handler 0x003A jmp TIM3_COMPB; Timer3 CompareB Handler 0x003C jmp TIM3_COMPC; Timer3 CompareC Handler 0x003E jmp TIM3_OVF ; Timer3 Overflow Handler 0x0040 jmp USART1_RXC; USART1 RX Complete Handler 0x0042 jmp USART1_DRE; USART1,UDR Empty Handler 0x0044 jmp USART1_TXC; USART1 TX Complete Handler 0x0046 jmp TWI ; TWI Interrupt Handler 0x0048 jmp SPM_RDY ; SPM Ready Handler ; 0x004A RESET: ldi r16, high(RAMEND) ; Main program start 0x004B out SPH,r16 ;Set Stack Pointer to top of RAM 0x004C ldi r16, low(RAMEND) 0x004D out SPL,r16 0x004E sei ; Enable interrupts 0x004F <instr> xxx ... ... ... ... When the BOOTRST Fuse is unprogrammed, the Boot section size set to 8K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: ;AddressLabels Code Comments 0x0000 RESET: ldi r16,high(RAMEND) ; Main program start 0x0001 out SPH,r16 ; Set Stack Pointer to top of RAM 0x0002 ldi r16,low(RAMEND) 0x0003 out SPL,r16 AT90CAN32/64/128 62 7679H–CAN–08/08

AT90CAN32/64/128 0x0004 sei ; Enable interrupts 0x0005 <instr> xxx ; .org (BootResetAdd + 0x0002) 0x..02 jmp EXT_INT0 ; IRQ0 Handler 0x..04 jmp PCINT0 ; PCINT0 Handler ... ... ... ; 0x..0C jmp SPM_RDY ; Store Program Memory Ready Handler When the BOOTRST Fuse is programmed and the Boot section size set to 8K bytes, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: ;AddressLabels Code Comments .org 0x0002 0x0002 jmp EXT_INT0 ; IRQ0 Handler 0x0004 jmp PCINT0 ; PCINT0 Handler ... ... ... ; 0x002C jmp SPM_RDY ; Store Program Memory Ready Handler ; .org (BootResetAdd) 0x..00 RESET: ldi r16,high(RAMEND) ; Main program start 0x..01 out SPH,r16 ; Set Stack Pointer to top of RAM 0x..02 ldi r16,low(RAMEND) 0x..03 out SPL,r16 0x..04 sei ; Enable interrupts 0x..05 <instr> xxx When the BOOTRST Fuse is programmed, the Boot section size set to 8K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: ;AddressLabels Code Comments ; .org (BootResetAdd) 0x..00 jmp RESET ; Reset handler 0x0002 jmp EXT_INT0 ; IRQ0 Handler 0x..04 jmp PCINT0 ; PCINT0 Handler ... ... ... ; 0x..44 jmp SPM_RDY ; Store Program Memory Ready Handler ; 0x..46 RESET: ldi r16,high(RAMEND) ; Main program start 0x..47 out SPH,r16 ; Set Stack Pointer to top of RAM 0x..48 ldi r16,low(RAMEND) 0x..49 out SPL,r16 0x..4A sei ; Enable interrupts 0x..4B <instr> xxx 63 7679H–CAN–08/08

8.2 Moving Interrupts Between Application and Boot Space The General Interrupt Control Register controls the placement of the Interrupt Vector table. 8.2.1 MCU Control Register – MCUCR Bit 7 6 5 4 3 2 1 0 JTD – – PUD – – IVSEL IVCE MCUCR Read/Write R/W R R R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 1 – IVSEL: Interrupt Vector Select When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot Loader section of the Flash. The actual address of the start of the Boot Flash Section is deter- mined by the BOOTSZ Fuses. Refer to the section “Boot Loader Support – Read-While-Write Self- Programming” on page 321 for details. To avoid unintentional changes of Interrupt Vector tables, a special write procedure must be followed to change the IVSEL bit: 1. Write the Interrupt Vector Change Enable (IVCE) bit to one. 2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE. Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the cycle IVCE is set, and they remain disabled until after the instruction following the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status Register is unaffected by the automatic disabling. Note: If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is pro- grammed, interrupts are disabled while executing from the Application section. If Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts are dis- abled while executing from the Boot Loader section. Refer to the section “Boot Loader Support – Read-While-Write Self-Programming” on page 321 for details on Boot Lock bits. AT90CAN32/64/128 64 7679H–CAN–08/08

AT90CAN32/64/128 • Bit 0 – IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above. See Code Example below. Assembly Code Example Move_interrupts: ; Get MCUCR in r16, MCUCR mov r17, r16 ; Enable change of Interrupt Vectors ori r16, (1<<IVCE) out MCUCR, r16 ; Move interrupts to Boot Flash section ori r17, (1<<IVSEL) out MCUCR, r17 ret C Code Example void Move_interrupts(void) { uchar temp; /* Get MCUCR*/ temp = MCUCR; /* Enable change of Interrupt Vectors */ MCUCR = temp | (1<<IVCE); /* Move interrupts to Boot Flash section */ MCUCR = temp | (1<<IVSEL); } 65 7679H–CAN–08/08

9. I/O-Ports 9.1 Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when chang- ing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input). Each output buffer has symmetrical drive characteristics with both high sink and source capability. All port pins have individually selectable pull-up resistors with a supply-voltage invari- ant resistance. All I/O pins have protection diodes to both V and Ground as indicated in Figure CC 9-1. Refer to “Electrical Characteristics (1)” on page 365 for a complete list of parameters. Figure 9-1. I/O Pin Equivalent Schematic R pu Pxn Logic C pin See Figure "General Digital I/O" for Details All registers and bit references in this section are written in general form. A lower case “x” repre- sents the numbering letter for the port, and a lower case “n” represents the bit number. However, when using the register or bit defines in a program, the precise form must be used. For example, PORTB3 for bit no. 3 in Port B, here documented generally as PORTxn. The physical I/O Regis- ters and bit locations are listed in “Register Description for I/O-Ports”. Three I/O memory address locations are allocated for each port, one each for the Data Register – PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx. The Port Input Pins I/O location is read only, while the Data Register and the Data Direction Register are read/write. However, writing a logic one to a bit in the PINx Register, will result in a toggle in the correspond- ing bit in the Data Register. In addition, the Pull-up Disable – PUD bit in MCUCR disables the pull-up function for all pins in all ports when set. Using the I/O port as General Digital I/O is described in “Ports as General Digital I/O”. Most port pins are multiplexed with alternate functions for the peripheral features on the device. How each alternate function interferes with the port pin is described in “Alternate Port Functions” on page 71. Refer to the individual module sections for a full description of the alternate functions. Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. AT90CAN32/64/128 66 7679H–CAN–08/08

AT90CAN32/64/128 9.2 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 9-2 shows a func- tional description of one I/O-port pin, here generically called Pxn. Figure 9-2. General Digital I/O(1) PUD Q D DDxn QCLR WDx RESET RDx S U 1 B Pxn Q D A PORTxn 0 T QCLR DA WPx RESET WRx SLEEP RRx SYNCHRONIZER RPx D Q D Q PINxn L Q Q clk I/O WDx: WRITE DDRx PUD: PULLUP DISABLE RDx: READ DDRx SLEEP: SLEEP CONTROL WRx: WRITE PORTx clkI/O: I/O CLOCK RRx: READ PORTx REGISTER RPx: READ PORTx PIN WPx: WRITE PINx REGISTER Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk , I/O SLEEP, and PUD are common to all ports. 9.2.1 Configuring the Pin Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in “Register Description for I/O-Ports” on page 89, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx I/O address. The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one, Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin. If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to be configured as an output pin The port pins are tri-stated when reset condition becomes active, even if no clocks are running. 67 7679H–CAN–08/08

If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). 9.2.2 Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port. 9.2.3 Switching Between Input and Output When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) occurs. Normally, the pull-up enabled state is fully acceptable, as a high-impedant environment will not notice the difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the MCUCR Register can be set to disable all pull- ups in all ports. Switching between input with pull-up and output low generates the same problem. The user must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn} = 0b11) as an intermediate step. Table 9-1 summarizes the control signals for the pin value. Table 9-1. Port Pin Configurations PUD DDxn PORTxn I/O Pull-up Comment (in MCUCR) Default configuration after Reset. 0 0 X Input No Tri-state (Hi-Z) 0 1 0 Input Yes Pxn will source current if ext. pulled low. 0 1 1 Input No Tri-state (Hi-Z) 1 0 X Output No Output Low (Sink) 1 1 X Output No Output High (Source) 9.2.4 Reading the Pin Value Independent of the setting of Data Direction bit DDxn, the port pin can be read through the PINxn Register bit. As shown in Figure 9-2, the PINxn Register bit and the preceding latch con- stitute a synchronizer. This is needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a delay. Figure 9-3 shows a timing dia- gram of the synchronization when reading an externally applied pin value. The maximum and minimum propagation delays are denoted t and t respectively. pd,max pd,min AT90CAN32/64/128 68 7679H–CAN–08/08

AT90CAN32/64/128 Figure 9-3. Synchronization when Reading an Externally Applied Pin value SYSTEM CLK INSTRUCTIONS XXX XXX in r17, PINx SYNC LATCH PINxn r17 0x00 0xFF t pd, max tpd, min Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indi- cated by the two arrows t and t , a single signal transition on the pin will be delayed pd,max pd,min between ½ and 1½ system clock period depending upon the time of assertion. When reading back a software assigned pin value, a nop instruction must be inserted as indi- cated in Figure 9-4. The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock. In this case, the delay t through the synchronizer is 1 system clock period. pd Figure 9-4. Synchronization when Reading a Software Assigned Pin Value SYSTEM CLK r16 0xFF INSTRUCTIONS out PORTx, r16 nop in r17, PINx SYNC LATCH PINxn r17 0x00 0xFF t pd 69 7679H–CAN–08/08

The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. Assembly Code Example(1) ... ; Define pull-ups and set outputs high ; Define directions for port pins ldi r16, (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0) ldi r17, (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0) out PORTB, r16 out DDRB, r17 ; Insert nop for synchronization nop ; Read port pins in r16, PINB ... C Code Example(1) unsigned char i; ... /* Define pull-ups and set outputs high */ /* Define directions for port pins */ PORTB = (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0); DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0); /* Insert nop for synchronization*/ _NOP(); /* Read port pins */ i = PINB; ... Note: 1. For the assembly program, two temporary registers are used to minimize the time from pull- ups are set on pins 0, 1, 6, and 7, until the direction bits are correctly set, defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers. 9.2.5 Digital Input Enable and Sleep Modes As shown in Figure 9-2, the digital input signal can be clamped to ground at the input of the schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down mode, Power-save mode, and Standby mode to avoid high power consumption if some input signals are left floating, or have an analog signal level close to V /2. CC SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt request is not enabled, SLEEP is active also for these pins. SLEEP is also overridden by various other alternate functions as described in “Alternate Port Functions” on page 71. If a logic high level (“one”) is present on an Asynchronous External Interrupt pin configured as “Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt is not enabled, the corresponding External Interrupt Flag will be set when resuming from the AT90CAN32/64/128 70 7679H–CAN–08/08

AT90CAN32/64/128 above mentioned sleep modes, as the clamping in these sleep modes produces the requested logic change. 9.2.6 Unconnected Pins If some pins are unused, it is recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, float- ing inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode). The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up. In this case, the pull-up will be disabled during reset. If low power consumption during reset is important, it is recommended to use an external pull-up or pull-down. Connecting unused pins directly to VCC or GND is not rec- ommended, since this may cause excessive currents if the pin is accidentally configured as an output. 9.3 Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. Figure 9-5 shows how the port pin control signals from the simplified Figure 9-2 can be overridden by alternate functions. The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family. 71 7679H–CAN–08/08

Figure 9-5. Alternate Port Functions(1) PUOExn PUOVxn 1 PUD 0 DDOExn DDOVxn 1 0 Q D DDxn QCLR WDx PVOExn RESET RDx PVOVxn S U Pxn 1 1 B 0 Q D 0 A PORTxn T DIEOExn QCLR PTOExn DA WPx DIEOVxn RESET 1 WRx RRx 0 SLEEP SYNCHRONIZER RPx DSETQ D Q PINxn LCLRQ CLRQ clkI/O DIxn AIOxn PUOExn: Pxn PULL-UP OVERRIDE ENABLE PUD: PULLUP DISABLE PUOVxn: Pxn PULL-UP OVERRIDE VALUE WDx : WRITE DDRx DDOExn: Pxn DATA DIRECTION OVERRIDE ENABLE RDx : READ DDRx DDOVxn: Pxn DATA DIRECTION OVERRIDE VALUE RRx : READ PORTx REGISTER PVOExn: Pxn PORT VALUE OVERRIDE ENABLE WRx : WRITE PORTx PVOVxn: Pxn PORT VALUE OVERRIDE VALUE RPx : READ PORTx PIN DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE WPx: WRITE PINx DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE clk : I/O CLOCK I/O SLEEP: SLEEP CONTROL DIxn : DIGITAL INPUT PIN n ON PORTx PTOExn: Pxn, PORT TOGGLE OVERRIDE ENABLE AIOxn : ANALOG INPUT/OUTPUT PIN n ON PORTx Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk , I/O SLEEP, and PUD are common to all ports. All other signals are unique for each pin. Table 9-2 summarizes the function of the overriding signals. The pin and port indexes from Figure 9-5 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function. AT90CAN32/64/128 72 7679H–CAN–08/08

AT90CAN32/64/128 Table 9-2. Generic Description of Overriding Signals for Alternate Functions Signal Name Full Name Description If this signal is set, the pull-up enable is controlled by the PUOV Pull-up Override PUOE signal. If this signal is cleared, the pull-up is enabled when Enable {DDxn, PORTxn, PUD} = 0b010. If PUOE is set, the pull-up is enabled/disabled when PUOV is Pull-up Override PUOV set/cleared, regardless of the setting of the DDxn, PORTxn, Value and PUD Register bits. If this signal is set, the Output Driver Enable is controlled by the Data Direction DDOE DDOV signal. If this signal is cleared, the Output driver is Override Enable enabled by the DDxn Register bit. If DDOE is set, the Output Driver is enabled/disabled when Data Direction DDOV DDOV is set/cleared, regardless of the setting of the DDxn Override Value Register bit. If this signal is set and the Output Driver is enabled, the port Port Value value is controlled by the PVOV signal. If PVOE is cleared, and PVOE Override Enable the Output Driver is enabled, the port Value is controlled by the PORTxn Register bit. Port Value If PVOE is set, the port value is set to PVOV, regardless of the PVOV Override Value setting of the PORTxn Register bit. Port Toggle PTOE If PTOE is set, the PORTxn Register bit is inverted. Override Enable Digital Input If this bit is set, the Digital Input Enable is controlled by the DIEOE Enable Override DIEOV signal. If this signal is cleared, the Digital Input Enable Enable is determined by MCU state (Normal mode, sleep mode). Digital Input If DIEOE is set, the Digital Input is enabled/disabled when DIEOV Enable Override DIEOV is set/cleared, regardless of the MCU state (Normal Value mode, sleep mode). This is the Digital Input to alternate functions. In the figure, the signal is connected to the output of the schmitt trigger but DI Digital Input before the synchronizer. Unless the Digital Input is used as a clock source, the module with the alternate function will use its own synchronizer. This is the Analog Input/output to/from alternate functions. The Analog AIO signal is connected directly to the pad, and can be used bi- Input/Output directionally. The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for further details. 9.3.1 MCU Control Register – MCUCR Bit 7 6 5 4 3 2 1 0 JTD – – PUD – – IVSEL IVCE MCUCR Read/Write R/W R R R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 73 7679H–CAN–08/08

• Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See “Con- figuring the Pin” for more details about this feature. 9.3.2 Alternate Functions of Port A The Port A has an alternate function as the address low byte and data lines for the External Memory Interface. The Port A pins with alternate functions are shown in Table 9-3. Table 9-3. Port A Pins Alternate Functions Port Pin Alternate Function PA7 AD7 (External memory interface address and data bit 7) PA6 AD6 (External memory interface address and data bit 6) PA5 AD5 (External memory interface address and data bit 5) PA4 AD4 (External memory interface address and data bit 4) PA3 AD3 (External memory interface address and data bit 3) PA2 AD2 (External memory interface address and data bit 2) PA1 AD1 (External memory interface address and data bit 1) PA0 AD0 (External memory interface address and data bit 0) The alternate pin configuration is as follows: • AD7 – Port A, Bit 7 AD7, External memory interface address 7 and Data 7. • AD6 – Port A, Bit 6 AD6, External memory interface address 6 and Data 6. • AD5 – Port A, Bit 5 AD5, External memory interface address 5 and Data 5. • AD4 – Port A, Bit 4 AD4, External memory interface address 4 and Data 4. • AD3 – Port A, Bit 3 AD3, External memory interface address 3 and Data 3. • AD2 – Port A, Bit 2 AD2, External memory interface address 2 and Data 2. • AD1 – Port A, Bit 1 AD1, External memory interface address 1 and Data 1. • AD0 – Port A, Bit 0 AD0, External memory interface address 0 and Data 0. AT90CAN32/64/128 74 7679H–CAN–08/08

AT90CAN32/64/128 Table 9-4 and Table 9-5 relates the alternate functions of Port A to the overriding signals shown in Figure 9-5 on page 72. Table 9-4. Overriding Signals for Alternate Functions in PA7..PA4 Signal Name PA7/AD7 PA6/AD6 PA5/AD5 PA4/AD4 SRE • SRE • SRE • SRE • PUOE (ADA(1) + WR) (ADA(1) + WR) (ADA(1) + WR) (ADA(1) + WR) PUOV 0 0 0 0 DDOE SRE SRE SRE SRE DDOV WR + ADA WR + ADA WR + ADA WR + ADA PVOE SRE SRE SRE SRE A7 • ADA(1) + D7 A6 • ADA(1) + D6 A5 • ADA(1) + D5 A4 • ADA(1) + D4 PVOV OUTPUT • WR OUTPUT • WR OUTPUT • WR OUTPUT • WR PTOE 0 0 0 0 DIEOE 0 0 0 0 DIEOV 0 0 0 0 DI D7 INPUT D6 INPUT D5 INPUT D4 INPUT AIO – – – – Note: 1. ADA is short for ADdress Active and represents the time when address is output. See “Exter- nal Memory Interface” on page 27 for details. Table 9-5. Overriding Signals for Alternate Functions in PA3..PA0 Signal Name PA3/AD3 PA2/AD2 PA1/AD1 PA0/AD0 SRE • SRE • SRE • SRE • PUOE (ADA(1) + WR) (ADA(1) + WR) (ADA(1) + WR) (ADA(1) + WR) PUOV 0 0 0 0 DDOE SRE SRE SRE SRE DDOV WR + ADA WR + ADA WR + ADA WR + ADA PVOE SRE SRE SRE SRE A3 • ADA(1) + D3 A2 • ADA(1) + D2 A1 • ADA(1) + D1 A0 • ADA(1) + D0 PVOV OUTPUT • WR OUTPUT • WR OUTPUT • WR OUTPUT • WR PTOE 0 0 0 0 DIEOE 0 0 0 0 DIEOV 0 0 0 0 DI D3 INPUT D2 INPUT D1 INPUT D0 INPUT AIO – – – – Note: 1. ADA is short for ADdress Active and represents the time when address is output. See “Exter- nal Memory Interface” on page 27 for details. 75 7679H–CAN–08/08

9.3.3 Alternate Functions of Port B The Port B pins with alternate functions are shown in Table 9-6. Table 9-6. Port B Pins Alternate Functions Port Pin Alternate Functions OC0A/OC1C (Output Compare and PWM Output A for Timer/Counter0 or Output Compare PB7 and PWM Output C for Timer/Counter1) PB6 OC1B (Output Compare and PWM Output B for Timer/Counter1) PB5 OC1A (Output Compare and PWM Output A for Timer/Counter1) PB4 OC2A (Output Compare and PWM Output A for Timer/Counter2 ) PB3 MISO (SPI Bus Master Input/Slave Output) PB2 MOSI (SPI Bus Master Output/Slave Input) PB1 SCK (SPI Bus Serial Clock) PB0 SS (SPI Slave Select input) The alternate pin configuration is as follows: • OC0A/OC1C, Bit 7 OC0A, Output Compare Match A output. The PB7 pin can serve as an external output for the Timer/Counter0 Output Compare A. The pin has to be configured as an output (DDB7 set “one”) to serve this function. The OC0A pin is also the output pin for the PWM mode timer function. OC1C, Output Compare Match C output. The PB7 pin can serve as an external output for the Timer/Counter1 Output Compare C. The pin has to be configured as an output (DDB7 set “one”) to serve this function. The OC1C pin is also the output pin for the PWM mode timer function. • OC1B, Bit 6 OC1B, Output Compare Match B output. The PB6 pin can serve as an external output for the Timer/Counter1 Output Compare B. The pin has to be configured as an output (DDB6 set “one”) to serve this function. The OC1B pin is also the output pin for the PWM mode timer function. • OC1A, Bit 5 OC1A, Output Compare Match A output. The PB5 pin can serve as an external output for the Timer/Counter1 Output Compare A. The pin has to be configured as an output (DDB5 set “one”) to serve this function. The OC1A pin is also the output pin for the PWM mode timer function. • OC2A, Bit 4 OC2A, Output Compare Match A output. The PB4 pin can serve as an external output for the Timer/Counter2 Output Compare A. The pin has to be configured as an output (DDB4 set “one”) to serve this function. The OC2A pin is also the output pin for the PWM mode timer function. • MISO – Port B, Bit 3 MISO, Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled as a master, this pin is configured as an input regardless of the setting of DDB3. When the SPI is enabled as a slave, the data direction of this pin is controlled by DDB3. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB3 bit. • MOSI – Port B, Bit 2 AT90CAN32/64/128 76 7679H–CAN–08/08

AT90CAN32/64/128 MOSI, SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB2. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB2. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB2 bit. • SCK – Port B, Bit 1 SCK, Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB1. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB1. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB1 bit. • SS – Port B, Bit 0 SS, Slave Port Select input. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB0. As a slave, the SPI is activated when this pin is driven low. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB0. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB0 bit. Table 9-7 and Table 9-8 relate the alternate functions of Port B to the overriding signals shown in Figure 9-5 on page 72. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the MISO sig- nal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT. Table 9-7 and Table 9-8 relates the alternate functions of Port B to the overriding signals shown in Figure 9-5 on page 72. Table 9-7. Overriding Signals for Alternate Functions in PB7..PB4 Signal Name PB7/OC0A/OC1C PB6/OC1B PB5/OC1A PB4/OC2A PUOE 0 0 0 0 PUOV 0 0 0 0 DDOE 0 0 0 0 DDOV 0 0 0 0 OC0A/OC1C PVOE OC1B ENABLE OC1A ENABLE OC2A ENABLE ENABLE(1) PVOV OC0A/OC1C(1) OC1B OC1A OC2A PTOE 0 0 0 0 DIEOE 0 0 0 0 DIEOV 0 0 0 0 DI – – – – AIO – – – – Note: 1. See “Output Compare Modulator - OCM” on page 165 for details. 77 7679H–CAN–08/08

Table 9-8. Overriding Signals for Alternate Functions in PB3..PB0 Signal Name PB3/MISO PB2/MOSI PB1/SCK PB0/SS PUOE SPE • MSTR SPE • MSTR SPE • MSTR SPE • MSTR PUOV PORTB3 • PUD PORTB2 • PUD PORTB1 • PUD PORTB0 • PUD DDOE SPE • MSTR SPE • MSTR SPE • MSTR SPE • MSTR DDOV 0 0 0 0 PVOE SPE • MSTR SPE • MSTR SPE • MSTR 0 SPI SLAVE SPI MASTER PVOV SCK OUTPUT 0 OUTPUT OUTPUT PTOE 0 0 0 0 DIEOE 0 0 0 0 DIEOV 0 0 0 0 SPI MASTER SPI SLAVE DI SCK INPUT SPI SS INPUT INPUT • RESET AIO – – – – 9.3.4 Alternate Functions of Port C The Port C has an alternate function as the address high byte for the External Memory Interface. The Port C pins with alternate functions are shown in Table 9-9. Table 9-9. Port C Pins Alternate Functions Port Pin Alternate Function A15/CLKO (External memory interface address 15 or Divided System PC7 Clock) PC6 A14 (External memory interface address 14) PC5 A13 (External memory interface address 13) PC4 A12 (External memory interface address 12) PC3 A11 (External memory interface address 11) PC2 A10 (External memory interface address 10) PC1 A9 (External memory interface address 9) PC0 A8 (External memory interface address 8) The alternate pin configuration is as follows: • A15/CLKO – Port C, Bit 7 A15, External memory interface address 15. CLKO, Divided System Clock: The divided system clock can be output on the PC7 pin. The divided system clock will be output if the CKOUT Fuse is programmed, regardless of the PORTC7 and DDC7 settings. It will also be output during reset. AT90CAN32/64/128 78 7679H–CAN–08/08

AT90CAN32/64/128 • A14 – Port C, Bit 6 A14, External memory interface address 14. • A13 – Port C, Bit 5 A13, External memory interface address 13. • A12 – Port C, Bit 4 A12, External memory interface address 12. • A11 – Port C, Bit 3 A11, External memory interface address 11. • A10 – Port C, Bit 2 A10, External memory interface address 10. • A9 – Port C, Bit 1 A9, External memory interface address 9. • A8 – Port C, Bit 0 A8, External memory interface address 8. Table 9-10 and Table 9-11 relate the alternate functions of Port C to the overriding signals shown in Figure 9-5 on page 72. Table 9-10. Overriding Signals for Alternate Functions in PC7..PC4 Signal Name PC7/A15 PC6/A14 PC5/A13 PC4/A12 PUOE SRE • (XMM<1) SRE • (XMM<2) SRE • (XMM<3) SRE • (XMM<4) PUOV 0 0 0 0 CKOUT(1) + DDOE SRE • (XMM<2) SRE • (XMM<3) SRE • (XMM<4) (SRE • (XMM<1)) DDOV 1 1 1 1 CKOUT(1) + PVOE SRE • (XMM<2) SRE • (XMM<3) SRE • (XMM<4) (SRE • (XMM<1)) (A15 • CKOUT(1)) + PVOV A14 A13 A12 (CLKO • CKOUT(1)) PTOE 0 0 0 0 DIEOE 0 0 0 0 DIEOV 0 0 0 0 DI – – – – AIO – – – – Note: 1. CKOUT is one if the CKOUT Fuse is programmed 79 7679H–CAN–08/08

Table 9-11. Overriding Signals for Alternate Functions in PC3..PC0 Signal Name PC3/A11 PC2/A10 PC1/A9 PC0/A8 PUOE SRE • (XMM<5) SRE • (XMM<6) SRE • (XMM<7) SRE • (XMM<7) PUOV 0 0 0 0 DDOE SRE • (XMM<5) SRE • (XMM<6) SRE • (XMM<7) SRE • (XMM<7) DDOV 1 1 1 1 PVOE SRE • (XMM<5) SRE • (XMM<6) SRE • (XMM<7) SRE • (XMM<7) PVOV A11 A10 A9 A8 PTOE 0 0 0 0 DIEOE 0 0 0 0 DIEOV 0 0 0 0 DI – – – – AIO – – – – 9.3.5 Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 9-12. Table 9-12. Port D Pins Alternate Functions Port Pin Alternate Function PD7 T0 (Timer/Counter0 Clock Input) PD6 RXCAN/T1 (CAN Receive Pin or Timer/Counter1 Clock Input) PD5 TXCAN/XCK1 (CAN Transmit Pin or USART1 External Clock Input/Output) PD4 ICP1 (Timer/Counter1 Input Capture Trigger) PD3 INT3/TXD1 (External Interrupt3 Input or UART1 Transmit Pin) PD2 INT2/RXD1 (External Interrupt2 Input or UART1 Receive Pin) PD1 INT1/SDA (External Interrupt1 Input or TWI Serial DAta) PD0 INT0/SCL (External Interrupt0 Input or TWI Serial CLock) The alternate pin configuration is as follows: • T0 – Port D, Bit 7 T0, Timer/Counter0 counter source. • RXCAN/T1 – Port D, Bit 6 RXCAN, CAN Receive Data (Data input pin for the CAN). When the CAN controller is enabled this pin is configured as an input regardless of the value of DDD6. When the CAN forces this pin to be an input, the pull-up can still be controlled by the PORTD6 bit. T1, Timer/Counter1 counter source. • TXCAN/XCK1 – Port D, Bit 5 AT90CAN32/64/128 80 7679H–CAN–08/08

AT90CAN32/64/128 TXCAN, CAN Transmit Data (Data output pin for the CAN). When the CAN is enabled, this pin is configured as an output regardless of the value of DDD5. XCK1, USART1 External clock. The Data Direction Register (DDD5) controls whether the clock is output (DDD5 set) or input (DDD45 cleared). The XCK1 pin is active only when the USART1 operates in Synchronous mode. • ICP1 – Port D, Bit 4 ICP1, Input Capture Pin1. The PD4 pin can act as an input capture pin for Timer/Counter1. • INT3/TXD1 – Port D, Bit 3 INT3, External Interrupt source 3. The PD3 pin can serve as an external interrupt source to the MCU. TXD1, Transmit Data (Data output pin for the USART1). When the USART1 Transmitter is enabled, this pin is configured as an output regardless of the value of DDD3. • INT2/RXD1 – Port D, Bit 2 INT2, External Interrupt source 2. The PD2 pin can serve as an External Interrupt source to the MCU. RXD1, Receive Data (Data input pin for the USART1). When the USART1 receiver is enabled this pin is configured as an input regardless of the value of DDD2. When the USART forces this pin to be an input, the pull-up can still be controlled by the PORTD2 bit. • INT1/SDA – Port D, Bit 1 INT1, External Interrupt source 1. The PD1 pin can serve as an external interrupt source to the MCU. SDA, Two-wire Serial Interface Data. When the TWEN bit in TWCR is set (one) to enable the Two-wire Serial Interface, pin PD1 is disconnected from the port and becomes the Serial Data I/O pin for the Two-wire Serial Interface. In this mode, there is a spike filter on the pin to sup- press spikes shorter than 50 ns on the input signal, and the pin is driven by an open drain driver with slew-rate limitation. • INT0/SCL – Port D, Bit 0 INT0, External Interrupt source 0. The PD0 pin can serve as an external interrupt source to the MCU. SCL, Two-wire Serial Interface Clock: When the TWEN bit in TWCR is set (one) to enable the Two-wire Serial Interface, pin PD0 is disconnected from the port and becomes the Serial Clock I/O pin for the Two-wire Serial Interface. In this mode, there is a spike filter on the pin to sup- press spikes shorter than 50 ns on the input signal, and the pin is driven by an open drain driver with slew-rate limitation. 81 7679H–CAN–08/08

Table 9-13 and Table 9-14 relates the alternate functions of Port D to the overriding signals shown in Figure 9-5 on page 72. Table 9-13. Overriding Signals for Alternate Functions PD7..PD4 Signal Name PD7/T0 PD6/T1/RXCAN PD5/XCK1/TXCAN PD4/ICP1 PUOE 0 RXCANEN TXCANEN + 0 PUOV 0 PORTD6 • PUD 0 0 DDOE 0 RXCANEN TXCANEN 0 DDOV 0 0 1 0 PVOE 0 0 TXCANEN + UMSEL1 0 (XCK1 OUTPUT • PVOV 0 0 UMSEL1 • TXCANEN) + 0 (TXCAN • TXCANEN) PTOE 0 0 0 0 DIEOE 0 0 0 0 DIEOV 0 0 0 0 DI T0 INPUT T1 INPUT/RXCAN XCK1 INPUT ICP1 INPUT AIO – – – – Table 9-14. Overriding Signals for Alternate Functions in PD3..PD0(1) Signal Name PD3/INT3/TXD1 PD2/INT2/RXD1 PD1/INT1/SDA PD0/INT0/SCL PUOE TXEN1 RXEN1 TWEN TWEN PUOV 0 PORTD2 • PUD PORTD1 • PUD PORTD0 • PUD DDOE TXEN1 RXEN1 0 0 DDOV 1 0 0 0 PVOE TXEN1 0 TWEN TWEN PVOV TXD1 0 SDA_OUT SCL_OUT PTOE 0 0 0 0 DIEOE INT3 ENABLE INT2 ENABLE INT1 ENABLE INT0 ENABLE DIEOV INT3 ENABLE INT2 ENABLE INT1 ENABLE INT0 ENABLE DI INT3 INPUT INT2 INPUT/RXD1 INT1 INPUT INT0 INPUT AIO – – SDA INPUT SCL INPUT Note: 1. When enabled, the Two-wire Serial Interface enables Slew-Rate controls on the output pins PD0 and PD1. This is not shown in this table. In addition, spike filters are connected between the AIO outputs shown in the port figure and the digital logic of the TWI module. AT90CAN32/64/128 82 7679H–CAN–08/08

AT90CAN32/64/128 9.3.6 Alternate Functions of Port E The Port E pins with alternate functions are shown in Table 9-15. Table 9-15. Port E Pins Alternate Functions Port Pin Alternate Function PE7 INT7/ICP3 (External Interrupt 7 Input or Timer/Counter3 Input Capture Trigger) PE6 INT6/ T3 (External Interrupt 6 Input or Timer/Counter3 Clock Input) INT5/OC3C (External Interrupt 5 Input or Output Compare and PWM Output C for PE5 Timer/Counter3) INT4/OC3B (External Interrupt4 Input or Output Compare and PWM Output B for PE4 Timer/Counter3) AIN1/OC3A (Analog Comparator Negative Input or Output Compare and PWM Output A PE3 for Timer/Counter3) PE2 AIN0/XCK0 (Analog Comparator Positive Input or USART0 external clock input/output) PE1 PDO/TXD0 (Programming Data Output or UART0 Transmit Pin) PE0 PDI/RXD0 (Programming Data Input or UART0 Receive Pin) The alternate pin configuration is as follows: • PCINT7/ICP3 – Port E, Bit 7 INT7, External Interrupt source 7. The PE7 pin can serve as an external interrupt source. ICP3, Input Capture Pin3: The PE7 pin can act as an input capture pin for Timer/Counter3. • INT6/T3 – Port E, Bit 6 INT6, External Interrupt source 6. The PE6 pin can serve as an external interrupt source. T3, Timer/Counter3 counter source. • INT5/OC3C – Port E, Bit 5 INT5, External Interrupt source 5. The PE5 pin can serve as an External Interrupt source. OC3C, Output Compare Match C output. The PE5 pin can serve as an External output for the Timer/Counter3 Output Compare C. The pin has to be configured as an output (DDE5 set “one”) to serve this function. The OC3C pin is also the output pin for the PWM mode timer function. • INT4/OC3B – Port E, Bit 4 INT4, External Interrupt source 4. The PE4 pin can serve as an External Interrupt source. OC3B, Output Compare Match B output. The PE4 pin can serve as an External output for the Timer/Counter3 Output Compare B. The pin has to be configured as an output (DDE4 set (one)) to serve this function. The OC3B pin is also the output pin for the PWM mode timer function. • AIN1/OC3A – Port E, Bit 3 AIN1 – Analog Comparator Negative input. This pin is directly connected to the negative input of the Analog Comparator. OC3A, Output Compare Match A output. The PE3 pin can serve as an External output for the Timer/Counter3 Output Compare A. The pin has to be configured as an output (DDE3 set “one”) to serve this function. The OC3A pin is also the output pin for the PWM mode timer function. 83 7679H–CAN–08/08

• AIN0/XCK0 – Port E, Bit 2 AIN0 – Analog Comparator Positive input. This pin is directly connected to the positive input of the Analog Comparator. XCK0, USART0 External clock. The Data Direction Register (DDE2) controls whether the clock is output (DDE2 set) or input (DDE2 cleared). The XCK0 pin is active only when the USART0 operates in Synchronous mode. • PDO/TXD0 – Port E, Bit 1 PDO, SPI Serial Programming Data Output. During Serial Program Downloading, this pin is used as data output line for the AT90CAN32/64/128. TXD0, UART0 Transmit pin. • PDI/RXD0 – Port E, Bit 0 PDI, SPI Serial Programming Data Input. During Serial Program Downloading, this pin is used as data input line for the AT90CAN32/64/128. RXD0, USART0 Receive Pin. Receive Data (Data input pin for the USART0). When the USART0 receiver is enabled this pin is configured as an input regardless of the value of DDRE0. When the USART0 forces this pin to be an input, a logical one in PORTE0 will turn on the inter- nal pull-up. Table 9-16 and Table 9-17 relates the alternate functions of Port E to the overriding signals shown in Figure 9-5 on page 72. Table 9-16. Overriding Signals for Alternate Functions PE7..PE4 Signal Name PE7/INT7/ICP3 PE6/INT6/T3 PE5/INT5/OC3C PE4/INT4/OC3B PUOE 0 0 0 0 PUOV 0 0 0 0 DDOE 0 0 0 0 DDOV 0 0 0 0 PVOE 0 0 OC3C ENABLE OC3B ENABLE PVOV 0 0 OC3C OC3B PTOE 0 0 0 0 DIEOE INT7 ENABLE INT6 ENABLE INT5 ENABLE INT4 ENABLE DIEOV INT7 ENABLE INT6 ENABLE INT5 ENABLE INT4 ENABLE INT7 INPUT INT6 INPUT DI INT5 INPUT INT4 INPUT /ICP3 INPUT /T3 INPUT AIO – – – – AT90CAN32/64/128 84 7679H–CAN–08/08

AT90CAN32/64/128 Table 9-17. Overriding Signals for Alternate Functions in PE3..PE0 Signal Name PE3/AIN1/OC3A PE2/AIN0/XCK0 PE1/PDO/TXD0 PE0/PDI/RXD0 PUOE 0 0 TXEN0 RXEN0 PUOV 0 0 0 PORTE0 • PUD DDOE 0 0 TXEN0 RXEN0 DDOV 0 0 1 0 PVOE OC3A ENABLE UMSEL0 TXEN0 0 PVOV OC3A XCK0 OUTPUT TXD0 0 PTOE 0 0 0 0 DIEOE AIN1D(1) AIN0D(1) 0 0 DIEOV 0 0 0 0 DI 0 XCK0 INPUT – RXD0 AIO AIN1 INPUT AIN0 INPUT – – Note: 1. AIN0D and AIN1D is described in “Digital Input Disable Register1 – DIDR1” on page 272. 9.3.7 Alternate Functions of Port F The Port F has an alternate function as analog input for the ADC as shown in Table 9-18. If some Port F pins are configured as outputs, it is essential that these do not switch when a con- version is in progress. This might corrupt the result of the conversion. If the JTAG interface is enabled, the pull-up resistors on pins PF7 (TDI), PF5 (TMS) and PF4 (TCK) will be activated even if a reset occurs. Table 9-18. Port F Pins Alternate Functions Port Pin Alternate Function PF7 ADC7/TDI (ADC input channel 7 or JTAG Data Input) PF6 ADC6/TDO (ADC input channel 6 or JTAG Data Output) PF5 ADC5/TMS (ADC input channel 5 or JTAG mode Select) PF4 ADC4/TCK (ADC input channel 4 or JTAG ClocK) PF3 ADC3 (ADC input channel 3) PF2 ADC2 (ADC input channel 2) PF1 ADC1 (ADC input channel 1) PF0 ADC0 (ADC input channel 0) The alternate pin configuration is as follows: • TDI, ADC7 – Port F, Bit 7 ADC7, Analog to Digital Converter, input channel 7. 85 7679H–CAN–08/08

TDI, JTAG Test Data In. Serial input data to be shifted in to the Instruction Register or Data Reg- ister (scan chains). When the JTAG interface is enabled, this pin can not be used as an I/O pin. • TCK, ADC6 – Port F, Bit 6 ADC6, Analog to Digital Converter, input channel 6. TDO, JTAG Test Data Out. Serial output data from Instruction Register or Data Register. When the JTAG interface is enabled, this pin can not be used as an I/O pin. • TMS, ADC5 – Port F, Bit 5 ADC5, Analog to Digital Converter, input channel 5. TMS, JTAG Test mode Select. This pin is used for navigating through the TAP-controller state machine. When the JTAG interface is enabled, this pin can not be used as an I/O pin. • TDO, ADC4 – Port F, Bit 4 ADC4, Analog to Digital Converter, input channel 4. TCK, JTAG Test Clock. JTAG operation is synchronous to TCK. When the JTAG interface is enabled, this pin can not be used as an I/O pin. • ADC3 – Port F, Bit 3 ADC3, Analog to Digital Converter, input channel 3. • ADC2 – Port F, Bit 2 ADC2, Analog to Digital Converter, input channel 2. • ADC1 – Port F, Bit 1 ADC1, Analog to Digital Converter, input channel 1. • ADC0 – Port F, Bit 0 ADC0, Analog to Digital Converter, input channel 0. AT90CAN32/64/128 86 7679H–CAN–08/08

AT90CAN32/64/128 Table 9-19 and Table 9-20 relates the alternate functions of Port F to the overriding signals shown in Figure 9-5 on page 72. Table 9-19. Overriding Signals for Alternate Functions in PF7..PF4 Signal Name PF7/ADC7/TDI PF6/ADC6/TDO PF5/ADC5/TMS PF4/ADC4/TCK PUOE JTAGEN JTAGEN JTAGEN JTAGEN PUOV JTAGEN JTAGEN JTAGEN JTAGEN DDOE JTAGEN JTAGEN JTAGEN JTAGEN SHIFT_IR + DDOV 0 0 0 SHIFT_DR PVOE JTAGEN JTAGEN JTAGEN JTAGEN PVOV 0 TDO 0 0 PTOE 0 0 0 0 JTAGEN + JTAGEN + JTAGEN + JTAGEN + DIEOE ADC7D ADC6D ADC5D ADC4D DIEOV JTAGEN 0 JTAGEN JTAGEN DI TDI – TMS TCK AIO ADC7 INPUT ADC6 INPUT ADC5 INPUT ADC4 INPUT Table 9-20. Overriding Signals for Alternate Functions in PF3..PF0 Signal Name PF3/ADC3 PF2/ADC2 PF1/ADC1 PF0/ADC0 PUOE 0 0 0 0 PUOV 0 0 0 0 DDOE 0 0 0 0 DDOV 0 0 0 0 PVOE 0 0 0 0 PVOV 0 0 0 0 PTOE 0 0 0 0 DIEOE ADC3D ADC2D ADC1D ADC0D DIEOV 0 0 0 0 DI – – – – AIO ADC3 INPUT ADC2 INPUT ADC1 INPUT ADC0 INPUT 87 7679H–CAN–08/08

9.3.8 Alternate Functions of Port G The alternate pin configuration is as follows: Table 9-21. Port G Pins Alternate Functions Port Pin Alternate Function PG4 TOSC1 (RTC Oscillator Timer/Counter2) PG3 TOSC2 (RTC Oscillator Timer/Counter2) PG2 ALE (Address Latch Enable to external memory) PG1 RD (Read strobe to external memory) PG0 WR (Write strobe to external memory) The alternate pin configuration is as follows: • TOSC1 – Port G, Bit 4 TOSC2, Timer/Counter2 Oscillator pin 1. When the AS2 bit in ASSR is set (one) to enable asyn- chronous clocking of Timer/Counter2, pin PG4 is disconnected from the port, and becomes the input of the inverting Oscillator amplifier. In this mode, a Crystal Oscillator is connected to this pin, and the pin can not be used as an I/O pin. • TOSC2 – Port G, Bit 3 TOSC2, Timer/Counter2 Oscillator pin 2. When the AS2 bit in ASSR is set (one) to enable asyn- chronous clocking of Timer/Counter2, pin PG3 is disconnected from the port, and becomes the inverting output of the Oscillator amplifier. In this mode, a Crystal Oscillator is connected to this pin, and the pin can not be used as an I/O pin. • ALE – Port G, Bit 2 ALE is the external data memory Address Latch Enable signal. • RD – Port G, Bit 1 RD is the external data memory read control strobe. • WR – Port G, Bit 0 WR is the external data memory write control strobe. AT90CAN32/64/128 88 7679H–CAN–08/08

AT90CAN32/64/128 Table 9-21 and Table 9-22 relates the alternate functions of Port G to the overriding signals shown in Figure 9-5 on page 72. Table 9-22. Overriding Signals for Alternate Function in PG4 Signal Name - - - PG4/TOSC1 PUOE AS2 PUOV 0 DDOE AS2 DDOV 0 PVOE 0 PVOV 0 PTOE 0 DIEOE AS2 DIEOV EXCLK DI – AIO T/C2 OSC INPUT Table 9-23. Overriding Signals for Alternate Functions in PG3:0 Signal Name PG3/TOSC2 PG2/ALE PG1/RD PG0/WR PUOE AS2 • EXCLK SRE SRE SRE PUOV 0 0 0 0 DDOE AS2 • EXCLK SRE SRE SRE DDOV 0 1 1 1 PVOE 0 SRE SRE SRE PVOV 0 ALE RD WR PTOE 0 0 0 0 DIEOE AS2 0 0 0 DIEOV 0 0 0 0 DI – – – – AIO T/C2 OSC OUTPUT – – – 9.4 Register Description for I/O-Ports 9.4.1 Port A Data Register – PORTA Bit 7 6 5 4 3 2 1 0 PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 PORTA Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 89 7679H–CAN–08/08

9.4.2 Port A Data Direction Register – DDRA Bit 7 6 5 4 3 2 1 0 DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 DDRA Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 9.4.3 Port A Input Pins Address – PINA Bit 7 6 5 4 3 2 1 0 PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 PINA Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value N/A N/A N/A N/A N/A N/A N/A N/A 9.4.4 Port B Data Register – PORTB Bit 7 6 5 4 3 2 1 0 PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 PORTB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 9.4.5 Port B Data Direction Register – DDRB Bit 7 6 5 4 3 2 1 0 DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 DDRB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 9.4.6 Port B Input Pins Address – PINB Bit 7 6 5 4 3 2 1 0 PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 PINB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value N/A N/A N/A N/A N/A N/A N/A N/A 9.4.7 Port C Data Register – PORTC Bit 7 6 5 4 3 2 1 0 PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 PORTC Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 9.4.8 Port C Data Direction Register – DDRC Bit 7 6 5 4 3 2 1 0 DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 DDRC Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 9.4.9 Port C Input Pins Address – PINC Bit 7 6 5 4 3 2 1 0 PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 PINC Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value N/A N/A N/A N/A N/A N/A N/A N/A AT90CAN32/64/128 90 7679H–CAN–08/08

AT90CAN32/64/128 9.4.10 Port D Data Register – PORTD Bit 7 6 5 4 3 2 1 0 PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 PORTD Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 9.4.11 Port D Data Direction Register – DDRD Bit 7 6 5 4 3 2 1 0 DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 DDRD Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 9.4.12 Port D Input Pins Address – PIND Bit 7 6 5 4 3 2 1 0 PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 PIND Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value N/A N/A N/A N/A N/A N/A N/A N/A 9.4.13 Port E Data Register – PORTE Bit 7 6 5 4 3 2 1 0 PORTE7 PORTE6 PORTE5 PORTE4 PORTE3 PORTE2 PORTE1 PORTE0 PORTE Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 9.4.14 Port E Data Direction Register – DDRE Bit 7 6 5 4 3 2 1 0 DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 DDE1 DDE0 DDRE Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 9.4.15 Port E Input Pins Address – PINE Bit 7 6 5 4 3 2 1 0 PINE7 PINE6 PINE5 PINE4 PINE3 PINE2 PINE1 PINE0 PINE Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value N/A N/A N/A N/A N/A N/A N/A N/A 9.4.16 Port F Data Register – PORTF Bit 7 6 5 4 3 2 1 0 PORTF7 PORTF6 PORTF5 PORTF4 PORTF3 PORTF2 PORTF1 PORTF0 PORTF Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 9.4.17 Port F Data Direction Register – DDRF Bit 7 6 5 4 3 2 1 0 DDF7 DDF6 DDF5 DDF4 DDF3 DDF2 DDF1 DDF0 DDRF Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 91 7679H–CAN–08/08

9.4.18 Port F Input Pins Address – PINF Bit 7 6 5 4 3 2 1 0 PINF7 PINF6 PINF5 PINF4 PINF3 PINF2 PINF1 PINF0 PINF Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value N/A N/A N/A N/A N/A N/A N/A N/A 9.4.19 Port G Data Register – PORTG Bit 7 6 5 4 3 2 1 0 – – – PORTG4 PORTG3 PORTG2 PORTG1 PORTG0 PORTG Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 9.4.20 Port G Data Direction Register – DDRG Bit 7 6 5 4 3 2 1 0 – – – DDG4 DDG3 DDG2 DDG1 DDG0 DDRG Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 9.4.21 Port G Input Pins Address – PING Bit 7 6 5 4 3 2 1 0 – – – PING4 PING3 PING2 PING1 PING0 PING Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 N/A N/A N/A N/A N/A AT90CAN32/64/128 92 7679H–CAN–08/08

AT90CAN32/64/128 10. External Interrupts The External Interrupts are triggered by the INT7:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT7:0 pins are configured as outputs. This feature provides a way of gen- erating a software interrupt. The External Interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the External Interrupt Control Reg- isters – EICRA (INT3:0) and EICRB (INT7:4). When the external interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT7:4 requires the presence of an I/O clock, described in “Clock Systems and theirDistribution” on page 37. Low level interrupts and the edge interrupt on INT3:0 are detected asynchronously. This implies that these interrupts can be used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode. Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed level must be held for some time to wake up the MCU. This makes the MCU less sensitive to noise. The changed level is sampled twice by the Watchdog Oscillator clock. The period of the Watchdog Oscillator is 1 µs (nominal) at 5.0V and 25°C. The frequency of the Watchdog Oscilla- tor is voltage dependent as shown in the “Electrical Characteristics (1)” on page 365. The MCU will wake up if the input has the required level during this sampling or if it is held until the end of the start-up time. The start-up time is defined by the SUT fuses as described in “System Clock” on page 37. If the level is sampled twice by the Watchdog Oscillator clock but disappears before the end of the start-up time, the MCU will still wake up, but no interrupt will be generated. The required level must be held long enough for the MCU to complete the wake up to trigger the level interrupt. 10.1 External Interrupt Register Description 10.1.1 Asynchronous External Interrupt Control Register A – EICRA Bit 7 6 5 4 3 2 1 0 ISC31 ISC30 ISC21 ISC20 ISC11 ISC10 ISC01 ISC00 EICRA Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bits 7..0 – ISC31, ISC30 – ISC01, ISC00: Asynchronous External Interrupt 3 - 0 Sense Control Bits The External Interrupts 3 - 0 are activated by the external pins INT3:0 if the SREG I-flag and the corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that activate the interrupts are defined in Table 10-1. Edges on INT3..INT0 are registered asynchro- nously. Pulses on INT3:0 pins wider than the minimum pulse width given in Table 10-2 will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an inter- rupt request as long as the pin is held low. When changing the ISCn bit, an interrupt can occur. Therefore, it is recommended to first disable INTn by clearing its Interrupt Enable bit in the EIMSK Register. Then, the ISCn bit can be changed. Finally, the INTn interrupt flag should be cleared by writing a logical one to its Interrupt Flag bit (INTFn) in the EIFR Register before the interrupt is re-enabled. 93 7679H–CAN–08/08

Table 10-1. Asynchronous External Interrupt Sense Control(1) ISCn1 ISCn0 Description 0 0 The low level of INTn generates an interrupt request. 0 1 Any logical change on INTn generates an interrupt request 1 0 The falling edge of INTn generates asynchronously an interrupt request. 1 1 The rising edge of INTn generates asynchronously an interrupt request. Note: 1. n = 3, 2, 1 or 0. When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed. Table 10-2. Asynchronous External Interrupt Characteristics Symbol Parameter Condition Min Typ Max Units Minimum pulse width for asynchronous t 50 ns INT external interrupt 10.1.2 Synchronous External Interrupt Control Register B – EICRB Bit 7 6 5 4 3 2 1 0 ISC71 ISC70 ISC61 ISC60 ISC51 ISC50 ISC41 ISC40 EICRB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bits 7..0 – ISC71, ISC70 - ISC41, ISC40: Synchronous External Interrupt 7 - 4 Sense Control Bits The External Interrupts 7 - 4 are activated by the external pins INT7:4 if the SREG I-flag and the corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that activate the interrupts are defined in Table 10-3. The value on the INT7:4 pins are sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an inter- rupt. Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL divider is enabled. If low level interrupt is selected, the low level must be held until the comple- tion of the currently executing instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an interrupt request as long as the pin is held low. Table 10-3. Synchronous External Interrupt Sense Control(1) ISCn1 ISCn0 Description 0 0 The low level of INTn generates an interrupt request. 0 1 Any logical change on INTn generates an interrupt request 1 0 The falling edge between two samples of INTn generates an interrupt request. 1 1 The rising edge between two samples of INTn generates an interrupt request. Note: 1. n = 7, 6, 5 or 4. When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed. AT90CAN32/64/128 94 7679H–CAN–08/08

AT90CAN32/64/128 10.1.3 External Interrupt Mask Register – EIMSK Bit 7 6 5 4 3 2 1 0 INT7 INT6 INT5 INT4 INT3 INT2 INT1 IINT0 EIMSK Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bits 7..0 – INT7 – INT0: External Interrupt Request 7 - 0 Enable When an INT7 – INT0 bit is written to one and the I-bit in the Status Register (SREG) is set (one), the corresponding external pin interrupt is enabled. The Interrupt Sense Control bits in the External Interrupt Control Registers – EICRA and EICRB – defines whether the external inter- rupt is activated on rising or falling edge or level sensed. Activity on any of these pins will trigger an interrupt request even if the pin is enabled as an output. This provides a way of generating a software interrupt. 10.1.4 External Interrupt Flag Register – EIFR Bit 7 6 5 4 3 2 1 0 INTF7 INTF6 INTF5 INTF4 INTF3 INTF2 INTF1 IINTF0 EIFR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bits 7..0 – INTF7 - INTF0: External Interrupt Flags 7 - 0 When an edge or logic change on the INT7:0 pin triggers an interrupt request, INTF7:0 becomes set (one). If the I-bit in SREG and the corresponding interrupt enable bit, INT7:0 in EIMSK, are set (one), the MCU will jump to the interrupt vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. These flags are always cleared when INT7:0 are configured as level interrupt. Note that when entering sleep mode with the INT3:0 interrupts disabled, the input buffers on these pins will be disabled. This may cause a logic change in internal signals which will set the INTF3:0 flags. See “Digital Input Enable and Sleep Modes” on page 70 for more information. 95 7679H–CAN–08/08

11. Timer/Counter3/1/0 Prescalers Timer/Counter3, Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter3, Timer/Counter1 and Timer/Counter0. 11.1 Overview Most bit references in this section are written in general form. A lower case “n” replaces the Timer/Counter number. 11.1.1 Internal Clock Source The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0=1). This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system clock frequency (f ). Alternatively, one of four taps from the prescaler can be used as a CLK_I/O clock source. The prescaled clock has a frequency of either f /8, f /64, f /256, or CLK_I/O CLK_I/O CLK_I/O f /1024. CLK_I/O 11.1.2 Prescaler Reset The prescaler is free running, i.e., operates independently of the Clock Select logic of the Timer/Counter, and it is shared by Timer/Counter3, Timer/Counter1 and Timer/Counter0. Since the prescaler is not affected by the Timer/Counter’s clock select, the state of the prescaler will have implications for situations where a prescaled clock is used. One example of prescaling arti- facts occurs when the timer is enabled and clocked by the prescaler (6 > CSn2:0 > 1). The number of system clock cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024). It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execu- tion. However, care must be taken if the other Timer/Counter that shares the same prescaler also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it is connected to. 11.1.3 External Clock Source An external clock source applied to the T3/T1/T0 pin can be used as Timer/Counter clock (clk /clk /clk ). The T3/T1/T0 pin is sampled once every system clock cycle by the pin syn- T3 T1 T0 chronization logic. The synchronized (sampled) signal is then passed through the edge detector. Figure 11-1 shows a functional equivalent block diagram of the T3/T1/T0 synchronization and edge detector logic. The registers are clocked at the positive edge of the internal system clock (clk ). The latch is transparent in the high period of the internal system clock. I/O The edge detector generates one clk /clk /clk pulse for each positive (CSn2:0=7) or nega- T3 T1 T0 tive (CSn2:0=6) edge it detects. AT90CAN32/64/128 96 7679H–CAN–08/08

AT90CAN32/64/128 Figure 11-1. T3/T1/T0 Pin Sampling Tn D Q D Q D Q Tn_sync (To Clock Select Logic) LE clk I/O Synchronization Edge Detector The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the T3/T1/T0 pin to the counter is updated. Enabling and disabling of the clock input must be done when T3/T1/T0 has been stable for at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated. Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the sys- tem clock frequency (f <f /2) given a 50/50% duty cycle. Since the edge detector uses ExtClk clk_I/O sampling, the maximum frequency of an external clock it can detect is half the sampling fre- quency (Nyquist sampling theorem). However, due to variation of the system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than f /2.5. clk_I/O An external clock source can not be prescaled. Figure 11-2. Prescaler for Timer/Counter3, Timer/Counter1 and Timer/Counter0 (1) CK 10-BIT T/C PRESCALER Clear PSR310 CK/8 CK/64 CK/256 CK/1024 T3 Synchronization T1 Synchronization T0 Synchronization 0 0 0 CS00 CS10 CS30 CS01 CS11 CS31 CS02 CS12 CS32 TIMER/COUNTER0 CLOCK SOURCE TIMER/COUNTER1 CLOCK SOURCE TIMER/COUNTER3 CLOCK SOURCE clkT0 clkT1 clkT3 Note: 1. The synchronization logic on the input pins (T0/T1/T3) is shown in Figure 11-1. 97 7679H–CAN–08/08

11.2 Timer/Counter0/1/3 Prescalers Register Description 11.2.1 General Timer/Counter Control Register – GTCCR Bit 7 6 5 4 3 2 1 0 TSM – – – – – PSR2 PSR310 GTCCR Read/Write R/W R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 7 – TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSR2 and PSR310 bits is kept, hence keeping the corresponding prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during con- figuration. When the TSM bit is written to zero, the PSR2 and PSR310 bits are cleared by hardware, and the Timer/Counters start counting simultaneously. • Bit 0 – PSR310: Prescaler Reset Timer/Counter3, Timer/Counter1 and Timer/Counter0 When this bit is one, Timer/Counter3, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter3, Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect these three timers. AT90CAN32/64/128 98 7679H–CAN–08/08

AT90CAN32/64/128 12. 8-bit Timer/Counter0 with PWM Timer/Counter0 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: 12.1 Features • Single Channel Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse Width Modulator (PWM) • Frequency Generator • External Event Counter • 10-bit Clock Prescaler • Overflow and Compare Match Interrupt Sources (TOV0 and OCF0A) 12.2 Overview Many register and bit references in this section are written in general form. • A lower case “n” replaces the Timer/Counter number, in this case 0. However, when using the register or bit defines in a program, the precise form must be used, i.e., TCNT0 for accessing Timer/Counter0 counter value and so on. • A lower case “x” replaces the Output Compare unit channel, in this case A. However, when using the register or bit defines in a program, the precise form must be used, i.e., OCR0A for accessing Timer/Counter0 output compare channel A value and so on. A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 12-1. For the actual placement of I/O pins, refer to “Pin Configurations” on page 5. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit loca- tions are listed in the “8-bit Timer/Counter Register Description” on page 109. Figure 12-1. 8-bit Timer/Counter Block Diagram TCCRn count TOVn clear (Int.Req.) Control Logic direction clkTn Clock Select Edge Tn Detector BOTTOM TOP S ( From Prescaler ) U Timer/Counter A B TCNTn = 0 = 0xFF T OCn A (Int.Req.) D = Waveform OCnx Generation OCRnx 99 7679H–CAN–08/08

12.2.1 Registers The Timer/Counter (TCNT0) and Output Compare Register (OCR0A) are 8-bit registers. Inter- rupt request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR0). All interrupts are individually masked with the Timer Interrupt Mask Reg- ister (TIMSK0). TIFR0 and TIMSK0 are not shown in the figure. The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clk ). T0 The double buffered Output Compare Register (OCR0A) is compared with the Timer/Counter value at all times. The result of the compare can be used by the Waveform Generator to gener- ate a PWM or variable frequency output on the Output Compare pin (OC0A). See “Output Compare Unit” on page 101. for details. The compare match event will also set the Compare Flag (OCF0A) which can be used to generate an Output Compare interrupt request. 12.2.2 Definitions The following definitions are used extensively throughout the section: BOTTOM The counter reaches the BOTTOM when it becomes 0x00. MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255). TOP The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR0A Register. The assignment is depen- dent on the mode of operation. 12.3 Timer/Counter Clock Sources The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CS02:0) bits located in the Timer/Counter Control Register (TCCR0A). For details on clock sources and pres- caler, see “Timer/Counter3/1/0 Prescalers” on page 96. 12.4 Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 12-2 shows a block diagram of the counter and its surroundings. Figure 12-2. Counter Unit Block Diagram TOVn DATA BUS (Int.Req.) Clock Select count Edge Tn TCNTn clear Control Logic clkTn Detector direction ( From Prescaler ) bottom top AT90CAN32/64/128 100 7679H–CAN–08/08

AT90CAN32/64/128 Signal description (internal signals): count Increment or decrement TCNT0 by 1. direction Select between increment and decrement. clear Clear TCNT0 (set all bits to zero). clk Timer/Counter clock, referred to as clk in the following. Tn T0 top Signalize that TCNT0 has reached maximum value. bottom Signalize that TCNT0 has reached minimum value (zero). Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk ). clk can be generated from an external or internal clock source, T0 T0 selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of whether clk is present or not. A CPU write overrides (has priority over) all counter clear or T0 count operations. The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in the Timer/Counter Control Register (TCCR0A). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare output OC0A. For more details about advanced counting sequences and waveform generation, see “Modes of Operation” on page 104. The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation selected by the WGM01:0 bits. TOV0 can be used for generating a CPU interrupt. 12.5 Output Compare Unit The 8-bit comparator continuously compares TCNT0 with the Output Compare Register (OCR0A). Whenever TCNT0 equals OCR0A, the comparator signals a match. A match will set the Output Compare Flag (OCF0A) at the next timer clock cycle. If enabled (OCIE0A = 1 and Global Interrupt Flag in SREG is set), the Output Compare Flag generates an Output Compare interrupt. The OCF0A flag is automatically cleared when the interrupt is executed. Alternatively, the OCF0A flag can be cleared by software by writing a logical one to its I/O bit location. The Waveform Generator uses the match signal to generate an output according to operating mode set by the WGM01:0 bits and Compare Output mode (COM0A1:0) bits. The max and bottom sig- nals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation (See “Modes of Operation” on page 104.). 101 7679H–CAN–08/08

Figure 12-3 shows a block diagram of the Output Compare unit. Figure 12-3. Output Compare Unit, Block Diagram DATA BUS OCRnx TCNTn = (8-bit Comparator ) OCFnx (Int.Req.) top bottom Waveform Generator OCnx FOCn WGMn1:0 COMnX1:0 The OCR0A Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buff- ering is disabled. The double buffering synchronizes the update of the OCR0A Compare Register to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR0A Register access may seem complex, but this is not case. When the double buffer- ing is enabled, the CPU has access to the OCR0A Buffer Register, and if double buffering is disabled the CPU will access the OCR0A directly. 12.5.1 Force Output Compare In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC0A) bit. Forcing compare match will not set the OCF0A flag or reload/clear the timer, but the OC0A pin will be updated as if a real compare match had occurred (the COM0A1:0 bits settings define whether the OC0A pin is set, cleared or toggled). 12.5.2 Compare Match Blocking by TCNT0 Write All CPU write operations to the TCNT0 Register will block any compare match that occur in the next timer clock cycle, even when the timer is stopped. This feature allows OCR0A to be initial- ized to the same value as TCNT0 without triggering an interrupt when the Timer/Counter clock is enabled. 12.5.3 Using the Output Compare Unit Since writing TCNT0 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT0 when using the Output Compare channel, independently of whether the Timer/Counter is running or not. If the value written to TCNT0 equals the OCR0A value, the compare match will be missed, resulting in incorrect waveform AT90CAN32/64/128 102 7679H–CAN–08/08

AT90CAN32/64/128 generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is downcounting. The setup of the OC0A should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC0A value is to use the Force Output Com- pare (FOC0A) strobe bits in Normal mode. The OC0A Register keeps its value even when changing between Waveform Generation modes. Be aware that the COM0A1:0 bits are not double buffered together with the compare value. Changing the COM0A1:0 bits will take effect immediately. 12.6 Compare Match Output Unit The Compare Output mode (COM0A1:0) bits have two functions. The Waveform Generator uses the COM0A1:0 bits for defining the Output Compare (OC0A) state at the next compare match. Also, the COM0A1:0 bits control the OC0A pin output source. Figure 12-4 shows a sim- plified schematic of the logic affected by the COM0A1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O port control regis- ters (DDR and PORT) that are affected by the COM0A1:0 bits are shown. When referring to the OC0A state, the reference is for the internal OC0A Register, not the OC0A pin. If a system reset occur, the OC0A Register is reset to “0”. Figure 12-4. Compare Match Output Unit, Schematic COMnx1 COMnx0 Waveform D Q FOCnx Generator 1 OCnx OCnx Pin 0 D Q S U B PORT A T A D D Q DDR clk I/O 12.6.1 Compare Output Function The general I/O port function is overridden by the Output Compare (OC0A) from the Waveform Generator if either of the COM0A1:0 bits are set. However, the OC0A pin direction (input or out- put) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC0A pin (DDR_OC0A) must be set as output before the OC0A value is vis- ible on the pin. The port override function is independent of the Waveform Generation mode. The design of the Output Compare pin logic allows initialization of the OC0A state before the output is enabled. Note that some COM0A1:0 bit settings are reserved for certain modes of operation. See “8-bit Timer/Counter Register Description” on page 109. 103 7679H–CAN–08/08

12.6.2 Compare Output Mode and Waveform Generation The Waveform Generator uses the COM0A1:0 bits differently in Normal, CTC, and PWM modes. For all modes, setting the COM0A1:0 = 0 tells the Waveform Generator that no action on the OC0A Register is to be performed on the next compare match. For compare output actions in the non-PWM modes refer to Table 12-2 on page 110. For fast PWM mode, refer to Table 12- 3 on page 110, and for phase correct PWM refer to Table 12-4 on page 111. A change of the COM0A1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC0A strobe bits. 12.7 Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM01:0) and Compare Output mode (COM0A1:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM0A1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COM0A1:0 bits control whether the output should be set, cleared, or toggled at a compare match (See “Compare Match Output Unit” on page 103.). For detailed timing information refer to Figure 12-8, Figure 12-9, Figure 12-10 and Figure 12-11 in “Timer/Counter Timing Diagrams” on page 108. 12.7.1 Normal Mode The simplest mode of operation is the Normal mode (WGM01:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bot- tom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV0) will be set in the same timer clock cycle as the TCNT0 becomes zero. The TOV0 flag in this case behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV0 flag, the timer resolution can be increased by software. There are no special cases to consider in the Normal mode, a new counter value can be written anytime. The Output Compare unit can be used to generate interrupts at some given time. Using the Out- put Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time. 12.7.2 Clear Timer on Compare Match (CTC) Mode In Clear Timer on Compare or CTC mode (WGM01:0 = 2), the OCR0A Register is used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT0) matches the OCR0A. The OCR0A defines the top value for the counter, hence also its resolution. This mode allows greater control of the compare match output frequency. It also simplifies the operation of counting external events. The timing diagram for the CTC mode is shown in Figure 12-5. The counter value (TCNT0) increases until a compare match occurs between TCNT0 and OCR0A, and then counter (TCNT0) is cleared. AT90CAN32/64/128 104 7679H–CAN–08/08

AT90CAN32/64/128 Figure 12-5. CTC Mode, Timing Diagram OCnx Interrupt Flag Set TCNTn OCnx (COMnx1:0 = 1) (Toggle) Period 1 2 3 4 An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCR0A is lower than the current value of TCNT0, the counter will miss the compare match. The counter will then have to count to its max- imum value (0xFF) and wrap around starting at 0x00 before the compare match can occur. For generating a waveform output in CTC mode, the OC0A output can be set to toggle its logical level on each compare match by setting the Compare Output mode bits to toggle mode (COM0A1:0 = 1). The OC0A value will not be visible on the port pin unless the data direction for the pin is set to output. The waveform generated will have a maximum frequency of f = OC0A f /2 when OCR0A is set to zero (0x00). The waveform frequency is defined by the following clk_I/O equation: f clk_I/O f = -------------------------------------------------- OCnx 2⋅N⋅(1+OCRnx) The N variable represents the prescale factor (1, 8, 64, 256, or 1024). As for the Normal mode of operation, the TOV0 flag is set in the same timer clock cycle that the counter counts from MAX to 0x00. 12.7.3 Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM01:0 = 3) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM option by its sin- gle-slope operation. The counter counts from BOTTOM to MAX then restarts from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC0A) is cleared on the compare match between TCNT0 and OCR0A, and set at BOTTOM. In inverting Compare Output mode, the output is set on compare match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM mode that use dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. In fast PWM mode, the counter is incremented until the counter value matches the MAX value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 12-6. The TCNT0 value is in the timing diagram shown as a his- togram for illustrating the single-slope operation. The diagram includes non-inverted and 105 7679H–CAN–08/08

inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0A and TCNT0. Figure 12-6. Fast PWM Mode, Timing Diagram OCRnx Interrupt Flag Set OCRnx Update and(cid:31) TOVn Interrupt Flag Set TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 5 6 7 The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches MAX. If the inter- rupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0A pin. Setting the COM0A1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM0A1:0 to three (See Table 12-3 on page 110). The actual OC0A value will only be visible on the port pin if the data direction for the port pin is set as out- put. The PWM waveform is generated by setting (or clearing) the OC0A Register at the compare match between OCR0A and TCNT0, and clearing (or setting) the OC0A Register at the timer clock cycle the counter is cleared (changes from MAX to BOTTOM). The PWM frequency for the output can be calculated by the following equation: f clk_I/O f = ------------------ OCnxPWM N⋅256 The N variable represents the prescale factor (1, 8, 64, 256, or 1024). The extreme values for the OCR0A Register represents special cases when generating a PWM waveform output in the fast PWM mode. If the OCR0A is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR0A equal to MAX will result in a constantly high or low output (depending on the polarity of the output set by the COM0A1:0 bits.) A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set- ting OC0A to toggle its logical level on each compare match (COM0A1:0 = 1). The waveform generated will have a maximum frequency of f = f /2 when OCR0A is set to zero. This OC0A clk_I/O feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the Out- put Compare unit is enabled in the fast PWM mode. AT90CAN32/64/128 106 7679H–CAN–08/08

AT90CAN32/64/128 12.7.4 Phase Correct PWM Mode The phase correct PWM mode (WGM01:0 = 1) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM. In non- inverting Compare Output mode, the Output Compare (OC0A) is cleared on the compare match between TCNT0 and OCR0A while upcounting, and set on the compare match while down- counting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the sym- metric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode is fixed to eight bits. In phase correct PWM mode the counter is incremented until the counter value matches MAX. When the counter reaches MAX, it changes the count direction. The TCNT0 value will be equal to MAX for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 12-7. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0A and TCNT0. Figure 12-7. Phase Correct PWM Mode, Timing Diagram OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The interrupt flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0A pin. Setting the COM0A1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM0A1:0 to three (See Table 12-4 on page 111). The actual OC0A value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by clearing (or setting) the OC0A Register at the compare match between OCR0A and TCNT0 when the counter increments, and setting (or clearing) the OC0A Register at compare match between OCR0A and TCNT0 when the counter 107 7679H–CAN–08/08

decrements. The PWM frequency for the output when using phase correct PWM can be calcu- lated by the following equation: f clk_I/O f = ------------------ OCnxPCPWM N⋅510 The N variable represents the prescale factor (1, 8, 64, 256, or 1024). The extreme values for the OCR0A Register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR0A is set equal to BOTTOM, the output will be continuously low and if set equal to MAX the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. 12.8 Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clk ) is therefore shown as a T0 clock enable signal in the following figures. The figures include information on when interrupt flags are set. Figure 12-8 contains timing data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes other than phase correct PWM mode. Figure 12-8. Timer/Counter Timing Diagram, no Prescaling clk I/O clk Tn (clk /1) I/O TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 12-9 shows the same timing data, but with the prescaler enabled. Figure 12-9. Timer/Counter Timing Diagram, with Prescaler (f /8) clk_I/O clk I/O clk Tn (clk /8) I/O TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn AT90CAN32/64/128 108 7679H–CAN–08/08

AT90CAN32/64/128 Figure 12-10 shows the setting of OCF0A in all modes except CTC mode. Figure 12-10. Timer/Counter Timing Diagram, Setting of OCF0A, with Prescaler (f /8) clk_I/O clk I/O clk Tn (clk /8) I/O TCNTn OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 OCRnx OCRnx Value OCFnx Figure 12-11 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode. Figure 12-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres- caler (f /8) clk_I/O clk I/O clk Tn (clk /8) I/O TCNTn TOP - 1 TOP BOTTOM BOTTOM + 1 (CTC) OCRnx TOP OCFnx 12.9 8-bit Timer/Counter Register Description 12.9.1 Timer/Counter0 Control Register A – TCCR0A Bit 7 6 5 4 3 2 1 0 FOC0A WGM00 COM0A1 COM0A0 WGM01 CS02 CS01 CS00 TCCR0A Read/Write W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM00 bit specifies a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0A is written when operating in PWM mode. When writing a logical one to the FOC0A bit, an immediate com- pare match is forced on the Waveform Generation unit. The OC0A output is changed according to its COM0A1:0 bits setting. Note that the FOC0A bit is implemented as a strobe. Therefore it is the value present in the COM0A1:0 bits that determines the effect of the forced compare. A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0A as TOP. The FOC0A bit is always read as zero. 109 7679H–CAN–08/08

• Bit 6, 3 – WGM01:0: Waveform Generation Mode These bits control the counting sequence of the counter, the source for the maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. See Table 12-1 and “Modes of Operation” on page 104. Table 12-1. Waveform Generation Mode Bit Description(1) WGM01 WGM00 Timer/Counter Update of TOV0 Flag Mode TOP (CTC0) (PWM0) Mode of Operation OCR0A at Set on 0 0 0 Normal 0xFF Immediate MAX 1 0 1 PWM, Phase Correct 0xFF TOP BOTTOM 2 1 0 CTC OCR0A Immediate MAX 3 1 1 Fast PWM 0xFF TOP MAX Note: 1. The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 definitions. However, the functionality and location of these bits are compatible with previous versions of the timer. • Bit 5:4 – COM01:0: Compare Match Output Mode These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0 bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0A pin must be set in order to enable the output driver. When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the WGM01:0 bit setting. Table 12-2 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to a normal or CTC mode (non-PWM). Table 12-2. Compare Output Mode, non-PWM Mode COM0A1 COM0A0 Description 0 0 Normal port operation, OC0A disconnected. 0 1 Toggle OC0A on compare match 1 0 Clear OC0A on compare match 1 1 Set OC0A on compare match Table 12-3 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast PWM mode. Table 12-3. Compare Output Mode, Fast PWM Mode(1) COM0A1 COM0A0 Description 0 0 Normal port operation, OC0A disconnected. 0 1 Reserved Clear OC0A on compare match. 1 0 Set OC0A at TOP Set OC0A on compare match. 1 1 Clear OC0A at TOP AT90CAN32/64/128 110 7679H–CAN–08/08

AT90CAN32/64/128 Note: 1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the com- pare match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode” on page 105 for more details. Table 12-4 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to phase cor- rect PWM mode. Table 12-4. Compare Output Mode, Phase Correct PWM Mode(1) COM0A1 COM0A0 Description 0 0 Normal port operation, OC0A disconnected. 0 1 Reserved Clear OC0A on compare match when up-counting. 1 0 Set OC0A on compare match when downcounting. Set OC0A on compare match when up-counting. 1 1 Clear OC0A on compare match when downcounting. Note: 1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the com- pare match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on page 107 for more details. • Bit 2:0 – CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter. Table 12-5. Clock Select Bit Description CS02 CS01 CS00 Description 0 0 0 No clock source (Timer/Counter stopped) 0 0 1 clk /(No prescaling) I/O 0 1 0 clk /8 (From prescaler) I/O 0 1 1 clk /64 (From prescaler) I/O 1 0 0 clk /256 (From prescaler) I/O 1 0 1 clk /1024 (From prescaler) I/O 1 1 0 External clock source on T0 pin. Clock on falling edge. 1 1 1 External clock source on T0 pin. Clock on rising edge. If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. 12.9.2 Timer/Counter0 Register – TCNT0 Bit 7 6 5 4 3 2 1 0 TCNT0[7:0] TCNT0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the compare match on the following timer clock. Modifying the counter (TCNT0) while the counter is running, introduces a risk of missing a compare match between TCNT0 and the OCR0A Register. 111 7679H–CAN–08/08

12.9.3 Output Compare Register A – OCR0A Bit 7 6 5 4 3 2 1 0 OCR0A[7:0] OCR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC0A pin. 12.9.4 Timer/Counter0 Interrupt Mask Register – TIMSK0 Bit 7 6 5 4 3 2 1 0 – – – – – – OCIE0A TOIE0 TIMSK0 Read/Write R R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 7..2 – Reserved Bits These are reserved bits for future use. • Bit 1 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable When the OCIE0A bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter0 occurs, i.e., when the OCF0A bit is set in the Timer/Counter 0 Interrupt Flag Register – TIFR0. • Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable When the TOIE0 bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter 0 Inter- rupt Flag Register – TIFR0. 12.9.5 Timer/Counter0 Interrupt Flag Register – TIFR0 Bit 7 6 5 4 3 2 1 0 – – – – – – OCF0A TOV0 TIFR0 Read/Write R R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 1 – OCF0A: Output Compare Flag 0 A The OCF0A bit is set (one) when a compare match occurs between the Timer/Counter0 and the data in OCR0A – Output Compare Register0. OCF0A is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF0A is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare match Interrupt Enable), and OCF0A are set (one), the Timer/Counter0 Compare match Interrupt is executed. • Bit 0 – TOV0: Timer/Counter0 Overflow Flag The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hard- ware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Inter- rupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed. In phase correct PWM mode, this bit is set when Timer/Counter0 changes counting direction at 0x00. AT90CAN32/64/128 112 7679H–CAN–08/08

AT90CAN32/64/128 13. 16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3) The 16-bit Timer/Counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. The main features are: 13.1 Features • True 16-bit Design (i.e., Allows 16-bit PWM) • Three independent Output Compare Units • Double Buffered Output Compare Registers • One Input Capture Unit • Input Capture Noise Canceler • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse Width Modulator (PWM) • Variable PWM Period • Frequency Generator • External Event Counter • Four independent interrupt Sources (TOV1, OCF1A, OCF1B, and ICF1 for Timer/Counter1 - TOV3, OCF3A, OCF3B, and ICF3 for Timer/Counter3) 13.2 Overview Many register and bit references in this section are written in general form. • A lower case “n” replaces the Timer/Counter number, in this case 1 or 3. However, when using the register or bit defines in a program, the precise form must be used, i.e., TCNT1 for accessing Timer/Counter1 counter value and so on. • A lower case “x” replaces the Output Compare unit channel, in this case A, B or C. However, when using the register or bit defines in a program, the precise form must be used, i.e., OCRnA for accessing Timer/Countern output compare channel A value and so on. A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 13-1. For the actual placement of I/O pins, refer to “Pin Configurations” on page 5. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit loca- tions are listed in the “16-bit Timer/Counter Register Description” on page 135. 113 7679H–CAN–08/08

Figure 13-1. 16-bit Timer/Counter Block Diagram(1) Count TOVn Clear (Int.Req.) Control Logic Direction clkTn Clock Select Edge Tn Detector TOP BOTTOM ( From Prescaler ) Timer/Counter TCNTn = = 0 OCFnA (Int.Req.) = Waveform OCnA Generation OCRnA OCFnB Fixed TOP (Int.Req.) Values = Waveform OCnB Generation S U OCRnB B A OCFnC T (Int.Req.) A D = Waveform OCnC Generation OCRnC ( From Analog Comparator Ouput ) ICFn (Int.Req.) Edge Noise ICRn Detector Canceler ICPn TCCRnA TCCRnB TCCRnC Note: 1. Refer to Figure 1-2 on page 5 or Figure 1-3 on page 6, Table 9-6 on page 76, and Table 9-15 on page 83 for Timer/Counter1 and 3 pin placement and description. 13.2.1 Registers The Timer/Counter (TCNTn), Output Compare Registers (OCRnx), and Input Capture Register (ICRn) are all 16-bit registers. Special procedures must be followed when accessing the 16-bit registers. These procedures are described in the section “Accessing 16-bit Registers” on page 116. The Timer/Counter Control Registers (TCCRnx) are 8-bit registers and have no CPU access restrictions. Interrupt requests (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFRn). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSKn). TIFRn and TIMSKn are not shown in the figure. The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the Tn pin. The Clock Select logic block controls which clock source and edge the Timer/Counter AT90CAN32/64/128 114 7679H–CAN–08/08

AT90CAN32/64/128 uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clk ). Tn The double buffered Output Compare Registers (OCRnx) are compared with the Timer/Counter value at all time. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pin (OCnx). See “Output Compare Units” on page 123.. The compare match event will also set the Compare Match Flag (OCFnx) which can be used to generate an Output Compare interrupt request. The Input Capture Register can capture the Timer/Counter value at a given external (edge trig- gered) event on either the Input Capture pin (ICPn) or on the Analog Comparator pins (See “Analog Comparator” on page 269.) The Input Capture unit includes a digital filtering unit (Noise Canceler) for reducing the chance of capturing noise spikes. The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined by either the OCRnA Register, the ICRn Register, or by a set of fixed values. When using OCRnA as TOP value in a PWM mode, the OCRnA Register can not be used for generating a PWM output. However, the TOP value will in this case be double buffered allowing the TOP value to be changed in run time. If a fixed TOP value is required, the ICRn Register can be used as an alternative, freeing the OCRnA to be used as PWM output. 13.2.2 Definitions The following definitions are used extensively throughout the section: BOTTOM The counter reaches the BOTTOM when it becomes 0x0000. MAX The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65,535). The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF, TOP or 0x03FF, or to the value stored in the OCRnA or ICRn Register. The assignment is dependent of the mode of operation. 13.2.3 Compatibility The 16-bit Timer/Counter has been updated and improved from previous versions of the 16-bit AVR Timer/Counter. This 16-bit Timer/Counter is fully compatible with the earlier version regarding: • All 16-bit Timer/Counter related I/O Register address locations, including Timer Interrupt Registers. • Bit locations inside all 16-bit Timer/Counter Registers, including Timer Interrupt Registers. • Interrupt Vectors. The following control bits have changed name, but have same functionality and register location: • PWMn0 is changed to WGMn0. • PWMn1 is changed to WGMn1. • CTCn is changed to WGMn2. The following registers are added to the 16-bit Timer/Counter: • Timer/Counter Control Register C (TCCRnC). • Output Compare Register C, OCRnCH and OCRnCL, combined OCRnC. 115 7679H–CAN–08/08

The 16-bit Timer/Counter has improvements that will affect the compatibility in some special cases. The following bits are added to the 16-bit Timer/Counter Control Registers: • COMnC1:0 are added to TCCRnA. • FOCnA, FOCnB and FOCnC are added to TCCRnC. • WGMn3 is added to TCCRnB. Interrupt flag and mask bits for output compare unit C are added. The 16-bit Timer/Counter has improvements that will affect the compatibility in some special cases. 13.3 Accessing 16-bit Registers The TCNTn, OCRnx, and ICRn are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations. Each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16-bit access. The same temporary register is shared between all 16-bit registers within each 16-bit timer. Accessing the low byte triggers the 16-bit read or write operation. When the low byte of a 16-bit register is written by the CPU, the high byte stored in the temporary register, and the low byte written are both copied into the 16-bit register in the same clock cycle. When the low byte of a 16-bit register is read by the CPU, the high byte of the 16-bit register is copied into the tempo- rary register in the same clock cycle as the low byte is read. Not all 16-bit accesses uses the temporary register for the high byte. Reading the OCRnx 16-bit registers does not involve using the temporary register. To do a 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low byte must be read before the high byte. AT90CAN32/64/128 116 7679H–CAN–08/08

AT90CAN32/64/128 13.3.1 Code Examples The following code examples show how to access the 16-bit timer registers assuming that no interrupts updates the temporary register. The same principle can be used directly for accessing the OCRnx and ICRn Registers. Note that when using “C”, the compiler handles the 16-bit access. Assembly Code Examples(1) ... ; Set TCNTn to 0x01FF ldi r17,0x01 ldi r16,0xFF sts TCNTnH,r17 sts TCNTnL,r16 ; Read TCNTn into r17:r16 lds r16,TCNTnL lds r17,TCNTnH ... C Code Examples(1) unsigned int i; ... /* Set TCNTn to 0x01FF */ TCNTn = 0x1FF; /* Read TCNTn into i */ i = TCNTn; ... Note: 1. The example code assumes that the part specific header file is included. The assembly code example returns the TCNTn value in the r17:r16 register pair. It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt occurs between the two instructions accessing the 16-bit register, and the interrupt code updates the temporary register by accessing the same or any other of the 16-bit timer registers, then the result of the access outside the interrupt will be corrupted. Therefore, when both the main code and the interrupt code update the temporary register, the main code must disable the interrupts during the 16-bit access. 117 7679H–CAN–08/08

The following code examples show how to do an atomic read of the TCNTn Register contents. Reading any of the OCRnx or ICRn Registers can be done by using the same principle. Assembly Code Example(1) TIM16_ReadTCNTn: ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Read TCNTn into r17:r16 lds r16,TCNTnL lds r17,TCNTnH ; Restore global interrupt flag out SREG,r18 ret C Code Example(1) unsigned int TIM16_ReadTCNTn(void) { unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Read TCNTn into i */ i = TCNTn; /* Restore global interrupt flag */ SREG = sreg; return i; } Note: 1. The example code assumes that the part specific header file is included. The assembly code example returns the TCNTn value in the r17:r16 register pair. AT90CAN32/64/128 118 7679H–CAN–08/08

AT90CAN32/64/128 The following code examples show how to do an atomic write of the TCNTn Register contents. Writing any of the OCRnx or ICRn Registers can be done by using the same principle. Assembly Code Example(1) TIM16_WriteTCNTn: ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Set TCNTn to r17:r16 sts TCNTnH,r17 sts TCNTnL,r16 ; Restore global interrupt flag out SREG,r18 ret C Code Example(1) void TIM16_WriteTCNTn(unsigned int i) { unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ _CLI(); /* Set TCNTn to i */ TCNTn = i; /* Restore global interrupt flag */ SREG = sreg; } Note: 1. The example code assumes that the part specific header file is included. The assembly code example requires that the r17:r16 register pair contains the value to be writ- ten to TCNTn. 13.3.2 Reusing the Temporary High Byte Register If writing to more than one 16-bit register where the high byte is the same for all registers written, then the high byte only needs to be written once. However, note that the same rule of atomic operation described previously also applies in this case. 13.4 Timer/Counter Clock Sources The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CSn2:0) bits located in the Timer/Counter control Register B (TCCRnB). For details on clock sources and prescaler, see “Timer/Counter3/1/0 Prescalers” on page 96. 119 7679H–CAN–08/08

13.5 Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 13-2 shows a block diagram of the counter and its surroundings. Figure 13-2. Counter Unit Block Diagram DATA BUS (8-bit) TOVn (Int.Req.) TEMP (8-bit) Clock Select Count Edge Tn TCNTnH (8-bit) TCNTnL (8-bit) Clear clk Detector Control Logic Tn Direction TCNTn (16-bit Counter) ( From Prescaler ) TOP BOTTOM Signal description (internal signals): Count Increment or decrement TCNTn by 1. Direction Select between increment and decrement. Clear Clear TCNTn (set all bits to zero). clk Timer/Counter clock. Tn TOP Signalize that TCNTn has reached maximum value. BOTTOM Signalize that TCNTn has reached minimum value (zero). The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNTnH) con- taining the upper eight bits of the counter, and Counter Low (TCNTnL) containing the lower eight bits. The TCNTnH Register can only be indirectly accessed by the CPU. When the CPU does an access to the TCNTnH I/O location, the CPU accesses the high byte temporary register (TEMP). The temporary register is updated with the TCNTnH value when the TCNTnL is read, and TCNTnH is updated with the temporary register value when TCNTnL is written. This allows the CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus. It is important to notice that there are special cases of writing to the TCNTn Register when the counter is counting that will give unpredictable results. The special cases are described in the sections where they are of importance. Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk ). The clk can be generated from an external or internal clock source, Tn Tn selected by the Clock Select bits (CSn2:0). When no clock source is selected (CSn2:0 = 0) the timer is stopped. However, the TCNTn value can be accessed by the CPU, independent of whether clk is present or not. A CPU write overrides (has priority over) all counter clear or Tn count operations. The counting sequence is determined by the setting of the Waveform Generation mode bits (WGMn3:0) located in the Timer/Counter Control Registers A and B (TCCRnA and TCCRnB). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare outputs OCnx. For more details about advanced counting sequences and waveform generation, see “Modes of Operation” on page 126. AT90CAN32/64/128 120 7679H–CAN–08/08

AT90CAN32/64/128 The Timer/Counter Overflow Flag (TOVn) is set according to the mode of operation selected by the WGMn3:0 bits. TOVn can be used for generating a CPU interrupt. 13.6 Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can capture external events and give them a time-stamp indicating time of occurrence. The external signal indicating an event, or mul- tiple events, can be applied via the ICPn pin or alternatively, via the analog-comparator unit. The time-stamps can then be used to calculate frequency, duty-cycle, and other features of the sig- nal applied. Alternatively the time-stamps can be used for creating a log of the events. The Input Capture unit is illustrated by the block diagram shown in Figure 13-3. The elements of the block diagram that are not directly a part of the Input Capture unit are gray shaded. Figure 13-3. Input Capture Unit Block Diagram DATA BUS (8-bit) TEMP (8-bit) ICRnH (8-bit) ICRnL (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) WRITE ICRn (16-bit Register) TCNTn (16-bit Counter) ICNC3 ICES3 Noise Edge ICP3 ICF3 (Int.Req.) Canceler Detector ACIC* ICNC1 ICES1 ICP1 Noise Edge ICF1 (Int.Req.) Canceler Detector ACO* Analog Comparator Note: The Analog Comparator Output (ACO) can only trigger the Timer/Counter1 IC Unit– not Timer/Counter3. When a change of the logic level (an event) occurs on the Input Capture pin (ICPn), alternatively on the Analog Comparator output (ACO), and this change confirms to the setting of the edge detector, a capture will be triggered. When a capture is triggered, the 16-bit value of the counter (TCNTn) is written to the Input Capture Register (ICRn). The Input Capture Flag (ICFn) is set at the same system clock as the TCNTn value is copied into ICRn Register. If enabled (ICIEn = 1), the Input Capture Flag generates an Input Capture interrupt. The ICFn flag is automatically 121 7679H–CAN–08/08

cleared when the interrupt is executed. Alternatively the ICFn flag can be cleared by software by writing a logical one to its I/O bit location. Reading the 16-bit value in the Input Capture Register (ICRn) is done by first reading the low byte (ICRnL) and then the high byte (ICRnH). When the low byte is read the high byte is copied into the high byte temporary register (TEMP). When the CPU reads the ICRnH I/O location it will access the TEMP Register. The ICRn Register can only be written when using a Waveform Generation mode that utilizes the ICRn Register for defining the counter’s TOP value. In these cases the Waveform Genera- tion mode (WGMn3:0) bits must be set before the TOP value can be written to the ICRn Register. When writing the ICRn Register the high byte must be written to the ICRnH I/O location before the low byte is written to ICRnL. For more information on how to access the 16-bit registers refer to “Accessing 16-bit Registers” on page 116. 13.6.1 Input Capture Trigger Source The main trigger source for the Input Capture unit is the Input Capture pin (ICPn). Only Timer/Counter1 can alternatively use the Analog Comparator output as trigger source for the Input Capture unit. The Analog Comparator is selected as trigger source by setting the Analog Comparator Input Capture (ACIC) bit in the Analog Comparator Control and Status Register (ACSR). Be aware that changing trigger source can trigger a capture. The Input Capture Flag must therefore be cleared after the change. Both the Input Capture pin (ICPn) and the Analog Comparator output (ACO) inputs are sampled using the same technique as for the Tn pin (Figure 11-1 on page 97). The edge detector is also identical. However, when the noise canceler is enabled, additional logic is inserted before the edge detector, which increases the delay by four system clock cycles. Note that the input of the noise canceler and edge detector is always enabled unless the Timer/Counter is set in a Wave- form Generation mode that uses ICRn to define TOP. An Input Capture can be triggered by software by controlling the port of the ICPn pin. 13.6.2 Noise Canceler The noise canceler improves noise immunity by using a simple digital filtering scheme. The noise canceler input is monitored over four samples, and all four must be equal for changing the output that in turn is used by the edge detector. The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNCn) bit in Timer/Counter Control Register B (TCCRnB). When enabled the noise canceler introduces addi- tional four system clock cycles of delay from a change applied to the input, to the update of the ICRn Register. The noise canceler uses the system clock and is therefore not affected by the prescaler. 13.6.3 Using the Input Capture Unit The main challenge when using the Input Capture unit is to assign enough processor capacity for handling the incoming events. The time between two events is critical. If the processor has not read the captured value in the ICRn Register before the next event occurs, the ICRn will be overwritten with a new value. In this case the result of the capture will be incorrect. When using the Input Capture interrupt, the ICRn Register should be read as early in the inter- rupt handler routine as possible. Even though the Input Capture interrupt has relatively high AT90CAN32/64/128 122 7679H–CAN–08/08

AT90CAN32/64/128 priority, the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests. Using the Input Capture unit in any mode of operation when the TOP value (resolution) is actively changed during operation, is not recommended. Measurement of an external signal’s duty cycle requires that the trigger edge is changed after each capture. Changing the edge sensing must be done as early as possible after the ICRn Register has been read. After a change of the edge, the Input Capture Flag (ICFn) must be cleared by software (writing a logical one to the I/O bit location). For measuring frequency only, the clearing of the ICFn flag is not required (if an interrupt handler is used). 13.7 Output Compare Units The 16-bit comparator continuously compares TCNTn with the Output Compare Register (OCRnx). If TCNT equals OCRnx the comparator signals a match. A match will set the Output Compare Flag (OCFnx) at the next timer clock cycle. If enabled (OCIEnx = 1), the Output Com- pare Flag generates an Output Compare interrupt. The OCFnx flag is automatically cleared when the interrupt is executed. Alternatively the OCFnx flag can be cleared by software by writ- ing a logical one to its I/O bit location. The Waveform Generator uses the match signal to generate an output according to operating mode set by the Waveform Generation mode (WGMn3:0) bits and Compare Output mode (COMnx1:0) bits. The TOP and BOTTOM signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation (See “Modes of Operation” on page 126.) A special feature of Output Compare unit A allows it to define the Timer/Counter TOP value (i.e., counter resolution). In addition to the counter resolution, the TOP value defines the period time for waveforms generated by the Waveform Generator. Figure 13-4 shows a block diagram of the Output Compare unit. The elements of the block dia- gram that are not directly a part of the Output Compare unit are gray shaded. 123 7679H–CAN–08/08

Figure 13-4. Output Compare Unit, Block Diagram DATA BUS (8-bit) TEMP (8-bit) OCRnxH Buf.(8-bit) OCRnxL Buf.(8-bit) TCNTnH (8-bit) TCNTnL (8-bit) OCRnx Buffer (16-bit Register) TCNTn (16-bit Counter) OCRnxH (8-bit) OCRnxL (8-bit) OCRnx (16-bit Register) = (16-bit Comparator ) OCFnx (Int.Req.) TOP Waveform Generator OCnx BOTTOM WGMn3:0 COMnx1:0 The OCRnx Register is double buffered when using any of the twelve Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCRnx Com- pare Register to either TOP or BOTTOM of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the out- put glitch-free. The OCRnx Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCRnx Buffer Register, and if double buffering is dis- abled the CPU will access the OCRnx directly. The content of the OCRnx (Buffer or Compare) Register is only changed by a write operation (the Timer/Counter does not update this register automatically as the TCNT1 and ICRn Register). Therefore OCRnx is not read via the high byte temporary register (TEMP). However, it is a good practice to read the low byte first as when accessing other 16-bit registers. Writing the OCRnx Registers must be done via the TEMP Reg- ister since the compare of all 16 bits is done continuously. The high byte (OCRnxH) has to be written first. When the high byte I/O location is written by the CPU, the TEMP Register will be updated by the value written. Then when the low byte (OCRnxL) is written to the lower eight bits, the high byte will be copied into the upper 8-bits of either the OCRnx buffer or OCRnx Compare Register in the same system clock cycle. For more information of how to access the 16-bit registers refer to “Accessing 16-bit Registers” on page 116. 13.7.1 Force Output Compare In non-PWM Waveform Generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOCnx) bit. Forcing compare match will not set the OCFnx flag or reload/clear the timer, but the OCnx pin will be updated as if a real compare AT90CAN32/64/128 124 7679H–CAN–08/08

AT90CAN32/64/128 match had occurred (the COMnx1:0 bits settings define whether the OCnx pin is set, cleared or toggled). 13.7.2 Compare Match Blocking by TCNTn Write All CPU writes to the TCNTn Register will block any compare match that occurs in the next timer clock cycle, even when the timer is stopped. This feature allows OCRnx to be initialized to the same value as TCNTn without triggering an interrupt when the Timer/Counter clock is enabled. 13.7.3 Using the Output Compare Unit Since writing TCNTn in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNTn when using any of the Output Compare channels, independent of whether the Timer/Counter is running or not. If the value written to TCNTn equals the OCRnx value, the compare match will be missed, resulting in incorrect wave- form generation. Do not write the TCNTn equal to TOP in PWM modes with variable TOP values. The compare match for the TOP will be ignored and the counter will continue to 0xFFFF. Similarly, do not write the TCNTn value equal to BOTTOM when the counter is downcounting. The setup of the OCnx should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OCnx value is to use the Force Output Com- pare (FOCnx) strobe bits in Normal mode. The OCnx Register keeps its value even when changing between Waveform Generation modes. Be aware that the COMnx1:0 bits are not double buffered together with the compare value. Changing the COMnx1:0 bits will take effect immediately. 13.8 Compare Match Output Unit The Compare Output mode (COMnx1:0) bits have two functions. The Waveform Generator uses the COMnx1:0 bits for defining the Output Compare (OCnx) state at the next compare match. Secondly the COMnx1:0 bits control the OCnx pin output source. Figure 13-5 shows a simplified schematic of the logic affected by the COMnx1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O port control registers (DDR and PORT) that are affected by the COMnx1:0 bits are shown. When referring to the OCnx state, the reference is for the internal OCnx Register, not the OCnx pin. If a system reset occur, the OCnx Register is reset to “0”. 125 7679H–CAN–08/08

Figure 13-5. Compare Match Output Unit, Schematic COMnx1 COMnx0 Waveform D Q FOCnx Generator 1 OCnx OCnx Pin 0 D Q S U B PORT A T A D D Q DDR clk I/O 13.8.1 Compare Output Function The general I/O port function is overridden by the Output Compare (OCnx) from the Waveform Generator if either of the COMnx1:0 bits are set. However, the OCnx pin direction (input or out- put) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OCnx pin (DDR_OCnx) must be set as output before the OCnx value is visi- ble on the pin. The port override function is generally independent of the Waveform Generation mode, but there are some exceptions. Refer to Table 13-1, Table 13-2 and Table 13-3 for details. The design of the Output Compare pin logic allows initialization of the OCnx state before the out- put is enabled. Note that some COMnx1:0 bit settings are reserved for certain modes of operation. See “16-bit Timer/Counter Register Description” on page 135. The COMnx1:0 bits have no effect on the Input Capture unit. 13.8.2 Compare Output Mode and Waveform Generation The Waveform Generator uses the COMnx1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COMnx1:0 = 0 tells the Waveform Generator that no action on the OCnx Register is to be performed on the next compare match. For compare output actions in the non-PWM modes refer to Table 13-1 on page 136. For fast PWM mode refer to Table 13-2 on page 136, and for phase correct and phase and frequency correct PWM refer to Table 13-3 on page 137. A change of the COMnx1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOCnx strobe bits. 13.9 Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGMn3:0) and Compare Output mode (COMnx1:0) bits. The Compare Output mode bits do not affect the counting sequence, AT90CAN32/64/128 126 7679H–CAN–08/08

AT90CAN32/64/128 while the Waveform Generation mode bits do. The COMnx1:0 bits control whether the PWM out- put generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COMnx1:0 bits control whether the output should be set, cleared or toggle at a compare match (See “Compare Match Output Unit” on page 125.) For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 134. 13.9.1 Normal Mode The simplest mode of operation is the Normal mode (WGMn3:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and then restarts from the BOTTOM (0x0000). In normal operation the Timer/Counter Overflow Flag (TOVn) will be set in the same timer clock cycle as the TCNTn becomes zero. The TOVn flag in this case behaves like a 17th bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOVn flag, the timer resolution can be increased by soft- ware. There are no special cases to consider in the Normal mode, a new counter value can be written anytime. The Input Capture unit is easy to use in Normal mode. However, observe that the maximum interval between the external events must not exceed the resolution of the counter. If the interval between events are too long, the timer overflow interrupt or the prescaler must be used to extend the resolution for the capture unit. The Output Compare units can be used to generate interrupts at some given time. Using the Output Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time. 13.9.2 Clear Timer on Compare Match (CTC) Mode In Clear Timer on Compare or CTC mode (WGMn3:0 = 4 or 12), the OCRnA or ICRn Register are used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNTn) matches either the OCRnA (WGMn3:0 = 4) or the ICRn (WGMn3:0 = 12). The OCRnA or ICRn define the top value for the counter, hence also its resolution. This mode allows greater control of the compare match output frequency. It also simplifies the opera- tion of counting external events. The timing diagram for the CTC mode is shown in Figure 13-6. The counter value (TCNTn) increases until a compare match occurs with either OCRnA or ICRn, and then counter (TCNTn) is cleared. Figure 13-6. CTC Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TCNTn OCnA (COMnA1:0 = 1) (Toggle) Period 1 2 3 4 127 7679H–CAN–08/08

An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCFnA or ICFn flag according to the register used to define the TOP value. If the inter- rupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing the TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCRnA or ICRn is lower than the current value of TCNTn, the counter will miss the compare match. The counter will then have to count to its maximum value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur. In many cases this feature is not desirable. An alternative will then be to use the fast PWM mode using OCRnA for defining TOP (WGMn3:0 = 15) since the OCRnA then will be double buffered. For generating a waveform output in CTC mode, the OCnA output can be set to toggle its logical level on each compare match by setting the Compare Output mode bits to toggle mode (COMnA1:0 = 1). The OCnA value will not be visible on the port pin unless the data direction for the pin is set to output (DDR_OCnA = 1). The waveform generated will have a maximum fre- quency of f = f /2 when OCRnA is set to zero (0x0000). The waveform frequency is OCnA clk_I/O defined by the following equation: f clk_I/O f = --------------------------------------------------- OCnA 2⋅N⋅(1+OCRnA) The N variable represents the prescaler factor (1, 8, 64, 256, or 1024). As for the Normal mode of operation, the TOVn flag is set in the same timer clock cycle that the counter counts from MAX to 0x0000. 13.9.3 Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGMn3:0 = 5, 6, 7, 14, or 15) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM options by its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OCnx) is set on the compare match between TCNTn and OCRnx, and cleared at TOP. In inverting Compare Output mode output is cleared on compare match and set at TOP. Due to the single-slope oper- ation, the operating frequency of the fast PWM mode can be twice as high as the phase correct and phase and frequency correct PWM modes that use dual-slope operation. This high fre- quency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capaci- tors), hence reduces total system cost. The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the max- imum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM resolution in bits can be calculated by using the following equation: log(TOP+1) R = ----------------------------------- FPWM log(2) In fast PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGMn3:0 = 5, 6, or 7), the value in ICRn (WGMn3:0 = 14), or the value in OCRnA (WGMn3:0 = 15). The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 13-7. The figure AT90CAN32/64/128 128 7679H–CAN–08/08

AT90CAN32/64/128 shows fast PWM mode when OCRnA or ICRn is used to define TOP. The TCNTn value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNTn slopes represent compare matches between OCRnx and TCNTn. The OCnx interrupt flag will be set when a compare match occurs. Figure 13-7. Fast PWM Mode, Timing Diagram OCRnx/TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 5 6 7 8 The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches TOP. In addition the OCnA or ICFn flag is set at the same timer clock cycle as TOVn is set when either OCRnA or ICRn is used for defining the TOP value. If one of the interrupts are enabled, the interrupt han- dler routine can be used for updating the TOP and compare values. When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will never occur between the TCNTn and the OCRnx. Note that when using fixed TOP values the unused bits are masked to zero when any of the OCRnx Registers are written. The procedure for updating ICRn differs from updating OCRnA when used for defining the TOP value. The ICRn Register is not double buffered. This means that if ICRn is changed to a low value when the counter is running with none or a low prescaler value, there is a risk that the new ICRn value written is lower than the current value of TCNTn. The result will then be that the counter will miss the compare match at the TOP value. The counter will then have to count to the MAX value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur. The OCRnA Register however, is double buffered. This feature allows the OCRnA I/O location to be written anytime. When the OCRnA I/O location is written the value written will be put into the OCRnA Buffer Register. The OCRnA Compare Register will then be updated with the value in the Buffer Register at the next timer clock cycle the TCNTn matches TOP. The update is done at the same timer clock cycle as the TCNTn is cleared and the TOVn flag is set. Using the ICRn Register for defining TOP works well when using fixed TOP values. By using ICRn, the OCRnA Register is free to be used for generating a PWM output on OCnA. However, if the base PWM frequency is actively changed (by changing the TOP value), using the OCRnA as TOP is clearly a better choice due to its double buffer feature. 129 7679H–CAN–08/08

In fast PWM mode, the compare units allow generation of PWM waveforms on the OCnx pins. Setting the COMnx1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COMnx1:0 to three (see Table on page 136). The actual OCnx value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OCnx). The PWM waveform is generated by setting (or clearing) the OCnx Register at the compare match between OCRnx and TCNTn, and clearing (or setting) the OCnx Register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM). The PWM frequency for the output can be calculated by the following equation: f clk_I/O f = ----------------------------------- OCnxPWM N⋅(1+TOP) The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCRnx Register represents special cases when generating a PWM waveform output in the fast PWM mode. If the OCRnx is set equal to BOTTOM (0x0000) the out- put will be a narrow spike for each TOP+1 timer clock cycle. Setting the OCRnx equal to TOP will result in a constant high or low output (depending on the polarity of the output set by the COMnx1:0 bits.) A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set- ting OCnA to toggle its logical level on each compare match (COMnA1:0 = 1). The waveform generated will have a maximum frequency of f = f /2 when OCRnA is set to zero OCnA clk_I/O (0x0000). This feature is similar to the OCnA toggle in CTC mode, except the double buffer fea- ture of the Output Compare unit is enabled in the fast PWM mode. 13.9.4 Phase Correct PWM Mode The phase correct Pulse Width Modulation or phase correct PWM mode (WGMn3:0=1, 2, 3, 10, or 11) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is, like the phase and frequency correct PWM mode, based on a dual- slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OCnx) is cleared on the compare match between TCNTn and OCRnx while upcounting, and set on the compare match while downcounting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the maximum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM resolu- tion in bits can be calculated by using the following equation: log(TOP+1) R = ----------------------------------- PCPWM log(2) In phase correct PWM mode the counter is incremented until the counter value matches either one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGMn3:0 = 1, 2, or 3), the value in ICRn (WGMn3:0 = 10), or the value in OCRnA (WGMn3:0 = 11). The counter has then reached the TOP and changes the count direction. The TCNTn value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 13-8. The figure shows phase correct PWM mode when OCRnA or ICRn is used to define TOP. The TCNTn AT90CAN32/64/128 130 7679H–CAN–08/08

AT90CAN32/64/128 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNTn slopes represent compare matches between OCRnx and TCNTn. The OCnx inter- rupt flag will be set when a compare match occurs. Figure 13-8. Phase Correct PWM Mode, Timing Diagram OCRnx/TOP Update and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches BOTTOM. When either OCRnA or ICRn is used for defining the TOP value, the OCnA or ICFn flag is set accord- ingly at the same timer clock cycle as the OCRnx Registers are updated with the double buffer value (at TOP). The interrupt flags can be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value. When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will never occur between the TCNTn and the OCRnx. Note that when using fixed TOP values, the unused bits are masked to zero when any of the OCRnx Registers are written. As the third period shown in Figure 13-8 illustrates, changing the TOP actively while the Timer/Counter is running in the phase correct mode can result in an unsymmetrical output. The reason for this can be found in the time of update of the OCRnx Reg- ister. Since the OCRnx update occurs at TOP, the PWM period starts and ends at TOP. This implies that the length of the falling slope is determined by the previous TOP value, while the length of the rising slope is determined by the new TOP value. When these two values differ the two slopes of the period will differ in length. The difference in length gives the unsymmetrical result on the output. It is recommended to use the phase and frequency correct mode instead of the phase correct mode when changing the TOP value while the Timer/Counter is running. When using a static TOP value there are practically no differences between the two modes of operation. In phase correct PWM mode, the compare units allow generation of PWM waveforms on the OCnx pins. Setting the COMnx1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COMnx1:0 to three (See Table on page 137). The actual OCnx value will only be visible on the port pin if the data direction for the port pin is set as 131 7679H–CAN–08/08

output (DDR_OCnx). The PWM waveform is generated by setting (or clearing) the OCnx Regis- ter at the compare match between OCRnx and TCNTn when the counter increments, and clearing (or setting) the OCnx Register at compare match between OCRnx and TCNTn when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: f clk_I/O f = ---------------------------- OCnxPCPWM 2⋅N⋅TOP The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCRnx Register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCRnx is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. 13.9.5 Phase and Frequency Correct PWM Mode The phase and frequency correct Pulse Width Modulation, or phase and frequency correct PWM mode (WGMn3:0 = 8 or 9) provides a high resolution phase and frequency correct PWM wave- form generation option. The phase and frequency correct PWM mode is, like the phase correct PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OCnx) is cleared on the compare match between TCNTn and OCRnx while upcounting, and set on the compare match while downcounting. In inverting Compare Output mode, the operation is inverted. The dual-slope operation gives a lower maximum operation fre- quency compared to the single-slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The main difference between the phase correct, and the phase and frequency correct PWM mode is the time the OCRnx Register is updated by the OCRnx Buffer Register, (see Figure 13- 8 and Figure 13-9). The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the maximum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM resolution in bits can be calculated using the following equation: log(TOP+1) R = ----------------------------------- PFCPWM log(2) In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the value in ICRn (WGMn3:0 = 8), or the value in OCRnA (WGMn3:0 = 9). The counter has then reached the TOP and changes the count direction. The TCNTn value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct and frequency correct PWM mode is shown on Figure 13-9. The figure shows phase and frequency correct PWM mode when OCRnA or ICRn is used to define TOP. The TCNTn value is in the timing dia- gram shown as a histogram for illustrating the dual-slope operation. The diagram includes non- inverted and inverted PWM outputs. The small horizontal line marks on the TCNTn slopes repre- sent compare matches between OCRnx and TCNTn. The OCnx interrupt flag will be set when a compare match occurs. AT90CAN32/64/128 132 7679H–CAN–08/08

AT90CAN32/64/128 Figure 13-9. Phase and Frequency Correct PWM Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx/TOP Update and TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 The Timer/Counter Overflow Flag (TOVn) is set at the same timer clock cycle as the OCRnx Registers are updated with the double buffer value (at BOTTOM). When either OCRnA or ICRn is used for defining the TOP value, the OCnA or ICFn flag set when TCNTn has reached TOP. The interrupt flags can then be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value. When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will never occur between the TCNTn and the OCRnx. As Figure 13-9 shows the output generated is, in contrast to the phase correct mode, symmetri- cal in all periods. Since the OCRnx Registers are updated at BOTTOM, the length of the rising and the falling slopes will always be equal. This gives symmetrical output pulses and is therefore frequency correct. Using the ICRn Register for defining TOP works well when using fixed TOP values. By using ICRn, the OCRnA Register is free to be used for generating a PWM output on OCnA. However, if the base PWM frequency is actively changed by changing the TOP value, using the OCRnA as TOP is clearly a better choice due to its double buffer feature. In phase and frequency correct PWM mode, the compare units allow generation of PWM wave- forms on the OCnx pins. Setting the COMnx1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COMnx1:0 to three (See Table on page 137). The actual OCnx value will only be visible on the port pin if the data direction for the port pin is set as output (DDR_OCnx). The PWM waveform is generated by setting (or clearing) the OCnx Register at the compare match between OCRnx and TCNTn when the counter incre- ments, and clearing (or setting) the OCnx Register at compare match between OCRnx and TCNTn when the counter decrements. The PWM frequency for the output when using phase and frequency correct PWM can be calculated by the following equation: f clk_I/O f = ---------------------------- OCnxPFCPWM 2⋅N⋅TOP 133 7679H–CAN–08/08

The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCRnx Register represents special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCRnx is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be set to high for non- inverted PWM mode. For inverted PWM the output will have the opposite logic values. 13.10 Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clk ) is therefore shown as a Tn clock enable signal in the following figures. The figures include information on when interrupt flags are set, and when the OCRnx Register is updated with the OCRnx buffer value (only for modes utilizing double buffering). Figure 13-10 shows a timing diagram for the setting of OCFnx. Figure 13-10. Timer/Counter Timing Diagram, Setting of OCFnx, no Prescaling clk I/O clk Tn (clk /1) I/O TCNTn OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 OCRnx OCRnx Value OCFnx Figure 13-11 shows the same timing data, but with the prescaler enabled. Figure 13-11. Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (f /8) clk_I/O clk I/O clk Tn (clk /8) I/O TCNTn OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 OCRnx OCRnx Value OCFnx Figure 13-12 shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode the OCRnx Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOVn flag at BOTTOM. AT90CAN32/64/128 134 7679H–CAN–08/08

AT90CAN32/64/128 Figure 13-12. Timer/Counter Timing Diagram, no Prescaling clk I/O clk Tn (clk /1) I/O TCNTn TOP - 1 TOP BOTTOM BOTTOM + 1 (CTC and FPWM) TCNTn TOP - 1 TOP TOP - 1 TOP - 2 (PC and PFC PWM) TOVn (FPWM) and ICFn (if used as TOP) OCRnx Old OCRnx Value New OCRnx Value (Update at TOP) Figure 13-13 shows the same timing data, but with the prescaler enabled. Figure 13-13. Timer/Counter Timing Diagram, with Prescaler (f /8) clk_I/O clk I/O clk Tn (clk/8) I/O TCNTn TOP - 1 TOP BOTTOM BOTTOM + 1 (CTC and FPWM) TCNTn TOP - 1 TOP TOP - 1 TOP - 2 (PC and PFC PWM) TOVn( FPWM) and ICFn (ifused as TOP) OCRnx Old OCRnx Value New OCRnx Value (Update at TOP) 13.11 16-bit Timer/Counter Register Description 13.11.1 Timer/Counter1 Control Register A – TCCR1A Bit 7 6 5 4 3 2 1 0 COM1A1 COM1A0 COM1B1 COM1B0 COM1C1 COM1C0 WGM11 WGM10 TCCR1A Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 13.11.2 Timer/Counter3 Control Register A – TCCR3A Bit 7 6 5 4 3 2 1 0 COM3A1 COM3A0 COM3B1 COM3B0 COM3C1 COM3C0 WGM31 WGM30 TCCR3A Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 135 7679H–CAN–08/08

• Bit 7:6 – COMnA1:0: Compare Output Mode for Channel A • Bit 5:4 – COMnB1:0: Compare Output Mode for Channel B • Bit 3:2 – COMnC1:0: Compare Output Mode for Channel C The COMnA1:0, COMnB1:0 and COMnC1:0 control the Output Compare pins (OCnA, OCnB and OCnC respectively) behavior. If one or both of the COMnA1:0 bits are written to one, the OCnA output overrides the normal port functionality of the I/O pin it is connected to. If one or both of the COMnB1:0 bit are written to one, the OCnB output overrides the normal port func- tionality of the I/O pin it is connected to. If one or both of the COMnC1:0 bit are written to one, the OCnC output overrides the normal port functionality of the I/O pin it is connected to. How- ever, note that the Data Direction Register (DDR) bit corresponding to the OCnA, OCnB or OCnC pin must be set in order to enable the output driver. When the OCnA, OCnB or OCnC is connected to the pin, the function of the COMnx1:0 bits is dependent of the WGMn3:0 bits setting. Table 13-1 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to a Normal or a CTC mode (non-PWM). Table 13-1. Compare Output Mode, non-PWM COMnA1/COMnB1/ COMnA0/COMnB0/ Description COMnC1 COMnC0 Normal port operation, OCnA/OCnB/OCnC 0 0 disconnected. 0 1 Toggle OCnA/OCnB/OCnC on Compare Match. Clear OCnA/OCnB/OCnC on Compare Match (Set 1 0 output to low level). Set OCnA/OCnB/OCnC on Compare Match (Set 1 1 output to high level). Table 13-2 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the fast PWM mode. Table 13-2. Compare Output Mode, Fast PWM (1) COMnA1/COMnB1/ COMnA0/COMnB0/ Description COMnC1 COMnC0 Normal port operation, OCnA/OCnB/OCnC 0 0 disconnected. WGMn3=0: Normal port operation, OCnA/OCnB/OCnC disconnected. 0 1 WGMn3=1: Toggle OCnA on Compare Match, OCnB/OCnC reserved. Clear OCnA/OCnB/OCnC on Compare Match 1 0 Set OCnA/OCnB/OCnC at TOP Set OCnA/OCnB/OCnC on Compare Match 1 1 Clear OCnA/OCnB/OCnC at TOP Note: 1. A special case occurs when OCRnA/OCRnB/OCRnC equals TOP and COMnA1/COMnB1/COMnC1 is set. In this case the compare match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode” on page 128. for more details. AT90CAN32/64/128 136 7679H–CAN–08/08

AT90CAN32/64/128 Table 13-3 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the phase correct or the phase and frequency correct, PWM mode. Table 13-3. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM(1) COMnA1/COMnB1/ COMnA0/COMnB0/ Description COMnC1 COMnC0 Normal port operation, OCnA/OCnB/OCnC 0 0 disconnected. WGMn3=0: Normal port operation, OCnA/OCnB/OCnC disconnected. 0 1 WGMn3=1: Toggle OCnA on Compare Match, OCnB/OCnC reserved. Clear OCnA/OCnB/OCnC on Compare Match when up-counting. 1 0 Set OCnA/OCnB/OCnC on Compare Match when downcounting. Set OCnA/OCnB/OCnC on Compare Match when up- counting. 1 1 Clear OCnA/OCnB/OCnC on Compare Match when downcounting. Note: 1. A special case occurs when OCnA/OCnB/OCnC equals TOP and COMnA1/COMnB1/COMnC1 is set. See “Phase Correct PWM Mode” on page 130. for more details. • Bit 1:0 – WGMn1:0: Waveform Generation Mode Combined with the WGMn3:2 bits found in the TCCRnB Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of wave- form generation to be used, see Table 13-4. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. (See “Modes of Operation” on page 126.). 137 7679H–CAN–08/08

Table 13-4. Waveform Generation Mode Bit Description (1) WGMn2 WGMn1 WGMn0 Timer/Counter Update of TOVn Flag Mode WGMn3 TOP (CTCn) (PWMn1) (PWMn0) Mode of Operation OCRnx at Set on 0 0 0 0 0 Normal 0xFFFF Immediate MAX 1 0 0 0 1 PWM, Phase Correct, 8-bit 0x00FF TOP BOTTOM 2 0 0 1 0 PWM, Phase Correct, 9-bit 0x01FF TOP BOTTOM PWM, Phase Correct, 10- 3 0 0 1 1 0x03FF TOP BOTTOM bit 4 0 1 0 0 CTC OCRnA Immediate MAX 5 0 1 0 1 Fast PWM, 8-bit 0x00FF TOP TOP 6 0 1 1 0 Fast PWM, 9-bit 0x01FF TOP TOP 7 0 1 1 1 Fast PWM, 10-bit 0x03FF TOP TOP PWM, Phase and 8 1 0 0 0 ICRn BOTTOM BOTTOM Frequency Correct PWM, Phase and 9 1 0 0 1 OCRnA BOTTOM BOTTOM Frequency Correct 10 1 0 1 0 PWM, Phase Correct ICRn TOP BOTTOM 11 1 0 1 1 PWM, Phase Correct OCRnA TOP BOTTOM 12 1 1 0 0 CTC ICRn Immediate MAX 13 1 1 0 1 (Reserved) – – – 14 1 1 1 0 Fast PWM ICRn TOP TOP 15 1 1 1 1 Fast PWM OCRnA TOP TOP Note: 1. The CTCn and PWMn1:0 bit definition names are obsolete. Use the WGMn2:0 definitions. However, the functionality and location of these bits are compatible with previous versions of the timer. 13.11.3 Timer/Counter1 Control Register B – TCCR1B Bit 7 6 5 4 3 2 1 0 ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 TCCR1B Read/Write R/W R/W R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 13.11.4 Timer/Counter3 Control Register B – TCCR3B Bit 7 6 5 4 3 2 1 0 ICNC3 ICES3 – WGM33 WGM32 CS32 CS31 CS30 TCCR3B Read/Write R/W R/W R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 7 – ICNCn: Input Capture Noise Canceler Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is activated, the input from the Input Capture pin (ICPn) is filtered. The filter function requires four successive equal valued samples of the ICPn pin for changing its output. The Input Capture is therefore delayed by four Oscillator cycles when the noise canceler is enabled. • Bit 6 – ICESn: Input Capture Edge Select AT90CAN32/64/128 138 7679H–CAN–08/08

AT90CAN32/64/128 This bit selects which edge on the Input Capture pin (ICPn) that is used to trigger a capture event. When the ICESn bit is written to zero, a falling (negative) edge is used as trigger, and when the ICESn bit is written to one, a rising (positive) edge will trigger the capture. When a capture is triggered according to the ICESn setting, the counter value is copied into the Input Capture Register (ICRn). The event will also set the Input Capture Flag (ICFn), and this can be used to cause an Input Capture Interrupt, if this interrupt is enabled. When the ICRn is used as TOP value (see description of the WGMn3:0 bits located in the TCCRnA and the TCCRnB Register), the ICPn is disconnected and consequently the Input Cap- ture function is disabled. • Bit 5 – Reserved Bit This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero when TCCRnB is written. • Bit 4:3 – WGMn3:2: Waveform Generation Mode See TCCRnA Register description. • Bit 2:0 – CSn2:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter, see Figure 13-10 and Figure 13-11. Table 13-5. Clock Select Bit Description CSn2 CSn1 CSn0 Description 0 0 0 No clock source (Timer/Counter stopped). 0 0 1 clk /1 (No prescaling) I/O 0 1 0 clk /8 (From prescaler) I/O 0 1 1 clk /64 (From prescaler) I/O 1 0 0 clk /256 (From prescaler) I/O 1 0 1 clk /1024 (From prescaler) I/O 1 1 0 External clock source on Tn pin. Clock on falling edge. 1 1 1 External clock source on Tn pin. Clock on rising edge. If external pin modes are used for the Timer/Countern, transitions on the Tn pin will clock the counter even if the pin is configured as an output. This feature allows software control of the counting. 13.11.5 Timer/Counter1 Control Register C – TCCR1C Bit 7 6 5 4 3 2 1 0 FOC1A FOC1B FOC1C – – – – – TCCR1C Read/Write R/W R/W R/W R R R R R Initial Value 0 0 0 0 0 0 0 0 139 7679H–CAN–08/08

13.11.6 Timer/Counter3 Control Register C – TCCR3C Bit 7 6 5 4 3 2 1 0 FOC3A FOC3B FOC3C – – – – – TCCR3C Read/Write R/W R/W R/W R R R R R Initial Value 0 0 0 0 0 0 0 0 • Bit 7 – FOCnA: Force Output Compare for Channel A • Bit 6 – FOCnB: Force Output Compare for Channel B • Bit 5 – FOCnC: Force Output Compare for Channel C The FOCnA/FOCnB/FOCnC bits are only active when the WGMn3:0 bits specifies a non-PWM mode. However, for ensuring compatibility with future devices, these bits must be set to zero when TCCRnA is written when operating in a PWM mode. When writing a logical one to the FOCnA/FOCnB/FOCnC bit, an immediate compare match is forced on the Waveform Genera- tion unit. The OCnA/OCnB/OCnC output is changed according to its COMnx1:0 bits setting. Note that the FOCnA/FOCnB/FOCnC bits are implemented as strobes. Therefore it is the value present in the COMnx1:0 bits that determine the effect of the forced compare. A FOCnA/FOCnB/FOCnC strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCRnA as TOP. The FOCnA/FOCnB/FOCnC bits are always read as zero. 13.11.7 Timer/Counter1 – TCNT1H and TCNT1L Bit 7 6 5 4 3 2 1 0 TCNT1[15:8] TCNT1H TCNT1[7:0] TCNT1L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 13.11.8 Timer/Counter3 – TCNT3H and TCNT3L Bit 7 6 5 4 3 2 1 0 TCNT3[15:8] TCNT3H TCNT3[7:0] TCNT3L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The two Timer/Counter I/O locations (TCNTnH and TCNTnL, combined TCNTn) give direct access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 116. Modifying the counter (TCNTn) while the counter is running introduces a risk of missing a com- pare match between TCNTn and one of the OCRnx Registers. Writing to the TCNTn Register blocks (removes) the compare match on the following timer clock for all compare units. AT90CAN32/64/128 140 7679H–CAN–08/08

AT90CAN32/64/128 13.11.9 Output Compare Register A – OCR1AH and OCR1AL Bit 7 6 5 4 3 2 1 0 OCR1A[15:8] OCR1AH OCR1A[7:0] OCR1AL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 13.11.10 Output Compare Register B – OCR1BH and OCR1BL Bit 7 6 5 4 3 2 1 0 OCR1B[15:8] OCR1BH OCR1B[7:0] OCR1BL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 13.11.11 Output Compare Register C – OCR1CH and OCR1CL Bit 7 6 5 4 3 2 1 0 OCR1C[15:8] OCR1CH OCR1C[7:0] OCR1CL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 13.11.12 Output Compare Register A – OCR3AH and OCR3AL Bit 7 6 5 4 3 2 1 0 OCR3A[15:8] OCR3AH OCR3A[7:0] OCR3AL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 13.11.13 Output Compare Register B – OCR3BH and OCR3BL Bit 7 6 5 4 3 2 1 0 OCR3B[15:8] OCR3BH OCR3B[7:0] OCR3BL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 13.11.14 Output Compare Register C – OCR3CH and OCR3CL Bit 7 6 5 4 3 2 1 0 OCR3C[15:8] OCR3CH OCR3C[7:0] OCR3CL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNTn). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OCnx pin. The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16- bit registers. See “Accessing 16-bit Registers” on page 116. 141 7679H–CAN–08/08

13.11.15 Input Capture Register – ICR1H and ICR1L Bit 7 6 5 4 3 2 1 0 ICR1[15:8] ICR1H ICR1[7:0] ICR1L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 13.11.16 Input Capture Register – ICR3H and ICR3L Bit 7 6 5 4 3 2 1 0 ICR3[15:8] ICR3H ICR3[7:0] ICR3L Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Input Capture is updated with the counter (TCNTn) value each time an event occurs on the ICPn pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture can be used for defining the counter TOP value. The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 116. 13.11.17 Timer/Counter1 Interrupt Mask Register – TIMSK1 Bit 7 6 5 4 3 2 1 0 – – ICIE1 – OCIE1C OCIE1B OCIE1A TOIE1 TIMSK1 Read/Write R R R/W R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 13.11.18 Timer/Counter3 Interrupt Mask Register – TIMSK3 Bit 7 6 5 4 3 2 1 0 – – ICIE3 – OCIE3C OCIE3B OCIE3A TOIE3 TIMSK3 Read/Write R R R/W R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 7..6 – Reserved Bits These bits are reserved for future use. • Bit 5 – ICIEn: Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Countern Input Capture interrupt is enabled. The corresponding Interrupt Vector (See “Interrupts” on page 60.) is executed when the ICFn flag, located in TIFRn, is set. • Bit 4 – Reserved Bit This bit is reserved for future use. • Bit 3 – OCIEnC: Output Compare C Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Countern Output Compare C Match interrupt is enabled. The corresponding Interrupt Vector (See “Interrupts” on page 60.) is executed when the OCFnC flag, located in TIFRn, is set. AT90CAN32/64/128 142 7679H–CAN–08/08

AT90CAN32/64/128 • Bit 2 – OCIEnB: Output Compare B Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Countern Output Compare B Match interrupt is enabled. The corresponding Interrupt Vector (See “Interrupts” on page 60.) is executed when the OCFnB flag, located in TIFRn, is set. • Bit 1 – OCIEnA: Output Compare A Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Countern Output Compare A Match interrupt is enabled. The corresponding Interrupt Vector (See “Interrupts” on page 60.) is executed when the OCFnA flag, located in TIFRn, is set. • Bit 0 – TOIEn: Timer/Counter Overflow Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Countern Overflow interrupt is enabled. The corresponding Interrupt Vector (See “Interrupts” on page 60.) is executed when the TOVn flag, located in TIFRn, is set. 13.11.19 Timer/Counter1 Interrupt Flag Register – TIFR1 Bit 7 6 5 4 3 2 1 0 – – ICF1 – OCF1C OCF1B OCF1A TOV1 TIFR1 Read/Write R R R/W R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 13.11.20 Timer/Counter3 Interrupt Flag Register – TIFR3 Bit 7 6 5 4 3 2 1 0 – – ICF3 – OCF3C OCF3B OCF3A TOV3 TIFR3 Read/Write R R R/W R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 7..6 – Reserved Bits These bits are reserved for future use. • Bit 5 – ICFn: Input Capture Flag This flag is set when a capture event occurs on the ICPn pin. When the Input Capture Register (ICRn) is set by the WGMn3:0 to be used as the TOP value, the ICFn flag is set when the counter reaches the TOP value. ICFn is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICFn can be cleared by writing a logic one to its bit location. • Bit 4 – Reserved Bit This bit is reserved for future use. • Bit 3 – OCFnC: Output Compare C Match Flag This flag is set in the timer clock cycle after the counter (TCNTn) value matches the Output Compare Register C (OCRnC). Note that a Forced Output Compare (FOCnC) strobe will not set the OCFnC flag. OCFnC is automatically cleared when the Output Compare Match C Interrupt Vector is exe- cuted. Alternatively, OCFnC can be cleared by writing a logic one to its bit location. 143 7679H–CAN–08/08

• Bit 2 – OCFnB: Output Compare B Match Flag This flag is set in the timer clock cycle after the counter (TCNTn) value matches the Output Compare Register B (OCRnB). Note that a Forced Output Compare (FOCnB) strobe will not set the OCFnB flag. OCFnB is automatically cleared when the Output Compare Match B Interrupt Vector is exe- cuted. Alternatively, OCFnB can be cleared by writing a logic one to its bit location. • Bit 1 – OCFnA: Output Compare A Match Flag This flag is set in the timer clock cycle after the counter (TCNTn) value matches the Output Compare Register A (OCRnA). Note that a Forced Output Compare (FOCnA) strobe will not set the OCFnA flag. OCFnA is automatically cleared when the Output Compare Match A Interrupt Vector is exe- cuted. Alternatively, OCFnA can be cleared by writing a logic one to its bit location. • Bit 0 – TOVn: Timer/Counter Overflow Flag The setting of this flag is dependent of the WGMn3:0 bits setting. In Normal and CTC modes, the TOVn flag is set when the timer overflows. Refer to Table 13-4 on page 138 for the TOVn flag behavior when using another WGMn3:0 bit setting. TOVn is automatically cleared when the Timer/Countern Overflow Interrupt Vector is executed. Alternatively, TOVn can be cleared by writing a logic one to its bit location. AT90CAN32/64/128 144 7679H–CAN–08/08

AT90CAN32/64/128 14. 8-bit Timer/Counter2 with PWM and Asynchronous Operation Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are: 14.1 Features • Single Channel Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse Width Modulator (PWM) • Frequency Generator • 10-bit Clock Prescaler • Overflow and Compare Match Interrupt Sources (TOV2 and OCF2A) • Allows Clocking from External 32 kHz Watch Crystal Independent of the I/O Clock 14.2 Overview Many register and bit references in this section are written in general form. • A lower case “n” replaces the Timer/Counter number, in this case 2. However, when using the register or bit defines in a program, the precise form must be used, i.e., TCNT2 for accessing Timer/Counter2 counter value and so on. • A lower case “x” replaces the Output Compare unit channel, in this case A. However, when using the register or bit defines in a program, the precise form must be used, i.e., OCR2A for accessing Timer/Counter2 output compare channel A value and so on. A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 14-1. For the actual placement of I/O pins, refer to Figure 1-2 on page 5 or Figure 1-3 on page 6. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the “8-bit Timer/Counter Register Description” on page 157. 145 7679H–CAN–08/08

Figure 14-1. 8-bit Timer/Counter2 Block Diagram TCCRnx count TOVn clear (Int.Req.) Control Logic direction clk Tn TOSC2 BOTTOM TOP T/C Oscillator Prescaler TOSC1 Timer/Counter TCNTn = 0 = 0xFF OCnx clkI/O S (Int.Req.) U A B = GWeanveerfaotriomn OCnx T A D OCRnx clk Synchronized Status flags I/O Synchronization Unit clk ASY Status flags ASSRn asynchronous mode select (ASn) The Timer/Counter (TCNT2) and Output Compare Register (OCR2A) are 8-bit registers. Inter- rupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR2). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK2). TIFR2 and TIMSK2 are not shown in the figure. The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from the TOSC1/2 pins, as detailed later in this section. The asynchronous operation is controlled by the Asynchronous Status Register (ASSR). The Clock Select logic block controls which clock source the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inac- tive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clk ). T2 The double buffered Output Compare Register (OCR2A) is compared with the Timer/Counter value at all times. The result of the compare can be used by the Waveform Generator to gener- ate a PWM or variable frequency output on the Output Compare pin (OC2A). See “Output Compare Unit” on page 148. for details. The compare match event will also set the compare flag (OCF2A) which can be used to generate an Output Compare interrupt request. AT90CAN32/64/128 146 7679H–CAN–08/08

AT90CAN32/64/128 14.2.1 Definitions The following definitions are used extensively throughout the section: BOTTOM The counter reaches the BOTTOM when it becomes zero (0x00). MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255). TOP The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR2A Register. The assignment is depen- dent on the mode of operation. 14.3 Timer/Counter Clock Sources The Timer/Counter can be clocked by an internal synchronous or an external asynchronous clock source. The clock source is selected by the clock select logic which is controlled by the clock select (CS22:0) bits located in the Timer/Counter control register (TCCR2).The clock source clk is by default equal to the MCU clock, clk . When the AS2 bit in the ASSR Register T2 I/O is written to logic one, the clock source is taken from the Timer/Counter Oscillator connected to TOSC1 and TOSC2 or directly from TOSC1. For details on asynchronous operation, see “Asyn- chronous Status Register – ASSR” on page 160. For details on clock sources and prescaler, see “Timer/Counter2 Prescaler” on page 163. 14.4 Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 14-2 shows a block diagram of the counter and its surrounding environment. Figure 14-2. Counter Unit Block Diagram TOVn DATA BUS (Int.Req.) TOSC2 count T/C TCNTn clear Control Logic clkTn Prescaler clkTnS Oscillator direction TOSC1 bottom top clk I/O Figure 14-3. Signal description (internal signals): count Increment or decrement TCNT2 by 1. direction Selects between increment and decrement. clear Clear TCNT2 (set all bits to zero). clk Timer/Counter clock. T2 top Signalizes that TCNT2 has reached maximum value. bottom Signalizes that TCNT2 has reached minimum value (zero). 147 7679H–CAN–08/08

Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk ). clk can be generated from an external or internal clock source, T2 T2 selected by the Clock Select bits (CS22:0). When no clock source is selected (CS22:0 = 0) the timer is stopped. However, the TCNT2 value can be accessed by the CPU, regardless of whether clk is present or not. A CPU write overrides (has priority over) all counter clear or T2 count operations. The counting sequence is determined by the setting of the WGM21 and WGM20 bits located in the Timer/Counter Control Register (TCCR2A). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare output OC2A. For more details about advanced counting sequences and waveform generation, see “Modes of Operation” on page 150. The Timer/Counter Overflow Flag (TOV2) is set according to the mode of operation selected by the WGM21:0 bits. TOV2 can be used for generating a CPU interrupt. 14.5 Output Compare Unit The 8-bit comparator continuously compares TCNT2 with the Output Compare Register (OCR2A). Whenever TCNT2 equals OCR2A, the comparator signals a match. A match will set the Output Compare Flag (OCF2A) at the next timer clock cycle. If enabled (OCIE2A = 1), the Output Compare Flag generates an Output Compare interrupt. The OCF2A flag is automatically cleared when the interrupt is executed. Alternatively, the OCF2A flag can be cleared by software by writing a logical one to its I/O bit location. The Waveform Generator uses the match signal to generate an output according to operating mode set by the WGM21:0 bits and Compare Output mode (COM2A1:0) bits. The max and bottom signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation (“Modes of Oper- ation” on page 150). Figure 14-4 shows a block diagram of the Output Compare unit. Figure 14-4. Output Compare Unit, Block Diagram DATA BUS OCRnx TCNTn = (8-bit Comparator ) OCFnx (Int.Req.) top bottom Waveform Generator OCnx FOCn WGMn1:0 COMnX1:0 The OCR2A Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR2A Compare AT90CAN32/64/128 148 7679H–CAN–08/08

AT90CAN32/64/128 Register to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR2A Register access may seem complex, but this is not case. When the double buffer- ing is enabled, the CPU has access to the OCR2A Buffer Register, and if double buffering is disabled the CPU will access the OCR2A directly. 14.5.1 Force Output Compare In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC2A) bit. Forcing compare match will not set the OCF2A flag or reload/clear the timer, but the OC2A pin will be updated as if a real compare match had occurred (the COM2A1:0 bits settings define whether the OC2A pin is set, cleared or toggled). 14.5.2 Compare Match Blocking by TCNT2 Write All CPU write operations to the TCNT2 Register will block any compare match that occurs in the next timer clock cycle, even when the timer is stopped. This feature allows OCR2A to be initial- ized to the same value as TCNT2 without triggering an interrupt when the Timer/Counter clock is enabled. 14.5.3 Using the Output Compare Unit Since writing TCNT2 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT2 when using the Output Compare channel, independently of whether the Timer/Counter is running or not. If the value written to TCNT2 equals the OCR2A value, the compare match will be missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT2 value equal to BOTTOM when the counter is downcounting. The setup of the OC2A should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC2A value is to use the Force Output Com- pare (FOC2A) strobe bit in Normal mode. The OC2A Register keeps its value even when changing between Waveform Generation modes. Be aware that the COM2A1:0 bits are not double buffered together with the compare value. Changing the COM2A1:0 bits will take effect immediately. 14.6 Compare Match Output Unit The Compare Output mode (COM2A1:0) bits have two functions. The Waveform Generator uses the COM2A1:0 bits for defining the Output Compare (OC2A) state at the next compare match. Also, the COM2A1:0 bits control the OC2A pin output source. Figure 14-5 shows a sim- plified schematic of the logic affected by the COM2A1:0 bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O port control regis- ters (DDR and PORT) that are affected by the COM2A1:0 bits are shown. When referring to the OC2A state, the reference is for the internal OC2A Register, not the OC2A pin. 149 7679H–CAN–08/08

Figure 14-5. Compare Match Output Unit, Schematic COMnx1 COMnx0 Waveform D Q FOCnx Generator 1 OCnx OCnx Pin 0 D Q S U B PORT A T A D D Q DDR clk I/O 14.6.1 Compare Output Function The general I/O port function is overridden by the Output Compare (OC2A) from the Waveform Generator if either of the COM2A1:0 bits are set. However, the OC2A pin direction (input or out- put) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC2A pin (DDR_OC2A) must be set as output before the OC2A value is vis- ible on the pin. The port override function is independent of the Waveform Generation mode. The design of the Output Compare pin logic allows initialization of the OC2A state before the output is enabled. Note that some COM2A1:0 bit settings are reserved for certain modes of operation. See “8-bit Timer/Counter Register Description” on page 157. 14.6.2 Compare Output Mode and Waveform Generation The Waveform Generator uses the COM2A1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM2A1:0 = 0 tells the Waveform Generator that no action on the OC2A Register is to be performed on the next compare match. For compare output actions in the non-PWM modes refer to Table 14-2 on page 158. For fast PWM mode, refer to Table 14-3 on page 158, and for phase correct PWM refer to Table 14-4 on page 159. A change of the COM2A1:0 bits state will have effect at the first compare match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC2A strobe bits. 14.7 Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM21:0) and Compare Output mode (COM2A1:0) bits. The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM2A1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COM2A1:0 bits control whether the output should be set, cleared, or toggled at a compare match (See “Compare Match Output Unit” on page 149.). AT90CAN32/64/128 150 7679H–CAN–08/08

AT90CAN32/64/128 For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 155. 14.7.1 Normal Mode The simplest mode of operation is the Normal mode (WGM21:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bot- tom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV2) will be set in the same timer clock cycle as the TCNT2 becomes zero. The TOV2 flag in this case behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV2 flag, the timer resolution can be increased by software. There are no special cases to consider in the Normal mode, a new counter value can be written anytime. The Output Compare unit can be used to generate interrupts at some given time. Using the Out- put Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time. 14.7.2 Clear Timer on Compare Match (CTC) Mode In Clear Timer on Compare or CTC mode (WGM21:0 = 2), the OCR2A Register is used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT2) matches the OCR2A. The OCR2A defines the top value for the counter, hence also its resolution. This mode allows greater control of the compare match output frequency. It also simplifies the operation of counting external events. The timing diagram for the CTC mode is shown in Figure 14-6. The counter value (TCNT2) increases until a compare match occurs between TCNT2 and OCR2A, and then counter (TCNT2) is cleared. Figure 14-6. CTC Mode, Timing Diagram OCnx Interrupt Flag Set TCNTn OCnx (COMnx1:0 = 1) (Toggle) Period 1 2 3 4 An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2A flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing the TOP to a value close to BOTTOM when the counter is run- ning with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCR2A is lower than the current value of TCNT2, the counter will miss the compare match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can occur. 151 7679H–CAN–08/08

For generating a waveform output in CTC mode, the OC2A output can be set to toggle its logical level on each compare match by setting the Compare Output mode bits to toggle mode (COM2A1:0 = 1). The OC2A value will not be visible on the port pin unless the data direction for the pin is set to output. The waveform generated will have a maximum frequency of f = OC2A f /2 when OCR2A is set to zero (0x00). The waveform frequency is defined by the following clk_I/O equation: f clk_I/O f = -------------------------------------------------- OCnx 2⋅N⋅(1+OCRnx) The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). As for the Normal mode of operation, the TOV2 flag is set in the same timer clock cycle that the counter counts from MAX to 0x00. 14.7.3 Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM21:0 = 3) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM option by its sin- gle-slope operation. The counter counts from BOTTOM to MAX then restarts from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC2A) is cleared on the compare match between TCNT2 and OCR2A, and set at BOTTOM. In inverting Compare Output mode, the output is set on compare match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM mode that uses dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. In fast PWM mode, the counter is incremented until the counter value matches the MAX value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 14-7. The TCNT2 value is in the timing diagram shown as a his- togram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2A and TCNT2. Figure 14-7. Fast PWM Mode, Timing Diagram OCRnx Interrupt Flag Set OCRnx Update and(cid:31) TOVn Interrupt Flag Set TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 5 6 7 AT90CAN32/64/128 152 7679H–CAN–08/08

AT90CAN32/64/128 The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches MAX. If the inter- rupt is enabled, the interrupt handler routine can be used for updating the compare value. In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2A pin. Setting the COM2A1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM2A1:0 to three (See Table 14-3 on page 158). The actual OC2A value will only be visible on the port pin if the data direction for the port pin is set as out- put. The PWM waveform is generated by setting (or clearing) the OC2A Register at the compare match between OCR2A and TCNT2, and clearing (or setting) the OC2A Register at the timer clock cycle the counter is cleared (changes from MAX to BOTTOM). The PWM frequency for the output can be calculated by the following equation: f clk_I/O f = ------------------ OCnxPWM N⋅256 The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). The extreme values for the OCR2A Register represent special cases when generating a PWM waveform output in the fast PWM mode. If the OCR2A is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR2A equal to MAX will result in a constantly high or low output (depending on the polarity of the output set by the COM2A1:0 bits.) A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set- ting OC2A to toggle its logical level on each compare match (COM2A1:0 = 1). The waveform generated will have a maximum frequency of f = f /2 when OCR2A is set to zero. This oc2A clk_I/O feature is similar to the OC2A toggle in CTC mode, except the double buffer feature of the Out- put Compare unit is enabled in the fast PWM mode. 14.7.4 Phase Correct PWM Mode The phase correct PWM mode (WGM21:0 = 1) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM. In non- inverting Compare Output mode, the Output Compare (OC2A) is cleared on the compare match between TCNT2 and OCR2A while upcounting, and set on the compare match while down- counting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the sym- metric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode is fixed to eight bits. In phase correct PWM mode the counter is incremented until the counter value matches MAX. When the counter reaches MAX, it changes the count direction. The TCNT2 value will be equal to MAX for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 14-8. The TCNT2 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2A and TCNT2. 153 7679H–CAN–08/08

Figure 14-8. Phase Correct PWM Mode, Timing Diagram OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The interrupt flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2A pin. Setting the COM2A1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM2A1:0 to three (See Table 14-4 on page 159). The actual OC2A value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by clearing (or setting) the OC2A Register at the compare match between OCR2A and TCNT2 when the counter increments, and setting (or clearing) the OC2A Register at compare match between OCR2A and TCNT2 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calcu- lated by the following equation: f clk_I/O f = ------------------ OCnxPCPWM N⋅510 The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). The extreme values for the OCR2A Register represent special cases when generating a PWM waveform output in the phase correct PWM mode. If the OCR2A is set equal to BOTTOM, the output will be continuously low and if set equal to MAX the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. At the very start of period 2 in Figure 14-8 on page 154 OCnx has a transition from high to low even though there is no Compare Match. The point of this transition is to guarantee symmetry around BOTTOM. There are two cases that give a transition without Compare Match. • OCR2A changes its value from MAX, like in Figure 14-8 on page 154. When the OCR2A value is MAX the OCn pin value is the same as the result of a down-counting compare AT90CAN32/64/128 154 7679H–CAN–08/08

AT90CAN32/64/128 match. To ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-counting Compare Match. • The timer starts counting from a value higher than the one in OCR2A, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up. 14.8 Timer/Counter Timing Diagrams The following figures show the Timer/Counter in synchronous mode, and the timer clock (clk ) T2 is therefore shown as a clock enable signal. In asynchronous mode, clk should be replaced by I/O the Timer/Counter Oscillator clock. The figures include information on when interrupt flags are set. Figure 14-9 contains timing data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes other than phase correct PWM mode. Figure 14-9. Timer/Counter Timing Diagram, no Prescaling clk I/O clk Tn (clk /1) I/O TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 14-10 shows the same timing data, but with the prescaler enabled. Figure 14-10. Timer/Counter Timing Diagram, with Prescaler (f /8) clk_I/O clk I/O clk Tn (clk /8) I/O TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 14-11 shows the setting of OCF2A in all modes except CTC mode. 155 7679H–CAN–08/08

Figure 14-11. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (f /8) clk_I/O clk I/O clk Tn (clk /8) I/O TCNTn OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2 OCRnx OCRnx Value OCFnx AT90CAN32/64/128 156 7679H–CAN–08/08

AT90CAN32/64/128 Figure 14-12 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode. Figure 14-12. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres- caler (f /8) clk_I/O clk I/O clk Tn (clk /8) I/O TCNTn TOP - 1 TOP BOTTOM BOTTOM + 1 (CTC) OCRnx TOP OCFnx 14.9 8-bit Timer/Counter Register Description 14.9.1 Timer/Counter2 Control Register A– TCCR2A Bit 7 6 5 4 3 2 1 0 FOC2A WGM20 COM2A1 COM2A0 WGM21 CS22 CS21 CS20 TCCR2A Read/Write W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 7 – FOC2A: Force Output Compare A The FOC2A bit is only active when the WGM bits specify a non-PWM mode. However, for ensur- ing compatibility with future devices, this bit must be set to zero when TCCR2A is written when operating in PWM mode. When writing a logical one to the FOC2A bit, an immediate compare match is forced on the Waveform Generation unit. The OC2A output is changed according to its COM2A1:0 bits setting. Note that the FOC2A bit is implemented as a strobe. Therefore it is the value present in the COM2A1:0 bits that determines the effect of the forced compare. A FOC2A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR2A as TOP. The FOC2A bit is always read as zero. • Bit 6, 3 – WGM21:0: Waveform Generation Mode These bits control the counting sequence of the counter, the source for the maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and 157 7679H–CAN–08/08

two types of Pulse Width Modulation (PWM) modes. See Table 14-1 and “Modes of Operation” on page 150. Table 14-1. Waveform Generation Mode Bit Description(1) WGM21 WGM20 Timer/Counter Update of TOV2 Flag Mode TOP (CTC2) (PWM2) Mode of Operation OCR2A at Set on 0 0 0 Normal 0xFF Immediate MAX 1 0 1 PWM, Phase Correct 0xFF TOP BOTTOM 2 1 0 CTC OCR2A Immediate MAX 3 1 1 Fast PWM 0xFF TOP MAX Note: 1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 definitions. However, the functionality and location of these bits are compatible with previous versions of the timer. • Bit 5:4 – COM2A1:0: Compare Match Output Mode A These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A1:0 bits are set, the OC2A output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to OC2A pin must be set in order to enable the output driver. When OC2A is connected to the pin, the function of the COM2A1:0 bits depends on the WGM21:0 bit setting. Table 14-2 shows the COM2A1:0 bit functionality when the WGM21:0 bits are set to a normal or CTC mode (non-PWM). Table 14-2. Compare Output Mode, non-PWM Mode COM2A1 COM2A0 Description 0 0 Normal port operation, OC2A disconnected. 0 1 Toggle OC2A on compare match. 1 0 Clear OC2A on compare match. 1 1 Set OC2A on compare match. Table 14-3 shows the COM2A1:0 bit functionality when the WGM21:0 bits are set to fast PWM mode. Table 14-3. Compare Output Mode, Fast PWM Mode(1) COM2A1 COM2A0 Description 0 0 Normal port operation, OC2A disconnected. 0 1 Reserved Clear OC2A on compare match. 1 0 Set OC2A at TOP. Set OC2A on compare match. 1 1 Clear OC2A at TOP. Note: 1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the com- pare match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode” on page 152 for more details. AT90CAN32/64/128 158 7679H–CAN–08/08

AT90CAN32/64/128 Table 14-4 shows the COM21:0 bit functionality when the WGM21:0 bits are set to phase cor- rect PWM mode. Table 14-4. Compare Output Mode, Phase Correct PWM Mode(1) COM2A1 COM2A0 Description 0 0 Normal port operation, OC2A disconnected. 0 1 Reserved Clear OC2A on compare match when up-counting. 1 0 Set OC2A on compare match when downcounting. Set OC2A on compare match when up-counting. 1 1 Clear OC2A on compare match when downcounting. Note: 1. A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the com- pare match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on page 153 for more details. • Bit 2:0 – CS22:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter, see Table 14-5. Table 14-5. Clock Select Bit Description CS22 CS21 CS20 Description 0 0 0 No clock source (Timer/Counter stopped). 0 0 1 clk /(No prescaling) T2S 0 1 0 clk /8 (From prescaler) T2S 0 1 1 clk /32 (From prescaler) T2S 1 0 0 clk /64 (From prescaler) T2S 1 0 1 clk /128 (From prescaler) T2S 1 1 0 clk /256 (From prescaler) T2S 1 1 1 clk /1024 (From prescaler) T2S 14.9.2 Timer/Counter2 Register – TCNT2 Bit 7 6 5 4 3 2 1 0 TCNT2[7:0] TCNT2 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT2 Register blocks (removes) the compare match on the following timer clock. Modifying the counter (TCNT2) while the counter is running, introduces a risk of missing a compare match between TCNT2 and the OCR2A Register. 14.9.3 Output Compare Register A – OCR2A Bit 7 6 5 4 3 2 1 0 OCR2A[7:0] OCR2A Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 159 7679H–CAN–08/08

The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value (TCNT2). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC2A pin. 14.10 Asynchronous operation of the Timer/Counter2 14.10.1 Asynchronous Status Register – ASSR Bit 7 6 5 4 3 2 1 0 – – – EXCLK AS2 TCN2UB OCR2UB TCR2UB ASSR Read/Write R R R R/W R/W R R R Initial Value 0 0 0 0 0 0 0 0 • Bit 7..5 – Reserved Bits These bits are reserved for future use. • Bit 4 – EXCLK: Enable External Clock Input When EXCLK is written to one, and asynchronous clock is selected, the external clock input buffer is enabled and an external clock can be input on Timer Oscillator 1 (TOSC1) pin instead of a 32 kHz crystal. Writing to EXCLK should be done before asynchronous operation is selected. Note that the crystal Oscillator will only run when this bit is zero. • Bit 3 – AS2: Asynchronous Timer/Counter2 When AS2 is written to zero, Timer/Counter2 is clocked from the I/O clock, clk and the crystal I/O Oscillator connected to the Timer/Counter2 Oscillator (TOSC) does nor run. When AS2 is written to one, Timer/Counter2 is clocked from a crystal Oscillator connected to the Timer/Counter2 Oscillator (TOSC) or from external clock on TOSC1 depending on EXCLK setting. When the value of AS2 is changed, the contents of TCNT2, OCR2A, and TCCR2A might be corrupted. • Bit 2 – TCN2UB: Timer/Counter2 Update Busy When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set. When TCNT2 has been updated from the temporary storage register, this bit is cleared by hard- ware. A logical zero in this bit indicates that TCNT2 is ready to be updated with a new value. • Bit 1 – OCR2UB: Output Compare Register2 Update Busy When Timer/Counter2 operates asynchronously and OCR2A is written, this bit becomes set. When OCR2A has been updated from the temporary storage register, this bit is cleared by hard- ware. A logical zero in this bit indicates that OCR2A is ready to be updated with a new value. • Bit 0 – TCR2UB: Timer/Counter Control Register2 Update Busy When Timer/Counter2 operates asynchronously and TCCR2A is written, this bit becomes set. When TCCR2A has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCCR2A is ready to be updated with a new value. If a write is performed to any of the three Timer/Counter2 Registers while its update busy flag is set, the updated value might get corrupted and cause an unintentional interrupt to occur. The mechanisms for reading TCNT2, OCR2A, and TCCR2A are different. When reading TCNT2, the actual timer value is read. When reading OCR2A or TCCR2A, the value in the tem- porary storage register is read. AT90CAN32/64/128 160 7679H–CAN–08/08

AT90CAN32/64/128 14.10.2 Asynchronous Operation of Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken. • Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the timer registers TCNT2, OCR2A, and TCCR2A might be corrupted. A safe procedure for switching clock source is: a. Disable the Timer/Counter2 interrupts by clearing OCIE2A and TOIE2. b. Select clock source by setting AS2 and EXCLK as appropriate. c. Write new values to TCNT2, OCR2A, and TCCR2A. d. To switch to asynchronous operation: Wait for TCN2UB, OCR2UB, and TCR2UB. e. Clear the Timer/Counter2 interrupt flags. f. Enable interrupts, if needed. • The Oscillator is optimized for use with a 32.768 kHz watch crystal. The CPU main clock frequency must be more than four times the Oscillator or external clock frequency. • When writing to one of the registers TCNT2, OCR2A, or TCCR2A, the value is transferred to a temporary register, and latched after two positive edges on TOSC1. The user should not write a new value before the contents of the temporary register have been transferred to its destination. Each of the three mentioned registers have their individual temporary register, which means that e.g. writing to TCNT2 does not disturb an OCR2A write in progress. To detect that a transfer to the destination register has taken place, the Asynchronous Status Register – ASSR has been implemented. • When entering Power-save or Extended Standby mode after having written to TCNT2, OCR2A, or TCCR2A, the user must wait until the written register has been updated if Timer/Counter2 is used to wake up the device. Otherwise, the MCU will enter sleep mode before the changes are effective. This is particularly important if the Output Compare2 interrupt is used to wake up the device, since the Output Compare function is disabled during writing to OCR2A or TCNT2. If the write cycle is not finished, and the MCU enters sleep mode before the OCR2UB bit returns to zero, the device will never receive a compare match interrupt, and the MCU will not wake up. • If Timer/Counter2 is used to wake the device up from Power-save or Extended Standby mode, precautions must be taken if the user wants to re-enter one of these modes: The interrupt logic needs one TOSC1 cycle to be reset. If the time between wake-up and re- entering sleep mode is less than one TOSC1 cycle, the interrupt will not occur, and the device will fail to wake up. If the user is in doubt whether the time before re-entering Power- save mode is sufficient, the following algorithm can be used to ensure that one TOSC1 cycle has elapsed: a. Write a value to TCCR2A, TCNT2, or OCR2A. b. Wait until the corresponding Update Busy flag in ASSR returns to zero. c. Enter Power-save or ADC Noise Reduction mode. • When the asynchronous operation is selected, the 32.768 kHz Oscillator for Timer/Counter2 is always running, except in Power-down and Standby modes. After a Power-up Reset or wake-up from Power-down or Standby mode, the user should be aware of the fact that this Oscillator might take as long as one second to stabilize. The user is advised to wait for at least one second before using Timer/Counter2 after power-up or wake-up from Power-down or Standby mode. The contents of all Timer/Counter2 Registers must be considered lost after a wake-up from Power-down or Standby mode due to unstable clock signal upon start-up, no matter whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin. 161 7679H–CAN–08/08

• Description of wake up from Power-save mode when the timer is clocked asynchronously: When the interrupt condition is met, the wake up process is started on the following cycle of the timer clock, that is, the timer is always advanced by at least one before the processor can read the counter value. After wake-up, the MCU is halted for four cycles, it executes the interrupt routine, and resumes execution from the instruction following SLEEP. • Reading of the TCNT2 Register shortly after wake-up from Power-save may give an incorrect result. Since TCNT2 is clocked on the asynchronous TOSC clock, reading TCNT2 must be done through a register synchronized to the internal I/O clock domain. Synchronization takes place for every rising TOSC1 edge. When waking up from Power-save mode, and the I/O clock (clk ) again becomes active, TCNT2 will read as the previous value (before entering I/O sleep) until the next rising TOSC1 edge. The phase of the TOSC clock after waking up from Power-save mode is essentially unpredictable, as it depends on the wake-up time. The recommended procedure for reading TCNT2 is thus as follows: a. Write any value to either of the registers OCR2A or TCCR2A. b. Wait for the corresponding Update Busy Flag to be cleared. c. Read TCNT2. • During asynchronous operation, the synchronization of the interrupt flags for the asynchronous timer takes 3processor cycles plus one timer cycle. The timer is therefore advanced by at least one before the processor can read the timer value causing the setting of the interrupt flag. The Output Compare pin is changed on the timer clock and is not synchronized to the processor clock. 14.10.3 Timer/Counter2 Interrupt Mask Register – TIMSK2 Bit 7 6 5 4 3 2 1 0 – – – – – – OCIE2A TOIE2 TIMSK2 Read/Write R R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 7..2 – Reserved Bits These bits are reserved for future use. • Bit 1 – OCIE2A: Timer/Counter2 Output Compare Match A Interrupt Enable When the OCIE2A bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match A interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter2 occurs, i.e., when the OCF2A bit is set in the Timer/Counter2 Interrupt Flag Register – TIFR2. • Bit 0 – TOIE2: Timer/Counter2 Overflow Interrupt Enable When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter2 occurs, i.e., when the TOV2 bit is set in the Timer/Counter2 Interrupt Flag Register – TIFR2. 14.10.4 Timer/Counter2 Interrupt Flag Register – TIFR2 Bit 7 6 5 4 3 2 1 0 – – – – – – OCF2A TOV2 TIFR2 Read/Write R R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 AT90CAN32/64/128 162 7679H–CAN–08/08

AT90CAN32/64/128 • Bit 7..2 – Reserved Bits These bits are reserved for future use. • Bit 1 – OCF2A: Output Compare Flag 2 A The OCF2A bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2A – Output Compare Register2. OCF2A is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF2A is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2 (Timer/Counter2 Compare match Interrupt Enable), and OCF2A are set (one), the Timer/Counter2 Compare match Interrupt is executed. • Bit 0 – TOV2: Timer/Counter2 Overflow Flag The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hard- ware when executing the corresponding interrupt handling vector. Alternatively, TOV2 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE2A (Timer/Counter2 Overflow Inter- rupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter2 changes counting direction at 0x00. 14.11 Timer/Counter2 Prescaler Figure 14-13. Prescaler for Timer/Counter2 AS2 EXCLK TOSC2 Enable clkI/O 0 clk 32 kHz(cid:31) 0 T2S 10-BIT T/C PRESCALER Oscillator Clear TOSC1 1 1 clk/8T2S clk/32T2S clk/64T2S clk/128T2S clk/256T2S clk/1024T2S EXCLK AS2 0 PSR2 CS20 CS21 CS22 TIMER/COUNTER2 CLOCK SOURCE clk T2 The clock source for Timer/Counter2 is named clk . clk is by default connected to the main T2S T2S system I/O clock clk . By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously IO clocked from the TOSC oscillator or TOSC1 pin. This enables use of Timer/Counter2 as a Real Time Counter (RTC). A crystal can then be connected between the TOSC1 and TOSC2 pins to serve as an indepen- dent clock source for Timer/Counter2. The Oscillator is optimized for use with a 32.768 kHz crystal. Setting AS2 and resetting EXCLK enables the TOSC oscillator. 163 7679H–CAN–08/08

Figure 14-14. Timer/Counter2 Crystal Oscillator Connections 12 - 22 pF TOSC2 32.768 KHz TOSC1 12 - 22 pF GND A external clock can also be used using TOSC1 as input. Setting AS2 and EXCLK enables this configuration. Figure 14-15. Timer/Counter2 External Clock Connections NC TOSC2 External Clock TOSC1 Signal For Timer/Counter2, the possible prescaled selections are: clk /8, clk /32, clk /64, T2S T2S T2S clk /128, clk /256, and clk /1024. Additionally, clk as well as 0 (stop) may be selected. T2S T2S T2S T2S Setting the PSR2 bit in GTCCR resets the prescaler. This allows the user to operate with a pre- dictable prescaler. 14.11.1 General Timer/Counter Control Register – GTCCR Bit 7 6 5 4 3 2 1 0 TSM – – – – – PSR2 PSR310 GTCCR Read/Write R/W R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 1 – PSR2: Prescaler Reset Timer/Counter2 When this bit is one, the Timer/Counter2 prescaler will be reset. This bit is normally cleared immediately by hardware. If the bit is written when Timer/Counter2 is operating in asynchronous mode, the bit will remain one until the prescaler has been reset. The bit will not be cleared by hardware if the TSM bit is set. Refer to the description of the “Bit 7 – TSM: Timer/Counter Syn- chronization Mode” on page 98 for a description of the Timer/Counter Synchronization mode. AT90CAN32/64/128 164 7679H–CAN–08/08

AT90CAN32/64/128 15. Output Compare Modulator - OCM 15.1 Overview Many register and bit references in this section are written in general form. • A lower case “n” replaces the Timer/Counter number, in this case 0 and 1. However, when using the register or bit defines in a program, the precise form must be used, i.e., TCNT0 for accessing Timer/Counter0 counter value and so on. • A lower case “x” replaces the Output Compare unit channel, in this case A or C. However, when using the register or bit defines in a program, the precise form must be used, i.e., OCR0A for accessing Timer/Counter0 output compare channel A value and so on. The Output Compare Modulator (OCM) allows generation of waveforms modulated with a carrier frequency. The modulator uses the outputs from the Output Compare Unit C of the 16-bit Timer/Counter1 and the Output Compare Unit of the 8-bit Timer/Counter0. For more details about these Timer/Counters see “16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3)” on page 113 and “8-bit Timer/Counter0 with PWM” on page 99. Figure 15-1. Output Compare Modulator, Block Diagram Timer/Counter 1 OC1C Pin OC0A / OC1C / PB7 Timer/Counter 0 OC0A When the modulator is enabled, the two output compare channels are modulated together as shown in the block diagram (Figure 15-1). 15.2 Description The Output Compare unit 1C and Output Compare unit 0A shares the PB7 port pin for output. The outputs of the Output Compare units (OC1C and OC0A) overrides the normal PORTB7 Register when one of them is enabled (i.e., when COMnx1:0 is not equal to zero). When both OC1C and OC0A are enabled at the same time, the modulator is automatically enabled. When the modulator is enabled the type of modulation (logical AND or OR) can be selected by the PORTB7 Register. Note that the DDRB7 controls the direction of the port independent of the COMnx1:0 bit setting. The functional equivalent schematic of the modulator is shown on Figure 15-2. The schematic includes part of the Timer/Counter units and the port B pin 7 output driver circuit. 165 7679H–CAN–08/08

Figure 15-2. Output Compare Modulator, Schematic COM0A1 Vcc COM0A0 COM1C1 Modulator COM1C0 0 1 (From T/C1 D Q Waveform Generator) 1 OC1C Pin 0 (From T/C0 D Q OC0A / OC1C / PB7 Waveform Generator) OC0A D Q D Q PORTB7 DDRB7 DATABUS 15.2.1 Timing Example Figure 15-3 illustrates the modulator in action. In this example the Timer/Counter1 is set to oper- ate in fast PWM mode (non-inverted) and Timer/Counter0 uses CTC waveform mode with toggle Compare Output mode (COMnx1:0 = 1). Figure 15-3. Output Compare Modulator, Timing Diagram clk I/O OC1C (FPWM Mode) OC0A (CTC Mode) PB7 (PORTB7 = 0) PB7 (PORTB7 = 1) 1 2 3 (Period) In this example, Timer/Counter0 provides the carrier, while the modulating signal is generated by the Output Compare unit C of the Timer/Counter1. AT90CAN32/64/128 166 7679H–CAN–08/08

AT90CAN32/64/128 15.2.2 Resolution of the PWM Signal The resolution of the PWM signal (OC1C) is reduced by the modulation. The reduction factor is equal to the number of system clock cycles of one period of the carrier (OC0A). In this example the resolution is reduced by a factor of two. The reason for the reduction is illustrated in Figure 15-3 at the second and third period of the PB7 output when PORTB7 equals zero. The period 2 high time is one cycle longer than the period 3 high time, but the result on the PB7 output is equal in both periods. 167 7679H–CAN–08/08

16. Serial Peripheral Interface – SPI The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the AT90CAN32/64/128 and peripheral devices or between several AVR devices. The AT90CAN32/64/128 SPI includes the following features: 16.1 Features • Full-duplex, Three-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Seven Programmable Bit Rates • End of Transmission Interrupt Flag • Write Collision Flag Protection • Wake-up from Idle Mode • Double Speed (CK/2) Master SPI Mode Figure 16-1. SPI Block Diagram(1) clk IO DIVIDER /2/4/8/16/32/64/128 X 2 PI S X 2 PI S Note: 1. Refer to Figure 1-2 on page 5 or Figure 1-3 on page 6, and Table 9-6 on page 76 for SPI pin placement. AT90CAN32/64/128 168 7679H–CAN–08/08

AT90CAN32/64/128 The interconnection between Master and Slave CPUs with SPI is shown in Figure 16-2. The sys- tem consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave. Master and Slave prepare the data to be sent in their respective shift Registers, and the Master generates the required clock pulses on the SCK line to interchange data. Data is always shifted from Mas- ter to Slave on the Master Out – Slave In, MOSI, line, and from Slave to Master on the Master In – Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave by pulling high the Slave Select, SS, line. When configured as a Master, the SPI interface has no automatic control of the SS line. This must be handled by user software before communication can start. When this is done, writing a byte to the SPI Data Register starts the SPI clock generator, and the hardware shifts the eight bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the end of transmission flag (SPIF). If the SPI Interrupt Enable bit (SPIE) in the SPCR Register is set, an interrupt is requested. The Master may continue to shift the next byte by writing it into SPDR, or signal the end of packet by pulling high the Slave Select, SS line. The last incoming byte will be kept in the Buffer Register for later use. When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated as long as the SS pin is driven high. In this state, software may update the contents of the SPI Data Register, SPDR, but the data will not be shifted out by incoming clock pulses on the SCK pin until the SS pin is driven low. As one byte has been completely shifted, the end of transmission flag, SPIF is set. If the SPI Interrupt Enable bit, SPIE, in the SPCR Register is set, an interrupt is requested. The Slave may continue to place new data to be sent into SPDR before reading the incoming data. The last incoming byte will be kept in the Buffer Register for later use. Figure 16-2. SPI Master-slave Interconnection SHIFT ENABLE The system is single buffered in the transmit direction and double buffered in the receive direc- tion. This means that bytes to be transmitted cannot be written to the SPI Data Register before the entire shift cycle is completed. When receiving data, however, a received character must be read from the SPI Data Register before the next character has been completely shifted in. Oth- erwise, the first byte is lost. In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling of the clock signal, the minimum low and high period should be: – Low period: Longer than 2 CPU clock cycles, – High period: Longer than 2 CPU clock cycles. 169 7679H–CAN–08/08

When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Table 16-1. For more details on automatic port overrides, refer to “Alternate Port Functions” on page 71. Table 16-1. SPI Pin Overrides(1) Pin Direction, Master SPI Direction, Slave SPI MOSI User Defined Input MISO Input User Defined SCK User Defined Input SS User Defined Input Note: 1. See “Alternate Functions of Port B” on page 76 for a detailed description of how to define the direction of the user defined SPI pins. AT90CAN32/64/128 170 7679H–CAN–08/08

AT90CAN32/64/128 The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. E.g. if MOSI is placed on pin PB2, replace DD_MOSI with DDB2 and DDR_SPI with DDRB. Assembly Code Example(1) SPI_MasterInit: ; Set MOSI and SCK output, all others input ldi r17,(1<<DD_MOSI)|(1<<DD_SCK) out DDR_SPI,r17 ; Enable SPI, Master, set clock rate fck/16 ldi r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0) out SPCR,r17 ret SPI_MasterTransmit: ; Start transmission of data (r16) out SPDR,r16 Wait_Transmit: ; Wait for transmission complete in r17,SPSR sbrs r17,SPIF rjmp Wait_Transmit ret C Code Example(1) void SPI_MasterInit(void) { /* Set MOSI and SCK output, all others input */ DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK); /* Enable SPI, Master, set clock rate fck/16 */ SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0); } void SPI_MasterTransmit(char cData) { /* Start transmission */ SPDR = cData; /* Wait for transmission complete */ while(!(SPSR & (1<<SPIF))); } Note: 1. The example code assumes that the part specific header file is included. 171 7679H–CAN–08/08

The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception. Assembly Code Example(1) SPI_SlaveInit: ; Set MISO output, all others input ldi r17,(1<<DD_MISO) out DDR_SPI,r17 ; Enable SPI ldi r17,(1<<SPE) out SPCR,r17 ret SPI_SlaveReceive: ; Wait for reception complete sbis SPSR,SPIF rjmp SPI_SlaveReceive ; Read received data and return in r16,SPDR ret C Code Example(1) void SPI_SlaveInit(void) { /* Set MISO output, all others input */ DDR_SPI = (1<<DD_MISO); /* Enable SPI */ SPCR = (1<<SPE); } char SPI_SlaveReceive(void) { /* Wait for reception complete */ while(!(SPSR & (1<<SPIF))); /* Return data register */ return SPDR; } Note: 1. The example code assumes that the part specific header file is included. 16.2 SS Pin Functionality 16.2.1 Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the user. All other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which AT90CAN32/64/128 172 7679H–CAN–08/08

AT90CAN32/64/128 means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin is driven high. The SS pin is useful for packet/byte synchronization to keep the slave bit counter synchronous with the master clock generator. When the SS pin is driven high, the SPI slave will immediately reset the send and receive logic, and drop any partially received data in the Shift Register. 16.2.2 Master Mode When the SPI is configured as a Master (MSTR in SPCR is set), the user can determine the direction of the SS pin. If SS is configured as an output, the pin is a general output pin which does not affect the SPI system. Typically, the pin will be driving the SS pin of the SPI Slave. If SS is configured as an input, it must be held high to ensure Master SPI operation. If the SS pin is driven low by peripheral circuitry when the SPI is configured as a Master with the SS pin defined as an input, the SPI system interprets this as another master selecting the SPI as a slave and starting to send data to it. To avoid bus contention, the SPI system takes the following actions: 1. The MSTR bit in SPCR is cleared and the SPI system becomes a Slave. As a result of the SPI becoming a Slave, the MOSI and SCK pins become inputs. 2. The SPIF flag in SPSR is set, and if the SPI interrupt is enabled, and the I-bit in SREG is set, the interrupt routine will be executed. Thus, when interrupt-driven SPI transmission is used in Master mode, and there exists a possi- bility that SS is driven low, the interrupt should always check that the MSTR bit is still set. If the MSTR bit has been cleared by a slave select, it must be set by the user to re-enable SPI Master mode. 16.2.3 SPI Control Register – SPCR Bit 7 6 5 4 3 2 1 0 SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 SPCR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 7 – SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if the Global Interrupt Enable bit in SREG is set. • Bit 6 – SPE: SPI Enable When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI operations. • Bit 5 – DORD: Data Order When the DORD bit is written to one, the LSB of the data word is transmitted first. When the DORD bit is written to zero, the MSB of the data word is transmitted first. • Bit 4 – MSTR: Master/Slave Select This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, 173 7679H–CAN–08/08

and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Mas- ter mode. • Bit 3 – CPOL: Clock Polarity When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low when idle. Refer to Figure 16-3 and Figure 16-4 for an example. The CPOL functionality is sum- marized below: Table 16-2. CPOL Functionality CPOL Leading Edge Trailing Edge 0 Rising Falling 1 Falling Rising • Bit 2 – CPHA: Clock Phase The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or trailing (last) edge of SCK. Refer to Figure 16-3 and Figure 16-4 for an example. The CPOL functionality is summarized below: Table 16-3. CPHA Functionality CPHA Leading Edge Trailing Edge 0 Sample Setup 1 Setup Sample • Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between SCK and the clk frequency f is shown in IO clkio the following table: Table 16-4. Relationship Between SCK and the Oscillator Frequency SPI2X SPR1 SPR0 SCK Frequency 0 0 0 f /4 clkio 0 0 1 f /16 clkio 0 1 0 f /64 clkio 0 1 1 f /128 clkio 1 0 0 f /2 clkio 1 0 1 f /8 clkio 1 1 0 f /32 clkio 1 1 1 f /64 clkio AT90CAN32/64/128 174 7679H–CAN–08/08

AT90CAN32/64/128 16.2.4 SPI Status Register – SPSR Bit 7 6 5 4 3 2 1 0 SPIF WCOL – – – – – SPI2X SPSR Read/Write R R R R R R R R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 7 – SPIF: SPI Interrupt Flag When a serial transfer is complete, the SPIF flag is set. An interrupt is generated if SPIE in SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI is in Master mode, this will also set the SPIF flag. SPIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the SPI Status Register with SPIF set, then accessing the SPI Data Register (SPDR). • Bit 6 – WCOL: Write COLlision Flag The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL set, and then accessing the SPI Data Register. • Bit 5..1 – Res: Reserved Bits These bits are reserved bits in the AT90CAN32/64/128 and will always read as zero. • Bit 0 – SPI2X: Double SPI Speed Bit When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see Table 16-4). This means that the minimum SCK period will be two CPU clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at f /4 clkio or lower. The SPI interface on the AT90CAN32/64/128 is also used for program memory and EEPROM downloading or uploading. See “SPI Serial Programming Overview” on page 348 for serial pro- gramming and verification. 16.2.5 SPI Data Register – SPDR Bit 7 6 5 4 3 2 1 0 SPD7 SPD6 SPD5 SPD4 SPD3 SPD2 SPD1 SPD0 SPDR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value X X X X X X X X Undefined • Bits 7:0 - SPD7:0: SPI Data The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. Reading the regis- ter causes the Shift Register Receive buffer to be read. 16.3 Data Modes There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure 16-3 and Figure 16-4. Data bits are shifted out and latched in on opposite edges of the SCK sig- 175 7679H–CAN–08/08

nal, ensuring sufficient time for data signals to stabilize. This is clearly seen by summarizing Table 16-2 and Table 16-3, as done below: Table 16-5. CPOL Functionality Leading Edge Trailing Edge SPI Mode CPOL=0, CPHA=0 Sample (Rising) Setup (Falling) 0 CPOL=0, CPHA=1 Setup (Rising) Sample (Falling) 1 CPOL=1, CPHA=0 Sample (Falling) Setup (Rising) 2 CPOL=1, CPHA=1 Setup (Falling) Sample (Rising) 3 Figure 16-3. SPI Transfer Format with CPHA = 0 SCK (CPOL = 0) mode 0 SCK (CPOL = 1) mode 2 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB LSB first (DORD = 1) LSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Figure 16-4. SPI Transfer Format with CPHA = 1 SCK (CPOL = 0) mode 1 SCK (CPOL = 1) mode 3 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB LSB first (DORD = 1) LSB Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB AT90CAN32/64/128 176 7679H–CAN–08/08

AT90CAN32/64/128 17. USART (USART0 and USART1) The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication device. The main features are: 17.1 Features • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • High Resolution Baud Rate Generator • Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits • Odd or Even Parity Generation and Parity Check Supported by Hardware • Data OverRun Detection • Framing Error Detection • Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter • Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete • Multi-processor Communication Mode • Double Speed Asynchronous Communication Mode 17.2 Overview Many registers and bit references in this section are written in general form. • A lower case “n” replaces the USART number, in this case 0 or 1. However, when using the register or bit defines in a program, the precise form must be used, i.e., UDR0 for accessing USART0 I/O data value and so on. 17.3 Dual USART The AT90CAN32/64/128 has two USART’s, USART0 and USART1. The functionality for both USART’s is described below. USART0 and USART1 have different I/O registers as shown in “Register Summary” on page 405. A simplified block diagram of the USARTn Transmitter is shown in Figure 17-1. CPU accessible I/O Registers and I/O pins are shown in bold. 177 7679H–CAN–08/08

Figure 17-1. USARTn Block Diagram (1) Clock Generator UBRRn[H:L] CLKio BAUD RATE GENERATOR SYNC LOGIC PIN XCKn CONTROL Transmitter TX UDRn (Transmit) CONTROL PARITY S GENERATOR U PIN B TRANSMIT SHIFT REGISTER CONTROL TxDn A T A D Receiver CLOCK RX RECOVERY CONTROL DATA PIN RECEIVE SHIFT REGISTER RxDn RECOVERY CONTROL PARITY UDRn (Receive) CHECKER UCSRAn UCSRBn UCSRCn Note: 1. Refer to Figure 1-2 on page 5 or Figure 1-3 on page 6, Table 9-15 on page 83, and Table 9-10 on page 79 for USARTn pin placement. The dashed boxes in the block diagram separate the three main parts of the USARTn (listed from the top): Clock Generator, Transmitter and Receiver. Control registers are shared by all units. The Clock Generation logic consists of synchronization logic for external clock input used by synchronous slave operation, and the baud rate generator. The XCKn (Transfer Clock) pin is only used by synchronous transfer mode. The Transmitter consists of a single write buffer, a serial Shift Register, Parity Generator and Control logic for handling different serial frame for- mats. The write buffer allows a continuous transfer of data without any delay between frames. The Receiver is the most complex part of the USARTn module due to its clock and data recovery units. The recovery units are used for asynchronous data reception. In addition to the recovery units, the Receiver includes a Parity Checker, Control logic, a Shift Register and a two level receive buffer (UDRn). The Receiver supports the same frame formats as the Transmitter, and can detect Frame Error, Data OverRun and Parity Errors. AT90CAN32/64/128 178 7679H–CAN–08/08

AT90CAN32/64/128 17.4 Clock Generation The Clock Generation logic generates the base clock for the Transmitter and Receiver. The USARTn supports four modes of clock operation: Normal asynchronous, Double Speed asyn- chronous, Master synchronous and Slave synchronous mode. The UMSELn bit in USARTn Control and Status Register C (UCSRnC) selects between asynchronous and synchronous operation. Double Speed (asynchronous mode only) is controlled by the U2Xn found in the UCSRnA Register. When using synchronous mode (UMSELn = 1), the Data Direction Register for the XCKn pin (DDR_XCKn) controls whether the clock source is internal (Master mode) or external (Slave mode). The XCKn pin is only active when using synchronous mode. Figure 17-2 shows a block diagram of the clock generation logic. Figure 17-2. USARTn Clock Generation Logic, Block Diagram UBRRn U2Xn fclkio Prescaling UBRRn+1 /2 /4 /2 Down-Counter 0 1 0 clkio 1 txn clk DDR_XCKn Sync Edge xn cki Register Detector 0 XCKn UMSELn Pin xn cko 1 DDR_XCKn UCPOLn 1 rxn clk 0 Signal description: txn clk Transmitter clock (Internal Signal). rxn clk Receiver base clock (Internal Signal). xn cki Input from XCK pin (internal Signal). Used for synchronous slave operation. xn cko Clock output to XCK pin (Internal Signal). Used for synchronous master operation. fclk System I/O Clock frequency. io 17.4.1 Internal Clock Generation – Baud Rate Generator Internal clock generation is used for the asynchronous and the synchronous master modes of operation. The description in this section refers to Figure 17-2. The USARTn Baud Rate Register (UBRRn) and the down-counter connected to it function as a programmable prescaler or baud rate generator. The down-counter, running at system clock (fclk ), is loaded with the UBRRn value each time the counter has counted down to zero or io when the UBRRnL Register is written. A clock is generated each time the counter reaches zero. This clock is the baud rate generator clock output (= fclk /(UBRRn+1)). The Transmitter divides io the baud rate generator clock output by 2, 8 or 16 depending on mode. The baud rate generator output is used directly by the Receiver’s clock and data recovery units. However, the recovery 179 7679H–CAN–08/08

units use a state machine that uses 2, 8 or 16 states depending on mode set by the state of the UMSELn, U2Xn and DDR_XCKn bits. Table 17-1 contains equations for calculating the baud rate (in bits per second) and for calculat- ing the UBRRn value for each mode of operation using an internally generated clock source. Table 17-1. Equations for Calculating Baud Rate Register Setting Equation for Calculating Baud Equation for Calculating Operating Mode Rate (1) UBRRn Value A(Us2yXncnh =ro 0n)ous Normal mode BAUD = 1----6----(--U----f-BC----RL---K-R---i-o-n----+-----1----)- UBRRn = 1----6f--C-B---L--A-K---U-i-o--D----–1 f f Asynchronous Double Speed CLKio CLKio BAUD = --------------------------------------- UBRRn = --------------------–1 mode (U2Xn = 1) 8(UBRRn+1) 8BAUD f f CLKio CLKio BAUD = --------------------------------------- UBRRn = --------------------–1 Synchronous Master mode 2(UBRRn+1) 2BAUD Note: 1. The baud rate is defined to be the transfer rate in bit per second (bps) BAUD Baud rate (in bits per second, bps). fclk System I/O Clock frequency. io UBRRn Contents of the UBRRnH and UBRRnL Registers, (0-4095). Some examples of UBRRn values for some system clock frequencies are found in Table 17-9 (see page 200). 17.4.2 Double Speed Operation (U2X) The transfer rate can be doubled by setting the U2Xn bit in UCSRnA. Setting this bit only has effect for the asynchronous operation. Set this bit to zero when using synchronous operation. Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively doubling the transfer rate for asynchronous communication. Note however that the Receiver will in this case only use half the number of samples (reduced from 16 to 8) for data sampling and clock recovery, and therefore a more accurate baud rate setting and system clock are required when this mode is used. For the Transmitter, there are no downsides. 17.4.3 External Clock External clocking is used by the synchronous slave modes of operation. The description in this section refers to Figure 17-2 for details. External clock input from the XCKn pin is sampled by a synchronization register to minimize the chance of meta-stability. The output from the synchronization register must then pass through an edge detector before it can be used by the Transmitter and Receiver. This process intro- duces a two CPU clock period delay and therefore the maximum external XCKn clock frequency is limited by the following equation: f CLKio f <---------------- XCKn 4 AT90CAN32/64/128 180 7679H–CAN–08/08

AT90CAN32/64/128 Note that fclk depends on the stability of the system clock source. It is therefore recommended io to add some margin to avoid possible loss of data due to frequency variations. 17.4.4 Synchronous Clock Operation When synchronous mode is used (UMSELn = 1), the XCKn pin will be used as either clock input (Slave) or clock output (Master). The dependency between the clock edges and data sampling or data change is the same. The basic principle is that data input (on RxDn) is sampled at the opposite XCKn clock edge of the edge the data output (TxDn) is changed. Figure 17-3. Synchronous Mode XCKn Timing. UCPOLn = 1 XCKn RxDn / TxDn Sample UCPOLn = 0 XCKn RxDn / TxDn Sample The UCPOLn bit UCRSnC selects which XCKn clock edge is used for data sampling and which is used for data change. As Figure 17-3 shows, when UCPOLn is zero the data will be changed at rising XCKn edge and sampled at falling XCKn edge. If UCPOLn is set, the data will be changed at falling XCKn edge and sampled at rising XCKn edge. 17.5 Serial Frame A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit for error checking. 17.5.1 Frame Formats The USARTn accepts all 30 combinations of the following as valid frame formats: • 1 start bit • 5, 6, 7, 8, or 9 data bits • no, even or odd parity bit • 1 or 2 stop bits A frame starts with the start bit followed by the least significant data bit. Then the next data bits, up to a total of nine, are succeeding, ending with the most significant bit. If enabled, the parity bit is inserted after the data bits, before the stop bits. When a complete frame is transmitted, it can be directly followed by a new frame, or the communication line can be set to an idle (high) state. Figure 17-4 illustrates the possible combinations of the frame formats. Bits inside brackets are optional. 181 7679H–CAN–08/08

Figure 17-4. Frame Formats FRAME (IDLE) St 0 1 2 3 4 [5] [6] [7] [8] [P] Sp1 [Sp2] (St / IDLE) St Start bit, always low. (n) Data bits (0 to 8). P Parity bit. Can be odd or even. Sp Stop bit, always high. IDLE No transfers on the communication line (RxDn or TxDn). An IDLE line must be high. The frame format used by the USARTn is set by the UCSZn2:0, UPMn1:0 and USBSn bits in UCSRnB and UCSRnC. The Receiver and Transmitter use the same setting. Note that changing the setting of any of these bits will corrupt all ongoing communication for both the Receiver and Transmitter. The USARTn Character SiZe (UCSZn2:0) bits select the number of data bits in the frame. The USARTn Parity mode (UPMn1:0) bits enable and set the type of parity bit. The selection between one or two stop bits is done by the USARTn Stop Bit Select (USBSn) bit. The Receiver ignores the second stop bit. An FEn (Frame Error) will therefore only be detected in the cases where the first stop bit is zero. 17.5.2 Parity Bit Calculation The parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is used, the result of the exclusive or is inverted. The relation between the parity bit and data bits is as follows: P = d ⊕…⊕d ⊕d ⊕d ⊕d ⊕0 even n–1 3 2 1 0 P = d ⊕…⊕d ⊕d ⊕d ⊕d ⊕1 odd n–1 3 2 1 0 P Parity bit using even parity even Podd Parity bit using odd parity d Data bit n of the character n If used, the parity bit is located between the last data bit and first stop bit of a serial frame. 17.6 USART Initialization The USARTn has to be initialized before any communication can take place. The initialization process normally consists of setting the baud rate, setting frame format and enabling the Trans- mitter or the Receiver depending on the usage. For interrupt driven USARTn operation, the Global Interrupt Flag should be cleared (and interrupts globally disabled) when doing the initialization. Before doing a re-initialization with changed baud rate or frame format, be sure that there are no ongoing transmissions during the period the registers are changed. The TXCn flag can be used to check that the Transmitter has completed all transfers, and the RXCn flag can be used to AT90CAN32/64/128 182 7679H–CAN–08/08

AT90CAN32/64/128 check that there are no unread data in the receive buffer. Note that the TXCn flag must be cleared before each transmission (before UDRn is written) if it is used for this purpose. The following simple USART0 initialization code examples show one assembly and one C func- tion that are equal in functionality. The examples assume asynchronous operation using polling (no interrupts enabled) and a fixed frame format. The baud rate is given as a function parameter. For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 Registers. Assembly Code Example (1) USART0_Init: ; Set baud rate sts UBRR0H, r17 sts UBRR0L, r16 ; Set frame format: 8data, no parity & 2 stop bits ldi r16, (0<<UMSEL0)|(0<<UPM0)|(1<<USBS0)|(3<<UCSZ0) sts UCSR0C, r16 ; Enable receiver and transmitter ldi r16, (1<<RXEN0)|(1<<TXEN0) sts UCSR0B, r16 ret C Code Example (1) void USART0_Init (unsigned int baud) { /* Set baud rate */ UBRR0H = (unsigned char) (baud>>8); UBRR0L = (unsigned char) baud; /* Set frame format: 8data, no parity & 2 stop bits */ UCSR0C = (0<<UMSEL0) | (0<<UPM0) | (1<<USBS0) | (3<<UCSZ0); /* Enable receiver and transmitter */ UCSR0B = (1<<RXEN0) | (1<<TXEN0); } Note: 1. The example code assumes that the part specific header file is included. More advanced initialization routines can be made that include frame format as parameters, dis- able interrupts and so on. However, many applications use a fixed setting of the baud and control registers, and for these types of applications the initialization code can be placed directly in the main routine, or be combined with initialization code for other I/O modules. 17.7 Data Transmission – USART Transmitter The USARTn Transmitter is enabled by setting the Transmit Enable (TXENn) bit in the UCSRnB Register. When the Transmitter is enabled, the normal port operation of the TxDn pin is overrid- den by the USARTn and given the function as the Transmitter’s serial output. The baud rate, mode of operation and frame format must be set up once before doing any transmissions. If syn- 183 7679H–CAN–08/08

chronous operation is used, the clock on the XCKn pin will be overridden and used as transmission clock. 17.7.1 Sending Frames with 5 to 8 Data Bit A data transmission is initiated by loading the transmit buffer with the data to be transmitted. The CPU can load the transmit buffer by writing to the UDRn I/O location. The buffered data in the transmit buffer will be moved to the Shift Register when the Shift Register is ready to send a new frame. The Shift Register is loaded with new data if it is in idle state (no ongoing transmission) or immediately after the last stop bit of the previous frame is transmitted. When the Shift Register is loaded with new data, it will transfer one complete frame at the rate given by the Baud Register, U2Xn bit or by XCKn depending on mode of operation. The following code examples show a simple USART0 transmit function based on polling of the Data Register Empty (UDRE0) flag. When using frames with less than eight bits, the most signif- icant bits written to the UDR0 are ignored. The USART0 has to be initialized before the function can be used. For the assembly code, the data to be sent is assumed to be stored in Register R16. Assembly Code Example (1) USART0_Transmit: ; Wait for empty transmit buffer lds r17, UCSR0A sbrs r17, UDRE0 rjmp USART0_Transmit ; Put data (r16) into buffer, sends the data sts UDR0, r16 ret C Code Example (1) void USART0_Transmit (unsigned char data) { /* Wait for empty transmit buffer */ while ( ! ( UCSRA0 & (1<<UDRE0))); /* Put data into buffer, sends the data */ UDR0 = data; } Note: 1. The example code assumes that the part specific header file is included. The function simply waits for the transmit buffer to be empty by checking the UDRE0 flag, before loading it with new data to be transmitted. If the Data Register Empty interrupt is utilized, the interrupt routine writes the data into the buffer. AT90CAN32/64/128 184 7679H–CAN–08/08

AT90CAN32/64/128 17.7.2 Sending Frames with 9 Data Bit If 9-bit characters are used (UCSZn = 7), the ninth bit must be written to the TXB8n bit in UCS- RnB before the low byte of the character is written to UDRn. The following code examples show a transmit function that handles 9-bit characters. For the assembly code, the data to be sent is assumed to be stored in registers R17:R16. Assembly Code Example (1)(2) USART0_Transmit: ; Wait for empty transmit buffer lds r18, UCSR0A sbrs r18, UDRE0 rjmp USART0_Transmit ; Copy 9th bit from r17-bit0 to TXB80 via T-bit of SREG lds r18, UCSR0B bst r17, 0 bld r18, TXB80 sts UCSR0B, r18 ; Put LSB data (r16) into buffer, sends the data sts UDR0, r16 ret C Code Example (1)(2) void USART0_Transmit (unsigned int data) { /* Wait for empty transmit buffer */ while ( !( UCSR0A & (1<<UDRE0))); /* Copy 9th bit to TXB8 */ UCSR0B &= ~(1<<TXB80); if ( data & 0x0100 ) UCSR0B |= (1<<TXB80); /* Put data into buffer, sends the data */ UDR0 = data; } Notes: 1. These transmit functions are written to be general functions. They can be optimized if the con- tents of the UCSR0B is static. For example, only the TXB80 bit of the UCSRB0 Register is used after initialization. 2. The example code assumes that the part specific header file is included. The ninth bit can be used for indicating an address frame when using multi processor communi- cation mode or for other protocol handling as for example synchronization. 17.7.3 Transmitter Flags and Interrupts The USARTn Transmitter has two flags that indicate its state: USART Data Register Empty (UDREn) and Transmit Complete (TXCn). Both flags can be used for generating interrupts. 185 7679H–CAN–08/08

The Data Register Empty (UDREn) flag indicates whether the transmit buffer is ready to receive new data. This bit is set when the transmit buffer is empty, and cleared when the transmit buffer contains data to be transmitted that has not yet been moved into the Shift Register. For compat- ibility with future devices, always write this bit to zero when writing the UCSRnA Register. When the Data Register Empty Interrupt Enable (UDRIEn) bit in UCSRBn is written to one, the USARTn Data Register Empty Interrupt will be executed as long as UDREn is set (provided that global interrupts are enabled). UDREn is cleared by writing UDRn. When interrupt-driven data transmission is used, the Data Register Empty interrupt routine must either write new data to UDRn in order to clear UDREn or disable the Data Register Empty interrupt, otherwise a new interrupt will occur once the interrupt routine terminates. The Transmit Complete (TXCn) flag bit is set one when the entire frame in the Transmit Shift Register has been shifted out and there are no new data currently present in the transmit buffer. The TXCn flag bit is automatically cleared when a transmit complete interrupt is executed, or it can be cleared by writing a one to its bit location. The TXCn flag is useful in half-duplex commu- nication interfaces (like the RS-485 standard), where a transmitting application must enter receive mode and free the communication bus immediately after completing the transmission. When the Transmit Complete Interrupt Enable (TXCIEn) bit in UCSRnB is set, the USARTn Transmit Complete Interrupt will be executed when the TXCn flag becomes set (provided that global interrupts are enabled). When the transmit complete interrupt is used, the interrupt han- dling routine does not have to clear the TXCn flag, this is done automatically when the interrupt is executed. 17.7.4 Parity Generator The Parity Generator calculates the parity bit for the serial frame data. When parity bit is enabled (UPMn1 = 1), the transmitter control logic inserts the parity bit between the last data bit and the first stop bit of the frame that is sent. 17.7.5 Disabling the Transmitter The disabling of the Transmitter (setting the TXENn to zero) will not become effective until ongo- ing and pending transmissions are completed, i.e., when the Transmit Shift Register and Transmit Buffer Register do not contain data to be transmitted. When disabled, the Transmitter will no longer override the TxDn pin. 17.8 Data Reception – USART Receiver The USARTn Receiver is enabled by writing the Receive Enable (RXENn) bit in the UCSRnB Register to one. When the Receiver is enabled, the normal pin operation of the RxDn pin is over- ridden by the USARTn and given the function as the Receiver’s serial input. The baud rate, mode of operation and frame format must be set up once before any serial reception can be done. If synchronous operation is used, the clock on the XCKn pin will be used as transfer clock. 17.8.1 Receiving Frames with 5 to 8 Data Bits The Receiver starts data reception when it detects a valid start bit. Each bit that follows the start bit will be sampled at the baud rate or XCKn clock, and shifted into the Receive Shift Register until the first stop bit of a frame is received. A second stop bit will be ignored by the Receiver. When the first stop bit is received, i.e., a complete serial frame is present in the Receive Shift Register, the contents of the Shift Register will be moved into the receive buffer. The receive buffer can then be read by reading the UDRn I/O location. AT90CAN32/64/128 186 7679H–CAN–08/08

AT90CAN32/64/128 The following code example shows a simple USART0 receive function based on polling of the Receive Complete (RXC0) flag. When using frames with less than eight bits the most significant bits of the data read from the UDR0 will be masked to zero. The USART0 has to be initialized before the function can be used. Assembly Code Example (1) USART0_Receive: ; Wait for data to be received lds r18, UCSR0A sbrs r18, RXC0 rjmp USART0_Receive ; Get and return received data from buffer lds r16, UDR0 ret C Code Example (1) unsigned char USART0_Receive (void) { /* Wait for data to be received */ while ( ! (UCSR0A & (1<<RXC0))); /* Get and return received data from buffer */ return UDR0; } Note: 1. The example code assumes that the part specific header file is included. The function simply waits for data to be present in the receive buffer by checking the RXC0 flag, before reading the buffer and returning the value. 17.8.2 Receiving Frames with 9 Data Bits If 9-bit characters are used (UCSZn=7) the ninth bit must be read from the RXB8n bit in UCS- RnB before reading the low bits from the UDRn. This rule applies to the FEn, DORn and UPEn Status Flags as well. Read status from UCSRnA, then data from UDRn. Reading the UDRn I/O location will change the state of the receive buffer FIFO and consequently the TXB8n, FEn, DORn and UPEn bits, which all are stored in the FIFO, will change. 187 7679H–CAN–08/08

The following code example shows a simple USART0 receive function that handles both nine bit characters and the status bits. Assembly Code Example (1) USART0_Receive: ; Wait for data to be received lds r18, UCSR0A sbrs r18, RXC0 rjmp USART0_Receive ; Get status and 9th bit, then data from buffer lds r17, UCSR0B lds r16, UDR0 ; If error, return -1 andi r18, (1<<FE0) | (1<<DOR0) | (1<<UPE0) breq USART0_ReceiveNoError ldi r17, HIGH(-1) ldi r16, LOW(-1) USART0_ReceiveNoError: ; Filter the 9th bit, then return lsr r17 andi r17, 0x01 ret C Code Example (1) unsigned int USART0_Receive(void) { unsigned char status, resh, resl; /* Wait for data to be received */ while ( ! (UCSR0A & (1<<RXC0))); /* Get status and 9th bit, then data */ /* from buffer */ status = UCSR0A; resh = UCSR0B; resl = UDR0; /* If error, return -1 */ if ( status & (1<<FE0)|(1<<DOR0)|(1<<UPE0) ) return -1; /* Filter the 9th bit, then return */ resh = (resh >> 1) & 0x01; return ((resh << 8) | resl); } Note: 1. The example code assumes that the part specific header file is included. The receive function example reads all the I/O Registers into the Register File before any com- putation is done. This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as early as possible. AT90CAN32/64/128 188 7679H–CAN–08/08

AT90CAN32/64/128 17.8.3 Receive Complete Flag and Interrupt The USARTn Receiver has one flag that indicates the Receiver state. The Receive Complete (RXCn) flag indicates if there are unread data present in the receive buffer. This flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled (RXENn = 0), the receive buffer will be flushed and consequently the RXCn bit will become zero. When the Receive Complete Interrupt Enable (RXCIEn) in UCSRnB is set, the USARTn Receive Complete interrupt will be executed as long as the RXCn flag is set (provided that glo- bal interrupts are enabled). When interrupt-driven data reception is used, the receive complete routine must read the received data from UDRn in order to clear the RXCn flag, otherwise a new interrupt will occur once the interrupt routine terminates. 17.8.4 Receiver Error Flags The USARTn Receiver has three error flags: Frame Error (FEn), Data OverRun (DORn) and Parity Error (UPEn). All can be accessed by reading UCSRnA. Common for the error flags is that they are located in the receive buffer together with the frame for which they indicate the error status. Due to the buffering of the error flags, the UCSRnA must be read before the receive buffer (UDRn), since reading the UDRn I/O location changes the buffer read location. Another equality for the error flags is that they can not be altered by software doing a write to the flag location. However, all flags must be set to zero when the UCSRnA is written for upward compat- ibility of future USART implementations. None of the error flags can generate interrupts. The Frame Error (FEn) flag indicates the state of the first stop bit of the next readable frame stored in the receive buffer. The FEn flag is zero when the stop bit was correctly read (as one), and the FEn flag will be one when the stop bit was incorrect (zero). This flag can be used for detecting out-of-sync conditions, detecting break conditions and protocol handling. The FEn flag is not affected by the setting of the USBSn bit in UCSRnC since the Receiver ignores all, except for the first, stop bits. For compatibility with future devices, always set this bit to zero when writ- ing to UCSRnA. The Data OverRun (DORn) flag indicates data loss due to a receiver buffer full condition. A Data OverRun occurs when the receive buffer is full (two characters), it is a new character waiting in the Receive Shift Register, and a new start bit is detected. If the DORn flag is set there was one or more serial frame lost between the frame last read from UDRn, and the next frame read from UDRn. For compatibility with future devices, always write this bit to zero when writing to UCS- RnA. The DORn flag is cleared when the frame received was successfully moved from the Shift Register to the receive buffer. The Parity Error (UPEn) Flag indicates that the next frame in the receive buffer had a Parity Error when received. If Parity Check is not enabled the UPEn bit will always be read zero. For compatibility with future devices, always set this bit to zero when writing to UCSRnA. For more details see “Parity Bit Calculation” on page 182 and “Parity Checker” on page 189. 17.8.5 Parity Checker The Parity Checker is active when the high USARTn Parity mode (UPMn1) bit is set. Type of Parity Check to be performed (odd or even) is selected by the UPMn0 bit. When enabled, the Parity Checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit from the serial frame. The result of the check is stored in the receive buffer together with the received data and stop bits. The Parity Error (UPEn) flag can then be read by software to check if the frame had a Parity Error. 189 7679H–CAN–08/08

The UPEn bit is set if the next character that can be read from the receive buffer had a Parity Error when received and the Parity Checking was enabled at that point (UPMn1 = 1). This bit is valid until the receive buffer (UDRn) is read. 17.8.6 Disabling the Receiver In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing receptions will therefore be lost. When disabled (i.e., the RXENn is set to zero) the Receiver will no longer override the normal function of the RxDn port pin. The Receiver buffer FIFO will be flushed when the Receiver is disabled. Remaining data in the buffer will be lost 17.8.7 Flushing the Receive Buffer The receiver buffer FIFO will be flushed when the Receiver is disabled, i.e., the buffer will be emptied of its contents. Unread data will be lost. If the buffer has to be flushed during normal operation, due to for instance an error condition, read the UDRn I/O location until the RXCn flag is cleared. The following code example shows how to flush the receive buffer. Assembly Code Example (1) USART0_Flush: lds r16, UCSR0A sbrs r16, RXC0 ret lds r16, UDR0 rjmp USART0_Flush C Code Example (1) void USART0_Flush (void) { unsigned char dummy; while (UCSR0A & (1<<RXC0) ) dummy = UDR0; } Note: 1. The example code assumes that the part specific header file is included. 17.9 Asynchronous Data Reception The USARTn includes a clock recovery and a data recovery unit for handling asynchronous data reception. The clock recovery logic is used for synchronizing the internally generated baud rate clock to the incoming asynchronous serial frames at the RxDn pin. The data recovery logic sam- ples and low pass filters each incoming bit, thereby improving the noise immunity of the Receiver. The asynchronous reception operational range depends on the accuracy of the inter- nal baud rate clock, the rate of the incoming frames, and the frame size in number of bits. 17.9.1 Asynchronous Clock Recovery The clock recovery logic synchronizes internal clock to the incoming serial frames. Figure 17-5 illustrates the sampling process of the start bit of an incoming frame. The sample rate is 16 times the baud rate for Normal mode, and eight times the baud rate for Double Speed mode. The hor- AT90CAN32/64/128 190 7679H–CAN–08/08

AT90CAN32/64/128 izontal arrows illustrate the synchronization variation due to the sampling process. Note the larger time variation when using the Double Speed mode (U2Xn = 1) of operation. Samples denoted zero are samples done when the RxDn line is idle (i.e., no communication activity). Figure 17-5. Start Bit Sampling RxDn IDLE START BIT 0 Sample (U2Xn = 0) 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 Sample (U2Xn = 1) 0 1 2 3 4 5 6 7 8 1 2 When the clock recovery logic detects a high (idle) to low (start) transition on the RxDn line, the start bit detection sequence is initiated. Let sample 1 denote the first zero-sample as shown in the figure. The clock recovery logic then uses samples 8, 9, and 10 for Normal mode, and sam- ples 4, 5, and 6 for Double Speed mode (indicated with sample numbers inside boxes on the figure), to decide if a valid start bit is received. If two or more of these three samples have logical high levels (the majority wins), the start bit is rejected as a noise spike and the Receiver starts looking for the next high to low-transition. If however, a valid start bit is detected, the clock recov- ery logic is synchronized and the data recovery can begin. The synchronization process is repeated for each start bit. 17.9.2 Asynchronous Data Recovery When the receiver clock is synchronized to the start bit, the data recovery can begin. The data recovery unit uses a state machine that has 16 states for each bit in Normal mode and eight states for each bit in Double Speed mode. Figure 17-6 shows the sampling of the data bits and the parity bit. Each of the samples is given a number that is equal to the state of the recovery unit. Figure 17-6. Sampling of Data and Parity Bit RxDn BIT x Sample (U2Xn = 0) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 Sample (U2Xn = 1) 1 2 3 4 5 6 7 8 1 The decision of the logic level of the received bit is taken by doing a majority voting of the logic value to the three samples in the center of the received bit. The center samples are emphasized on the figure by having the sample number inside boxes. The majority voting process is done as follows: If two or all three samples have high levels, the received bit is registered to be a logic 1. If two or all three samples have low levels, the received bit is registered to be a logic 0. This majority voting process acts as a low pass filter for the incoming signal on the RxDn pin. The recovery process is then repeated until a complete frame is received. Including the first stop bit. Note that the Receiver only uses the first stop bit of a frame. 191 7679H–CAN–08/08

Figure 17-7 shows the sampling of the stop bit and the earliest possible beginning of the start bit of the next frame. Figure 17-7. Stop Bit Sampling and Next Start Bit Sampling RxDn STOP 1 (A) (B) (C) Sample (U2Xn = 0) 1 2 3 4 5 6 7 8 9 10 0/1 0/1 0/1 Sample (U2Xn = 1) 1 2 3 4 5 6 0/1 The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is registered to have a logic 0 value, the Frame Error (FEn) flag will be set. A new high to low transition indicating the start bit of a new frame can come right after the last of the bits used for majority voting. For Normal Speed mode, the first low level sample can be at point marked (A) in Figure 17-7. For Double Speed mode the first low level must be delayed to (B). (C) marks a stop bit of full length. The early start bit detection influences the operational range of the Receiver. 17.9.3 Asynchronous Operational Range The operational range of the Receiver is dependent on the mismatch between the received bit rate and the internally generated baud rate. If the Transmitter is sending frames at too fast or too slow bit rates, or the internally generated baud rate of the Receiver does not have a similar (see Table 17-2) base frequency, the Receiver will not be able to synchronize the frames to the start bit. The following equations can be used to calculate the ratio of the incoming data rate and internal receiver baud rate. Rslow = S-----–----1--(--D-+-----+D-----1-⋅---)S--S---+----S----F-- Rfast = -(--D----(--+-D----1--+-)---S2----)+---S--S---M--- D Sum of character size and parity size (D = 5 to 10 bit) S Samples per bit. S = 16 for Normal Speed mode and S = 8 for Double Speed mode. S First sample number used for majority voting. S = 8 for normal speed and F F S = 4 for Double Speed mode. F S Middle sample number used for majority voting. S = 9 for normal speed and M M S =5 for Double Speed mode. M R is the ratio of the slowest incoming data rate that can be accepted in relation to slow the receiver baud rate. R is the ratio of the fastest incoming data rate that can be accepted in relation to the fast receiver baud rate. Table 17-2 and Table 17-3 list the maximum receiver baud rate error that can be tolerated. Note that Normal Speed mode has higher toleration of baud rate variations. AT90CAN32/64/128 192 7679H–CAN–08/08

AT90CAN32/64/128 Table 17-2. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2Xn = 0) D Recommended Max R (%) R (%) Max Total Error (%) # (Data + Parity Bit) slow fast Receiver Error (%) 5 93.20 106.67 +6.67/-6.8 ± 3.0 6 94.12 105.79 +5.79/-5.88 ± 2.5 7 94.81 105.11 +5.11/-5.19 ± 2.0 8 95.36 104.58 +4.58/-4.54 ± 2.0 9 95.81 104.14 +4.14/-4.19 ± 1.5 10 96.17 103.78 +3.78/-3.83 ± 1.5 Table 17-3. Recommended Maximum Receiver Baud Rate Error for Double Speed Mode (U2Xn = 1) D Recommended Max R (%) R (%) Max Total Error (%) # (Data + Parity Bit) slow fast Receiver Error (%) 5 94.12 105.66 +5.66/-5.88 ± 2.5 6 94.92 104.92 +4.92/-5.08 ± 2.0 7 95.52 104,35 +4.35/-4.48 ± 1.5 8 96.00 103.90 +3.90/-4.00 ± 1.5 9 96.39 103.53 +3.53/-3.61 ± 1.5 10 96.70 103.23 +3.23/-3.30 ± 1.0 The recommendations of the maximum receiver baud rate error was made under the assump- tion that the Receiver and Transmitter equally divides the maximum total error. There are two possible sources for the receivers baud rate error. The Receiver’s system clock (XTAL) will always have some minor instability over the supply voltage range and the tempera- ture range. When using a crystal to generate the system clock, this is rarely a problem, but for a resonator the system clock may differ more than 2% depending of the resonators tolerance. The second source for the error is more controllable. The baud rate generator can not always do an exact division of the system frequency to get the baud rate wanted. In this case an UBRRn value that gives an acceptable low error can be used if possible. 17.10 Multi-processor Communication Mode Setting the Multi-processor Communication mode (MPCMn) bit in UCSRnA enables a filtering function of incoming frames received by the USARTn Receiver. Frames that do not contain address information will be ignored and not put into the receive buffer. This effectively reduces the number of incoming frames that has to be handled by the CPU, in a system with multiple MCUs that communicate via the same serial bus. The Transmitter is unaffected by the MPCMn setting, but has to be used differently when it is a part of a system utilizing the Multi-processor Communication mode. 193 7679H–CAN–08/08

17.10.1 MPCM Protocol If the Receiver is set up to receive frames that contain 5 to 8 data bits, then the first stop bit indi- cates if the frame contains data or address information. If the Receiver is set up for frames with nine data bits, then the ninth bit (RXB8n) is used for identifying address and data frames. When the frame type bit (the first stop or the ninth bit) is one, the frame contains an address. When the frame type bit is zero the frame is a data frame. The Multi-processor Communication mode enables several slave MCUs to receive data from a master MCU. This is done by first decoding an address frame to find out which MCU has been addressed. If a particular slave MCU has been addressed, it will receive the following data frames as normal, while the other slave MCUs will ignore the received frames until another address frame is received. 17.10.2 Using MPCM For an MCU to act as a master MCU, it can use a 9-bit character frame format (UCSZn = 7). The ninth bit (TXB8n) must be set when an address frame (TXB8n = 1) or cleared when a data frame (TXBn = 0) is being transmitted. The slave MCUs must in this case be set to use a 9-bit charac- ter frame format. The following procedure should be used to exchange data in Multi-processor Communication mode: 1. All Slave MCUs are in Multi-processor Communication mode (MPCMn in UCSRnA is set). 2. The Master MCU sends an address frame, and all slaves receive and read this frame. In the Slave MCUs, the RXCn flag in UCSRnA will be set as normal. 3. Each Slave MCU reads the UDRn Register and determines if it has been selected. If so, it clears the MPCMn bit in UCSRnA, otherwise it waits for the next address byte and keeps the MPCMn setting. 4. The addressed MCU will receive all data frames until a new address frame is received. The other Slave MCUs, which still have the MPCMn bit set, will ignore the data frames. 5. When the last data frame is received by the addressed MCU, the addressed MCU sets the MPCMn bit and waits for a new address frame from master. The process then repeats from 2. Using any of the 5- to 8-bit character frame formats is possible, but impractical since the Receiver must change between using N and N+1 character frame formats. This makes full- duplex operation difficult since the Transmitter and Receiver use the same character size set- ting. If 5- to 8-bit character frames are used, the Transmitter must be set to use two stop bit (USBSn = 1) since the first stop bit is used for indicating the frame type. AT90CAN32/64/128 194 7679H–CAN–08/08

AT90CAN32/64/128 17.11 USART Register Description 17.11.1 USART0 I/O Data Register – UDR0 Bit 7 6 5 4 3 2 1 0 RXB0[7:0] UDR0 (Read) TXB0[7:0] UDR0 (Write) Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 17.11.2 USART1 I/O Data Register – UDR1 Bit 7 6 5 4 3 2 1 0 RXB1[7:0] UDR1 (Read) TXB1[7:0] UDR1 (Write) Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 7:0 – RxBn7:0: Receive Data Buffer (read access) • Bit 7:0 – TxBn7:0: Transmit Data Buffer (write access) The USARTn Transmit Data Buffer Register and USARTn Receive Data Buffer Registers share the same I/O address referred to as USARTn Data Register or UDRn. The Transmit Data Buffer Register (TXBn) will be the destination for data written to the UDRn Register location. Reading the UDRn Register location will return the contents of the Receive Data Buffer Register (RXBn). For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the Transmitter and set to zero by the Receiver. The transmit buffer can only be written when the UDREn flag in the UCSRnA Register is set. Data written to UDRn when the UDREn flag is not set, will be ignored by the USARTn Transmit- ter. When data is written to the transmit buffer, and the Transmitter is enabled, the Transmitter will load the data into the Transmit Shift Register when the Shift Register is empty. Then the data will be serially transmitted on the TxDn pin. The receive buffer consists of a two level FIFO. The FIFO will change its state whenever the receive buffer is accessed. 17.11.3 USART0 Control and Status Register A – UCSR0A Bit 7 6 5 4 3 2 1 0 RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0 UCSR0A Read/Write R R/W R R R R R/W R/W Initial Value 0 0 1 0 0 0 0 0 17.11.4 USART1 Control and Status Register A – UCSR1A Bit 7 6 5 4 3 2 1 0 RXC1 TXC1 UDRE1 FE1 DOR1 UPE1 U2X1 MPCM1 UCSR1A Read/Write R R/W R R R R R/W R/W Initial Value 0 0 1 0 0 0 0 0 • Bit 7 – RXCn: USARTn Receive Complete This flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled, the receive buffer will be flushed and consequently the RXCn bit will become zero. The RXCn flag can be used to generate a Receive Complete interrupt (see description of the RXCIEn bit). 195 7679H–CAN–08/08

• Bit 6 – TXCn: USARTn Transmit Complete This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and there are no new data currently present in the transmit buffer (UDRn). The TXCn flag bit is auto- matically cleared when a transmit complete interrupt is executed, or it can be cleared by writing a one to its bit location. The TXCn flag can generate a Transmit Complete interrupt (see descrip- tion of the TXCIEn bit). • Bit 5 – UDREn: USARTn Data Register Empty The UDREn flag indicates if the transmit buffer (UDRn) is ready to receive new data. If UDREn is one, the buffer is empty, and therefore ready to be written. The UDREn flag can generate a Data Register Empty interrupt (see description of the UDRIEn bit). UDREn is set after a reset to indicate that the Transmitter is ready. • Bit 4 – FEn: Frame Error This bit is set if the next character in the receive buffer had a Frame Error when received. I.e., when the first stop bit of the next character in the receive buffer is zero. This bit is valid until the receive buffer (UDRn) is read. The FEn bit is zero when the stop bit of received data is one. Always set this bit to zero when writing to UCSRnA. • Bit 3 – DORn: Data OverRun This bit is set if a Data OverRun condition is detected. A Data OverRun occurs when the receive buffer is full (two characters), it is a new character waiting in the Receive Shift Register, and a new start bit is detected. This bit is valid until the receive buffer (UDRn) is read. Always set this bit to zero when writing to UCSRnA. • Bit 2 – UPEn: USARTn Parity Error This bit is set if the next character in the receive buffer had a Parity Error when received and the Parity Checking was enabled at that point (UPMn1 = 1). This bit is valid until the receive buffer (UDRn) is read. Always set this bit to zero when writing to UCSRnA. • Bit 1 – U2Xn: Double the USARTn Transmission Speed This bit only has effect for the asynchronous operation. Write this bit to zero when using syn- chronous operation. Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively dou- bling the transfer rate for asynchronous communication. • Bit 0 – MPCMn: Multi-processor Communication Mode This bit enables the Multi-processor Communication mode. When the MPCMn bit is written to one, all the incoming frames received by the USARnT Receiver that do not contain address information will be ignored. The Transmitter is unaffected by the MPCMn setting. For more detailed information see “Multi-processor Communication Mode” on page 193. 17.11.5 USART0 Control and Status Register B – UCSR0B Bit 7 6 5 4 3 2 1 0 RXCIE0 TXCIE0 UDRIE0 RXEN0 TXEN0 UCSZ02 RXB80 TXB80 UCSR0B Read/Write R/W R/W R/W R/W R/W R/W R R/W Initial Value 0 0 0 0 0 0 0 0 AT90CAN32/64/128 196 7679H–CAN–08/08

AT90CAN32/64/128 17.11.6 USART1 Control and Status Register B – UCSR1B Bit 7 6 5 4 3 2 1 0 RXCIE1 TXCIE1 UDRIE1 RXEN1 TXEN1 UCSZ12 RXB81 TXB81 UCSR1B Read/Write R/W R/W R/W R/W R/W R/W R R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 7 – RXCIEn: RX Complete Interrupt Enable Writing this bit to one enables interrupt on the RXCn flag. A USARTn Receive Complete inter- rupt will be generated only if the RXCIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the RXCn bit in UCSRnA is set. • Bit 6 – TXCIEn: TX Complete Interrupt Enable Writing this bit to one enables interrupt on the TXCn flag. A USARTn Transmit Complete inter- rupt will be generated only if the TXCIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the TXCn bit in UCSRnA is set. • Bit 5 – UDRIEn: USARTn Data Register Empty Interrupt Enable Writing this bit to one enables interrupt on the UDREn flag. A Data Register Empty interrupt will be generated only if the UDRIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the UDREn bit in UCSRnA is set. • Bit 4 – RXENn: Receiver Enable Writing this bit to one enables the USARTn Receiver. The Receiver will override normal port operation for the RxDn pin when enabled. Disabling the Receiver will flush the receive buffer invalidating the FEn, DORn, and UPEn Flags. • Bit 3 – TXENn: Transmitter Enable Writing this bit to one enables the USARTn Transmitter. The Transmitter will override normal port operation for the TxDn pin when enabled. The disabling of the Transmitter (writing TXENn to zero) will not become effective until ongoing and pending transmissions are completed, i.e., when the Transmit Shift Register and Transmit Buffer Register do not contain data to be trans- mitted. When disabled, the Transmitter will no longer override the TxDn port. • Bit 2 – UCSZn2: Character Size The UCSZn2 bits combined with the UCSZn1:0 bit in UCSRnC sets the number of data bits (Character SiZe) in a frame the Receiver and Transmitter use. • Bit 1 – RXB8n: Receive Data Bit 8 RXB8n is the ninth data bit of the received character when operating with serial frames with nine data bits. Must be read before reading the low bits from UDRn. • Bit 0 – TXB8n: Transmit Data Bit 8 TXB8n is the ninth data bit in the character to be transmitted when operating with serial frames with nine data bits. Must be written before writing the low bits to UDRn. 17.11.7 USART0 Control and Status Register C – UCSR0C Bit 7 6 5 4 3 2 1 0 – UMSEL0 UPM01 UPM00 USBS0 UCSZ01 UCSZ00 UCPOL0 UCSR0C Read/Write R R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 1 1 0 197 7679H–CAN–08/08

17.11.8 USART1 Control and Status Register C – UCSR1C Bit 7 6 5 4 3 2 1 0 – UMSEL1 UPM11 UPM10 USBS1 UCSZ11 UCSZ10 UCPO1L UCSR1C Read/Write R R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 1 1 0 • Bit 7 – Reserved Bit This bit is reserved for future use. For compatibility with future devices, these bit must be written to zero when UCSRnC is written. • Bit 6 – UMSELn: USARTn Mode Select This bit selects between asynchronous and synchronous mode of operation. Table 17-4. UMSELn Bit Settings UMSELn Mode 0 Asynchronous Operation 1 Synchronous Operation • Bit 5:4 – UPMn1:0: Parity Mode These bits enable and set type of parity generation and check. If enabled, the Transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The Receiver will generate a parity value for the incoming data and compare it to the UPMn0 setting. If a mismatch is detected, the UPEn Flag in UCSRnA will be set. Table 17-5. UPMn Bits Settings UPMn1 UPMn0 Parity Mode 0 0 Disabled 0 1 Reserved 1 0 Enabled, Even Parity 1 1 Enabled, Odd Parity • Bit 3 – USBSn: Stop Bit Select This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores this setting. Table 17-6. USBSn Bit Settings USBSn Stop Bit(s) 0 1-bit 1 2-bit AT90CAN32/64/128 198 7679H–CAN–08/08

AT90CAN32/64/128 • Bit 2:1 – UCSZn1:0: Character Size The UCSZn1:0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits (Character SiZe) in a frame the Receiver and Transmitter use. Table 17-7. UCSZn Bits Settings UCSZn2 UCSZn1 UCSZn0 Character Size 0 0 0 5-bit 0 0 1 6-bit 0 1 0 7-bit 0 1 1 8-bit 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 9-bit • Bit 0 – UCPOLn: Clock Polarity This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOLn bit sets the relationship between data output change and data input sample, and the synchronous clock (XCKn). Table 17-8. UCPOLn Bit Settings Transmitted Data Changed Received Data Sampled UCPOLn (Output of TxDn Pin) (Input on RxDn Pin) 0 Rising XCK Edge Falling XCK Edge 1 Falling XCK Edge Rising XCK Edge 17.11.9 USART0 Baud Rate Registers – UBRR0L and UBRR0H Bit 15 14 13 12 11 10 9 8 – – – – UBRR0[11:8] UBRR0H UBRR0[7:0] UBRR0L 7 6 5 4 3 2 1 0 Read/Write R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17.11.10 USART1 Baud Rate Registers – UBRR1L and UBRR1H Bit 15 14 13 12 11 10 9 8 – – – – UBRR1[11:8] UBRR1H UBRR1[7:0] UBRR1L 7 6 5 4 3 2 1 0 Read/Write R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 199 7679H–CAN–08/08

• Bit 15:12 – Reserved Bits These bits are reserved for future use. For compatibility with future devices, these bit must be written to zero when UBRRnH is written. • Bit 11:0 – UBRRn11:0: USARTn Baud Rate Register This is a 12-bit register which contains the USARTn baud rate. The UBRRnH contains the four most significant bits, and the UBRRnL contains the eight least significant bits of the USARTn baud rate. Ongoing transmissions by the Transmitter and Receiver will be corrupted if the baud rate is changed. Writing UBRRnL will trigger an immediate update of the baud rate prescaler. 17.12 Examples of Baud Rate Setting For standard crystal, resonator and external oscillator frequencies, the most commonly used baud rates for asynchronous operation can be generated by using the UBRRn settings in Table 17-9 up to Table 17-12. UBRRn values which yield an actual baud rate differing less than 0.5% from the target baud rate, are bold in the table. Higher error ratings are acceptable, but the Receiver will have less noise resistance when the error ratings are high, especially for large serial frames (see “Asynchronous Operational Range” on page 192). The error values are calcu- lated using the following equation: BaudRate ⎛ Closest Match⎞ Error[%] = 1–-------------------------------------------------------- •100% ⎝ BaudRate ⎠ Table 17-9. Examples of UBRRn Settings for Commonly Frequencies fclk = 1.0000 MHz fclk = 1.8432 MHz fclk = 2.0000 MHz Baud io io io Rate U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1 (bps) UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error 2400 25 0.2% 51 0.2% 47 0.0% 95 0.0% 51 0.2% 103 0.2% 4800 12 0.2% 25 0.2% 23 0.0% 47 0.0% 25 0.2% 51 0.2% 9600 6 -7.0% 12 0.2% 11 0.0% 23 0.0% 12 0.2% 25 0.2% 14.4k 3 8.5% 8 -3.5% 7 0.0% 15 0.0% 8 -3.5% 16 2.1% 19.2k 2 8.5% 6 -7.0% 5 0.0% 11 0.0% 6 -7.0% 12 0.2% 28.8k 1 8.5% 3 8.5% 3 0.0% 7 0.0% 3 8.5% 8 -3.5% 38.4k 1 -18.6% 2 8.5% 2 0.0% 5 0.0% 2 8.5% 6 -7.0% 57.6k 0 8.5% 1 8.5% 1 0.0% 3 0.0% 1 8.5% 3 8.5% 76.8k – – 1 -18.6% 1 -25.0% 2 0.0% 1 -18.6% 2 8.5% 115.2k – – 0 8.5% 0 0.0% 1 0.0% 0 8.5% 1 8.5% 230.4k – – – – – – 0 0.0% – – – – 250k – – – – – – – – – – – – 500k – – – – – – – – – – – – 1M – – – – – – – – – – – – Max. (1) 62.5 Kbps 125 Kbps 115.2 Kbps 230.4 Kbps 125 Kbps 250 Kbps Note: 1. UBRRn = 0, Error = 0.0% AT90CAN32/64/128 200 7679H–CAN–08/08

AT90CAN32/64/128 Table 17-10. Examples of UBRRn Settings for Commonly Frequencies (Continued) fclk = 3.6864 MHz fclk = 4.0000 MHz fclk = 7.3728 MHz Baud io io io Rate U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1 (bps) UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error 2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0% 4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0% 9600 23 0.0% 47 0.0% 25 0.2% 51 0.2% 47 0.0% 95 0.0% 14.4k 15 0.0% 31 0.0% 16 2.1% 34 -0.8% 31 0.0% 63 0.0% 19.2k 11 0.0% 23 0.0% 12 0.2% 25 0.2% 23 0.0% 47 0.0% 28.8k 7 0.0% 15 0.0% 8 -3.5% 16 2.1% 15 0.0% 31 0.0% 38.4k 5 0.0% 11 0.0% 6 -7.0% 12 0.2% 11 0.0% 23 0.0% 57.6k 3 0.0% 7 0.0% 3 8.5% 8 -3.5% 7 0.0% 15 0.0% 76.8k 2 0.0% 5 0.0% 2 8.5% 6 -7.0% 5 0.0% 11 0.0% 115.2k 1 0.0% 3 0.0% 1 8.5% 3 8.5% 3 0.0% 7 0.0% 230.4k 0 0.0% 1 0.0% 0 8.5% 1 8.5% 1 0.0% 3 0.0% 250k 0 -7.8% 1 -7.8% 0 0.0% 1 0.0% 1 -7.8% 3 -7.8% 500k – – 0 -7.8% – – 0 0.0% 0 -7.8% 1 -7.8% 1M – – – – – – – – – – 0 -7.8% Max.(1) 230.4 Kbps 460.8 Kbps 250 Kbps 0.5 Mbps 460.8 Kbps 921.6 Kbps Note: 1. UBRRn = 0, Error = 0.0% 201 7679H–CAN–08/08

Table 17-11. Examples of UBRRn Settings for Commonly Frequencies (Continued) fclk = 8.0000 MHz fclk = 10.000 MHz fclk = 11.0592 MHz Baud io io io Rate U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1 (bps) UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error 2400 207 0.2% 416 -0.1% 259 0.2% 520 0.0% 287 0.0% 575 0.0% 4800 103 0.2% 207 0.2% 129 0.2% 259 0.2% 143 0.0% 287 0.0% 9600 51 0.2% 103 0.2% 64 0.2% 129 0.2% 71 0.0% 143 0.0% 14.4k 34 -0.8% 68 0.6% 42 0.9% 86 0.2% 47 0.0% 95 0.0% 19.2k 25 0.2% 51 0.2% 32 -1.4% 64 0.2% 35 0.0% 71 0.0% 28.8k 16 2.1% 34 -0.8% 21 -1.4% 42 0.9% 23 0.0% 47 0.0% 38.4k 12 0.2% 25 0.2% 15 1.8% 32 -1.4% 17 0.0% 35 0.0% 57.6k 8 -3.5% 16 2.1% 10 -1.5% 21 -1.4% 11 0.0% 23 0.0% 76.8k 6 -7.0% 12 0.2% 7 1.9% 15 1.8% 8 0.0% 17 0.0% 115.2k 3 8.5% 8 -3.5% 4 9.6% 10 -1.5% 5 0.0% 11 0.0% 230.4k 1 8.5% 3 8.5% 2 -16.8% 4 9.6% 2 0.0% 5 0.0% 250k 1 0.0% 3 0.0% 2 -33.3% 4 0.0% 2 -7.8% 5 -7.8% 500k 0 0.0% 1 0.0% – – 2 -33.3% – – 2 -7.8% 1M – – 0 0.0% – – – – – – – – Max. (1) 0.5 Mbps 1 Mbps 625 Kbps 1.25 Mbps 691.2 Kbps 1.3824 Mbps Note: 1. UBRRn = 0, Error = 0.0% AT90CAN32/64/128 202 7679H–CAN–08/08

AT90CAN32/64/128 Table 17-12. Examples of UBRRn Settings for Commonly Frequencies (Continued) fclk = 12.0000 MHz fclk = 14.7456 MHz fclk = 16.0000 MHz Baud io io io Rate U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1 U2Xn = 0 U2Xn = 1 (bps) UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error UBRRn Error 2400 312 -0.2% 624 0.0% 383 0.0% 767 0.0% 416 -0.1% 832 0.0% 4800 155 0.2% 312 -0.2% 191 0.0% 383 0.0% 207 0.2% 416 -0.1% 9600 77 0.2% 155 0.2% 95 0.0% 191 0.0% 103 0.2% 207 0.2% 14.4k 51 0.2% 103 0.2% 63 0.0% 127 0.0% 68 0.6% 138 -0.1% 19.2k 38 0.2% 77 0.2% 47 0.0% 95 0.0% 51 0.2% 103 0.2% 28.8k 25 0.2% 51 0.2% 31 0.0% 63 0.0% 34 -0.8% 68 0.6% 38.4k 19 -2.5% 38 0.2% 23 0.0% 47 0.0% 25 0.2% 51 0.2% 57.6k 12 0.2% 25 0.2% 15 0.0% 31 0.0% 16 2.1% 34 -0.8% 76.8k 9 -2.7% 19 -2.5% 11 0.0% 23 0.0% 12 0.2% 25 0.2% 115.2k 6 -8.9% 12 0.2% 7 0.0% 15 0.0% 8 -3.5% 16 2.1% 230.4k 2 11.3% 6 -8.9% 3 0.0% 7 0.0% 3 8.5% 8 -3.5% 250k 2 0.0% 5 0.0% 3 -7.8% 6 5.3% 3 0.0% 7 0.0% 500k – – 2 0.0% 1 -7.8% 3 -7.8% 1 0.0% 3 0.0% 1M – – – – 0 -7.8% 1 -7.8% 0 0.0% 1 0.0% Max. (1) 750 Kbps 1.5 Mbps 921.6 Kbps 1.8432 Mbps 1 Mbps 2 Mbps Note: 1. UBRRn = 0, Error = 0.0% 203 7679H–CAN–08/08

18. Two-wire Serial Interface 18.1 Features • Simple yet Powerful and Flexible Communication Interface, only Two Bus Lines Needed • Both Master and Slave Operation Supported • Device can Operate as Transmitter or Receiver • 7-bit Address Space allows up to 128 Different Slave Addresses • Multi-master Arbitration Support • Up to 400 kHz Data Transfer Speed • Slew-rate Limited Output Drivers • Noise Suppression Circuitry Rejects Spikes on Bus Lines • Fully Programmable Slave Address with General Call Support • Address Recognition Causes Wake-up when AVR is in Sleep Mode 18.2 Two-wire Serial Interface Bus Definition The Two-wire Serial Interface (TWI) is ideally suited for typical microcontroller applications. The TWI protocol allows the systems designer to interconnect up to 128 different devices using only two bi-directional bus lines, one for clock (SCL) and one for data (SDA). The only external hard- ware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines. All devices connected to the bus have individual addresses, and mechanisms for resolving bus contention are inherent in the TWI protocol. Figure 18-1. TWI Bus Interconnection Device 1 Device 2 Device 3 ........ Device n V CC R1 R2 SDA SCL 18.2.1 TWI Terminology The following definitions are frequently encountered in this section. Table 18-1. TWI Terminology Term Description The device that initiates and terminates a transmission. The master also generates the Master SCL clock Slave The device addressed by a master Transmitter The device placing data on the bus Receiver The device reading data from the bus AT90CAN32/64/128 204 7679H–CAN–08/08

AT90CAN32/64/128 18.2.2 Electrical Interconnection As depicted in Figure 18-1, both bus lines are connected to the positive supply voltage through pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or open-collector. This implements a wired-AND function which is essential to the operation of the interface. A low level on a TWI bus line is generated when one or more TWI devices output a zero. A high level is output when all TWI devices tri-state their outputs, allowing the pull-up resistors to pull the line high. Note that all AVR devices connected to the TWI bus must be powered in order to allow any bus operation. The number of devices that can be connected to the bus is only limited by the bus capacitance limit of 400 pF and the 7-bit slave address space. A detailed specification of the electrical char- acteristics of the TWI is given in “Two-wire Serial Interface Characteristics” on page 369. Two different sets of specifications are presented there, one relevant for bus speeds below 100 kHz, and one valid for bus speeds up to 400 kHz. 18.3 Data Transfer and Frame Format 18.3.1 Transferring Bits Each data bit transferred on the TWI bus is accompanied by a pulse on the clock line. The level of the data line must be stable when the clock line is high. The only exception to this rule is for generating start and stop conditions. Figure 18-2. Data Validity SDA SCL Data Stable Data Stable Data Change 18.3.2 START and STOP Conditions The master initiates and terminates a data transmission. The transmission is initiated when the master issues a START condition on the bus, and it is terminated when the master issues a STOP condition. Between a START and a STOP condition, the bus is considered busy, and no other master should try to seize control of the bus. A special case occurs when a new START condition is issued between a START and STOP condition. This is referred to as a REPEATED START condition, and is used when the master wishes to initiate a new transfer without relin- quishing control of the bus. After a REPEATED START, the bus is considered busy until the next STOP. This is identical to the START behaviour, and therefore START is used to describe both START and REPEATED START for the remainder of this datasheet, unless otherwise noted. As depicted below, START and STOP conditions are signalled by changing the level of the SDA line when the SCL line is high. 205 7679H–CAN–08/08

Figure 18-3. START, REPEATED START and STOP Conditions SDA SCL START STOP START REPEATED START STOP 18.3.3 Address Packet Format All address packets transmitted on the TWI bus are 9 bits long, consisting of 7 address bits, one READ/WRITE control bit and an acknowledge bit. If the READ/WRITE bit is set, a read opera- tion is to be performed, otherwise a write operation should be performed. When a slave recognizes that it is being addressed, it should acknowledge by pulling SDA low in the ninth SCL (ACK) cycle. If the addressed slave is busy, or for some other reason can not service the mas- ter’s request, the SDA line should be left high in the ACK clock cycle. The master can then transmit a STOP condition, or a REPEATED START condition to initiate a new transmission. An address packet consisting of a slave address and a READ or a WRITE bit is called SLA+R or SLA+W, respectively. The MSB of the address byte is transmitted first. Slave addresses can freely be allocated by the designer, but the address 0000 000 is reserved for a general call. When a general call is issued, all slaves should respond by pulling the SDA line low in the ACK cycle. A general call is used when a master wishes to transmit the same message to several slaves in the system. When the general call address followed by a Write bit is transmitted on the bus, all slaves set up to acknowledge the general call will pull the SDA line low in the ack cycle. The following data packets will then be received by all the slaves that acknowledged the general call. Note that transmitting the general call address followed by a Read bit is meaningless, as this would cause contention if several slaves started transmitting different data. All addresses of the format 1111 xxx should be reserved for future purposes. Figure 18-4. Address Packet Format Addr MSB Addr LSB R/W ACK SDA SCL 1 2 7 8 9 START 18.3.4 Data Packet Format All data packets transmitted on the TWI bus are 9 bits long, consisting of one data byte and an acknowledge bit. During a data transfer, the master generates the clock and the START and STOP conditions, while the receiver is responsible for acknowledging the reception. An AT90CAN32/64/128 206 7679H–CAN–08/08

AT90CAN32/64/128 Acknowledge (ACK) is signalled by the receiver pulling the SDA line low during the ninth SCL cycle. If the receiver leaves the SDA line high, a NACK is signalled. When the receiver has received the last byte, or for some reason cannot receive any more bytes, it should inform the transmitter by sending a NACK after the final byte. The MSB of the data byte is transmitted first. Figure 18-5. Data Packet Format Data MSB Data LSB ACK Aggregate SDA SDA from Transmitter SDA from Receiver SCL from Master 1 2 7 8 9 STOP, REPEATED SLA+R/W Data Byte START or Next Data Byte 18.3.5 Combining Address and Data Packets Into a Transmission A transmission basically consists of a START condition, a SLA+R/W, one or more data packets and a STOP condition. An empty message, consisting of a START followed by a STOP condi- tion, is illegal. Note that the Wired-ANDing of the SCL line can be used to implement handshaking between the master and the slave. The slave can extend the SCL low period by pulling the SCL line low. This is useful if the clock speed set up by the master is too fast for the slave, or the slave needs extra time for processing between the data transmissions. The slave extending the SCL low period will not affect the SCL high period, which is determined by the master. As a consequence, the slave can reduce the TWI data transfer speed by prolonging the SCL duty cycle. Figure 18-6 shows a typical data transmission. Note that several data bytes can be transmitted between the SLA+R/W and the STOP condition, depending on the software protocol imple- mented by the application software. Figure 18-6. Typical Data Transmission Addr MSB Addr LSB R/W ACK Data MSB Data LSB ACK SDA SCL 1 2 7 8 9 1 2 7 8 9 START SLA+R/W Data Byte STOP 18.4 Multi-master Bus Systems, Arbitration and Synchronization The TWI protocol allows bus systems with several masters. Special concerns have been taken in order to ensure that transmissions will proceed as normal, even if two or more masters initiate a transmission at the same time. Two problems arise in multi-master systems: 207 7679H–CAN–08/08

• An algorithm must be implemented allowing only one of the masters to complete the transmission. All other masters should cease transmission when they discover that they have lost the selection process. This selection process is called arbitration. When a contending master discovers that it has lost the arbitration process, it should immediately switch to slave mode to check whether it is being addressed by the winning master. The fact that multiple masters have started transmission at the same time should not be detectable to the slaves, i.e., the data being transferred on the bus must not be corrupted. • Different masters may use different SCL frequencies. A scheme must be devised to synchronize the serial clocks from all masters, in order to let the transmission proceed in a lockstep fashion. This will facilitate the arbitration process. The wired-ANDing of the bus lines is used to solve both these problems. The serial clocks from all masters will be wired-ANDed, yielding a combined clock with a high period equal to the one from the master with the shortest high period. The low period of the combined clock is equal to the low period of the master with the longest low period. Note that all masters listen to the SCL line, effectively starting to count their SCL high and low time-out periods when the combined SCL line goes high or low, respectively. Figure 18-7. SCL Synchronization between Multiple Masters TA TA low high SCL from master A SCL from master B SCL Bus Line TB TB low high Masters Start Masters Start Counting Low Period Counting High Period Arbitration is carried out by all masters continuously monitoring the SDA line after outputting data. If the value read from the SDA line does not match the value the master had output, it has lost the arbitration. Note that a master can only lose arbitration when it outputs a high SDA value while another master outputs a low value. The losing master should immediately go to slave mode, checking if it is being addressed by the winning master. The SDA line should be left high, but losing masters are allowed to generate a clock signal until the end of the current data or address packet. Arbitration will continue until only one master remains, and this may take many bits. If several masters are trying to address the same slave, arbitration will continue into the data packet. AT90CAN32/64/128 208 7679H–CAN–08/08

AT90CAN32/64/128 Figure 18-8. Arbitration Between two Masters START Master A loses Arbitration, SDA SDA SDA from A Master A SDA from Master B SDA Line Synchronized SCL Line Note that arbitration is not allowed between: • A REPEATED START condition and a data bit • A STOP condition and a data bit • A REPEATED START and a STOP condition It is the user software’s responsibility to ensure that these illegal arbitration conditions never occur. This implies that in multi-master systems, all data transfers must use the same composi- tion of SLA+R/W and data packets. In other words: All transmissions must contain the same number of data packets, otherwise the result of the arbitration is undefined. 18.5 Overview of the TWI Module The TWI module is comprised of several submodules, as shown in Figure 18-9. All registers drawn in a thick line are accessible through the AVR data bus. 209 7679H–CAN–08/08

Figure 18-9. Overview of the TWI Module SCL SDA Slew-rate Spike Slew-rate Spike Control Filter Control Filter Bus Interface Unit Bit Rate Generator START / STOP Spike Suppression Prescaler Control Address/Data Shift Bit Rate Register Arbitration detection Ack Register (TWDR) (TWBR) Address Match Unit Control Unit Address Register Status Register Control Register (TWAR) (TWSR) (TWCR) TWI State Machine and Address Comparator Status control Unit 18.5.1 SCL and SDA Pins These pins interface the AVR TWI with the rest of the MCU system. The output drivers contain a slew-rate limiter in order to conform to the TWI specification. The input stages contain a spike suppression unit removing spikes shorter than 50 ns. Note that the internal pullups in the AVR pads can be enabled by setting the PORT bits corresponding to the SCL and SDA pins, as explained in the I/O Port section. The internal pull-ups can in some systems eliminate the need for external ones. 18.5.2 Bit Rate Generator Unit This unit controls the period of SCL when operating in a Master mode. The SCL period is con- trolled by settings in the TWI Bit Rate Register (TWBR) and the Prescaler bits in the TWI Status Register (TWSR). Slave operation does not depend on Bit Rate or Prescaler settings, but the CPU clock frequency in the slave must be at least 16 times higher than the SCL frequency. Note that slaves may prolong the SCL low period, thereby reducing the average TWI bus clock period. The SCL frequency is generated according to the following equation: CLKio SCL frequency = ----------------------------------------------------------- TWPS 16+2(TWBR)⋅4 • TWBR = Value of the TWI Bit Rate Register • TWPS = Value of the prescaler bits in the TWI Status Register Note: TWBR should be 10 or higher if the TWI operates in Master mode. If TWBR is lower than 10, the master may produce an incorrect output on SDA and SCL for the reminder of the byte. The prob- lem occurs when operating the TWI in Master mode, sending Start + SLA + R/W to a slave (a slave does not need to be connected to the bus for the condition to happen). AT90CAN32/64/128 210 7679H–CAN–08/08

AT90CAN32/64/128 18.5.3 Bus Interface Unit This unit contains the Data and Address Shift Register (TWDR), a START/STOP Controller and Arbitration detection hardware. The TWDR contains the address or data bytes to be transmitted, or the address or data bytes received. In addition to the 8-bit TWDR, the Bus Interface Unit also contains a register containing the (N)ACK bit to be transmitted or received. This (N)ACK Regis- ter is not directly accessible by the application software. However, when receiving, it can be set or cleared by manipulating the TWI Control Register (TWCR). When in Transmitter mode, the value of the received (N)ACK bit can be determined by the value in the TWSR. The START/STOP Controller is responsible for generation and detection of START, REPEATED START, and STOP conditions. The START/STOP controller is able to detect START and STOP conditions even when the AVR MCU is in one of the sleep modes, enabling the MCU to wake up if addressed by a master. If the TWI has initiated a transmission as master, the Arbitration Detection hardware continu- ously monitors the transmission trying to determine if arbitration is in process. If the TWI has lost an arbitration, the Control Unit is informed. Correct action can then be taken and appropriate status codes generated. 18.5.4 Address Match Unit The Address Match unit checks if received address bytes match the 7-bit address in the TWI Address Register (TWAR). If the TWI General Call Recognition Enable (TWGCE) bit in the TWAR is written to one, all incoming address bits will also be compared against the General Call address. Upon an address match, the Control Unit is informed, allowing correct action to be taken. The TWI may or may not acknowledge its address, depending on settings in the TWCR. The Address Match unit is able to compare addresses even when the AVR MCU is in sleep mode, enabling the MCU to wake up if addressed by a master. If another interrupt (e.g., INT0) occurs during TWI Power-down address match and wakes up the CPU, the TWI aborts opera- tion and return to it’s idle state. If this cause any problems, ensure that TWI Address Match is the only enabled interrupt when entering Power-down. 18.5.5 Control Unit The Control unit monitors the TWI bus and generates responses corresponding to settings in the TWI Control Register (TWCR). When an event requiring the attention of the application occurs on the TWI bus, the TWI Interrupt Flag (TWINT) is asserted. In the next clock cycle, the TWI Sta- tus Register (TWSR) is updated with a status code identifying the event. The TWSR only contains relevant status information when the TWI Interrupt Flag is asserted. At all other times, the TWSR contains a special status code indicating that no relevant status information is avail- able. As long as the TWINT flag is set, the SCL line is held low. This allows the application software to complete its tasks before allowing the TWI transmission to continue. The TWINT flag is set in the following situations: • After the TWI has transmitted a START/REPEATED START condition • After the TWI has transmitted SLA+R/W • After the TWI has transmitted an address byte • After the TWI has lost arbitration • After the TWI has been addressed by own slave address or general call • After the TWI has received a data byte • After a STOP or REPEATED START has been received while still addressed as a slave 211 7679H–CAN–08/08

• When a bus error has occurred due to an illegal START or STOP condition 18.6 TWI Register Description 18.6.1 TWI Bit Rate Register – TWBR Bit 7 6 5 4 3 2 1 0 TWBR7 TWBR6 TWBR5 TWBR4 TWBR3 TWBR2 TWBR1 TWBR0 TWBR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bits 7.0 – TWI Bit Rate Register TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency divider which generates the SCL clock frequency in the Master modes. See “Bit Rate Generator Unit” on page 210 for calculating bit rates. 18.6.2 TWI Control Register – TWCR Bit 7 6 5 4 3 2 1 0 TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE TWCR Read/Write R/W R/W R/W R/W R R/W R R/W Initial Value 0 0 0 0 0 0 0 0 The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to initiate a master access by applying a START condition to the bus, to generate a receiver acknowledge, to generate a stop condition, and to control halting of the bus while the data to be written to the bus are written to the TWDR. It also indicates a write collision if data is attempted written to TWDR while the register is inaccessible. • Bit 7 – TWINT: TWI Interrupt Flag This bit is set by hardware when the TWI has finished its current job and expects application software response. If the I-bit in SREG and TWIE in TWCR are set, the MCU will jump to the TWI interrupt vector. While the TWINT flag is set, the SCL low period is stretched. The TWINT flag must be cleared by software by writing a logic one to it. Note that this flag is not automati- cally cleared by hardware when executing the interrupt routine. Also note that clearing this flag starts the operation of the TWI, so all accesses to the TWI Address Register (TWAR), TWI Sta- tus Register (TWSR), and TWI Data Register (TWDR) must be complete before clearing this flag. • Bit 6 – TWEA: TWI Enable Acknowledge Bit The TWEA bit controls the generation of the ACK pulse. If the TWEA bit is written to one, the ACK pulse is generated on the TWI bus if the following conditions are met: 1. The device’s own slave address has been received. 2. A general call has been received, while the TWGCE bit in the TWAR is set. 3. A data byte has been received in Master Receiver or Slave Receiver mode. By writing the TWEA bit to zero, the device can be virtually disconnected from the Two-wire Serial Bus temporarily. Address recognition can then be resumed by writing the TWEA bit to one again. • Bit 5 – TWSTA: TWI START Condition Bit AT90CAN32/64/128 212 7679H–CAN–08/08

AT90CAN32/64/128 The application writes the TWSTA bit to one when it desires to become a master on the Two- wire Serial Bus. The TWI hardware checks if the bus is available, and generates a START con- dition on the bus if it is free. However, if the bus is not free, the TWI waits until a STOP condition is detected, and then generates a new START condition to claim the bus Master status. TWSTA must be cleared by software when the START condition has been transmitted. • Bit 4 – TWSTO: TWI STOP Condition Bit Writing the TWSTO bit to one in Master mode will generate a STOP condition on the Two-wire Serial Bus. When the STOP condition is executed on the bus, the TWSTO bit is cleared auto- matically. In slave mode, setting the TWSTO bit can be used to recover from an error condition. This will not generate a STOP condition, but the TWI returns to a well-defined unaddressed Slave mode and releases the SCL and SDA lines to a high impedance state. • Bit 3 – TWWC: TWI Write Collision Flag The TWWC bit is set when attempting to write to the TWI Data Register – TWDR when TWINT is low. This flag is cleared by writing the TWDR Register when TWINT is high. • Bit 2 – TWEN: TWI Enable Bit The TWEN bit enables TWI operation and activates the TWI interface. When TWEN is written to one, the TWI takes control over the I/O pins connected to the SCL and SDA pins, enabling the slew-rate limiters and spike filters. If this bit is written to zero, the TWI is switched off and all TWI transmissions are terminated, regardless of any ongoing operation. • Bit 1 – Reserved Bit This bit is reserved for future use. For compatibility with future devices, this must be written to zero when TWCR is written. • Bit 0 – TWIE: TWI Interrupt Enable When this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request will be acti- vated for as long as the TWINT flag is high. 18.6.3 TWI Status Register – TWSR Bit 7 6 5 4 3 2 1 0 TWS7 TWS6 TWS5 TWS4 TWS3 – TWPS1 TWPS0 TWSR Read/Write R R R R R R R/W R/W Initial Value 1 1 1 1 1 0 0 0 • Bits 7.3 – TWS: TWI Status These 5 bits reflect the status of the TWI logic and the Two-wire Serial Bus. The different status codes are described later in this section. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should mask the pres- caler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted. • Bit 2 – Res: Reserved Bit This bit is reserved and will always read as zero. 213 7679H–CAN–08/08

• Bits 1.0 – TWPS: TWI Prescaler Bits These bits can be read and written, and control the bit rate prescaler. Table 18-2. TWI Bit Rate Prescaler TWPS1 TWPS0 Prescaler Value 0 0 1 0 1 4 1 0 16 1 1 64 To calculate bit rates, see “Bit Rate Generator Unit” on page 210. The value of TWPS1.0 is used in the equation. 18.6.4 TWI Data Register – TWDR Bit 7 6 5 4 3 2 1 0 TWD7 TWD6 TWD5 TWD4 TWD3 TWD2 TWD1 TWD0 TWDR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 1 1 1 1 1 1 1 1 In Transmit mode, TWDR contains the next byte to be transmitted. In receive mode, the TWDR contains the last byte received. It is writable while the TWI is not in the process of shifting a byte. This occurs when the TWI interrupt flag (TWINT) is set by hardware. Note that the Data Register cannot be initialized by the user before the first interrupt occurs. The data in TWDR remains sta- ble as long as TWINT is set. While data is shifted out, data on the bus is simultaneously shifted in. TWDR always contains the last byte present on the bus, except after a wake up from a sleep mode by the TWI interrupt. In this case, the contents of TWDR is undefined. In the case of a lost bus arbitration, no data is lost in the transition from Master to Slave. Handling of the ACK bit is controlled automatically by the TWI logic, the CPU cannot access the ACK bit directly. • Bits 7.0 – TWD: TWI Data Register These eight bits constitute the next data byte to be transmitted, or the latest data byte received on the TWI Serial Bus. 18.6.5 TWI (Slave) Address Register – TWAR Bit 7 6 5 4 3 2 1 0 TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE TWAR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 1 1 1 1 1 1 1 0 • Bits 7.1 – TWA: TWI (Slave) Address Register These seven bits constitute the slave address of the TWI unit. The TWAR should be loaded with the 7-bit slave address to which the TWI will respond when programmed as a slave transmitter or receiver, and not needed in the master modes. In multimaster systems, TWAR must be set in masters which can be addressed as slaves by other masters. • Bit 0 – TWGCE: TWI General Call Recognition Enable Bit AT90CAN32/64/128 214 7679H–CAN–08/08

AT90CAN32/64/128 TWGCE is used to enable recognition of the general call address (0x00). There is an associated address comparator that looks for the slave address (or general call address if enabled) in the received serial address. If a match is found, an interrupt request is generated. If set, this bit enables the recognition of a General Call given over the TWI Serial Bus. 18.7 Using the TWI The AVR TWI is byte-oriented and interrupt based. Interrupts are issued after all bus events, like reception of a byte or transmission of a START condition. Because the TWI is interrupt-based, the application software is free to carry on other operations during a TWI byte transfer. Note that the TWI Interrupt Enable (TWIE) bit in TWCR together with the Global Interrupt Enable bit in SREG allow the application to decide whether or not assertion of the TWINT flag should gener- ate an interrupt request. If the TWIE bit is cleared, the application must poll the TWINT flag in order to detect actions on the TWI bus. When the TWINT flag is asserted, the TWI has finished an operation and awaits application response. In this case, the TWI Status Register (TWSR) contains a value indicating the current state of the TWI bus. The application software can then decide how the TWI should behave in the next TWI bus cycle by manipulating the TWCR and TWDR Registers. Figure 18-10 is a simple example of how the application can interface to the TWI hardware. In this example, a master wishes to transmit a single data byte to a slave. This description is quite abstract, a more detailed explanation follows later in this section. A simple code example imple- menting the desired behavior is also presented. Figure 18-10. Interfacing the Application to the TWI in a Typical Transmission 1. Application 3. Check TWSR to see if 5. Check TWSR to see if SLA+W 7. Check TWSR to see if data n writes to TWCR START was sent. Application was sent and ACK received. was sent and ACK received. o pplicatiction ttSoraT inAnsRitmiTai.tsesion of llioonaatodd Tss WSapLCpARr+o,W pmr iaainktteion cgTo WsnutDrroeRl t,sh iaagntndals Aainnptodp lTliocWaatdCiosRn a, lpompaardokspin rdigaa tsteau crineot notht rTaotWl TsDWigRnIN,alTs Acinoptnopt lTricoWal tsCioigRnn, a lomlsaa dtkosi n sagep nspduro rSep TrtihOaatPet AA TWINT is written to one. is written to one. TWINT is written to one. TWI bus START SLA+W A Data A STOP Indicates 2. TWINT set. 4. TWINT set. 6. TWINT set. TWINT set Status code indicates Status code indicates Status code indicates TWI START condition sent SLA+W sendt, data sent, Hardware ACK received ACK received Action 1. The first step in a TWI transmission is to transmit a START condition. This is done by writing a specific value into TWCR, instructing the TWI hardware to transmit a START condition. Which value to write is described later on. However, it is important that the TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI will not start any operation as long as the TWINT bit in TWCR is set. Immediately after 215 7679H–CAN–08/08

the application has cleared TWINT, the TWI will initiate transmission of the START condition. 2. When the START condition has been transmitted, the TWINT flag in TWCR is set, and TWSR is updated with a status code indicating that the START condition has success- fully been sent. 3. The application software should now examine the value of TWSR, to make sure that the START condition was successfully transmitted. If TWSR indicates otherwise, the application software might take some special action, like calling an error routine. Assuming that the status code is as expected, the application must load SLA+W into TWDR. Remember that TWDR is used both for address and data. After TWDR has been loaded with the desired SLA+W, a specific value must be written to TWCR, instructing the TWI hardware to transmit the SLA+W present in TWDR. Which value to write is described later on. However, it is important that the TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI will not start any operation as long as the TWINT bit in TWCR is set. Immediately after the application has cleared TWINT, the TWI will initiate transmission of the address packet. 4. When the address packet has been transmitted, the TWINT flag in TWCR is set, and TWSR is updated with a status code indicating that the address packet has success- fully been sent. The status code will also reflect whether a slave acknowledged the packet or not. 5. The application software should now examine the value of TWSR, to make sure that the address packet was successfully transmitted, and that the value of the ACK bit was as expected. If TWSR indicates otherwise, the application software might take some special action, like calling an error routine. Assuming that the status code is as expected, the application must load a data packet into TWDR. Subsequently, a specific value must be written to TWCR, instructing the TWI hardware to transmit the data packet present in TWDR. Which value to write is described later on. However, it is important that the TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI will not start any operation as long as the TWINT bit in TWCR is set. Immediately after the application has cleared TWINT, the TWI will initiate transmission of the data packet. 6. When the data packet has been transmitted, the TWINT flag in TWCR is set, and TWSR is updated with a status code indicating that the data packet has successfully been sent. The status code will also reflect whether a slave acknowledged the packet or not. 7. The application software should now examine the value of TWSR, to make sure that the data packet was successfully transmitted, and that the value of the ACK bit was as expected. If TWSR indicates otherwise, the application software might take some spe- cial action, like calling an error routine. Assuming that the status code is as expected, the application must write a specific value to TWCR, instructing the TWI hardware to transmit a STOP condition. Which value to write is described later on. However, it is important that the TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI will not start any operation as long as the TWINT bit in TWCR is set. Immediately after the application has cleared TWINT, the TWI will initiate transmission of the STOP condition. Note that TWINT is NOT set after a STOP condition has been sent. Even though this example is simple, it shows the principles involved in all TWI transmissions. These can be summarized as follows: • When the TWI has finished an operation and expects application response, the TWINT flag is set. The SCL line is pulled low until TWINT is cleared. AT90CAN32/64/128 216 7679H–CAN–08/08

AT90CAN32/64/128 • When the TWINT flag is set, the user must update all TWI Registers with the value relevant for the next TWI bus cycle. As an example, TWDR must be loaded with the value to be transmitted in the next bus cycle. • After all TWI Register updates and other pending application software tasks have been completed, TWCR is written. When writing TWCR, the TWINT bit should be set. Writing a one to TWINT clears the flag. The TWI will then commence executing whatever operation was specified by the TWCR setting. In the following an assembly and C implementation of the example is given. Note that the code below assumes that several definitions have been made for example by using include-files. Assembly Code Example C Example Comments ldi r16, (1<<TWINT)| TWCR = (1<<TWINT)| (1<<TWSTA)| (1<<TWSTA)| 1 (1<<TWEN) (1<<TWEN) Send START condition sts TWCR, r16 wait1: lds r16,TWCR Wait for TWINT flag set. This indicates that 2 while (!(TWCR & (1<<TWINT))); sbrs r16,TWINT the START condition has been transmitted rjmp wait1 lds r16,TWSR andi r16, 0xF8 if ((TWSR & 0xF8)!= START) Check value of TWI Status Register. Mask cpi r16, START ERROR(); prescaler bits. If status different from START go to ERROR brne ERROR 3 ldi r16, SLA_W sts TWDR, r16 TWDR = SLA_W; Load SLA_W into TWDR Register. Clear ldi r16, (1<<TWINT)| TWCR = (1<<TWINT)|(1<<TWEN); TWINT bit in TWCR to start transmission of (1<<TWEN) address sts TWCR, r16 wait2: Wait for TWINT flag set. This indicates that lds r16,TWCR 4 while (!(TWCR & (1<<TWINT))); the SLA+W has been transmitted, and sbrs r16,TWINT ACK/NACK has been received. rjmp wait2 lds r16,TWSR andi r16, 0xF8 if ((TWSR & 0xF8)!= MT_SLA_ACK) Check value of TWI Status Register. Mask cpi r16, MT_SLA_ACK ERROR(); prescaler bits. If status different from MT_SLA_ACK go to ERROR brne ERROR 5 ldi r16, DATA sts TWDR, r16 TWDR = DATA; ldi r16, (1<<TWINT)| TWCR = (1<<TWINT)|(1<<TWEN); Load DATA into TWDR Register. Clear TWINT bit in TWCR to start transmission of data (1<<TWEN) sts TWCR, r16 wait3: while (!(TWCR & (1<<TWINT))); Wait for TWINT flag set. This indicates that lds r16,TWCR 6 the DATA has been transmitted, and sbrs r16,TWINT ACK/NACK has been received. rjmp wait3 lds r16,TWSR andi r16, 0xF8 if ((TWSR & 0xF8)!=MT_DATA_ACK) Check value of TWI Status Register. Mask ERROR(); prescaler bits. If status different from cpi r16, MT_DATA_ACK MT_DATA_ACK go to ERROR brne ERROR 7 ldi r16, (1<<TWINT)| TWCR = (1<<TWINT)| (1<<TWEN) | (1<<TWEN) | (1<<TWSTO) (1<<TWSTO); Transmit STOP condition sts TWCR, r16 217 7679H–CAN–08/08

18.8 Transmission Modes The TWI can operate in one of four major modes. These are named Master Transmitter (MT), Master Receiver (MR), Slave Transmitter (ST) and Slave Receiver (SR). Several of these modes can be used in the same application. As an example, the TWI can use MT mode to write data into a TWI EEPROM, MR mode to read the data back from the EEPROM. If other masters are present in the system, some of these might transmit data to the TWI, and then SR mode would be used. It is the application software that decides which modes are legal. The following sections describe each of these modes. Possible status codes are described along with figures detailing data transmission in each of the modes. These figures contain the following abbreviations: S: START condition Rs: REPEATED START condition R: Read bit (high level at SDA) W: Write bit (low level at SDA) A: Acknowledge bit (low level at SDA) A: Not acknowledge bit (high level at SDA) Data: 8-bit data byte P: STOP condition SLA: Slave Address In Figure 18-12 to Figure 18-18, circles are used to indicate that the TWINT flag is set. The num- bers in the circles show the status code held in TWSR, with the prescaler bits masked to zero. At these points, actions must be taken by the application to continue or complete the TWI transfer. The TWI transfer is suspended until the TWINT flag is cleared by software. When the TWINT flag is set, the status code in TWSR is used to determine the appropriate soft- ware action. For each status code, the required software action and details of the following serial transfer are given in Table 18-3 to Table 18-6. Note that the prescaler bits are masked to zero in these tables. 18.8.1 Master Transmitter Mode In the Master Transmitter mode, a number of data bytes are transmitted to a slave receiver (see Figure 18-11). In order to enter a Master mode, a START condition must be transmitted. The for- mat of the following address packet determines whether Master Transmitter or Master Receiver mode is to be entered. If SLA+W is transmitted, MT mode is entered, if SLA+R is transmitted, MR mode is entered. All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. AT90CAN32/64/128 218 7679H–CAN–08/08

AT90CAN32/64/128 Figure 18-11. Data Transfer in Master Transmitter Mode Device 1 Device 2 MASTER SLAVE Device 3 ........ Device n TRANSMITTER RECEIVER V CC R1 R2 SDA SCL A START condition is sent by writing the following value to TWCR: TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE value 1 X 1 0 X 1 0 X TWEN must be set to enable the Two-wire Serial Interface, TWSTA must be written to one to transmit a START condition and TWINT must be written to one to clear the TWINT flag. The TWI will then test the Two-wire Serial Bus and generate a START condition as soon as the bus becomes free. After a START condition has been transmitted, the TWINT flag is set by hard- ware, and the status code in TWSR will be 0x08 (See Table 18-3). In order to enter MT mode, SLA+W must be transmitted. This is done by writing SLA+W to TWDR. Thereafter the TWINT bit should be cleared (by writing it to one) to continue the transfer. This is accomplished by writing the following value to TWCR: TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE value 1 X 0 0 X 1 0 X When SLA+W have been transmitted and an acknowledgment bit has been received, TWINT is set again and a number of status codes in TWSR are possible. Possible status codes in Master mode are 0x18, 0x20, or 0x38. The appropriate action to be taken for each of these status codes is detailed in Table 18-3. When SLA+W has been successfully transmitted, a data packet should be transmitted. This is done by writing the data byte to TWDR. TWDR must only be written when TWINT is high. If not, the access will be discarded, and the Write Collision bit (TWWC) will be set in the TWCR Regis- ter. After updating TWDR, the TWINT bit should be cleared (by writing it to one) to continue the transfer. This is accomplished by writing the following value to TWCR: TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE value 1 X 0 0 X 1 0 X This scheme is repeated until the last byte has been sent and the transfer is ended by generat- ing a STOP condition or a repeated START condition. A STOP condition is generated by writing the following value to TWCR: TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE value 1 X 0 1 X 1 0 X A REPEATED START condition is generated by writing the following value to TWCR: TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE value 1 X 1 0 X 1 0 X 219 7679H–CAN–08/08

After a repeated START condition (state 0x10) the Two-wire Serial Interface can access the same slave again, or a new slave without transmitting a STOP condition. Repeated START enables the master to switch between slaves, Master Transmitter mode and Master Receiver mode without losing control of the bus. Table 18-3. Status Codes for Master Transmitter Mode Status Code Application Software Response Status of the Two-wire Serial Bus (TWSR) and Two-wire Serial Interface To TWCR Next Action Taken by TWI Hardware Parree s0caler Bits Hardware To/from TWDR STA STO TWINT TWEA 0x08 A START condition has been Load SLA+W X 0 1 X SLA+W will be transmitted; transmitted ACK or NOT ACK will be received 0x10 A repeated START condition has Load SLA+W or X 0 1 X SLA+W will be transmitted; been transmitted ACK or NOT ACK will be received Load SLA+R X 0 1 X SLA+R will be transmitted; Logic will switch to master receiver mode 0x18 SLA+W has been transmitted; Load data byte or 0 0 1 X Data byte will be transmitted and ACK or NOT ACK will be ACK has been received received No TWDR action or 1 0 1 X Repeated START will be transmitted No TWDR action or 0 1 1 X STOP condition will be transmitted and TWSTO flag will be reset No TWDR action 1 1 1 X STOP condition followed by a START condition will be transmitted and TWSTO flag will be reset 0x20 SLA+W has been transmitted; Load data byte or 0 0 1 X Data byte will be transmitted and ACK or NOT ACK will be NOT ACK has been received received No TWDR action or 1 0 1 X Repeated START will be transmitted No TWDR action or 0 1 1 X STOP condition will be transmitted and TWSTO flag will be reset No TWDR action 1 1 1 X STOP condition followed by a START condition will be transmitted and TWSTO flag will be reset 0x28 Data byte has been transmitted; Load data byte or 0 0 1 X Data byte will be transmitted and ACK or NOT ACK will be ACK has been received received No TWDR action or 1 0 1 X Repeated START will be transmitted No TWDR action or 0 1 1 X STOP condition will be transmitted and TWSTO flag will be reset No TWDR action 1 1 1 X STOP condition followed by a START condition will be transmitted and TWSTO flag will be reset 0x30 Data byte has been transmitted; Load data byte or 0 0 1 X Data byte will be transmitted and ACK or NOT ACK will be NOT ACK has been received received No TWDR action or 1 0 1 X Repeated START will be transmitted No TWDR action or 0 1 1 X STOP condition will be transmitted and TWSTO flag will be reset No TWDR action 1 1 1 X STOP condition followed by a START condition will be transmitted and TWSTO flag will be reset 0x38 Arbitration lost in SLA+W or data No TWDR action or 0 0 1 X Two-wire Serial Bus will be released and not addressed bytes slave mode entered No TWDR action 1 0 1 X A START condition will be transmitted when the bus be- comes free AT90CAN32/64/128 220 7679H–CAN–08/08

AT90CAN32/64/128 Figure 18-12. Formats and States in the Master Transmitter Mode MT Successfull S SLA W A DATA A P transmission to a slave receiver 0x08 0x18 0x28 Next transfer R SLA W started with a S repeated start condition 0x10 Not acknowledge R A P received after the slave address 0x20 MR Not acknowledge A P received after a data byte 0x30 Arbitration lost in slave A or A Other master A or A Other master address or data byte continues continues 0x38 0x38 Arbitration lost and A Other master addressed as slave continues To corresponding 0x68 0x78 0xB0 states in slave mode Any number of data bytes From master to slave DATA A and their associated acknowledge bits From slave to master This number (contained in TWSR) corresponds n to a defined state of the Two-wire Serial Bus. The prescaler bits are zero or masked to zero 221 7679H–CAN–08/08

18.8.2 Master Receiver Mode In the Master Receiver Mode, a number of data bytes are received from a slave transmitter (see Figure 18-13). In order to enter a Master mode, a START condition must be transmitted. The for- mat of the following address packet determines whether Master Transmitter or Master Receiver mode is to be entered. If SLA+W is transmitted, MT mode is entered, if SLA+R is transmitted, MR mode is entered. All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. Figure 18-13. Data Transfer in Master Receiver Mode Device 1 Device 2 MASTER SLAVE Device 3 ........ Device n RECEIVER TRANSMITTER V CC R1 R2 SDA SCL A START condition is sent by writing the following value to TWCR: TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE value 1 X 1 0 X 1 0 X TWEN must be written to one to enable the Two-wire Serial Interface, TWSTA must be written to one to transmit a START condition and TWINT must be set to clear the TWINT flag. The TWI will then test the Two-wire Serial Bus and generate a START condition as soon as the bus becomes free. After a START condition has been transmitted, the TWINT flag is set by hardware, and the status code in TWSR will be 0x08 (See Table 18-3). In order to enter MR mode, SLA+R must be transmitted. This is done by writing SLA+R to TWDR. Thereafter the TWINT bit should be cleared (by writing it to one) to continue the transfer. This is accomplished by writing the follow- ing value to TWCR: TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE value 1 X 0 0 X 1 0 X When SLA+R have been transmitted and an acknowledgment bit has been received, TWINT is set again and a number of status codes in TWSR are possible. Possible status codes in Master mode are 0x38, 0x40, or 0x48. The appropriate action to be taken for each of these status codes is detailed in Table 18-12. Received data can be read from the TWDR Register when the TWINT flag is set high by hardware. This scheme is repeated until the last byte has been received. After the last byte has been received, the MR should inform the ST by sending a NACK after the last received data byte. The transfer is ended by generating a STOP condition or a repeated START condition. A STOP condition is generated by writing the following value to TWCR: TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE value 1 X 0 1 X 1 0 X AT90CAN32/64/128 222 7679H–CAN–08/08

AT90CAN32/64/128 A REPEATED START condition is generated by writing the following value to TWCR: TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE value 1 X 1 0 X 1 0 X After a repeated START condition (state 0x10) the Two-wire Serial Interface can access the same slave again, or a new slave without transmitting a STOP condition. Repeated START enables the master to switch between slaves, Master Transmitter mode and Master Receiver mode without losing control over the bus. Figure 18-14. Formats and States in the Master Receiver Mode MR Successfull S SLA R A DATA A DATA A P reception from a slave receiver 0x08 0x40 0x50 0x58 Next transfer R SLA R started with a S repeated start condition 0x10 Not acknowledge W A P received after the slave address 0x48 MT Arbitration lost in slave A or A Other master A Other master address or data byte continues continues 0x38 0x38 Arbitration lost and A Other master addressed as slave continues To corresponding 0x68 0x78 0xB0 states in slave mode Any number of data bytes From master to slave DATA A and their associated acknowledge bits From slave to master This number (contained in TWSR) corresponds n to a defined state of the Two-wire Serial Bus. The prescaler bits are zero or masked to zero 223 7679H–CAN–08/08

Table 18-4. Status Codes for Master Receiver Mode Status Code Application Software Response Status of the Two-wire Serial Bus (TWSR) and Two-wire Serial Interface To TWCR Next Action Taken by TWI Hardware Parree s0caler Bits Hardware To/from TWDR STA STO TWINT TWEA 0x08 A START condition has been Load SLA+R X 0 1 X SLA+R will be transmitted transmitted ACK or NOT ACK will be received 0x10 A repeated START condition has Load SLA+R or X 0 1 X SLA+R will be transmitted been transmitted ACK or NOT ACK will be received Load SLA+W X 0 1 X SLA+W will be transmitted Logic will switch to master transmitter mode 0x38 Arbitration lost in SLA+R or NOT No TWDR action or 0 0 1 X Two-wire Serial Bus will be released and not addressed ACK bit slave mode will be entered No TWDR action 1 0 1 X A START condition will be transmitted when the bus becomes free 0x40 SLA+R has been transmitted; No TWDR action or 0 0 1 0 Data byte will be received and NOT ACK will be ACK has been received returned No TWDR action 0 0 1 1 Data byte will be received and ACK will be returned 0x48 SLA+R has been transmitted; No TWDR action or 1 0 1 X Repeated START will be transmitted NOT ACK has been received No TWDR action or 0 1 1 X STOP condition will be transmitted and TWSTO flag will be reset No TWDR action 1 1 1 X STOP condition followed by a START condition will be transmitted and TWSTO flag will be reset 0x50 Data byte has been received; Read data byte or 0 0 1 0 Data byte will be received and NOT ACK will be ACK has been returned returned Read data byte 0 0 1 1 Data byte will be received and ACK will be returned 0x58 Data byte has been received; Read data byte or 1 0 1 X Repeated START will be transmitted NOT ACK has been returned Read data byte or 0 1 1 X STOP condition will be transmitted and TWSTO flag will be reset Read data byte 1 1 1 X STOP condition followed by a START condition will be transmitted and TWSTO flag will be reset 18.8.3 Slave Receiver Mode In the Slave Receiver mode, a number of data bytes are received from a master transmitter (see Figure 18-15). All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. Figure 18-15. Data Transfer in Slave Receiver Mode Device 1 Device 2 SLAVE MASTER Device 3 ........ Device n RECEIVER TRANSMITTER V CC R1 R2 SDA SCL AT90CAN32/64/128 224 7679H–CAN–08/08

AT90CAN32/64/128 To initiate the Slave Receiver mode, TWAR and TWCR must be initialized as follows: TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE value Device’s Own Slave Address The upper seven bits are the address to which the Two-wire Serial Interface will respond when addressed by a master. If the LSB is set, the TWI will respond to the general call address (0x00), otherwise it will ignore the general call address. TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE value 0 1 0 0 0 1 0 X TWEN must be written to one to enable the TWI. The TWEA bit must be written to one to enable the acknowledgment of the device’s own slave address or the general call address. TWSTA and TWSTO must be written to zero. When TWAR and TWCR have been initialized, the TWI waits until it is addressed by its own slave address (or the general call address if enabled) followed by the data direction bit. If the direction bit is “0” (write), the TWI will operate in SR mode, otherwise ST mode is entered. After its own slave address and the write bit have been received, the TWINT flag is set and a valid status code can be read from TWSR. The status code is used to determine the appropriate soft- ware action. The appropriate action to be taken for each status code is detailed in Table 18-5. The slave receiver mode may also be entered if arbitration is lost while the TWI is in the master mode (see states 0x68 and 0x78). If the TWEA bit is reset during a transfer, the TWI will return a “Not Acknowledge” (“1”) to SDA after the next received data byte. This can be used to indicate that the slave is not able to receive any more bytes. While TWEA is zero, the TWI does not acknowledge its own slave address. However, the Two-wire Serial Bus is still monitored and address recognition may resume at any time by setting TWEA. This implies that the TWEA bit may be used to temporarily isolate the TWI from the Two-wire Serial Bus. In all sleep modes other than Idle mode, the clock system to the TWI is turned off. If the TWEA bit is set, the interface can still acknowledge its own slave address or the general call address by using the Two-wire Serial Bus clock as a clock source. The part will then wake up from sleep and the TWI will hold the SCL clock low during the wake up and until the TWINT flag is cleared (by writing it to one). Further data reception will be carried out as normal, with the AVR clocks running as normal. Observe that if the AVR is set up with a long start-up time, the SCL line may be held low for a long time, blocking other data transmissions. Note that the Two-wire Serial Interface Data Register – TWDR does not reflect the last byte present on the bus when waking up from these sleep modes. 225 7679H–CAN–08/08

Table 18-5. Status Codes for Slave Receiver Mode Status Code Application Software Response Status of the Two-wire Serial Bus (TWSR) and Two-wire Serial Interface Hard- To TWCR Next Action Taken by TWI Hardware Parree s0caler Bits ware To/from TWDR STA STO TWINT TWEA 0x60 Own SLA+W has been received; No TWDR action or X 0 1 0 Data byte will be received and NOT ACK will be ACK has been returned returned No TWDR action X 0 1 1 Data byte will be received and ACK will be returned 0x68 Arbitration lost in SLA+R/W as mas- No TWDR action or X 0 1 0 Data byte will be received and NOT ACK will be ter; own SLA+W has been returned received; ACK has been returned No TWDR action X 0 1 1 Data byte will be received and ACK will be returned 0x70 General call address has been No TWDR action or X 0 1 0 Data byte will be received and NOT ACK will be received; ACK has been returned returned No TWDR action X 0 1 1 Data byte will be received and ACK will be returned 0x78 Arbitration lost in SLA+R/W as mas- No TWDR action or X 0 1 0 Data byte will be received and NOT ACK will be ter; General call address has been returned received; ACK has been No TWDR action X 0 1 1 Data byte will be received and ACK will be returned returned 0x80 Previously addressed with own Read data byte or X 0 1 0 Data byte will be received and NOT ACK will be SLA+W; data has been received; returned ACK has been returned Read data byte X 0 1 1 Data byte will be received and ACK will be returned 0x88 Previously addressed with own Read data byte or 0 0 1 0 Switched to the not addressed slave mode; SLA+W; data has been received; no recognition of own SLA or GCA NOT ACK has been returned Read data byte or 0 0 1 1 Switched to the not addressed slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = “1” Read data byte or 1 0 1 0 Switched to the not addressed slave mode; no recognition of own SLA or GCA; a START condition will be transmitted when the bus becomes free Read data byte 1 0 1 1 Switched to the not addressed slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = “1”; a START condition will be transmitted when the bus becomes free 0x90 Previously addressed with Read data byte or X 0 1 0 Data byte will be received and NOT ACK will be general call; data has been re- returned ceived; ACK has been returned Read data byte X 0 1 1 Data byte will be received and ACK will be returned 0x98 Previously addressed with Read data byte or 0 0 1 0 Switched to the not addressed slave mode; general call; data has been no recognition of own SLA or GCA received; NOT ACK has been Read data byte or 0 0 1 1 Switched to the not addressed slave mode; returned own SLA will be recognized; GCA will be recognized if TWGCE = “1” Read data byte or 1 0 1 0 Switched to the not addressed slave mode; no recognition of own SLA or GCA; a START condition will be transmitted when the bus becomes free Read data byte 1 0 1 1 Switched to the not addressed slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = “1”; a START condition will be transmitted when the bus becomes free 0xA0 A STOP condition or repeated Read data byte or 0 0 1 0 Switched to the not addressed slave mode; START condition has been no recognition of own SLA or GCA received while still addressed as Read data byte or 0 0 1 1 Switched to the not addressed slave mode; slave own SLA will be recognized; GCA will be recognized if TWGCE = “1” Read data byte or 1 0 1 0 Switched to the not addressed slave mode; no recognition of own SLA or GCA; a START condition will be transmitted when the bus becomes free Read data byte 1 0 1 1 Switched to the not addressed slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = “1”; a START condition will be transmitted when the bus becomes free AT90CAN32/64/128 226 7679H–CAN–08/08

AT90CAN32/64/128 Figure 18-16. Formats and States in the Slave Receiver Mode Reception of the (cid:31) S SLA W A DATA A DATA A P or S own slave address (cid:31) and one or more (cid:31) data bytes. All are acknowledged 0x60 0x80 0x80 0xA0 Last data byte received A P or S is not acknowledged 0x88 Arbitration lost as master A and addressed as slave 0x68 Reception of the general call General Call A DATA A DATA A P or S address and one or more data bytes 0x70 0x90 0x90 0xA0 Last data byte received is A P or S not acknowledged 0x98 Arbitration lost as master and A addressed as slave by general call 0x78 Any number of data bytes From master to slave DATA A and their associated acknowledge bits From slave to master This number (contained in TWSR) corresponds n to a defined state of the Two-wire Serial Bus. The prescaler bits are zero or masked to zero 227 7679H–CAN–08/08

18.8.4 Slave Transmitter Mode In the Slave Transmitter mode, a number of data bytes are transmitted to a master receiver (see Figure 18-17). All the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. Figure 18-17. Data Transfer in Slave Transmitter Mode Device 1 Device 2 SLAVE MASTER Device 3 ........ Device n TRANSMITTER RECEIVER V CC R1 R2 SDA SCL To initiate the Slave Transmitter mode, TWAR and TWCR must be initialized as follows: TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE value Device’s Own Slave Address The upper seven bits are the address to which the Two-wire Serial Interface will respond when addressed by a master. If the LSB is set, the TWI will respond to the general call address (0x00), otherwise it will ignore the general call address. TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE value 0 1 0 0 0 1 0 X TWEN must be written to one to enable the TWI. The TWEA bit must be written to one to enable the acknowledgment of the device’s own slave address or the general call address. TWSTA and TWSTO must be written to zero. When TWAR and TWCR have been initialized, the TWI waits until it is addressed by its own slave address (or the general call address if enabled) followed by the data direction bit. If the direction bit is “1” (read), the TWI will operate in ST mode, otherwise SR mode is entered. After its own slave address and the write bit have been received, the TWINT flag is set and a valid status code can be read from TWSR. The status code is used to determine the appropriate soft- ware action. The appropriate action to be taken for each status code is detailed in Table 18-6. The Slave Transmitter mode may also be entered if arbitration is lost while the TWI is in the Master mode (see state 0xB0). If the TWEA bit is written to zero during a transfer, the TWI will transmit the last byte of the trans- fer. State 0xC0 or state 0xC8 will be entered, depending on whether the master receiver transmits a NACK or ACK after the final byte. The TWI is switched to the not addressed slave mode, and will ignore the master if it continues the transfer. Thus the master receiver receives all “1” as serial data. State 0xC8 is entered if the master demands additional data bytes (by transmitting ACK), even though the slave has transmitted the last byte (TWEA zero and expect- ing NACK from the master). AT90CAN32/64/128 228 7679H–CAN–08/08

AT90CAN32/64/128 While TWEA is zero, the TWI does not respond to its own slave address. However, the Two-wire Serial Bus is still monitored and address recognition may resume at any time by setting TWEA. This implies that the TWEA bit may be used to temporarily isolate the TWI from the Two-wire Serial Bus. In all sleep modes other than Idle mode, the clock system to the TWI is turned off. If the TWEA bit is set, the interface can still acknowledge its own slave address or the general call address by using the Two-wire Serial Bus clock as a clock source. The part will then wake up from sleep and the TWI will hold the SCL clock will low during the wake up and until the TWINT flag is cleared (by writing it to one). Further data transmission will be carried out as normal, with the AVR clocks running as normal. Observe that if the AVR is set up with a long start-up time, the SCL line may be held low for a long time, blocking other data transmissions. Note that the Two-wire Serial Interface Data Register – TWDR does not reflect the last byte present on the bus when waking up from these sleep modes. Table 18-6. Status Codes for Slave Transmitter Mode Status Code Application Software Response Status of the Two-wire Serial Bus (TWSR) and Two-wire Serial Interface Hard- To TWCR Next Action Taken by TWI Hardware Parree s0caler Bits ware To/from TWDR STA STO TWINT TWEA 0xA8 Own SLA+R has been received; Load data byte or X 0 1 0 Last data byte will be transmitted and NOT ACK should ACK has been returned be received Load data byte X 0 1 1 Data byte will be transmitted and ACK should be received 0xB0 Arbitration lost in SLA+R/W as mas- Load data byte or X 0 1 0 Last data byte will be transmitted and NOT ACK should ter; own SLA+R has been be received received; ACK has been returned Load data byte X 0 1 1 Data byte will be transmitted and ACK should be received 0xB8 Data byte in TWDR has been Load data byte or X 0 1 0 Last data byte will be transmitted and NOT ACK should transmitted; ACK has been be received received Load data byte X 0 1 1 Data byte will be transmitted and ACK should be received 0xC0 Data byte in TWDR has been No TWDR action or 0 0 1 0 Switched to the not addressed slave mode; transmitted; NOT ACK has been no recognition of own SLA or GCA received No TWDR action or 0 0 1 1 Switched to the not addressed slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = “1” No TWDR action or 1 0 1 0 Switched to the not addressed slave mode; no recognition of own SLA or GCA; a START condition will be transmitted when the bus becomes free No TWDR action 1 0 1 1 Switched to the not addressed slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = “1”; a START condition will be transmitted when the bus becomes free 0xC8 Last data byte in TWDR has been No TWDR action or 0 0 1 0 Switched to the not addressed slave mode; transmitted (TWEA = “0”); ACK has no recognition of own SLA or GCA been received No TWDR action or 0 0 1 1 Switched to the not addressed slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = “1” No TWDR action or 1 0 1 0 Switched to the not addressed slave mode; no recognition of own SLA or GCA; a START condition will be transmitted when the bus becomes free No TWDR action 1 0 1 1 Switched to the not addressed slave mode; own SLA will be recognized; GCA will be recognized if TWGCE = “1”; a START condition will be transmitted when the bus becomes free 229 7679H–CAN–08/08

Figure 18-18. Formats and States in the Slave Transmitter Mode Reception of the (cid:31) S SLA R A DATA A DATA A P or S own slave address (cid:31) and one or more data bytes 0xA8 0xB8 0xC0 Arbitration lost as master A and addressed as slave 0xB0 Last data byte transmitted. A All 1’s P or S Switched to not addressed slave (TWEA = ’0’) 0xC8 Any number of data bytes From master to slave DATA A and their associated acknowledge bits From slave to master This number (contained in TWSR) corresponds n to a defined state of the Two-wire Serial Bus. The prescaler bits are zero or masked to zero 18.8.5 Miscellaneous States There are two status codes that do not correspond to a defined TWI state, see Table 18-7. Status 0xF8 indicates that no relevant information is available because the TWINT flag is not set. This occurs between other states, and when the TWI is not involved in a serial transfer. Status 0x00 indicates that a bus error has occurred during a Two-wire Serial Bus transfer. A bus error occurs when a START or STOP condition occurs at an illegal position in the format frame. Examples of such illegal positions are during the serial transfer of an address byte, a data byte, or an acknowledge bit. When a bus error occurs, TWINT is set. To recover from a bus error, the TWSTO flag must set and TWINT must be cleared by writing a logic one to it. This causes the TWI to enter the not addressed slave mode and to clear the TWSTO flag (no other bits in TWCR are affected). The SDA and SCL lines are released, and no STOP condition is transmitted. Table 18-7. Miscellaneous States Status Code Application Software Response Status of the Two-wire Serial Bus (TWSR) and Two-wire Serial Interface To TWCR Next Action Taken by TWI Hardware Parree s0caler Bits Hardware To/from TWDR STA STO TWINT TWEA 0xF8 No relevant state information No TWDR action No TWCR action Wait or proceed current transfer available; TWINT = “0” 0x00 Bus error due to an illegal START No TWDR action 0 1 1 X Only the internal hardware is affected, no STOP condition or STOP condition is sent on the bus. In all cases, the bus is released and TWSTO is cleared. AT90CAN32/64/128 230 7679H–CAN–08/08

AT90CAN32/64/128 18.8.6 Combining Several TWI Modes In some cases, several TWI modes must be combined in order to complete the desired action. Consider for example reading data from a serial EEPROM. Typically, such a transfer involves the following steps: 1. The transfer must be initiated 2. The EEPROM must be instructed what location should be read 3. The reading must be performed 4. The transfer must be finished Note that data is transmitted both from master to slave and vice versa. The master must instruct the slave what location it wants to read, requiring the use of the MT mode. Subsequently, data must be read from the slave, implying the use of the MR mode. Thus, the transfer direction must be changed. The master must keep control of the bus during all these steps, and the steps should be carried out as an atomical operation. If this principle is violated in a multimaster sys- tem, another master can alter the data pointer in the EEPROM between steps 2 and 3, and the master will read the wrong data location. Such a change in transfer direction is accomplished by transmitting a REPEATED START between the transmission of the address byte and reception of the data. After a REPEATED START, the master keeps ownership of the bus. The following figure shows the flow in this transfer. Figure 18-19. Combining Several TWI Modes to Access a Serial EEPROM Master Transmitter Master Receiver S SLA+W A ADDRESS A Rs SLA+R A DATA A P S = START Rs = REPEATED START P = STOP Transmitted from master to slave Transmitted from slave to master 231 7679H–CAN–08/08

18.9 Multi-master Systems and Arbitration If multiple masters are connected to the same bus, transmissions may be initiated simulta- neously by one or more of them. The TWI standard ensures that such situations are handled in such a way that one of the masters will be allowed to proceed with the transfer, and that no data will be lost in the process. An example of an arbitration situation is depicted below, where two masters are trying to transmit data to a slave receiver. Figure 18-20. An Arbitration Example Device 1 Device 2 Device 3 MASTER SLAVE SLAVE ........ Device n TRANSMITTER RECEIVER RECEIVER V CC R1 R2 SDA SCL Several different scenarios may arise during arbitration, as described below: • Two or more masters are performing identical communication with the same slave. In this case, neither the slave nor any of the masters will know about the bus contention. • Two or more masters are accessing the same slave with different data or direction bit. In this case, arbitration will occur, either in the READ/WRITE bit or in the data bits. The masters trying to output a one on SDA while another master outputs a zero will lose the arbitration. Losing masters will switch to not addressed slave mode or wait until the bus is free and transmit a new START condition, depending on application software action. • Two or more masters are accessing different slaves. In this case, arbitration will occur in the SLA bits. Masters trying to output a one on SDA while another master outputs a zero will lose the arbitration. Masters losing arbitration in SLA will switch to slave mode to check if they are being addressed by the winning master. If addressed, they will switch to SR or ST mode, depending on the value of the READ/WRITE bit. If they are not being addressed, they will switch to not addressed slave mode or wait until the bus is free and transmit a new START condition, depending on application software action. AT90CAN32/64/128 232 7679H–CAN–08/08

AT90CAN32/64/128 This is summarized in Figure 18-21. Possible status values are given in circles. Figure 18-21. Possible Status Codes Caused by Arbitration START SLA Data STOP Arbitration lost in SLA Arbitration lost in Data Own No 0x38 TWI bus will be released and not addressed slave mode will be entered Address / General Call A START condition will be transmitted when the bus becomes free received Yes Write 0x68 / 0x78 Data byte will be received and NOT ACK will be returned Direction Data byte will be received and ACK will be returned Read Last data byte will be transmitted and NOT ACK should be received 0xB0 Data byte will be transmitted and ACK should be received 233 7679H–CAN–08/08

19. Controller Area Network - CAN The Controller Area Network (CAN) protocol is a real-time, serial, broadcast protocol with a very high level of security. The AT90CAN32/64/128 CAN controller is fully compatible with the CAN Specification 2.0 Part A and Part B. It delivers the features required to implement the kernel of the CAN bus protocol according to the ISO/OSI Reference Model: • The Data Link Layer - the Logical Link Control (LLC) sublayer - the Medium Access Control (MAC) sublayer • The Physical Layer - the Physical Signalling (PLS) sublayer - not supported - the Physical Medium Attach (PMA) - not supported - the Medium Dependent Interface (MDI) The CAN controller is able to handle all types of frames (Data, Remote, Error and Overload) and achieves a bitrate of 1 Mbit/s. 19.1 Features • Full Can Controller • Fully Compliant with CAN Standard rev 2.0 A and rev 2.0 B • 15 MOb (Message Object) with their own: – 11 bits of Identifier Tag (rev 2.0 A), 29 bits of Identifier Tag (rev 2.0 B) – 11 bits of Identifier Mask (rev 2.0 A), 29 bits of Identifier Mask (rev 2.0 B) – 8 Bytes Data Buffer (Static Allocation) – Tx, Rx, Frame Buffer or Automatic Reply Configuration – Time Stamping • 1 Mbit/s Maximum Transfer Rate at 8 MHz • TTC Timer • Listening Mode (for Spying or Autobaud) 19.2 CAN Protocol The CAN protocol is an international standard defined in the ISO 11898 for high speed and ISO 11519-2 for low speed. 19.2.1 Principles CAN is based on a broadcast communication mechanism. This broadcast communication is achieved by using a message oriented transmission protocol. These messages are identified by using a message identifier. Such a message identifier has to be unique within the whole network and it defines not only the content but also the priority of the message. The priority at which a message is transmitted compared to another less urgent message is specified by the identifier of each message. The priorities are laid down during system design in the form of corresponding binary values and cannot be changed dynamically. The identifier with the lowest binary number has the highest priority. Bus access conflicts are resolved by bit-wise arbitration on the identifiers involved by each node observing the bus level bit for bit. This happens in accordance with the "wired and" mechanism, AT90CAN32/64/128 234 7679H–CAN–08/08

AT90CAN32/64/128 by which the dominant state overwrites the recessive state. The competition for bus allocation is lost by all nodes with recessive transmission and dominant observation. All the "losers" automat- ically become receivers of the message with the highest priority and do not re-attempt transmission until the bus is available again. 19.2.2 Message Formats The CAN protocol supports two message frame formats, the only essential difference being in the length of the identifier. The CAN standard frame, also known as CAN 2.0 A, supports a length of 11 bits for the identifier, and the CAN extended frame, also known as CAN 2.0 B, sup- ports a length of 29 bits for the identifier. 19.2.2.1 Can Standard Frame Figure 19-1. CAN Standard Frames Data Frame Bus Idle 11-bit identifier 4-bit DLC CRC ACK Intermission Bus Idle SSOOFF ID10..0 RTR IDE r0 DLC4..0 0 - 8 bytes 15-bit CRC del. ACK del. 7 bits 3 bits (Indefinite) Interframe Arbitration Control Data CRC ACK End of Interframe Space Field Field Field Field Field Frame Space Remote Frame Bus Idle 11-bit identifier 4-bit DLC CRC ACK Intermission Bus Idle SSOOFF ID10..0 RTR IDE r0 DLC4..0 15-bit CRC del. ACK del. 7 bits 3 bits (Indefinite) Interframe Arbitration Control CRC ACK End of Interframe Space Field Field Field Field Frame Space A message in the CAN standard frame format begins with the "Start Of Frame (SOF)", this is fol- lowed by the "Arbitration field" which consist of the identifier and the "Remote Transmission Request (RTR)" bit used to distinguish between the data frame and the data request frame called remote frame. The following "Control field" contains the "IDentifier Extension (IDE)" bit and the "Data Length Code (DLC)" used to indicate the number of following data bytes in the "Data field". In a remote frame, the DLC contains the number of requested data bytes. The "Data field" that follows can hold up to 8 data bytes. The frame integrity is guaranteed by the following "Cyclic Redundant Check (CRC)" sum. The "ACKnowledge (ACK) field" compromises the ACK slot and the ACK delimiter. The bit in the ACK slot is sent as a recessive bit and is overwritten as a dominant bit by the receivers which have at this time received the data correctly. Correct mes- sages are acknowledged by the receivers regardless of the result of the acceptance test. The end of the message is indicated by "End Of Frame (EOF)". The "Intermission Frame Space (IFS)" is the minimum number of bits separating consecutive messages. If there is no following bus access by any node, the bus remains idle. 235 7679H–CAN–08/08

19.2.2.2 CAN Extended Frame Figure 19-2. CAN Extended Frames Data Frame Bus Idle 11-bit base identifier 18-bit identifier extension 4-bit DLC CRC ACK Intermission Bus Idle SSOOFF IDT28..18 SRR IDE ID17..0 RTR r1 r0 DLC4..0 0 - 8 bytes 15-bit CRC del. ACK del. 7 bits 3 bits (Indefinite) Interframe Arbitration Control Data CRC ACK End of Interframe Space Field Field Field Field Field Frame Space Remote Frame Bus Idle 11-bit base identifier 18-bit identifier extension 4-bit DLC CRC ACK Intermission Bus Idle SSOOFF IDT28..18 SRR IDE ID17..0 RTR r1 r0 DLC4..0 15-bit CRC del. ACK del. 7 bits 3 bits (Indefinite) Interframe Arbitration Control CRC ACK End of Interframe Space Field Field Field Field Frame Space A message in the CAN extended frame format is likely the same as a message in CAN standard frame format. The difference is the length of the identifier used. The identifier is made up of the existing 11-bit identifier (base identifier) and an 18-bit extension (identifier extension). The dis- tinction between CAN standard frame format and CAN extended frame format is made by using the IDE bit which is transmitted as dominant in case of a frame in CAN standard frame format, and transmitted as recessive in the other case. 19.2.2.3 Format Co-existence As the two formats have to co-exist on one bus, it is laid down which message has higher priority on the bus in the case of bus access collision with different formats and the same identifier / base identifier: The message in CAN standard frame format always has priority over the mes- sage in extended format. There are three different types of CAN modules available: – 2.0A - Considers 29 bit ID as an error – 2.0B Passive - Ignores 29 bit ID messages – 2.0B Active - Handles both 11 and 29 bit ID Messages 19.2.3 CAN Bit Timing To ensure correct sampling up to the last bit, a CAN node needs to re-synchronize throughout the entire frame. This is done at the beginning of each message with the falling edge SOF and on each recessive to dominant edge. 19.2.3.1 Bit Construction One CAN bit time is specified as four non-overlapping time segments. Each segment is con- structed from an integer multiple of the Time Quantum. The Time Quantum or TQ is the smallest discrete timing resolution used by a CAN node. AT90CAN32/64/128 236 7679H–CAN–08/08

AT90CAN32/64/128 Figure 19-3. CAN Bit Construction CAN Frame (producer) Transmission Point (producer) Nominal CAN Bit Time Time Quantum (producer) Segments SYNC_SEG PROP_SEG PHASE_SEG_1 PHASE_SEG_2 (producer) propagation delay Segments SYNC_SEG PROP_SEG PHASE_SEG_1 PHASE_SEG_2 (consumer) Sample Point 19.2.3.2 Synchronization Segment The first segment is used to synchronize the various bus nodes. On transmission, at the start of this segment, the current bit level is output. If there is a bit state change between the previous bit and the current bit, then the bus state change is expected to occur within this segment by the receiving nodes. 19.2.3.3 Propagation Time Segment This segment is used to compensate for signal delays across the network. This is necessary to compensate for signal propagation delays on the bus line and through the transceivers of the bus nodes. 19.2.3.4 Phase Segment 1 Phase Segment 1 is used to compensate for edge phase errors. This segment may be lengthened during re-synchronization. 19.2.3.5 Sample Point The sample point is the point of time at which the bus level is read and interpreted as the value of the respective bit. Its location is at the end of Phase Segment 1 (between the two Phase Segments). 19.2.3.6 Phase Segment 2 This segment is also used to compensate for edge phase errors. This segment may be shortened during re-synchronization, but the length has to be at least as long as the Information Processing Time (IPT) and may not be more than the length of Phase Segment 1. 19.2.3.7 Information Processing Time It is the time required for the logic to determine the bit level of a sampled bit. 237 7679H–CAN–08/08

The IPT begins at the sample point, is measured in TQ and is fixed at 2TQ for the Atmel CAN. Since Phase Segment 2 also begins at the sample point and is the last segment in the bit time, PS2 minimum shall not be less than the IPT. 19.2.3.8 Bit Lengthening As a result of resynchronization, Phase Segment 1 may be lengthened or Phase Segment 2 may be shortened to compensate for oscillator tolerances. If, for example, the transmitter oscilla- tor is slower than the receiver oscillator, the next falling edge used for resynchronization may be delayed. So Phase Segment 1 is lengthened in order to adjust the sample point and the end of the bit time. 19.2.3.9 Bit Shortening If, on the other hand, the transmitter oscillator is faster than the receiver one, the next falling edge used for resynchronization may be too early. So Phase Segment 2 in bit N is shortened in order to adjust the sample point for bit N+1 and the end of the bit time 19.2.3.10 Synchronization Jump Width The limit to the amount of lengthening or shortening of the Phase Segments is set by the Resyn- chronization Jump Width. This segment may not be longer than Phase Segment 2. 19.2.3.11 Programming the Sample Point Programming of the sample point allows "tuning" of the characteristics to suit the bus. Early sampling allows more Time Quanta in the Phase Segment 2 so the Synchronization Jump Width can be programmed to its maximum. This maximum capacity to shorten or lengthen the bit time decreases the sensitivity to node oscillator tolerances, so that lower cost oscillators such as ceramic resonators may be used. Late sampling allows more Time Quanta in the Propagation Time Segment which allows a poorer bus topology and maximum bus length. 19.2.3.12 Synchronization Hard synchronization occurs on the recessive-to-dominant transition of the start bit. The bit time is restarted from that edge. Re-synchronization occurs when a recessive-to-dominant edge doesn't occur within the Syn- chronization Segment in a message. 19.2.4 Arbitration The CAN protocol handles bus accesses according to the concept called “Carrier Sense Multiple Access with Arbitration on Message Priority”. During transmission, arbitration on the CAN bus can be lost to a competing device with a higher priority CAN Identifier. This arbitration concept avoids collisions of messages whose transmis- sion was started by more than one node simultaneously and makes sure the most important message is sent first without time loss. The bus access conflict is resolved during the arbitration field mostly over the identifier value. If a data frame and a remote frame with the same identifier are initiated at the same time, the data frame prevails over the remote frame (c.f. RTR bit). AT90CAN32/64/128 238 7679H–CAN–08/08

AT90CAN32/64/128 Figure 19-4. Bus Arbitration Arbitration lost node A TXCAN Node A loses the bus Node B wins the bus node B TXCAN CAN bus SSOOFFID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR IDE - - - - - - - - - 19.2.5 Errors The CAN protocol signals any errors immediately as they occur. Three error detection mecha- nisms are implemented at the message level and two at the bit level: 19.2.5.1 Error at Message Level • Cyclic Redundancy Check (CRC) The CRC safeguards the information in the frame by adding redundant check bits at the transmission end. At the receiver these bits are re-computed and tested against the received bits. If they do not agree there has been a CRC error. • Frame Check This mechanism verifies the structure of the transmitted frame by checking the bit fields against the fixed format and the frame size. Errors detected by frame checks are designated "format errors". • ACK Errors As already mentioned frames received are acknowledged by all receivers through positive acknowledgement. If no acknowledgement is received by the transmitter of the message an ACK error is indicated. 19.2.5.2 Error at Bit Level • Monitoring The ability of the transmitter to detect errors is based on the monitoring of bus signals. Each node which transmits also observes the bus level and thus detects differences between the bit sent and the bit received. This permits reliable detection of global errors and errors local to the transmitter. • Bit Stuffing The coding of the individual bits is tested at bit level. The bit representation used by CAN is "Non Return to Zero (NRZ)" coding, which guarantees maximum efficiency in bit coding. The synchronization edges are generated by means of bit stuffing. 19.2.5.3 Error Signalling If one or more errors are discovered by at least one node using the above mechanisms, the cur- rent transmission is aborted by sending an "error flag". This prevents other nodes accepting the message and thus ensures the consistency of data throughout the network. After transmission of an erroneous message that has been aborted, the sender automatically re-attempts transmission. 239 7679H–CAN–08/08

19.3 CAN Controller The CAN controller implemented into AT90CAN32/64/128 offers V2.0B Active. This full-CAN controller provides the whole hardware for convenient acceptance filtering and message management. For each message to be transmitted or received this module contains one so called message object in which all information regarding the message (e.g. identifier, data bytes etc.) are stored. During the initialization of the peripheral, the application defines which messages are to be sent and which are to be received. Only if the CAN controller receives a message whose identifier matches with one of the identifiers of the programmed (receive-) message objects the message is stored and the application is informed by interrupt. Another advantage is that incoming remote frames can be answered automatically by the full-CAN controller with the corresponding data frame. In this way, the CPU load is strongly reduced compared to a basic-CAN solution. Using full-CAN controller, high baudrates and high bus loads with many messages can be handled. Figure 19-5. CAN Controller Structure Low priority Control Status Buffer MOb i IDtag+IDmask Time Stamp MOb i MOb Scanning Control Status es Buffer MOb2 IDtag+IDmask Gen. Control Byt Time Stamp Gen. Status 0 Enable MOb LCC Internal 12 MOb2 Interrupt TxCAN = MAC Size Control BLiint eT iEmrirnogr PLS IRnxteCrAnaNl Status CAN Timer Buffer MOb1 IDtag+IDmask Time Stamp CAN Channel MOb1 Control Status Buffer MOb0 IDtag+IDmask Time Stamp MOb0 CAN Data Buffers Message Objets High priority Mailbox AT90CAN32/64/128 240 7679H–CAN–08/08

AT90CAN32/64/128 19.4 CAN Channel 19.4.1 Configuration The CAN channel can be in: • Enabled mode In this mode: – the CAN channel (internal TxCAN & RxCAN) is enabled, – the input clock is enabled. • Standby mode In standby mode: – the transmitter constantly provides a recessive level (on internal TxCAN) and the receiver is disabled, – input clock is enabled, – the registers and pages remain accessible. • Listening mode This mode is transparent for the CAN channel: – enables a hardware loop back, internal TxCAN on internal RxCAN – provides a recessive level on TXCAN output pin – does not disable RXCAN input pin – freezes TEC and REC error counters Figure 19-6. Listening Mode internal TxCAN PD5 TXCAN LISTEN internal 1 PD6 RXCAN RxCAN 0 19.4.2 Bit Timing FSM’s (Finite State Machine) of the CAN channel need to be synchronous to the time quantum. So, the input clock for bit timing is the clock used into CAN channel FSM’s. Field and segment abbreviations: • BRP: Baud Rate Prescaler. • TQ: Time Quantum (output of Baud Rate Prescaler). • SYNS: SYNchronization Segment is 1 TQ long. • PRS: PRopagation time Segment is programmable to be 1, 2, ..., 8 TQ long. • PHS1: PHase Segment 1 is programmable to be 1, 2, ..., 8 TQ long. • PHS2: PHase Segment 2 is programmable to be ≤ PHS1 and ≥ INFORMATION PROCESSING TIME. • INFORMATION PROCESSING TIME is 2 TQ. • SJW: (Re) Synchronization Jump Width is programmable between 1 and min(4, PHS1). 241 7679H–CAN–08/08

The total number of TQ in a bit time has to be programmed at least from 8 to 25. Figure 19-7. Sample and Transmission Point Bit Timing PRS (3-bit length) Sample PHS1 (3-bit length) Point CLK Fcan (Tscl) IO Prescaler BRP Time Quantum Transmission PHS2 (3-bit length) Point SJW (2-bit length) Figure 19-8. General Structure of a Bit Period 1/ CLKIO CLK IO Bit Rate Prescaler Tscl (TQ) F CAN Data one nominal bit Tsyns(5) Tprs Tphs1 (1) Tphs2 (2) Notes: 1. Phase error < 0 or or 2. Phase error > 0 Tphs1+Tsjw (3) Tphs2+Tsjw (4) 3. Phase error > 0 4. Phase error < 0 Tbit 5. Synchronization Segment: SYNS Tsyns=1xTscl (fixed) Sample Transmission Point Point 19.4.3 Baud Rate With no baud rate prescaler (BRP[5..0]=0) the sampling point comes one time quantum too early. This leads to a fail according the ISO16845 Test plan. It is necessary to lengthen the Phase Segment 1 by one time quantum and to shorten the Phase Segment 2 by one time quan- tum to compensate. The baud rate selection is made by T calculation: bit Tbit(1) = Tsyns + Tprs + Tphs1 + Tphs2 1. Tsyns = 1 x Tscl = (BRP[5..0]+ 1)/clk (= 1TQ) IO 2. Tprs = (1 to 8) x Tscl = (PRS[2..0]+ 1) x Tscl 3. Tphs1 = (1 to 8) x Tscl = (PHS1[2..0]+ 1) x Tscl 4. Tphs2 = (1 to 8) x Tscl = (PHS2[2..0](2)+ 1) x Tscl AT90CAN32/64/128 242 7679H–CAN–08/08

AT90CAN32/64/128 5. Tsjw = (1 to 4) x Tscl = (SJW[1..0]+ 1) x Tscl Notes: 1. The total number of Tscl (Time Quanta) in a bit time must be from 8 to 25. 2. PHS2[2..0] 2 is programmable to be ≤ PHS1[2..0] and ≥ 1. 19.4.4 Fault Confinement (c.f. Section 19.7 ”Error Management” on page 248). 19.4.5 Overload Frame An overload frame is sent by setting an overload request (OVRQ). After the next reception, the CAN channel sends an overload frame in accordance with the CAN specification. A status or flag is set (OVRG) as long as the overload frame is sent. Figure 19-9. Overload Frame Instructions Setting OVRQ bit Resetting OVRQ bit OVRQ bit OVRG bit RXCAN Ident "A" Cmd Message Data "A" CRC A Interframe Overload Frame Ident "B" TXCAN Overload Frame 19.5 Message Objects The MOb is a CAN frame descriptor. It contains all information to handle a CAN frame. This means that a MOb has been outlined to allow to describe a CAN message like an object. The set of MObs is the front end part of the “mailbox” where the messages to send and/or to receive are pre-defined as well as possible to decrease the work load of the software. The MObs are independent but priority is given to the lower one in case of multi matching. The operating modes are: – Disabled mode – Transmit mode – Receive mode – Automatic reply – Frame buffer receive mode 19.5.1 Number of MObs This device has 15 MObs, they are numbered from 0 up to 14 (i=14, no MOb 15). 243 7679H–CAN–08/08

19.5.2 Operating Modes There is no default mode after RESET. Every MOb has its own fields to control the operating mode. Before enabling the CAN periph- eral, each MOb must be configured (ex: disabled mode - CONMOB=00). Table 19-1. MOb Configuration MOb Configuration Reply Valid RTR Tag Operating Mode 0 0 x x Disabled x 0 Tx Data Frame 0 1 x 1 Tx Remote Frame x 0 Rx Data Frame 1 0 0 Rx Remote Frame 1 1 Rx Remote Frame then, Tx Data Frame (reply) 1 1 x x Frame Buffer Receive Mode 19.5.2.1 Disabled In this mode, the MOb is “free”. 19.5.2.2 Tx Data & Remote Frame 1. Several fields must be initialized before sending: – Identifier tag (IDT) – Identifier extension (IDE) – Remote transmission request (RTRTAG) – Data length code (DLC) – Reserved bit(s) tag (RBnTAG) – Data bytes of message (MSG) 2. The MOb is ready to send a data or a remote frame when the MOb configuration is set (CONMOB). 3. Then, the CAN channel scans all the MObs in Tx configuration, finds the MOb having the highest priority and tries to send it. 4. When the transmission is completed the TXOK flag is set (interrupt). 5. All the parameters and data are available in the MOb until a new initialization. 19.5.2.3 Rx Data & Remote Frame 1. Several fields must be initialized before receiving: – Identifier tag (IDT) – Identifier mask (IDMSK) – Identifier extension (IDE) – Identifier extension mask (IDEMSK) – Remote transmission request (RTRTAG) – Remote transmission request mask (RTRMSK) – Data length code (DLC) – Reserved bit(s) tag (RBnTAG) AT90CAN32/64/128 244 7679H–CAN–08/08

AT90CAN32/64/128 2. The MOb is ready to receive a data or a remote frame when the MOb configuration is set (CONMOB). 3. When a frame identifier is received on CAN network, the CAN channel scans all the MObs in receive mode, tries to find the MOb having the highest priority which is matching. 4. On a hit, the IDT, the IDE and the DLC of the matched MOb are updated from the incoming (frame) values. 5. Once the reception is completed, the data bytes of the received message are stored (not for remote frame) in the data buffer of the matched MOb and the RXOK flag is set (interrupt). 6. All the parameters and data are available in the MOb until a new initialization. 19.5.2.4 Automatic Reply A reply (data frame) to a remote frame can be automatically sent after reception of the expected remote frame. 1. Several fields must be initialized before receiving the remote frame: – Reply valid (RPLV) in a identical flow to the one described in Section 19.5.2.3 ”Rx Data & Remote Frame” on page 244. 2. When a remote frame matches, automatically the RTRTAG and the reply valid bit (RPLV) are reset. No flag (or interrupt) is set at this time. Since the CAN data buffer has not been used by the incoming remote frame, the MOb is then ready to be in transmit mode without any more setting. The IDT, the IDE, the other tags and the DLC of the received remote frame are used for the reply. 3. When the transmission of the reply is completed the TXOK flag is set (interrupt). 4. All the parameters and data are available in the MOb until a new initialization. 19.5.2.5 Frame Buffer Receive Mode This mode is useful to receive multi frames. The priority between MObs offers a management for these incoming frames. One set MObs (including non-consecutive MObs) is created when the MObs are set in this mode. Due to the mode setting, only one set is possible. A frame buffer completed flag (or interrupt) - BXOK - will rise only when all the MObs of the set will have received their dedicated CAN frame. 1. MObs in frame buffer receive mode need to be initialized as MObs in standard receive mode. 2. The MObs are ready to receive data (or a remote) frames when their respective config- urations are set (CONMOB). 3. When a frame identifier is received on CAN network, the CAN channel scans all the MObs in receive mode, tries to find the MOb having the highest priority which is matching. 4. On a hit, the IDT, the IDE and the DLC of the matched MOb are updated from the incoming (frame) values. 5. Once the reception is completed, the data bytes of the received message are stored (not for remote frame) in the data buffer of the matched MOb and the RXOK flag is set (interrupt). 6. When the reception in the last MOb of the set is completed, the frame buffer completed BXOK flag is set (interrupt). BXOK flag can be cleared only if all CONMOB fields of the set have been re-written before. 7. All the parameters and data are available in the MObs until a new initialization. 245 7679H–CAN–08/08

19.5.3 Acceptance Filter Upon a reception hit (i.e., a good comparison between the ID + RTR + RBn + IDE received and an IDT+ RTRTAG + RBnTAG + IDE specified while taking the comparison mask into account) the IDT + RTRTAG + RBnTAG + IDE received are updated in the MOb (written over the registers). Figure 19-10. Acceptance Filter Block Diagram internal RxDcan Rx Shift Register (internal) ID & RB RTR IDE 14(33) RB excluded = 13(31) Hit MOb[i] Write Enable 1 14(33) 13(31) - RB excluded 13(31) ID & RB RTRTAG IDE IDMSK RTRMSK IDEMSK CANIDT Registers & CANCDMOB (MOb[i]) CANIDM Registers (MOb[i]) Note: Examples: Full filtering: to accept only ID = 0x317 in part A. - ID MSK = 111 1111 1111 b - ID TAG = 011 0001 0111 b Partial filtering: to accept ID from 0x310 up to 0x317 in part A. - ID MSK = 111 1111 1000 b - ID TAG = 011 0001 0xxx b No filtering: to accept all ID from 0x000 up to 0x7FF in part A. - ID MSK = 000 0000 0000 b - ID TAG = xxx xxxx xxxx b 19.5.4 MOb Page Every MOb is mapped into a page to save place. The page number is the MOb number. This page number is set in CANPAGE register. The number 15 is reserved for factory tests. CANHPMOB register gives the MOb having the highest priority in CANSIT registers. It is format- ted to provide a direct entry for CANPAGE register. Because CANHPMOB codes CANSIT registers, it will be only updated if the corresponding enable bits (ENRX, ENTX, ENERR) are enabled (c.f. Figure 19-14). 19.5.5 CAN Data Buffers To preserve register allocation, the CAN data buffer is seen such as a FIFO (with address pointer accessible) into a MOb selection.This also allows to reduce the risks of un-controlled accesses. There is one FIFO per MOb. This FIFO is accessed into a MOb page thanks to the CAN mes- sage register. AT90CAN32/64/128 246 7679H–CAN–08/08

AT90CAN32/64/128 The data index (INDX) is the address pointer to the required data byte. The data byte can be read or write. The data index is automatically incremented after every access if the AINC* bit is reset. A roll-over is implemented, after data index=7 it is data index=0. The first byte of a CAN frame is stored at the data index=0, the second one at the data index=1, ... 19.6 CAN Timer A programmable 16-bit timer is used for message stamping and time trigger communication (TTC). Figure 19-11. CAN Timer Block Diagram clk 8 CANTCON ENFG IO clk CANTIM TTC SYNCTTC overrun OVRTIM CANTIM TXOK[i] "EOF" "SOF" RXOK[i] CANSTM[i] CANTTC 19.6.1 Prescaler An 8-bit prescaler is initialized by CANTCON register. It receives the clk frequency divided by IO 8. It provides clk frequency to the CAN Timer if the CAN controller is enabled. CANTIM Tclk = Tclk x 8 x (CANTCON [7:0] + 1) CANTIM IO 19.6.2 16-bit Timer This timer starts counting from 0x0000 when the CAN controller is enabled (ENFG bit). When the timer rolls over from 0xFFFF to 0x0000, an interrupt is generated (OVRTIM). 19.6.3 Time Triggering Two synchronization modes are implemented for TTC (TTC bit): – synchronization on Start of Frame (SYNCTTC=0), – synchronization on End of Frame (SYNCTTC=1). In TTC mode, a frame is sent once, even if an error occurs. 19.6.4 Stamping Message The capture of the timer value is done in the MOb which receives or sends the frame. All man- aged MOb are stamped, the stamping of a received (sent) frame occurs on RxOk (TXOK). 247 7679H–CAN–08/08

19.7 Error Management 19.7.1 Fault Confinement The CAN channel may be in one of the three following states: • Error active (default): The CAN channel takes part in bus communication and can send an active error frame when the CAN macro detects an error. • Error passive: The CAN channel cannot send an active error frame. It takes part in bus communication, but when an error is detected, a passive error frame is sent. Also, after a transmission, an error passive unit will wait before initiating further transmission. • Bus off: The CAN channel is not allowed to have any influence on the bus. For fault confinement, a transmit error counter (TEC) and a receive error counter (REC) are implemented. BOFF and ERRP bits give the information of the state of the CAN channel. Setting BOFF to one may generate an interrupt. Figure 19-12. Line Error Mode Reset ERRP = 0 BOFF = 0 Error Active TEC > 127 or 128 occurrences REC > 127 of 11 consecutive recessive bit TEC < 127 and ERRP = 1 REC < 127 ERRP = 0 BOFF = 0 BOFF = 1 Error Bus Passive Off TEC > 255 interrupt - BOFFIT Note: More than one REC/TEC change may apply during a given message transfer. 19.7.2 Error Types • BERR: Bit error. The bit value which is monitored is different from the bit value sent. Note: Exceptions: - Recessive bit sent monitored as dominant bit during the arbitration field and the acknowl- edge slot. - Detecting a dominant bit during the sending of an error frame. • SERR: Stuff error. Detection of more than five consecutive bit with the same polarity. • CERR: CRC error (Rx only). The receiver performs a CRC check on every destuffed received message from the start of frame up to the data field. If this checking does not match with the destuffed CRC field, an CRC error is set. • FERR: Form error. The form error results from one (or more) violations of the fixed form of the following bit fields: – CRC delimiter – acknowledgement delimiter AT90CAN32/64/128 248 7679H–CAN–08/08

AT90CAN32/64/128 – end-of-frame – error delimiter – overload delimiter • AERR: Acknowledgment error (Tx only). No detection of the dominant bit in the acknowledge slot. Figure 19-13. Error Detection Procedures in a Data Frame Bit error Arbitration Stuff error Form error Tx ACK error SOF Identifier RTR Control Message Data CRC CdRelC. ACKAdCelK. EOF inter. Rx Bit error Stuff error Form error CRC error 19.7.3 Error Setting The CAN channel can detect some errors on the CAN network. • In transmission: The error is set at MOb level. • In reception: - The identified has matched: The error is set at MOb level. - The identified has not or not yet matched: The error is set at general level. After detecting an error, the CAN channel sends an error frame on network. If the CAN channel detects an error frame on network, it sends its own error frame. 19.8 Interrupts 19.8.1 Interrupt organization The different interrupts are: • Interrupt on receive completed OK, • Interrupt on transmit completed OK, • Interrupt on error (bit error, stuff error, CRC error, form error, acknowledge error), • Interrupt on frame buffer full, • Interrupt on “Bus Off” setting, • Interrupt on overrun of CAN timer. The general interrupt enable is provided by ENIT bit and the specific interrupt enable for CAN timer overrun is provided by ENORVT bit. 249 7679H–CAN–08/08

Figure 19-14. CAN Controller Interrupt Structure CANGIE.4 CANGIE.5 CANGIE.3 ENTX ENRX ENERR CANSIT 1/2 SIT[i] CANSTMOB.6 TXOK[i] CANIE 1/2 CANSTMOB.5 RXOK[i] IEMOB[i] CANSTMOB.4 BERR[i] 0 CANSTMOB.3 SERR[i] CANGIT.7 CANSTMOB.2 CERR[i] CANIT i CANSTMOB.1 FERR[i] CANGIE.7 CANGIE.2 CANGIE.1 CANGIE.6 CANSTMOB.0 AERR[i] ENIT ENBX ENERG ENBOFF CANGIT.4 BXOK CAN IT CANGIT.3 SERG CANGIT.2 CERG CANGIT.1 FERG CANGIT.0 AERG CANGIE.0 CANGIT.6 BOFFI ENOVRT CANGIT.5 OVRTIM OVR IT 19.8.2 Interrupt Behavior When an interrupt occurs, an interrupt flag bit is set in the corresponding MOb-CANSTMOB reg- ister or in the general CANGIT register. If in the CANIE register, ENRX / ENTX / ENERR bit are set, then the corresponding MOb bit is set in the CANSITn register. To acknowledge a MOb interrupt, the corresponding bits of CANSTMOB register (RXOK, TXOK,...) must be cleared by the software application. This operation needs a read-modify-write software routine. To acknowledge a general interrupt, the corresponding bits of CANGIT register (BXOK, BOF- FIT,...) must be cleared by the software application. This operation is made writing a logical one in these interrupt flags (writing a logical zero doesn’t change the interrupt flag value). OVRTIM interrupt flag is reset as the other interrupt sources of CANGIT register and is also reset entering in its dedicated interrupt handler. When the CAN node is in transmission and detects a Form Error in its frame, a bit Error will also be raised. Consequently, two consecutive interrupts can occur, both due to the same error. When a MOb error occurs and is set in its own CANSTMOB register, no general error is set in CANGIT register. AT90CAN32/64/128 250 7679H–CAN–08/08

AT90CAN32/64/128 19.9 CAN Register Description Figure 19-15. Registers Organization AVR Registers Registers in Pages General Control General Status General Interrupt Bit Timing 1 Bit Timing 2 Bit Timing 3 Enable MOb 2 Enable MOb 1 Enable Interrupt Enable Interrupt MOb 2 Enable Interrupt MOb 1 Status Interrupt MOb 2 Status Interrupt MOb 1 CAN Timer Control CAN Timer Low CAN Timer High CAN TTC Low CAN TTC High TEC Counter REC Counter Hightest Priority MOb MOb NuPmabgere MODbata Index (i+1) Message Objects MMOOb(bi) (i-) M- MOOb Cb tSrl t&a tDuLsC MOb(i) - ID Tag 4 Page MOb MOb(i) - ID Tag 3 MOb(i) - ID Tag 2 MOb Status MOb0 - MOb Status MOb(i) - ID Tag 1 MOb Control & DLC MOb0 - MOb Ctrl & DLC MOb(i) - ID Mask 4 ID Tag 4 MOb0 - ID Tag 4 MOb(i) - ID Mask 3 ID Tag 3 MOb0 - ID Tag 3 MOb(i) - ID Mask 2 ID Tag 2 MOb0 - ID Tag 2 MOb(i) - ID Mask 1 ID Tag 1 MOb0 - ID Tag 1 MOb(i) - Time Stamp Low ID Mask 4 MOb0 - ID Mask 4 MOb(i) - Time Stamp High ID Mask 3 MOb0 - ID Mask 3 ID Mask 2 MOb0 - ID Mask 2 MOb(i) - Mess. Data - byte 0 ID Mask 1 MOb0 - ID Mask 1 Time Stamp Low MOb0 - Time Stamp Low Time Stamp High MOb0 - Time Stamp High Message Data MOb0 - Mess. Data - byte 0 8 bytes 251 7679H–CAN–08/08

19.10 General CAN Registers 19.10.1 CAN General Control Register - CANGCON Bit 7 6 5 4 3 2 1 0 ABRQ OVRQ TTC SYNTTC LISTEN TEST ENA/STB SWRES CANGCON Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 7 – ABRQ: Abort Request This is not an auto resettable bit. – 0 - no request. – 1 - abort request: a reset of CANEN1 and CANEN2 registers is done. The pending communications are immediately disabled and the on-going one will be normally terminated, setting the appropriate status flags. Note that CANCDMOB register remain unchanged. • Bit 6 – OVRQ: Overload Frame Request This is not an auto resettable bit. – 0 - no request. – 1 - overload frame request: send an overload frame after the next received frame. The overload frame can be traced observing OVFG in CANGSTA register (c.f. Figure 19-9 on page 243). • Bit 5 – TTC: Time Trigger Communication – 0 - no TTC. – 1 - TTC mode. • Bit 4 – SYNTTC: Synchronization of TTC This bit is only used in TTC mode. – 0 - the TTC timer is caught on SOF. – 1 - the TTC timer is caught on the last bit of the EOF. • Bit 3 – LISTEN: Listening Mode – 0 - no listening mode. – 1 - listening mode. • Bit 2 – TEST: Test Mode – 0 - no test mode – 1 - test mode: intend for factory testing and not for customer use. Note: CAN may malfunction if this bit is set. • Bit 1 – ENA/STB: Enable / Standby Mode Because this bit is a command and is not immediately effective, the ENFG bit in CANGSTA reg- ister gives the true state of the chosen mode. AT90CAN32/64/128 252 7679H–CAN–08/08

AT90CAN32/64/128 – 0 - standby mode: The on-going transmission (if exists) is normally terminated and the CAN channel is frozen (the CONMOB bits of every MOb do not change). The transmitter constantly provides a recessive level. In this mode, the receiver is not enabled but all the registers and mailbox remain accessible from CPU. Note: A standby mode applied during a reception may corrupt the on-going reception or set the controller in a wrong state. The controller will restart correctly from this state if a software reset (SWRES) is applied. If no reset is considered, a possible solution is to wait for a lake of a receiver busy (RXBSY) before to enter in stand-by mode. The best solution is first to apply an abort request command (ABRQ) and then wait for the lake of the receiver busy (RXBSY) before to enter in stand-by mode. In any cases, this standby mode behav- ior has no effect on the CAN bus integrity. – 1 - enable mode: The CAN channel enters in enable mode once 11 recessive bits has been read. • Bit 0 – SWRES: Software Reset Request This auto resettable bit only resets the CAN controller. – 0 - no reset – 1 - reset: this reset is “ORed” with the hardware reset. 19.10.2 CAN General Status Register - CANGSTA Bit 7 6 5 4 3 2 1 0 - OVRG - TXBSY RXBSY ENFG BOFF ERRP CANGSTA Read/Write - R - R R R R R Initial Value - 0 - 0 0 0 0 0 • Bit 7 – Reserved Bit This bit is reserved for future use. • Bit 6 – OVRG: Overload Frame Flag This flag does not generate an interrupt. – 0 - no overload frame. – 1 - overload frame: set by hardware as long as the produced overload frame is sent. • Bit 5 – Reserved Bit This bit is reserved for future use. • Bit 4 – TXBSY: Transmitter Busy This flag does not generate an interrupt. – 0 - transmitter not busy. – 1 - transmitter busy: set by hardware as long as a frame (data, remote, overload or error frame) or an ACK field is sent. Also set when an inter frame space is sent. • Bit 3 – RXBSY: Receiver Busy This flag does not generate an interrupt. – 0 - receiver not busy – 1 - receiver busy: set by hardware as long as a frame is received or monitored. • Bit 2 – ENFG: Enable Flag 253 7679H–CAN–08/08

This flag does not generate an interrupt. – 0 - CAN controller disable: because an enable/standby command is not immediately effective, this status gives the true state of the chosen mode. – 1 - CAN controller enable. • Bit 1 – BOFF: Bus Off Mode BOFF gives the information of the state of the CAN channel. Only entering in bus off mode gen- erates the BOFFIT interrupt. – 0 - no bus off mode. – 1 - bus off mode. • Bit 0 – ERRP: Error Passive Mode ERRP gives the information of the state of the CAN channel. This flag does not generate an interrupt. – 0 - no error passive mode. – 1 - error passive mode. 19.10.3 CAN General Interrupt Register - CANGIT Bit 7 6 5 4 3 2 1 0 CANIT BOFFIT OVRTIM BXOK SERG CERG FERG AERG CANGIT Read/Write R R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 7 – CANIT: General Interrupt Flag This is a read only bit. – 0 - no interrupt. – 1 - CAN interrupt: image of all the CAN controller interrupts except for OVRTIM interrupt. This bit can be used for polling method. • Bit 6 – BOFFIT: Bus Off Interrupt Flag Writing a logical one resets this interrupt flag. BOFFIT flag is only set when the CAN enters in bus off mode (coming from error passive mode). – 0 - no interrupt. – 1 - bus off interrupt when the CAN enters in bus off mode. • Bit 5 – OVRTIM: Overrun CAN Timer Writing a logical one resets this interrupt flag. Entering in CAN timer overrun interrupt handler also reset this interrupt flag – 0 - no interrupt. – 1 - CAN timer overrun interrupt: set when the CAN timer switches from 0xFFFF to 0. • Bit 4 – BXOK: Frame Buffer Receive Interrupt Writing a logical one resets this interrupt flag. BXOK flag can be cleared only if all CONMOB fields of the MOb’s of the buffer have been re-written before. – 0 - no interrupt. AT90CAN32/64/128 254 7679H–CAN–08/08

AT90CAN32/64/128 – 1 - burst receive interrupt: set when the frame buffer receive is completed. • Bit 3 – SERG: Stuff Error General Writing a logical one resets this interrupt flag. – 0 - no interrupt. – 1 - stuff error interrupt: detection of more than 5 consecutive bits with the same polarity. • Bit 2 – CERG: CRC Error General Writing a logical one resets this interrupt flag. – 0 - no interrupt. – 1 - CRC error interrupt: the CRC check on destuffed message does not fit with the CRC field. • Bit 1 – FERG: Form Error General Writing a logical one resets this interrupt flag. – 0 - no interrupt. – 1 - form error interrupt: one or more violations of the fixed form in the CRC delimiter, acknowledgment delimiter or EOF. • Bit 0 – AERG: Acknowledgment Error General Writing a logical one resets this interrupt flag. – 0 - no interrupt. – 1 - acknowledgment error interrupt: no detection of the dominant bit in acknowledge slot. 19.10.4 CAN General Interrupt Enable Register - CANGIE Bit 7 6 5 4 3 2 1 0 ENIT ENBOFF ENRX ENTX ENERR ENBX ENERG ENOVRT CANGIE Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 7 – ENIT: Enable all Interrupts (Except for CAN Timer Overrun Interrupt) – 0 - interrupt disabled. – 1- CANIT interrupt enabled. • Bit 6 – ENBOFF: Enable Bus Off Interrupt – 0 - interrupt disabled. – 1- bus off interrupt enabled. • Bit 5 – ENRX: Enable Receive Interrupt – 0 - interrupt disabled. – 1- receive interrupt enabled. • Bit 4 – ENTX: Enable Transmit Interrupt – 0 - interrupt disabled. 255 7679H–CAN–08/08

– 1- transmit interrupt enabled. • Bit 3 – ENERR: Enable MOb Errors Interrupt – 0 - interrupt disabled. – 1- MOb errors interrupt enabled. • Bit 2 – ENBX: Enable Frame Buffer Interrupt – 0 - interrupt disabled. – 1- frame buffer interrupt enabled. • Bit 1 – ENERG: Enable General Errors Interrupt – 0 - interrupt disabled. – 1- general errors interrupt enabled. • Bit 0 – ENOVRT: Enable CAN Timer Overrun Interrupt – 0 - interrupt disabled. – 1- CAN timer interrupt overrun enabled. 19.10.5 CAN Enable MOb Registers - CANEN2 and CANEN1 Bit 7 6 5 4 3 2 1 0 ENMOB7 ENMOB6 ENMOB5 ENMOB4 ENMOB3 ENMOB2 ENMOB1 ENMOB0 CANEN2 - ENMOB14 ENMOB13 ENMOB12 ENMOB11 ENMOB10 ENMOB9 ENMOB8 CANEN1 Bit 15 14 13 12 11 10 9 8 Read/Write R R R R R R R R Initial Value 0 0 0 0 0 0 0 0 Read/Write - R R R R R R R Initial Value - 0 0 0 0 0 0 0 • Bits 14:0 - ENMOB14:0: Enable MOb This bit provides the availability of the MOb. It is set to one when the MOb is enabled (i.e. CONMOB1:0 of CANCDMOB register). Once TXOK or RXOK is set to one (TXOK for automatic reply), the corresponding ENMOB is reset. ENMOB is also set to zero configuring the MOb in disabled mode, applying abortion or standby mode. – 0 - message object disabled: MOb available for a new transmission or reception. – 1 - message object enabled: MOb in use. • Bit 15 – Reserved Bit This bit is reserved for future use. AT90CAN32/64/128 256 7679H–CAN–08/08

AT90CAN32/64/128 19.10.6 CAN Enable Interrupt MOb Registers - CANIE2 and CANIE1 Bit 7 6 5 4 3 2 1 0 IEMOB7 IEMOB6 IEMOB5 IEMOB4 IEMOB3 IEMOB2 IEMOB1 IEMOB0 CANIE2 - IEMOB14 IEMOB13 IEMOB12 IEMOB11 IEMOB10 IEMOB9 IEMOB8 CANIE1 Bit 15 14 13 12 11 10 9 8 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Read/Write - R/W R/W R/W R/W R/W R/W R/W Initial Value - 0 0 0 0 0 0 0 • Bits 14:0 - IEMOB14:0: Interrupt Enable by MOb – 0 - interrupt disabled. – 1 - MOb interrupt enabled Note: Example: CANIE2 = 0000 1100 : enable of interrupts on MOb 2 & 3. b • Bit 15 – Reserved Bit This bit is reserved for future use. For compatibility with future devices, it must be written to zero when CANIE1 is written. 19.10.7 CAN Status Interrupt MOb Registers - CANSIT2 and CANSIT1 Bit 7 6 5 4 3 2 1 0 SIT7 SIT6 SIT5 SIT4 SIT3 SIT2 SIT1 SIT0 CANSIT2 - SIT14 SIT13 SIT12 SIT11 SIT10 SIT9 SIT8 CANSIT1 Bit 15 14 13 12 11 10 9 8 Read/Write R R R R R R R R Initial Value 0 0 0 0 0 0 0 0 Read/Write - R R R R R R R Initial Value - 0 0 0 0 0 0 0 • Bits 14:0 - SIT14:0: Status of Interrupt by MOb – 0 - no interrupt. – 1- MOb interrupt. Note: Example: CANSIT2 = 0010 0001 : MOb 0 & 5 interrupts. b • Bit 15 – Reserved Bit This bit is reserved for future use. 19.10.8 CAN Bit Timing Register 1 - CANBT1 Bit 7 6 5 4 3 2 1 0 - BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 - CANBT1 Read/Write - R/W R/W R/W R/W R/W R/W - Initial Value - 0 0 0 0 0 0 - • Bit 7– Reserved Bit This bit is reserved for future use. For compatibility with future devices, it must be written to zero when CANBT1 is written. • Bit 6:1 – BRP5:0: Baud Rate Prescaler 257 7679H–CAN–08/08

The period of the CAN controller system clock Tscl is programmable and determines the individ- ual bit timing. BRP[5:0] + 1 Tscl = clk frequency IO If BRP[5..0]=0, see Section 19.4.3 ”Baud Rate” on page 242 and Section • ”Bit 0 – SMP: Sample Point(s)” on page 259. • Bit 0 – Reserved Bit This bit is reserved for future use. For compatibility with future devices, it must be written to zero when CANBT1 is written. 19.10.9 CAN Bit Timing Register 2 - CANBT2 Bit 7 6 5 4 3 2 1 0 - SJW1 SJW0 - PRS2 PRS1 PRS0 - CANBT2 Read/Write - R/W R/W - R/W R/W R/W - Initial Value - 0 0 - 0 0 0 - • Bit 7– Reserved Bit This bit is reserved for future use. For compatibility with future devices, it must be written to zero when CANBT2 is written. • Bit 6:5 – SJW1:0: Re-Synchronization Jump Width To compensate for phase shifts between clock oscillators of different bus controllers, the control- ler must re-synchronize on any relevant signal edge of the current transmission. The synchronization jump width defines the maximum number of clock cycles. A bit period may be shortened or lengthened by a re-synchronization. Tsjw = Tscl x (SJW [1:0] +1) • Bit 4 – Reserved Bit This bit is reserved for future use. For compatibility with future devices, it must be written to zero when CANBT2 is written. • Bit 3:1 – PRS2:0: Propagation Time Segment This part of the bit time is used to compensate for the physical delay times within the network. It is twice the sum of the signal propagation time on the bus line, the input comparator delay and the output driver delay. Tprs = Tscl x (PRS [2:0] + 1) • Bit 0 – Reserved Bit This bit is reserved for future use. For compatibility with future devices, it must be written to zero when CANBT2 is written. 19.10.10 CAN Bit Timing Register 3 - CANBT3 Bit 7 6 5 4 3 2 1 0 - PHS22 PHS21 PHS20 PHS12 PHS11 PHS10 SMP CANBT3 Read/Write - R/W R/W R/W R/W R/W R/W R/W Initial Value - 0 0 0 0 0 0 0 AT90CAN32/64/128 258 7679H–CAN–08/08

AT90CAN32/64/128 • Bit 7– Reserved Bit This bit is reserved for future use. For compatibility with future devices, it must be written to zero when CANBT3 is written. • Bit 6:4 – PHS22:0: Phase Segment 2 This phase is used to compensate for phase edge errors. This segment may be shortened by the re-synchronization jump width. PHS2[2..0] shall be ≥1 and ≤PHS1[2..0] (c.f. Section 19.2.3 ”CAN Bit Timing” on page 236 and Section 19.4.3 ”Baud Rate” on page 242). Tphs2 = Tscl x (PHS2 [2:0] + 1) • Bit 3:1 – PHS12:0: Phase Segment 1 This phase is used to compensate for phase edge errors. This segment may be lengthened by the re-synchronization jump width. Tphs1 = Tscl x (PHS1 [2:0] + 1) • Bit 0 – SMP: Sample Point(s) This option allows to filter possible noise on TxCAN input pin. – 0 - the sampling will occur once at the user configured sampling point - SP. – 1 - with three-point sampling configuration the first sampling will occur two Tclk IO clocks before the user configured sampling point - SP, again at one Tclk clock IO before SP and finally at SP. Then the bit level will be determined by a majority vote of the three samples. ‘SMP=1’ configuration is not compatible with ‘BRP[5:0]=0’ because TQ = Tclk . IO If BRP = 0, SMP must be cleared. 19.10.11 CAN Timer Control Register - CANTCON Bit 7 6 5 4 3 2 1 0 TPRSC7 TPRSC6 TPRSC5 TPRSC4 TPRSC3 TPRSC2 TRPSC1 TPRSC0 CANTCON Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 7:0 – TPRSC7:0: CAN Timer Prescaler Prescaler for the CAN timer upper counter range 0 to 255. It provides the clock to the CAN timer if the CAN controller is enabled. Tclk = Tclk x 8 x (CANTCON [7:0] + 1) CANTIM IO 19.10.12 CAN Timer Registers - CANTIML and CANTIMH Bit 7 6 5 4 3 2 1 0 CANTIM7 CANTIM6 CANTIM5 CANTIM4 CANTIM3 CANTIM2 CANTIM1 CANTIM0 CANTIML CANTIM15 CANTIM14 CANTIM13 CANTIM12 CANTIM11 CANTIM10 CANTIM9 CANTIM8 CANTIMH Bit 15 14 13 12 11 10 9 8 Read/Write R R R R R R R R Initial Value 0 0 0 0 0 0 0 0 • Bits 15:0 - CANTIM15:0: CAN Timer Count CAN timer counter range 0 to 65,535. 259 7679H–CAN–08/08

19.10.13 CAN TTC Timer Registers - CANTTCL and CANTTCH Bit 7 6 5 4 3 2 1 0 TIMTTC7 TIMTTC6 TIMTTC5 TIMTTC4 TIMTTC3 TIMTTC2 TIMTTC1 TIMTTC0 CANTTCL TIMTTC15 TIMTTC14 TIMTTC13 TIMTTC12 TIMTTC11 TIMTTC10 TIMTTC9 TIMTTC8 CANTTCH Bit 15 14 13 12 11 10 9 8 Read/Write R R R R R R R R Initial Value 0 0 0 0 0 0 0 0 • Bits 15:0 - TIMTTC15:0: TTC Timer Count CAN TTC timer counter range 0 to 65,535. 19.10.14 CAN Transmit Error Counter Register - CANTEC Bit 7 6 5 4 3 2 1 0 TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 CANTEC Read/Write R R R R R R R R Initial Value 0 0 0 0 0 0 0 0 • Bit 7:0 – TEC7:0: Transmit Error Count CAN transmit error counter range 0 to 255. 19.10.15 CAN Receive Error Counter Register - CANREC Bit 7 6 5 4 3 2 1 0 REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 CANREC Read/Write R R R R R R R R Initial Value 0 0 0 0 0 0 0 0 • Bit 7:0 – REC7:0: Receive Error Count CAN receive error counter range 0 to 255. 19.10.16 CAN Highest Priority MOb Register - CANHPMOB Bit 7 6 5 4 3 2 1 0 HPMOB3 HPMOB2 HPMOB1 HPMOB0 CGP3 CGP2 CGP1 CGP0 CANHPMOB Read/Write R R R R R/W R/W R/W R/W Initial Value 1 1 1 1 0 0 0 0 • Bit 7:4 – HPMOB3:0: Highest Priority MOb Number MOb having the highest priority in CANSIT registers. If CANSIT = 0 (no MOb), the return value is 0xF. Note: Do not confuse “MOb priority” and “Message ID priority”.See “Message Objects” on page 243. • Bit 3:0 – CGP3:0: CAN General Purpose Bits These bits can be pre-programmed to match with the wanted configuration of the CANPAGE register (i.e., AINC and INDX2:0 setting). 19.10.17 CAN Page MOb Register - CANPAGE Bit 7 6 5 4 3 2 1 0 MOBNB3 MOBNB2 MOBNB1 MOBNB0 AINC INDX2 INDX1 INDX0 CANPAGE Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 AT90CAN32/64/128 260 7679H–CAN–08/08

AT90CAN32/64/128 • Bit 7:4 – MOBNB3:0: MOb Number Selection of the MOb number, the available numbers are from 0 to 14. • Bit 3 – AINC: Auto Increment of the FIFO CAN Data Buffer Index (Active Low) – 0 - auto increment of the index (default value). – 1- no auto increment of the index. • Bit 2:0 – INDX2:0: FIFO CAN Data Buffer Index Byte location of the CAN data byte into the FIFO for the defined MOb. 19.11 MOb Registers The MOb registers has no initial (default) value after RESET. 19.11.1 CAN MOb Status Register - CANSTMOB Bit 7 6 5 4 3 2 1 0 DLCW TXOK RXOK BERR SERR CERR FERR AERR CANSTMOB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value - - - - - - - - • Bit 7 – DLCW: Data Length Code Warning The incoming message does not have the DLC expected. Whatever the frame type, the DLC field of the CANCDMOB register is updated by the received DLC. • Bit 6 – TXOK: Transmit OK This flag can generate an interrupt. It must be cleared using a read-modify-write software routine on the whole CANSTMOB register. The communication enabled by transmission is completed. TxOK rises at the end of EOF field and then, the MOb is disabled (the corresponding ENMOB-bit of CANEN registers is cleared). When the controller is ready to send a frame, if two or more message objects are enabled as producers, the lower MOb index is supplied first. • Bit 5 – RXOK: Receive OK This flag can generate an interrupt. It must be cleared using a read-modify-write software routine on the whole CANSTMOB register. The communication enabled by reception is completed. RxOK rises at the end of the 6th bit of EOF field and then, the MOb is disabled (the correspond- ing ENMOB-bit of CANEN registers is cleared). In case of two or more message object reception hits, the lower MOb index is updated first. • Bit 4 – BERR: Bit Error (Only in Transmission) This flag can generate an interrupt. It must be cleared using a read-modify-write software routine on the whole CANSTMOB register. The bit value monitored is different from the bit value sent. Exceptions: the monitored recessive bit sent as a dominant bit during the arbitration field and the acknowledge slot detecting a dominant bit during the sending of an error frame. 261 7679H–CAN–08/08

The rising of this flag does not disable the MOb (the corresponding ENMOB-bit of CANEN regis- ters is not cleared). The next matching frame will update the BERR flag. • Bit 3 – SERR: Stuff Error This flag can generate an interrupt. It must be cleared using a read-modify-write software routine on the whole CANSTMOB register. Detection of more than five consecutive bits with the same polarity. This flag can generate an interrupt. The rising of this flag does not disable the MOb (the corresponding ENMOB-bit of CANEN regis- ters is not cleared). The next matching frame will update the SERR flag. • Bit 2 – CERR: CRC Error This flag can generate an interrupt. It must be cleared using a read-modify-write software routine on the whole CANSTMOB register. The receiver performs a CRC check on every de-stuffed received message from the start of frame up to the data field. If this checking does not match with the de-stuffed CRC field, a CRC error is set. The rising of this flag does not disable the MOb (the corresponding ENMOB-bit of CANEN regis- ters is not cleared). The next matching frame will update the CERR flag. • Bit 1 – FERR: Form Error This flag can generate an interrupt. It must be cleared using a read-modify-write software routine on the whole CANSTMOB register. The form error results from one or more violations of the fixed form in the following bit fields: • CRC delimiter. • Acknowledgment delimiter. • EOF The rising of this flag does not disable the MOb (the corresponding ENMOB-bit of CANEN regis- ters is not cleared). The next matching frame will update the FERR flag. • Bit 0 – AERR: Acknowledgment Error This flag can generate an interrupt. It must be cleared using a read-modify-write software routine on the whole CANSTMOB register. No detection of the dominant bit in the acknowledge slot. The rising of this flag does not disable the MOb (the corresponding ENMOB-bit of CANEN regis- ters is not cleared). The next matching frame will update the AERR flag. 19.11.2 CAN MOb Control and DLC Register - CANCDMOB Bit 7 6 5 4 3 2 1 0 CONMOB1 CONMOB0 RPLV IDE DLC3 DLC2 DLC1 DLC0 CANCDMOB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value - - - - - - - - • Bit 7:6 – CONMOB1:0: Configuration of Message Object These bits set the communication to be performed (no initial value after RESET). AT90CAN32/64/128 262 7679H–CAN–08/08

AT90CAN32/64/128 – 00 - disable. – 01 - enable transmission. – 10 - enable reception. – 11 - enable frame buffer reception These bits are not cleared once the communication is performed. The user must re-write the configuration to enable a new communication. • This operation is necessary to be able to reset the BXOK flag. • This operation also set the corresponding bit in the CANEN registers. • Bit 5 – RPLV: Reply Valid Used in the automatic reply mode after receiving a remote frame. – 0 - reply not ready. – 1 - reply ready and valid. • Bit 4 – IDE: Identifier Extension IDE bit of the remote or data frame to send. This bit is updated with the corresponding value of the remote or data frame received. – 0 - CAN standard rev 2.0 A (identifiers length = 11 bits). – 1 - CAN standard rev 2.0 B (identifiers length = 29 bits). • Bit 3:0 – DLC3:0: Data Length Code Number of Bytes in the data field of the message. DLC field of the remote or data frame to send. The range of DLC is from 0 up to 8. If DLC field >8 then effective DLC=8. This field is updated with the corresponding value of the remote or data frame received. If the expected DLC differs from the incoming DLC, a DLC warning appears in the CANSTMOB register. 19.11.3 CAN Identifier Tag Registers - CANIDT1, CANIDT2, CANIDT3, and CANIDT4 V2.0 part A Bit 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0 - - - - - RTRTAG - RB0TAG CANIDT4 - - - - - - - - CANIDT3 IDT2 IDT1 IDT0 - - - - - CANIDT2 IDT10 IDT9 IDT8 IDT7 IDT6 IDT5 IDT4 IDT3 CANIDT1 Bit 31/23 30/22 29/21 28/20 27/19 26/18 25/17 24/16 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value - - - - - - - - V2.0 part B Bit 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0 IDT4 IDT3 IDT2 IDT1 IDT0 RTRTAG RB1TAG RB0TAG CANIDT4 IDT12 IDT11 IDT10 IDT9 IDT8 IDT7 IDT6 IDT5 CANIDT3 IDT20 IDT19 IDT18 IDT17 IDT16 IDT15 IDT14 IDT13 CANIDT2 IDT28 IDT27 IDT26 IDT25 IDT24 IDT23 IDT22 IDT21 CANIDT1 263 7679H–CAN–08/08

Bit 31/23 30/22 29/21 28/20 27/19 26/18 25/17 24/16 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value - - - - - - - - V2.0 part A • Bit 31:21 – IDT10:0: Identifier Tag Identifier field of the remote or data frame to send. This field is updated with the corresponding value of the remote or data frame received. • Bit 20:3 – Reserved Bits These bits are reserved for future use. For compatibility with future devices, they must be written to zero when CANIDTn are written. When a remote or data frame is received, these bits do not operate in the comparison but they are updated with un-predicted values. • Bit 2 – RTRTAG: Remote Transmission Request Tag RTR bit of the remote or data frame to send. This tag is updated with the corresponding value of the remote or data frame received. In case of Automatic Reply mode, this bit is automatically reset before sending the response. • Bit 1 – Reserved Bit This bit is reserved for future use. For compatibility with future devices, it must be written to zero when CANIDTn are written. When a remote or data frame is received, this bit does not operate in the comparison but it is updated with un-predicted values. • Bit 0 – RB0TAG: Reserved Bit 0 Tag RB0 bit of the remote or data frame to send. This tag is updated with the corresponding value of the remote or data frame received. V2.0 part B • Bit 31:3 – IDT28:0: Identifier Tag Identifier field of the remote or data frame to send. This field is updated with the corresponding value of the remote or data frame received. • Bit 2 – RTRTAG: Remote Transmission Request Tag RTR bit of the remote or data frame to send. This tag is updated with the corresponding value of the remote or data frame received. In case of Automatic Reply mode, this bit is automatically reset before sending the response. • Bit 1 – RB1TAG: Reserved Bit 1 Tag RB1 bit of the remote or data frame to send. This tag is updated with the corresponding value of the remote or data frame received. AT90CAN32/64/128 264 7679H–CAN–08/08

AT90CAN32/64/128 • Bit 0 – RB0TAG: Reserved Bit 0 Tag RB0 bit of the remote or data frame to send. This tag is updated with the corresponding value of the remote or data frame received. 19.11.4 CAN Identifier Mask Registers - CANIDM1, CANIDM2, CANIDM3, and CANIDM4 V2.0 part A Bit 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0 - - - - - RTRMSK - IDEMSK CANIDM4 - - - - - - - - CANIDM3 IDMSK2 IDMSK1 IDMSK0 - - - - - CANIDM2 IDMSK10 IDMSK9 IDMSK8 IDMSK7 IDMSK6 IDMSK5 IDMSK4 IDMSK3 CANIDM1 Bit 31/23 30/22 29/21 28/20 27/19 26/18 25/17 24/16 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value - - - - - - - - V2.0 part B Bit 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0 IDMSK4 IDMSK3 IDMSK2 IDMSK1 IDMSK0 RTRMSK - IDEMSK CANIDM4 IDMSK12 IDMSK11 IDMSK10 IDMSK9 IDMSK8 IDMSK7 IDMSK6 IDMSK5 CANIDM3 IDMSK20 IDMSK19 IDMSK18 IDMSK17 IDMSK16 IDMSK15 IDMSK14 IDMSK13 CANIDM2 IDMSK28 IDMSK27 IDMSK26 IDMSK25 IDMSK24 IDMSK23 IDMSK22 IDMSK21 CANIDM1 Bit 31/23 30/22 29/21 28/20 27/19 26/18 25/17 24/16 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value - - - - - - - - V2.0 part A • Bit 31:21 – IDMSK10:0: Identifier Mask – 0 - comparison true forced - See “Acceptance Filter” on page 246. – 1 - bit comparison enabled - See “Acceptance Filter” on page 246. • Bit 20:3 – Reserved Bits These bits are reserved for future use. For compatibility with future devices, they must be written to zero when CANIDMn are written. • Bit 2 – RTRMSK: Remote Transmission Request Mask – 0 - comparison true forced. – 1 - bit comparison enabled. • Bit 1 – Reserved Bit This bit is reserved for future use. For compatibility with future devices, it must be written to zero when CANIDTn are written. • Bit 0 – IDEMSK: Identifier Extension Mask – 0 - comparison true forced. – 1 - bit comparison enabled. V2.0 part B 265 7679H–CAN–08/08

• Bit 31:3 – IDMSK28:0: Identifier Mask – 0 - comparison true forced - See “Acceptance Filter” on page 246. – 1 - bit comparison enabled - See “Acceptance Filter” on page 246. • Bit 2 – RTRMSK: Remote Transmission Request Mask – 0 - comparison true forced – 1 - bit comparison enabled. • Bit 1 – Reserved Bit Writing zero in this bit is recommended. • Bit 0 – IDEMSK: Identifier Extension Mask – 0 - comparison true forced – 1 - bit comparison enabled. 19.11.5 CAN Time Stamp Registers - CANSTML and CANSTMH Bit 7 6 5 4 3 2 1 0 TIMSTM7 TIMSTM6 TIMSTM5 TIMSTM4 TIMSTM3 TIMSTM2 TIMSTM1 TIMSTM0 CANSTML TIMSTM15TIMSTM14TIMSTM13TIMSTM12TIMSTM11TIMSTM10 TIMSTM9 TIMSTM8 CANSTMH Bit 15 14 13 12 11 10 9 8 Read/Write R R R R R R R R Initial Value - - - - - - - - • Bits 15:0 - TIMSTM15:0: Time Stamp Count CAN time stamp counter range 0 to 65,535. 19.11.6 CAN Data Message Register - CANMSG Bit 7 6 5 4 3 2 1 0 MSG 7 MSG 6 MSG 5 MSG 4 MSG 3 MSG 2 MSG 1 MSG 0 CANMSG Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value - - - - - - - - • Bit 7:0 – MSG7:0: Message Data This register contains the CAN data byte pointed at the page MOb register. After writing in the page MOb register, this byte is equal to the specified message location of the pre-defined identifier + index. If auto-incrementation is used, at the end of the data register writ- ing or reading cycle, the index is auto-incremented. The range of the counting is 8 with no end of loop (0, 1,..., 7, 0,...). 19.12 Examples of CAN Baud Rate Setting The CAN bus requires very accurate timing especially for high baud rates. It is recommended to use only an external crystal for CAN operations. (Refer to “Bit Timing” on page 241 and “Baud Rate” on page 242 for timing description and page 257 to page 258 for “CAN Bit Timing Registers”). AT90CAN32/64/128 266 7679H–CAN–08/08

AT90CAN32/64/128 Table 19-2. Examples of CAN Baud Rate Settings for Commonly Frequencies Description Segments Registers CAN fclk Baudrate Sampling TQ Tbit Tprs Tph1 Tph2 Tsjw io (MHz) (Kbps) Point (µs) (TQ) (TQ) (TQ) (TQ) (TQ) CANBT1 CANBT2 CANBT3 69 % (1) 0.0625 16 7 4 4 1 0x00 0x0C 0x36 (2) 1000 75 % 0.125 8 3 2 2 1 0x02 0x04 0x13 0.125 16 7 4 4 1 0x02 0x0C 0x37 500 75 % 0.250 8 3 2 2 1 0x06 0x04 0x13 0.250 16 7 4 4 1 0x06 0x0C 0x37 250 75 % 0.500 8 3 2 2 1 0x0E 0x04 0x13 16.000 0.3125 16 7 4 4 1 0x08 0x0C 0x37 200 75 % 0.625 8 3 2 2 1 0x12 0x04 0x13 0.500 16 7 4 4 1 0x0E 0x0C 0x37 125 75 % 1.000 8 3 2 2 1 0x1E 0x04 0x13 0.625 16 7 4 4 1 0x12 0x0C 0x37 100 75 % 1.250 8 3 2 2 1 0x26 0x04 0x13 0.083333 12 5 3 3 1 0x00 0x08 0x24 (2) 1000 67 % (1) x - - - n o d a t a - - - 0.166666 12 5 3 3 1 0x02 0x08 0x25 500 75 % 0.250 8 3 2 2 1 0x04 0x04 0x13 0.250 16 7 4 4 1 0x04 0x0C 0x37 250 75 % 0.500 8 3 2 2 1 0x0A 0x04 0x13 12.000 0.250 20 8 6 5 1 0x04 0x0E 0x4B 200 75 % 0.416666 12 5 3 3 1 0x08 0x08 0x25 0.500 16 7 4 4 1 0x0A 0x0C 0x37 125 75 % 1.000 8 3 2 2 1 0x16 0x04 0x13 0.500 20 8 6 5 1 0x0A 0x0E 0x4B 100 75 % 0.833333 12 5 3 3 1 0x12 0x08 0x25 267 7679H–CAN–08/08

Table 19-2. Examples of CAN Baud Rate Settings for Commonly Frequencies (Continued) Description Segments Registers CAN fclk Baudrate Sampling TQ Tbit Tprs Tph1 Tph2 Tsjw io (MHz) (Kbps) Point (µs) (TQ) (TQ) (TQ) (TQ) (TQ) CANBT1 CANBT2 CANBT3 x - - - n o d a t a - - - 1000 63 % (1) 0.125 8 3 2 2 1 0x00 0x04 0x12 (2) 69 % (1) 0.125 16 7 4 4 1 0x00 0x0C 0x36 (2) 500 75 % 0.250 8 3 2 2 1 0x02 0x04 0x13 0.250 16 7 4 4 1 0x02 0x0C 0x37 250 75 % 0.500 8 3 2 2 1 0x06 0x04 0x13 8.000 0.250 20 8 6 5 1 0x02 0x0E 0x4B 200 75 % 0.625 8 3 2 2 1 0x08 0x04 0x13 0.500 16 7 4 4 1 0x06 0x0C 0x37 125 75 % 1.000 8 3 2 2 1 0x0E 0x04 0x13 0.625 16 7 4 4 1 0x08 0x0C 0x37 100 75 % 1.250 8 3 2 2 1 0x12 0x04 0x13 1000 - - - n o t a p p l i c a b l e - - - 0.166666 12 5 3 3 1 0x00 0x08 0x24 (2) 500 67 % (1) x - - - n o d a t a - - - 0.333333 12 5 3 3 1 0x02 0x08 0x25 250 75 % 0.500 8 3 2 2 1 0x04 0x04 0x13 6.000 0.333333 15 7 4 3 1 0x02 0x0C 0x35 200 80 % 0.500 10 4 3 2 1 0x04 0x06 0x23 0.500 16 7 4 4 1 0x04 0x0C 0x37 125 75 % 1.000 8 3 2 2 1 0x0A 0x04 0x13 0.500 20 8 6 5 1 0x04 0x0E 0x4B 100 75 % 0.833333 12 5 3 3 1 0x08 0x08 0x25 1000 - - - n o t a p p l i c a b l e - - - x - - - n o d a t a - - - 500 63 % (1) 0.250 8 3 2 2 1 0x00 0x04 0x12 (2) 69 % (1) 0.250 16 7 4 4 1 0x00 0x0C 0x36 (2) 250 75 % 0.500 8 3 2 2 1 0x02 0x04 0x13 4.000 0.250 20 8 6 5 1 0x00 0x0E 0x4A (2) 200 70 % (1) x - - - n o d a t a - - - 0.500 16 7 4 4 1 0x02 0x0C 0x37 125 75 % 1.000 8 3 2 2 1 0x06 0x04 0x13 0.500 20 8 6 5 1 0x02 0x0E 0x4B 100 75 % 1.250 8 3 2 2 1 0x08 0x04 0x13 Note: 1. See Section 19.4.3 ”Baud Rate” on page 242. 2. See Section • ”Bit 0 – SMP: Sample Point(s)” on page 259 AT90CAN32/64/128 268 7679H–CAN–08/08

AT90CAN32/64/128 20. Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. 20.1 Overview When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator output, ACO, is set. The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate inter- rupt, exclusive to the Analog Comparator. The user can select Interrupt triggering on comparator output rise, fall or toggle. A block diagram of the comparator and its surrounding logic is shown in Figure 20-1. Figure 20-1. Analog Comparator Block Diagram(1)(2) BANDGAP REFERENCE ACBG ACME ADEN T/C1 INPUT CAPTURE ADC MULTIPLEXER OUTPUT Notes: 1. ADC multiplexer output: see Table 20-2 on page 271. 2. Refer to Figure 1-2 on page 5 or Figure 1-3 on page 6 and Table 9-15 on page 83 for Analog Comparator pin placement. 20.2 Analog Comparator Register Description 20.2.1 ADC Control and Status Register B – ADCSRB Bit 7 6 5 4 3 2 1 0 - ACME – – – ADTS2 ADTS1 ADTS0 ADCSRB Read/Write R R/W R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 6 – ACME: Analog Comparator Multiplexer Enable When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero), the ADC multiplexer selects the negative input to the Analog Comparator. When this bit is written logic zero, AIN1 is applied to the negative input of the Analog Comparator. For a detailed description of this bit, see “Analog Comparator Multiplexed Input” on page 271. 269 7679H–CAN–08/08

20.2.2 Analog Comparator Control and Status Register – ACSR Bit 7 6 5 4 3 2 1 0 ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 ACSR Read/Write R/W R/W R R/W R/W R/W R/W R/W Initial Value 0 0 N/A 0 0 0 0 0 • Bit 7 – ACD: Analog Comparator Disable When this bit is written logic one, the power to the Analog Comparator is switched off. This bit can be set at any time to turn off the Analog Comparator. This will reduce power consumption in Active and Idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed. • Bit 6 – ACBG: Analog Comparator Bandgap Select When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Compar- ator. See “Internal Voltage Reference” on page 56. • Bit 5 – ACO: Analog Comparator Output The output of the Analog Comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1 - 2 clock cycles. • Bit 4 – ACI: Analog Comparator Interrupt Flag This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding inter- rupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag. • Bit 3 – ACIE: Analog Comparator Interrupt Enable When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Analog Com- parator interrupt is activated. When written logic zero, the interrupt is disabled. • Bit 2 – ACIC: Analog Comparator Input Capture Enable When written logic one, this bit enables the input capture function in Timer/Counter1 to be trig- gered by the Analog Comparator. The comparator output is in this case directly connected to the input capture front-end logic, making the comparator utilize the noise canceler and edge select features of the Timer/Counter1 Input Capture interrupt. When written logic zero, no connection between the Analog Comparator and the input capture function exists. To make the comparator trigger the Timer/Counter1 Input Capture interrupt, the ICIE1 bit in the Timer Interrupt Mask Register (TIMSK1) must be set. AT90CAN32/64/128 270 7679H–CAN–08/08

AT90CAN32/64/128 • Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select These bits determine which comparator events that trigger the Analog Comparator interrupt. The different settings are shown in Table 20-1. Table 20-1. ACIS1/ACIS0 Settings ACIS1 ACIS0 Interrupt Mode 0 0 Comparator Interrupt on Output Toggle. 0 1 Reserved 1 0 Comparator Interrupt on Falling Output Edge. 1 1 Comparator Interrupt on Rising Output Edge. When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the bits are changed. 20.3 Analog Comparator Multiplexed Input It is possible to select any of the ADC7..0 pins to replace the negative input to the Analog Com- parator. The ADC multiplexer is used to select this input, and consequently, the ADC must be switched off to utilize this feature. If the Analog Comparator Multiplexer Enable bit (ACME in ADCSRB) is set and the ADC is switched off (ADEN in ADCSRA is zero), MUX2..0 in ADMUX select the input pin to replace the negative input to the Analog Comparator, as shown in Table 20-2. If ACME is cleared or ADEN is set, AIN1 is applied to the negative input to the Analog Comparator. Table 20-2. Analog Comparator Multiplexed Input ACME ADEN MUX2..0 Analog Comparator Negative Input 0 x xxx AIN1 1 1 xxx AIN1 1 0 000 ADC0 1 0 001 ADC1 1 0 010 ADC2 1 0 011 ADC3 1 0 100 ADC4 1 0 101 ADC5 1 0 110 ADC6 1 0 111 ADC7 271 7679H–CAN–08/08

20.3.1 Digital Input Disable Register1 – DIDR1 Bit 7 6 5 4 3 2 1 0 – – – – – – AIN1D AIN0D DIDR1 Read/Write R R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 1, 0 – AIN1D, AIN0D: AIN1, AIN0 Digital Input Disable When this bit is written logic one, the digital input buffer on the AIN1/0 pin is disabled. The corre- sponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not needed, this bit should be writ- ten logic one to reduce power consumption in the digital input buffer. AT90CAN32/64/128 272 7679H–CAN–08/08

AT90CAN32/64/128 21. Analog to Digital Converter - ADC 21.1 Features • 10-bit Resolution • 0.5 LSB Integral Non-linearity • ± 2 LSB Absolute Accuracy • 65 - 260 µs Conversion Time • Up to 15 kSPS at Maximum Resolution • Eight Multiplexed Single Ended Input Channels • Seven Differential input channels • Optional Left Adjustment for ADC Result Readout • 0 - V ADC Input Voltage Range CC • Selectable 2.56 V ADC Reference Voltage • Free Running or Single Conversion Mode • ADC Start Conversion by Auto Triggering on Interrupt Sources • Interrupt on ADC Conversion Complete • Sleep Mode Noise Canceler The AT90CAN32/64/128 features a 10-bit successive approximation ADC. The ADC is con- nected to an 8-channel Analog Multiplexer which allows eight single-ended voltage inputs constructed from the pins of Port F. The single-ended voltage inputs refer to 0V (GND). The device also supports 16 differential voltage input combinations. Two of the differential inputs (ADC1, ADC0 and ADC3, ADC2) are equipped with a programmable gain stage, providing amplification steps of 0 dB (1x), 20 dB (10x), or 46 dB (200x) on the differential input voltage before the A/D conversion. Seven differential analog input channels share a common negative terminal (ADC1), while any other ADC input can be selected as the positive input terminal. If 1x or 10x gain is used, 8-bit resolution can be expected. If 200x gain is used, 7-bit resolution can be expected. The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is held at a constant level during conversion. A block diagram of the ADC is shown in Figure 21-1. The ADC has a separate analog supply voltage pin, AV . AV must not differ more than ± CC CC 0.3V from V . See the paragraph “ADC Noise Canceler” on page 280 on how to connect this CC pin. Internal reference voltages of nominally 2.56V or AV are provided On-chip. The voltage refer- CC ence may be externally decoupled at the AREF pin by a capacitor for better noise performance. 273 7679H–CAN–08/08

Figure 21-1. Analog to Digital Converter Block Schematic ADC CONVERSION COMPLETE IRQ INTERRUPT FLAGS ADTS[2:0] 8-BIT DATA BUS ADIF ADIE 15 0 ADC MULTIPLEXER ADC CTRL. & STATUS ADC DATA REGISTER SELECT (ADMUX) REGISTER (ADCSRA) (ADCH/ADCL) REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 ADEN ADSC ADATE ADIF ADPS2 ADPS1 ADPS0 TRIGGER C[9:0] SELECT AD MUX DECODER PRESCALER ON N START AVCC ANNEL SELECTI GAIN SELECTIO CONVERSION LOGIC H C INTERNAL REFERENCE SAMPLE & HOLD COMPARATOR AREF 10-BIT DAC - + GND BANDGAP REFERENCE ADC7 SINGLE ENDED / DIFFERENTIAL SELECTION ADC6 POS. ADC MULTIPLEXER ADC5 INPUT OUTPUT MUX ADC4 ADC3 DIFFERENTIAL AMPLIFIER + ADC2 - ADC1 ADC0 NEG. INPUT MUX 21.2 Operation The ADC converts an analog input voltage to a 10-bit digital value through successive approxi- mation. The minimum value represents GND and the maximum value represents the voltage on AT90CAN32/64/128 274 7679H–CAN–08/08

AT90CAN32/64/128 the AREF pin minus 1 LSB. Optionally, AV or an internal 2.56V reference voltage may be con- CC nected to the AREF pin by writing to the REFSn bits in the ADMUX Register. The internal voltage reference may thus be decoupled by an external capacitor at the AREF pin to improve noise immunity. The analog input channel and differential gain are selected by writing to the MUX bits in ADMUX. Any of the ADC input pins, as well as GND and a fixed bandgap voltage reference, can be selected as single ended inputs to the ADC. A selection of ADC input pins can be selected as positive and negative inputs to the differential amplifier. The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage reference and input channel selections will not go into effect until ADEN is set. The ADC does not consume power when ADEN is cleared, so it is recommended to switch off the ADC before entering power saving sleep modes. The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and ADCL. By default, the result is presented right adjusted, but can optionally be presented left adjusted by setting the ADLAR bit in ADMUX. If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the Data Registers belongs to the same conversion. Once ADCL is read, ADC access to Data Registers is blocked. This means that if ADCL has been read, and a conversion completes before ADCH is read, neither register is updated and the result from the conversion is lost. When ADCH is read, ADC access to the ADCH and ADCL Registers is re-enabled. The ADC has its own interrupt which can be triggered when a conversion completes. The ADC access to the Data Registers is prohibited between reading of ADCH and ADCL, the interrupt will trigger even if the result is lost. 21.3 Starting a Conversion A single conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC. This bit stays high as long as the conversion is in progress and will be cleared by hardware when the conversion is completed. If a different data channel is selected while a conversion is in progress, the ADC will finish the current conversion before performing the channel change. Alternatively, a conversion can be triggered automatically by various sources. Auto Triggering is enabled by setting the ADC Auto Trigger Enable bit, ADATE in ADCSRA. The trigger source is selected by setting the ADC Trigger Select bits, ADTS in ADCSRB (See description of the ADTS bits for a list of the trigger sources). When a positive edge occurs on the selected trigger signal, the ADC prescaler is reset and a conversion is started. This provides a method of starting con- versions at fixed intervals. If the trigger signal is still set when the conversion completes, a new conversion will not be started. If another positive edge occurs on the trigger signal during con- version, the edge will be ignored. Note that an interrupt flag will be set even if the specific interrupt is disabled or the Global Interrupt Enable bit in SREG is cleared. A conversion can thus be triggered without causing an interrupt. However, the interrupt flag must be cleared in order to trigger a new conversion at the next interrupt event. 275 7679H–CAN–08/08

Figure 21-2. ADC Auto Trigger Logic ADTS[2:0] PRESCALER START CLK ADC ADIF ADATE SOURCE 1 . CONVERSION . LOGIC . . EDGE SOURCE n DETECTOR ADSC Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the ongoing conversion has finished. The ADC then operates in Free Running mode, con- stantly sampling and updating the ADC Data Register. The first conversion must be started by writing a logical one to the ADSC bit in ADCSRA. In this mode the ADC will perform successive conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or not. If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to one. ADSC can also be used to determine if a conversion is in progress. The ADSC bit will be read as one during a conversion, independently of how the conversion was started. 21.4 Prescaling and Conversion Timing Figure 21-3. ADC Prescaler ADEN START Reset 7-BIT ADC PRESCALER CK 8 K/2 K/4 K/8 K/16 K/32 K/64 K/12 C C C C C C C ADPS0 ADPS1 ADPS2 ADC CLOCK SOURCE By default, the successive approximation circuitry requires an input clock frequency between 50 kHz and 200 kHz to get maximum resolution. If a lower resolution than 10 bits is needed, the input clock frequency to the ADC can be higher than 200 kHz to get a higher sample rate. The ADC module contains a prescaler, which generates an acceptable ADC clock frequency from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA. The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously reset when ADEN is low. AT90CAN32/64/128 276 7679H–CAN–08/08

AT90CAN32/64/128 When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion starts at the following rising edge of the ADC clock cycle. See “Differential Channels” on page 278 for details on differential conversion timing. A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry. The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conver- sion and 13.5 ADC clock cycles after the start of an first conversion. When a conversion is complete, the result is written to the ADC Data Registers, and ADIF is set. In Single Conversion mode, ADSC is cleared simultaneously. The software may then set ADSC again, and a new conversion will be initiated on the first rising ADC clock edge. When Auto Triggering is used, the prescaler is reset when the trigger event occurs. This assures a fixed delay from the trigger event to the start of conversion. In this mode, the sample-and-hold takes place two ADC clock cycles after the rising edge on the trigger source signal. Three addi- tional CPU clock cycles are used for synchronization logic. In Free Running mode, a new conversion will be started immediately after the conversion com- pletes, while ADSC remains high. For a summary of conversion times, see Table 21-1. Figure 21-4. ADC Timing Diagram, First Conversion (Single Conversion Mode) Next First Conversion Conversion Cycle Number 1 2 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 ADC Clock ADEN ADSC ADIF ADCH Sign and MSB of Result ADCL LSB of Result MUX MUX and REFS Conversion and REFS Update Sample & Hold Complete Update Figure 21-5. ADC Timing Diagram, Single Conversion One Conversion Next Conversion Cycle Number 1 2 3 4 5 6 7 8 9 10 11 12 13 1 2 3 ADC Clock ADSC ADIF ADCH Sign and MSB of Result ADCL LSB of Result Sample & Hold Conversion MUX and REFS MUX and REFS Complete Update Update 277 7679H–CAN–08/08

Figure 21-6. ADC Timing Diagram, Auto Triggered Conversion One Conversion Next Conversion Cycle Number 1 2 3 4 5 6 7 8 9 10 11 12 13 1 2 ADC Clock Trigger Source ADATE ADIF ADCH Sign and MSB of Result ADCL LSB of Result Sample & Conversion Prescaler Prescaler Hold Complete Reset Reset MUX and REFS Update Figure 21-7. ADC Timing Diagram, Free Running Conversion One Conversion Next Conversion Cycle Number 11 12 13 1 2 3 4 ADC Clock ADSC ADIF ADCH Sign and MSB of Result ADCL LSB of Result Conversion Sample & Hold Complete MUX and REFS Update Table 21-1. ADC Conversion Time Normal Auto First Condition Conversion, Triggered Conversion Single Ended Conversion Sample & Hold (Cycles from Start of 14.5 1.5 2 Convention) Conversion Time (Cycles) 25 13 13.5 21.4.1 Differential Channels When using differential channels, certain aspects of the conversion need to be taken into consideration. Differential conversions are synchronized to the internal clock CK equal to half the ADC ADC2 clock frequency. This synchronization is done automatically by the ADC interface in such a way that the sample-and-hold occurs at a specific phase of CK . A conversion initiated by the ADC2 user (i.e., all single conversions, and the first free running conversion) when CK is low will ADC2 take the same amount of time as a single ended conversion (13 ADC clock cycles from the next prescaled clock cycle). A conversion initiated by the user when CK is high will take 14 ADC ADC2 clock cycles due to the synchronization mechanism. In Free Running mode, a new conversion is AT90CAN32/64/128 278 7679H–CAN–08/08

AT90CAN32/64/128 initiated immediately after the previous conversion completes, and since CK is high at this ADC2 time, all automatically started (i.e., all but the first) Free Running conversions will take 14 ADC clock cycles. If differential channels are used and conversions are started by Auto Triggering, the ADC must be switched off between conversions. When Auto Triggering is used, the ADC prescaler is reset before the conversion is started. Since the stage is dependent of a stable ADC clock prior to the conversion, this conversion will not be valid. By disabling and then re-enabling the ADC between each conversion (writing ADEN in ADCSRA to “0” then to “1”), only extended conversions are performed. The result from the extended conversions will be valid. See “Prescaling and Conver- sion Timing” on page 276 for timing details. The gain stage is optimized for a bandwidth of 4 kHz at all gain settings. Higher frequencies may be subjected to non-linear amplification. An external low-pass filter should be used if the input signal contains higher frequency components than the gain stage bandwidth. Note that the ADC clock frequency is independent of the gain stage bandwidth limitation. E.g. the ADC clock period may be 6 µs, allowing a channel to be sampled at 12 kSPS, regardless of the bandwidth of this channel. 21.5 Changing Channel or Reference Selection The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary register to which the CPU has random access. This ensures that the channels and reference selection only takes place at a safe point during the conversion. The channel and reference selection is continuously updated until a conversion is started. Once the conversion starts, the channel and reference selection is locked to ensure a sufficient sampling time for the ADC. Con- tinuous updating resumes in the last ADC clock cycle before the conversion completes (ADIF in ADCSRA is set). Note that the conversion starts on the following rising ADC clock edge after ADSC is written. The user is thus advised not to write new channel or reference selection values to ADMUX until one ADC clock cycle after ADSC is written. If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special care must be taken when updating the ADMUX Register, in order to control which conversion will be affected by the new settings. If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the ADMUX Register is changed in this period, the user cannot tell if the next conversion is based on the old or the new settings. ADMUX can be safely updated in the following ways: 1. When ADATE or ADEN is cleared. 2. During conversion, minimum one ADC clock cycle after the trigger event. 3. After a conversion, before the interrupt flag used as trigger source is cleared. When updating ADMUX in one of these conditions, the new settings will affect the next ADC conversion. Special care should be taken when changing differential channels. Once a differential channel has been selected, the stage may take as much as 125 µs to stabilize to the new value. Thus conversions should not be started within the first 125 µs after selecting a new differential chan- nel. Alternatively, conversion results obtained within this period should be discarded. The same settling time should be observed for the first differential conversion after changing ADC reference (by changing the REFS1:0 bits in ADMUX). 279 7679H–CAN–08/08

21.5.1 ADC Input Channels When changing channel selections, the user should observe the following guidelines to ensure that the correct channel is selected: • In Single Conversion mode, always select the channel before starting the conversion. The channel selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the conversion to complete before changing the channel selection. • In Free Running mode, always select the channel before starting the first conversion. The channel selection may be changed one ADC clock cycle after writing one to ADSC. However, the simplest method is to wait for the first conversion to complete, and then change the channel selection. Since the next conversion has already started automatically, the next result will reflect the previous channel selection. Subsequent conversions will reflect the new channel selection. When switching to a differential gain channel, the first conversion result may have a poor accu- racy due to the required settling time for the automatic offset cancellation circuitry. The user should preferably disregard the first conversion result. 21.5.2 ADC Voltage Reference The reference voltage for the ADC (V ) indicates the conversion range for the ADC. Single REF ended channels that exceed V will result in codes close to 0x3FF. V can be selected as REF REF either AV , internal 2.56V reference, or external AREF pin. CC AV is connected to the ADC through a passive switch. The internal 2.56V reference is gener- CC ated from the internal bandgap reference (V ) through an internal amplifier. In either case, the BG external AREF pin is directly connected to the ADC, and the reference voltage can be made more immune to noise by connecting a capacitor between the AREF pin and ground. V can REF also be measured at the AREF pin with a high impedant voltmeter. Note that V is a high REF impedant source, and only a capacitive load should be connected in a system. If the user has a fixed voltage source connected to the AREF pin, the user may not use the other reference voltage options in the application, as they will be shorted to the external voltage. If no external voltage is applied to the AREF pin, the user may switch between AV and 2.56V as CC reference selection. The first ADC conversion result after switching reference voltage source may be inaccurate, and the user is advised to discard this result. If differential channels are used, the selected reference should not be closer to AV than indi- CC cated in Table 26-6 on page 374. 21.6 ADC Noise Canceler The ADC features a noise canceler that enables conversion during sleep mode to reduce noise induced from the CPU core and other I/O peripherals. The noise canceler can be used with ADC Noise Reduction and Idle mode. To make use of this feature, the following procedure should be used: 1. Make sure that the ADC is enabled and is not busy converting. Single Conversion mode must be selected and the ADC conversion complete interrupt must be enabled. 2. Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conversion once the CPU has been halted. 3. If no other interrupts occur before the ADC conversion completes, the ADC interrupt will wake up the CPU and execute the ADC Conversion Complete interrupt routine. If AT90CAN32/64/128 280 7679H–CAN–08/08

AT90CAN32/64/128 another interrupt wakes up the CPU before the ADC conversion is complete, that inter- rupt will be executed, and an ADC Conversion Complete interrupt request will be generated when the ADC conversion completes. The CPU will remain in active mode until a new sleep command is executed. Note that the ADC will not be automatically turned off when entering other sleep modes than Idle mode and ADC Noise Reduction mode. The user is advised to write zero to ADEN before enter- ing such sleep modes to avoid excessive power consumption. If the ADC is enabled in such sleep modes and the user wants to perform differential conver- sions, the user is advised to switch the ADC off and on after waking up from sleep to prompt an extended conversion to get a valid result. 21.6.1 Analog Input Circuitry The analog input circuitry for single ended channels is illustrated in Figure 21-8. An analog source applied to ADCn is subjected to the pin capacitance and input leakage of that pin, regard- less of whether that channel is selected as input for the ADC. When the channel is selected, the source must drive the S/H capacitor through the series resistance (combined resistance in the input path). The ADC is optimized for analog signals with an output impedance of approximately 10kΩ or less. If such a source is used, the sampling time will be negligible. If a source with higher imped- ance is used, the sampling time will depend on how long time the source needs to charge the S/H capacitor, with can vary widely. The user is recommended to only use low impedant sources with slowly varying signals, since this minimizes the required charge transfer to the S/H capacitor. If differential gain channels are used, the input circuitry looks somewhat different, although source impedances of a few hundred kΩ or less is recommended. Signal components higher than the Nyquist frequency (f /2) should not be present for either ADC kind of channels, to avoid distortion from unpredictable signal convolution. The user is advised to remove high frequency components with a low-pass filter before applying the signals as inputs to the ADC. Figure 21-8. Analog Input Circuitry I IH ADCn 1..100 kO C = 14 pF S/H I IL V /2 CC 21.6.2 Analog Noise Canceling Techniques Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: 281 7679H–CAN–08/08

1. Keep analog signal paths as short as possible. Make sure analog tracks run over the analog ground plane, and keep them well away from high-speed switching digital tracks. 2. The AV pin on the device should be connected to the digital V supply voltage via CC CC an LC network as shown in Figure 21-9. 3. Use the ADC noise canceler function to reduce induced noise from the CPU. 4. If any ADC port pins are used as digital outputs, it is essential that these do not switch while a conversion is in progress. Figure 21-9. ADC Power Connections (AD0) PA0 51 VCC 52 GND 53 (ADC7) PF7 54 (ADC6) PF6 55 (ADC5) PF5 56 (ADC4) PF4 57 (ADC3) PF3 58 (ADC2) PF2 59 (ADC1) PF1 60 (ADC0) PF0 6611 10uH AREF 6622 GND 6633 AVCC 6644 100nF 1 Analog Ground Plane C N 21.6.3 Offset Compensation Schemes The gain stage has a built-in offset cancellation circuitry that nulls the offset of differential mea- surements as much as possible. The remaining offset in the analog path can be measured directly by selecting the same channel for both differential inputs. This offset residue can be then subtracted in software from the measurement results. Using this kind of software based offset correction, offset on any channel can be reduced below one LSB. 21.6.4 ADC Accuracy Definitions An n-bit single-ended ADC converts a voltage linearly between GND and V in 2n steps REF (LSBs). The lowest code is read as 0, and the highest code is read as 2n-1. Several parameters describe the deviation from the ideal behavior: • Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5 LSB). Ideal value: 0 LSB. AT90CAN32/64/128 282 7679H–CAN–08/08

AT90CAN32/64/128 Figure 21-10. Offset Error Output Code Ideal ADC Actual ADC Offset Error V Input Voltage REF • Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB Figure 21-11. Gain Error Output Code Gain Error Ideal ADC Actual ADC V Input Voltage REF • Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0 LSB. 283 7679H–CAN–08/08

Figure 21-12. Integral Non-linearity (INL) Output Code IN L Ideal ADC Actual ADC V Input Voltage REF • Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. Figure 21-13. Differential Non-linearity (DNL) Output Code 0x3FF 1 LSB DNL 0x000 0 V Input Voltage REF • Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 LSB wide) will code to the same value. Always ± 0.5 LSB. • Absolute Accuracy: The maximum deviation of an actual (unadjusted) transition compared to an ideal transition for any code. This is the compound effect of offset, gain error, differential error, non-linearity, and quantization error. Ideal value: ± 0.5 LSB. 21.7 ADC Conversion Result After the conversion is complete (ADIF is high), the conversion result can be found in the ADC Result Registers (ADCL, ADCH). AT90CAN32/64/128 284 7679H–CAN–08/08

AT90CAN32/64/128 For single ended conversion, the result is: V ⋅1023 IN ADC = -------------------------- V REF where V is the voltage on the selected input pin and V the selected voltage reference (see IN REF Table 21-3 on page 287 and Table 21-4 on page 288). 0x000 represents analog ground, and 0x3FF represents the selected reference voltage minus one LSB. If differential channels are used, the result is: (V –V )⋅GAIN⋅512 POS NEG ADC = ------------------------------------------------------------------------ V REF where V is the voltage on the positive input pin, V the voltage on the negative input pin, POS NEG GAIN the selected gain factor and V the selected voltage reference. The result is presented REF in two’s complement form, from 0x200 (-512d) through 0x1FF (+511d). Note that if the user wants to perform a quick polarity check of the result, it is sufficient to read the MSB of the result (ADC9 in ADCH). If the bit is one, the result is negative, and if this bit is zero, the result is posi- tive. Figure 21-14 shows the decoding of the differential input range. Table 82 shows the resulting output codes if the differential input channel pair (ADCn - ADCm) is selected with a reference voltage of V . REF Figure 21-14. Differential Measurement Range Output Code 0x1FF 0x000 - VREF 0x3FF 0 VREF DVoiflfteargeen t(iValo Ilntsp)ut 0x200 285 7679H–CAN–08/08

Table 21-2. Correlation Between Input Voltage and Output Codes V Read code Corresponding decimal value ADCn V + V /GAIN 0x1FF 511 ADCm REF V + 0.999 V /GAIN 0x1FF 511 ADCm REF V + 0.998 V /GAIN 0x1FE 510 ADCm REF ... ... ... V + 0.001 V /GAIN 0x001 1 ADCm REF V 0x000 0 ADCm V - 0.001 V /GAIN 0x3FF -1 ADCm REF ... ... ... V - 0.999 V /GAIN 0x201 -511 ADCm REF V - V /GAIN 0x200 -512 ADCm REF Example 1: – ADMUX = 0xED (ADC3 - ADC2, 10x gain, 2.56V reference, left adjusted result) – Voltage on ADC3 is 300 mV, voltage on ADC2 is 500 mV. – ADCR = 512 * 10 * (300 - 500) / 2560 = -400 = 0x270 – ADCL will thus read 0x00, and ADCH will read 0x9C. Writing zero to ADLAR right adjusts the result: ADCL = 0x70, ADCH = 0x02. Example 2: – ADMUX = 0xFB (ADC3 - ADC2, 1x gain, 2.56V reference, left adjusted result) – Voltage on ADC3 is 300 mV, voltage on ADC2 is 500 mV. – ADCR = 512 * 1 * (300 - 500) / 2560 = -41 = 0x029. – ADCL will thus read 0x40, and ADCH will read 0x0A. Writing zero to ADLAR right adjusts the result: ADCL = 0x00, ADCH = 0x29. AT90CAN32/64/128 286 7679H–CAN–08/08

AT90CAN32/64/128 21.8 ADC Register Description 21.8.1 ADC Multiplexer Selection Register – ADMUX Bit 7 6 5 4 3 2 1 0 REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 ADMUX Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 7:6 – REFS1:0: Reference Selection Bits These bits select the voltage reference for the ADC, as shown in Table 21-3. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSRA is set). The internal voltage reference options may not be used if an external reference voltage is being applied to the AREF pin. Table 21-3. Voltage Reference Selections for ADC REFS1 REFS0 Voltage Reference Selection 0 0 AREF, Internal Vref turned off 0 1 AV with external capacitor on AREF pin CC 1 0 Reserved 1 1 Internal 2.56V Voltage Reference with external capacitor on AREF pin • Bit 5 – ADLAR: ADC Left Adjust Result The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register. Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing conver- sions. For a complete description of this bit, see “The ADC Data Register – ADCL and ADCH” on page 290. • Bits 4:0 – MUX4:0: Analog Channel Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. These bits also select the gain for the differential channels. See Table 21-4 for details. If these bits are changed during a conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSRA is set). 287 7679H–CAN–08/08

Table 21-4. Input Channel and Gain Selections Single Ended Positive Differential Negative Differential MUX4..0 Gain Input Input Input 00000 ADC0 00001 ADC1 00010 ADC2 00011 ADC3 N/A 00100 ADC4 00101 ADC5 00110 ADC6 00111 ADC7 01000 (ADC0 / ADC0 / 10x) 01001 ADC1 ADC0 10x 01010 (ADC0 / ADC0 / 200x) 01011 ADC1 ADC0 200x 01100 (ADC2 / ADC2 / 10x) 01101 ADC3 ADC2 10x 01110 (ADC2 / ADC2 / 200x) 01111 ADC3 ADC2 200x 10000 ADC0 ADC1 1x 10001 (ADC1 / ADC1 / 1x) 10010 ADC2 ADC1 1x N/A 10011 ADC3 ADC1 1x 10100 ADC4 ADC1 1x 10101 ADC5 ADC1 1x 10110 ADC6 ADC1 1x 10111 ADC7 ADC1 1x 11000 ADC0 ADC2 1x 11001 ADC1 ADC2 1x 11010 (ADC2 / ADC2 / 1x) 11011 ADC3 ADC2 1x 11100 ADC4 ADC2 1x 11101 ADC5 ADC2 1x 11110 1.1V (V ) Band Gap N/A 11111 0V (GND) AT90CAN32/64/128 288 7679H–CAN–08/08

AT90CAN32/64/128 21.8.2 ADC Control and Status Register A – ADCSRA Bit 7 6 5 4 3 2 1 0 ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 ADCSRA Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 7 – ADEN: ADC Enable Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion. • Bit 6 – ADSC: ADC Start Conversion In Single Conversion mode, write this bit to one to start each conversion. In Free Running mode, write this bit to one to start the first conversion. The first conversion after ADSC has been written after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled, will take 25 ADC clock cycles instead of the normal 13. This first conversion performs initializa- tion of the ADC. ADSC will read as one as long as a conversion is in progress. When the conversion is complete, it returns to zero. Writing zero to this bit has no effect. • Bit 5 – ADATE: ADC Auto Trigger Enable When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a con- version on a positive edge of the selected trigger signal. The trigger source is selected by setting the ADC Trigger Select bits, ADTS in ADCSRB. • Bit 4 – ADIF: ADC Interrupt Flag This bit is set when an ADC conversion completes and the Data Registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set. ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alter- natively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a Read-Modify- Write on ADCSRA, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used. • Bit 3 – ADIE: ADC Interrupt Enable When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Inter- rupt is activated. 289 7679H–CAN–08/08

• Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits These bits determine the division factor between the XTAL frequency and the input clock to the ADC. Table 21-5. ADC Prescaler Selections ADPS2 ADPS1 ADPS0 Division Factor 0 0 0 2 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 128 21.8.3 The ADC Data Register – ADCL and ADCH ADLAR = 0 Bit 15 14 13 12 11 10 9 8 – – – – – – ADC9 ADC8 ADCH ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL Bit 7 6 5 4 3 2 1 0 Read/Write R R R R R R R R R R R R R R R R Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADLAR = 1 Bit 15 14 13 12 11 10 9 8 ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADCH ADC1 ADC0 – – – – – – ADCL Bit 7 6 5 4 3 2 1 0 Read/Write R R R R R R R R R R R R R R R R Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 When an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8-bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adjusted. AT90CAN32/64/128 290 7679H–CAN–08/08

AT90CAN32/64/128 • ADC9:0: ADC Conversion Result These bits represent the result from the conversion, as detailed in “ADC Conversion Result” on page 284. 21.8.4 ADC Control and Status Register B – ADCSRB Bit 7 6 5 4 3 2 1 0 – ACME – – – ADTS2 ADTS1 ADTS0 ADCSRB Read/Write R R/W R R R R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 7– Reserved Bit This bit is reserved for future use. For compatibility with future devices, it must be written to zero when ADCSRB is written. • Bit 5:3– Reserved Bits These bits are reserved for future use. For compatibility with future devices, they must be written to zero when ADCSRB is written. • Bit 2:0 – ADTS2:0: ADC Auto Trigger Source If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect. A conversion will be triggered by the rising edge of the selected interrupt flag. Note that switching from a trig- ger source that is cleared to a trigger source that is set, will generate a positive edge on the trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set. Table 21-6. ADC Auto Trigger Source Selections ADTS2 ADTS1 ADTS0 Trigger Source 0 0 0 Free Running mode 0 0 1 Analog Comparator 0 1 0 External Interrupt Request 0 0 1 1 Timer/Counter0 Compare Match 1 0 0 Timer/Counter0 Overflow 1 0 1 Timer/Counter1 Compare Match B 1 1 0 Timer/Counter1 Overflow 1 1 1 Timer/Counter1 Capture Event 291 7679H–CAN–08/08

21.8.5 Digital Input Disable Register0 – DIDR0 Bit 7 6 5 4 3 2 1 0 ADC7D ADC6D ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D DIDR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 7:0 – ADC7D..ADC0D: ADC7:0 Digital Input Disable When this bit is written logic one, the digital input buffer on the corresponding ADC pin is dis- abled. The corresponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. AT90CAN32/64/128 292 7679H–CAN–08/08

AT90CAN32/64/128 22. JTAG Interface and On-chip Debug System 22.1 Features • JTAG (IEEE std. 1149.1 Compliant) Interface • Boundary-scan Capabilities According to the IEEE std. 1149.1 (JTAG) Standard • Debugger Access to: – All Internal Peripheral Units – Internal and External RAM – The Internal Register File – Program Counter – EEPROM and Flash Memories • Extensive On-chip Debug Support for Break Conditions, Including – AVR Break Instruction – Break on Change of Program Memory Flow – Single Step Break – Program Memory Break Points on Single Address or Address Range – Data Memory Break Points on Single Address or Address Range • Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface • On-chip Debugging Supported by AVR Studio® 22.2 Overview The AVR IEEE std. 1149.1 compliant JTAG interface can be used for: • Testing PCBs by using the JTAG Boundary-scan capability • Programming the non-volatile memories, Fuses and Lock bits • On-chip debugging A brief description is given in the following sections. Detailed descriptions for Programming via the JTAG interface, and using the Boundary-scan Chain can be found in the sections “JTAG Programming Overview” on page 352 and “Boundary-scan IEEE 1149.1 (JTAG)” on page 300, respectively. The On-chip Debug support is considered being private JTAG instructions, and dis- tributed within ATMEL and to selected third party vendors only. Figure 22-1 shows a block diagram of the JTAG interface and the On-chip Debug system. The TAP Controller is a state machine controlled by the TCK and TMS signals. The TAP Controller selects either the JTAG Instruction Register or one of several Data Registers as the scan chain (Shift Register) between the TDI – input and TDO – output. The Instruction Register holds JTAG instructions controlling the behavior of a Data Register. The ID-Register (IDentifier Register), Bypass Register, and the Boundary-scan Chain are the Data Registers used for board-level testing. The JTAG Programming Interface (actually consist- ing of several physical and virtual Data Registers) is used for serial programming via the JTAG interface. The Internal Scan Chain and Break Point Scan Chain are used for On-chip debugging only. 22.3 Test Access Port – TAP The JTAG interface is accessed through four of the AVR’s pins. In JTAG terminology, these pins constitute the Test Access Port – TAP. These pins are: • TMS: Test mode select. This pin is used for navigating through the TAP-controller state machine. 293 7679H–CAN–08/08

• TCK: Test Clock. JTAG operation is synchronous to TCK. • TDI: Test Data In. Serial input data to be shifted in to the Instruction Register or Data Register (Scan Chains). • TDO: Test Data Out. Serial output data from Instruction Register or Data Register (Scan Chains). The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT – which is not provided. When the JTAGEN fuse is unprogrammed, these four TAP pins are normal port pins and the TAP controller is in reset. When programmed and the JTD bit in MCUCR is cleared, the TAP input signals are internally pulled high and the JTAG is enabled for Boundary-scan and program- ming. In this case, the TAP output pin (TDO) is left floating in states where the JTAG TAP controller is not shifting data, and must therefore be connected to a pull-up resistor or other hardware having pull-ups (for instance the TDI-input of the next device in the scan chain). The device is shipped with this fuse programmed. For the On-chip Debug system, in addition to the JTAG interface pins, the RESET pin is moni- tored by the debugger to be able to detect external reset sources. The debugger can also pull the RESET pin low to reset the whole system, assuming only open collectors on the reset line are used in the application. AT90CAN32/64/128 294 7679H–CAN–08/08

AT90CAN32/64/128 Figure 22-1. Block Diagram I/O PORT 0 DEVICE BOUNDARY BOUNDARY SCAN CHAIN TDI JTAG PROGRAMMING TDO TAP INTERFACE TCK CONTROLLER TMS INTERNAL FLASH Address SCAN PC INSTRUCTION MEMORY Data CHAIN Instruction REGISTER AVR CPU ID REGISTER BREAKPOINT UNIT MUX RBEYGPISATSESR FLOWU CNOITNTROL PEDRUIIGPNIHITTEASRLAL PEARUNIPNAHILTEOSRGIAL nalog inputs BREAKPOINT A SCAN CHAIN JTAG / AVR CORE DAEDCDORDESESR OCD STATUS COIMNMTEURNFICAACTEION k lines AND CONTROL oc Cl & ol ntr o C I/O PORT n 295 7679H–CAN–08/08

Figure 22-2. TAP Controller State Diagram 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 1 0 0 1 1 Capture-DR Capture-IR 0 0 Shift-DR 0 Shift-IR 0 1 1 1 1 Exit1-DR Exit1-IR 0 0 Pause-DR 0 Pause-IR 0 1 1 0 0 Exit2-DR Exit2-IR 1 1 Update-DR Update-IR 1 0 1 0 22.4 TAP Controller The TAP controller is a 16-state finite state machine that controls the operation of the Boundary- scan circuitry, JTAG programming circuitry, or On-chip Debug system. The state transitions depicted in Figure 22-2 depend on the signal present on TMS (shown adjacent to each state transition) at the time of the rising edge at TCK. The initial state after a Power-on Reset is Test- Logic-Reset. As a definition in this document, the LSB is shifted in and out first for all Shift Registers. Assuming Run-Test/Idle is the present state, a typical scenario for using the JTAG interface is: • At the TMS input, apply the sequence 1, 1, 0, 0 at the rising edges of TCK to enter the Shift Instruction Register – Shift-IR state. While in this state, shift the four bits of the JTAG instructions into the JTAG Instruction Register from the TDI input at the rising edge of TCK. The TMS input must be held low during input of the 3 LSBs in order to remain in the Shift-IR state. The MSB of the instruction is shifted in when this state is left by setting TMS high. While the instruction is shifted in from the TDI pin, the captured IR-state 0x01 is shifted out on the TDO pin. The JTAG Instruction selects a particular Data Register as path between TDI and TDO and controls the circuitry surrounding the selected Data Register. AT90CAN32/64/128 296 7679H–CAN–08/08

AT90CAN32/64/128 • Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction is latched onto the parallel output from the Shift Register path in the Update-IR state. The Exit-IR, Pause-IR, and Exit2-IR states are only used for navigating the state machine. • At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the Shift Data Register – Shift-DR state. While in this state, upload the selected data register (selected by the present JTAG instruction in the JTAG Instruction Register) from the TDI input at the rising edge of TCK. In order to remain in the Shift-DR state, the TMS input must be held low during input of all bits except the MSB. The MSB of the data is shifted in when this state is left by setting TMS high. While the data register is shifted in from the TDI pin, the parallel inputs to the data register captured in the Capture-DR state is shifted out on the TDO pin. • Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. If the selected data register has a latched parallel-output, the latching takes place in the Update-DR state. The Exit-DR, Pause-DR, and Exit2-DR states are only used for navigating the state machine. As shown in the state diagram, the Run-Test/Idle state need not be entered between selecting JTAG instruction and using data registers, and some JTAG instructions may select certain func- tions to be performed in the Run-Test/Idle, making it unsuitable as an Idle state. Note: Independent of the initial state of the TAP Controller, the Test-Logic-Reset state can always be entered by holding TMS high for five TCK clock periods. For detailed information on the JTAG specification, refer to the literature listed in “Bibliography” on page 299. 22.5 Using the Boundary-scan Chain A complete description of the Boundary-scan capabilities are given in the section “Boundary- scan IEEE 1149.1 (JTAG)” on page 300. 22.6 Using the On-chip Debug System As shown in Figure 22-1, the hardware support for On-chip Debugging consists mainly of • A scan chain on the interface between the internal AVR CPU and the internal peripheral units. • Break Point unit. • Communication interface between the CPU and JTAG system. All read or modify/write operations needed for implementing the Debugger are done by applying AVR instructions via the internal AVR CPU Scan Chain. The CPU sends the result to an I/O memory mapped location which is part of the communication interface between the CPU and the JTAG system. The Break Point Unit implements Break on Change of Program Flow, Single Step Break, two Program Memory Break Points, and two combined Break Points. Together, the four Break Points can be configured as either: • 4 single Program Memory Break Points. • 3 single Program Memory Break Points + 1 single Data Memory Break Point. • 2 single Program Memory Break Points + 2 single Data Memory Break Points. 297 7679H–CAN–08/08

• 2 single Program Memory Break Points + 1 Program Memory Break Point with mask (“range Break Point”). • 2 single Program Memory Break Points + 1 Data Memory Break Point with mask (“range Break Point”). A debugger, like the AVR Studio, may however use one or more of these resources for its inter- nal purpose, leaving less flexibility to the end-user. A list of the On-chip Debug specific JTAG instructions is given in “On-chip Debug Specific JTAG Instructions” on page 298. The JTAGEN Fuse must be programmed to enable the JTAG Test Access Port. In addition, the OCDEN Fuse must be programmed and no Lock bits must be set for the On-chip debug system to work. As a security feature, the On-chip debug system is disabled when either of the LB1 or LB2 Lock bits are set. Otherwise, the On-chip debug system would have provided a back-door into a secured device. The AVR Studio enables the user to fully control execution of programs on an AVR device with On-chip Debug capability, AVR In-Circuit Emulator, or the built-in AVR Instruction Set Simulator. AVR Studio® supports source level execution of Assembly programs assembled with Atmel Cor- poration’s AVR Assembler and C programs compiled with third party vendors’ compilers. AVR Studio runs under Microsoft® Windows® 95/98/2000/NT/XP. For a full description of the AVR Studio, please refer to the AVR Studio User Guide. Only high- lights are presented in this document. All necessary execution commands are available in AVR Studio, both on source level and on disassembly level. The user can execute the program, single step through the code either by tracing into or stepping over functions, step out of functions, place the cursor on a statement and execute until the statement is reached, stop the execution, and reset the execution target. In addition, the user can have an unlimited number of code Break Points (using the BREAK instruction) and up to two data memory Break Points, alternatively combined as a mask (range) Break Point. 22.7 On-chip Debug Specific JTAG Instructions The On-chip debug support is considered being private JTAG instructions, and distributed within ATMEL and to selected third party vendors only. Instruction opcodes are listed for reference. 22.7.1 PRIVATE0 (0x8) Private JTAG instruction for accessing On-chip debug system. 22.7.2 PRIVATE1 (0x9) Private JTAG instruction for accessing On-chip debug system. 22.7.3 PRIVATE2 (0xA) Private JTAG instruction for accessing On-chip debug system. 22.7.4 PRIVATE3 (0xB) Private JTAG instruction for accessing On-chip debug system. AT90CAN32/64/128 298 7679H–CAN–08/08

AT90CAN32/64/128 22.8 On-chip Debug Related Register in I/O Memory 22.8.1 On-chip Debug Register – OCDR Bit 7 6 5 4 3 2 1 0 IDRD/OCDR7 OCDR6 OCDR5 OCDR4 OCDR3 OCDR2 OCDR1 OCDR0 OCDR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The OCDR Register provides a communication channel from the running program in the micro- controller to the debugger. The CPU can transfer a byte to the debugger by writing to this location. At the same time, an internal flag; I/O Debug Register Dirty – IDRD – is set to indicate to the debugger that the register has been written. When the CPU reads the OCDR Register the 7 LSB will be from the OCDR Register, while the MSB is the IDRD bit. The debugger clears the IDRD bit when it has read the information. In some AVR devices, this register is shared with a standard I/O location. In this case, the OCDR Register can only be accessed if the OCDEN Fuse is programmed, and the debugger enables access to the OCDR Register. In all other cases, the standard I/O location is accessed. Refer to the debugger documentation for further information on how to use this register. 22.9 Using the JTAG Programming Capabilities Programming of AVR parts via JTAG is performed via the 4-pin JTAG port, TCK, TMS, TDI, and TDO. These are the only pins that need to be controlled/observed to perform JTAG program- ming (in addition to power pins). It is not required to apply 12V externally. The JTAGEN Fuse must be programmed and the JTD bit in the MCUCR Register must be cleared to enable the JTAG Test Access Port. The JTAG programming capability supports: • Flash programming and verifying. • EEPROM programming and verifying. • Fuse programming and verifying. • Lock bit programming and verifying. The Lock bit security is exactly as in parallel programming mode. If the Lock bits LB1 or LB2 are programmed, the OCDEN Fuse cannot be programmed unless first doing a chip erase. This is a security feature that ensures no back-door exists for reading out the content of a secured device. The details on programming through the JTAG interface and programming specific JTAG instructions are given in the section “JTAG Programming Overview” on page 352. 22.10 Bibliography For more information about general Boundary-scan, the following literature can be consulted: • IEEE: IEEE Std 1149.1-1990. IEEE Standard Test Access Port and Boundary-scan Architecture, IEEE, 1993. • Colin Maunder: The Board Designers Guide to Testable Logic Circuits, Addison-Wesley, 1992. 299 7679H–CAN–08/08

23. Boundary-scan IEEE 1149.1 (JTAG) 23.1 Features • JTAG (IEEE std. 1149.1 compliant) Interface • Boundary-scan Capabilities According to the JTAG Standard • Full Scan of all Port Functions as well as Analog Circuitry having Off-chip Connections • Supports the Optional IDCODE Instruction • Additional Public AVR_RESET Instruction to Reset the AVR 23.2 System Overview The Boundary-scan chain has the capability of driving and observing the logic levels on the digi- tal I/O pins, as well as the boundary between digital and analog logic for analog circuitry having off-chip connections. At system level, all ICs having JTAG capabilities are connected serially by the TDI/TDO signals to form a long Shift Register. An external controller sets up the devices to drive values at their output pins, and observe the input values received from other devices. The controller compares the received data with the expected result. In this way, Boundary-scan pro- vides a mechanism for testing interconnections and integrity of components on Printed Circuits Boards by using the four TAP signals only. The four IEEE 1149.1 defined mandatory JTAG instructions IDCODE, BYPASS, SAMPLE/PRE- LOAD, and EXTEST, as well as the AVR specific public JTAG instruction AVR_RESET can be used for testing the Printed Circuit Board. Initial scanning of the data register path will show the ID-Code of the device, since IDCODE is the default JTAG instruction. It may be desirable to have the AVR device in reset during test mode. If not reset, inputs to the device may be deter- mined by the scan operations, and the internal software may be in an undetermined state when exiting the test mode. Entering reset, the outputs of any port pin will instantly enter the high impedance state, making the HIGHZ instruction redundant. If needed, the BYPASS instruction can be issued to make the shortest possible scan chain through the device. The device can be set in the reset state either by pulling the external RESET pin low, or issuing the AVR_RESET instruction with appropriate setting of the Reset Data Register. The EXTEST instruction is used for sampling external pins and loading output pins with data. The data from the output latch will be driven out on the pins as soon as the EXTEST instruction is loaded into the JTAG IR-Register. Therefore, the SAMPLE/PRELOAD should also be used for setting initial values to the scan ring, to avoid damaging the board when issuing the EXTEST instruction for the first time. SAMPLE/PRELOAD can also be used for taking a snapshot of the external pins during normal operation of the part. The JTAGEN Fuse must be programmed and the JTD bit in the I/O Register MCUCR must be cleared to enable the JTAG Test Access Port. When using the JTAG interface for Boundary-scan, using a JTAG TCK clock frequency higher than the internal chip frequency is possible. The chip clock is not required to run. 23.3 Data Registers The data registers relevant for Boundary-scan operations are: • Bypass Register • Device Identification Register • Reset Register • Boundary-scan Chain AT90CAN32/64/128 300 7679H–CAN–08/08

AT90CAN32/64/128 23.3.1 Bypass Register The Bypass Register consists of a single Shift Register stage. When the Bypass Register is selected as path between TDI and TDO, the register is reset to 0 when leaving the Capture-DR controller state. The Bypass Register may be used to shorten the scan chain on a system when the other devices are to be tested. 23.3.2 Device Identification Register Figure 23-1 shows the structure of the Device Identification Register. Figure 23-1. The Format of the Device Identification Register MSB LSB Bit 31 28 27 12 11 1 0 Device ID Version Part Number Manufacturer ID 1 4 bits 16 bits 11 bits 1-bit 23.3.2.1 Version Version is a 4-bit number identifying the revision of the component. The relevant version number is shown in Table 23-1. Table 23-1. JTAG Version Numbers Version JTAG Version Number (Hex) AT90CAN32 revision A 0x0 AT90CAN64 revision A 0x0 AT90CAN128 revision A 0x0 23.3.2.2 Part Number The part number is a 16-bit code identifying the component. The JTAG Part Number for AT90CAN32/64/128 is listed in Table 23-2. Table 23-2. AVR JTAG Part Number Part Number JTAG Part Number (Hex) AT90CAN32 0x9581 AT90CAN64 0x9681 AT90CAN128 0x9781 23.3.2.3 Manufacturer ID The Manufacturer ID is a 11-bit code identifying the manufacturer. The JTAG manufacturer ID for ATMEL is listed in Table 23-3. Table 23-3. Manufacturer ID Manufacturer JTAG Manufacturer ID (Hex) ATMEL 0x01F 301 7679H–CAN–08/08

23.3.2.4 Device ID The full Device ID is listed in Table 23-4 following the AT90CAN32/64/128 version. Table 23-4. Device ID Version JTAG Device ID (Hex) AT90CAN32 revision A 0x0958103F AT90CAN64 revision A 0x0968103F AT90CAN128 revision A 0x0978103F 23.3.3 Reset Register The Reset Register is a test data register used to reset the part. Since the AVR tri-states Port Pins when reset, the Reset Register can also replace the function of the unimplemented optional JTAG instruction HIGHZ. A high value in the Reset Register corresponds to pulling the external Reset low. The part is reset as long as there is a high value present in the Reset Register. Depending on the fuse set- tings for the clock options, the part will remain reset for a reset time-out period (refer to “System Clock” on page 37) after releasing the Reset Register. The output from this data register is not latched, so the reset will take place immediately, as shown in Figure 23-2. Figure 23-2. Reset Register From Other Internal and External Reset Sources Internal reset From TDI D Q To TDO ClockDR • AVR_RESET 23.3.4 Boundary-scan Chain The Boundary-scan Chain has the capability of driving and observing the logic levels on the dig- ital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having off-chip connections. See “Boundary-scan Chain” on page 304 for a complete description. 23.4 Boundary-scan Specific JTAG Instructions The instruction register is 4-bit wide, supporting up to 16 instructions. Listed below are the JTAG instructions useful for Boundary-scan operation. Note that the optional HIGHZ instruction is not implemented, but all outputs with tri-state capability can be set in high-impedant state by using the AVR_RESET instruction, since the initial state for all port pins is tri-state. As a definition in this datasheet, the LSB is shifted in and out first for all Shift Registers. The OPCODE for each instruction is shown behind the instruction name in hex format. The text describes which data register is selected as path between TDI and TDO for each instruction. AT90CAN32/64/128 302 7679H–CAN–08/08

AT90CAN32/64/128 23.4.1 EXTEST (0x0) Mandatory JTAG instruction for selecting the Boundary-scan Chain as data register for testing circuitry external to the AVR package. For port-pins, Pull-up Disable, Output Control, Output Data, and Input Data are all accessible in the scan chain. For Analog circuits having off-chip connections, the interface between the analog and the digital logic is in the scan chain. The con- tents of the latched outputs of the Boundary-scan chain is driven out as soon as the JTAG IR- Register is loaded with the EXTEST instruction. The active states are: • Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain. • Shift-DR: The Internal Scan Chain is shifted by the TCK input. • Update-DR: Data from the scan chain is applied to output pins. 23.4.2 IDCODE (0x1) Optional JTAG instruction selecting the 32 bit ID-Register as data register. The ID-Register con- sists of a version number, a device number and the manufacturer code chosen by JEDEC. This is the default instruction after power-up. The active states are: • Capture-DR: Data in the IDCODE Register is sampled into the Boundary-scan Chain. • Shift-DR: The IDCODE scan chain is shifted by the TCK input. 23.4.3 SAMPLE_PRELOAD (0x2) Mandatory JTAG instruction for pre-loading the output latches and taking a snap-shot of the input/output pins without affecting the system operation. However, the output latches are not connected to the pins. The Boundary-scan Chain is selected as data register. The active states are: • Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain. • Shift-DR: The Boundary-scan Chain is shifted by the TCK input. • Update-DR: Data from the Boundary-scan chain is applied to the output latches. However, the output latches are not connected to the pins. 23.4.4 AVR_RESET (0xC) The AVR specific public JTAG instruction for forcing the AVR device into the Reset mode or releasing the JTAG reset source. The TAP controller is not reset by this instruction. The one bit Reset Register is selected as data register. Note that the reset will be active as long as there is a logic “one” in the Reset Chain. The output from this chain is not latched. The active states are: • Shift-DR: The Reset Register is shifted by the TCK input. 23.4.5 BYPASS (0xF) Mandatory JTAG instruction selecting the Bypass Register for data register. The active states are: • Capture-DR: Loads a logic “0” into the Bypass Register. 303 7679H–CAN–08/08

• Shift-DR: The Bypass Register cell between TDI and TDO is shifted. 23.5 Boundary-scan Related Register in I/O Memory 23.5.1 MCU Control Register – MCUCR The MCU Control Register contains control bits for general MCU functions. Bit 7 6 5 4 3 2 1 0 JTD – – PUD – – IVSEL IVCE MCUCR Read/Write R/W R R R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bits 7 – JTD: JTAG Interface Disable When this bit is zero, the JTAG interface is enabled if the JTAGEN Fuse is programmed. If this bit is one, the JTAG interface is disabled. In order to avoid unintentional disabling or enabling of the JTAG interface, a timed sequence must be followed when changing this bit: The application software must write this bit to the desired value twice within four cycles to change its value. Note that this bit must not be altered when using the On-chip Debug system. If the JTAG interface is left unconnected to other JTAG circuitry, the JTD bit should be set to one. The reason for this is to avoid static current at the TDO pin in the JTAG interface. 23.5.2 MCU Status Register – MCUSR The MCU Status Register provides information on which reset source caused an MCU reset. Bit 7 6 5 4 3 2 1 0 – – – JTRF WDRF BORF EXTRF PORF MCUSR Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 See Bit Description • Bit 4 – JTRF: JTAG Reset Flag This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic zero to the flag. 23.6 Boundary-scan Chain The Boundary-scan chain has the capability of driving and observing the logic levels on the digi- tal I/O pins, as well as the boundary between digital and analog logic for analog circuitry having off-chip connection. 23.6.1 Scanning the Digital Port Pins Figure 23-3 shows the Boundary-scan Cell for a bi-directional port pin with pull-up function. The cell consists of a standard Boundary-scan cell for the Pull-up Enable – PUExn – function, and a bi-directional pin cell that combines the three signals Output Control – OCxn, Output Data – ODxn, and Input Data – IDxn, into only a two-stage Shift Register. The port and pin indexes are not used in the following description The Boundary-scan logic is not included in the figures in the datasheet. Figure 23-4 shows a simple digital port pin as described in the section “I/O-Ports” on page 66. The Boundary-scan details from Figure 23-3 replaces the dashed box in Figure 23-4. AT90CAN32/64/128 304 7679H–CAN–08/08

AT90CAN32/64/128 When no alternate port function is present, the Input Data – ID – corresponds to the PINxn Reg- ister value (but ID has no synchronizer), Output Data corresponds to the PORT Register, Output Control corresponds to the Data Direction – DD Register, and the Pull-up Enable – PUExn – cor- responds to logic expression PUD · DDxn · PORTxn. Digital alternate port functions are connected outside the dotted box in Figure 23-4 to make the scan chain read the actual pin value. For Analog function, there is a direct connection from the external pin to the analog circuit, and a scan chain is inserted on the interface between the digi- tal logic and the analog circuitry. Figure 23-3. Boundary-scan Cell for Bi-directional Port Pin with Pull-up Function. ShiftDR To Next Cell EXTEST Vcc Pullup Enable (PUE) 0 FF2 LD2 1 0 D Q D Q 1 G Output Control (OC) FF1 LD1 0 0 D Q D Q 1 1 G Output Data (OD) n) X 0 FF0 LD0 0 P 1 01 D Q D Q 1 Port Pin ( G Input Data (ID) From Last Cell ClockDR UpdateDR 305 7679H–CAN–08/08

Figure 23-4. General Port Pin Schematic Diagram See Boundary-scan Description for Details! PUExn PUD Q D DDxn QCLR WDx RESET OCxn RDx S U B Pxn Q D A ODxn PORTxn T IDxn QCLR WPx DA RESET SLEEP RRx SYNCHRONIZER RPx D Q D Q PINxn L Q Q CLKI/O PUD: PULLUP DISABLE WDx: WRITE DDRx PUExn: PULLUP ENABLE for pin Pxn RDx: READ DDRx OCxn: OUTPUT CONTROL for pin Pxn WPx: WRITE PORTx ODxn: OUTPUT DATA to pin Pxn RRx: READ PORTx REGISTER IDxn: INPUT DATA from pin Pxn RPx: READ PORTx PIN SLEEP: SLEEP CONTROL CLK I /O : I/O CLOCK 23.6.2 Boundary-scan and the Two-wire Interface The two Two-wire Interface pins SCL and SDA have one additional control signal in the scan- chain; Two-wire Interface Enable – TWIEN. As shown in Figure 23-5, the TWIEN signal enables a tri-state buffer with slew-rate control in parallel with the ordinary digital port pins. A general scan cell as shown in Figure 23-9 is attached to the TWIEN signal. Notes: 1. A separate scan chain for the 50 ns spike filter on the input is not provided. The ordinary scan support for digital port pins suffice for connectivity tests. The only reason for having TWIEN in the scan path, is to be able to disconnect the slew-rate control buffer when doing boundary- scan. 2. Make sure the OC and TWIEN signals are not asserted simultaneously, as this will lead to drive contention. AT90CAN32/64/128 306 7679H–CAN–08/08

AT90CAN32/64/128 Figure 23-5. Additional Scan Signal for the Two-wire Interface PUExn OCxn ODxn Pxn TWIEN SRC Slew-rate limited IDxn 23.6.3 Scanning the RESET Pin The RESET pin accepts 3V or 5V active low logic for standard reset operation, and 12V active high logic for High Voltage Parallel programming. An observe-only cell as shown in Figure 23-6 is inserted both for the 3V or 5V reset signal - RSTT, and the 12V reset signal - RSTHV. Figure 23-6. Observe-only Cell for RESET pin To Next ShiftDR Cell From System Pin To System Logic FF1 0 D Q 1 From ClockDR Previous Cell 23.6.4 Scanning the Clock Pins The AVR devices have many clock options selectable by fuses. These are: Internal RC Oscilla- tor, External Clock, (High Frequency) Crystal Oscillator, Low-frequency Crystal Oscillator, and Ceramic Resonator. Figure 23-7 shows how each oscillator with external connection is supported in the scan chain. The Enable signal is supported with a general Boundary-scan cell, while the Oscillator/clock out- put is attached to an observe-only cell. In addition to the main clock, the Timer2 Oscillator is scanned in the same way. The output from the internal RC Oscillator is not scanned, as this oscillator does not have external connections. 307 7679H–CAN–08/08

Figure 23-7. Boundary-scan Cells for Oscillators and Clock Options XTAL1 / TOSC1 XTAL2 / TOSC2 To Next Oscillator To ShiftDR Cell EXTEST Next ShiftDR Cell From Digital Logic 0 ENABLE OUTPUT To System Logic 1 0 FF1 D Q D Q 0 1 D Q G 1 From ClockDR UpdateDR Previous From ClockDR Cell Previous Cell Table 23-5 summaries the scan registers for the external clock pin XTAL1, oscillators with XTAL1/XTAL2 connections as well as external Timer2 clock pin TOSC1 and 32kHz Timer2 Oscillator. Table 23-5. Scan Signals for the Oscillators(1)(2)(3) Scanned Clock Line Enable Signal Scanned Clock Line Clock Option when not Used EXTCLKEN EXTCLK (XTAL1) External Main Clock 0 External Crystal OSCON OSCCK 1 External Ceramic Resonator OSC32EN OSC32CK Low Freq. External Crystal 1 TOSKON TOSCK 32 kHz Timer2 Oscillator 1 Notes: 1. Do not enable more than one clock source as clock at a time. 2. Scanning an Oscillator output gives unpredictable results as there is a frequency drift between the internal Oscillator and the JTAG TCK clock. If possible, scanning an external clock is preferred. 3. The main clock configuration is programmed by fuses. As a fuse is not changed run-time, the main clock configuration is considered fixed for a given application. The user is advised to scan the same clock option as to be used in the final system. The enable signals are sup- ported in the scan chain because the system logic can disable clock options in sleep modes, thereby disconnecting the Oscillator pins from the scan path if not provided. 23.6.5 Scanning the Analog Comparator The relevant Comparator signals regarding Boundary-scan are shown in Figure 23-8. The Boundary-scan cell from Figure 23-9 is attached to each of these signals. The signals are described in Table 23-6. The Comparator need not be used for pure connectivity testing, since all analog inputs are shared with a digital port pin as well. AT90CAN32/64/128 308 7679H–CAN–08/08

AT90CAN32/64/128 Figure 23-8. Analog Comparator BANDGAP REFERENCE ACBG ACO AC_IDLE ACME ADCEN ADC MULTIPLEXER OUTPUT Figure 23-9. General Boundary-scan cell Used for Signals for Comparator and ADC To Next ShiftDR Cell EXTEST From Digital Logic/ From Analog Ciruitry 0 To Analog Circuitry/ To Digital Logic 1 0 D Q D Q 1 G From ClockDR UpdateDR Previous Cell Table 23-6. Boundary-scan Signals for the Analog Comparator Direction as Recommended Output Values when Signal Seen from the Description Input when Not Recommended Inputs Name Comparator in Use are Used Turns off Analog Depends upon µC code AC_IDLE input Comparator when 1 being executed true Will become input Analog Comparator ACO output to µC code being 0 Output executed Uses output signal Depends upon µC code ACME input from ADC mux when 0 being executed true Bandgap Reference Depends upon µC code ACBG input 0 enable being executed 309 7679H–CAN–08/08

23.6.6 Scanning the ADC Figure 23-10 shows a block diagram of the ADC with all relevant control and observe signals. The Boundary-scan cell from Figure 23-9 is attached to each of these signals. The ADC need not be used for pure connectivity testing, since all analog inputs are shared with a digital port pin as well. Figure 23-10. Analog to Digital Converter VCCREN AREF IREFEN 2.56V To Comparator ref MUXEN_7 PASSEN ADC_7 MUXEN_6 ADC_6 MUXEN_5 ADC_5 MUXEN_4 ADCBGEN ADC_4 SCTEST EXTCH 1.22V PRECH MUXEN_3 ref PRECH ADC_3 AREF MUXEN_2 DACOUT ADC_2 DAC_9..0 MUXEN_1 10-bit DAC + COMP MP MUAXDECN__10 G10 G20 ADCEN - CO ACTEN ADC_0 + + NEGSEL_2 10x 20x ADC_2 - - HOLD NEGSEL_1 ADC_1 GNDEN ST NEGSEL_0 ADC_0 ACLK AMPEN The signals are described briefly in Table 23-7. AT90CAN32/64/128 310 7679H–CAN–08/08

AT90CAN32/64/128 Table 23-7. Boundary-scan Signals for the ADC(1) Direction Output Values when Recommended Signal as Seen Recommended Inputs Description Input Name from the are Used, and CPU is when not in use ADC not Using the ADC COMP Output Comparator Output 0 0 Clock signal to gain ACLK Input stages implemented as 0 0 Switch-cap filters Enable path from gain ACTEN Input 0 0 stages to the comparator Enable Band-gap ADCBGEN Input reference as negative 0 0 input to comparator Power-on signal to the ADCEN Input 0 0 ADC Power-on signal to the AMPEN Input 0 0 gain stages Bit 9 of digital value to DAC_9 Input 1 1 DAC Bit 8 of digital value to DAC_8 Input 0 0 DAC Bit 7 of digital value to DAC_7 Input 0 0 DAC Bit 6 of digital value to DAC_6 Input 0 0 DAC Bit 5 of digital value to DAC_5 Input 0 0 DAC Bit 4 of digital value to DAC_4 Input 0 0 DAC Bit 3 of digital value to DAC_3 Input 0 0 DAC Bit 2 of digital value to DAC_2 Input 0 0 DAC Bit 1 of digital value to DAC_1 Input 0 0 DAC Bit 0 of digital value to DAC_0 Input 0 0 DAC Connect ADC channels 0 EXTCH Input - 3 to by-pass path 1 1 around gain stages G10 Input Enable 10x gain 0 0 G20 Input Enable 20x gain 0 0 311 7679H–CAN–08/08

Table 23-7. Boundary-scan Signals for the ADC(1) (Continued) Direction Output Values when Recommended Signal as Seen Recommended Inputs Description Input Name from the are Used, and CPU is when not in use ADC not Using the ADC Ground the negative GNDEN Input input to comparator when 0 0 true Sample & Hold signal. Sample analog signal when low. Hold signal HOLD Input when high. If gain stages 1 1 are used, this signal must go active when ACLK is high. Enables Band-gap IREFEN Input reference as AREF 0 0 signal to DAC MUXEN_7 Input Input Mux bit 7 0 0 MUXEN_6 Input Input Mux bit 6 0 0 MUXEN_5 Input Input Mux bit 5 0 0 MUXEN_4 Input Input Mux bit 4 0 0 MUXEN_3 Input Input Mux bit 3 0 0 MUXEN_2 Input Input Mux bit 2 0 0 MUXEN_1 Input Input Mux bit 1 0 0 MUXEN_0 Input Input Mux bit 0 1 1 Input Mux for negative NEGSEL_2 Input input for differential 0 0 signal, bit 2 Input Mux for negative NEGSEL_1 Input input for differential 0 0 signal, bit 1 Input Mux for negative NEGSEL_0 Input input for differential 0 0 signal, bit 0 Enable pass-gate of gain PASSEN Input 1 1 stages. Precharge output latch of PRECH Input 1 1 comparator. (Active low) AT90CAN32/64/128 312 7679H–CAN–08/08

AT90CAN32/64/128 Table 23-7. Boundary-scan Signals for the ADC(1) (Continued) Direction Output Values when Recommended Signal as Seen Recommended Inputs Description Input Name from the are Used, and CPU is when not in use ADC not Using the ADC Switch-cap TEST enable. Output from x10 SCTEST Input 0 0 gain stage send out to Port Pin having ADC_4 Output of gain stages will settle faster if this signal ST Input is high first two ACLK 0 0 periods after AMPEN goes high. Selects Vcc as the ACC VCCREN Input 0 0 reference voltage. Note: 1. Incorrect setting of the switches in Figure 23-10 will make signal contention and may damage the part. There are several input choices to the S&H circuitry on the negative input of the out- put comparator in Figure 23-10. Make sure only one path is selected from either one ADC pin, Bandgap reference source, or Ground. If the ADC is not to be used during scan, the recommended input values from Table 23-7 should be used. The user is recommended not to use the Differential Gain stages during scan. Switch- Cap based gain stages require fast operation and accurate timing which is difficult to obtain when used in a scan chain. Details concerning operations of the differential gain stage is there- fore not provided. The AVR ADC is based on the analog circuitry shown in Figure 23-10 with a successive approx- imation algorithm implemented in the digital logic. When used in Boundary-scan, the problem is usually to ensure that an applied analog voltage is measured within some limits. This can easily be done without running a successive approximation algorithm: apply the lower limit on the digi- tal DAC[9:0] lines, make sure the output from the comparator is low, then apply the upper limit on the digital DAC[9:0] lines, and verify the output from the comparator to be high. The ADC need not be used for pure connectivity testing, since all analog inputs are shared with a digital port pin as well. When using the ADC, remember the following • The port pin for the ADC channel in use must be configured to be an input with pull-up disabled to avoid signal contention. • In Normal mode, a dummy conversion (consisting of 10 comparisons) is performed when enabling the ADC. The user is advised to wait at least 200ns after enabling the ADC before controlling/observing any ADC signal, or perform a dummy conversion before using the first result. • The DAC values must be stable at the midpoint value 0x200 when having the HOLD signal low (Sample mode). As an example, consider the task of verifying a 1.5V ± 5% input signal at ADC channel 3 when the power supply is 5.0V and AREF is externally connected to V CC. The lower limit is: [ 1024 * 1.5V * 0.95 / 5V ] = 291 = 0x123 The upper limit is: [ 1024 * 1.5V * 1.05 / 5V ] = 323 = 0x143 313 7679H–CAN–08/08

The recommended values from Table 23-7 are used unless other values are given in the algo- rithm in Table 23-8. Only the DAC and port pin values of the Scan Chain are shown. The column “Actions” describes what JTAG instruction to be used before filling the Boundary-scan Register with the succeeding columns. The verification should be done on the data scanned out when scanning in the data on the same row in the table. Table 23-8. Algorithm for Using the ADC PA3. PA3. PA3. Step Actions ADCEN DAC MUXEN HOLD PRECH Pullup_ Data Control Enable SAMPLE_ 1 1 0x200 0x08 1 1 0 0 0 PRELOAD 2 EXTEST 1 0x200 0x08 0 1 0 0 0 3 1 0x200 0x08 1 1 0 0 0 4 1 0x123 0x08 1 1 0 0 0 5 1 0x123 0x08 1 0 0 0 0 Verify the COMP bit 6 1 0x200 0x08 1 1 0 0 0 scanned out to be 0 7 1 0x200 0x08 0 1 0 0 0 8 1 0x200 0x08 1 1 0 0 0 9 1 0x143 0x08 1 1 0 0 0 10 1 0x143 0x08 1 0 0 0 0 Verify the COMP bit 11 1 0x200 0x08 1 1 0 0 0 scanned out to be 1 Using this algorithm, the timing constraint on the HOLD signal constrains the TCK clock fre- quency. As the algorithm keeps HOLD high for five steps, the TCK clock frequency has to be at least five times the number of scan bits divided by the maximum hold time, t hold,max 23.7 AT90CAN32/64/128 Boundary-scan Order Table 23-9 shows the Scan order between TDI and TDO when the Boundary-scan chain is selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned out. The scan order follows the pin-out order as far as possible. Therefore, the bits of Port A is scanned in the opposite bit order of the other ports. Exceptions from the rules are the Scan chains for the analog circuits, which constitute the most significant bits of the scan chain regardless of which physical pin they are connected to. In Figure 23-3, PXn. Data corresponds to FF0, PXn. Control AT90CAN32/64/128 314 7679H–CAN–08/08

AT90CAN32/64/128 corresponds to FF1, and PXn. Pullup_enable corresponds to FF2. Bit 2, 3, 4, and 5 of Port C is not in the scan chain, since these pins constitute the TAP pins when the JTAG is enabled. Table 23-9. AT90CAN32/64/128 Boundary-scan Order Bit Number Signal Name Comment Module 200 AC_IDLE 199 ACO Comparator 198 ACME 197 AINBG 196 COMP ADC 195 ACLK 194 ACTEN 193 PRIVATE_SIGNAL(1) 192 ADCBGEN 191 ADCEN 190 AMPEN 189 DAC_9 188 DAC_8 187 DAC_7 186 DAC_6 185 DAC_5 184 DAC_4 183 DAC_3 182 DAC_2 181 DAC_1 180 DAC_0 179 EXTCH 178 G10 177 G20 176 GNDEN 175 HOLD 174 IREFEN 173 MUXEN_7 172 MUXEN_6 171 MUXEN_5 170 MUXEN_4 169 MUXEN_3 168 MUXEN_2 167 MUXEN_1 166 MUXEN_0 165 NEGSEL_2 315 7679H–CAN–08/08

Table 23-9. AT90CAN32/64/128 Boundary-scan Order (Continued) Bit Number Signal Name Comment Module 164 NEGSEL_1 ADC 163 NEGSEL_0 162 PASSEN 161 PRECH 160 SCTEST 159 ST 158 VCCREN 157 PE0.Data Port E 156 PE0.Control 155 PE0.Pullup_Enable 154 PE1.Data 153 PE1.Control 152 PE1.Pullup_Enable 151 PE2.Data 150 PE2.Control 149 PE2.Pullup_Enable 148 PE3.Data 147 PE3.Control 146 PE3.Pullup_Enable 145 PE4.Data 144 PE4.Control 143 PE4.Pullup_Enable 142 PE5.Data 141 PE5.Control 140 PE5.Pullup_Enable 139 PE6.Data 138 PE6.Control 137 PE6.Pullup_Enable 136 PE7.Data 135 PE7.Control 134 PE7.Pullup_Enable 133 PB0.Data Port B 132 PB0.Control 131 PB0.Pullup_Enable 130 PB1.Data 129 PB1.Control 128 PB1.Pullup_Enable 127 PB2.Data AT90CAN32/64/128 316 7679H–CAN–08/08

AT90CAN32/64/128 Table 23-9. AT90CAN32/64/128 Boundary-scan Order (Continued) Bit Number Signal Name Comment Module 126 PB2.Control Port B 125 PB2.Pullup_Enable 124 PB3.Data 123 PB3.Control 122 PB3.Pullup_Enable 121 PB4.Data 120 PB4.Control 119 PB4.Pullup_Enable 118 PB5.Data 117 PB5.Control 116 PB5.Pullup_Enable 115 PB6.Data 114 PB6.Control 113 PB6.Pullup_Enable 112 PB7.Data 111 PB7.Control 110 PB7.Pullup_Enable 109 PG3.Data Port G 108 PG3.Control 107 PG3.Pullup_Enable 106 PG4.Data 105 PG4.Control 104 PG4.Pullup_Enable 103 PRIVATE_SIGNAL(1) – 102 RSTT (Observe Only) RESET Logic 101 RSTHV 100 EXTCLKEN Oscillators 99 OSCON 98 OSC32EN 97 TOSKON 96 EXTCLK (XTAL1) 95 OSCCK 94 OSC32CK 93 TOSK 92 PD0.Data Port D 91 PD0.Control 90 PD0.Pullup_Enable 89 PD1.Data 317 7679H–CAN–08/08

Table 23-9. AT90CAN32/64/128 Boundary-scan Order (Continued) Bit Number Signal Name Comment Module 88 PD1.Control Port D 87 PD1.Pullup_Enable 86 PD2.Data 85 PD2.Control 84 PD2.Pullup_Enable 83 PD3.Data 82 PD3.Control 81 PD3.Pullup_Enable 80 PD4.Data 79 PD4.Control 78 PD4.Pullup_Enable 77 PD5.Data 76 PD5.Control 75 PD5.Pullup_Enable 74 PD6.Data 73 PD6.Control 72 PD6.Pullup_Enable 71 PD7.Data 70 PD7.Control 69 PD7.Pullup_Enable 68 PG0.Data Port G 67 PG0.Control 66 PG0.Pullup_Enable 65 PG1.Data 64 PG1.Control 63 PG1.Pullup_Enable 62 PC0.Data Port C 61 PC0.Control 60 PC0.Pullup_Enable 59 PC1.Data 58 PC1.Control 57 PC1.Pullup_Enable 56 PC2.Data 55 PC2.Control 54 PC2.Pullup_Enable 53 PC3.Data 52 PC3.Control 51 PC3.Pullup_Enable AT90CAN32/64/128 318 7679H–CAN–08/08

AT90CAN32/64/128 Table 23-9. AT90CAN32/64/128 Boundary-scan Order (Continued) Bit Number Signal Name Comment Module 50 PC4.Data Port C 49 PC4.Control 48 PC4.Pullup_Enable 47 PC5.Data 46 PC5.Control 45 PC5.Pullup_Enable 44 PC6.Data 43 PC6.Control 42 PC6.Pullup_Enable 41 PC7.Data 40 PC7.Control 39 PC7.Pullup_Enable 38 PG2.Data Port G 37 PG2.Control 36 PG2.Pullup_Enable 35 PA7.Data Port A 34 PA7.Control 33 PA7.Pullup_Enable 32 PA6.Data 31 PA6.Control 30 PA6.Pullup_Enable 29 PA5.Data 28 PA5.Control 27 PA5.Pullup_Enable 26 PA4.Data 25 PA4.Control 24 PA4.Pullup_Enable 23 PA3.Data 22 PA3.Control 21 PA3.Pullup_Enable 20 PA2.Data 19 PA2.Control 18 PA2.Pullup_Enable 17 PA1.Data 16 PA1.Control 15 PA1.Pullup_Enable 14 PA0.Data 13 PA0.Control 319 7679H–CAN–08/08

Table 23-9. AT90CAN32/64/128 Boundary-scan Order (Continued) Bit Number Signal Name Comment Module 12 PA0.Pullup_Enable Port A 11 PF3.Data Port F 10 PF3.Control 9 PF3.Pullup_Enable 8 PF2.Data 7 PF2.Control 6 PF2.Pullup_Enable 5 PF1.Data 4 PF1.Control 3 PF1.Pullup_Enable 2 PF0.Data 1 PF0.Control 0 PF0.Pullup_Enable Notes: 1. PRIVATE_SIGNAL should always be scanned-in as zero. 23.8 Boundary-scan Description Language Files Boundary-scan Description Language (BSDL) files describe Boundary-scan capable devices in a standard format used by automated test-generation software. The order and function of bits in the Boundary-scan Data Register are included in this description. A BSDL file for AT90CAN32/64/128 is available. AT90CAN32/64/128 320 7679H–CAN–08/08

AT90CAN32/64/128 24. Boot Loader Support – Read-While-Write Self-Programming The Boot Loader Support provides a real Read-While-Write Self-Programming mechanism for downloading and uploading program code by the MCU itself. This feature allows flexible applica- tion software updates controlled by the MCU using a Flash-resident Boot Loader program. The Boot Loader program can use any available data interface and associated protocol to read code and write (program) that code into the Flash memory, or read the code from the program mem- ory. The program code within the Boot Loader section has the capability to write into the entire Flash, including the Boot Loader memory. The Boot Loader can thus even modify itself, and it can also erase itself from the code if the feature is not needed anymore. The size of the Boot Loader memory is configurable with fuses and the Boot Loader has two separate sets of Boot Lock bits which can be set independently. This gives the user a unique flexibility to select differ- ent levels of protection. 24.1 Features • Read-While-Write Self-Programming • Flexible Boot Memory Size • High Security (Separate Boot Lock Bits for a Flexible Protection) • Separate Fuse to Select Reset Vector • Optimized Page(1) Size • Code Efficient Algorithm • Efficient Read-Modify-Write Support Note: 1. A page is a section in the Flash consisting of several bytes (see Table 25-11 on page 341) used during programming. The page organization does not affect normal operation. 24.2 Application and Boot Loader Flash Sections The Flash memory is organized in two main sections, the Application section and the Boot Loader section (see Figure 24-2). The size of the different sections is configured by the BOOTSZ Fuses as shown in Table 24-6 on page 334 and Figure 24-2. These two sections can have different level of protection since they have different sets of Lock bits. 24.2.1 AS - Application Section The Application section is the section of the Flash that is used for storing the application code. The protection level for the Application section can be selected by the application Boot Lock bits (BLB02 and BLB01 bits), see Table 24-2 on page 325. The Application section can never store any Boot Loader code since the SPM instruction is disabled when executed from the Application section. 24.2.2 BLS – Boot Loader Section While the Application section is used for storing the application code, the The Boot Loader soft- ware must be located in the BLS since the SPM instruction can initiate a programming when executing from the BLS only. The SPM instruction can access the entire Flash, including the BLS itself. The protection level for the Boot Loader section can be selected by the Boot Loader Lock bits (BLB12 and BLB11 bits), see Table 24-3 on page 325. 24.3 Read-While-Write and No Read-While-Write Flash Sections Whether the CPU supports Read-While-Write or if the CPU is halted during a Boot Loader soft- ware update is dependent on which address that is being programmed. In addition to the two 321 7679H–CAN–08/08

sections that are configurable by the BOOTSZ Fuses as described above, the Flash is also divided into two fixed sections, the Read-While-Write (RWW) section and the No Read-While- Write (NRWW) section. The limit between the RWW- and NRWW sections is given in Table 24- 7 on page 334 and Figure 24-2 on page 324. The main difference between the two sections is: • When erasing or writing a page located inside the RWW section, the NRWW section can be read during the operation. • When erasing or writing a page located inside the NRWW section, the CPU is halted during the entire operation. Note that the user software can never read any code that is located inside the RWW section dur- ing a Boot Loader software operation. The syntax “Read-While-Write section” refers to which section that is being programmed (erased or written), not which section that actually is being read during a Boot Loader software update. 24.3.1 RWW – Read-While-Write Section If a Boot Loader software update is programming a page inside the RWW section, it is possible to read code from the Flash, but only code that is located in the NRWW section. During an on- going programming, the software must ensure that the RWW section never is being read. If the user software is trying to read code that is located inside the RWW section (i.e., by a call/jmp/lpm or an interrupt) during programming, the software might end up in an unknown state. To avoid this, the interrupts should either be disabled or moved to the Boot Loader sec- tion. The Boot Loader section is always located in the NRWW section. The RWW Section Busy bit (RWWSB) in the Store Program Memory Control and Status Register (SPMCSR) will be read as logical one as long as the RWW section is blocked for reading. After a programming is com- pleted, the RWWSB must be cleared by software before reading code located in the RWW section. See “Store Program Memory Control and Status Register – SPMCSR” on page 326. for details on how to clear RWWSB. 24.3.2 NRWW – No Read-While-Write Section The code located in the NRWW section can be read when the Boot Loader software is updating a page in the RWW section. When the Boot Loader code updates the NRWW section, the CPU is halted during the entire Page Erase or Page Write operation. Table 24-1. Read-While-Write Features Which Section Can Which Section does the Z-pointer Is the CPU Read-While-Write be Read During Address During the Programming? Halted? Supported? Programming? RWW Section NRWW Section No Yes NRWW Section None Yes No AT90CAN32/64/128 322 7679H–CAN–08/08

AT90CAN32/64/128 Figure 24-1. Read-While-Write vs. No Read-While-Write Read-While-Write (RWW) Section Z-pointer Addresses NRWW Section Z-pointer Addresses RWW No Read-While-Write Section (NRWW) Section CPU is Halted During the Operation Code Located in NRWW Section Can be Read During the Operation 323 7679H–CAN–08/08

Figure 24-2. Memory Sections Program Memory Program Memory BOOTSZ = ’11’ BOOTSZ = ’10’ 0x0000 0x0000 e e Writ Application Flash Section Writ Application Flash Section While-ection While-ection d-S d-S a a e e R R End RWW End RWW Write Start NRWW Write Start NRWW ead-While-Section Application Flash Section End Application ead-While-Section Application Flash Section ESntadr tA Bpopolitc Laotioander o R Boot Loader Flash Section Start Boot Loader o R Boot Loader Flash Section N Flashend N Flashend Program Memory Program Memory BOOTSZ = ’01’ BOOTSZ = ’00’ 0x0000 0x0000 e e Writ Application Flash Section Writ Application Flash Section While-ection While-ection d-S d-S a a e e R R End RWW End RWW, End Application Write Application Flash Section Start NRWW Write Start NRWW, Start Boot Loader ead-While-Section Boot Loader Flash Section ESntadr tA Bpopolitc Laotioander ead-While-Section Boot Loader Flash Section R R o o N Flash end N Flash end Note: The parameters in the figure above are given in Table 24-6 on page 334. 24.4 Boot Loader Lock Bits If no Boot Loader capability is needed, the entire Flash is available for application code. The Boot Loader has two separate sets of Boot Lock bits which can be set independently. This gives the user a unique flexibility to select different levels of protection. The user can select: • To protect the entire Flash from a software update by the MCU. • To protect only the Boot Loader Flash section from a software update by the MCU. • To protect only the Application Flash section from a software update by the MCU. AT90CAN32/64/128 324 7679H–CAN–08/08

AT90CAN32/64/128 • Allow software update in the entire Flash. See Table 24-2 and Table 24-3 for further details. The Boot Lock bits can be set in software and in Serial or Parallel Programming mode, but they can be cleared by a Chip Erase command only. The general Write Lock (Lock Bit mode 2) does not control the programming of the Flash memory by SPM instruction. Similarly, the general Read/Write Lock (Lock Bit mode 1) does not control reading nor writing by LPM/SPM (Load Program Memory / Store Program Memory) instructions, if it is attempted. Table 24-2. Boot Lock Bit0 Protection Modes (Application Section)(1) Lock Bit BLB02 BLB01 Protection Mode 1 1 1 No restrictions for SPM or LPM accessing the Application section. 2 1 0 SPM is not allowed to write to the Application section. SPM is not allowed to write to the Application section, and LPM executing from the Boot Loader section is not allowed to read 3 0 0 from the Application section. If Interrupt Vectors are placed in the Boot Loader section, interrupts are disabled while executing from the Application section. LPM executing from the Boot Loader section is not allowed to read from the Application section. If Interrupt Vectors are placed 4 0 1 in the Boot Loader section, interrupts are disabled while executing from the Application section. Note: 1. “1” means unprogrammed, “0” means programmed Table 24-3. Boot Lock Bit1 Protection Modes (Boot Loader Section)(1) Lock Bit BLB12 BLB11 Protection Mode No restrictions for SPM or LPM accessing the Boot Loader 1 1 1 section. 2 1 0 SPM is not allowed to write to the Boot Loader section. SPM is not allowed to write to the Boot Loader section, and LPM executing from the Application section is not allowed to read from 3 0 0 the Boot Loader section. If Interrupt Vectors are placed in the Application section, interrupts are disabled while executing from the Boot Loader section. LPM executing from the Application section is not allowed to read from the Boot Loader section. If Interrupt Vectors are placed in the 4 0 1 Application section, interrupts are disabled while executing from the Boot Loader section. Note: 1. “1” means unprogrammed, “0” means programmed 24.5 Entering the Boot Loader Program Entering the Boot Loader takes place by a jump or call from the application program. This may be initiated by a trigger such as a command received via USART, or SPI interface. Alternatively, the Boot Reset Fuse can be programmed so that the Reset Vector is pointing to the Boot Flash start address after a reset. In this case, the Boot Loader is started after a reset. After the applica- tion code is loaded, the program can start executing the application code. Note that the fuses cannot be changed by the MCU itself. This means that once the Boot Reset Fuse is pro- 325 7679H–CAN–08/08

grammed, the Reset Vector will always point to the Boot Loader Reset and the fuse can only be changed through the serial or parallel programming interface. Table 24-4. Boot Reset Fuse(1) BOOTRST Reset Address 1 Reset Vector = Application Reset (address 0x0000) 0 Reset Vector = Boot Loader Reset (see Table 24-6 on page 334) Note: 1. “1” means unprogrammed, “0” means programmed 24.5.1 Store Program Memory Control and Status Register – SPMCSR The Store Program Memory Control and Status Register contains the control bits needed to con- trol the Boot Loader operations. Bit 7 6 5 4 3 2 1 0 SPMIE RWWSB – RWWSRE BLBSET PGWRT PGERS SPMEN SPMCSR Read/Write R/W R R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 • Bit 7 – SPMIE: SPM Interrupt Enable When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the SPMEN bit in the SPMCSR Register is cleared. • Bit 6 – RWWSB: Read-While-Write Section Busy When a Self-Programming (Page Erase or Page Write) operation to the RWW section is initi- ated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW section cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to one after a Self-Programming operation is completed. Alternatively the RWWSB bit will automatically be cleared if a page load operation is initiated. • Bit 5 – Res: Reserved Bit This bit is a reserved bit in the AT90CAN32/64/128 and always read as zero. • Bit 4 – RWWSRE: Read-While-Write Section Read Enable When programming (Page Erase or Page Write) to the RWW section, the RWW section is blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW section, the user software must wait until the programming is completed (SPMEN will be cleared). Then, if the RWWSRE bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles re-enables the RWW section. The RWW section cannot be re-enabled while the Flash is busy with a Page Erase or a Page Write (SPMEN is set). If the RWWSRE bit is writ- ten while the Flash is being loaded, the Flash load operation will abort and the data loaded will be lost. • Bit 3 – BLBSET: Boot Lock Bit Set If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles sets Boot Lock bits, according to the data in R0. The data in R1 and the address in the Z- pointer are ignored. The BLBSET bit will automatically be cleared upon completion of the Lock bit set, or if no SPM instruction is executed within four clock cycles. AT90CAN32/64/128 326 7679H–CAN–08/08

AT90CAN32/64/128 An LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCSR Reg- ister, will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the destination register. See “Reading the Fuse and Lock Bits from Software” on page 330 for details. • Bit 2 – PGWRT: Page Write If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Write, with the data stored in the temporary buffer. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit will auto-clear upon completion of a Page Write, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire Page Write operation if the NRWW section is addressed. • Bit 1 – PGERS: Page Erase If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles executes Page Erase. The page address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a Page Erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire Page Write operation if the NRWW section is addressed. • Bit 0 – SPMEN: Store Program Memory Enable This bit enables the SPM instruction for the next four clock cycles. If written to one together with either RWWSRE, BLBSET, PGWRT’ or PGERS, the following SPM instruction will have a spe- cial meaning, see description above. If only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer. The LSB of the Z-pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed within four clock cycles. During Page Erase and Page Write, the SPMEN bit remains high until the operation is completed. Writing any other combination than “10001”, “01001”, “00101”, “00011” or “00001” in the lower five bits will have no effect. 24.6 Addressing the Flash During Self-Programming The Z-pointer is used to address the SPM commands. The Z pointer consists of the Z-registers ZL and ZH in the register file, and RAMPZ in the I/O space. The number of bits actually used is implementation dependent. Note that the RAMPZ register is only implemented when the pro- gram space is larger than 64K bytes. Bit 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 RAMPZ – – – – – – – RAMPZ0 ZH (R31) Z15 Z14 Z13 Z12 Z11 Z10 Z9 Z8 ZL (R30) Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 7 6 5 4 3 2 1 0 Since the Flash is organized in pages (see Table 25-11 on page 341), the Program Counter can be treated as having two different sections. One section, consisting of the least significant bits, is addressing the words within a page, while the most significant bits are addressing the pages. This is shown in Figure 24-3. Note that the page erase and page write operations are addressed independently. Therefore it is of major importance that the Boot Loader software addresses the 327 7679H–CAN–08/08

same page in both the page erase and page write operation. Once a programming operation is initiated, the address is latched and the Z-pointer can be used for other operations. The (E)LPM instruction use the Z-pointer to store the address. Since this instruction addresses the Flash byte-by-byte, also bit Z0 of the Z-pointer is used. Figure 24-3. Addressing the Flash During SPM(1) BIT 23 ZPCMSB ZPAGEMSB 1 0 0 Z - POINTER PCMSB PAGEMSB PROGRAM COUNTER PCPAGE PCWORD PAGE ADDRESS WORD ADDRESS WITHIN THE FLASH WITHIN A PAGE PROGRAM MEMORY PAGE PCWORD[PAGEMSB:0]: PAGE INSTRUCTION WORD 00 01 02 PAGEEND Note: 1. The different variables used in Figure 24-3 are listed in Table 24-8 on page 335. 24.7 Self-Programming the Flash The program memory is updated in a page by page fashion. Before programming a page with the data stored in the temporary page buffer, the page must be erased. The temporary page buffer is filled one word at a time using SPM and the buffer can be filled either before the Page Erase command or between a Page Erase and a Page Write operation: Alternative 1: fill the buffer before a Page Erase • Fill temporary page buffer • Perform a Page Erase • Perform a Page Write Alternative 2: fill the buffer after Page Erase • Perform a Page Erase • Fill temporary page buffer • Perform a Page Write AT90CAN32/64/128 328 7679H–CAN–08/08

AT90CAN32/64/128 If only a part of the page needs to be changed, the rest of the page must be stored (for example in the temporary page buffer) before the erase, and then be rewritten. When using alternative 1, the Boot Loader provides an effective Read-Modify-Write feature which allows the user software to first read the page, do the necessary changes, and then write back the modified data. If alter- native 2 is used, it is not possible to read the old data while loading since the page is already erased. The temporary page buffer can be accessed in a random sequence. It is essential that the page address used in both the Page Erase and Page Write operation is addressing the same page. See “Simple Assembly Code Example for a Boot Loader” on page 332 for an assembly code example. 24.7.1 Performing Page Erase by SPM To execute Page Erase, set up the address in the Z-pointer, write “X0000011” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE in the Z-register. Other bits in the Z-pointer will be ignored during this operation. • Page Erase to the RWW section: The NRWW section can be read during the Page Erase. • Page Erase to the NRWW section: The CPU is halted during the operation. 24.7.2 Filling the Temporary Buffer (Page Loading) To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write “00000001” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The content of PCWORD in the Z-register is used to address the data in the temporary buffer. The temporary buffer will auto-erase after a Page Write operation or by writing the RWWSRE bit in SPMCSR. It is also erased after a system reset. Note that it is not possible to write more than one time to each address without erasing the temporary buffer. If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be lost. 24.7.3 Performing a Page Write To execute Page Write, set up the address in the Z-pointer, write “X0000101” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE. Other bits in the Z-pointer will be ignored during this operation. • Page Write to the RWW section: The NRWW section can be read during the Page Write. • Page Write to the NRWW section: The CPU is halted during the operation. 24.7.4 Using the SPM Interrupt If the SPM interrupt is enabled, the SPM interrupt will generate a constant interrupt when the SPMEN bit in SPMCSR is cleared. This means that the interrupt can be used instead of polling the SPMCSR Register in software. When using the SPM interrupt, the Interrupt Vectors should be moved to the BLS section to avoid that an interrupt is accessing the RWW section when it is blocked for reading. How to move the interrupts is described in “Interrupts” on page 60. 24.7.5 Consideration While Updating BLS Special care must be taken if the user allows the Boot Loader section to be updated by leaving Boot Lock bit11 unprogrammed. An accidental write to the Boot Loader itself can corrupt the entire Boot Loader, and further software updates might be impossible. If it is not necessary to 329 7679H–CAN–08/08

change the Boot Loader software itself, it is recommended to program the Boot Lock bit11 to protect the Boot Loader software from any internal software changes. 24.7.6 Prevent Reading the RWW Section During Self-Programming During Self-Programming (either Page Erase or Page Write), the RWW section is always blocked for reading. The user software itself must prevent that this section is addressed during the self programming operation. The RWWSB in the SPMCSR will be set as long as the RWW section is busy. During Self-Programming the Interrupt Vector table should be moved to the BLS as described in “Interrupts” on page 60, or the interrupts must be disabled. Before addressing the RWW section after the programming is completed, the user software must clear the RWWSB by writing the RWWSRE. See “Simple Assembly Code Example for a Boot Loader” on page 332 for an example. 24.7.7 Setting the Boot Loader Lock Bits by SPM To set the Boot Loader Lock bits, write the desired data to R0, write “X0001001” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The only accessible Lock bits are the Boot Lock bits that may prevent the Application and Boot Loader section from any soft- ware update by the MCU. Bit 7 6 5 4 3 2 1 0 R0 1 1 BLB12 BLB11 BLB02 BLB01 1 1 See Table 24-2 and Table 24-3 for how the different settings of the Boot Loader bits affect the Flash access. If bits 5..2 in R0 are cleared (zero), the corresponding Boot Lock bit will be programmed if an SPM instruction is executed within four cycles after BLBSET and SPMEN are set in SPMCSR. The Z-pointer is don’t care during this operation, but for future compatibility it is recommended to load the Z-pointer with 0x0001 (same as used for reading the Lock bits). For future compatibility it is also recommended to set bits 7, 6, 1, and 0 in R0 to “1” when writing the Lock bits. When programming the Lock bits the entire Flash can be read during the operation. 24.7.8 EEPROM Write Prevents Writing to SPMCSR Note that an EEPROM write operation will block all software programming to Flash. Reading the Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It is recommended that the user checks the status bit (EEWE) in the EECR Register and verifies that the bit is cleared before writing to the SPMCSR Register. 24.7.9 Reading the Fuse and Lock Bits from Software It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the Z-pointer with 0x0001 and set the BLBSET and SPMEN bits in SPMCSR. When an LPM instruc- tion is executed within three CPU cycles after the BLBSET and SPMEN bits are set in SPMCSR, the value of the Lock bits will be loaded in the destination register. The BLBSET and SPMEN bits will auto-clear upon completion of reading the Lock bits or if no LPM instruction is executed within three CPU cycles or no SPM instruction is executed within four CPU cycles. When BLB- SET and SPMEN are cleared, LPM will work as described in the Instruction set Manual. Bit 7 6 5 4 3 2 1 0 Rd (Z=0x0001) – – BLB12 BLB11 BLB02 BLB01 LB2 LB1 AT90CAN32/64/128 330 7679H–CAN–08/08

AT90CAN32/64/128 The algorithm for reading the Fuse Low byte is similar to the one described above for reading the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and set the BLBSET and SPMEN bits in SPMCSR. When an LPM instruction is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the value of the Fuse Low byte (FLB) will be loaded in the destination register as shown below. Refer to Table 25-5 on page 338 for a detailed description and mapping of the Fuse Low byte. Bit 7 6 5 4 3 2 1 0 Rd (Z=0x0000) FLB7 FLB6 FLB5 FLB4 FLB3 FLB2 FLB1 FLB0 Similarly, when reading the Fuse High byte, load 0x0003 in the Z-pointer. When an LPM instruc- tion is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the value of the Fuse High byte (FHB) will be loaded in the destination register as shown below. Refer to Table 25-4 on page 337 for detailed description and mapping of the Fuse High byte. Bit 7 6 5 4 3 2 1 0 Rd (Z=0x0003) FHB7 FHB6 FHB5 FHB4 FHB3 FHB2 FHB1 FHB0 When reading the Extended Fuse byte, load 0x0002 in the Z-pointer. When an LPM instruction is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the value of the Extended Fuse byte (EFB) will be loaded in the destination register as shown below. Refer to Table 25-3 on page 337 for detailed description and mapping of the Extended Fuse byte. Bit 7 6 5 4 3 2 1 0 Rd (Z=0x0002) – – – – EFB3 EFB2 EFB1 EFB0 Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are unprogrammed, will be read as one. 24.7.10 Preventing Flash Corruption During periods of low V , the Flash program can be corrupted because the supply voltage is CC too low for the CPU and the Flash to operate properly. These issues are the same as for board level systems using the Flash, and the same design solutions should be applied. A Flash program corruption can be caused by two situations when the voltage is too low. • First, a regular write sequence to the Flash requires a minimum voltage to operate correctly. • Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions is too low. Flash corruption can easily be avoided by following these design recommendations (one is sufficient): 1. If there is no need for a Boot Loader update in the system, program the Boot Loader Lock bits to prevent any Boot Loader software updates. 2. Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD) if the operating voltage matches the detection level. If not, an external low V reset protection circuit CC can be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient. 331 7679H–CAN–08/08

3. Keep the AVR core in Power-down sleep mode during periods of low V . This will pre- CC vent the CPU from attempting to decode and execute instructions, effectively protecting the SPMCSR Register and thus the Flash from unintentional writes. 24.7.11 Programming Time for Flash when Using SPM The calibrated RC Oscillator is used to time Flash accesses. Table 24-5 shows the typical pro- gramming time for Flash accesses from the CPU. Table 24-5. SPM Programming Time Symbol Min Programming Time Max Programming Time Flash write (Page Erase, Page Write, and 3.7 ms 4.5 ms write Lock bits by SPM) 24.7.12 Simple Assembly Code Example for a Boot Loader ;- the routine writes one page of data from RAM to Flash ; the first data location in RAM is pointed to by the Y-pointer ; the first data location in Flash is pointed to by the Z-pointer ;- error handling is not included ;- the routine must be placed inside the Boot space ; (at least the Do_spm sub routine). Only code inside NRWW section can ; be read during Self-Programming (Page Erase and Page Write). ;- registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24), ; loophi (r25), spmcsrval (r20) ; storing and restoring of registers is not included in the routine ; register usage can be optimized at the expense of code size ;- it is assumed that either the interrupt table is moved to the Boot ; loader section or that the interrupts are disabled. .equ PAGESIZEB = PAGESIZE*2 ;PAGESIZEB is page size in BYTES, not words .org SMALLBOOTSTART Write_page: ; Page Erase ldi spmcsrval, (1<<PGERS) | (1<<SPMEN) call Do_spm ; re-enable the RWW section ldi spmcsrval, (1<<RWWSRE) | (1<<SPMEN) call Do_spm ; transfer data from RAM to Flash page buffer ldi looplo, low(PAGESIZEB) ;init loop variable ldi loophi, high(PAGESIZEB) ;not required for PAGESIZEB<=256 Wrloop: ld r0, Y+ ld r1, Y+ ldi spmcsrval, (1<<SPMEN) call Do_spm adiw ZH:ZL, 2 sbiw loophi:looplo, 2 ;use subi for PAGESIZEB<=256 brne Wrloop ; execute Page Write subi ZL, low(PAGESIZEB) ;restore pointer AT90CAN32/64/128 332 7679H–CAN–08/08

AT90CAN32/64/128 sbci ZH, high(PAGESIZEB) ;not required for PAGESIZEB<=256 ldi spmcsrval, (1<<PGWRT) | (1<<SPMEN) call Do_spm ; re-enable the RWW section ldi spmcsrval, (1<<RWWSRE) | (1<<SPMEN) call Do_spm ; read back and check, optional ldi looplo, low(PAGESIZEB) ;init loop variable ldi loophi, high(PAGESIZEB) ;not required for PAGESIZEB<=256 subi YL, low(PAGESIZEB) ;restore pointer sbci YH, high(PAGESIZEB) Rdloop: lpm r0, Z+ ld r1, Y+ cpse r0, r1 jmp Error sbiw loophi:looplo, 1 ;use subi for PAGESIZEB<=256 brne Rdloop ; return to RWW section ; verify that RWW section is safe to read Return: in temp1, SPMCSR sbrs temp1, RWWSB ; If RWWSB is set, the RWW section is not ready yet ret ; re-enable the RWW section ldi spmcsrval, (1<<RWWSRE) | (1<<SPMEN) call Do_spm rjmp Return Do_spm: ; check for previous SPM complete Wait_spm: in temp1, SPMCSR sbrc temp1, SPMEN rjmp Wait_spm ; input: spmcsrval determines SPM action ; disable interrupts if enabled, store status in temp2, SREG cli ; check that no EEPROM write access is present Wait_ee: sbic EECR, EEWE rjmp Wait_ee ; SPM timed sequence out SPMCSR, spmcsrval spm ; restore SREG (to enable interrupts if originally enabled) out SREG, temp2 ret 333 7679H–CAN–08/08

24.7.13 Boot Loader Parameters In Table 24-6 through Table 24-8, the parameters used in the description of the Self-Program- ming are given. Table 24-6. Boot Size Configuration (Word Addresses)(1) Device BOOTSZ1 BOOTSZ0 Boot Size Pages ApplicationFlash Section Boot LoaderFlash Section EndApplication Section BootReset Address (Start BootLoader Section) 1 1 512 words 4 0x0000 - 0x3DFF 0x3E00 - 0x3FFF 0x3DFF 0x3E00 2 3 N 1 0 1024 words 8 0x0000 - 0x3BFF 0x3C00 - 0x3FFF 0x3BFF 0x3C00 A C 0 0 1 2048 words 16 0x0000 - 0x37FF 0x3800 - 0x3FFF 0x37FF 0x3800 9 T A 0 0 4096 words 32 0x0000 - 0x2FFF 0x3000 - 0x3FFF 0x2FFF 0x3000 1 1 512 words 4 0x0000 - 0x7DFF 0x7E00 - 0x7FFF 0x7DFF 0x7E00 4 6 N 1 0 1024 words 8 0x0000 - 0x7BFF 0x7C00 - 0x7FFF 0x7BFF 0x7C00 A C 0 0 1 2048 words 16 0x0000 - 0x77FF 0x7800 - 0x7FFF 0x77FF 0x7800 9 T A 0 0 4096 words 32 0x0000 - 0x6FFF 0x7000 - 0x7FFF 0x6FFF 0x7000 8 1 1 512 words 4 0x0000 - 0xFDFF 0xFE00 - 0xFFFF 0xFDFF 0xFE00 2 1 N 1 0 1024 words 8 0x0000 - 0xFBFF 0xFC00 - 0xFFFF 0xFBFF 0xFC00 A C 0 0 1 2048 words 16 0x0000 - 0xF7FF 0xF800 - 0xFFFF 0xF7FF 0xF800 9 T A 0 0 4096 words 32 0x0000 - 0xEFFF 0xF000 - 0xFFFF 0xEFFF 0xF000 Notes: 1. The different BOOTSZ Fuse configurations are shown in Figure 24-2 Table 24-7. Read-While-Write Limit (Word Addresses)(1) Device Section Pages Address Read-While-Write section (RWW) 96 0x0000 - 0x2FFF AT90CAN32 No Read-While-Write section (NRWW) 32 0x3000 - 0x3FFF Read-While-Write section (RWW) 224 0x0000 - 0x6FFF AT90CAN64 No Read-While-Write section (NRWW) 32 0x7000 - 0x7FFF Read-While-Write section (RWW) 480 0x0000 - 0xEFFF AT90CAN128 No Read-While-Write section (NRWW) 32 0xF000 - 0xFFFF Notes: 1. For details about these two section, see “NRWW – No Read-While-Write Section” on page 322 and “RWW – Read-While-Write Section” on page 322. AT90CAN32/64/128 334 7679H–CAN–08/08

AT90CAN32/64/128 Table 24-8. Explanation of Different Variables Used in Figure 24-3 on page 328 and the Mapping to the Z-Pointer(1) Device ariableName ariableValue CorrZe-svpaoluneding Description(2) V V PCMSB 13 Most significant bit in the program counter. (The program counter is 14 bits PC[13:0]) Most significant bit which is used to address the words within one page (128 words in a page PAGEMSB 6 requires 7 bits PC [6:0]). 2 3 Bit in Z-register that is mapped to PCMSB. Because Z0 is not used, the ZPCMSB equals N ZPCMSB Z14 A PCMSB + 1. C 0 Bit in Z-register that is mapped to PAGEMSB. Because Z0 is not used, the ZPAGEMSB 9 ZPAGEMSB Z7 T equals PAGEMSB + 1. A PCPAGE PC[13:7] Z14:Z7 Program counter page address: Page select, for Page Erase and Page Write. Program counter word address: Word select, for filling temporary buffer (must be zero during PCWORD PC[6:0] Z7:Z1 PAGE WRITE operation). PCMSB 14 Most significant bit in the program counter. (The program counter is 15 bits PC[14:0]) Most significant bit which is used to address the words within one page (128 words in a page PAGEMSB 6 requires 7 bits PC [6:0]). 4 6 Bit in Z-register that is mapped to PCMSB. Because Z0 is not used, the ZPCMSB equals N ZPCMSB Z15 A PCMSB + 1. C 0 Bit in Z-register that is mapped to PAGEMSB. Because Z0 is not used, the ZPAGEMSB 9 ZPAGEMSB Z7 T equals PAGEMSB + 1. A PCPAGE PC[14:7] Z15:Z7 Program counter page address: Page select, for Page Erase and Page Write. Program counter word address: Word select, for filling temporary buffer (must be zero during PCWORD PC[6:0] Z7:Z1 PAGE WRITE operation). PCMSB 15 Most significant bit in the program counter. (The program counter is 16 bits PC[15:0]) Most significant bit which is used to address the words within one page (128 words in a page PAGEMSB 6 requires 7 bits PC [6:0]). 8 2 Bit in Z-register that is mapped to PCMSB. Because Z0 is not used, the ZPCMSB equals 1 ZPCMSB Z16(3) N PCMSB + 1. A C 0 Bit in Z-register that is mapped to PAGEMSB. Because Z0 is not used, the ZPAGEMSB 9 ZPAGEMSB Z7 T equals PAGEMSB + 1. A PCPAGE PC[15:7] Z16(3):Z7 Program counter page address: Page select, for Page Erase and Page Write. Program counter word address: Word select, for filling temporary buffer (must be zero during PCWORD PC[6:0] Z7:Z1 PAGE WRITE operation). Notes: 1. See “Addressing the Flash During Self-Programming” on page 327 for details about the use of Z-pointer during self-programming. 2. Z0: should be zero for all SPM commands, byte select for the (E)LPM instruction. 3. The Z-register is only 16 bits wide. Bit 16 is located in RAMPZ register in I/O map. 335 7679H–CAN–08/08

25. Memory Programming 25.1 Program and Data Memory Lock Bits The AT90CAN32/64/128 provides six Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 25-2. The Lock bits can only be erased to “1” with the Chip Erase command. Table 25-1. Lock Bit Byte(1) Lock Bit Byte Bit No Description Default Value 7 – 1 (unprogrammed) 6 – 1 (unprogrammed) BLB12 5 Boot Lock bit 1 (unprogrammed) BLB11 4 Boot Lock bit 1 (unprogrammed) BLB02 3 Boot Lock bit 1 (unprogrammed) BLB01 2 Boot Lock bit 1 (unprogrammed) LB2 1 Lock bit 1 (unprogrammed) LB1 0 Lock bit 1 (unprogrammed) Note: 1. “1” means unprogrammed, “0” means programmed. Table 25-2. Lock Bit Protection Modes(1)(2) Memory Lock Bits Protection Type LB Mode LB2 LB1 1 1 1 No memory lock features enabled. Further programming of the Flash and EEPROM is disabled in Parallel and 2 1 0 Serial Programming mode. The Fuse bits are locked in both Serial and Parallel Programming mode.(1) Further programming and verification of the Flash and EEPROM is disabled 3 0 0 in Parallel and Serial Programming mode. The Boot Lock bits and Fuse bits are locked in both Serial and Parallel Programming mode.(1) BLB0 Mode BLB02 BLB01 No restrictions for SPM (Store Program Memory) or LPM (Load Program 1 1 1 Memory) accessing the Application section. 2 1 0 SPM is not allowed to write to the Application section. SPM is not allowed to write to the Application section, and LPM executing from the Boot Loader section is not allowed to read from the Application 3 0 0 section. If Interrupt Vectors are placed in the Boot Loader section, interrupts are disabled while executing from the Application section. LPM executing from the Boot Loader section is not allowed to read from the 4 0 1 Application section. If Interrupt Vectors are placed in the Boot Loader section, interrupts are disabled while executing from the Application section. BLB1 Mode BLB12 BLB11 1 1 1 No restrictions for SPM or LPM accessing the Boot Loader section. AT90CAN32/64/128 336 7679H–CAN–08/08

AT90CAN32/64/128 Table 25-2. Lock Bit Protection Modes(1)(2) (Continued) Memory Lock Bits Protection Type 2 1 0 SPM is not allowed to write to the Boot Loader section. SPM is not allowed to write to the Boot Loader section, and LPM executing from the Application section is not allowed to read from the Boot Loader 3 0 0 section. If Interrupt Vectors are placed in the Application section, interrupts are disabled while executing from the Boot Loader section. LPM executing from the Application section is not allowed to read from the Boot Loader section. If Interrupt Vectors are placed in the Application 4 0 1 section, interrupts are disabled while executing from the Boot Loader section. Notes: 1. Program the Fuse bits and Boot Lock bits before programming the LB1 and LB2. 2. “1” means unprogrammed, “0” means programmed 25.2 Fuse Bits The AT90CAN32/64/128 has three Fuse bytes. Table 25-3, Table 25-4 and Table 25-5 describe briefly the functionality of all the fuses and how they are mapped into the Fuse bytes. Note that the fuses are read as logical zero, “0”, if they are programmed. Table 25-3. Extended Fuse Byte Fuse Extended Byte Bit No Description Default Value – 7 – 1 – 6 – 1 – 5 – 1 – 4 – 1 BODLEVEL2(1) 3 Brown-out Detector trigger level 1 (unprogrammed) BODLEVEL1(1) 2 Brown-out Detector trigger level 1 (unprogrammed) BODLEVEL0(1) 1 Brown-out Detector trigger level 1 (unprogrammed) TA0SEL 0 (Reserved for factory tests) 1 (unprogrammed) Note: 1. See Table 7-2 on page 54 for BODLEVEL Fuse decoding. Table 25-4. Fuse High Byte Fuse High Byte Bit No Description Default Value OCDEN(4) 7 Enable OCD 1 (unprogrammed, OCD disabled) JTAGEN(5) 6 Enable JTAG 0 (programmed, JTAG enabled) Enable Serial Program and SPIEN(1) 5 0 (programmed, SPI prog. enabled) Data Downloading WDTON(3) 4 Watchdog Timer always on 1 (unprogrammed) EEPROM memory is preserved EESAVE 3 1 (unprogrammed, EEPROM not preserved) through the Chip Erase 337 7679H–CAN–08/08

Table 25-4. Fuse High Byte (Continued) Fuse High Byte Bit No Description Default Value Select Boot Size(6) BOOTSZ1 2 0 (programmed)(2) (see Table 24-6 for details) Select Boot Size(6) BOOTSZ0 1 0 (programmed)(2) (see Table 24-6 for details) Select Reset Vector(7) BOOTRST 0 1 (unprogrammed) (see Table 24-6 for details) Notes: 1. The SPIEN Fuse is not accessible in serial programming mode. 2. The default value of BOOTSZ1..0 results in maximum Boot Size. See Table 24-6 on page 334 for details. 3. See “Watchdog Timer Control Register – WDTCR” on page 58 for details. 4. Never ship a product with the OCDEN Fuse programmed regardless of the setting of Lock bits and JTAGEN Fuse. A programmed OCDEN Fuse enables some parts of the clock system to be running in all sleep modes. This may increase the power consumption. 5. If the JTAG interface is left unconnected, the JTAGEN fuse should if possible be disabled. This to avoid static current at the TDO pin in the JTAG interface. 6. The boot sizes of all the AVR CAN microcontrollers are identical. 7. Due to the flash size, the boot reset address differs from one AVR CAN microcontroller to another. Table 25-5. Fuse Low Byte Fuse Low Byte Bit No Description Default Value CKDIV8(4) 7 Divide clock by 8 0 (programmed) CKOUT(3) 6 Clock output 1 (unprogrammed) SUT1 5 Select start-up time 1 (unprogrammed)(1) SUT0 4 Select start-up time 0 (programmed)(1) CKSEL3 3 Select Clock source 0 (programmed)(2) CKSEL2 2 Select Clock source 0 (programmed)(2) CKSEL1 1 Select Clock source 1 (unprogrammed)(2) CKSEL0 0 Select Clock source 0 (programmed)(2) Notes: 1. The default value of SUT1..0 results in maximum start-up time for the default clock source. See Table 5-8 on page 42 for details. 2. The default setting of CKSEL3..0 results in internal RC Oscillator @ 8 MHz. See Table 5-1 on page 38 for details. 3. The CKOUT Fuse allow the system clock to be output on Port PC7. See “Clock Output Buffer” on page 43 for details. 4. See “System Clock Prescaler” on page 44 for details. The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits are locked if Lock bit1 (LB1) is programmed. Program the Fuse bits before programming the Lock bits. 25.2.1 Latching of Fuses The fuse values are latched when the device enters programming mode and changes of the fuse values will have no effect until the part leaves Programming mode. This does not apply to the EESAVE Fuse which will take effect once it is programmed. The fuses are also latched on Power-up in Normal mode. AT90CAN32/64/128 338 7679H–CAN–08/08

AT90CAN32/64/128 25.3 Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in both serial and parallel mode, also when the device is locked. The three bytes reside in a separate address space. Table 25-6. Signature Bytes Device Address Value Signature Byte Description 0 0x1E Indicates manufactured by Atmel AT90CAN32 1 0x95 Indicates 32 KB Flash memory 2 0x81 Indicates AT90CAN32 device when address 1 contains 0x95 0 0x1E Indicates manufactured by Atmel AT90CAN64 1 0x96 Indicates 64 KB Flash memory 2 0x81 Indicates AT90CAN64 device when address 1 contains 0x96 0 0x1E Indicates manufactured by Atmel AT90CAN128 1 0x97 Indicates 128 KB Flash memory 2 0x81 Indicates AT90CAN128 device when address 1 contains 0x97 25.4 Calibration Byte The AT90CAN32/64/128 has a byte calibration value for the internal RC Oscillator. This byte resides in the high byte of address 0x000 in the signature address space. During reset, this byte is automatically written into the OSCCAL Register to ensure correct frequency of the calibrated RC Oscillator. 25.5 Parallel Programming Overview This section describes how to parallel program and verify Flash Program memory, EEPROM Data memory, Memory Lock bits, and Fuse bits in the AT90CAN32/64/128. Pulses are assumed to be at least 250 ns unless otherwise noted. 25.5.1 Signal Names In this section, some pins of the AT90CAN32/64/128 are referenced by signal names describing their functionality during parallel programming, see Figure 25-1 and Table 25-7. Pins not described in the following table are referenced by pin names. The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse. The bit coding is shown in Table 25-9. When pulsing WR or OE, the command loaded determines the action executed. The different Commands are shown in Table 25-10. 339 7679H–CAN–08/08

Figure 25-1. Parallel Programming +2.7 - +5.5V RDY/BSY PD1 VCC OE PD2 +2.7 - +5.5V WR PD3 AVCC BS1 PD4 XA0 PD5 XA1 PD6 PB7 - PB0 DATA PAGEL PD7 +12 V RESET BS2 PA0 XTAL1 GND 25.5.2 Pin Mapping Table 25-7. Pin Name Mapping Signal Name in Pin Name I/O Function Programming Mode 0: Device is busy programming, RDY/BSY PD1 O 1: Device is ready for new command. OE PD2 I Output Enable (Active low). WR PD3 I Write Pulse (Active low). BS1 PD4 I Byte Select 1 (“0” selects low byte, “1” selects high byte). XA0 PD5 I XTAL Action Bit 0 XA1 PD6 I XTAL Action Bit 1 PAGEL PD7 I Program Memory and EEPROM data Page Load. BS2 PA0 I Byte Select 2 (“0” selects low byte, “1” selects 2’nd high byte). DATA PB7-0 I/O Bi-directional Data bus (Output when OE is low). 25.5.3 Commands Table 25-8. Pin Values Used to Enter Programming Mode Pin Symbol Value PAGEL Prog_enable[3] 0 XA1 Prog_enable[2] 0 XA0 Prog_enable[1] 0 BS1 Prog_enable[0] 0 AT90CAN32/64/128 340 7679H–CAN–08/08

AT90CAN32/64/128 Table 25-9. XA1 and XA0 Coding XA1 XA0 Action when XTAL1 is Pulsed 0 0 Load Flash or EEPROM Address (High or low address byte determined by BS1). 0 1 Load Data (High or Low data byte for Flash determined by BS1). 1 0 Load Command 1 1 No Action, Idle Table 25-10. Command Byte Bit Coding Command Byte Command Executed 1000 0000 Chip Erase 0100 0000 Write Fuse bits 0010 0000 Write Lock bits 0001 0000 Write Flash 0001 0001 Write EEPROM 0000 1000 Read Signature bytes and Calibration byte 0000 0100 Read Fuse and Lock bits 0000 0010 Read Flash 0000 0011 Read EEPROM 25.5.4 Parameters Table 25-11. No. of Words in a Page and No. of Pages in the Flash Device Flash Size Page Size PCWORD No. of Pages PCPAGE PCMSB AT90CAN32 16K words 128 words PC[6:0] 128 PC[13:7] 13 AT90CAN64 32K words 128 words PC[6:0] 256 PC[14:7] 14 AT90CAN128 64K words 128 words PC[6:0] 512 PC[15:7] 15 Table 25-12. No. of Words in a Page and No. of Pages in the EEPROM Device EEPROM Size Page Size PCWORD No. of Pages PCPAGE EEAMSB AT90CAN32 1K bytes 8 bytes EEA[2:0] 128 EEA[9:3] 9 AT90CAN64 2K bytes 8 bytes EEA[2:0] 256 EEA[10:3] 10 AT90CAN128 4K bytes 8 bytes EEA[2:0] 512 EEA[11:3] 11 341 7679H–CAN–08/08

25.6 Parallel Programming 25.6.1 Enter Programming Mode The following algorithm puts the device in parallel programming mode: 1. Apply power between V and GND. CC 2. Set RESET to “0” and toggle XTAL1 at least six times. 3. Set the Prog_enable pins listed in Table 25-8 on page 340 to “0000” and wait at least 100 ns. 4. Apply 11.5 - 12.5V to RESET. Any activity on Prog_enable pins within 100 ns after +12V has been applied to RESET, will cause the device to fail entering programming mode. 5. Wait at least 50 µs before sending a new command. 25.6.2 Considerations for EfficientProgramming The loaded command and address are retained in the device during programming. For efficient programming, the following should be considered. • The command needs only be loaded once when writing or reading multiple memory locations. • Skip writing the data value 0xFF, that is the contents of the entire EEPROM (unless the EESAVE Fuse is programmed) and Flash after a Chip Erase. • Address high byte needs only be loaded before programming or reading a new 256 word window in Flash or 256 byte EEPROM. This consideration also applies to Signature bytes reading. 25.6.3 Chip Erase The Chip Erase will erase the Flash and EEPROM(1) memories plus Lock bits. The Lock bits are not reset until the program memory has been completely erased. The Fuse bits are not changed. A Chip Erase must be performed before the Flash and/or EEPROM are reprogrammed. Load Command “Chip Erase” 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set BS1 to “0”. 3. Set DATA to “1000 0000”. This is the command for Chip Erase. 4. Give XTAL1 a positive pulse. This loads the command. 5. Give WR a negative pulse. This starts the Chip Erase. RDY/BSY goes low. 6. Wait until RDY/BSY goes high before loading a new command. Note: 1. The EEPROM memory is preserved during Chip Erase if the EESAVE Fuse is programmed. 25.6.4 Programming the Flash The Flash is organized in pages, see Table 25-11 on page 341. When programming the Flash, the program data is latched into a page buffer. This allows one page of program data to be pro- grammed simultaneously. The following procedure describes how to program the entire Flash memory: A: Load Command “Write Flash” AT90CAN32/64/128 342 7679H–CAN–08/08

AT90CAN32/64/128 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set BS1 to “0”. 3. Set DATA to “0001 0000”. This is the command for Write Flash. 4. Give XTAL1 a positive pulse. This loads the command. B: Load Address Low byte 1. Set XA1, XA0 to “00”. This enables address loading. 2. Set BS1 to “0”. This selects low address. 3. Set DATA = Address low byte (0x00 - 0xFF). 4. Give XTAL1 a positive pulse. This loads the address low byte. C: Load Data Low Byte 1. Set XA1, XA0 to “01”. This enables data loading. 2. Set DATA = Data low byte (0x00 - 0xFF). 3. Give XTAL1 a positive pulse. This loads the data byte. D: Load Data High Byte 1. Set BS1 to “1”. This selects high data byte. 2. Set XA1, XA0 to “01”. This enables data loading. 3. Set DATA = Data high byte (0x00 - 0xFF). 4. Give XTAL1 a positive pulse. This loads the data byte. E: Latch Data 1. Set BS1 to “1”. This selects high data byte. 2. Give PAGEL a positive pulse. This latches the data bytes. (See Figure 25-3 for signal waveforms) F: Repeat B through E until the entire buffer is filled or until all data within the page is loaded. While the lower bits in the address are mapped to words within the page, the higher bits address the pages within the FLASH. This is illustrated in Figure 25-2 on page 344. Note that if less than eight bits are required to address words in the page (pagesize < 256), the most significant bit(s) in the address low byte are used to address the page when performing a Page Write. G: Load Address High byte 1. Set XA1, XA0 to “00”. This enables address loading. 2. Set BS1 to “1”. This selects high address. 3. Set DATA = Address high byte (0x00 - 0xFF). 4. Give XTAL1 a positive pulse. This loads the address high byte. H: Program Page 1. Give WR a negative pulse. This starts programming of the entire page of data. RDY/BSY goes low. 2. Wait until RDY/BSY goes high (See Figure 25-3 for signal waveforms). I: Repeat B through H until the entire Flash is programmed or until all data has been programmed. J: End Page Programming 343 7679H–CAN–08/08

1. 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set DATA to “0000 0000”. This is the command for No Operation. 3. Give XTAL1 a positive pulse. This loads the command, and the internal write signals are reset. Figure 25-2. Addressing the Flash Which is Organized in Pages(1) PCMSB PAGEMSB PROGRAM COUNTER PCPAGE PCWORD PAGE ADDRESS WORD ADDRESS WITHIN THE FLASH WITHIN A PAGE PROGRAM MEMORY PAGE PCWORD[PAGEMSB:0]: PAGE INSTRUCTION WORD 00 01 02 PAGEEND Note: 1. PCPAGE and PCWORD are listed in Table 25-11 on page 341. Figure 25-3. Programming the Flash Waveforms(1) F A B C D E B C D E G H DATA 0x10 ADDR. LOW DATA LOW DATA HIGH XX ADDR. LOW DATA LOW DATA HIGH XX ADDR. HIGH XX XA1 XA0 BS1 XTAL1 WR RDY/BSY RESET +12V OE PAGEL BS2 Note: 1. “XX” is don’t care. The letters refer to the programming description above. AT90CAN32/64/128 344 7679H–CAN–08/08

AT90CAN32/64/128 25.6.5 Programming the EEPROM The EEPROM is organized in pages, see Table 25-12 on page 341. When programming the EEPROM, the program data is latched into a page buffer. This allows one page of data to be programmed simultaneously. The programming algorithm for the EEPROM data memory is as follows (refer to “Programming the Flash” on page 342 for details on Command, Address and Data loading): 1. A: Load Command “0001 0001”. 2. G: Load Address High Byte (0x00 - 0xFF). 3. B: Load Address Low Byte (0x00 - 0xFF). 4. C: Load Data (0x00 - 0xFF). 5. E: Latch data (give PAGEL a positive pulse). K: Repeat 3 through 5 until the entire buffer is filled. L: Program EEPROM page 1. Set BS1 to “0”. 2. Give WR a negative pulse. This starts programming of the EEPROM page. RDY/BSY goes low. 3. Wait until to RDY/BSY goes high before programming the next page (See Figure 25-4 for signal waveforms). Figure 25-4. Programming the EEPROM Waveforms K A G B C E B C E L DATA 0x11 ADDR. HIGH ADDR. LOW DATA XX ADDR. LOW DATA XX XA1 XA0 BS1 XTAL1 WR RDY/BSY RESET +12V OE PAGEL BS2 25.6.6 Reading the Flash The algorithm for reading the Flash memory is as follows (refer to “Programming the Flash” on page 342 for details on Command and Address loading): 1. A: Load Command “0000 0010”. 2. G: Load Address High Byte (0x00 - 0xFF). 3. B: Load Address Low Byte (0x00 - 0xFF). 4. Set OE to “0”, and BS1 to “0”. The Flash word low byte can now be read at DATA. 5. Set BS1 to “1”. The Flash word high byte can now be read at DATA. 6. Set OE to “1”. 345 7679H–CAN–08/08

25.6.7 Reading the EEPROM The algorithm for reading the EEPROM memory is as follows (refer to “Programming the Flash” on page 342 for details on Command and Address loading): 1. A: Load Command “0000 0011”. 2. G: Load Address High Byte (0x00 - 0xFF). 3. B: Load Address Low Byte (0x00 - 0xFF). 4. Set OE to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at DATA. 5. Set OE to “1”. 25.6.8 Programming the FuseLowBits The algorithm for programming the Fuse Low bits is as follows (refer to “Programming the Flash” on page 342 for details on Command and Data loading): 1. A: Load Command “0100 0000”. 2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit. 3. Give WR a negative pulse and wait for RDY/BSY to go high. 25.6.9 Programming the FuseHighBits The algorithm for programming the Fuse High bits is as follows (refer to “Programming the Flash” on page 342 for details on Command and Data loading): 1. A: Load Command “0100 0000”. 2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit. 3. Set BS1 to “1” and BS2 to “0”. This selects high data byte. 4. Give WR a negative pulse and wait for RDY/BSY to go high. 5. Set BS1 to “0”. This selects low data byte. 25.6.10 Programming the ExtendedFuse Bits The algorithm for programming the Extended Fuse bits is as follows (refer to “Programming the Flash” on page 342 for details on Command and Data loading): 1. A: Load Command “0100 0000”. 2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit. 3. Set BS1 to “0” and BS2 to “1”. This selects extended data byte. 4. Give WR a negative pulse and wait for RDY/BSY to go high. 5. Set BS2 to “0”. This selects low data byte. AT90CAN32/64/128 346 7679H–CAN–08/08

AT90CAN32/64/128 Figure 25-5. Programming the FUSES Waveforms Write Fuse Low byte Write Fuse high byte Write Extended Fuse byte A C A C A C DATA 0x40 DATA XX 0x40 DATA XX 0x40 DATA XX XA1 XA0 BS1 BS2 XTAL1 WR RDY/BSY RESET +12V OE PAGEL 25.6.11 Programming the Lock Bits The algorithm for programming the Lock bits is as follows (refer to “Programming the Flash” on page 342 for details on Command and Data loading): 1. A: Load Command “0010 0000”. 2. C: Load Data Low Byte. Bit n = “0” programs the Lock bit. If LB mode 3 is programmed (LB1 and LB2 is programmed), it is not possible to program the Boot Lock bits by any External Programming mode. 3. Give WR a negative pulse and wait for RDY/BSY to go high. The Lock bits can only be cleared by executing Chip Erase. 25.6.12 Reading the Fuse and LockBits The algorithm for reading the Fuse and Lock bits is as follows (refer to “Programming the Flash” on page 342 for details on Command loading): 1. A: Load Command “0000 0100”. 2. Set OE to “0”, BS2 to “0” and BS1 to “0”. The status of the Fuse Low bits can now be read at DATA (“0” means programmed). 3. Set OE to “0”, BS2 to “1” and BS1 to “1”. The status of the Fuse High bits can now be read at DATA (“0” means programmed). 4. Set OE to “0”, BS2 to “1”, and BS1 to “0”. The status of the Extended Fuse bits can now be read at DATA (“0” means programmed). 5. Set OE to “0”, BS2 to “0” and BS1 to “1”. The status of the Lock bits can now be read at DATA (“0” means programmed). 6. Set OE to “1”. 347 7679H–CAN–08/08

Figure 25-6. Mapping Between BS1, BS2 and the Fuse and Lock Bits During Read Fuse Low Byte 0 Extended Fuse Byte 1 0 BS2 DATA Lock Bits 0 1 Fuse High Byte 1 BS1 BS2 25.6.13 Reading the Signature Bytes The algorithm for reading the Signature bytes is as follows (refer to “Programming the Flash” on page 342 for details on Command and Address loading): 1. A: Load Command “0000 1000”. 2. B: Load Address Low Byte (0x00 - 0x02). 3. Set OE to “0”, and BS1 to “0”. The selected Signature byte can now be read at DATA. 4. Set OE to “1”. 25.6.14 Reading the Calibration Byte The algorithm for reading the Calibration byte is as follows (refer to “Programming the Flash” on page 342 for details on Command and Address loading): 1. A: Load Command “0000 1000”. 2. B: Load Address Low Byte, 0x00. 3. Set OE to “0”, and BS1 to “1”. The Calibration byte can now be read at DATA. 4. Set OE to “1”. 25.7 SPI Serial Programming Overview This section describes how to serial program and verify Flash Program memory, EEPROM Data memory, Memory Lock bits, and Fuse bits in the AT90CAN32/64/128. 25.7.1 Signal Names Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (out- put). After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase operations can be executed. NOTE, in Table 25-13 on page 349, the pin mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal SPI interface. Note that throughout the description about Serial downloading, MOSI and MISO are used to describe the serial data in and serial data out respectively. For AT90CAN32/64/128 these pins are mapped to PDI (PE0) and PDO (PE1). AT90CAN32/64/128 348 7679H–CAN–08/08

AT90CAN32/64/128 Figure 25-7. Serial Programming and Verify(1) +2.7 - +5.5V VCC +2.7 - +5.5V PDI PE0 PDO PE1 AVCC SCK PB1 XTAL1 RESET GND Notes: 1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the XTAL1 pin. When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase instruction. The Chip Erase operation turns the content of every memory location in both the Program and EEPROM arrays into 0xFF. Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods for the serial clock (SCK) input are defined as follows: Low: > 2 CPU clock cycles for f < 12 MHz, 3 CPU clock cycles for f ≥ 12 MHz ck ck High: > 2 CPU clock cycles for f < 12 MHz, 3 CPU clock cycles for f ≥ 12 MHz ck ck 25.7.2 Pin Mapping Table 25-13. Pin Mapping Serial Programming Symbol Pins I/O Description MOSI (PDI) PE0 I Serial Data in MISO (PDO) PE1 O Serial Data out SCK PB1 I Serial Clock 25.7.3 Parameters The Flash parameters are given in Table 25-11 on page 341 and the EEPROM parameters in Table 25-12 on page 341. 25.8 SPI Serial Programming When writing serial data to the AT90CAN32/64/128, data is clocked on the rising edge of SCK. When reading data from the AT90CAN32/64/128, data is clocked on the falling edge of SCK. To program and verify the AT90CAN32/64/128 in the serial programming mode, the following sequence is recommended (See four byte instruction formats in Table 25-15): 349 7679H–CAN–08/08

1. Power-up sequence: Apply power between V and GND while RESET and SCK are set to “0”. In some sys- CC tems, the programmer can not guarantee that SCK is held low during power-up. In this case, RESET must be given a positive pulse of at least two CPU clock cycles duration after SCK has been set to “0”. 2. Wait for at least 20 ms and enable serial programming by sending the Programming Enable serial instruction to pin MOSI. 3. The serial programming instructions will not work if the communication is out of syn- chronization. When in sync. the second byte (0x53), will echo back when issuing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a positive pulse and issue a new Programming Enable command. 4. The Flash is programmed one page at a time. The page size is found in Table 25-11 on page 341. The memory page is loaded one byte at a time by supplying the 7 LSB of the address and data together with the Load Program Memory Page instruction. To ensure correct loading of the page, the data low byte must be loaded before data high byte is applied for given address. The Program Memory Page is stored by loading the Write Program Memory Page instruction with the 9 MSB of the address. If polling is not used, the user must wait at least tWD_FLASH before issuing the next page. (See Table 25-14). Note: If other commands than polling (read) are applied before any write operation (Flash, EEPROM, Lock bits, Fuses) is completed, may result in incorrect programming. A delay of 1µs is sufficient. 5. The EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written. If polling is not used, the user must wait at least t before issuing the next byte. (See Table 25-14.) In a chip WD_EEPROM erased device, no 0xFFs in the data file(s) need to be programmed. 6. Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output MISO. 7. At the end of the programming session, RESET can be set high to commence normal operation. 8. Power-off sequence (if needed): Set RESET to “1”. Turn Vcc power off. 25.8.1 Data Polling Flash When a page is being programmed into the Flash, reading an address location within the page being programmed will give the value 0xFF. At the time the device is ready for a new page, the programmed value will read correctly. This is used to determine when the next page can be writ- ten. Note that the entire page is written simultaneously and any address within the page can be used for polling. Data polling of the Flash will not work for the value 0xFF, so when programming this value, the user will have to wait for at least t before programming the next page. As WD_FLASH a chip-erased device contains 0xFF in all locations, programming of addresses that are meant to contain 0xFF, can be skipped. See Table 25-14 for t value. WD_FLASH 25.8.2 Data Polling EEPROM When a new byte has been written and is being programmed into EEPROM, reading the address location being programmed will give the value 0xFF. At the time the device is ready for a new byte, the programmed value will read correctly. This is used to determine when the next byte can be written. This will not work for the value 0xFF, but the user should have the following in mind: As a chip-erased device contains 0xFF in all locations, programming of addresses that AT90CAN32/64/128 350 7679H–CAN–08/08

AT90CAN32/64/128 are meant to contain 0xFF, can be skipped. This does not apply if the EEPROM is re-pro- grammed without chip erasing the device. In this case, data polling cannot be used for the value 0xFF, and the user will have to wait at least t before programming the next byte. See WD_EEPROM Table 25-14 for t value. WD_EEPROM Table 25-14. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location Symbol Minimum Wait Delay t 4.5 ms WD_FUSE t 4.5 ms WD_FLASH t 9.0 ms WD_EEPROM t 9.0 ms WD_ERASE Figure 25-8. Serial Programming Waveforms SERIAL DATA INPUT MSB LSB (MOSI-PDI) SERIAL DATA OUTPUT MSB LSB (MISO-PDO) SERIAL CLOCK INPUT (SCK) Sample Table 25-15. Serial Programming Instruction Set Seta = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction Format(1) Instruction Operation(1) Byte 1 Byte 2(2) Byte 3 Byte4 Programming 1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable Serial Programming after RESET goes low. Enable Chip Erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip Erase EEPROM and Flash. Read Read H (high or low) data o from Program memory at 0010 H000 aaaa aaaa bbbb bbbb oooo oooo Program Memory word address a:b. Write H (high or low) data i to Program Memory page Load at word address b. Data low byte must be loaded Program Memory 0100 H000 000x xxxx xbbb bbbb iiii iiii before Data high byte is applied within the same Page address. Write Program Memory 0100 1100 aaaa aaaa bxxx xxxx xxxx xxxx Write Program Memory Page at address a:b. Page Read 1010 0000 000x aaaa bbbb bbbb oooo oooo Read data o from EEPROM memory at address a:b. EEPROM Memory Write 1100 0000 000x aaaa bbbb bbbb iiii iiii Write data i to EEPROM memory at address a:b. EEPROM Memory 351 7679H–CAN–08/08

Table 25-15. Serial Programming Instruction Set (Continued) Seta = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction Format(1) Instruction Operation(1) Byte 1 Byte 2(2) Byte 3 Byte4 Load Load data i to EEPROM memory page buffer. After EEPROM Memory 1100 0001 0000 0000 0000 0bbb iiii iiii data is loaded, program EEPROM page. Page (page access) Write EEPROM Memory 1100 0010 000x aaaa bbbb b000 xxxx xxxx Write EEPROM page at address a:b. Page (page access) Read Lock bits. “0”=programmed, “1”=unprogrammed. Read Lockbits 0101 1000 0000 0000 xxxx xxxx xxoo oooo See Table 25-1 on page 336 for details. Write Write Lock bits. Set bits = “0” to program Lock bits. 1010 1100 111x xxxx xxxx xxxx 11ii iiii Lock bits See Table 25-1 on page 336 for details. Read 0011 0000 000x xxxx xxxx xxbb oooo oooo Read Signature Byte o at address b. Signature Byte Write Set bits = “0” to program, “1” to unprogram. 1010 1100 1010 0000 xxxx xxxx iiii iiii Fuse Low bits See Table 25-5 on page 338 for details. Write Set bits = “0” to program, “1” to unprogram. 1010 1100 1010 1000 xxxx xxxx iiii iiii Fuse High bits See Table 25-4 on page 337 for details. Write Set bits = “0” to program, “1” to unprogram. 1010 1100 1010 0100 xxxx xxxx xxxx iiii Extended Fuse Bits See Table 25-3 on page 337 for details. Read Read Fuse bits. “0”=programmed, “1”=unprogrammed. 0101 0000 0000 0000 xxxx xxxx oooo oooo Fuse Low bits See Table 25-5 on page 338 for details. Read Fuse High bits. Read 0101 1000 0000 1000 xxxx xxxx oooo oooo “0”=programmed, “1”=unprogrammed. Fuse High bits See Table 25-4 on page 337 for details. Read Extended Fuse bits. Read 0101 0000 0000 1000 xxxx xxxx oooo oooo “0”=programmed, “1”=unprogrammed. Extended Fuse Bits See Table 25-3 on page 337 for details. Read 0011 1000 000x xxxx 0000 0000 oooo oooo Read Calibration Byte Calibration Byte If o = “1”, a programming operation is still busy. Wait Poll RDY/BSY 1111 0000 0000 0000 xxxx xxxx xxxx xxxo until this bit returns to “0” before applying another command. Notes: 1. All bytes are represented by binary digits (0b...). 2. Address bits exceeding PCMSB and EEAMSB (see Table 25-11 on page 341 and Table 25-12 on page 341) are don’t care. 25.9 JTAG Programming Overview Programming through the JTAG interface requires control of the four JTAG specific pins: TCK, TMS, TDI, and TDO. Control of the reset and clock pins is not required. To be able to use the JTAG interface, the JTAGEN Fuse must be programmed. The device is default shipped with the fuse programmed. In addition, the JTD bit in MCUCR must be cleared. Alternatively, if the JTD bit is set, the external reset can be forced low. Then, the JTD bit will be cleared after two chip clocks, and the JTAG pins are available for programming. This provides a means of using the JTAG pins as normal port pins in Running mode while still allowing In-Sys- tem Programming via the JTAG interface. Note that this technique can not be used when using AT90CAN32/64/128 352 7679H–CAN–08/08

AT90CAN32/64/128 the JTAG pins for Boundary-scan or On-chip Debug. In these cases the JTAG pins must be ded- icated for this purpose. During programming the clock frequency of the TCK Input must be less than the maximum fre- quency of the chip. The System Clock Prescaler can not be used to divide the TCK Clock Input into a sufficiently low frequency. As a definition in this datasheet, the LSB is shifted in and out first of all Shift Registers. 25.9.1 Programming Specific JTAG Instructions The instruction register is 4-bit wide, supporting up to 16 instructions. The JTAG instructions useful for programming are listed below. The OPCODE for each instruction is shown behind the instruction name in hex format. The text describes which data register is selected as path between TDI and TDO for each instruction. The Run-Test/Idle state of the TAP controller is used to generate internal clocks. It can also be used as an idle state between JTAG sequences. The state machine sequence for changing the instruction word is shown in Figure 25-9. Figure 25-9. State Machine Sequence for Changing the Instruction Word 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 1 0 0 1 1 Capture-DR Capture-IR 0 0 Shift-DR 0 Shift-IR 0 1 1 1 1 Exit1-DR Exit1-IR 0 0 Pause-DR 0 Pause-IR 0 1 1 0 0 Exit2-DR Exit2-IR 1 1 Update-DR Update-IR 1 0 1 0 353 7679H–CAN–08/08

25.9.1.1 AVR_RESET (0xC) The AVR specific public JTAG instruction for setting the AVR device in the Reset mode or taking the device out from the Reset mode. The TAP controller is not reset by this instruction. The one bit Reset Register is selected as data register. Note that the reset will be active as long as there is a logic “one” in the Reset Chain. The output from this chain is not latched. The active states are: • Shift-DR: The Reset Register is shifted by the TCK input. 25.9.1.2 PROG_ENABLE (0x4) The AVR specific public JTAG instruction for enabling programming via the JTAG port. The 16- bit Programming Enable Register is selected as data register. The active states are the following: • Shift-DR: The programming enable signature is shifted into the data register. • Update-DR: The programming enable signature is compared to the correct value, and Programming mode is entered if the signature is valid. 25.9.1.3 PROG_COMMANDS (0x5) The AVR specific public JTAG instruction for entering programming commands via the JTAG port. The 15-bit Programming Command Register is selected as data register. The active states are the following: • Capture-DR: The result of the previous command is loaded into the data register. • Shift-DR: The data register is shifted by the TCK input, shifting out the result of the previous command and shifting in the new command. • Update-DR: The programming command is applied to the Flash inputs • Run-Test/Idle: One clock cycle is generated, executing the applied command (not always required, see Table 25-16 below). 25.9.1.4 PROG_PAGELOAD (0x6) The AVR specific public JTAG instruction to directly load the Flash data page via the JTAG port. An 8-bit Flash Data Byte Register is selected as the data register. This is physically the 8 LSBs of the Programming Command Register. The active states are the following: • Shift-DR: The Flash Data Byte Register is shifted by the TCK input. • Update-DR: The content of the Flash Data Byte Register is copied into a temporary register. A write sequence is initiated that within 11 TCK cycles loads the content of the temporary register into the Flash page buffer. The AVR automatically alternates between writing the low and the high byte for each new Update-DR state, starting with the low byte for the first Update-DR encountered after entering the PROG_PAGELOAD command. The Program Counter is pre-incremented before writing the low byte, except for the first written byte. This ensures that the first data is written to the address set up by PROG_COMMANDS, and loading the last location in the page buffer does not make the program counter increment into the next page. 25.9.1.5 PROG_PAGEREAD (0x7) The AVR specific public JTAG instruction to directly capture the Flash content via the JTAG port. An 8-bit Flash Data Byte Register is selected as the data register. This is physically the 8 LSBs of the Programming Command Register. The active states are the following: AT90CAN32/64/128 354 7679H–CAN–08/08

AT90CAN32/64/128 • Capture-DR: The content of the selected Flash byte is captured into the Flash Data Byte Register. The AVR automatically alternates between reading the low and the high byte for each new Capture-DR state, starting with the low byte for the first Capture-DR encountered after entering the PROG_PAGEREAD command. The Program Counter is post-incremented after reading each high byte, including the first read byte. This ensures that the first data is captured from the first address set up by PROG_COMMANDS, and reading the last location in the page makes the program counter increment into the next page. • Shift-DR: The Flash Data Byte Register is shifted by the TCK input. 25.9.2 Data Registers The data registers are selected by the JTAG instruction registers described in section “Program- ming Specific JTAG Instructions” on page 353. The data registers relevant for programming operations are: • Reset Register • Programming Enable Register • Programming Command Register • Flash Data Byte Register 25.9.2.1 Reset Register The Reset Register is a Test Data Register used to reset the part during programming. It is required to reset the part before entering Programming mode. A high value in the Reset Register corresponds to pulling the external reset low. The part is reset as long as there is a high value present in the Reset Register. Depending on the Fuse settings for the clock options, the part will remain reset for a Reset Time-out period (refer to “Clock Sources” on page 38) after releasing the Reset Register. The output from this data register is not latched, so the reset will take place immediately, as shown in Figure 23-2 on page 302. 25.9.2.2 Programming Enable Register The Programming Enable Register is a 16-bit register. The contents of this register is compared to the programming enable signature, binary code 0b1010_0011_0111_0000. When the con- tents of the register is equal to the programming enable signature, programming via the JTAG port is enabled. The register is reset to 0 on Power-on Reset, and should always be reset when leaving Programming mode. Figure 25-10. Programming Enable Register TDI D 0xA370 = A D Q Programming Enable T A ClockDR & PROG_ENABLE TDO 355 7679H–CAN–08/08

25.9.2.3 Programming Command Register The Programming Command Register is a 15-bit register. This register is used to serially shift in programming commands, and to serially shift out the result of the previous command, if any. The JTAG Programming Instruction Set is shown in Table 25-16. The state sequence when shifting in the programming commands is illustrated in Figure 25-12. Figure 25-11. Programming Command Register TDI S T R O B E S Flash EEPROM A Fuses D Lock Bits D R E S S / D A T A TDO Table 25-16. JTAG Programming Instruction Seta = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI Sequence(1)(2) TDO Sequence(1)(2) Notes 0100011_10000000 xxxxxxx_xxxxxxxx 0110001_10000000 xxxxxxx_xxxxxxxx 1a. Chip Erase 0110011_10000000 xxxxxxx_xxxxxxxx 0110011_10000000 xxxxxxx_xxxxxxxx 1b. Poll for Chip Erase Complete 0110011_10000000 xxxxxox_xxxxxxxx (4) 2a. Enter Flash Write 0100011_00010000 xxxxxxx_xxxxxxxx 2b. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx (11) 2c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 2d. Load Data Low Byte 0010011_iiiiiiii xxxxxxx_xxxxxxxx 2e. Load Data High Byte 0010111_iiiiiiii xxxxxxx_xxxxxxxx 0110111_00000000 xxxxxxx_xxxxxxxx 2f. Latch Data 1110111_00000000 xxxxxxx_xxxxxxxx (3) 0110111_00000000 xxxxxxx_xxxxxxxx AT90CAN32/64/128 356 7679H–CAN–08/08

AT90CAN32/64/128 Table 25-16. JTAG Programming Instruction (Continued) Seta = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI Sequence(1)(2) TDO Sequence(1)(2) Notes 0110111_00000000 xxxxxxx_xxxxxxxx 0110101_00000000 xxxxxxx_xxxxxxxx 2g. Write Flash Page (3) 0110111_00000000 xxxxxxx_xxxxxxxx 0110111_00000000 xxxxxxx_xxxxxxxx 2h. Poll for Page Write Complete 0110111_00000000 xxxxxox_xxxxxxxx (4) 3a. Enter Flash Read 0100011_00000010 xxxxxxx_xxxxxxxx 3b. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx (11) 3c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 0110010_00000000 xxxxxxx_xxxxxxxx 3d. Read Data Low and High Byte 0110110_00000000 xxxxxxx_oooooooo Low byte 0110111_00000000 xxxxxxx_oooooooo High byte 4a. Enter EEPROM Write 0100011_00010001 xxxxxxx_xxxxxxxx 4b. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx (11) 4c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 4d. Load Data Byte 0010011_iiiiiiii xxxxxxx_xxxxxxxx 0110111_00000000 xxxxxxx_xxxxxxxx 4e. Latch Data 1110111_00000000 xxxxxxx_xxxxxxxx (3) 0110111_00000000 xxxxxxx_xxxxxxxx 0110011_00000000 xxxxxxx_xxxxxxxx 0110001_00000000 xxxxxxx_xxxxxxxx 4f. Write EEPROM Page (3) 0110011_00000000 xxxxxxx_xxxxxxxx 0110011_00000000 xxxxxxx_xxxxxxxx 4g. Poll for Page Write Complete 0110011_00000000 xxxxxox_xxxxxxxx (4) 5a. Enter EEPROM Read 0100011_00000011 xxxxxxx_xxxxxxxx 5b. Load Address High Byte 0000111_aaaaaaaa xxxxxxx_xxxxxxxx (11) 5c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 0110011_bbbbbbbb xxxxxxx_xxxxxxxx 5d. Read Data Byte 0110010_00000000 xxxxxxx_xxxxxxxx 0110011_00000000 xxxxxxx_oooooooo 6a. Enter Fuse Write 0100011_01000000 xxxxxxx_xxxxxxxx 6b. Load Data Low Byte(8) 0010011_iiiiiiii xxxxxxx_xxxxxxxx (5) 0111011_00000000 xxxxxxx_xxxxxxxx 0111001_00000000 xxxxxxx_xxxxxxxx 6c. Write Fuse Extended Byte (3) 0111011_00000000 xxxxxxx_xxxxxxxx 0111011_00000000 xxxxxxx_xxxxxxxx 6d. Poll for Fuse Write Complete 0110111_00000000 xxxxxox_xxxxxxxx (4) 6e. Load Data Low Byte(9) 0010011_iiiiiiii xxxxxxx_xxxxxxxx (5) 357 7679H–CAN–08/08

Table 25-16. JTAG Programming Instruction (Continued) Seta = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI Sequence(1)(2) TDO Sequence(1)(2) Notes 0110111_00000000 xxxxxxx_xxxxxxxx 0110101_00000000 xxxxxxx_xxxxxxxx 6f. Write Fuse High Byte (3) 0110111_00000000 xxxxxxx_xxxxxxxx 0110111_00000000 xxxxxxx_xxxxxxxx 6g. Poll for Fuse Write Complete 0110111_00000000 xxxxxox_xxxxxxxx (4) 6h. Load Data Low Byte(9) 0010011_iiiiiiii xxxxxxx_xxxxxxxx (5) 0110011_00000000 xxxxxxx_xxxxxxxx 0110001_00000000 xxxxxxx_xxxxxxxx 6i. Write Fuse Low Byte (3) 0110011_00000000 xxxxxxx_xxxxxxxx 0110011_00000000 xxxxxxx_xxxxxxxx 6j. Poll for Fuse Write Complete 0110011_00000000 xxxxxox_xxxxxxxx (4) 7a. Enter Lock Bit Write 0100011_00100000 xxxxxxx_xxxxxxxx 7b. Load Data Byte(11) 0010011_11iiiiii xxxxxxx_xxxxxxxx (6) 0110011_00000000 xxxxxxx_xxxxxxxx 0110001_00000000 xxxxxxx_xxxxxxxx 7c. Write Lock Bits (3) 0110011_00000000 xxxxxxx_xxxxxxxx 0110011_00000000 xxxxxxx_xxxxxxxx 7d. Poll for Lock Bit Write complete 0110011_00000000 xxxxxox_xxxxxxxx (4) 8a. Enter Fuse/Lock Bit Read 0100011_00000100 xxxxxxx_xxxxxxxx 0111010_00000000 xxxxxxx_xxxxxxxx 8b. Read Extended Fuse Byte(8) 0111011_00000000 xxxxxxx_oooooooo 0111110_00000000 xxxxxxx_xxxxxxxx 8c. Read Fuse High Byte(9) 0111111_00000000 xxxxxxx_oooooooo 0110010_00000000 xxxxxxx_xxxxxxxx 8d. Read Fuse Low Byte(10) 0110011_00000000 xxxxxxx_oooooooo 0110110_00000000 xxxxxxx_xxxxxxxx 8e. Read Lock Bits(11) (7) 0110111_00000000 xxxxxxx_xxoooooo 0111010_00000000 xxxxxxx_xxxxxxxx (7) 0111110_00000000 xxxxxxx_oooooooo Fuse Ext. byte 8f. Read Fuses and Lock Bits 0110010_00000000 xxxxxxx_oooooooo Fuse High byte 0110110_00000000 xxxxxxx_oooooooo Fuse Low byte 0110111_00000000 xxxxxxx_oooooooo Lock bits 9a. Enter Signature Byte Read 0100011_00001000 xxxxxxx_xxxxxxxx 9b. Load Address Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 0110010_00000000 xxxxxxx_xxxxxxxx 9c. Read Signature Byte 0110011_00000000 xxxxxxx_oooooooo 10a. Enter Calibration Byte Read 0100011_00001000 xxxxxxx_xxxxxxxx AT90CAN32/64/128 358 7679H–CAN–08/08

AT90CAN32/64/128 Table 25-16. JTAG Programming Instruction (Continued) Seta = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care Instruction TDI Sequence(1)(2) TDO Sequence(1)(2) Notes 10b. Load Address Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 0110110_00000000 xxxxxxx_xxxxxxxx 10c. Read Calibration Byte 0110111_00000000 xxxxxxx_oooooooo 0100011_00000000 xxxxxxx_xxxxxxxx 11a. Load No Operation Command 0110011_00000000 xxxxxxx_xxxxxxxx Notes: 1. Address bits exceeding PCMSB and EEAMSB (Table 25-11 and Table 25-12) are don’t care. 2. All TDI and TDO sequences are represented by binary digits (0b...). 3. This command sequence is not required if the seven MSB are correctly set by the previous command sequence (which is normally the case). 4. Repeat until o = “1”. 5. Set bits to “0” to program the corresponding Fuse, “1” to unprogram the Fuse. 6. Set bits to “0” to program the corresponding Lock bit, “1” to leave the Lock bit unchanged. 7. “0” = programmed, “1” = unprogrammed. 8. The bit mapping for Fuses Extended byte is listed in Table 25-3 on page 337. 9. The bit mapping for Fuses High byte is listed in Table 25-4 on page 337. 10.The bit mapping for Fuses Low byte is listed in Table 25-5 on page 338. 11.The bit mapping for Lock bits byte is listed in Table 25-1 on page 336. 359 7679H–CAN–08/08

Figure 25-12. State Machine Sequence for Changing/Reading the Data Word 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 1 0 0 1 1 Capture-DR Capture-IR 0 0 Shift-DR 0 Shift-IR 0 1 1 1 1 Exit1-DR Exit1-IR 0 0 Pause-DR 0 Pause-IR 0 1 1 0 0 Exit2-DR Exit2-IR 1 1 Update-DR Update-IR 1 0 1 0 25.9.2.4 Flash Data Byte Register The Flash Data Byte Register provides an efficient way to load the entire Flash page buffer before executing Page Write, or to read out/verify the content of the Flash. A state machine sets up the control signals to the Flash and senses the strobe signals from the Flash, thus only the data words need to be shifted in/out. The Flash Data Byte Register actually consists of the 8-bit scan chain and a 8-bit temporary reg- ister. During page load, the Update-DR state copies the content of the scan chain over to the temporary register and initiates a write sequence that within 11 TCK cycles loads the content of the temporary register into the Flash page buffer. The AVR automatically alternates between writing the low and the high byte for each new Update-DR state, starting with the low byte for the first Update-DR encountered after entering the PROG_PAGELOAD command. The Program Counter is pre-incremented before writing the low byte, except for the first written byte. This ensures that the first data is written to the address set up by PROG_COMMANDS, and loading the last location in the page buffer does not make the Program Counter increment into the next page. During Page Read, the content of the selected Flash byte is captured into the Flash Data Byte Register during the Capture-DR state. The AVR automatically alternates between reading the low and the high byte for each new Capture-DR state, starting with the low byte for the first Cap- AT90CAN32/64/128 360 7679H–CAN–08/08

AT90CAN32/64/128 ture-DR encountered after entering the PROG_PAGEREAD command. The Program Counter is post-incremented after reading each high byte, including the first read byte. This ensures that the first data is captured from the first address set up by PROG_COMMANDS, and reading the last location in the page makes the program counter increment into the next page. Figure 25-13. Flash Data Byte Register STROBES State Machine ADDRESS TDI Flash EEPROM Fuses Lock Bits D A T A TDO The state machine controlling the Flash Data Byte Register is clocked by TCK. During normal operation in which eight bits are shifted for each Flash byte, the clock cycles needed to navigate through the TAP controller automatically feeds the state machine for the Flash Data Byte Regis- ter with sufficient number of clock pulses to complete its operation transparently for the user. However, if too few bits are shifted between each Update-DR state during page load, the TAP controller should stay in the Run-Test/Idle state for some TCK cycles to ensure that there are at least 11 TCK cycles between each Update-DR state. 25.9.3 Programming Algorithm All references below of type “1a”, “1b”, and so on, refer to Table 25-16 on page 356. 25.9.3.1 Entering Programming Mode 1. Enter JTAG instruction AVR_RESET and shift 1 in the Reset Register. 2. Enter instruction PROG_ENABLE and shift 0b1010_0011_0111_0000 in the Program- ming Enable Register. 25.9.3.2 Leaving Programming Mode 1. Enter JTAG instruction PROG_COMMANDS. 2. Disable all programming instructions by using no operation instruction 11a. 3. Enter instruction PROG_ENABLE and shift 0b0000_0000_0000_0000 in the program- ming Enable Register. 4. Enter JTAG instruction AVR_RESET and shift 0 in the Reset Register. 361 7679H–CAN–08/08

25.9.3.3 Performing Chip Erase 1. Enter JTAG instruction PROG_COMMANDS. 2. Start Chip Erase using programming instruction 1a. 3. Poll for Chip Erase complete using programming instruction 1b, or wait for t WLRH_CE (refer to Table 26-15 on page 382). 25.9.3.4 Programming the Flash 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash write using programming instruction 2a. 3. Load address High byte using programming instruction 2b. 4. Load address Low byte using programming instruction 2c. 5. Load data using programming instructions 2d, 2e and 2f. 6. Repeat steps 4 and 5 for all instruction words in the page. 7. Write the page using programming instruction 2g. 8. Poll for Flash write complete using programming instruction 2h, or wait for t (refer WLRH to ). 9. Repeat steps 3 to 7 until all data have been programmed. A more efficient data transfer can be achieved using the PROG_PAGELOAD instruction: 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash write using programming instruction 2a. 3. Load the page address using programming instructions 2b and 2c. PCWORD (refer to Table 25-11 on page 341) is used to address within one page and must be written as 0. 4. Enter JTAG instruction PROG_PAGELOAD. 5. Load the entire page by shifting in all instruction words in the page byte-by-byte, start- ing with the LSB of the first instruction in the page and ending with the MSB of the last instruction in the page. Use Update-DR to copy the contents of the Flash Data Byte Register into the Flash page location and to auto-increment the Program Counter before each new word. 6. Enter JTAG instruction PROG_COMMANDS. 7. Write the page using programming instruction 2g. 8. Poll for Flash write complete using programming instruction 2h, or wait for t (refer WLRH to Table 26-15 on page 382). 9. Repeat steps 3 to 8 until all data have been programmed. 25.9.3.5 Reading the Flash 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash read using programming instruction 3a. 3. Load address using programming instructions 3b and 3c. 4. Read data using programming instruction 3d. 5. Repeat steps 3 and 4 until all data have been read. A more efficient data transfer can be achieved using the PROG_PAGEREAD instruction: 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash read using programming instruction 3a. 3. Load the page address using programming instructions 3b and 3c. PCWORD (refer to Table 25-11 on page 341) is used to address within one page and must be written as 0. AT90CAN32/64/128 362 7679H–CAN–08/08

AT90CAN32/64/128 4. Enter JTAG instruction PROG_PAGEREAD. 5. Read the entire page (or Flash) by shifting out all instruction words in the page (or Flash), starting with the LSB of the first instruction in the page (Flash) and ending with the MSB of the last instruction in the page (Flash). The Capture-DR state both captures the data from the Flash, and also auto-increments the program counter after each word is read. Note that Capture-DR comes before the shift-DR state. Hence, the first byte which is shifted out contains valid data. 6. Enter JTAG instruction PROG_COMMANDS. 7. Repeat steps 3 to 6 until all data have been read. 25.9.3.6 Programming the EEPROM 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable EEPROM write using programming instruction 4a. 3. Load address High byte using programming instruction 4b. 4. Load address Low byte using programming instruction 4c. 5. Load data using programming instructions 4d and 4e. 6. Repeat steps 4 and 5 for all data bytes in the page. 7. Write the data using programming instruction 4f. 8. Poll for EEPROM write complete using programming instruction 4g, or wait for t WLRH (refer to Table 26-15 on page 382). 9. Repeat steps 3 to 8 until all data have been programmed. Note that the PROG_PAGELOAD instruction can not be used when programming the EEPROM. 25.9.3.7 Reading the EEPROM 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable EEPROM read using programming instruction 5a. 3. Load address using programming instructions 5b and 5c. 4. Read data using programming instruction 5d. 5. Repeat steps 3 and 4 until all data have been read. Note that the PROG_PAGEREAD instruction can not be used when reading the EEPROM. 25.9.3.8 Programming the Fuses 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Fuse write using programming instruction 6a. 3. Load data high byte using programming instructions 6b. A bit value of “0” will program the corresponding fuse, a “1” will unprogram the fuse. 4. Write Fuse High byte using programming instruction 6c. 5. Poll for Fuse write complete using programming instruction 6d, or wait for t (refer to WLRH Table 26-15 on page 382). 6. Load data low byte using programming instructions 6e. A “0” will program the fuse, a “1” will unprogram the fuse. 7. Write Fuse low byte using programming instruction 6f. 8. Poll for Fuse write complete using programming instruction 6g, or wait for t (refer to WLRH Table 26-15 on page 382). 363 7679H–CAN–08/08

25.9.3.9 Programming the Lock Bits 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Lock bit write using programming instruction 7a. 3. Load data using programming instructions 7b. A bit value of “0” will program the corre- sponding lock bit, a “1” will leave the lock bit unchanged. 4. Write Lock bits using programming instruction 7c. 5. Poll for Lock bit write complete using programming instruction 7d, or wait for t WLRH (refer to Table 26-15 on page 382). 25.9.3.10 Reading the Fuses and LockBits 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Fuse/Lock bit read using programming instruction 8a. 3. To read all Fuses and Lock bits, use programming instruction 8f. To only read Extended Fuse byte, use programming instruction 8b. To only read Fuse High byte, use programming instruction 8c. To only read Fuse Low byte, use programming instruction 8d. To only read Lock bits, use programming instruction 8e. 25.9.3.11 Reading the Signature Bytes 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Signature byte read using programming instruction 9a. 3. Load address 0x00 using programming instruction 9b. 4. Read first signature byte using programming instruction 9c. 5. Repeat steps 3 and 4 with address 0x01 and address 0x02 to read the second and third signature bytes, respectively. 25.9.3.12 Reading the Calibration Byte 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Calibration byte read using programming instruction 10a. 3. Load address 0x00 using programming instruction 10b. 4. Read the calibration byte using programming instruction 10c. AT90CAN32/64/128 364 7679H–CAN–08/08

AT90CAN32/64/128 26. Electrical Characteristics (1) 26.1 Absolute Maximum Ratings* Industrial Operating Temperature...................– 40°C to +85°C *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam- Storage Temperature....................................– 65°C to +150°C age to the device. This is a stress rating only and functional operation of the device at these or Voltage on any Pin except RESET other conditions beyond those indicated in the with respect to Ground..............................– 0.5V to V +0.5V operational sections of this specification is not CC implied. Exposure to absolute maximum rating Voltage on RESET with respect to Ground....– 0.5V to +13.0V conditions for extended periods may affect device reliability. Voltage on V with respect to Ground.............– 0.5V to 6.0V CC DC Current per I/O Pin...............................................40.0 mA DC Current V and GND Pins................................200.0 mA CC Note: 1. Electrical Characteristics for this product have not yet been finalized. Please consider all values listed herein as preliminary and non-contractual. 365 7679H–CAN–08/08

26.2 DC Characteristics T = -40°C to +85°C, V = 2.7V to 5.5V (unless otherwise noted) A CC Symbol Parameter Condition Min. Typ. Max. Units Except XTAL1 and V Input Low Voltage – 0.5 0.2 Vcc (1) V IL RESET pins XTAL1 pin - External V Input Low Voltage – 0.5 0.1 Vcc (1) V IL1 Clock Selected V Input Low Voltage RESET pin – 0.5 0.2 Vcc (1) V IL2 Except XTAL1 and V Input High Voltage 0.6 Vcc (2) Vcc + 0.5 V IH RESET pins XTAL1 pin - External V Input High Voltage 0.7 Vcc (2) Vcc + 0.5 V IH1 Clock Selected V Input High Voltage RESET pin 0.85 Vcc (2) Vcc + 0.5 V IH2 Output Low Voltage (3) I = 20 mA, V = 5V 0.7 V OL CC V OL (Ports A, B, C, D, E, F, G) I = 10 mA, V = 3V 0.5 OL CC Output High Voltage (4) I = – 20 mA, V = 5V 4.2 V OH CC V OH (Ports A, B, C, D, E, F, G) I = – 10 mA, V = 3V 2.4 OH CC Input Leakage V = 5.5V, pin low I CC 1.0 µA IL Current I/O Pin (absolute value) Input Leakage V = 5.5V, pin high I CC 1.0 µA IH Current I/O Pin (absolute value) R Reset Pull-up Resistor 30 100 kΩ RST R I/O Pin Pull-up Resistor 20 50 kΩ pu 8 MHz, V = 5V 15 mA CC Power Supply Current 16 MHz, V = 5V 29 mA CC Active Mode (external clock) 4 MHz, VCC = 3V 4 mA 8 MHz, V = 3V 8 mA CC 8 MHz, V = 5V 9 mA CC Power Supply Current 16 MHz, V = 5V 17 mA CC I Idle Mode CC (external clock) 4 MHz, VCC = 3V 3 mA 8 MHz, V = 3V 5 mA CC WDT enabled, V = 5V 40 µA CC Power Supply Current WDT disabled, VCC = 5V 18 µA Power-down Mode WDT enabled, V = 3V 25 µA CC WDT disabled, V = 3V 10 µA CC Analog Comparator V = 5V V CC 1.0 8.0 20 mV ACIO Input Offset Voltage V = V /2 in CC AT90CAN32/64/128 366 7679H–CAN–08/08

AT90CAN32/64/128 T = -40°C to +85°C, V = 2.7V to 5.5V (unless otherwise noted) (Continued) A CC Symbol Parameter Condition Min. Typ. Max. Units Analog Comparator V = 5V I CC – 50 50 nA ACLK Input Leakage Current V = V /2 in CC Analog Comparator V = 2.7V 170 ns CC t Propagation Delay ACID Common Mode Vcc/2 VCC = 5.0V 180 ns Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low 2. “Min” means the lowest value where the pin is guaranteed to be read as high 3. Although each I/O port can sink more than the test conditions (20 mA at V = 5V, 10 mA at V = 3V) under steady state CC CC conditions (non-transient), the following must be observed: TQFP and QFN Package: 1] The sum of all IOL, for all ports, should not exceed 400 mA. 2] The sum of all IOL, for ports A0 - A7, G2, C3 - C7 should not exceed 300 mA. 3] The sum of all IOL, for ports C0 - C2, G0 - G1, D0 - D7, XTAL2 should not exceed 150 mA. 4] The sum of all IOL, for ports B0 - B7, G3 - G4, E0 - E7 should not exceed 150 mA. 5] The sum of all IOL, for ports F0 - F7, should not exceed 200 mA. If I exceeds the test condition, V may exceed the related specification. Pins are not guaranteed to sink current greater OL OL than the listed test condition. 4. Although each I/O port can source more than the test conditions (-20 mA at V = 5V, -10 mA at V = 3V) under steady CC CC state conditions (non-transient), the following must be observed: TQFP and QFN Package: 1] The sum of all I , for all ports, should not exceed -400 mA. OH 2] The sum of all I , for ports A0 - A7, G2, C3 - C7 should not exceed -300 mA. OH 3] The sum of all I , for ports C0 - C2, G0 - G1, D0 - D7, XTAL2 should not exceed 1-50 mA. OH 4] The sum of all I , for ports B0 - B7, G3 - G4, E0 - E7 should not exceed -150 mA. OH 5] The sum of all I , for ports F0 - F7, should not exceed -200 mA. OH If I exceeds the test condition, V may exceed the related specification. Pins are not guaranteed to source current OH OH greater than the listed test condition. 26.3 External Clock Drive Characteristics Figure 26-1. External Clock Drive Waveforms VIH1 VIL1 Table 26-1. External Clock Drive V = 2.7 - 5.5V V = 4.5 - 5.5V CC CC Symbol Parameter Units Min. Max. Min. Max. 1/t Oscillator Frequency 0 8 0 16 MHz CLCL t Clock Period 125 62.5 ns CLCL t High Time 50 25 ns CHCX 367 7679H–CAN–08/08

Table 26-1. External Clock Drive (Continued) V = 2.7 - 5.5V V = 4.5 - 5.5V CC CC Symbol Parameter Units Min. Max. Min. Max. t Low Time 50 25 ns CLCX t Rise Time 1.6 0.5 μs CLCH t Fall Time 1.6 0.5 μs CHCL Change in period from one clock cycle Δt 2 2 % CLCL to the next 26.4 Maximum Speed vs. V CC Maximum frequency is depending on V . As shown in Figure 26-2., the Maximum Frequency CC vs. V curve is linear between 1.8V < V < 4.5V. To calculate the maximum frequency at a CC CC given voltage in this interval, use this equation: Frequency = a•(V–Vx)+Fy To calculate required voltage for a given frequency, use this equation: Voltage = b•(F–Fy)+Vx Table 26-2. Constants used to calculate maximum speed vs. V CC Voltage and Frequency range a b Vx Fy 2.7 < VCC < 4.5 or 8 < Frequency < 16 8/1.8 1.8/8 2.7 8 8 At 3 Volt, this gives: Frequency = --------•(3–2.7)+8 = 9.33 1.8 Thus, when V = 3V, maximum frequency will be 9.33 MHz. CC 1.8 At 8 MHz this gives: Voltage = --------•(8–8)+2.7 = 2.7 8 Thus, a maximum frequency of 8 MHz requires V = 2.7V. CC Figure 26-2. Maximum Frequency vs. V , AT90CAN32/64/128 CC Frequency 16 MHz 8 MHz Safe Operating Area Voltage 2.7V 4.5V 5.5V AT90CAN32/64/128 368 7679H–CAN–08/08

AT90CAN32/64/128 26.5 Two-wire Serial Interface Characteristics Table 26-3 describes the requirements for devices connected to the Two-wire Serial Bus. The AT90CAN32/64/128 Two-wire Serial Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 26-3. Table 26-3. Two-wire Serial Bus Requirements Symbol Parameter Condition Min Max Units Input Low-voltage – 0.5 0.3 Vcc V VIL Input High-voltage 0.7 Vcc Vcc + 0.5 V VIH (1) Hysteresis of Schmitt Trigger Inputs 0.05 Vcc (2) – V Vhys (1) Output Low-voltage 3 mA sink current 0 0.4 V VOL 20 + 0.1C (1) Rise Time for both SDA and SCL b 300 ns tr (3)(2) 20 + 0.1C (1) Output Fall Time from V to V 10 pF < C < 400 pF (3) b 250 ns tof IHmin ILmax b (3)(2) (1) Spikes Suppressed by Input Filter 0 50 (2) ns tSP I Input Current each I/O Pin 0.1 V < V < 0.9 V – 10 10 µA i CC i CC C(1) Capacitance for each I/O Pin – 10 pF i f SCL Clock Frequency f (4) > max(16f , 250kHz) (5) 0 400 kHz SCL CK SCL fSCL ≤ 100 kHz -V---C----C----–-----0---,--4---V--- 1----0---0----0---n---s-- Ω 3mA C b Rp Value of Pull-up resistor fSCL > 100 kHz -V---C----C----–-----0---,--4---V--- 3----0---0----n---s-- Ω 3mA C b f ≤ 100 kHz 4.0 – µs SCL t Hold Time (repeated) START Condition HD;STA f > 100 kHz 0.6 – µs SCL f ≤ 100 kHz (6) 4.7 – µs SCL t Low Period of the SCL Clock LOW f > 100 kHz (7) 1.3 – µs SCL f ≤ 100 kHz 4.0 – µs SCL t High period of the SCL clock HIGH f > 100 kHz 0.6 – µs SCL Set-up time for a repeated START fSCL ≤ 100 kHz 4.7 – µs t SU;STA condition f > 100 kHz 0.6 – µs SCL f ≤ 100 kHz 0 3.45 µs SCL t Data hold time HD;DAT f > 100 kHz 0 0.9 µs SCL f ≤ 100 kHz 250 – ns SCL t Data setup time SU;DAT f > 100 kHz 100 – ns SCL f ≤ 100 kHz 4.0 – µs SCL t Setup time for STOP condition SU;STO f > 100 kHz 0.6 – µs SCL Bus free time between a STOP and t f ≤ 100 kHz 4.7 – µs BUF START condition SCL Notes: 1. In AT90CAN32/64/128, this parameter is characterized and not 100% tested. 369 7679H–CAN–08/08

2. Required only for f > 100 kHz. SCL 3. C = capacitance of one bus line in pF. b 4. f = CPU clock frequency CK 5. This requirement applies to all AT90CAN32/64/128 Two-wire Serial Interface operation. Other devices connected to the Two-wire Serial Bus need only obey the general f requirement. SCL 6. The actual low period generated by the AT90CAN32/64/128 Two-wire Serial Interface is (1/f - 2/f ), thus f must be SCL CK CK greater than 6 MHz for the low time requirement to be strictly met at f = 100 kHz. SCL 7. The actual low period generated by the AT90CAN32/64/128 Two-wire Serial Interface is (1/f - 2/f ), thus the low time SCL CK requirement will not be strictly met for f > 308 kHz when f = 8 MHz. Still, AT90CAN32/64/128 devices connected to the SCL CK bus may communicate at full speed (400 kHz) with other AT90CAN32/64/128 devices, as well as any other device with a proper t acceptance margin. LOW Figure 26-3. Two-wire Serial Bus Timing tof tHIGH tr tLOW tLOW SCL tSU;STA tHD;STA tHD;DAT tSU;DAT tSU;STO SDA tBUF 26.6 SPI Timing Characteristics See Figure 26-4 and Figure 26-5 for details. Table 26-4. SPI Timing Parameters Description Mode Min. Typ. Max. 1 SCK period Master See Table 16-4 2 SCK high/low Master 50% duty cycle 3 Rise/Fall time Master 3.6 4 Setup Master 10 5 Hold Master 10 6 Out to SCK Master 0.5 • t ns sck 7 SCK to out Master 10 8 SCK to out high Master 10 9 SS low to out Slave 15 10 SCK period Slave 4 • t ck 11 SCK high/low (1) Slave 2 • t ck 12 Rise/Fall time Slave 1.6 µs AT90CAN32/64/128 370 7679H–CAN–08/08

AT90CAN32/64/128 Table 26-4. SPI Timing Parameters (Continued) Description Mode Min. Typ. Max. 13 Setup Slave 10 14 Hold Slave t ck 15 SCK to out Slave 15 ns 16 SCK to SS high Slave 20 17 SS high to tri-state Slave 10 18 SS low to SCK Slave 2 • t ck Note: In SPI Programming mode the minimum SCK high/low period is: - 2 t for f < 12 MHz CLCL CK - 3 t for f >12 MHz CLCL CK Figure 26-4. SPI Interface Timing Requirements (Master Mode) SS 6 1 SCK (CPOL = 0) 2 2 SCK (CPOL = 1) 4 5 3 MISO MSB ... LSB (Data Input) 7 8 MOSI MSB ... LSB (Data Output) Figure 26-5. SPI Interface Timing Requirements (Slave Mode) 18 SS 10 16 9 SCK (CPOL = 0) 11 11 SCK (CPOL = 1) 13 14 12 MOSI MSB ... LSB (Data Input) 15 17 MISO MSB ... LSB X (Data Output) 371 7679H–CAN–08/08

26.7 CAN Physical Layer Characteristics Only pads dedicated to the CAN communication belong to the physical layer. Table : CAN Physical Layer Characteristics (1) Parameter Condition Min. Max. Units Vcc=2.7 V Load=20 pF 9 V /V =V /2 OL OH CC 1 TxCAN output delay Vcc=4.5 V Load=20 pF 5.3 V /V =V /2 ns OL OH CC VV/cVc==2V.7 V/2 9 + 1/ fCLKIO(2) IL IH CC 2 RxCAN input delay VV/cVc==4V.5 V/2 7.2 + 1/ fCLKIO(2) IL IH CC Notes: 1. Characteristics for CAN physical layer have not yet been finalized. 2. Metastable immunity flip-flop. AT90CAN32/64/128 372 7679H–CAN–08/08

AT90CAN32/64/128 26.8 ADC Characteristics Table 26-5. ADC Characteristics, Single Ended Channels Symbol Parameter Condition Min(1) Typ(1) Max(1) Units Resolution Single Ended Conversion 10 Bits Single Ended Conversion V = 4V, Vcc = 4V 1.5 LSB REF ADC clock = 200 kHz Single Ended Conversion V = 4V, Vcc = 4V LSB REF Absolute accuracy ADC clock = 1 MHz (Included INL, DNL, Single Ended Conversion Quantization Error, Gain and V = 4V, Vcc = 4V Offset Error) ADRECF clock = 200 kHz 1.5 LSB Noise Reduction Mode Single Ended Conversion V = 4V, Vcc = 4V REF LSB ADC clock = 1 MHz Noise Reduction Mode Single Ended Conversion Integral Non-linearity (INL) V = 4V, Vcc = 4V 0.5 1 LSB REF ADC clock = 200 kHz Single Ended Conversion Differential Non-linearity (DNL) V = 4V, Vcc = 4V 0.3 1 LSB REF ADC clock = 200 kHz Single Ended Conversion Gain Error V = 4V, Vcc = 4V – 2 0 + 2 LSB REF ADC clock = 200 kHz Single Ended Conversion Offset Error V = 4V, Vcc = 4V – 2 1 + 2 LSB REF ADC clock = 200 kHz Clock Frequency Free Running Conversion 50 1000 kHz Conversion Time Free Running Conversion 65 260 µs AV Analog Supply Voltage V – 0.3 (2) V + 0.3 (3) V CC CC CC V External Reference Voltage 2.0 AV V REF CC V Input voltage GND V V IN REF Input bandwidth 38.5 kHz V Internal Voltage Reference 2.4 2.56 2.7 V INT R Reference Input Resistance 32 kΩ REF R Analog Input Resistance 100 MΩ AIN Notes: 1. Values are guidelines only. 2. Minimum for AV is 2.7 V. CC 3. Maximum for AV is 5.5 V CC 373 7679H–CAN–08/08

Table 26-6. ADC Characteristics, Differential Channels Symbol Parameter Condition Min(1) Typ(1) Max(1) Units Differential Conversion 8 Bits Gain = 1x or 10x Resolution Differential Conversion 7 Bits Gain = 200x Gain = 1x, 10x or 200x Absolute accuracy V = 4V, Vcc = 5V 1 LSB REF ADC clock = 50 - 200 kHz Integral Non-linearity (INL) Gain = 1x, 10x or 200x (Accuracy after Calibration V = 4V, Vcc = 5V 0.5 1 LSB REF for Offset and Gain Error) ADC clock = 50 - 200 kHz Gain Error Gain = 1x, 10x or 200x – 2 0 + 2 LSB Gain = 1x, 10x or 200x Offset Error V = 4V, Vcc = 5V – 1 0 + 1 LSB REF ADC clock = 50 - 200 kHz Clock Frequency Free Running Conversion 50 200 kHz Conversion Time Free Running Conversion 65 260 µs AV Analog Supply Voltage V – 0.3 (2) V + 0.3 (3) V CC CC CC V External Reference Voltage Differential Conversion 2.0 AV V REF CC - 0.5 V Input voltage Differential Conversion 0 AV V IN CC V Input Differential Voltage –V /Gain +V /Gain V DIFF REF REF ADC Conversion Output –511 511 LSB Input bandwidth Differential Conversion 4 kHz V Internal Voltage Reference 2.4 2.56 2.7 V INT R Reference Input Resistance 32 kΩ REF R Analog Input Resistance 100 MΩ AIN Notes: 1. Values are guidelines only. 2. Minimum for AV is 2.7 V. CC 3. Maximum for AV is 5.5 V CC AT90CAN32/64/128 374 7679H–CAN–08/08

AT90CAN32/64/128 26.9 External Data Memory Characteristics Table 26-7. External Data Memory Characteristics, V = 4.5 - 5.5 Volts, No Wait-state CC 8 MHz Oscillator Variable Oscillator Symbol Parameter Unit Min. Max. Min. Max. 0 1/t Oscillator Frequency 0.0 16 MHz CLCL 1 t ALE Pulse Width 115 1.0 t – 10 ns LHLL CLCL 2 t Address Valid A to ALE Low 57.5 0.5 t – 5 (1) ns AVLL CLCL Address Hold After ALE Low, 3a t 5 5 ns LLAX_ST write access Address Hold after ALE Low, 3b t 5 5 ns LLAX_LD read access 4 t Address Valid C to ALE Low 57.5 0.5 t – 5 (1) ns AVLLC CLCL 5 t Address Valid to RD Low 115 1.0 t – 10 ns AVRL CLCL 6 t Address Valid to WR Low 115 1.0 t – 10 ns AVWL CLCL 7 t ALE Low to WR Low 47.5 67.5 0.5 t – 15 (2) 0.5 t + 5 (2) ns LLWL CLCL CLCL 8 t ALE Low to RD Low 47.5 67.5 0.5 t – 15 (2) 0.5 t + 5 (2) ns LLRL CLCL CLCL 9 t Data Setup to RD High 40 40 ns DVRH 10 t Read Low to Data Valid 75 1.0 t – 50 ns RLDV CLCL 11 t Data Hold After RD High 0 0 ns RHDX 12 t RD Pulse Width 115 1.0 t – 10 ns RLRH CLCL 13 t Data Setup to WR Low 42.5 0.5 t – 20 (1) ns DVWL CLCL 14 t Data Hold After WR High 115 1.0 t – 10 ns WHDX CLCL 15 t Data Valid to WR High 125 1.0 t ns DVWH CLCL 16 t WR Pulse Width 115 1.0 t – 10 ns WLWH CLCL Notes: 1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1. 2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1. Table 26-8. External Data Memory Characteristics, V = 4.5 - 5.5 Volts, 1 Cycle Wait-state CC 8 MHz Oscillator Variable Oscillator Symbol Parameter Unit Min. Max. Min. Max. 0 1/t Oscillator Frequency 0.0 16 MHz CLCL 10 t Read Low to Data Valid 200 2.0 t – 50 ns RLDV CLCL 12 t RD Pulse Width 240 2.0 t – 10 ns RLRH CLCL 15 t Data Valid to WR High 240 2.0 t ns DVWH CLCL 16 t WR Pulse Width 240 2.0 t – 10 ns WLWH CLCL 375 7679H–CAN–08/08

Table 26-9. External Data Memory Characteristics, V = 4.5 - 5.5 Volts, SRWn1 = 1, SRWn0 = 0 CC 8 MHz Oscillator Variable Oscillator Symbol Parameter Unit Min. Max. Min. Max. 0 1/t Oscillator Frequency 0.0 16 MHz CLCL 10 t Read Low to Data Valid 325 3.0 t – 50 ns RLDV CLCL 12 t RD Pulse Width 365 3.0 t – 10 ns RLRH CLCL 15 t Data Valid to WR High 375 3.0 t ns DVWH CLCL 16 t WR Pulse Width 365 3.0 t – 10 ns WLWH CLCL Table 26-10. External Data Memory Characteristics, V = 4.5 - 5.5 Volts, SRWn1 = 1, SRWn0 = 1 CC 8 MHz Oscillator Variable Oscillator Symbol Parameter Unit Min. Max. Min. Max. 0 1/t Oscillator Frequency 0.0 16 MHz CLCL 10 t Read Low to Data Valid 200 3.0 t – 50 ns RLDV CLCL 12 t RD Pulse Width 365 3.0 t – 10 ns RLRH CLCL 14 t Data Hold After WR High 240 2.0 t – 10 ns WHDX CLCL 15 t Data Valid to WR High 375 3.0 t ns DVWH CLCL 16 t WR Pulse Width 365 3.0 t – 10 ns WLWH CLCL Table 26-11. External Data Memory Characteristics, V = 2.7 - 5.5 Volts, No Wait-state CC 4 MHz Oscillator Variable Oscillator Symbol Parameter Unit Min. Max. Min. Max. 0 1/t Oscillator Frequency 0.0 16 MHz CLCL 1 t ALE Pulse Width 235 t – 15 ns LHLL CLCL 2 t Address Valid A to ALE Low 115 0.5 t – 10 (1) ns AVLL CLCL Address Hold After ALE Low, 3a t 5 5 ns LLAX_ST write access Address Hold after ALE Low, 3b t 5 5 ns LLAX_LD read access 4 t Address Valid C to ALE Low 115 0.5 t – 10 (1) ns AVLLC CLCL 5 t Address Valid to RD Low 235 1.0 t – 15 ns AVRL CLCL 6 t Address Valid to WR Low 235 1.0 t – 15 ns AVWL CLCL 7 t ALE Low to WR Low 115 130 0.5 t – 10 (2) 0.5 t + 5 (2) ns LLWL CLCL CLCL 8 t ALE Low to RD Low 115 130 0.5 t – 10 (2) 0.5 t + 5 (2) ns LLRL CLCL CLCL 9 t Data Setup to RD High 45 45 ns DVRH 10 t Read Low to Data Valid 190 1.0 t – 60 ns RLDV CLCL AT90CAN32/64/128 376 7679H–CAN–08/08

AT90CAN32/64/128 Table 26-11. External Data Memory Characteristics, V = 2.7 - 5.5 Volts, No Wait-state (Continued) CC 4 MHz Oscillator Variable Oscillator Symbol Parameter Unit Min. Max. Min. Max. 11 t Data Hold After RD High 0 0 ns RHDX 12 t RD Pulse Width 235 1.0 t – 15 ns RLRH CLCL 13 t Data Setup to WR Low 105 0.5 t – 20 (1) ns DVWL CLCL 14 t Data Hold After WR High 235 1.0 t – 15 ns WHDX CLCL 15 t Data Valid to WR High 250 1.0 t ns DVWH CLCL 16 t WR Pulse Width 235 1.0 t – 15 ns WLWH CLCL Notes: 1. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1. 2. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1. Table 26-12. External Data Memory Characteristics, V = 2.7 - 5.5 Volts, SRWn1 = 0, SRWn0 = 1 CC 4 MHz Oscillator Variable Oscillator Symbol Parameter Unit Min. Max. Min. Max. 0 1/t Oscillator Frequency 0.0 8 MHz CLCL 10 t Read Low to Data Valid 440 2.0 t – 60 ns RLDV CLCL 12 t RD Pulse Width 485 2.0 t – 15 ns RLRH CLCL 15 t Data Valid to WR High 500 2.0 t ns DVWH CLCL 16 t WR Pulse Width 485 2.0 t – 15 ns WLWH CLCL Table 26-13. External Data Memory Characteristics, V = 2.7 - 5.5 Volts, SRWn1 = 1, SRWn0 = 0 CC 4 MHz Oscillator Variable Oscillator Symbol Parameter Unit Min. Max. Min. Max. 0 1/t Oscillator Frequency 0.0 8 MHz CLCL 10 t Read Low to Data Valid 690 3.0 t – 60 ns RLDV CLCL 12 t RD Pulse Width 735 3.0 t – 15 ns RLRH CLCL 15 t Data Valid to WR High 750 3.0 t ns DVWH CLCL 16 t WR Pulse Width 735 3.0 t – 15 ns WLWH CLCL Table 26-14. External Data Memory Characteristics, V = 2.7 - 5.5 Volts, SRWn1 = 1, SRWn0 = 1 CC 4 MHz Oscillator Variable Oscillator Symbol Parameter Unit Min. Max. Min. Max. 0 1/t Oscillator Frequency 0.0 8 MHz CLCL 10 t Read Low to Data Valid 690 3.0 t – 60 ns RLDV CLCL 12 t RD Pulse Width 735 3.0 t – 15 ns RLRH CLCL 377 7679H–CAN–08/08

Table 26-14. External Data Memory Characteristics, V = 2.7 - 5.5 Volts, SRWn1 = 1, SRWn0 = 1 (Continued) CC 4 MHz Oscillator Variable Oscillator Symbol Parameter Unit Min. Max. Min. Max. 14 t Data Hold After WR High 485 2.0 t – 15 ns WHDX CLCL 15 t Data Valid to WR High 750 3.0 t ns DVWH CLCL 16 t WR Pulse Width 735 3.0 t – 15 ns WLWH CLCL Figure 26-6. External Memory Timing (SRWn1 = 0, SRWn0 = 0) T1 T2 T3 T4 System Clock (CLK ) CPU 1 ALE 4 7 A15:8 Prev. addr. Address 15 2 3a 13 DA7:0 Prev. data Address XX Data e 14 Writ 6 16 WR 3b 9 11 DA7:0 (XMBK = 0) Address Data 5 10 ad e R 8 12 RD AT90CAN32/64/128 378 7679H–CAN–08/08

AT90CAN32/64/128 Figure 26-7. External Memory Timing (SRWn1 = 0, SRWn0 = 1) T1 T2 T3 T4 T5 System Clock (CLK ) CPU 1 ALE 4 7 A15:8 Prev. addr. Address 15 2 3a 13 DA7:0 Prev. data Address XX Data e 14 Writ 6 16 WR 3b 9 11 DA7:0 (XMBK = 0) Address Data 5 10 ad e R 8 12 RD Figure 26-8. External Memory Timing (SRWn1 = 1, SRWn0 = 0) T1 T2 T3 T4 T5 T6 System Clock (CLKCPU) 1 ALE 4 7 A15:8 Prev. addr. Address 15 2 3a 13 DA7:0 Prev. data Address XX Data e 6 16 14 Writ WR 3b 9 11 DA7:0 (XMBK = 0) Address Data 5 10 ad e R 8 12 RD 379 7679H–CAN–08/08

Figure 26-9. External Memory Timing (SRWn1 = 1, SRWn0 = 1)(1) T1 T2 T3 T4 T5 T6 T7 System Clock (CLKCPU) 1 ALE 4 7 A15:8 Prev. addr. Address 15 2 3a 13 DA7:0 Prev. data Address XX Data e 6 16 14 Writ WR 3b 9 11 DA7:0 (XMBK = 0) Address Data 5 10 ad e R 8 12 RD Note: 1. The ALE pulse in the last period (T4-T7) is only present if the next instruction accesses the RAM (internal or external). 26.10 Parallel Programming Characteristics Figure 26-10. Parallel Programming Timing, Including some General Timing Requirements t XLWL t XTAL1 XHXL t t DVXH XLDX Data & Contol (DATA, XA0/1, BS1, BS2) t t t BVPH PLBX BVWL t WLBX PAGEL t PHPL t WLWH WR t PLWL WLRL RDY/BSY t WLRH AT90CAN32/64/128 380 7679H–CAN–08/08

AT90CAN32/64/128 Figure 26-11. Parallel Programming Timing, Loading Sequence with Timing Requirements(1) LOAD ADDRESS LOAD DATA LOAD DATA LOAD DATA LOAD ADDRESS (LOW BYTE) (LOW BYTE) (HIGH BYTE) (LOW BYTE) tXLXH tXLPH tPLXH XTAL1 BS1 PAGEL DATA ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte) XA0 XA1 Note: 1. The timing requirements shown in Figure 26-10 (i.e., t , t , and t ) also apply to DVXH XHXL XLDX loading operation. Figure 26-12. Parallel Programming Timing, Reading Sequence (within the Same Page) with Timing Requirements(1) LOAD ADDRESS READ DATA READ DATA LOAD ADDRESS (LOW BYTE) (LOW BYTE) (HIGH BYTE) (LOW BYTE) tXLOL XTAL1 tBVDV BS1 tOLDV OE tOHDZ DATA ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte) XA0 XA1 381 7679H–CAN–08/08

Note: 1. The timing requirements shown in Figure 26-10 (i.e., t , t , and t ) also apply to DVXH XHXL XLDX reading operation. Table 26-15. Parallel Programming Characteristics, V = 5V ± 10% CC Symbol Parameter Min. Typ. Max. Units V Programming Enable Voltage 11.5 12.5 V PP I Programming Enable Current 250 μA PP t Data and Control Valid before XTAL1 High 67 ns DVXH t XTAL1 Low to XTAL1 High 200 ns XLXH t XTAL1 Pulse Width High 150 ns XHXL t Data and Control Hold after XTAL1 Low 67 ns XLDX t XTAL1 Low to WR Low 0 ns XLWL t XTAL1 Low to PAGEL high 0 ns XLPH t PAGEL low to XTAL1 high 150 ns PLXH t BS1 Valid before PAGEL High 67 ns BVPH t PAGEL Pulse Width High 150 ns PHPL t BS1 Hold after PAGEL Low 67 ns PLBX t BS2/1 Hold after WR Low 67 ns WLBX t PAGEL Low to WR Low 67 ns PLWL t BS1 Valid to WR Low 67 ns BVWL t WR Pulse Width Low 150 ns WLWH t WR Low to RDY/BSY Low 0 1 μs WLRL t WR Low to RDY/BSY High(1) 3.7 5 ms WLRH t WR Low to RDY/BSY High for Chip Erase(2) 7.5 10 ms WLRH_CE t XTAL1 Low to OE Low 0 ns XLOL t BS1 Valid to DATA valid 0 250 ns BVDV t OE Low to DATA Valid 250 ns OLDV t OE High to DATA Tri-stated 250 ns OHDZ Notes: 1. t is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits WLRH commands. 2. t is valid for the Chip Erase command. WLRH_CE AT90CAN32/64/128 382 7679H–CAN–08/08

AT90CAN32/64/128 27. Decoupling Capacitors The operating frequency (i.e. system clock) of the processor determines in 95% of cases the value needed for microcontroller decoupling capacitors. The hypotheses used as first evaluation for decoupling capacitors are: • The operating frequency (fop) supplies itself the maximum peak levels of noise. The main peaks are located at fop and 2 • fop. • An SMC capacitor connected to 2 micro-vias on a PCB has the following characteristics: – 1.5 nH from the connection of the capacitor to the PCB, – 1.5 nH from the capacitor intrinsic inductance. Figure 27-1. Capacitor description 1.5 nH 0.75 nH Capacitor 0.75 nH PCB According to the operating frequency of the product, the decoupling capacitances are chosen considering the frequencies to filter, fop and 2 • fop. The relation between frequencies to cut and decoupling characteristics are defined by: fop = -----------1------------ and 2•fop = -----------1------------ 2Π LC 2Π LC 1 2 where: – L: the inductance equivalent to the global inductance on the Vcc/Gnd lines. – C & C : decoupling capacitors (C = 4 • C ). 1 2 1 2 Then, in normalized value range, the decoupling capacitors become: Table 27-1. Decoupling Capacitors vs. Frequency f , operating frequency C C op 1 2 16 MHz 33 nF 10 nF 12 MHz 56 nF 15 nF 10 MHz 82 nF 22 nF 8 MHz 120 nF 33 nF 6 MHz 220 nF 56 nF 4 MHz 560 nF 120 nF These decoupling capacitors must to be implemented as close as possible to each pair of power supply pins: – 21-22 and 52-53 for logic sub-system, – 64-63 for analogical sub-system. Nevertheless, a bulk capacitor of 10-47 µF is also needed on the power distribution network of the PCB, near the power source. For further information, please refer to Application Notes AVR040 “EMC Design Considerations“ and AVR042 “Hardware Design Considerations“ on the Atmel web site. 383 7679H–CAN–08/08

28. AT90CAN32/64/128 Typical Characteristics • The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock source. • The power consumption in Power-down mode is independent of clock selection. • The current consumption is a function of several factors such as: operating voltage, operating frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating voltage and frequency. • The current drawn from capacitive loaded pins may be estimated (for one pin) as C *V *f L CC where C = load capacitance, V = operating voltage and f = average switching frequency of L CC I/O pin. • The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to function properly at frequencies higher than the ordering code indicates. • The difference between current consumption in Power-down mode with Watchdog Timer enabled and Power-down mode with Watchdog Timer disabled represents the differential current drawn by the Watchdog Timer. 28.1 Active Supply Current Figure 28-1. Active Supply Current vs. Frequency (0.1 - 1.0 MHz) ACTIVE SUPPLY CURRENT vs. FREQUENCY (25°C, 0.1 - 1 MHz) 3 2.5 5.50V 2 5.00V A) 4.50V m 1.5 4.00V c ( c 3.30V I 1 3.00V 2.70V 0.5 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) AT90CAN32/64/128 384 7679H–CAN–08/08

AT90CAN32/64/128 Figure 28-2. Active Supply Current vs. Frequency (1 - 16 MHz) ACTIVE SUPPLY CURRENT vs. FREQUENCY (25°C, 1 - 16 MHz) 40 35 30 5.50V 25 5.00V A) 4.50V m 20 4.00V c ( c 3.30V I 15 3.00V 2.70V 10 5 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Frequency (MHz) Figure 28-3. Active Supply Current vs. Vcc (Internal RC Oscillator 8 MHz) ACTIVE SUPPLY CURRENT vs. Vcc (Internal RC Oscillator 8 MHz) 20 18 16 14 12 A) 85°C m 10 25°C c ( c -40°C I 8 6 4 2 0 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) 385 7679H–CAN–08/08

Figure 28-4. Active Supply Current vs. Vcc (Internal RC Oscillator 1 MHz) ACTIVE SUPPLY CURRENT vs. Vcc (Internal RC Oscillator 1 MHz) 3 2.5 2 A) 85°C m 1.5 25°C c ( c -40°C I 1 0.5 0 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Figure 28-5. Active Supply Current vs. Vcc (32 kHz Watch Crystal) ACTIVE SUPPLY CURRENT vs. Vcc (32 kHz Watch Crystal) 140 120 100 A) 80 c (u 25°C c 60 I 40 20 0 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) AT90CAN32/64/128 386 7679H–CAN–08/08

AT90CAN32/64/128 28.2 Idle Supply Current Figure 28-6. Idle Supply Current vs. Frequency (0.1 - 1.0 MHz) IDLE SUPPLY CURRENT vs. FREQUENCY (25°C, 0.1 - 1 MHz) 1.6 1.4 1.2 5.50V 5.00V 1 A) 4.50V m 0.8 4.00V c ( c 3.30V I 0.6 3.00V 0.4 2.70V 0.2 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 28-7. Idle Supply Current vs. Frequency (1 - 16 MHz) IDLE SUPPLY CURRENT vs. FREQUENCY (25°C, 1 - 16 MHz) 25 20 5.50V 5.00V 15 A) 4.50V m 4.00V c ( c 3.30V I 10 3.00V 2.70V 5 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Frequency (MHz) 387 7679H–CAN–08/08

Figure 28-8. Idle Supply Current vs. Vcc (Internal RC Oscillator 8 MHz) IDLE SUPPLY CURRENT vs. Vcc (Internal RC Oscillator 8 MHz) 14 12 10 A) 8 85°C m 25°C cc ( 6 -40°C I 4 2 0 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Figure 28-9. Idle Supply Current vs. Vcc (Internal RC Oscillator 1 MHz) IDLE SUPPLY CURRENT vs. Vcc (Internal RC Oscillator 1 MHz) 1.8 1.6 1.4 1.2 A) 1 85°C m 25°C c ( 0.8 c -40°C I 0.6 0.4 0.2 0 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) AT90CAN32/64/128 388 7679H–CAN–08/08

AT90CAN32/64/128 Figure 28-10. Idle Supply Current vs. Vcc (32 kHz Watch Crystal) IDLE SUPPLY CURRENT vs. Vcc (32 KHz Watch Crystal) 60 50 40 A) c (u 30 25°C c I 20 10 0 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) 28.3 Power-down Supply Current Figure 28-11. Power-down Supply Current vs. Vcc (Watchdog Timer Disabled) POWER-DOWN SUPPLY CURRENT vs. Vcc (Watchdog Timer Disabled) 9 8 7 6 A) 5 85°C c (u 4 25°C c -40°C I 3 2 1 0 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) 389 7679H–CAN–08/08

Figure 28-12. Power-down Supply Current vs. Vcc (Watchdog Timer Enabled) POWER-DOWN SUPPLY CURRENT vs. Vcc (Watchdog Timer Enabled) 25 22.5 20 17.5 15 A) 85°C c (u 12.5 25°C c -40°C I 10 7.5 5 2.5 0 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) 28.4 Power-save Supply Current Figure 28-13. Power-save Supply Current vs. Vcc (Watchdog Timer Disabled) POWER-SAVE SUPPLY CURRENT vs. Vcc (Watchdog Timer Disabled) 25 22.5 20 17.5 15 A) c (u 12.5 25°C c I 10 7.5 5 2.5 0 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) AT90CAN32/64/128 390 7679H–CAN–08/08

AT90CAN32/64/128 28.5 Standby Supply Current Figure 28-14. Power-save Supply Current vs. Vcc (25°C, Watchdog Timer Disabled) STANDBY SUPPLY CURRENT vs. Vcc (25°C, Watchdog Timer Disabled) 0.2 0.18 0.16 0.14 0.12 6 MHZ Xtal A) m 4 MHZ Res 0.1 c ( 2 MHZ Xtal c I 0.08 2 MHZ Res 0.06 0.04 0.02 0 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) 28.6 Pin Pull-up Figure 28-15. I/O Pin Pull-up Resistor Current vs. Input Voltage (Vcc = 5V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE (Vcc = 5V) 0 -20 -40 -60 A) 85°C (uO -80 25°C I I -40°C -100 -120 -140 -160 0 1 2 3 4 5 6 V IO (V) 391 7679H–CAN–08/08

Figure 28-16. I/O Pin Pull-up Resistor Current vs. Input Voltage (Vcc = 2.7V) I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE (Vcc = 2.7V) 0 -10 -20 -30 A) -40 85°C (uO -50 25°C I I -40°C -60 -70 -80 -90 0 0.5 1 1.5 2 2.5 3 V IO (V) Figure 28-17. Reset Pull-up Resistor Current vs. Reset Pin Voltage (Vcc = 5V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE (Vcc = 5V) 0 -20 -40 A) 85°C u (T -60 25°C E S RE -40°C I -80 -100 -120 0 1 2 3 4 5 6 V RESET (V) AT90CAN32/64/128 392 7679H–CAN–08/08

AT90CAN32/64/128 Figure 28-18. Reset Pull-up Resistor Current vs. Reset Pin Voltage (Vcc = 2.7V) RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE (Vcc = 2.7V) 0 -10 -20 A) -30 85°C u (T 25°C E S RE -40 -40°C I -50 -60 -70 0 0.5 1 1.5 2 2.5 3 V RESET (V) 28.7 Pin Driver Strength Figure 28-19. I/O Pin Source Current vs. Output Voltage (Vcc = 5V) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE (Vcc = 5V) 0 -10 -20 -30 A) -40 85°C m (H -50 25°C I O -40°C -60 -70 -80 -90 2.5 3 3.5 4 4.5 5 V OH (V) 393 7679H–CAN–08/08

Figure 28-20. I/O Pin Source Current vs. Output Voltage (Vcc = 2.7V) I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE (Vcc = 2.7V) 0 -5 -10 A) 85°C m (H -15 25°C I O -40°C -20 -25 -30 0.5 1 1.5 2 2.5 3 V OH (V) Figure 28-21. I/O Pin Sink Current vs. Output Voltage (Vcc = 5V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE (Vcc = 5V) 90 80 70 60 A) 50 85°C m (L 40 25°C I O -40°C 30 20 10 0 0 0.5 1 1.5 2 2.5 V OL (V) AT90CAN32/64/128 394 7679H–CAN–08/08

AT90CAN32/64/128 Figure 28-22. I/O Pin Sink Current vs. Output Voltage (Vcc = 2.7V) I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE (Vcc = 2.7V) 35 30 25 A) 20 85°C m I (OL 15 2-450°°CC 10 5 0 0 0.5 1 1.5 2 2.5 V OL (V) 28.8 Pin Thresholds and Hysteresis Figure 28-23. I/O Input Threshold Voltage vs. Vcc (V , I/O Pin Read as “1”) IH I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC (VIH, I/O PIN READ AS "1") 2 1.75 1.5 V) 85°C d ( ol 1.25 25°C h s e -40°C hr T 1 0.75 0.5 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) 395 7679H–CAN–08/08

Figure 1. I/O Input Threshold Voltage vs. Vcc (V , I/O Pin Read as “0”) IL I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC (VIL, I/O PIN READ AS "0") 2 1.75 1.5 V) d ( 85°C hol 1.25 25°C s e -40°C hr T 1 0.75 0.5 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Figure 2. I/O Input Hysteresis vs. Vcc I/O PIN INPUT HYSTERESIS vs. VCC 0.6 0.5 0.4 V) d ( 85°C hol 0.3 25°C s e -40°C hr T 0.2 0.1 0 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) AT90CAN32/64/128 396 7679H–CAN–08/08

AT90CAN32/64/128 28.9 BOD Thresholds and Analog Comparator Offset Figure 28-24. BOD Thresholds vs. Temperature (BOD level is 4.1V) BOD THRESHOLDS vs. TEMPERATURE (BOD level is 4.1V) 4.4 4.2 V) 4 old ( Rising Vcc h s Falling Vcc e hr 3.8 T 3.6 3.4 -60 -40 -20 0 20 40 60 80 100 Temp (°C) Figure 28-25. BOD Thresholds vs. Temperature (BOD level is 2.7V) BOD THRESHOLDS vs. TEMPERATURE (BOD level is 2.7V) 3 2.8 V) 2.6 old ( Rising Vcc h s Falling Vcc e hr 2.4 T 2.2 2 -60 -40 -20 0 20 40 60 80 100 Temp (°C) 397 7679H–CAN–08/08

Figure 28-26. Bandgap Voltage vs. Operating Voltage BANDGAP VOLTAGE vs. OPERATING VOLTAGE 1.14 1.13 V) e ( 1.12 g a 85°C Volt 1.11 25°C p -40°C a g nd 1.1 a B 1.09 1.08 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Figure 28-27. Analog Comparator Offset vs. Common Mode Voltage (Vcc = 5V) ANALOG COMPARATOR OFFSET vs. COMMON MODE VOLTAGE (Vcc = 5V) 0.012 0.01 V) ge ( 0.008 a olt et V 0.006 85°C s 25°C Off 0.004 -40°C or at ar 0.002 p m o C 0 -0.002 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Common Voltage Mode (V) AT90CAN32/64/128 398 7679H–CAN–08/08

AT90CAN32/64/128 28.10 Internal Oscillator Speed Figure 28-28. Watchdog Oscillator Frequency vs. Operating Voltage WATCHDOG OSCILLATOR FREQUENCY vs. VCC 1200 1150 1100 z) H 1050 (kG 85°C O 1000 25°C D H C -40°C T A 950 W F 900 850 800 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Figure 28-29. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE 8.8 8.6 8.4 8.2 z) 2.7V H M 8 4.0V (C R 5.5V F 7.8 7.6 7.4 7.2 -60 -40 -20 0 20 40 60 80 100 Temp (°C) 399 7679H–CAN–08/08

Figure 28-30. Calibrated 8 MHz RC Oscillator Frequency vs. Operating Voltage CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. VCC 10 9.5 9 8.5 z) 85°C H M 8 25°C (C R -40°C F 7.5 7 6.5 6 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Figure 28-31. Calibrated 8 MHz RC Oscillator Frequency vs. OSCCAL Value CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE 16 15 14 13 12 z) 11 85°C H M 10 25°C (C R 9 -40°C F 8 7 6 5 4 0 16 32 48 64 80 96 112 128 OSCCAL Value AT90CAN32/64/128 400 7679H–CAN–08/08

AT90CAN32/64/128 28.11 Current Consumption of Peripheral Units Figure 28-32. Brownout Detector Current vs. Operating Voltage BROWNOUT DETECTOR CURRENT vs. Vcc 35 30 25 A) 85°C c (u 20 25°C c -40°C I 15 10 5 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Figure 28-33. ADC Current vs. Operating Voltage (ADC at 1 MHz) ADC CURRENT vs. Vcc (ADC at 1 MHz) 300 250 200 A) 85°C c (u 150 25°C c -40°C I 100 50 0 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) 401 7679H–CAN–08/08

Figure 28-34. AREF External Reference Current vs. Operating Voltage AREF EXTERNAL REFERENCE CURRENT vs. Vcc 200 180 160 140 A) 85°C u (F 120 25°C E R -40°C A I 100 80 60 40 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) Figure 28-35. Analog Comparator Current vs. Operating Voltage ANALOG COMPARATOR CURRENT vs. Vcc 120 100 80 A) 85°C (uC 60 25°C I C -40°C 40 20 0 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) AT90CAN32/64/128 402 7679H–CAN–08/08

AT90CAN32/64/128 Figure 28-36. Programming Current vs. Operating Voltage PROGRAMMING CURRENT vs. Vcc 25 20 15 A) 85°C m 25°C (C C -40°C I 10 5 0 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) 28.12 Current Consumption in Reset and Reset Pulse Width Figure 28-37. Reset Supply Current vs. Operating Voltage (0.1 - 1.0 MHz) (Excluding Current Through the Reset Pull-up) RESET SUPPLY CURRENT vs. FREQUENCY (25°C, 0.1 - 1 MHz) (EXCLUDING CURRENT THROUGH THE RESET PULL-UP) 0.25 0.2 5.50V 5.00V 0.15 A) 4.50V m 4.00V c ( Ic 0.1 3.30V 3.00V 2.70V 0.05 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) 403 7679H–CAN–08/08

Figure 28-38. Reset Supply Current vs. Operating Voltage (1 - 16 MHz) (Excluding Current Through the Reset Pull-up) RESET SUPPLY CURRENT vs. FREQUENCY (1 - 16 MHz) (EXCLUDING CURRENT THROUGH THE RESET PULL-UP) 3.5 3 2.5 5.50V 5.00V A) 2 4.50V m 4.00V c ( c 1.5 3.30V I 3.00V 1 2.70V 0.5 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Frequency (MHz) Figure 28-39. Minimum Reset Pulse Width vs. Operating Voltage MINIMUM RESET PULSE WIDTH vs. Vcc 1500 1250 s) 1000 n h ( 85°C Widt 750 25°C e -40°C s Pul 500 250 0 2.5 3 3.5 4 4.5 5 5.5 Vcc (V) AT90CAN32/64/128 404 7679H–CAN–08/08

AT90CAN32/64/128 29. Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page (0xFF) Reserved (0xFE) Reserved (0xFD) Reserved (0xFC) Reserved (0xFB) Reserved (0xFA) CANMSG MSG 7 MSG 6 MSG 5 MSG 4 MSG 3 MSG 2 MSG 1 MSG 0 page 266 (0xF9) CANSTMH TIMSTM15 TIMSTM14 TIMSTM13 TIMSTM12 TIMSTM11 TIMSTM10 TIMSTM9 TIMSTM8 page 266 (0xF8) CANSTML TIMSTM7 TIMSTM6 TIMSTM5 TIMSTM4 TIMSTM3 TIMSTM2 TIMSTM1 TIMSTM0 page 266 (0xF7) CANIDM1 IDMSK28 IDMSK27 IDMSK26 IDMSK25 IDMSK24 IDMSK23 IDMSK22 IDMSK21 page 265 (0xF6) CANIDM2 IDMSK20 IDMSK19 IDMSK18 IDMSK17 IDMSK16 IDMSK15 IDMSK14 IDMSK13 page 265 (0xF5) CANIDM3 IDMSK12 IDMSK11 IDMSK10 IDMSK9 IDMSK8 IDMSK7 IDMSK6 IDMSK5 page 265 (0xF4) CANIDM4 IDMSK4 IDMSK3 IDMSK2 IDMSK1 IDMSK0 RTRMSK – IDEMSK page 265 (0xF3) CANIDT1 IDT28 IDT27 IDT26 IDT25 IDT24 IDT23 IDT22 IDT21 page 263 (0xF2) CANIDT2 IDT20 IDT19 IDT18 IDT17 IDT16 IDT15 IDT14 IDT13 page 263 (0xF1) CANIDT3 IDT12 IDT11 IDT10 IDT9 IDT8 IDT7 IDT6 IDT5 page 263 (0xF0) CANIDT4 IDT4 IDT3 IDT2 IDT1 IDT0 RTRTAG RB1TAG RB0TAG page 263 (0xEF) CANCDMOB CONMOB1 CONMOB0 RPLV IDE DLC3 DLC2 DLC1 DLC0 page 262 (0xEE) CANSTMOB DLCW TXOK RXOK BERR SERR CERR FERR AERR page 261 (0xED) CANPAGE MOBNB3 MOBNB2 MOBNB1 MOBNB0 AINC INDX2 INDX1 INDX0 page 260 (0xEC) CANHPMOB HPMOB3 HPMOB2 HPMOB1 HPMOB0 CGP3 CGP2 CGP1 CGP0 page 260 (0xEB) CANREC REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0 page 260 (0xEA) CANTEC TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0 page 260 (0xE9) CANTTCH TIMTTC15 TIMTTC14 TIMTTC13 TIMTTC12 TIMTTC11 TIMTTC10 TIMTTC9 TIMTTC8 page 260 (0xE8) CANTTCL TIMTTC7 TIMTTC6 TIMTTC5 TIMTTC4 TIMTTC3 TIMTTC2 TIMTTC1 TIMTTC0 page 260 (0xE7) CANTIMH CANTIM15 CANTIM14 CANTIM13 CANTIM12 CANTIM11 CANTIM10 CANTIM9 CANTIM8 page 259 (0xE6) CANTIML CANTIM7 CANTIM6 CANTIM5 CANTIM4 CANTIM3 CANTIM2 CANTIM1 CANTIM0 page 259 (0xE5) CANTCON TPRSC7 TPRSC6 TPRSC5 TPRSC4 TPRSC3 TPRSC2 TRPSC1 TPRSC0 page 259 (0xE4) CANBT3 – PHS22 PHS21 PHS20 PHS12 PHS11 PHS10 SMP page 258 (0xE3) CANBT2 – SJW1 SJW0 – PRS2 PRS1 PRS0 – page 258 (0xE2) CANBT1 – BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 – page 257 (0xE1) CANSIT1 – SIT14 SIT13 SIT12 SIT11 SIT10 SIT9 SIT8 page 257 (0xE0) CANSIT2 SIT7 SIT6 SIT5 SIT4 SIT3 SIT2 SIT1 SIT0 page 257 (0xDF) CANIE1 – IEMOB14 IEMOB13 IEMOB12 IEMOB11 IEMOB10 IEMOB9 IEMOB8 page 257 (0xDE) CANIE2 IEMOB7 IEMOB6 IEMOB5 IEMOB4 IEMOB3 IEMOB2 IEMOB1 IEMOB0 page 257 (0xDD) CANEN1 – ENMOB14 ENMOB13 ENMOB12 ENMOB11 ENMOB10 ENMOB9 ENMOB8 page 256 (0xDC) CANEN2 ENMOB7 ENMOB6 ENMOB5 ENMOB4 ENMOB3 ENMOB2 ENMOB1 ENMOB0 page 256 (0xDB) CANGIE ENIT ENBOFF ENRX ENTX ENERR ENBX ENERG ENOVRT page 255 (0xDA) CANGIT CANIT BOFFIT OVRTIM BXOK SERG CERG FERG AERG page 254 (0xD9) CANGSTA – OVRG – TXBSY RXBSY ENFG BOFF ERRP page 253 (0xD8) CANGCON ABRQ OVRQ TTC SYNTTC LISTEN TEST ENA/STB SWRES page 252 (0xD7) Reserved (0xD6) Reserved (0xD5) Reserved (0xD4) Reserved (0xD3) Reserved (0xD2) Reserved (0xD1) Reserved (0xD0) Reserved (0xCF) Reserved (0xCE) UDR1 UDR17 UDR16 UDR15 UDR14 UDR13 UDR12 UDR11 UDR10 page 195 (0xCD) UBRR1H – – – – UBRR111 UBRR110 UBRR19 UBRR18 page 199 (0xCC) UBRR1L UBRR17 UBRR16 UBRR15 UBRR14 UBRR13 UBRR12 UBRR11 UBRR10 page 199 (0xCB) Reserved (0xCA) UCSR1C – UMSEL1 UPM11 UPM10 USBS1 UCSZ11 UCSZ10 UCPOL1 page 198 (0xC9) UCSR1B RXCIE1 TXCIE1 UDRIE1 RXEN1 TXEN1 UCSZ12 RXB81 TXB81 page 197 (0xC8) UCSR1A RXC1 TXC1 UDRE1 FE1 DOR1 UPE1 U2X1 MPCM1 page 195 (0xC7) Reserved (0xC6) UDR0 UDR07 UDR06 UDR05 UDR04 UDR03 UDR02 UDR01 UDR00 page 195 (0xC5) UBRR0H – – – – UBRR011 UBRR010 UBRR09 UBRR08 page 199 (0xC4) UBRR0L UBRR07 UBRR06 UBRR05 UBRR04 UBRR03 UBRR02 UBRR01 UBRR00 page 199 (0xC3) Reserved (0xC2) UCSR0C – UMSEL0 UPM01 UPM00 USBS0 UCSZ01 UCSZ00 UCPOL0 page 197 (0xC1) UCSR0B RXCIE0 TXCIE0 UDRIE0 RXEN0 TXEN0 UCSZ02 RXB80 TXB80 page 196 (0xC0) UCSR0A RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0 page 195 (0xBF) Reserved 405 7679H–CAN–08/08

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page (0xBE) Reserved (0xBD) Reserved (0xBC) TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE page 212 (0xBB) TWDR TWDR7 TWDR6 TWDR5 TWDR4 TWDR3 TWDR2 TWDR1 TWDR0 page 214 (0xBA) TWAR TWAR6 TWAR5 TWAR4 TWAR3 TWAR2 TWAR1 TWAR0 TWGCE page 214 (0xB9) TWSR TWS7 TWS6 TWS5 TWS4 TWS3 – TWPS1 TWPS0 page 213 (0xB8) TWBR TWBR7 TWBR6 TWBR5 TWBR4 TWBR3 TWBR2 TWBR1 TWBR0 page 212 (0xB7) Reserved (0xB6) ASSR – – – EXCLK AS2 TCN2UB OCR2UB TCR2UB page 160 (0xB5) Reserved (0xB4) Reserved (0xB3) OCR2A OCR2A7 OCR2A6 OCR2A5 OCR2A4 OCR2A3 OCR2A2 OCR2A1 OCR2A0 page 159 (0xB2) TCNT2 TCNT27 TCNT26 TCNT25 TCNT24 TCNT23 TCNT22 TCNT21 TCNT20 page 159 (0xB1) Reserved (0xB0) TCCR2A FOC2A WGM20 COM2A1 COM2A0 WGM21 CS22 CS21 CS20 page 164 (0xAF) Reserved (0xAE) Reserved (0xAD) Reserved (0xAC) Reserved (0xAB) Reserved (0xAA) Reserved (0xA9) Reserved (0xA8) Reserved (0xA7) Reserved (0xA6) Reserved (0xA5) Reserved (0xA4) Reserved (0xA3) Reserved (0xA2) Reserved (0xA1) Reserved (0xA0) Reserved (0x9F) Reserved (0x9E) Reserved (0x9D) OCR3CH OCR3C15 OCR3C14 OCR3C13 OCR3C12 OCR3C11 OCR3C10 OCR3C9 OCR3C8 page 141 (0x9C) OCR3CL OCR3C7 OCR3C6 OCR3C5 OCR3C4 OCR3C3 OCR3C2 OCR3C1 OCR3C0 page 141 (0x9B) OCR3BH OCR3B15 OCR3B14 OCR3B13 OCR3B12 OCR3B11 OCR3B10 OCR3B9 OCR3B8 page 141 (0x9A) OCR3BL OCR3B7 OCR3B6 OCR3B5 OCR3B4 OCR3B3 OCR3B2 OCR3B1 OCR3B0 page 141 (0x99) OCR3AH OCR3A15 OCR3A14 OCR3A13 OCR3A12 OCR3A11 OCR3A10 OCR3A9 OCR3A8 page 141 (0x98) OCR3AL OCR3A7 OCR3A6 OCR3A5 OCR3A4 OCR3A3 OCR3A2 OCR3A1 OCR3A0 page 141 (0x97) ICR3H ICR315 ICR314 ICR313 ICR312 ICR311 ICR310 ICR39 ICR38 page 142 (0x96) ICR3L ICR37 ICR36 ICR35 ICR34 ICR33 ICR32 ICR31 ICR30 page 142 (0x95) TCNT3H TCNT315 TCNT314 TCNT313 TCNT312 TCNT311 TCNT310 TCNT39 TCNT38 page 140 (0x94) TCNT3L TCNT37 TCNT36 TCNT35 TCNT34 TCNT33 TCNT32 TCNT31 TCNT30 page 140 (0x93) Reserved (0x92) TCCR3C FOC3A FOC3B FOC3C – – – – page 140 (0x91) TCCR3B ICNC3 ICES3 – WGM33 WGM32 CS32 CS31 CS30 page 138 (0x90) TCCR3A COM3A1 COM3A0 COM3B1 COM3B0 COM3C1 COM3C0 WGM31 WGM30 page 135 (0x8F) Reserved (0x8E) Reserved (0x8D) OCR1CH OCR1C15 OCR1C14 OCR1C13 OCR1C12 OCR1C11 OCR1C10 OCR1C9 OCR1C8 page 141 (0x8C) OCR1CL OCR1C7 OCR1C6 OCR1C5 OCR1C4 OCR1C3 OCR1C2 OCR1C1 OCR1C0 page 141 (0x8B) OCR1BH OCR1B15 OCR1B14 OCR1B13 OCR1B12 OCR1B11 OCR1B10 OCR1B9 OCR1B8 page 141 (0x8A) OCR1BL OCR1B7 OCR1B6 OCR1B5 OCR1B4 OCR1B3 OCR1B2 OCR1B1 OCR1B0 page 141 (0x89) OCR1AH OCR1A15 OCR1A14 OCR1A13 OCR1A12 OCR1A11 OCR1A10 OCR1A9 OCR1A8 page 141 (0x88) OCR1AL OCR1A7 OCR1A6 OCR1A5 OCR1A4 OCR1A3 OCR1A2 OCR1A1 OCR1A0 page 141 (0x87) ICR1H ICR115 ICR114 ICR113 ICR112 ICR111 ICR110 ICR19 ICR18 page 142 (0x86) ICR1L ICR17 ICR16 ICR15 ICR14 ICR13 ICR12 ICR11 ICR10 page 142 (0x85) TCNT1H TCNT115 TCNT114 TCNT113 TCNT112 TCNT111 TCNT110 TCNT19 TCNT18 page 140 (0x84) TCNT1L TCNT17 TCNT16 TCNT15 TCNT14 TCNT13 TCNT12 TCNT11 TCNT10 page 140 (0x83) Reserved (0x82) TCCR1C FOC1A FOC1B FOC1C – – – – – page 139 (0x81) TCCR1B ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 page 138 (0x80) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 COM1C1 COM1C0 WGM11 WGM10 page 135 (0x7F) DIDR1 – – – – – – AIN1D AIN0D page 272 (0x7E) DIDR0 ADC7D ADC6D ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D page 292 (0x7D) Reserved AT90CAN32/64/128 406 7679H–CAN–08/08

AT90CAN32/64/128 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page (0x7C) ADMUX REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 page 287 (0x7B) ADCSRB – ACME – – – ADTS2 ADTS1 ADTS0 page 291, 269 (0x7A) ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 page 289 (0x79) ADCH - / ADC9 - / ADC8 - / ADC7 - / ADC6 - / ADC5 - / ADC4 ADC9 / ADC3 ADC8 / ADC2 page 290 (0x78) ADCL ADC7 / ADC1 ADC6 / ADC0 ADC5 / - ADC4 / - ADC3 / - ADC2 / - ADC1 / - ADC0 / page 290 (0x77) Reserved (0x76) Reserved (0x75) XMCRB XMBK – – – – XMM2 XMM1 XMM0 page 33 (0x74) XMCRA SRE SRL2 SRL1 SRL0 SRW11 SRW10 SRW01 SRW00 page 32 (0x73) Reserved (0x72) Reserved (0x71) TIMSK3 – – ICIE3 – OCIE3C OCIE3B OCIE3A TOIE3 page 142 (0x70) TIMSK2 – – – – – – OCIE2A TOIE2 page 162 (0x6F) TIMSK1 – – ICIE1 – OCIE1C OCIE1B OCIE1A TOIE1 page 142 (0x6E) TIMSK0 – – – – – – OCIE0A TOIE0 page 112 (0x6D) Reserved (0x6C) Reserved (0x6B) Reserved (0x6A) EICRB ISC71 ISC70 ISC61 ISC60 ISC51 ISC50 ISC41 ISC40 page 94 (0x69) EICRA ISC31 ISC30 ISC21 ISC20 ISC11 ISC10 ISC01 ISC00 page 93 (0x68) Reserved (0x67) Reserved (0x66) OSCCAL – CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 page 42 (0x65) Reserved (0x64) Reserved (0x63) Reserved (0x62) Reserved (0x61) CLKPR CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 page 44 (0x60) WDTCR – – – WDCE WDE WDP2 WDP1 WDP0 page 58 0x3F (0x5F) SREG I T H S V N Z C page 11 0x3E (0x5E) SPH SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 page 14 0x3D (0x5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 page 14 0x3C (0x5C) Reserved 0x3B (0x5B) RAMPZ(1) – – – – – – – RAMPZ0 page 13 0x3A (0x5A) Reserved 0x39 (0x59) Reserved 0x38 (0x58) Reserved 0x37 (0x57) SPMCSR SPMIE RWWSB – RWWSRE BLBSET PGWRT PGERS SPMEN page 326 0x36 (0x56) Reserved – – – – – – – – 0x35 (0x55) MCUCR JTD – – PUD – – IVSEL IVCE page 64, 73, 304 0x34 (0x54) MCUSR – – – JTRF WDRF BORF EXTRF PORF page 56, 304 0x33 (0x53) SMCR – – – – SM2 SM1 SM0 SE page 46 0x32 (0x52) Reserved 0x31 (0x51) OCDR IDRD/OCDR7 OCDR6 OCDR5 OCDR4 OCDR3 OCDR2 OCDR1 OCDR0 page 299 0x30 (0x50) ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 page 270 0x2F (0x4F) Reserved 0x2E (0x4E) SPDR SPD7 SPD6 SPD5 SPD4 SPD3 SPD2 SPD1 SPD0 page 175 0x2D (0x4D) SPSR SPIF WCOL – – – – – SPI2X page 175 0x2C (0x4C) SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 page 173 0x2B (0x4B) GPIOR2 GPIOR27 GPIOR26 GPIOR25 GPIOR24 GPIOR23 GPIOR22 GPIOR21 GPIOR20 page 36 0x2A (0x4A) GPIOR1 GPIOR17 GPIOR16 GPIOR15 GPIOR14 GPIOR13 GPIOR12 GPIOR11 GPIOR10 page 36 0x29 (0x49) Reserved 0x28 (0x48) Reserved 0x27 (0x47) OCR0A OCR0A7 OCR0A6 OCR0A5 OCR0A4 OCR0A3 OCR0A2 OCR0A1 OCR0A0 page 112 0x26 (0x46) TCNT0 TCNT07 TCNT06 TCNT05 TCNT04 TCNT03 TCNT02 TCNT01 TCNT00 page 111 0x25 (0x45) Reserved 0x24 (0x44) TCCR0A FOC0A WGM00 COM0A1 COM0A0 WGM01 CS02 CS01 CS00 page 109 0x23 (0x43) GTCCR TSM – – – – – PSR2 PSR310 page 98, 164 0x22 (0x42) EEARH(2) – – – – EEAR11 EEAR10 EEAR9 EEAR8 page 22 0x21 (0x41) EEARL EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 page 22 0x20 (0x40) EEDR EEDR7 EEDR6 EEDR5 EEDR4 EEDR3 EEDR2 EEDR1 EEDR0 page 23 0x1F (0x3F) EECR – – – – EERIE EEMWE EEWE EERE page 23 0x1E (0x3E) GPIOR0 GPIOR07 GPIOR06 GPIOR05 GPIOR04 GPIOR03 GPIOR02 GPIOR01 GPIOR00 page 36 0x1D (0x3D) EIMSK INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0 page 95 0x1C (0x3C) EIFR INTF7 INTF6 INTF5 INTF4 INTF3 INTF2 INTF1 INTF0 page 95 0x1B (0x3B) Reserved 407 7679H–CAN–08/08

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x1A (0x3A) Reserved 0x19 (0x39) Reserved 0x18 (0x38) TIFR3 – – ICF3 – OCF3C OCF3B OCF3A TOV3 page 143 0x17 (0x37) TIFR2 – – – – – – OCF2A TOV2 page 162 0x16 (0x36) TIFR1 – – ICF1 – OCF1C OCF1B OCF1A TOV1 page 143 0x15 (0x35) TIFR0 – – – – – – OCF0A TOV0 page 112 0x14 (0x34) PORTG – – – PORTG4 PORTG3 PORTG2 PORTG1 PORTG0 page 92 0x13 (0x33) DDRG – – – DDG4 DDG3 DDG2 DDG1 DDG0 page 92 0x12 (0x32) PING – – – PING4 PING3 PING2 PING1 PING0 page 92 0x11 (0x31) PORTF PORTF7 PORTF6 PORTF5 PORTF4 PORTF3 PORTF2 PORTF1 PORTF0 page 91 0x10 (0x30) DDRF DDF7 DDF6 DDF5 DDF4 DDF3 DDF2 DDF1 DDF0 page 91 0x0F (0x2F) PINF PINF7 PINF6 PINF5 PINF4 PINF3 PINF2 PINF1 PINF0 page 92 0x0E (0x2E) PORTE PORTE7 PORTE6 PORTE5 PORTE4 PORTE3 PORTE2 PORTE1 PORTE0 page 91 0x0D (0x2D) DDRE DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 DDE1 DDE0 page 91 0x0C (0x2C) PINE PINE7 PINE6 PINE5 PINE4 PINE3 PINE2 PINE1 PINE0 page 91 0x0B (0x2B) PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 page 91 0x0A (0x2A) DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 page 91 0x09 (0x29) PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 page 91 0x08 (0x28) PORTC PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 page 90 0x07 (0x27) DDRC DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 page 90 0x06 (0x26) PINC PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 page 90 0x05 (0x25) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 page 90 0x04 (0x24) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 page 90 0x03 (0x23) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 page 90 0x02 (0x22) PORTA PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 page 89 0x01 (0x21) DDRA DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 page 90 0x00 (0x20) PINA PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 page 90 Notes: 1. Address bits exceeding PCMSB (Table 25-11 on page 341) are don’t care. 2. Address bits exceeding EEAMSB (Table 25-12 on page 341) are don’t care. 3. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 4. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 5. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 6. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The AT90CAN32/64/128 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. AT90CAN32/64/128 408 7679H–CAN–08/08

AT90CAN32/64/128 30. Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H 1 ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2 SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1 SBCI Rd, K Subtract with Carry Constant from Reg. Rd ← Rd - K - C Z,C,N,V,H 1 SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl ← Rdh:Rdl - K Z,C,N,V,S 2 AND Rd, Rr Logical AND Registers Rd ← Rd • Rr Z,N,V 1 ANDI Rd, K Logical AND Register and Constant Rd ← Rd • K Z,N,V 1 OR Rd, Rr Logical OR Registers Rd ← Rd v Rr Z,N,V 1 ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V 1 EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V 1 COM Rd One’s Complement Rd ← 0xFF − Rd Z,C,N,V 1 NEG Rd Two’s Complement Rd ← 0x00 − Rd Z,C,N,V,H 1 SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1 CBR Rd,K Clear Bit(s) in Register Rd ← Rd • (0xFF - K) Z,N,V 1 INC Rd Increment Rd ← Rd + 1 Z,N,V 1 DEC Rd Decrement Rd ← Rd − 1 Z,N,V 1 TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V 1 CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1 SER Rd Set Register Rd ← 0xFF None 1 MUL Rd, Rr Multiply Unsigned R1:R0 ← Rd x Rr Z,C 2 MULS Rd, Rr Multiply Signed R1:R0 ← Rd x Rr Z,C 2 MULSU Rd, Rr Multiply Signed with Unsigned R1:R0 ← Rd x Rr Z,C 2 FMUL Rd, Rr Fractional Multiply Unsigned R1:R0 ← (Rd x Rr) << 1 Z,C 2 FMULS Rd, Rr Fractional Multiply Signed R1:R0 ← (Rd x Rr) << 1 Z,C 2 FMULSU Rd, Rr Fractional Multiply Signed with Unsigned R1:R0 ← (Rd x Rr) << 1 Z,C 2 BRANCH INSTRUCTIONS RJMP k Relative Jump PC ← PC + k + 1 None 2 IJMP Indirect Jump to (Z) PC ← Z None 2 JMP k Direct Jump PC ← k None 3 RCALL k Relative Subroutine Call PC ← PC + k + 1 None 3 ICALL Indirect Call to (Z) PC ← Z None 3 CALL k Direct Subroutine Call PC ← k None 4 RET Subroutine Return PC ← STACK None 4 RETI Interrupt Return PC ← STACK I 4 CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1/2/3 CP Rd,Rr Compare Rd − Rr Z, N,V,C,H 1 CPC Rd,Rr Compare with Carry Rd − Rr − C Z, N,V,C,H 1 CPI Rd,K Compare Register with Immediate Rd − K Z, N,V,C,H 1 SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ← PC + 2 or 3 None 1/2/3 SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC ← PC + 2 or 3 None 1/2/3 SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC ← PC + 2 or 3 None 1/2/3 SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC ← PC + 2 or 3 None 1/2/3 BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC←PC+k + 1 None 1/2 BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC←PC+k + 1 None 1/2 BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1/2 BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1/2 BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1/2 BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1/2 BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1/2 BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1/2 BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1/2 BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1/2 BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1 None 1/2 BRLT k Branch if Less Than Zero, Signed if (N ⊕ V= 1) then PC ← PC + k + 1 None 1/2 BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1/2 BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1/2 BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1 None 1/2 BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1/2 BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1/2 BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2 409 7679H–CAN–08/08

Mnemonics Operands Description Operation Flags #Clocks BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2 BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register I/O(P,b) ← 1 None 2 CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0 None 2 LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1 LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1 ROL Rd Rotate Left Through Carry Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Z,C,N,V 1 ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V 1 ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1 SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0) None 1 BSET s Flag Set SREG(s) ← 1 SREG(s) 1 BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1 BST Rr, b Bit Store from Register to T T ← Rr(b) T 1 BLD Rd, b Bit load from T to Register Rd(b) ← T None 1 SEC Set Carry C ← 1 C 1 CLC Clear Carry C ← 0 C 1 SEN Set Negative Flag N ← 1 N 1 CLN Clear Negative Flag N ← 0 N 1 SEZ Set Zero Flag Z ← 1 Z 1 CLZ Clear Zero Flag Z ← 0 Z 1 SEI Global Interrupt Enable I ← 1 I 1 CLI Global Interrupt Disable I ← 0 I 1 SES Set Signed Test Flag S ← 1 S 1 CLS Clear Signed Test Flag S ← 0 S 1 SEV Set Twos Complement Overflow. V ← 1 V 1 CLV Clear Twos Complement Overflow V ← 0 V 1 SET Set T in SREG T ← 1 T 1 CLT Clear T in SREG T ← 0 T 1 SEH Set Half Carry Flag in SREG H ← 1 H 1 CLH Clear Half Carry Flag in SREG H ← 0 H 1 DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move Between Registers Rd ← Rr None 1 MOVW Rd, Rr Copy Register Word Rd+1:Rd ← Rr+1:Rr None 1 LDI Rd, K Load Immediate Rd ← K None 1 LD Rd, X Load Indirect Rd ← (X) None 2 LD Rd, X+ Load Indirect and Post-Inc. Rd ← (X), X ← X + 1 None 2 LD Rd, - X Load Indirect and Pre-Dec. X ← X - 1, Rd ← (X) None 2 LD Rd, Y Load Indirect Rd ← (Y) None 2 LD Rd, Y+ Load Indirect and Post-Inc. Rd ← (Y), Y ← Y + 1 None 2 LD Rd, - Y Load Indirect and Pre-Dec. Y ← Y - 1, Rd ← (Y) None 2 LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q) None 2 LD Rd, Z Load Indirect Rd ← (Z) None 2 LD Rd, Z+ Load Indirect and Post-Inc. Rd ← (Z), Z ← Z+1 None 2 LD Rd, -Z Load Indirect and Pre-Dec. Z ← Z - 1, Rd ← (Z) None 2 LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2 LDS Rd, k Load Direct from SRAM Rd ← (k) None 2 ST X, Rr Store Indirect (X) ← Rr None 2 ST X+, Rr Store Indirect and Post-Inc. (X) ← Rr, X ← X + 1 None 2 ST - X, Rr Store Indirect and Pre-Dec. X ← X - 1, (X) ← Rr None 2 ST Y, Rr Store Indirect (Y) ← Rr None 2 ST Y+, Rr Store Indirect and Post-Inc. (Y) ← Rr, Y ← Y + 1 None 2 ST - Y, Rr Store Indirect and Pre-Dec. Y ← Y - 1, (Y) ← Rr None 2 STD Y+q,Rr Store Indirect with Displacement (Y + q) ← Rr None 2 ST Z, Rr Store Indirect (Z) ← Rr None 2 ST Z+, Rr Store Indirect and Post-Inc. (Z) ← Rr, Z ← Z + 1 None 2 ST -Z, Rr Store Indirect and Pre-Dec. Z ← Z - 1, (Z) ← Rr None 2 STD Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None 2 STS k, Rr Store Direct to SRAM (k) ← Rr None 2 LPM Load Program Memory R0 ← (Z) None 3 LPM Rd, Z Load Program Memory Rd ← (Z) None 3 LPM Rd, Z+ Load Program Memory and Post-Inc Rd ← (Z), Z ← Z+1 None 3 ELPM Extended Load Program Memory R0 ← (RAMPZ:Z) None 3 ELPM Rd, Z Extended Load Program Memory Rd ← (RAMPZ:Z) None 3 ELPM Rd, Z+ Extended Load Program Memory and Post-Inc Rd ← (RAMPZ:Z), RAMPZ:Z ← RAMPZ:Z+1 None 3 SPM Store Program Memory (Z) ← R1:R0 None - AT90CAN32/64/128 410 7679H–CAN–08/08

AT90CAN32/64/128 Mnemonics Operands Description Operation Flags #Clocks IN Rd, P In Port Rd ← P None 1 OUT P, Rr Out Port P ← Rr None 1 PUSH Rr Push Register on Stack STACK ← Rr None 2 POP Rd Pop Register from Stack Rd ← STACK None 2 MCU CONTROL INSTRUCTIONS NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR Watchdog Reset (see specific descr. for WDR/timer) None 1 BREAK Break For On-chip Debug Only None N/A 411 7679H–CAN–08/08

31. Ordering Information (1) Ordering Code Speed (MHz) Power Supply (V) Package Operation Range Product Marking AT90CAN32-16AI 16 2.7 - 5.5 A2 64 Industrial (-40° to +85°C) AT90CAN32-16AI AT90CAN32-16MI 16 2.7 - 5.5 Z64-1 Industrial (-40° to +85°C) AT90CAN32-16MI Industrial (-40° to +85°C) AT90CAN32-16AU 16 2.7 - 5.5 A2 64 AT90CAN32-16AU Green Industrial (-40° to +85°C) AT90CAN32-16MU 16 2.7 - 5.5 Z64-1 AT90CAN32-16MU Green AT90CAN64-16AI 16 2.7 - 5.5 A2 64 Industrial (-40° to +85°C) AT90CAN64-16AI AT90CAN64-16MI 16 2.7 - 5.5 Z64-2 Industrial (-40° to +85°C) AT90CAN64-16MI Industrial (-40° to +85°C) AT90CAN64-16AU 16 2.7 - 5.5 A2 64 AT90CAN64-16AU Green Industrial (-40° to +85°C) AT90CAN64-16MU 16 2.7 - 5.5 Z64-2 AT90CAN64-16MU Green AT90CAN128-16AI 16 2.7 - 5.5 A2 64 Industrial (-40° to +85°C) AT90CAN128-16AI AT90CAN128-16MI 16 2.7 - 5.5 Z64-2 Industrial (-40° to +85°C) AT90CAN128-16MI Industrial (-40° to +85°C) AT90CAN128-16AU 16 2.7 - 5.5 A2 64 AT90CAN128-16AU Green Industrial (-40° to +85°C) AT90CAN128-16MU 16 2.7 - 5.5 Z64-2 AT90CAN128-16MU Green Notes: 1. These devices can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering informa- tion and minimum quantities. 32. Packaging Information Package Type A2 64 64-Lead, Thin (1.0 mm / 0.03937 in) Plastic Gull Wing Quad Flat Package. Z64-1 64-Lead, QFN, Exposed Die Attach Pad D2/E2: 5.4 ± 0.1mm / 0.212 ± 0.004 in. Z64-2 64-Lead, QFN, Exposed Die Attach Pad D2/E2: 6.0 ± 0.1mm / 0.236 ± 0.004 in. AT90CAN32/64/128 412 7679H–CAN–08/08

AT90CAN32/64/128 32.1 TQFP64 64 PINS THIN QUAD FLAT PACK D 0O to 7O A L 64 e 1 E E1 f J C TOP VIEW 11O / 13O SIDE VIEW A2 DRAWINGS NOT SCALED 0.100 mm LEAD COPLANARITY MM INCH Min Max Min Max A - - - - 1.20 - - - - 0.047 A2 0.95 1.05 0.037 0.041 C 0.09 0.20 0.004 0.008 D 16.00 BSC 0.630 BSC D1 14.00 BSC 0.551 BSC E 16.00 BSC 0.630 BSC E1 14.00 BSC 0.551 BSC J 0.05 0.15 0.002 0.006 L 0.45 0.75 0.018 0.030 e 0.80 BSC 0.0315 BSC f 0.30 0.45 0.012 0.018 413 7679H–CAN–08/08

32.2 QFN64 AT90CAN32/64/128 414 7679H–CAN–08/08

AT90CAN32/64/128 415 7679H–CAN–08/08

33. Errata 33.1 Errata Summary 33.1.1 AT90CAN32 RevB (Date code ≥ 0107) • CAN acknowledge error in 3-sample mode with prescaler =1 • CAN transmission after 3-bit intermission • Asynchronous Timer-2 wakes up without interrupt 33.1.2 AT90CAN32 RevA (Date code < 0107) • CAN acknowledge error in 3-sample mode with prescaler =1 • CAN transmission after 3-bit intermission • Asynchronous Timer-2 wakes up without interrupt • Reset of Timer-2 flags in asynchronous mode • Miss-functioning when code stack is in XRAM 33.1.3 AT90CAN64 RevA • LPM Instruction versus Protection levels and BOOTSIZE • CAN acknowledge error in 3-sample mode with prescaler =1 • CAN transmission after 3-bit intermission • Asynchronous Timer-2 wakes up without interrupt 33.1.4 AT90CAN128 RevD (Date code ≥ 0107) • CAN acknowledge error in 3-sample mode with prescaler =1 • CAN transmission after 3-bit intermission • Asynchronous Timer-2 wakes up without interrupt 33.1.5 AT90CAN128 RevC (Date code < 4006) • CAN acknowledge error in 3-sample mode with prescaler =1 • CAN transmission after 3-bit intermission • Asynchronous Timer-2 wakes up without interrupt • Reset of Timer-2 flags in asynchronous mode • Miss-functioning when code stack is in XRAM • Extra consumption in power reduction modes • Power supply current in Power-down mode 33.2 Errata Description 8. AT90CAN64 : LPM Instruction versus Protection levels and BOOTSIZE In AT90CAN64 Product, if the Bootloader and Application protection modes are pro- grammed at level 3, the LPM instruction does not operate properly in some configuration cases. It will not load the right constant value. The differents cases versus BOOTSIZE value and Flash memory areas are detailed in following Tables : AT90CAN32/64/128 416 7679H–CAN–08/08

AT90CAN32/64/128 Let’s consider 4 sections in the Flash, described below: Table 33-1. Flash memory sections Memory Memory Memory Memory space A : space B : space C : space D : Application Application Application Bootloader Bootsize=4096 Words 0000h-2FFFh 3000h-3FFFh 4000h-6FFFh 7000h-7FFFh Bootsize=2048 Words 0000h-37FFh 3800h-3FFFh 4000h-77FFh 7800h-7FFFh Bootsize=1024 Words 0000h-3BFFh 3C00h-3FFFh 4000h-7BFFh 7C00h-7FFFh Bootsize=512 Words 0000h-3DFFh 3E00h-3FFFh 4000h-7DFFh 7E00h-7FFFh Failing cases : From memory To memeory Bug comment space space LPM instruction D B Allowed but should not be valid LPM instruction B D Allowed but should not be valid LPM instruction B A or C Not allowed but should be LPM instruction A or C B Not allowed but should be Problem fix / workaround If protection level 3 is mandatory, the LPM instruction must be moved outside the failing sections. 7. CAN acknowledge error in 3-sample mode with prescaler =1 Some acknowledge errors can occur when the clock prescaler = 1 (BRP[5..0] = 0 in CANBTR1 register) and the SMP bit is set (CANBTR3[0] = 1 in CANBTR3 register). That can result in a reduction of the maximum length of the CAN bus. Problem fix / workaround If BRP[5..0]=0 use SMP=0. 6. CAN transmission after 3-bit intermission If a Transmit Message Object (MOb) is enabled while the CAN bus is busy with an on going message, the transmitter will wait for the 3-bit intermission before starting its transmission. This is in full agreement with the CAN recommendation. If the transmitter lost arbitration against another node, two conditions can occur: - At least one receive MOb of the chip are programmed to accept the incoming message. In this case, the transmitter will wait for the next 3-bit intermission to retry its transmission. - No receive MOb of the chip are programmed to accept the incoming message. In this case the transmitter will wait for a 4-bit intermission to retry its transmission. In this case, any other CAN nodes ready to transmit after a 3-bit intermission will start transmit before the chip transmitter, even if their messages have lower priority IDs. Problem fix / workaround Always have a receive MOb enabled ready to accept any incoming messages. Thanks to the implementation of the CAN interface, a receive MOb must be enable at latest, before the 1st bit of the DLC field. The receive MOb status register is written (RXOK if message OK) immediately after the 6th bit of the End of Frame field. This will leave in CAN2.0A mode a minimum 19-bit time delay to respond to the end of message interrupt (RXOK) and re- enable the receive MOb before the start of the DLC field of the next incoming message. This 417 7679H–CAN–08/08

minimum delay will be 39-bit time in CAN2.0B. See CAN2.0A CAN2.0B frame timings below. T1 T2 CAN 2.0A 19-bit time minimum (RXOK) 15-bit CRC CdRelC. ACKAdCelK. 7 bits 3 bits SSOOFF 11-bIDit 1id0e..n0tifier RTR IDE r0 4D-bLiCt D4.L.0C CRC ACK End of Frame Inter- Arbitration Control Field Field mission Field Field T1 T2 CAN 2.0B 39-bit time minimum (RXOK) 15-bit CRC CdRelC. ACKAdCelK. 7 bits 3 bits SSOOFF 11-bitI DbaTs2e8 .i.d1e8ntifier SRR IDE 18-bit ideInDt1ifi7e.r. 0extension RTR r1 r0 4D-bLiCt D4.L.0C CRC ACK End of Frame Inter- Arbitration Control Field Field mission Field Field Workaround implementation The workaround is to have the last MOb (MOb14) as "spy" enabled all the time; it is the MOb of lowest priority. If a MOb other than MOb14 is programmed in receive mode and its accep- tance filter matches with the incoming message ID, this MOb will take the message. MOb14 will only take messages than no other MObs will have accepted. MOb14 will need to be re- enabled fast enough to manage back to back frames. The deadline to do this is the begin- ning of DLC slot of incoming frames as explained above. Minimum code to insert in CAN interrupt routine: __interrupt void can_int_handler(void) { if ((CANSIT1 & 0x40) == 0x40 ) /* MOb14 interrupt (SIT14=1) */ { CANPAGE = (0x0E << 4); /* select MOb14 */ CANSTMOB = 0x00; /* reset MOb14 status */ CANCDMOB = 0x88; /* reception enable */ } ........ ........ } 5. Asynchronous Timer-2 wakes up without interrupt The asynchronous timer can wake from sleep without giving interrupt. The error only occurs if the interrupt flag(s) is cleared by software less than 4 cycles before going to sleep and this clear is done exactly when it is supposed to be set (compare match or overflow). Only the interrupts flags are affected by the clear, not the signal witch is used to wake up the part. Problem fix / workaround No known workaround, try to lock the code to avoid such a timing. AT90CAN32/64/128 418 7679H–CAN–08/08

AT90CAN32/64/128 4. Reset of Timer-2 flags in asynchronous mode In asynchronous mode, a writing in any register of the TIMER-2 (TCCR2A, TCNT2 & OCR2A) automatically clears TOV2 and OCF2A flags in TFIR register. Problem fix / workaround – TOV2: Do not write in Timer-2 registers if TCNT2 is equal to 0xFF, 0x00 or 0x01. – OCF2A: Do not write in Timer-2 registers if TCNT2 and OCR2A differ from -1, 0 or 1. 3. Miss-functioning when code stack is in XRAM If the stack pointer (SP) targets the XRAM and if the execution of an instruction is split to serve a rising interrupt, the last operation of this instruction, executed after pushing out the return address from XRAM, may be disturbed providing wrong data to the system. Example: - the “OUT” instruction can be executed twice - the “MOV” instruction can update a register with un-predictable data. Problem fix / workaround Map the code stack in internal SRAM. 2. Extra consumption in power reduction modes When AVCC is selected as voltage reference for ADC (REF[1,0]=0,1), an extra consumption close to 30 µA (5.0V/25°C) appears in power reduction modes. Problem fix / workaround Switch from AVCC to AREF pin (REF[1,0]=0,0) before enabling one of the power reduction modes. 1. Power supply current in Power-down mode The power supply current in Power-down mode of AT90CAN128 parts with lot number before A04900 is: T = - 40°C to + 85°C A Symbol Parameter Condition Min. Typ. Max. Max. WDT enabled, V = 5 V 150 µA CC I Power Supply Current WDT disabled, VCC = 5 V 120 µA CC Power-down Mode WDT enabled, V = 3 V 50 µA CC WDT disabled, V = 3 V 40 µA CC 419 7679H–CAN–08/08

34. Datasheet Revision History for AT90CAN32/64/128 Please note that the page numbers in this section refer to this document. The revision noted in this section refer to the document revision. 34.1 Changes from 7679G - 03/08 to 7679H - 08/08 1. Minor corrections throughout the document. 34.2 Changes from 7679F - 11/07 to 7679G - 03/08 1. Added errata problem 8 on 416. 34.3 Changes from 7679E - 07/07 to 7679F - 11/07 1. Updated “Errata” on page 416. 2. Updated “Bit 0 – SMP: Sample Point(s)” on page 259 in Section“CAN Register Description” 34.4 Changes from 7679D - 02/07 to 7679E - 07/07 1. More details on CANSTMOB register. Section 19.11.1 on page 261. 2. Update to Ordering information, product marking. Section 32. on page 412. 34.5 Changes from 7679C - 01/07 to 7679D - 02/07 1. Modified DC Characteristics - Icc Active & Idle modes. Section 26.2 on page 366. 2. Removed “SPI programming timing” errata and replaced by the note in the 4th step of “SPI Serial Programming” on page 349. 3. Updated “Bit 1 – ENA/STB: Enable / Standby Mode” on page 252 in Section“CAN Reg- ister Description” 4. Updated POR characteristics in Table 7-1 on page 52. 5. Updated “Phase Correct PWM Mode” on page 153. 6. Updated SPI Features . Section 16.1 on page 168. 7. Updated “Errata” on page 416. 34.6 Changes from 7679B - 11/06 to 7679C - 01/07 1. Modified QFN64 package drawing. Section 32.2 on page 414 and Section 32. on page 412. 34.7 Changes from 7679A - 10/06 to 7679B - 11/06 1. CAN Sampling point position when the prescaler is bypassed in Section 19.4.3 ”Baud Rate” on page 242 and update of Table 19-2 on page 267. 34.8 Document Creation 1. 7679A - 10/06 AT90CAN32/64/128 420 7679H–CAN–08/08

AT90CAN32/64/128 Features.....................................................................................................1 1 Description ...............................................................................................2 1.1 Comparison Between AT90CAN32, AT90CAN64 and AT90CAN128 ................2 1.2 Part Description ..................................................................................................2 1.3 Disclaimer ...........................................................................................................3 1.4 Block Diagram ....................................................................................................4 1.5 Pin Configurations ..............................................................................................5 1.6 Pin Descriptions ..................................................................................................6 2 About Code Examples .............................................................................8 3 AVR CPU Core ..........................................................................................9 3.1 Introduction .........................................................................................................9 3.2 Architectural Overview ........................................................................................9 3.3 ALU – Arithmetic Logic Unit ..............................................................................10 3.4 Status Register .................................................................................................11 3.5 General Purpose Register File .........................................................................12 3.6 Stack Pointer ....................................................................................................14 3.7 Instruction Execution Timing .............................................................................14 3.8 Reset and Interrupt Handling ............................................................................15 4 Memories ................................................................................................18 4.1 In-System Reprogrammable Flash Program Memory ......................................18 4.2 SRAM Data Memory .........................................................................................19 4.3 EEPROM Data Memory ....................................................................................22 4.4 I/O Memory .......................................................................................................27 4.5 External Memory Interface ................................................................................27 4.6 General Purpose I/O Registers .........................................................................36 5 System Clock .........................................................................................37 5.1 Clock Systems and theirDistribution ................................................................37 5.2 Clock Sources ...................................................................................................38 5.3 Default Clock Source ........................................................................................38 5.4 Crystal Oscillator ...............................................................................................39 5.5 Low-frequency CrystalOscillator ......................................................................40 5.6 Calibrated Internal RCOscillator ......................................................................41 5.7 External Clock ...................................................................................................42 5.8 Clock Output Buffer ..........................................................................................43 421 7679H–CAN–08/08

5.9 Timer/Counter2 Oscillator .................................................................................43 5.10 System Clock Prescaler ....................................................................................44 6 Power Management and Sleep Modes .................................................46 6.1 Idle Mode ..........................................................................................................47 6.2 ADC Noise Reduction Mode .............................................................................47 6.3 Power-down Mode ............................................................................................47 6.4 Power-save Mode .............................................................................................47 6.5 Standby Mode ...................................................................................................48 6.6 Minimizing Power Consumption .......................................................................48 7 System Control and Reset ....................................................................51 7.1 Reset ................................................................................................................51 7.2 Internal Voltage Reference ...............................................................................56 7.3 Watchdog Timer ...............................................................................................57 7.4 Timed Sequences for Changing the Configuration of the Watchdog Timer .....59 8 Interrupts ................................................................................................60 8.1 Interrupt Vectors in AT90CAN32/64/128 ..........................................................60 8.2 Moving Interrupts Between Application and Boot Space ..................................64 9 I/O-Ports ..................................................................................................66 9.1 Introduction .......................................................................................................66 9.2 Ports as General Digital I/O ..............................................................................67 9.3 Alternate Port Functions ...................................................................................71 9.4 Register Description for I/O-Ports .....................................................................89 10 External Interrupts .................................................................................93 10.1 External Interrupt Register Description .............................................................93 11 Timer/Counter3/1/0 Prescalers .............................................................96 11.1 Overview ...........................................................................................................96 11.2 Timer/Counter0/1/3 Prescalers RegisterDescription .......................................98 12 8-bit Timer/Counter0 with PWM ............................................................99 12.1 Features ............................................................................................................99 12.2 Overview ...........................................................................................................99 12.3 Timer/Counter Clock Sources .........................................................................100 12.4 Counter Unit ....................................................................................................100 12.5 Output Compare Unit ......................................................................................101 12.6 Compare Match Output Unit ...........................................................................103 AT90CAN32/64/128 422 7679H–CAN–08/08

AT90CAN32/64/128 12.7 Modes of Operation ........................................................................................104 12.8 Timer/Counter Timing Diagrams .....................................................................108 12.9 8-bit Timer/Counter Register Description .......................................................109 13 16-bit Timer/Counter (Timer/Counter1 and Timer/Counter3) ...........113 13.1 Features ..........................................................................................................113 13.2 Overview .........................................................................................................113 13.3 Accessing 16-bit Registers .............................................................................116 13.4 Timer/Counter Clock Sources .........................................................................119 13.5 Counter Unit ....................................................................................................120 13.6 Input Capture Unit ...........................................................................................121 13.7 Output Compare Units ....................................................................................123 13.8 Compare Match Output Unit ...........................................................................125 13.9 Modes of Operation ........................................................................................126 13.10 Timer/Counter Timing Diagrams .....................................................................134 13.11 16-bit Timer/Counter Register Description .....................................................135 14 8-bit Timer/Counter2 with PWM and Asynchronous Operation ......145 14.1 Features ..........................................................................................................145 14.2 Overview .........................................................................................................145 14.3 Timer/Counter Clock Sources .........................................................................147 14.4 Counter Unit ....................................................................................................147 14.5 Output Compare Unit ......................................................................................148 14.6 Compare Match Output Unit ...........................................................................149 14.7 Modes of Operation ........................................................................................150 14.8 Timer/Counter Timing Diagrams .....................................................................155 14.9 8-bit Timer/Counter Register Description .......................................................157 14.10 Asynchronous operation of the Timer/Counter2 .............................................160 14.11 Timer/Counter2 Prescaler ...............................................................................163 15 Output Compare Modulator - OCM .....................................................165 15.1 Overview .........................................................................................................165 15.2 Description ......................................................................................................165 16 Serial Peripheral Interface – SPI .........................................................168 16.1 Features ..........................................................................................................168 16.2 SS Pin Functionality ........................................................................................172 16.3 Data Modes ....................................................................................................175 423 7679H–CAN–08/08

17 USART (USART0 and USART1) ..........................................................177 17.1 Features ..........................................................................................................177 17.2 Overview .........................................................................................................177 17.3 Dual USART ...................................................................................................177 17.4 Clock Generation ............................................................................................179 17.5 Serial Frame ...................................................................................................181 17.6 USART Initialization ........................................................................................182 17.7 Data Transmission – USART Transmitter ......................................................183 17.8 Data Reception – USART Receiver ................................................................186 17.9 Asynchronous Data Reception .......................................................................190 17.10 Multi-processor Communication Mode ...........................................................193 17.11 USART Register Description ..........................................................................195 17.12 Examples of Baud Rate Setting ......................................................................200 18 Two-wire Serial Interface .....................................................................204 18.1 Features ..........................................................................................................204 18.2 Two-wire Serial Interface Bus Definition .........................................................204 18.3 Data Transfer and Frame Format ...................................................................205 18.4 Multi-master Bus Systems, Arbitration and Synchronization ..........................207 18.5 Overview of the TWI Module ..........................................................................209 18.6 TWI Register Description ................................................................................212 18.7 Using the TWI .................................................................................................215 18.8 Transmission Modes .......................................................................................218 18.9 Multi-master Systems and Arbitration .............................................................232 19 Controller Area Network - CAN ...........................................................234 19.1 Features ..........................................................................................................234 19.2 CAN Protocol ..................................................................................................234 19.3 CAN Controller ................................................................................................240 19.4 CAN Channel ..................................................................................................241 19.5 Message Objects ............................................................................................243 19.6 CAN Timer ......................................................................................................247 19.7 Error Management ..........................................................................................248 19.8 Interrupts .........................................................................................................249 19.9 CAN Register Description ...............................................................................251 19.10 General CAN Registers ..................................................................................252 19.11 MOb Registers ................................................................................................261 AT90CAN32/64/128 424 7679H–CAN–08/08

AT90CAN32/64/128 19.12 Examples of CAN BaudRate Setting .............................................................266 20 Analog Comparator .............................................................................269 20.1 Overview .........................................................................................................269 20.2 Analog Comparator Register Description .......................................................269 20.3 Analog Comparator Multiplexed Input ............................................................271 21 Analog to Digital Converter - ADC .....................................................273 21.1 Features ..........................................................................................................273 21.2 Operation ........................................................................................................274 21.3 Starting a Conversion .....................................................................................275 21.4 Prescaling and Conversion Timing .................................................................276 21.5 Changing Channel or Reference Selection ....................................................279 21.6 ADC Noise Canceler .......................................................................................280 21.7 ADC Conversion Result ..................................................................................284 21.8 ADC Register Description ...............................................................................287 22 JTAG Interface and On-chip Debug System .....................................293 22.1 Features ..........................................................................................................293 22.2 Overview .........................................................................................................293 22.3 Test Access Port – TAP ..................................................................................293 22.4 TAP Controller ................................................................................................296 22.5 Using the Boundary-scan Chain .....................................................................297 22.6 Using the On-chip Debug System ..................................................................297 22.7 On-chip Debug Specific JTAG Instructions ....................................................298 22.8 On-chip Debug Related Register in I/O Memory ............................................299 22.9 Using the JTAG Programming Capabilities ....................................................299 22.10 Bibliography ....................................................................................................299 23 Boundary-scan IEEE 1149.1 (JTAG) ...................................................300 23.1 Features ..........................................................................................................300 23.2 System Overview ............................................................................................300 23.3 Data Registers ................................................................................................300 23.4 Boundary-scan Specific JTAG Instructions ....................................................302 23.5 Boundary-scan Related Register in I/O Memory ............................................304 23.6 Boundary-scan Chain .....................................................................................304 23.7 AT90CAN32/64/128 Boundary-scan Order ....................................................314 23.8 Boundary-scan Description Language Files ...................................................320 425 7679H–CAN–08/08

24 Boot Loader Support – Read-While-Write Self-Programming .........321 24.1 Features ..........................................................................................................321 24.2 Application and Boot Loader Flash Sections ..................................................321 24.3 Read-While-Write and No Read-While-Write Flash Sections .........................321 24.4 Boot Loader Lock Bits .....................................................................................324 24.5 Entering the Boot Loader Program .................................................................325 24.6 Addressing the Flash During Self-Programming ............................................327 24.7 Self-Programming the Flash ...........................................................................328 25 Memory Programming .........................................................................336 25.1 Program and Data Memory Lock Bits .............................................................336 25.2 Fuse Bits .........................................................................................................337 25.3 Signature Bytes ..............................................................................................339 25.4 Calibration Byte ..............................................................................................339 25.5 Parallel Programming Overview .....................................................................339 25.6 Parallel Programming .....................................................................................342 25.7 SPI Serial Programming Overview .................................................................348 25.8 SPI Serial Programming .................................................................................349 25.9 JTAG Programming Overview ........................................................................352 26 Electrical Characteristics (1) ...............................................................................................365 26.1 Absolute Maximum Ratings* ...........................................................................365 26.2 DC Characteristics ..........................................................................................366 26.3 External Clock Drive Characteristics ..............................................................367 26.4 Maximum Speed vs. VCC ...............................................................................368 26.5 Two-wire Serial Interface Characteristics .......................................................369 26.6 SPI Timing Characteristics .............................................................................370 26.7 CAN Physical Layer Characteristics ...............................................................372 26.8 ADC Characteristics .......................................................................................373 26.9 External Data Memory Characteristics ...........................................................375 26.10 Parallel Programming Characteristics ............................................................380 27 Decoupling Capacitors ........................................................................383 28 AT90CAN32/64/128 Typical Characteristics ......................................384 28.1 Active Supply Current .....................................................................................384 28.2 Idle Supply Current .........................................................................................387 28.3 Power-down Supply Current ...........................................................................389 28.4 Power-save Supply Current ............................................................................390 AT90CAN32/64/128 426 7679H–CAN–08/08

AT90CAN32/64/128 28.5 Standby Supply Current ..................................................................................391 28.6 Pin Pull-up ......................................................................................................391 28.7 Pin Driver Strength .........................................................................................393 28.8 Pin Thresholds and Hysteresis .......................................................................395 28.9 BOD Thresholds and Analog Comparator Offset ...........................................397 28.10 Internal Oscillator Speed ................................................................................399 28.11 Current Consumption of Peripheral Units .......................................................401 28.12 Current Consumption in Reset and ResetPulseWidth ..................................403 29 Register Summary ...............................................................................405 30 Instruction Set Summary ....................................................................409 31 Ordering Information ...........................................................................412 32 Packaging Information ........................................................................412 32.1 TQFP64 ..........................................................................................................413 32.2 QFN64 ............................................................................................................414 33 Errata .....................................................................................................416 33.1 Errata Summary ..............................................................................................416 33.2 Errata Description ...........................................................................................416 34 Datasheet Revision History for AT90CAN32/64/128 .........................420 34.1 Changes from 7679G - 03/08 to 7679H - 08/08 .............................................420 34.2 Changes from 7679F - 11/07 to 7679G - 03/08 ..............................................420 34.3 Changes from 7679E - 07/07 to 7679F - 11/07 ..............................................420 34.4 Changes from 7679D - 02/07 to 7679E - 07/07 ..............................................420 34.5 Changes from 7679C - 01/07 to 7679D - 02/07 ..............................................420 34.6 Changes from 7679B - 11/06 to 7679C - 01/07 ..............................................420 34.7 Changes from 7679A - 10/06 to 7679B - 11/06 ..............................................420 34.8 Document Creation .........................................................................................420 427 7679H–CAN–08/08

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